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product data sheet industrial sata ssd 2.5 x - 50 0 series sata ii, high performance, high reliability s lc nand flash b u: fl a sh p ro du ct s date : oc to be r 1 0 , 2 01 3 r e vi si o n: 1 .0 2 fi le : x - 5 00 _ da ta_ s he e t_ sa - q x bj_ r e v 1 0 2 .d oc
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 2 of 53 x - 5 00 series - industrial sata solid state drive 2.5 16 gb to 512 gb based on slc nand flash 1 feature summary ? form factor: o 2.5 - inch sata solid state drive (ssd) o 100 mm x 70mm x 9. 2 mm o 7+1 5 pin (sata+power) locking/latching sata connector ? interface: o sat a rev 2.6 - 3gbit/s (1.5gbit/s compatible) ? feature connector for o q uick erase and write protect input o d evice activity and quick erase output (led) o ground pin ? optional various secure erase /sanitize/purge methods (hardware and software trigge red) ? highly - integrated memory controller o m ax. udma6 supported o m ax. pio mode 4, mdma2 supported o slc nand flash o hardware bch - code ecc ( up to 40 bit correction per 2 sector s ) o f ix drive configuration ? low - power cmos technology ? 5.0 v 10 % power supply ? low power , less than 1w (idle ) / 3.5 w ( operation) / 0.7w slumber average current ? no mechanical noise ? wear leveling: active wear leveling of static and dynamic data the wear leveling assures that dynamic data as well as static data is balanced evenly across the mem ory. with that the maximum write endurance of the device is guaranteed. ? m echanical robustness (mil - std810) ? high reliability o best available slc nand flash technology o data r etention 10 years o staticdatarefresh and earlyretirement technologies for data refresh o mtbf 2,0 00,000 hours o number of connector insertions/removals: >1,000 cycles ? high performance o up to 300mb/s burst transfer rate in sata ii - 3.0gb/sec o sustained read / write performance: up to 240mb/s / 200mb/s o 4kb read / write iops : up to 14500 / 7000 o access time <0.2ms o trim and ncq support ? available densities o 16 gb up to 512 gb (slc) ? s.m.a.r.t. with extended information ? hpa, s ecurity feature set, 48bit feature set ? i nternal temperature sensor (current, minimum, maximum) ? operation systems: microsoft windows8, 7 , vista, xp (all 32/64bit), linux, apple macos x, embedded versions, rtos ? firmware update possible ? 2 o perating t emperature ranges o commercial temperature range 0 +70c o industrial temperature range - 40 +85c ? life cycle management ? controlled bom ? rohs, china - rohs, reach compatible , weee , ce, fcc compliant
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 3 of 53 2 contents 1 feature summary ................................ ................................ ................................ ................................ ................................ ... 2 2 content s ................................ ................................ ................................ ................................ ................................ .................. 3 3 order information ................................ ................................ ................................ ................................ ............................... 5 3.1 c urrent standard part numbers , commercial temperatu re grade ................................ ................................ ......................... 5 3.2 c urrent standard part numbers , industrial temperatu re grade ................................ ................................ .......................... 5 3.3 g eneral standard part numbers ................................ ................................ ................................ ................................ ........ 5 3.4 o ffered oem options ................................ ................................ ................................ ................................ ........................ 5 4 product specificat ion ................................ ................................ ................................ ................................ ........................... 6 4.1 p hysical description ................................ ................................ ................................ ................................ .......................... 6 4.2 s ystem p erformance ................................ ................................ ................................ ................................ ......................... 7 4.3 e nvironmental s pecifications ................................ ................................ ................................ ................................ ............ 8 4.4 p hysical d imensions ................................ ................................ ................................ ................................ ......................... 8 4.5 r eliability ................................ ................................ ................................ ................................ ................................ ........ 8 4.6 e ndurance (jesd219a) ................................ ................................ ................................ ................................ ..................... 9 4.7 d rive geometry / chs parameter ................................ ................................ ................................ ................................ ........ 9 4.8 t emperature sensor ................................ ................................ ................................ ................................ .......................... 9 5 electrical interfa ce ................................ ................................ ................................ ................................ ............................ 10 5.1 sata and p ower c onnector description ................................ ................................ ................................ ............................ 10 5.2 f eature connector ................................ ................................ ................................ ................................ .......................... 11 5.3 e lectrical s pecification ................................ ................................ ................................ ................................ ................... 12 6 ata command descri ption ................................ ................................ ................................ ................................ .................. 13 6.1 c heck p ower m ode (98 h or e5 h ) ................................ ................................ ................................ ................................ .... 15 6.2 e xecute d rive d iagnostic (90 h ) ................................ ................................ ................................ ................................ ....... 15 6.3 f lush c ache (e7 h ) ................................ ................................ ................................ ................................ ........................... 15 6.4 f lush c ache e xt (ea h ) 48 bit lba ................................ ................................ ................................ ................................ .... 16 6.5 i de ntify d evice (ec h ) ................................ ................................ ................................ ................................ ...................... 16 6.6 i dle (97 h or e3 h ) ................................ ................................ ................................ ................................ ........................... 23 6.7 i dle i mmediate (95 h or e1 h ) ................................ ................................ ................................ ................................ ............ 23 6.8 nop (00 h ) ................................ ................................ ................................ ................................ ................................ .... 24 6.9 r ead b uffer (e4 h ) ................................ ................................ ................................ ................................ ......................... 24 6.10 r ead dma (c8 h ) ................................ ................................ ................................ ................................ ........................... 24 6.11 r ead dma e xt (25 h ) 48 bit lba ................................ ................................ ................................ ................................ ...... 25 6.12 r ead fpdma q ueued (60 h ) ( if ncq feature set supporte d ) ................................ ................................ ............................ 25 6.13 r ead m ultiple (c4 h ) ................................ ................................ ................................ ................................ ...................... 25 6.14 r ead m ultiple e xt (29 h ) 48 bit lba ................................ ................................ ................................ ............................... 26 6.15 r ead n ative max address (f8 h ) ................................ ................................ ................................ ................................ ...... 27 6.16 r ead n ative max address e xt (27 h ) ................................ ................................ ................................ ................................ 27 6.17 r ead s ector ( s ) (20 h ) ................................ ................................ ................................ ................................ ..................... 27 6.18 r ead s ectors e xt (24 h ) 48 bit lba ................................ ................................ ................................ ................................ . 28 6.19 r ead v erify s ector ( s ) (40 h or 41 h ) ................................ ................................ ................................ ............................... 28 6.20 r ead v erify e xt (42 h ) 48 bit lba ................................ ................................ ................................ ................................ ... 28 6.21 s ecurity d isable p assword (f6 h ) ................................ ................................ ................................ ................................ ... 29 6.22 s ecurity e rase p repare (f3 h ) ................................ ................................ ................................ ................................ ........ 29 6.23 s ecurity e rase u nit (f4 h ) ................................ ................................ ................................ ................................ .............. 30 6.24 s ecurity f reeze l ock (f5 h ) ................................ ................................ ................................ ................................ ............ 30 6.25 s ecurity s et p assword (f1 h ) ................................ ................................ ................................ ................................ .......... 30 6.26 s ecurity u nlock (f2 h ) ................................ ................................ ................................ ................................ ................... 31 6.27 s et f eatures (ef h ) ................................ ................................ ................................ ................................ ........................ 32 6.28 s et max address (f9 h ) ................................ ................................ ................................ ................................ .................. 33 6.29 s et max address e xt (37 h ) 48 bit lba ................................ ................................ ................................ ............................. 34 6.30 s et m ultiple m ode (c6 h ) ................................ ................................ ................................ ................................ .............. 35 6 .31 s leep (99 h or e6) ................................ ................................ ................................ ................................ ......................... 35 6.32 s.m.a.r.t. (b0 h ) ................................ ................................ ................................ ................................ ........................ 36 6.33 s tandby (96 h or e2) ................................ ................................ ................................ ................................ ..................... 36 6.34 s tandby i mmediate (94 h or e0 h ) ................................ ................................ ................................ ................................ .. 36
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 4 of 53 6.35 w rite b uffer (e8 h ) ................................ ................................ ................................ ................................ ...................... 36 6.36 w rite dma (ca h ) ................................ ................................ ................................ ................................ ......................... 37 6.37 w rite dma e xt (35 h ) 48 bit lba ................................ ................................ ................................ ................................ ... 37 6.38 w rite dma fua e xt (3d h ) 48 bit lba ................................ ................................ ................................ ........................... 38 6.39 w ri te fpdma q ueued (61 h ) ( if ncq feature set supporte d ) ................................ ................................ ........................... 38 6.40 w rite m ultiple c ommand (c5 h ) ................................ ................................ ................................ ................................ .... 38 6.41 w rite m ultiple e xt (39 h ) 48 bit lba ................................ ................................ ................................ .............................. 39 6.42 w rite m ultiple fua e xt (ce h ) 48 bit lba ................................ ................................ ................................ ...................... 39 6.43 w rite s ector ( s ) (30 h ) ................................ ................................ ................................ ................................ ................... 39 6.44 w rite s ector ( s ) e xt (34 h ) 48 bit lba ................................ ................................ ................................ ............................. 40 7 s.m.a.r.t. functio nality ................................ ................................ ................................ ................................ ..................... 41 7.1 s.m.a.r.t. e nable / d isable o perations ................................ ................................ ................................ ........................... 41 7.2 s.m.a.r.t. r eturn s tatus ................................ ................................ ................................ ................................ ............... 41 7.3 s.m.a.r.t. e nable / d isable a ttribute a utosave ................................ ................................ ................................ .............. 42 7.4 s.m.a.r.t. s ave a ttribute v alues ................................ ................................ ................................ ................................ ... 42 7.5 s.m.a.r.t. e xecute off - line i mmediate ................................ ................................ ................................ ........................ 42 7.6 s.m. a.r.t. r ead data ................................ ................................ ................................ ................................ ..................... 42 8 package mechanical ................................ ................................ ................................ ................................ ........................... 45 9 ce declaration o f conformity ................................ ................................ ................................ ................................ ........ 47 10 rohs and weee upd ate from swissbit ................................ ................................ ................................ ........................... 48 11 part number decod er ................................ ................................ ................................ ................................ ........................ 50 11.1 m anufacturer ................................ ................................ ................................ ................................ ................................ 50 11.2 m emory t ype ................................ ................................ ................................ ................................ ................................ .. 50 11.3 p roduct t ype ................................ ................................ ................................ ................................ ................................ .. 50 11.4 d ensity ................................ ................................ ................................ ................................ ................................ .......... 50 11.5 p latform ................................ ................................ ................................ ................................ ................................ ....... 50 11.6 p roduct g eneration ................................ ................................ ................................ ................................ ....................... 50 11.7 m emory o rganization ................................ ................................ ................................ ................................ ..................... 50 11.8 t echnology ................................ ................................ ................................ ................................ ................................ .... 50 11.9 n umber of f lash c hip ................................ ................................ ................................ ................................ .................... 50 11.10 f lash c ode ................................ ................................ ................................ ................................ ................................ ... 50 11.11 t emp . o ption ................................ ................................ ................................ ................................ ................................ . 51 11.12 die c lassification ................................ ................................ ................................ ................................ .......................... 51 11.13 pin m ode ................................ ................................ ................................ ................................ ................................ ..... 51 11.14 d rive configuration xyz ................................ ................................ ................................ ................................ ............... 51 11.15 o ption ................................ ................................ ................................ ................................ ................................ .......... 51 12 swissbit x - 500 ssd marking specification ................................ ................................ ................................ .................... 52 12.1 t op view ................................ ................................ ................................ ................................ ................................ ......... 52 13 revision history ................................ ................................ ................................ ................................ ................................ . 53
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 5 of 53 3 order information the x - 500 series par t numbers are listed below for different temperature range s . 3.1 current standard part numbers, commercial temperature grade fix / sata ii/ udma6, mdma2, pio4 , commercial density part number 16gb sfsa 0 16gq1bj8to - c - dt - 2 2 6 - std 32gb sfsa 0 32gq1bjato - c - dt - 2 2 6 - std 64gb sfsa064g q1bjato - c - qt - 2 2 6 - std 128gb sfsa128gq1bj8to - c - nu - 2 2 6 - std 256gb sfsa256gq1bjato - c - nu - 2 2 6 - std 512gb sfsa512gq1bjato - c - nc - 226 - std table 1 : commercial temperature product list 3.2 current standard part numbers, industrial temperature grade fix / sata ii/ udma6 , mdma2 , pio4 , industrial density part number 16gb sfsa 016g q1bj8to - i - dt - 2 2 6 - std 32gb sfsa032g q1bjato - i - dt - 2 2 6 - std 64gb sfsa 0 64gq1bjato - i - qt - 2 2 6 - std 128gb sfsa128gq1bj8to - i - nu - 2 2 6 - std 256gb sfsa256gq1bjato - i - nu - 2 2 6 - std 512gb sfsa512gq1bjato - i - nc - 226 - std table 2 : industrial temperature product list 3.3 general s tandard part numbers fix / sata ii/ udma6, mdma2, pio4 density part number 16gb sfsa 0 16gqxb j 8 to - t - d t - 2y6 - ccc 32gb sfsa 0 32gqxbja to - t - dt - 2y6 - ccc 64gb sfsa 0 64gqxbja to - t - qt - 2y6 - ccc 128gb sfsa128gqxb j8to - t - nu - 2y6 - ccc 256gb sfsa256gqxbjato - t - nu - 2y6 - ccc 512gb sfsa512gqxbjato - t - nc - 2y6 - ccc table 3 : commercial temperature product list x= depends on product generation , y= depends on firmware generation , t= c for commercial temperature; i for industrial temperature ccc=std for standard ssds; stc for conformal coated ssds 3.4 offered oem options ? customer specified drive size and drive geometry (c/h/s C cylinder/head/sector) ? customer specified drive id (strings) ? preload service (also drive images with any file system) ? conformal coat ing (part number suffix C stc) ? erase input at feature connector ? various enhanced secure erase / sanitize / purge algorithms hardware and software - dod5220.22 - m - nsa (manual 130 - 2) - usa af affssi 5020 - usa army 380 - 19 - usa navy navso p - 5239 - 26 - irec (irig) 106 - nsa 9 - 12 ? 3.3v optional on request ?
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 6 of 53 4 product specification the solid state drive (ssd) is a small form factor (2.5) non - volatile m emory drive which provides high capacity data storage. it has a standard combined connector with sata and power/control part. the ssd works at a supply voltage of 5 v. the drive with the sata interface operates in mode 2.0 (1.5 or 3.0 gb/s burst) . the drive has an internal intelligent controller that manages interface protocols, data storage and retrieval as well as hardware bch - code error correction code (ecc) , defect handling, diagnostics and clock control . the wear leveling mechanism assures an equal usa ge of the flash memory cells to extend the life time. the hardware bch - code ecc allows to detect and correct up to 40 r andom bits per 1024 data bytes . the ssd has early w eak b lock r etirement d etection and data shaping for higher data reliability. the drive has a voltage detector and a powerful power - loss management feature to prevent data corruption after power - down. the ssd has hardware and software write protection, and hardware and software security erase function with different military erase algorithms . the specification has been realized and approved by the ata/atapi - 8 specification . the system highlights are shown in table 4 table 12 . related documentation ? serial tr ansport protocols and physical interconnect (ata/atapi - 8 ) ? at attachment interface document, american national standards institute, x3.221 - 1994 4.1 physical description the ssd contains a flash controller and flash memory modules. the controller interfaces with a host system allowing data to be written to and read from the flash memory modules. the ssd is offered in a 2.5 size package with a standard sata connector . the ssd has 4 screw holes at the side and 4 at the bottom side. figure 5 and figure 6 (page 45 ) show ssd dimensions and connector location.
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 7 of 53 4.2 system performance table 4 : system performance (measured) system performance typ. unit data transfer rate (sata burst (1.5 or 3.0gb/s)) 150 or 300 mb/s sequential read 16gb 226 mb/s 32gb 228 64gb 228 128gb 247 256gb 246 512 gb 236 sequential write 16gb 142 32gb 162 64gb 163 128gb 189 256gb 189 512 gb 220 random read 4 kb 16gb 14150 iops 32gb 14400 64gb 14400 128gb 14300 256gb 14300 512 gb 1 43 00 random write 4kb 16gb 4900 32gb 5300 64gb 5300 128gb 3800 256gb 3800 512gb 3800 all values refer to toshiba flash chips (see part number) with sata 3.0gbit/s . sustained speed depends on flash type and number , file /cluster size, and burst speed . mb/s = 1,000,000 byte/s . measured with crystaldiskmark 3.0.2 on windows 7, ntfs, 5x500mb , qd=32 .
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 8 of 53 4.3 environmental specifications 4.3.1 recommended operating conditio ns table 5 : recommended operating conditions parameter value commercial operating temperature 0c to 70c industrial operating temperature - 40c to 85c power supply vcc voltage 4.5v to 5.5v *) *) ssd reset below 4.2v table 6 : current consumption @5v * ) current consumption (ma) typ/max partial/ slumber idle mode read write qerase sanitize unit 16gb 100/120 155/170 270/300 330/400 270 395 ma 32gb 100/120 155/170 270/300 3 7 0/4 2 0 440 510 64gb 100/120 15 5/170 310/360 380/450 680 530 128gb 120/140 175/190 370/410 420/480 680 530 256gb 120/140 165/190 370/410 470/550 680 580 512gb 120/140 175/190 350/390 4 2 0/480 6 20 960 *) all values are typical at 25 c and nominal supply voltage and refer to satai i sequential performance test random pattern. due to simultaneous flash erase operations current bursts of up to 2000ma can occur for a few milliseconds. the voltage at the connector must be kept always above 4.2v. otherwise the ssd performs a reset. 4.3.2 recom mended storage conditions table 7 : recommended storage conditions parameter value commercial storage temperature - 5 5 c to 95 c *) industrial storage temperature - 5 5 c to 95 c *) *) storage temperatures above 40c can reduce the data retention 4.3.3 shock, vibration, and humidity table 8 : shock, vibration, and humidity parameter value humidity (non - condensing) 85% rh 85c, 1000 hrs (jedec jesd22, method a101 - b) vibration mil - std810; 20g, 10 - 2000hz random shoc k mil - std810; 2000g, 0.4ms; 50g 11ms 4.4 physical dimensions table 9 : physical dimensions physical dimensions unit length 100.1 0.2 mm width 69.850.2 thickness 9.20.2 weight (typ.) 8 0 g 4.5 reliability table 10 : system reliability and maintenance parameter value mtbf (at 25c)
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 9 of 53 4.6 endurance (jesd219a) table 11 : measured endurance values (tbyte written, jesd 219a specification) density (gb) 16 3 2 6 4 12 8 2 56 512 cl ient workload (tbw) ( ~ 500) ( ~ 1000) 2700 3700 7100 1 1 000 enterprise workload (tbw) 90 1 70 370 530 1070 ( ~ 1800) video streaming workload (tbw) ~ 1500 ~ 3000 ~ 6000 ~ 12000 ~ 24000 ~4800 0 jesd219a standard defines workloads for the endurance rating and enduranc e verification of ssd application classes. these workloads shall be used in conjunction with the solid state drive (ssd) requirements and endurance test method standard, jesd218. the tbw values are estimations, how many data can be written in the applicati ons, until the number of program erase cycles of the flash cells are reached. ( 16gb and 32gb client workload is not specified in jesd219a. 512gb values are estimated. ) the video streaming workload is a mainly sequential write application. 4.7 drive geometry / chs parameter table 12 : ssd density specification (slc flash) density default cylinders default heads default sectors sectors drive total addressable bytes remark 16gb 16 383*) 16 63 31 277 056 16 013 852 672 32gb 16 383*) 16 63 62 586 880 32 044 482 560 64gb 16 383*) 16 63 125'313'024 64160268288 128 gb 16 383*) 16 63 250'626'048 128320536576 256 gb 16 383*) 16 63 500118192 256'060'514'304 idema value 512 gb 16 383*) 16 63 1'000'215'216 512'110'190'592 idema value * ) the chs access is limited to about 8gb . above 8gb, the drive must be addressed in lba mode. 4.8 temperature sensor the ssd has an internal temperature sensor. the current temperature, minimum value, maximum value can be read out from s . m . a . r . t . information ( raw values of attribute id 194).
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 10 of 53 5 electrical interface 5.1 sata and power connector description the ssd is connected with a standard 7 pin sata connector and a standard 15 pin sata power connector. the signal/pin assignments and descriptions are listed in table 13 figure 1 : sata and power connector the signal/pin assignments and descriptions are listed in table 13 . table 13 : pin assignment , name , and description pin signal name description s1 ground signal ground s2 a+ + differential receive signal s3 a - - differential receive signal s4 ground signal ground s5 b - - differential transmit signal s6 b+ + differential tra nsmit signal s7 ground signal ground p1p3 3.3v 3.3v power ( not used, optional on request) p4p6 ground power ground p 7 p9 5v 5v power p10 ground power ground p11 device activity device activity, active low *) p12 ground power ground p13p15 12 v 12v power (not used) *) driven low, no internal pull up resistor connected
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 11 of 53 5.2 feature connector figure 2 : ssd connector side with power, sata and feature connector the x - 500 ssd has a 5 - circuit feature connector beside the s ata connector for the extra function ? write protect ? hardware erase triggering as well as for operation signalization ? device activity ? erase activity this feature connector mates e.g. with the molex connector (p art number 501330 - 0500 ) with 5 wire to bo ard terminals (part number 501334 - 0100 ) figure 3 : feature connector at ssd mating cab le connector wire to board terminal pin function usage 1 write protect input ground this pin for write protection 2 ground system level ground for 0 volt reference level 3 device activity output connect an led to ground (serial resistor depending on color) led is on at device activity by sata access 4 erase trigger input if this pin is grounded for at least 0 .8sec enhanced erase starts 5 erase activity output connect an led to ground (serial resistor depending on color) led blinks, if erase is in progress e rase (algorithm optional) can also be started with security erase unit command (0xf1, 0xf3, 0xf4 c ommand sequence)
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 12 of 53 5.3 electrical specification 5.3.1 power supply the standard ssd is supplied with 5v. ( optional 3.3v supply is possible on request. ) table 14 and table 15 define t he dc characteristics of the ssd . unless otherwise stated, conditions are: ? vcc = 5.0 v 10 % ? 0 c to + 70 c the current is measured by connecting an amp meter in series with the v cc supply. the meter should be set to the 2a scale range, and have a fast curren t probe with an rc filter with a time constant of 0.1ms. current measurements are taken while looping on a data transfer command with a sector count of 128. current consumption values for both read and write commands are not to exceed the maximum average r ms current specified in table 15 . table 14 : absolute maximum conditions parameter symbol conditions input power (5v pins) vcc - 0.3v to 6.5 v min operating voltage for operation (5v pins) v cc 4.5 v the power supply must guarantee a voltage of 4.2v. below this voltage, the ssd performs a hardware reset. table 15 : input power write and read mode maximum average rms current conditions sata ii (3.0gb/s) 500 ma *) 5v sa ta i (1.5gb/s) 400 ma *) idle 1 90 ma *) the ssd needs current peaks of > 1a during some milliseconds. 5.3.2 feature connector figure 4 : suggested circuit for feature connector led outputs ? pin3 device activity ? pin5 erase activity d riven high (3.3v , active ) and low (gnd , idle ) 13ma short current led can be connected directly to these pins to gnd (pin2) i nputs ? pin1 - write protect ? pin5 - erase trigger (if option supported) these pins are low active 0.4ma short current switches can be connected directly to these pins to gnd (pin2)
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 13 of 53 6 ata command description this section provides information on the ata commands supported by the ssd . the commands are issued to the ata by loading the required registers in the command block with the supp lied parameter, and then writing the command code to the register. ata command flow ddmai0: dma_in state this state is activated when the device receives a dma data - in command or the transmission of one or more data fis is required to complete the command . when in this state, the device shall prepare the data for transfer of a data fis to the host. transition ddmai0:1 when the device has the data ready to transfer a data fis, the device shall transition to the ddmai1: send_data state. transition ddmai0:2 when the device has transferred all of the data requested by this command or has encountered an error that causes the command to abort before completing the transfer of the requested data, then the device shall transition to the ddmai2: send_status state. ddmai1: send_data this state is activated when the device has the data ready to transfer a data fis to the host. when in this state, the device shall request that the transport layer transmit a data fis containing the data. the device command layer shall request a data fis size of no more than 2,048 dwords (8kb). transition ddmai1:1 when the data fis has been transferred, the device shall transition to the dmaoi0: dma_in state. ddmai2: send_status this state is activated when the device has transferred a ll of the data requested by the command or has encountered an error that causes the command to abort before completing the transfer of the requested data. when in this state, the device shall request that the transport layer transmit a register fis with th e register content as described in the command description in the ata/atapi - 6 standard and the i bit set to one. transition ddmai2:1 when the fis has been transmitted, the device shall transition to the di0: device_idle state.
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 14 of 53 for reasons of backward co mpatibility some commands are implemented as no operation nop. table 16 summarizes the drive command set with the paragraphs that follow describing the individual commands and the task file for each. table 16 : ata command set (1) command code fr sc sn cy dh lba check power mode e5h or 98h d execute drive diagnostic 90h d flush cache e7h d flush cache ext eah d identify drive ech d idle e3h or 97h y d idle immediate e1h or 95h d nop 00h d read buffer e4h d read dma c8 h y y y y y read dma ext 25h yy d yy read fpdma queued 60h y y y y d y read multiple c4h y y y y y read multiple ext 29h yy d yy read native max address f8h d read native max address ext 27h d read sector(s) 20h y y y y y read sector(s) ext 2) 24h yy yy yy d yy read verify sector(s) 40h or 41h y y y y y read verify sector(s) ext 42h yy yy yy d yy security disable password f6h d security erase prepare f3h d security erase unit f4h d security freeze lock f5h d security set password f1h d security unlock f2h d set features efh y d set max address (with set password) f9h y y y y y set max address ext 37h yy yy yy d yy set multiple mode c6h y d sleep e6h or 99h d s.m.a.r.t. b0h y y y d stand b y e2h or 96h d stand b y immediate e0h or 94h d write buffer e8h d write dma ca h y y y y y write dma ext 35h yy yy yy d yy write dma fua ext 3 d h yy yy yy d yy write fpdma queued 61h y y y d y write multiple c5h y y y y y write multiple ext 39h yy yy yy d yy write multiple fua ext ceh yy yy yy d yy write sector(s) 30h y y y y y write sector(s) ext 34h yy yy yy d yy 1. fr = f eatures register, sc = sector count register, sn = sector number register, cy = cylinder registers, dh = drive/head register, lba = logical block address mode supported (see command descriptions for use), y C the register contains a valid parameter for t his command. for the drive/head register y means both the drive and head parameters are used. yy C registers must be written twice for 48bit lba commands d C only the drive parameter is valid and not the head parameter c C the register contains command spe cific data (see command descriptors for use). 2. to read out the higher and lower byte of the 16bit registers bit7 of the device control register (write to alternate status r egister) must be set to 1 or 0, respectively. for details look at the sata - 8 specific ation e.g. draft here: http://www.t13.org/documents/uploadeddocuments/docs2007/d1699r4a - ata8 - acs.pdf
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 15 of 53 6.1 check power mode (98h or e5h) this command checks the power mode. issuing the command while the drive is in standby mode, is about to enter standby, or is exiting standby, the command will set bsy, set the sector count register to 00h, clear bsy and generate an interrupt. issuing the command when the drive is in i dle mode will set bsy, set the sector count register to ffh, clear bsy and generate an interrupt. table 17 defines the b yte sequence of the check power mode command. table 17 : check power m ode task file register 7 6 5 4 3 2 1 0 command 98h or e5h drive/head nu nu nu d nu cylinder hi nu cylinder low nu sector num nu sector count nu features nu 6.2 execute drive diagnostic (90h) this command performs the internal diagnostic tests implement ed by the drive . the drive bit is ignored and the diagnostic command is executed by both the master and the slave with the master responding with the status for both devices. table 18 defines the execute drive diag nostic command byte sequence. the diagnostic codes shown in table 19 are returned in the error register at the end of the command. table 18 : execute drive diagnostic task file register 7 6 5 4 3 2 1 0 command 90h drive/head nu nu nu d nu cylinder hi nu cylinder low nu sector num nu sector count nu features nu table 19 : diagnostic codes code error type 01h no error detected 02h formatter device error 03h s ector buffer error 04h ecc circuitry error 05h controlling microprocessor error 6.3 flush cache (e7h) this command causes the drive to complete writing data from its cache. the drive returns status with rdy=1 and dsc=1 after the data in the write cache buff er is written to the media. if the drive does not support the flush cache command, the drive shall return command aborted. table 20 : flush cache task file register 7 6 5 4 3 2 1 0 command e7h drive/head nu nu nu d nu cylinder hi nu cylinder low nu sector num nu sector count nu features nu
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 16 of 53 6.4 flush cache ext (eah) 48bit lba this command causes the ssd to complete writing data from its volatile cache into non - volatile memory. the bsy bit shall remain set to one until all data has been successfully written or an error occurs. the ssd returns status with rdy=1 and dsc=1 after the data in the write cache buffer is written to the media. if the ssd does not support the flush cache ext command, the ssd shall return command aborted. see table 21 for the data set management command inputs. table 21 : flush cache ext register write previous current task file register 15:8 7 6 5 4 3 2 1 0 command - eah drive/head - 1 1 1 drive reserved lba high nu nu lba mid nu nu lba low nu nu sector count nu nu features nu nu an unrecoverable error encountered while writing data results in aborting the command and the command block registers contain the 48 C bit sector address of th e sector where the first unrecoverable error occurred. subsequent flush cache ext commands continue the process of flushing the cache starting with the first sector after the sector in error. this command is used by the host to request the device to flush the write cache. if there is data in the write cache, that data shall be written to the media. the bsy bit shall remain set to one until all data has been successfully written or an error occurs. 6.5 identify device (ech) the identify device command enables th e host to receive parameter information from the drive . this command has the same protocol as the read sector(s) command. table 22 defines the identify device command byte sequence. all reserved bits or words are z ero. shows the definition of each field in the identify drive information. table 22 : identify d evice task file register 7 6 5 4 3 2 1 0 command ech drive/head nu nu nu d nu cylinder hi nu cylinder low nu sector num nu sector count nu features nu
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 17 of 53 table 23 : identify d evice information word address default value total bytes data field type information 0 0 040 h* 2 standard configuration fix 1 3fff h 2 default number of cylinders (obsolete) 2 c837h* 2 sp ecific configuration 3 00 10 h * 2 default number of heads (obsolete) 4 0000h * 2 (retired) 5 0240 h * 2 (retired) 6 003f h 2 default number of sectors per track (obsolete) 7 - 8 0000 h 4 reserved for compactflash 9 0000h 2 (retired) 10 - 19 aaaa 20 serial numb er in ascii (right justified) 20 0000 h 2 (retired) 21 000 0 h 2 (retired) 22 000 4 h * 2 (obsolete) 23 - 26 yyyy * 8 firmware revision in ascii. big endian byte order in word 27 - 46 yyyy * 40 model number in ascii (right justified (sf sa xxxx q xb j xxx - x - xx - xxx - xx x) 47 8001h 2 maximum number of sectors on read/write multiple command 48 0000h 2 trusted computing feature set options 49 0f00h* 2 capabilities with dma , lba, iordy supported 50 400 0 h 2 capabilities 51 0200h 2 pio data transfer cycle timing mode 2 (obsolete) 52 0000h 2 (o bsolete ) 53 0007h* 2 field validity (bytes 54 - 58, 64 - 70, 88) 54 3fff h * 2 current numbers of cylinders (obsolete) 55 0010 h * 2 current numbers of heads (obsolete) 56 003f h * 2 current sectors per track (obsolete) 57 - 58 xxxxh 4 c urrent capacity in sectors (lbas)(word 57 = lsw, word 58 = msw) (obsolete) 59 010 1 h * 2 multiple sector setting (can be changed by host). 60 - 61 xxxxh 4 total number of sectors addressable in lba mode 62 0000h 2 (o bsolete ) 63 0007h* 2 multi - word dma tran sfer support and selection (can be changed by host) . 64 0003h 2 advanced pio modes 3 and 4 supported 65 0078h* 2 minimum multi - word dma transfer cycle time per word. 66 0078h* 2 recommended multi - word dma transfer cycle time. 67 0078h* 2 minimum pio tr ansfer cycle time without flow control 68 0078h* 2 minimum pio transfer cycle time with iordy flow control 69 - 7 4 xxxx h 1 2 reserved 75 001fh* 2 maximum queue depth - 1 76 0 3 06h * 2 sata capabilities (power management, ncq, sata i & ii) 77 0000h 2 rese rved 78 004 8h * 2 sata feature support 79 00 4 0h* 2 sata features enabled (can be changed by host) 80 - 81 03f 0h 0000h 4 ata /atapi version 8,7,6,5; minor 0 82 - 84 7 4 2 bh* 7 5 0 1 h* 40 20 h* 6 features/command sets supported 85 - 87 7 4 2 9 h* 3 4 01 h* 40 2 0 h* 6 fea tures/command sets enabled (can change in operation) 88 4 07f * 2 udma mode supported 0,1,2,3,4,5,6 and selected 6 (changes in operation) 89 000 3* 2 time for security erase unit completion (e.g. 6 minutes) 9 0 - 91 0000h* 4 time for security and enhanced e rase completion 92 fffe* 2 master password revision code 9 3 - 99 0000h* 14 reserved 100 - 103 xxxxh 8 total number of user addressable sectors for the 48 - bit address feature set. 104 0000h 2 reserved
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 18 of 53 word address default value total bytes data field type information 105 0100h* 2 reserved 106 - 127 00 x 0h 44 reserved 128 0 0 21 h * 2 security status (changes in operation) 129 - 159 xx xx h 6 2 vendor specific (e.g. swissbit ssd ) 160 0000 h* 2 reserved ( max. current (cfa power mode)) 16 1 - 2 08 0000h 96 reserved 209 4000h* 2 alignment of logical blocks within a larger physical bl ock 210 - 216 000 0 h* 14 reserved 217 0001h 2 nominal media rotation rate ( ? ssd) 218 - 254 0000h 74 reserved 255 xxa5 h * 2 integrity word * standard values for full functionality, d epending on c onfiguration , can change in operation xxxx depending on dri ve capacity and drive geometry yyyy depending on drive configuration 6.5.1 word 0: general configuration this field indicates the general characteristics of the device. the default value for word 0 is set to 0 040 ah . some operating systems require bit 6 of word 0 to be set to 1 (non - removable device) to use the drive as the root storage device. 6.5.2 word 1: default number of cylinders this field contains the number of translated cylinders in the default translation mode. this value will be the same as the number o f cylinders. 6.5.3 word2: specific configuration c837h: device does not require set features subcommand to spin - up after power - up and identify device data is complete. 6.5.4 word 3: default number of heads this field contains the number of translated heads in the defa ult translation mode. 6.5.5 word 6: default number of sectors per track this field contains the number of sectors per track in the default translation mode. 6.5.6 word 7 - 8: number of sectors per drive this field contains the number of sectors per drive . this double wo rd value is also the first invalid address in lba translation mode. 6.5.7 word 10 - 19: memory drive serial number the contents of this field are right justified and padded with out spaces (20h). 6.5.8 word 23 - 26: firmware revision this field contains the revision of the firmware for this product. 6.5.9 word 27 - 46: model number this field contains the model number for this product and is left justified and padded with spaces (20h). 6.5.10 word 47: read/write multiple sector count this field contains the maximum number of sectors that can be read or written per interrupt using the read multiple or write multiple commands. 6.5.11 word 49: capabilities ? bit 13 standby timer: is set to 0 to indicate that the standby timer operation is defined by the manufacturer .
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 19 of 53 ? bit 11: iordy supported if bi t 11 is set to 1 then this drive supports iordy operation. if bit 11 is set to 0 then this drive may support iordy operation. ? bit 10: iordy may be disabled if b it 10 is set to 1 then iodrdy may be disabled . ? bit 9 lba support: drive support lba mode a ddressing. ? bit 8 dma support: read/write dma commands are supported. 6.5.12 word 51: pio data transfer cycle timing mode this field defines the mode for pio data transfer. for backward compatibility with bioss written before word 64 was defined for advanced modes , a device reports in word 51, the highest original pio mode it can support (pio mode 0, 1 or 2). bits 15 - 8: are set to 02h. 6.5.13 word 53: translation parameter valid ? bit 0: is set to 1 to indicate that words 54 to 58 are valid ? bit 1: is set to 1 to indica te that words 64 to 70 are valid ? bit 2 shall be set to 1 indicating that word 88 is valid and reflects the supported udma 6.5.14 word 54 - 56: current number of cylinders, heads, sectors/track these fields contain the current number of user addressable cylinders, heads, and sectors/track in the current translation mode. 6.5.15 word 57 - 58: current capacity this field contains the product of the current cylinders, heads and sectors. 6.5.16 word 59: multiple sector setting ? bits 15 - 9 are reserved and must be set to 0. ? bit 8 is s et to 1, to indicate that the multiple sector setting is valid. ? bits 7 - 0 are the current setting for the number of sectors to be transferred for every interrupt, on read/write multiple commands; the only values returned are 00h or 01h. 6.5.17 word 60 - 61: t otal sectors addressable in lba mode this field contains the number of sectors addressable for the drive in lba mode only. 6.5.18 word 63: multi - word dma transfer bits 15 through 8 of word 63 of the identify device parameter information is defined as the multiwor d dma mode selected field. if this field is supported, bit 1 of word 53 shall be set to one. this field is bit significant. only one of bits may be set to one in this field by the drive to indicate the multiword dma mode which is currently selected. of the se bits, bits 15 through 11 are reserved. bit 8, if set to one, indicates that multiword dma mode 0 has been selected. bit 9, if set to one, indicates that multiword dma mode 1 has been selected. bit 10, if set to one, indicates that multiword dma mode 2 h as been selected. selection of multiword dma modes 3 and above are specific to drive are as described in word 163. bits 7 through 0 of word 63 of the identify device parameter information is defined as the multiword dma data transfer supported field. if th is field is supported, bit 1 of word 53 shall be set to one. this field is bit significant. any number of bits may be set to one in this field by the drive to indicate the multiword dma modes it is capable of supporting. of these bits, bits 7 through 2 are reserved. bit 0, if set to one, indicates that the drive supports multiword dma mode 0. bit 1, if set to one, indicates that the drive supports multiword dma modes 1 and 0. bit 2, if set to one, indicates that the drive supports multiword dma modes 2, 1 a nd 0. support for multiword dma modes 3 and above are specific to drive are reported in word 163 as described in word 163. 6.5.19 word 64: advanced pio transfer modes supported this field is bit significant. any number of bits may be set to 1 in this field by t he drive to indicate the advanced pio modes it is capable of supporting. ? bits 7 - 2 are reserved for future advanced pio modes. ? bit 1 is set to 1, indicates that the drive supports pio mode 4.
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 20 of 53 ? bit 0 is set to 1 to indicate that the d rive supports pio mode 3. support for pio modes 5 and above are specific to drive are rep orted in word 163 as described in word 163. 6.5.20 word 65: minimum multi - word dma transfer cycle time word 65 of the parameter information of the identify device command is defined as the minimum multiword dma transfer cycle time. this field defines, in nanosec onds, the minimum cycle time that, if used by the host, the drive guarantees data integrity during the transfer. if this field is supported, bit 1 of word 53 shall be set to one. the value in word 65 shall not be less than the minimum cycle time for the fa stest dma mode supported by the device. this field shall be supported by all drive s supporting dma modes 1 and above. if bit 1 of word 53 is set to one, but this field is not supported, the drive shall return a value of zero in this field. 6.5.21 word 66: recomme nded multi - word dma transfer cycle time word 66 of the parameter information of the identify device command is defined as the recommended multiword dma transfer cycle time. this field defines, in nanoseconds, the cycle time that, if used by the host, may o ptimize the data transfer from by reducing the probability that the drive will need to negate the dmarq signal during the transfer of a sector. if this field is supported, bit 1 of word 53 shall be set to one. the value in word 66 shall not be less than th e value in word 65. this field shall be supported by all drive s supporting dma modes 1 and above. if bit 1 of word 53 is set to one, but this field is not supported, the drive shall return a value of zero in this field. 6.5.22 word 67: minimum pio transfer cycle time without flow control word 67 of the parameter information of the identify device command is defined as the minimum pio transfer without flow control cycle time. this field defines, in nanoseconds, the minimum cycle time that, if used by the host, the drive guarantees data integrity during the transfer without utilization of flow control. if this field is supported, bit 1 of word 53 shall be set to one. any drive that supports pio mode 3 or above shall support this field, and the value in word 67 shall not be less than the value reported in word 68. if bit 1 of word 53 is set to one because a drive supports a field in words 64 - 70 other than this field and the drive does not support this field, the drive shall return a value of zero in this field. 6.5.23 word 68 : minimum pio transfer cycle time with iordy word 68 of the parameter information of the identify device command is defined as the minimum pio transfer with iordy flow control cycle time. this field defines, in nanoseconds, the minimum cycle time that the drive supports while performing data transfers while utilizing iordy flow control. if this field is supported, bit 1 of word 53 shall be set to one. any drive that supports pio mode 3 or above shall support this field, and the value in word 68 shall be the fastest defined pio mode supported by the drive . if bit 1 of word 53 is set to one because a drive supports a field in words 64 - 70 other than this field and the drive does not support this field, the drive shall return a value of zero in this field. 6.5.24 word 75: queue depth bits (4:0) of word 75 indicate the maximum queue depth supported by the device. the queue depth includes all commands for which command acceptance has occurred and command completion has not occurred. the value in this field equals (maximum queue depth - 1), e.g., a value of zero indicates a queue depth of one, a value of 31 indicates a queue depth of 32. if bit 1 of word 83 is cleared to zero indicating that the device does not support read/write dma queued commands, or if bit 6 of word 76 is cleared to zero indicating that the device does not support read/write fpdma commands, the value in this field shall be zero. support of this word is mandatory if the tcq feature set is supported. 6.5.25 word 76: serial ata capabilities ? bit 15:11 reserved ? bit 10 1 = supports phy event counters ? bit 9 1 = supports receipt of host initiated power management requests ? bit 8 1 = supports native command queuing ? bit 7:3 reserved for future sata signaling speed grades ? bit 2 1 = supports sata gen2 signaling speed (3 .0gb/s) ? bit 1 1 = supports sata gen1 signaling speed (1.5gb/s) ? bit 0 shall be cleared to zero
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 21 of 53 6.5.26 word 7 8 : sata feature support ? bit 15 - 7 reserved ? bit 6 1 = supports software settings preservation ? bit 5 1 = supports asynchronous notification ? bit 4 1 = support s in - order data delivery ? bit 3 1 = device supports initiating interface power managment ? bit 2 1 = supports dma setup auto - activate optimization ? bit 1 1 = supports non - zero buffer offsets ? bit 0 shall be cleared to zero 6.5.27 word 7 9 : sata features enabled ? bit 15 - 7 reserved ? bit 6 1 = supports software settings preservation enabled ? bit 5 1 = supports asynchronous notification enabled ? bit 4 1 = supports in - order data delivery enabled ? bit 3 1 = device supports initiating interface power managment enabled ? bit 2 1 = su pports dma setup auto - activate optimization enabled ? bit 1 1 = supports non - zero buffer offsets enabled ? bit 0 shall be cleared to zero 6.5.28 words 82 - 84: features/command sets supported words 82, 83, and 84 shall indicate features/command sets supported. the valu e 0000h or ffffh was placed in each of these words by drive s prior to ata - 3 and shall be interpreted by the host as meaning that features/command sets supported are not indicated. bits 1 through 13 of word 83 and bits 0 through 13 of word 84 are reserved. bit 14 of word 83 and word 84 shall be set to one and bit 15 of word 83 and word 84 shall be cleared to zero to provide indication that the features/command sets supported words are valid. the values in these words should not be depended on by host impleme nters. ? bit 0 of word 82 shall be set to zero; the smart feature set is not supported. ? if bit 1 of word 82 is set to one, the security mode feature set is supported. ? bit 2 of word 82 shall be set to zero; the removable media feature set is not supported. ? b it 3 of word 82 shall be set to one; the power management feature set is supported. ? bit 4 of word 82 shall be set to zero; the packet command feature set is not supported. ? if bit 5 of word 82 is set to one, write cache is supported. ? if bit 6 of word 82 is set to one, look - ahead is supported. ? bit 7 of word 82 shall be set to zero; release interrupt is not supported. ? bit 8 of word 82 shall be set to zero; service interrupt is not supported. ? bit 9 of word 82 shall be set to zero; the device reset command is no t supported. ? bit 10 of word 82 shall be set to one ; the host protected area feature set is supported. ? bit 11 of word 82 is obsolete. ? bit 12 of word 82 shall be set to one; the drive supports the write buffer command. ? bit 13 of word 82 shall be set to one; the drive supports the read buffer command. ? bit 14 of word 82 shall be set to one; the drive supports the nop command. ? bit 15 of word 82 is obsolete. ? bit 0 of word 83 shall be set to one ; the drive support s the download microcode command. ? bit 1 of word 83 shall be set to zero; the drive does not support the read dma queued and write dma queued commands. ? bit 2 of word 83 shall be set to zero ; the drive does not support the cfa feature set. ? if bit 3 of word 83 is set to one, the drive supports the advanced power management feature set. ? bit 4 of word 83 shall be set to zero; the drive does not support the removable media status feature set. 6.5.29 words 85 - 87: features/command sets enabled words 85, 86, and 87 shall indicate features/command sets enabled. the value 0000h or ffffh was placed in each of these words by drive s prior to ata - 4 and shall be interpreted by the host as meaning that features/command sets enabled are not indicated. bits 1 through 15 of word 86 are reserved. bits 0 - 13 of word 87 are reserved. bi t 14 of word 87 shall be set to one and bit 15 of word 87 shall be cleared to zero to provide indication that the features/command sets enabled words are valid. the values in these words should not be depended on by host implementers.
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 22 of 53 ? bit 0 of word 85 shal l be set to zero; the smart feature set is not enabled. ? if bit 1 of word 85 is set to one, the security mode feature set has been enabled via the security ? set password command. ? bit 2 of word 85 shall be set to zero; the removable media feature set is not s upported. ? bit 3 of word 85 shall be set to one; the power management feature set is supported. ? bit 4 of word 85 shall be set to zero; the packet command feature set is not enabled. ? if bit 5 of word 85 is set to one, write cache is enabled. ? if bit 6 of word 85 is set to one, look - ahead is enabled. ? bit 7 of word 85 shall be set to zero; release interrupt is not enabled. ? bit 8 of word 85 shall be set to zero; service interrupt is not enabled. ? bit 9 of word 85 shall be set to zero; the device reset command is n ot supported. ? bit 10 of word 85 shall be set to zero; the host protected area feature set is not supported. ? bit 11 of word 85 is obsolete. ? bit 12 of word 85 shall be set to one; the drive supports the write buffer command. ? bit 13 of word 85 shall be set to one; the drive supports the read buffer command. ? bit 14 of word 85 shall be set to one; the drive supports the nop command. ? bit 15 of word 85 is obsolete. ? bit 0 of word 86 shall be set to one ; the drive support s the download microcode command. ? bit 1 of wo rd 86 shall be set to zero; the drive does not support the read dma queued and write dma queued commands. ? if bit 2 of word 86 shall be set to zero , the drive does not support the cfa feature set. ? if bit 3 of word 86 is set to one, the advanced power manage ment feature set has been enabled via the set features command. ? bit 4 of word 86 shall be set to zero; the drive does not support the removable media status feature set. 6.5.30 word 88: ultra dma modes supported and selected word 88 identifies the ultra dma trans fer modes supported by the device and indicates the mode that is currently selected. only one dma mode shall be selected at any given time. if an ultra dma mode is selected, then no multiword dma mode shall be selected. if a multiword dma mode is selected, then no ultra dma mode shall be selected. support of this word is mandatory if ultra dma is supported. word 88 shall return a value of 0 if the device does not support udma . ? bit 15: reserved ? bit 14: 1 = ultra dma mode 6 i s selected 0 = ultra dma mode 6 is not selected ? bit 13: 1 = ultra dma mode 5 is selected 0 = ultra dma mode 5 is not selected ? bit 12: 1 = ultra dma mode 4 i s selected 0 = ultra dma mode 4 is not selected ? bit 11: 1 = ultra dma mode 3 i s selected 0 = ultra dma mode 3 is not selected ? bit 10: 1 = ultra dma mode 2 i s selected 0 = ultra dma mode 2 is not selected ? bit 9: 1 = ultra dma mode 1 i s selected 0 = ultra dma mode 1 is not selected ? bit 8: 1 = ultra dma mode 0 i s selected 0 = ultra dma mode 0 is not selected ? bit 7: reserved ? b it 6: 1 = ultra dma mode 6 and below are supported. bits 0 - 5 shall be set to 1. ? bit 5: 1 = ultra dma mode 5 an d below are supported. bits 0 - 4 shall be set to 1. ? bit 4: 1 = ultra dma mode 4 an d below are supported. bits 0 - 3 shall be set to 1. ? bit 3: 1 = ultra dma mode 3 an d below are supported, bits 0 - 2 shall be set to 1. ? bit 2: 1 = ultra dma mode 2 an d below are supported. bits 0 - 1 shall be set to 1. ? bit 1: 1 = ultra dma mode 1 and below are supported. bit 0 shall be set to 1. ? bit 0: 1 = ultra d ma mode 0 is supported 6.5.31 word 89: time required for security erase unit completion word 89 specifies the time required for the security erase unit command to complete. support of this word is mandatory if the security feature set is supported. required time =(value*2) minutes 6.5.32 word 92: master password revision code word 92 contains the value of the master password revision code set when the master password was last changed. valid values are 0001h through fffeh. a value of 0000h or ffffh indicates that the mast er password revision is not supported. support of this word is mandatory if the security feature set is supported.
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 23 of 53 6.5.33 words 100 - 103: total number of user addressable sectors for the 48 - bit address feature set words 100 - 103 contain a value that is one greater than the maximum lba in user accessible space when the 48 - bit addressing feature set is supported. the maximum value that shall be placed in this field is 0000_ffff_ffff_ffffh. support of these words is mandatory if the 48 - bit address feature set is suppor ted. 6.5.34 word 128: security status support of this word is mandatory if the security feature set is supported. bit 8 of word 128 indicates the security level. if security mode is enabled and the security level is high, bit 8 shall be cleared to zero. if securi ty mode is enabled and the security level is maximum, bit 8 shall be set to one. when security mode is disabled, bit 8 shall be cleared to zero. bit 5 of word 128 indicates the enhanced security erase unit feature is supported. if bit 5 is set to one, the enhanced security erase unit feature set is supported. bit 4 of word 128 indicates that the security count has expired. if bit 4 is set to one, the security count is expired and security unlock and security erase unit are command aborted until a power - on r eset or hardware reset. bit 3 of word 128 indicates security frozen. if bit 3 is set to one, the security is frozen. bit 2 of word 128 indicates security locked. if bit 2 is set to one, the security is locked. bit 1 of word 128 indicates security enabled. if bit 1 is set to one, the security is enabled. bit 0 of word 128 indicates the security mode feature set supported. if bit 0 is set to one, security is supported. 6.5.35 word 209: alignment of logical blocks within a physical block word 209 shall report the loc ation of lba0 within the first physical sector of the media. this bit is valid if the bit 13 of word 106 is set to 1 indicating device has multiple sector per physical sector. 6.5.36 word 217: nominal media rotation rate word 217 indicates the nominal media rotat ion rate of the device. 0001h indicating a non - rotating media (ssd). 6.6 idle (97h or e3h) this command causes the drive to set bsy, enter the idle mode, clear bsy and generate an interrupt. if the sector count is non - zero, it is interpreted as a timer count ( each count is 5ms) and the automatic power down mode is enabled. if the sector count is zero, the automatic power down mode is disabled. note that this time base (5ms) is different from the ata specification. table 24 defines the byte sequence of the idle command. table 24 : idle task file register 7 6 5 4 3 2 1 0 command 97h or e3h drive/head nu nu nu d nu cylinder hi nu cylinder low nu sector num nu sector count timer count (5ms incre ments) features nu 6.7 idle immediate (95h or e1h) this command causes the drive to set bsy, enter the idle mode, clear bsy and generate an interrupt. tabl e 25 defines the idle immediate command byte sequence. tabl e 25 : idle immediate task file register 7 6 5 4 3 2 1 0 command 95h or e1h drive/head nu nu nu d nu cylinder hi nu cylinder low nu sector num nu sector count nu features nu
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 24 of 53 6.8 nop (00h) this command always fails with the d rive returning command aborted. table 26 defines the byte sequence of the nop command. table 26 : nop task file register 7 6 5 4 3 2 1 0 command 00h drive/head nu nu nu d nu cylinder hi nu c ylinder low nu sector num nu sector count nu features nu 6.9 read buffer (e4h) the read buffer command enables the host to read the current contents of the drive s sector buffer. this command has the same protocol as the read sector(s) command. table 27 defines the read buffer command byte sequence. table 27 : read buffer task file register 7 6 5 4 3 2 1 0 command e4h drive/head nu nu nu d nu cylinder hi nu cylinder low nu sector num nu sector count nu features nu 6.10 read dma (c8h) this command uses dma mode to read from 1 to 256 sectors as specified in the sector count register. a sector count of 0 requests 256 sectors. the transfer begins at the sector specified in the sector number r egister. when this command is issued the drive sets bsy, puts all or part of the sector of data in the buffer. the drive is then permitted, although not required, to set drq, clear bsy. the drive asserts dmareq while data is available to be transferred. th e drive asserts dmareq while data is available to be transferred. the host then reads the (512 * sector - count) bytes of data from the drive using dma. while dmareq is asserted by the drive , the host asserts - dmack while it is ready to transfer data by dma and asserts - iord once for each 16 bit word to be transferred to the host. interrupts are not generated on every sector, but upon completion of the transfer of the entire number of sectors to be transferred or upon the occurrence of an unrecoverable error. at command completion, the command block registers contain the cylinder, head and sector number of the last sector read. if an error occurs, the read terminates at the sector where the error occurred. the command block registers contain the cylinder, head , and sector number of the sector where the error occurred. the amount of data transferred is indeterminate. table 28 : read dma task file register 7 6 5 4 3 2 1 0 command c8h drive/head 1 lba 1 d head (lba 27 - 24) cylinder hi cyl inder high (lba23 - 16) cylinder low cylinder low (lba15 - 8) sector num sector number (lba7 - 0) sector count sector count features nu
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 25 of 53 6.11 read dma ext (25h) 48bit lba this command uses dma mode to read from 1 to 65536 sectors as specified in the sector count register. a sector count of 0 requests 65536 sectors. the transfer begins at the sector specified in the sector number register. when this command is issued the ssd sets bsy, puts all or part of the sector of data in the buffer. the ssd is then permitted, although not required, to set drq, clear bsy. the ssd asserts dmarq while data is available to be transferred. the ssd asserts dmarq while data is available to be transferred. the host then reads the (512 * sector - count) bytes of data from the ssd using d ma. while dmarq is asserted by the ssd , the host asserts - dmack while it is ready to transfer data by dma and asserts - iord once for each 16 bit word to be transferred to the host. interrupts are not generated on every sector, but upon completion of the t ransfer of the entire number of sectors to be transferred or upon the occurrence of an unrecoverable error. at command completion, the command block registers contain the lba of the last sector read. if an error occurs, the read terminates at the sector w here the error occurred. the command block registers contain the lba of the sector where the error occurred. the amount of data transferred is indeterminate. when a read dma ext command is received by the ssd and 8 bit transfer mode has been enabled by th e set features command, the ssd shall return the aborted error. table 29 : read dma ext register write previous current task file register 15:8 7 6 5 4 3 2 1 0 command - 25h drive/head - 1 1 1 drive reserved lba high lba (47:4 0) lba (23:16) lba mid lba (39:32) lba (15:8) lba low lba (31:24) lba (7:0) sector count 15:8 7:0 features nu nu 6.12 read fpdma queued (60h) (if ncq feature set supported) this command is mandatory for devices implementing the ncq feature set (see feature set reference). this command requests that data to be transferred from the device to the host. when the forced unit access (fua) bit is set to one the device shall retrieve the data from the ssd regardless of whether the device holds the requested informa tion in its volatile cache. if the device holds a modified copy of the requested data as a result of having volatile cached writes, the modified data shall be written to the non - volatile media before being retrieved from the non - volatile media as part of t his operation. when the fua bit is cleared to zero the data shall be retrieved either from the device's non - volatile media or cache. table 30 : read fpdma queued task file register 15:8 7 6 5 4 3 2 1 0 command - 61h drive/head - f ua 1 nu 0 nu cylinder hi lba (47:40) lba23:16 cylinder low lba (39:32) lba15:8 sector num lba (31:24) lba7:0 sector count nu ncq tag nu features the number of logical sectors to be transferred. a value of 0000h indicates that 65,536 logical sectors ar e to be transferred. for further details see the ata8 specification. 6.13 read multiple (c4h) the read multiple command performs similarly to the read sectors command. interrupts are not generated on every sector, but on the transfer of a block which contains the number of sectors defined by a set multiple command. command execution is identical to the read sectors operation except that the number of sectors defined by a set multiple command is transferred without intervening interrupts. drq qualification of th e transfer is required only at the start of the data block, not on each sector. the block count of sectors to be transferred without intervening interrupts is programmed by the set multiple mode command, which must be executed prior to the read multiple co mmand. when the read multiple command is issued, the sector count register contains the number of sectors (not the number of blocks or the block count) requested. if the number of requested sectors is not evenly divisible by the block count, as many
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 26 of 53 full b locks as possible are transferred, followed by a final, partial block transfer. the partial block transfer is for n sectors, where: n = (sector count) module (block count). if the read multiple command is attempted before the set multiple mode command has been executed or when read multiple commands are disabled, the read multiple operation is rejected with an aborted command error. disk errors encountered during read multiple commands are posted at the beginning of the block or partial block transfer, but drq is still set and the data transfer will take place as it normally would, including transfer of corrupted data, if any. interrupts are generated when drq is set at the beginning of each block or partial block. the error reporting is the same as that on a read sector(s) command. this command reads from 1 to 256 sectors as specified in the sector count register. a sector count of 0 requests 256 sectors. the transfer begins at the sector specified in the sector number register. if an error occurs, the read terminates at the sector where the error occurred. the command block registers contain the cylinder, head and sector number of the sector where the error occurred. the flawed data are pending in the sector buffer. subsequent blocks or partial blocks are tr ansferred only if the error was a correctable data error. all other errors cause the command to stop after transfer of the block which contained the error. table 31 defines the read multiple command byte sequence. table 31 : read multiple task file register 7 6 5 4 3 2 1 0 command c4h drive/head 1 lba 1 d head (lba 27 - 24) cylinder hi cylinder high (lba23 - 16) cylinder low cylinder low (lba15 - 8) sector num sector number (lba7 - 0) sector c ount sector count features nu 6.14 read multiple ext (29h) 48bit lba the read multiple ext command performs similarly to the read sectors ext command. interrupts are not generated on every sector, but on the transfer of a block, which contains the number of s ectors defined by a set multiple command. command execution is identical to the read sectors ext operation except that the number of sectors defined by a set multiple command is transferred without intervening interrupts. drq qualification of the transfer is required only at the start of the data block, not on each sector. the block count of sectors to be transferred without intervening interrupts is programmed by the set multiple mode command, which shall be executed prior to the read multiple command. w hen the read multiple command is issued, the sector count register contains the number of sectors (not the number of blocks or the block count) requested. if the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. the partial block transfer is for n sectors, where n = (sector count) modulo (block count). if the read multiple ext command is attempted before the set multiple mode command has been executed, or when read multiple ext command is disabled, the read multiple ext operation is rejected with an aborted command error. disk errors encountered during a read multiple ext command are posted at the beginning of the block or partial block transf er, but drq is still set and the data transfer shall take place as it normally would, including transfer of corrupted data, if any. interrupts are generated when drq is set at the beginning of each block or partial block. the error reporting is the same a s that on a read sector(s) command. this command reads from 1 to 65536 sectors as specified in the sector count register. a sector count of 0 requests 65536 sectors. the transfer begins at the sector specified in the sector number register. at command comp letion, the command block registers contain the lba of the last sector read. if an error occurs, the read terminates at the sector where the error occurred. the command block registers contain the lba of the sector where the error occurred. the flawed dat a is pending in the sector buffer. subsequent blocks or partial blocks are transferred only if the error was a correctable data error. all other errors cause the command to stop after transfer of the block that contained the error.
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 27 of 53 table 32 : read multiple ext register write previous current task file register 15:8 7 6 5 4 3 2 1 0 command - 29h drive/head - 1 1 1 drive reserved lba high lba (47:40) lba (23:16) lba mid lba (39:32) lba (15:8) lba low lba (31:24) lba (7:0) s ector count 15:8 7:0 features nu nu note: this specification requires that ssd s support a multiple block count of 1 and permits larger values to be supported. 6.15 read native max address (f8h) the read native max address command reads the max native address of the drive. it is related to the host protected area feature set. table 33 defines the read max native address command byte sequence. table 33 : read native max address task file register 7 6 5 4 3 2 1 0 command f8h drive/head nu lba nu d nu cylinder hi nu cylinder low nu sector num nu sector count nu features nu the lba bit shall be set to one to specify the address is an lba. dev shall specify the selected device. the native drive size is given in drive/head, cyl hi, cyl low and sector num register as lba value. 6.16 read native max address ext (27h) the read native max address ext command reads the max native address of the drive. it is related to the host protected area feature set an d 48 - bit address feature set. table 34 defines the read max native address command byte sequence. table 34 : read native max address task file register 7 6 5 4 3 2 1 0 command 27h drive/he ad nu lba nu d nu cylinder hi nu cylinder low nu sector num nu sector count nu features nu the lba bit shall be set to one to specify the address is an lba. dev shall specify the selected device. the native drive size is given in 16bit lba high, mid and low register as 48bit lba value. to read out the higher and lower byte of the 16bit registers bit7 of the device control register (hob=high order bit, write to alternate status register) must be set to 1 or 0, respectively. 6.17 read sector(s) (20h ) this c ommand reads from 1 to 256 sectors as specified in the sector count register. a sector count of 0 requests 256 sectors. the transfer begins at the sector specified in the sector number register. when this command is issued and after each sector of data (ex cept the last one) has been read by the host, the drive sets bsy, puts the sector of data in the buffer, sets drq, clears bsy, and generates an interrupt. the host then reads the 512 bytes of data from the buffer. if an error occurs, the read terminates at the sector where the error occurred. the command block registers contain the cylinder, head, and sector number of the sector where the error occurred. the flawed data are pending in the sector buffer. table 35 def ines the read sector command byte sequence.
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 28 of 53 table 35 : read sector(s) task file register 7 6 5 4 3 2 1 0 command 20h drive/head 1 lba 1 d head (lba 27 - 24) cylinder hi cylinder high (lba23 - 16) cylinder low cylinder low (lba15 - 8) sector num sector number (lba7 - 0) sector count sector count features nu 6.18 read sectors ext (24h) 48bit lba this command reads from 1 to 65536 sectors as specified in the sector count register. a sector count of 0 requests 65536 sectors. the transfer beg ins at the specified lba. when this command is issued and after each sector of data (except the last one) has been read by the host, the ssd sets bsy, puts the sector of data in the buffer, sets drq, clears bsy, and generates an interrupt. the host then re ads the 512 bytes of data from the buffer. at command completion, the command block registers contain the lba of the last sector read. if an error occurs, the read terminates at the sector where the error occurred. the command block registers contain the lba of the sector where the error occurred. the flawed data is pending in the sector buffer. table 36 : read multiple ext register write previous current task file register 15:8 7 6 5 4 3 2 1 0 command - 24h drive/head - 1 1 1 drive reserved lba high lba (47:40) lba (23:16) lba mid lba (39:32) lba (15:8) lba low lba (31:24) lba (7:0) sector count 15:8 7:0 features nu nu 6.19 read verify sector(s) (40h or 41h) this command is identical to the read sectors command, except that dr q is never set and no data is transferred to the host. when the command is accepted, the drive sets bsy. when the requested sectors have been verified, the drive clears bsy and generates an interrupt. if an error occurs, the verify terminates at the secto r where the error occurs. the command block registers contain the cylinder, head and sector number of the sector where the error occurred. the sector count register contains the number of sectors not yet verified. table 37 defines the read verify sector command byte sequence. table 37 : read verify sector(s) task file register 7 6 5 4 3 2 1 0 command 40h or 41h drive/head 1 lba 1 d head (lba 27 - 24) cylinder hi cylinder high (lba23 - 16) cy linder low cylinder low (lba15 - 8) sector num sector number (lba7 - 0) sector count sector count features nu 6.20 read verify ext (42h) 48bit lba this command is identical to the read sector(s) ext command, except that drq is never set and no data is transfer red to the host. when the command is accepted, the ssd sets bsy. when the requested sectors have been verified, the ssd clears bsy and generates an interrupt. upon command completion, the command block registers contain the lba of the last sector verified.
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 29 of 53 if an error occurs, the read verify command terminates at the sector where the error occurs. the command block registers contain the lba of the sector where the error occurred. the sector count register contains the number of sectors not yet verified. t able 38 : read multiple ext register write previous current task file register 15:8 7 6 5 4 3 2 1 0 command - 42h drive/head - 1 1 1 drive reserved lba high lba (47:40) lba (23:16) lba mid lba (39:32) lba (15:8) lba low lba ( 31:24) lba (7:0) sector count 15:8 7:0 features nu nu 6.21 security disable password (f6h) this command requests a transfer of a single sector of data from the host. table 39 defines the content of this sector of inf ormation. if the password selected by word 0 matches the password previously saved by the device, the device disables the lock mode. this command does not change the master password that may be reactivated later by setting a user password. table 39 : security disable password task file register 7 6 5 4 3 2 1 0 command f6h drive/head 1 lba 1 d nu cylinder hi nu cylinder low nu sector num nu sector count nu features nu table 40 : security password data c ontent word content 0 control word bit 0: i dentifier 0=compare user password 1=compare master password bit 1 - 15: reserved 1 - 16 password (32 bytes) 1 7 - 255 reserved 6.22 security erase prepare (f3h) this command shall be i ssued immediately before the security erase unit command to enable device erasing and unlocking. this command prevents accidental erase of the ssd . table 41 : security erase prepare task file register 7 6 5 4 3 2 1 0 command f3h d rive/head 1 lba 1 d nu cylinder hi nu cylinder low nu sector num nu sector count nu features nu
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 30 of 53 6.23 security erase unit (f4h) this command requests transfer of a single sector of data from the host. table 43 defines the conten t of this sector of information. if the password does not match the password previously saved by the ssd , the ssd rejects the command with command aborted. the security erase prepare command shall be completed immediately prior to the security erase unit c ommand. if the ssd receives a security erase unit command without an immediately prior security erase prepare command, the ssd aborts the security erase unit command. table 42 : security erase unit task file register 7 6 5 4 3 2 1 0 command f4h drive/head 1 lba 1 d nu cylinder hi nu cylinder low nu sector num nu sector count nu features nu table 43 : security erase password and parameter data content word content 0 control word bit 0: identifi er 0=compare user password 1=compare master password bit 1 - 15: reserved 1 - 16 password (32 bytes) 1 7 - 255 reserved *) is the enhance erase option is supported (ataid word128 bit5 = 1) enhanced erase features if supported (see s eparate specification document) 6.24 security freeze lock (f5h) the security freeze lock command sets the ssd to frozen mode. after command completion, any other commands that update the ssd lock mode are rejected. frozen mode is disabled by power off or hardwa re reset. if security freeze lock is issued when the ssd is in frozen mode, the command executes and the ssd remains in frozen mode. after command completion, the sector count register shall be set to 0. commands disabled by security freeze lock are: ? ? s ecurity set password ? ? security unlock ? ? security disable password ? ? security erase unit if security mode feature set is not supported, this command shall be handled as wear level command. table 44 : security freeze lock task fil e register 7 6 5 4 3 2 1 0 command f5h drive/head 1 lba 1 d nu cylinder hi nu cylinder low nu sector num nu sector count nu features nu 6.25 security set password (f1h) this command requests a transfer of a single sector of data from the host. table 46 defines the content of the sector of information. the data transferred controls the function of this command. table 47 defines the interaction of the identifier and secur ity level bits.
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 31 of 53 table 45 : security set password task file register 7 6 5 4 3 2 1 0 command f1h drive/head 1 lba 1 d nu cylinder hi nu cylinder low nu sector num nu sector count nu features nu table 46 : security set password data content word content 0 control word bit 0: identifier 0=set user password 1=set master password bit 1 - 7: reserved bit 8: security level 0=high 1=maximum bits 9 - 15: reserved 1 - 16 password (32 bytes) 17 - 255 reserved table 47 : identifier and security level bit interaction identifier level command result user high the password supplied with the command shall be saved as the new u ser password. the lock mode shall be enabled from the next power - on or hardware reset. the ssd shall then be unlocked by either the user password or the previously set master password. user maximum the password supplied with the command shall be saved as the new user password. the lock mode shall be enabled from the next power - on or hardware reset. the ssd shall then be unlocked by only the user password. the master password previously set is still stored in the ssd shall not be used to unlock the ssd . ma ster high or maximum this combination shall set a master password but shall not enable or disable the lock mode. the security level is not changed. 6.26 security unlock (f2h) this command requests transfer of a single sector of data from the host. table 40 defines the content of this sector of information. if the identifier bit is set to master and the device is in high security level, then the password supplied shall be compared with the stored master password. if the device is in the maximum security level, then the unlock command shall be rejected. if the identifier bit is set to user, then the device compares the supplied password with the stored user password. if the password compare fails then the device returns c ommand aborted to the host and decrements the unlock counter. this counter is initially set to five and is decremented for each password mismatch when security unlock is issued and the device is locked. once this counter reaches zero, the security unlock a nd security erase unit commands are command aborted until after a power - on reset or a hardware reset is received. security unlock commands issued when the device is unlocked have no effect on the unlock counter. table 48 : security unlock task file register 7 6 5 4 3 2 1 0 command f2h drive/head 1 lba 1 d nu cylinder hi nu cylinder low nu sector num nu sector count nu features nu
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 32 of 53 6.27 set features (efh) this command is used by the host to establish or select certain features. if any subcommand input value is not supported or is invalid, the ssd returns command aborted. table 49 : set features task file register 7 6 5 4 3 2 1 0 command efh drive/head nu d nu cylinder hi nu cylinder low nu sector num nu sector count config features feature table 50 : features supported feature operation 01h/81h enable/disable 8 - bit data transfers. 02h/82h enable/disable write cache. 03h set transfer mode based on value in sector count registe r. 05h/85h enable/disable advance power management. 09h/89h enable/disable extended power operations. 0ah/8ah enable/disable power level 1 commands. 55h/aah disable/enable read look ahead. 66h/cch disable/enable power on reset (por) established of def aults at soft reset. 69h nop accepted for backward compatibility. 96h nop accepted for backward compatibility. 97h accepted for backward compatibility. use of this feature is not recommended. 9ah set the host current source capability. allows trade - of f between current drawn and read/write speed. bbh 4 bytes of data apply on read/write long commands features 01h and 81h are used to enable and clear 8 bit data transfer modes in true ide mode. if the 01h feature command is issued all data transfers sha ll occur on the low order d[7:0] data bus and the - iois16 signal shall not be asserted for data register accesses. the host shall not enable this feature for dma transfers. features 02h and 82h allow the host to enable or disable write cache in ssd that im plement write cache. when the subcommand disable write cache is issued, the ssd shall initiate the sequence to flush cache to non - volatile memory before command completion. feature 03h allows the host to select the pio or multiword dma transfer mode by spe cifying a value in the sector count register. the upper 5 bits define the type of transfer and the low order 3 bits encode the mode value. one pio mode shall be selected at all times. for ssd s which support dma, one dma mode shall be selected at all times. the host may change the selected modes by the set features command. table 51 : transfer mode values mode bits (7:3) bits (2:0) pio default mode 00000b 000b pio default mode, disable iordy 00000b 001b pio flow control transfer mode 00001b mode (1) reserved 00010b n/a multi - word dma mode 00100b mode (1) ultra dma mode 01000b mode (1) reserved 1000b n/a (1)mode = transfer mode number if a ssd supports pio modes greater than 0 and receives a set features command with a set trans fer mode parameter and a sector count register value of 00000000b, it shall set its default pio mode. if the value is 00000001b and the ssd supports disabling of iordy, then the ssd shall set its default pio mode and disable iordy. a ssd shall support all pio modes below the highest mode supported, e.g., if pio mode 1 is supported pio mode 0 shall be supported.
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 33 of 53 support of iordy is mandatory when pio mode 3 or above is the current mode of operation. a ssd reporting support for multiword dma modes shall s upport all multiword dma modes below the highest mode supported. for example, if multiword dma mode 2 support is reported, then modes 1 and 0 shall also be supported. a ssd reporting support for ultra dma modes shall support all ultra dma modes below the h ighest mode supported. for example, if ultra dma mode 2 support is reported then modes 1 and 0 shall also be supported. if an ultra dma mode is enabled, any previously enabled multiword dma mode shall be disabled by the device. if a multiword dma mode is e nabled any previously enabled ultra dma mode shall be disabled by the device. feature 05h allows the host to enable advanced power management. to enable advanced power management, the host writes the sector count register with the desired advanced power ma nagement level and then executes a set features command with subcommand code 05h. the power management level is a scale from the lowest power consumption setting of 01h to the ma ximum performance level of feh. table 52 shows thes e values. table 52 : advanced power management levels level sector count value maximum performance feh intermediate power management levels without standby 81h - fdh minimum power consumption without standby 80h intermediate p ower management levels with standby 02h - 7fh minimum power consumption with standby 01h reserved ffh reserved 00h in the current version the advanced power management levels are accepted, but dont influence performance to best meet the host systems power requirements. the host sets a value in the sector count register that is equal to one - fourth of the desired maximum average current (in ma) that the ssd s hould consume. for example, if the sector count register were set to 6, the ssd would be configured to provide the best possible performance without exceeding 24 ma. upon completion of the command, the ssd responds to the host with the range of values supp orted by the ssd . the minimum value is set in the cylinder low register, and the maximum value is set in the cylinder hi register. the default value, after a power on reset, is to operate at the highest performance and therefore the highest current mode. t he ssd shall accept values outside this programmable range, but shall operate at either the lowest power or highest performance as appropriate. features 66h and cch can be used to enable and disable whether the power on reset (por) defaults shall be set wh en a soft reset occurs. the default setting is to revert to the por defaults when a soft reset occurs. 6.28 set max address (f9h) the set max address command sets the max address of the drive. it is related to the host protected area feature set. table 53 defines the set max address command byte sequence.
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 34 of 53 table 53 : read native max address task file register 7 6 5 4 3 2 1 0 command f8h drive/head nu lba nu d set max lba (27:24) cylinder hi se t max lba (23:16) cylinder low set max lba (15:8) sector num set max lba (7:0) sector count nu vv features feature the lba bit shall be set to one to specify the address is an lba. dev shall specify the selected device. prerequisites drdy set to one. a successful read native max address command shall immediately precede a set max address command. vv =value volatile. if bit 0 is set to one, the device shall preserve the maximum values over power - up or hardware reset. if bit 0 is cleared to zero, the de vice shall revert to the most recent nonvolatile maximum address value setting over power - up or hardware reset. the set max address can be locked/unlocked and secured by password with following features: table 54 : set max features feature register command 00h obsolete 01h set max set password 02h set max lock 03h set max unlock 04h set max freeze lock 05 - ffh reserved typical use of the set max address (f9h) and read native max address (f8h) commands would be: on reset bi os receives control after a system reset; 1. bios issues a read native max address command to find the max capacity of the device; 2. bios issues a set max address command to the values returned by read native max address; 3. bios reads configuration data from the highest area on the disk; 4. bios issues a read native max address command followed by a set max address command to reset the device to the size of the file system. on save to disk 1. bios receives control prior to shut down; 2. bios issues a read native max addres s command to find the max capacity of the device; 3. bios issues a volatile set max address command to the values returned by read native max address; 4. memory is copied to the reserved area; 5. shut down completes; 6. on power - on or hardware reset the device max add ress returns to the last non - volatile setting. these commands are intended for use only by system bios or other low - level boot time process. using these commands outside bios controlled boot or shutdown may result in damage to file systems on the device . devices should return command aborted if a subsequent non - volatile set max address command is received after a power - on or hardware reset. 6.29 set max address ext (37h) 48bit lba the set max address ext command sets the max address of the drive in 48bit lba mode. it is related to the host protected area feature set and 48bit feature set. table 53 defines the set max address command byte sequence.
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 35 of 53 table 55 : read native max address register wri te previous current task file register 15:8 7 6 5 4 3 2 1 0 command - 37h drive/head - 1 1 1 drive reserved lba high lba (47:40) lba (23:16) lba mid lba (39:32) lba (15:8) lba low lba (31:24) lba (7:0) sector count nu nu vv features nu nu the lb a bit shall be set to one to specify the address is an lba. dev shall specify the selected device. prerequisites drdy set to one. a successful read native max address command shall immediately precede a set max address command. vv =value volatile. if bit 0 is set to one, the device shall preserve the maximum values over power - up or hardware reset. if bit 0 is cleared to zero, the device shall revert to the most recent nonvolatile maximum address value setting over power - up or hardware reset. the output is the same as for readout native max address ext (see 6.15 and 6.16 ) ). 6.30 set multiple mode (c6h) this command enables the drive to perform read and write multiple operations and establishes the block c ount for these commands. the sector count register is loaded with the number of sectors per block. upon receipt of the command, the drive sets bsy and checks the sector count register. if the sector count register contains a valid value and the block count is supported, the value is loaded for all subsequent read multiple and write multiple commands and execution is enabled. if a block count is not supported, an aborted command error is posted, and read multiple and write multiple commands are disabled. if the sector count register contains 0 when the command is issued, read and write multiple commands are disabled. at power on the default mode is read and write multiple disabled, unless it is disabled by a set feature command. table 56 defines the set multiple mode command byte sequence. table 56 : set multiple mode task file register 7 6 5 4 3 2 1 0 command c6h drive/head nu d nu cylinder hi nu cylinder low nu sector num nu sector cou nt sector count features nu 6.31 sleep ( 99 h or e 6 ) this command causes the drive to set bsy, enter the sleep mode (which corresponds to the ata standby mode), clear bsy and return the interrupt immediately. recovery from sleep mode is accomplished by issui ng another command. table 57 defines the standby command byte sequence. table 57 : s leep task file register 7 6 5 4 3 2 1 0 command 9 9 h or e 6 h drive/head nu d nu cylinder hi nu cylind er low nu sector num nu sector count nu features nu
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 36 of 53 6.32 s.m.a.r.t. (b0h) the intent of self - monitoring, analysis, and reporting technology (the smart feature set) is to protect user data and minimize the likelihood of unscheduled system downtime that may b e caused by predictable degradation and/or fault of the device. by monitoring and storing critical performance and calibration parameters, smart feature set devices attempt to predict the likelihood of near - term degradation or fault condition. providing th e host system the knowledge of a negative reliability condition allows the host system to warn the user of the impending risk of a data loss and advise the user of appropriate action. support of this feature set is indicated in the identify device data (wo rd 82 bit 0). table 58 : s.m.a.r.t. features task file register 7 6 5 4 3 2 1 0 command b0h drive/head 1 1 1 d nu cylinder hi c2h cylinder low 4fh sector num nu sector count xxh features feature details of s.m.a.r.t. featur es are described in section 7 . 6.33 standby (96h or e2) this command causes the drive to set bsy, enter the sleep mode (which corresponds to the ata standby mode), clear bsy and return the interrupt immediately. re covery from sleep mode is accomplished by issuing another command. table 59 defines the standby command byte sequence. table 59 : standby task file register 7 6 5 4 3 2 1 0 command 96h or e2h drive/head nu d nu cylinder hi nu cylinder low nu sector num nu sector count nu features nu 6.34 standby immediate (94h or e0h) this command causes the drive to set bsy, enter the sleep mode (which corresponds to the ata standby mode), clear bsy and return the interrupt immediately. recovery from sleep mode is accomplished by issuing another command. table 60 defines the standby immediate byte sequence. table 60 : standby immediate ta sk file register 7 6 5 4 3 2 1 0 command 94h or e0h drive/head nu d nu cylinder hi nu cylinder low nu sector num nu sector count nu features nu 6.35 write buffer (e8h) the write buffer command enables the host to overwrite contents of the drive s sector buffer with any data pattern desired. this command has the same protocol as the write sector(s) command and transfers 512 bytes. table 61 defines the write buffer command byte sequence.
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 37 of 53 table 61 : write buffer task file register 7 6 5 4 3 2 1 0 command e8h drive/head nu d nu cylinder hi nu cylinder low nu sector num nu sector count nu features nu 6.36 write dma (c a h) this command uses dma mode to write from 1 to 256 sectors as specified i n the sector count register. a sector count of 0 requests 256 sectors. the transfer begins at the sector specified in the sector number register. when this command is issued the drive sets bsy, puts all or part of the sector of data in the buffer. the driv e is then permitted, although not required, to set drq, clear bsy. the drive asserts dmareq while data is available to be transferred. the host then writes the (512 * sector - count) bytes of data to the drive using dma. while dmareq is asserted by the drive , the host asserts - dmack while it is ready to transfer data by dma and asserts - iowr once for each 16 bit word to be transferred from the host. interrupts are not generated on every sector, but upon completion of the transfer of the entire number of secto rs to be transferred or upon the occurrence of an unrecoverable error. at command completion, the command block registers contain the cylinder, head and sector number of the last sector written. if an error occurs, the write terminates at the sector where the error occurred. the command block registers contain the cylinder, head, and sector number of the sector where the error occurred. the amount of data transferred is indeterminate. when a write dma command is received by the drive and 8 bit transfer mode has been enabled by the set features command, the drive shall return the aborted error. table 62 : write dma task file register 7 6 5 4 3 2 1 0 command c a h drive/head 1 lba 1 d head (lba 27 - 24) cylinder hi cylinder high (lba23 - 1 6) cylinder low cylinder low (lba15 - 8) sector num sector number (lba7 - 0) sector count sector count features nu 6.37 write dma ext (35h) 48bit lba this command uses dma mode to write from 1 to 65536 sectors as specified in the sector count register. a secto r count of 0 requests 65536 sectors. the transfer begins at the sector specified in the sector number register. when this command is issued the ssd sets bsy, puts all or part of the sector of data in the buffer. the ssd is then permitted, although not requ ired, to set drq, clear bsy. the ssd asserts dmarq while data is available to be transferred. the host then writes the (512 * sector - count) bytes of data to the ssd using the dma protocol. while dmarq is asserted by the ssd , the host asserts - dmack while i t is ready to transfer data by dma and asserts - iowr once for each 16 bit word to be transferred from the host. interrupts are not generated on every sector, but upon completion of the transfer of the entire number of sectors to be transferred or upon the occurrence of an unrecoverable error. at command completion, the command block registers contain the lba of the last sector written. if an error occurs, the write terminates at the sector where the error occurred. the command block registers contain the lba of the sector where the error occurred. the amount of data transferred is indeterminate. when a write dma command is received by the ssd and 8 bit transfer mode has been enabled by the set features command, the ssd shall return the aborted error.
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 38 of 53 t able 63 : write dma ext register write previous current task file register 15:8 7 6 5 4 3 2 1 0 command - 35h drive/head - 1 1 1 drive reserved lba high lba (47:40) lba (23:16) lba mid lba (39:32) lba (15:8) lba low lba (31:2 4) lba (7:0) sector count 15:8 7:0 features nu nu 6.38 write dma fua ext (3dh) 48bit lba the write dma fua ext command provides the same function as the write dma ext command except that regardless of whether write caching in the device is enabled or not, t he user data shall be written to the media before ending status for the command is reported. 6.39 write fpdma queued (61h) (if ncq feature set supported) this command is mandatory for devices implementing the ncq feature set (see feature set reference). this c ommand causes data to be transferred from the host to the device. when the forced unit access (fua) bit is set to one regardless of whether volatile and/or non - volatile write caching in the device is enabled or not, the user data shall be written to non - vo latile media before command completion is reported. when the fua bit is cleared to zero the device may return command completion before the data is written to the media. table 64 : write fpdma queued register write previous current task file register 15:8 7 6 5 4 3 2 1 0 command - 61h drive/head - fua 1 nu 0 nu cylinder hi lba (47:40) lba23:16 cylinder low lba (39:32) lba15:8 sector num lba (31:24) lba7:0 sector count nu ncq tag nu features the number of logical sectors to be transferred. a value of 0000h indicates that 65,536 logical sectors are to be transferred. for further details see the ata8 specification. 6.40 write multiple command (c5h) this command is similar to the write sectors command. the drive sets bsy within 400ns of accepting the command. interrupts are not presented on each sector but on the transfer of a block which contains the number of sectors defined by set multiple. command execution is identical to the write sectors operation except that the number of secto rs defined by the set multiple command is transferred without intervening interrupts. drq qualification of the transfer is required only at the start of the data block, not on each sector. the block count of sectors to be transferred without intervening in terrupts is programmed by the set multiple mode command, which must be executed prior to the write multiple command. when the write multiple command is issued, the sector count register contains the number of sectors (not the number of blocks or the block count) requested. if the number of requested sectors is not evenly divisible by the sector/block, as many full blocks as possible are transferred, followed by a final, partial block transfer. the partial block transfer is for n sectors, where: n = (sector count) module (block count). if the write multiple command is attempted before the set multiple mode command has been executed or when write multiple commands are disabled, the write multiple operation will be rejected with an aborted command error. errors encountered during write multiple commands are posted after the attempted writes of the block or partial block transferred. the write command ends with the sector in error, even if it is in the middle of a block. subsequent blocks are not transferred in t he event of an error. interrupts are generated when drq is set at the beginning of each block or partial block.
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 39 of 53 the command block registers contain the cylinder, head and sector number of the sector where the error occurred and the sector count register co ntains the residual number of sectors that need to be transferred for successful completion of the command. for example, each block has 4 sectors, a request for 8 sectors is issued and an error occurs on the third sector. the sector count register contains 6 and the address is that of the third sector. note: the current revision of the d rive only supports a block count of 1 as indicated in the identify drive command information. the write multiple command is provided for compatibility with future products w hich may support a larger block count. table 65 defines the write multiple command byte sequence. table 65 : write multiple task file register 7 6 5 4 3 2 1 0 command c 5 h drive/head 1 lba 1 d head (lba 27 - 24) cylinder hi cylinder high (lba23 - 16) cylinder low cylinder low (lba15 - 8) sector num sector number (lba7 - 0) sector count sector count features nu 6.41 write multiple ext (39h) 48bit lba the write multiple ext command is similar to the write multiple command, except that lba addressing is mandatory, the lba associated with this command is a 48 bit address, and the sector count field is a 16 bit field. the second (lower in the table) part of each 16 bit field can be written to or read fr om by setting the hob bit of the device control register to 1 before reading or writing the field. reading or writing the task file shall reset the hoa bit to 0. error handling is similar to the write multiple command, except that the error sector address is always returned as a 48 bit address, and the sector count is a 16 bit number. table 66 : write multiple ext register write previous current task file register 15:8 7 6 5 4 3 2 1 0 command - 39h drive/head - 1 1 1 drive rese rved lba high lba (47:40) lba (23:16) lba mid lba (39:32) lba (15:8) lba low lba (31:24) lba (7:0) sector count 15:8 7:0 features nu nu 6.42 write multiple fua ext (ceh) 48bit lba the write multiple fua ext command provides the same function as the write multiple ext command except that regardless of whether write caching in the device is enabled or not, the user data shall be written to the media before ending status for the command is reported. 6.43 write sector(s) (30h ) this command writes from 1 to 256 sect ors as specified in the sector count register. a sector count of zero requests 256 sectors. the transfer begins at the sector specified in the sector number register. when this command is accepted, the drive sets bsy, sets drq and clears bsy, then waits fo r the host to fill the sector buffer with the data to be written. no interrupt is generated to start the first host transfer operation. no data should be transferred by the host until bsy has been cleared by the host. for multiple sectors, after the first sector of data is in the buffer, bsy will be set and drq will be cleared. after the next buffer is ready for data, bsy is cleared, drq is set and an interrupt is generated. when the final sector of data is transferred, bsy is set and drq is cleared. it wil l remain in this state until the command is completed at which time bsy is cleared and an interrupt is generated. if an error occurs during a write of more than one sector, writing terminates at the sector where the error occurred. the command block regist ers contain the cylinder, head and sector number of the sector where the error occurred. the host may then read the command block to determine what error has occurred, and on which sector. table 67 defines the writ e sector(s) command byte sequence.
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 40 of 53 table 67 : write sector(s) task file register 7 6 5 4 3 2 1 0 command 30h drive/head 1 lba 1 d head (lba 27 - 24) cylinder hi cylinder high (lba23 - 16) cylinder low cylinder low (lba15 - 8) sector num sector number (lba7 - 0) sector count sector count features nu 6.44 write sector(s) ext (34h) 48bit lba this is the 48 - bit address version of the write sector(s) command. this command writes from 1 to 65,536 sectors as specified in the sector count regist er. a sector count value of 0000h requests 65,536 sectors. the device shall interrupt for each drq block transferred. if an error occurs during a write of more than one sector, writing terminates at the sector where the error occurs. the command block reg isters contain the 48 - bit lba of the sector where the error occurred. the host may then read the command block to determine what error has occurred, and on which sector. table 68 : write sector(s) ext register write previous current task file register 15:8 7 6 5 4 3 2 1 0 command - 34h drive/head - 1 1 1 drive reserved lba high lba (47:40) lba (23:16) lba mid lba (39:32) lba (15:8) lba low lba (31:24) lba (7:0) sector count 15:8 7:0 features nu nu
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 41 of 53 7 s.m.a.r.t . functionalit y the ssd support s the following smart commands, determined by the feature register value. table 69 : s.m.a.r.t. features supported feature operation d0h smart read data d1h smart read attribute thresholds (obsolete) d2h smart e nable/disable autosave d3h smart save attribute values (obsolete) d4h smart execute off - line immediate d8h smart enable operations d9h smart disable operations dah smart return status smart commands with feature register values not mentioned in the above table are not supported, and will be aborted. 7.1 s.m.a.r.t. enable / disable operations this command enables / disables access to the smart capabilities of the ssd . the state of smart (enabled or disabled) is preserved across power cycles. table 70 : s.m.a.r.t. enable / disable operations (feature d8h / d9h) task file register 7 6 5 4 3 2 1 0 command b0h drive/head 1 1 1 d nu cylinder hi c2h cylinder low 4fh sector num nu sector count nu features d8h / d9h 7.2 s.m.a.r.t. r eturn status this command checks the device reliability status. if a threshold exceeded condition exists for either the spare block count attribute (typical 25% of original spare blocks) or the erase count attribute (typical 1%) , the device will set the cy linder low register to f4h and the cylinder high register to 2ch. if no threshold exceeded condition exists, the device will set the cylinder low register to 4fh and the cylinder high register to c2h. table 71 : s.m.a.r.t. return st atus (feature d a h) task file register 7 6 5 4 3 2 1 0 command b0h drive/head 1 1 1 d nu cylinder hi c2h cylinder low 4fh sector num nu sector count nu features dah
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 42 of 53 7.3 s.m.a.r.t. enable / disable attribute autosave this command is effectively a no - op eration as the data for the smart functionality is always available and kept current in the ssd . table 72 : s.m.a.r.t. enable / disable attribute autosave (feature d2h) task file register 7 6 5 4 3 2 1 0 command b0h drive/head 1 1 1 d nu cylinder hi c2h cylinder low 4fh sector num nu sector count f1h or 00h (enable or disable) features d2h 7.4 s.m.a.r.t. save attribute values this command causes the device to immediately save any updated attribute values to the devices non - vol atile memory regardless of the state of the attribute autosave timer. upon receipt of this command from the host, the device sets bsy, writes any updated attribute values to non - volatile memory, clears bsy, and asserts intrq. this command is effectively a no - operation command. table 73 : s.m.a.r.t. save attribute values (feature d 3 h) task file register 7 6 5 4 3 2 1 0 command b0h drive/head 1 1 1 d nu cylinder hi c2h cylinder low 4fh sector num n u sector count nu features d 3 h 7.5 s.m.a.r.t. execute off - line immediate this command is effectively a no - operation as the data for the smart functionality is always available and kept current in the ssd . table 74 : s.m.a.r.t. execute off - line immediate (feature d 4h) task file register 7 6 5 4 3 2 1 0 command b0h drive/head 1 1 1 d nu cylinder hi c2h cylinder low 4fh sector num nu (subcommand specific) sector count nu features d4h 7.6 s.m.a.r.t. read data this command returns one sector of smart data. table 75 : s.m.a.r.t. read data (feature d0h) task file register 7 6 5 4 3 2 1 0 command b0h drive/head 1 1 1 d nu cylinder hi c2h cylinder low 4fh sector num nu sector count nu features d0h
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 43 of 53 the data structure returned is: table 76 : s.m.a.r.t. data structure offset typ. value description 0..1 0100h smart structure version 2..361 30x12bytes * attribute entries 1 to 30 (12 bytes each , little endian, see below ) 362 00 h off - line data collection status (no off - line data collection) 363 00h self - test execution status byte (self - test completed) 364..365 00 00h total time in seconds to complete off - line data collection 366 00h vendor specific 367 00h off - line data collection capability (no off - line data collect ion) 368..369 0200 h smart capabilities 370 00h error logging capability (no error logging) 371 00h vendor specific 372 0 1 h short self - test routine recommended polling time 373 0 1 h extended self - test routine recommended polling time 374 00h conveyance self - test routine recommended polling time 375..385 00h reserved 386..395 xx firmware version/date code (e.g. 396397 406 50 407415 418419 420423 510
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 44 of 53 7.6.1 att r ibute entries this table shows the structure of the s.m.a.r.t. attribute entries in the s.m.a.r.t. data structure. table 78 : attribute entry offset value description 0 xx h attribute id C 7.6.2 s.m.a.r.t. read attribute thresholds this comm and returns one sector of smart attribute thresholds. table 79 : s.m.a.r.t. read data thresholds (feature d1h) task file register 7 6 5 4 3 2 1 0 command b0h drive/head 1 1 1 d nu cylinder hi c2h cylinder low 4fh sector num nu sector count nu features d1h the data structure returned is: table 80 : s.m.a.r.t. data threshold structure offset value description 0..1 0 1 0 0 h smart structure version 2..361 attribute threshold entries 1 to 30 (12 bytes each ) 362..379 00h reserved 380..510 00h - 511 xxh data structure checksum this table shows the structure of the s.m.a.r.t. attribute entries in the s.m.a.r.t. data structure. table 81 : attribute threshold entry offset value des cription 0 xxh attribute id C
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 45 of 53 8 package mechanical the ssd has 4 screw holes at the side and 4 at the bottom side. figure 5 : housing dimensions dimension mm inches height a1 9.2 0.3 62 width a2 69.85 2.752 length a3 100.1 0 3.94 hole height a4 3.0 0.118 a7 n/a n/a a8 0.5 0.02 hole position a9 4.1 0.16 hole dista nce a10 61.7 2.43 a14 0.05 0.02 screw head diameter a15 6.0 0.315 hole depth bottom a16 min 5.0 0.2 hole depth side a17 min 5.0 0.2 1. hole a18 14.0 0.551 4 . hole a19 90.6 3.567 1. hole a20 14.0 0.551 4. hole a21 90.6 3.567 +height tolerance t1 0 .2 0.005 - height tolerance t2 0.2 0.01 width tolerance t3 0.2 0.01
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 46 of 53 figure 6 : connector location (sata and feature connector) bottom side top side
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 47 of 53 9 ce declaration of conformity we manufacturer: swissbit ag industriestrasse 4 ch - 9552 b ronschhofen switzerland declare under our sole responsibility that the product product type: solid state drive (ssd) brand name: swissmemory?
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 48 of 53 10 r ohs and weee update from swissbit dear valued customer, we at swissbit place great value on the environment and thus pay close atte n tion to the diverse aspects of manufacturing environmentally and health friendly products. the european parliament and the cou n cil of the european union have published two directives defining a european standard for environmental prote c tion. this states that solid state drives must comply with both directives in order for them to be sold on the eur o pean market: ? rohs C restric tion of hazardous substances ? weee C waste electrical and electronic equipment swissbit would like to take this opportunity to inform our customers about the measures we have impl e mented to adapt all our products to the european norms. what is the weee di rective (2002/96/ec)? the directive covers the following points: ? prevention of weee ? recovery, recycling and other measures leading to a minimization of was t age of electronic and electrical equipment ? improvement in the quality of environmental performance o f all operators i n volved in the eee life cycle, as well as measures to incorporate those i n volved at the eee waste disposal points what are the key elements? the weee directive covers the following responsibilities on the part of producers: producers must draft a disposal or recovery scheme to dispose of eee co r rectly. producers must be registered as producers in the country in which they distri b ute the goods. they must also supply and publish information about the eee categories. producers are obliged to finance the collection, treatment and disposal of weee. inclusion of weee logos on devices in reference to the directive, the weee logo must be printed directly on all d e vices that have sufficient space. ?in exceptional cases where this is necessary becau se of the size of the product, the symbol of the weee directive shall be printed on the packaging, on the instru c tions of use and on the warranty? (weee directive 2002/96/ec) when does the weee directive take effect? the directive came into effect interna tionally on 13 august, 2005. what is rohs (2002/95/ec)? the goals of the directive are to: ? place less of a burden on human health and to protect the environment by restricting the use of hazardous substances in new electrical and electronic d e vices ? to sup port the weee directive (see above) rohs enforces the restriction of the following 6 hazardous substances in electronic and electrical d e vices: ? lead (pb) C no more than 0.1% by weight in homogeneous m a terials ? mercury (hg) C no more than 0.1% by weight in homogeneous materials ? cadmium (cd) C no more than 0.01% by weight in homogeneous mater i als ? chromium (cr6+) C no more than 0.1% by weight in homogeneous mat e rials ? pbb, pbde C no more than 0.1% by weight in homogeneous materials
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 49 of 53 swissbit is obliged to minim ize the hazardous substances in the products. according to part of the directive, manufacturers are obliged to make a self - declaration for all devices with rohs. swissbit carried out intensive tests to comply with the self - declaration. we have also already taken steps to have the analyses of the individual components guaranteed by third - party co m panies. swissbit carried out the following steps during the year with the goal of offering our custo m ers products that are fully compliant with the rohs directive . ? preparing all far - reaching directives, logistical enhancements and alternatives regar d ing the full understanding and introduction of the rohs directives standards ? checking the components and raw materials: o replacing non - rohs - compliant components an d raw materials in the supply chain o cooperating closely with suppliers regarding the certification of all components and raw m a terials used by swissbit ? modifying the manufacturing processes and procedures o successfully adapting and optimizing the new manag ement - free integration pro c ess in the supply chain o updating existing production procedures and introducing the new procedures to support the integration process and the sorting of m a terials ? carrying out the quality process o performing detailed function and safety tests to ensure the continuous high quality of the swissbit pro d uct line when does the rohs directive take effect? as of 1 july, 2006, only new electrical and electronic devices with approved quantities of rohs will be put on the market. when will swissbit be offering rohs - approved products? swissbits rohs - approved products are available now. please contact your swissbit contact person to find out more about exchanging your existing products for rohs - compliant d e vices. for your attention we u nderstand that packaging and accessories are not eee mat e rial and are therefore not subject to the weee or rohs directives. contact details: swissbit ag industri estrasse 4 ch - 9552 bronschhofen tel: +41 71 913 03 03 C fax: +41 71 913 03 15 e - mail: industrial@swissbit.com C website: www.swissbit.com
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 50 of 53 11 part number decoder s f s a 256 g q 1 b j a to - i - n u - 2 1 6 - std 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 manuf. option memory type. configuration product type manuf. c ode: flash mode density manuf. code: flash package platform temp. option product generation flash vend or code memory organization number of flash chips technology 11.1 manufacturer swissbit code s 11.2 memory type flash f 11.3 product type sata - interface sa 11.4 density 16 gbyte 016g 32 gbyte 032g 64 gbyte 064g 128 gbyte 128g 256 gbyte 256g 512 gbyte 512 g 11.5 plat form ssd 2.5 11.6 product generation 11.7 memory organization x8 b 11.8 technology x - 5 platform j 11.9 number of flash chip 4 flash 4 8 flash 8 16 flash a 11.10 flash code toshiba to
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 51 of 53 11.11 temp. option industrial temp. range - 40c C 85c i standard temp . range 0c C 7 0c c 11.12 die classification x - 500 slc x - 5 5 em - mlc mono (single die package) m g ddp (dual die package) d l qdp (quad die package) q h odp (octal die package) n o 11.13 pin mode tsop b ga single nce & r/nb s a dual nce & dual r/nb t b quad nce & quad r/nb u c 11.14 drive configuration xyz x ? ? ? ? max. transfer mode max pio mode z udma6 (mdma2, pio4) 6 11.15 option swissbit / standard std standard with conformal coating stc
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 52 of 53 12 swissbit x - 500 ssd marking specification 12.1 top view connector side 12.1.1 label content defined in the qr - code: sap 6 digit - assylot/id 20 digit - mfg date 4 - digit ex ample: 601234 - 00006012345600000007 - 0513 part number lot code number - id manufacturing date code (cw/yy) m ade in germany qr - code sap number serial ata logo china rohs logo product / series es/qs placeholder
swissbit ag swissbit reserves the right to change products or specifications without notice. revision: 1. 0 2 industriestrasse 4 - 8 ch - 9552 bronschhofen www.swissbit.com x - 500_data_sheet_sa - qxbj_re v102.doc switzerland industrial@swissbit.com page 53 of 53 13 revision history table 82 : document revision history date revision revision details 16 - august - 2013 1.00 first release 10 - october - 201 3 1.0 1 add video stream workload tbw 07 - november - 2013 1.0 2 feature connecto r partnumber corrected disclaimer: no part of this document may be copied or reproduced in any form or by any means, or transferred to any third party, without the prior written consent of an authorized representative of swissbit ag ( swissbit ). the information in t his document is subject to change without notice. swissbit assumes no responsibility for any errors or omissions that may appear in this document, and disclaims responsibility for any consequences resulting from the use of the information set forth herein. swissbit makes no commitments to update or to keep current information contained in this document. the products listed in this document are not suitable for use in applications such as, but not limited to, aircraft control systems, aerospace equipment, su bmarine cables, nuclear reactor control systems and life support systems. moreover, swissbit does not recommend or approve the use of any of its products in life support devices or systems or in any application where failure could result in injury or death . if a customer wishes to use swissbit products in applications not intended by swissbit , said customer must contact an authorized swissbit representative to determine swissbit willingness to support a given application. the information set forth in this d ocument does not convey any license under the copyrights, patent rights, trademarks or other intellectual property rights claimed and owned by swissbit . the information set forth in this document is considered to be proprietary and confidential propert y owned by swissbit . all products sold by swissbit are covered by the provisions appearing in swissbit s terms and conditions of sale only, including the limitations of liability, warranty and infringement provisions. swissbit makes no warranties of any k ind, express, statutory, implied or otherwise, regarding information set forth herein or regarding the freedom of the described products from intellectual property infringement, and expressly disclaims any such warranties including without limitation any e xpress, statutory or implied warranties of merchantability or fitness for a particular purpose. ?201 3 swissbit ag all rights reserved.

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