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LTC2269 1 2269f typical application description 16-bit, 20msps low noise adc the ltc ? 2269 is a sampling 16-bit a/d converter designed for digitizing high frequency, wide dynamic range signals. it is perfect for demanding communications applications with ac performance that includes 84.1db snr and 99db spurious free dynamic range (sfdr). dc specs include 1lsb inl (typ), 0.2lsb dnl (typ) and no missing codes over temperature. the transition noise is 1.44lsb rms . the digital outputs can be either full rate cmos, double data rate cmos, or double data rate lvds. a separate output power supply allows the cmos output swing to range from 1.2v to 1.8v. the enc + and enc C inputs may be driven differentially or single-ended with a sine wave, pecl, lvds, ttl, or cmos inputs. an optional clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. integral non-linearity (inl) features applications n 84.1db snr (46v rms input referred noise) n 99db sfdr n 2.3lsb inl(maximum) n low power: 88mw n single 1.8v supply n cmos, ddr cmos, or ddr lvds outputs n selectable input ranges: 1v p-p to 2.1v p-p n 200mhz full power bandwidth s/h n shutdown and nap modes n serial spi port for configuration n pin compatible with ltc2160:16-bit, 25msps, 45mw n 48-lead (7mm 7mm) qfn package n low power instrumentation n software defined radios n portable medical imaging n multichannel data acquisition output code 0 C2.0 C1.5 C1.0 inl error (lsb) C0.5 0.5 0.0 1.0 1.5 2.0 16384 32768 49152 65536 2269 ta02 s/h output drivers 16-bit adc core clock control d15 t t t d0 20mhz clock analog input 2269 ta01 cmos ddr cmos or ddr lvds outputs 1.8v v dd 1.8v ov dd gnd ognd
LTC2269 2 2269f absolute maximum ratings supply voltages (v dd , o vdd ) ....................... C0.3v to 2v analog input voltage (a in + , a in C , par/ ser , sense) (note 3) ................................... C0.3v to (v dd + 0.2v) digital input voltage (enc + , enc C , cs , sdi, sck) (note 4) ................................................ C0.3v to 3.9v sdo (note 4) ............................................. C0.3v to 3.9v (notes 1, 2) full rate cmos output mode double data rate cmos output mode top view 49 gnd uk package 48-lead (7mm s 7mm) plastic qfn v cm 1 a in + 2 a in C 3 gnd 4 refh 5 refl 6 refh 7 refl 8 par/ ser 9 gnd 10 gnd 11 v dd 12 36 d11 35 d10 34 d9 33 d8 32 ov dd 31 ognd 30 clkout + 29 clkout C 28 d7 27 d6 26 d5 25 d4 48 v dd 47 v dd 46 sense 45 v ref 44 sdo 43 gnd 42 of 41 dnc 40 d15 39 d14 38 d13 37 d12 v dd 13 gnd 14 enc + 15 enc C 16 cs 17 sck 18 sdi 19 gnd 20 d0 21 d1 22 d2 23 d3 24 t jmax = 150c, ja = 29c/w exposed pad (pin 49) is gnd, must be soldered to pcb top view 49 gnd uk package 48-lead (7mm s 7mm) plastic qfn v cm 1 a in + 2 a in C 3 gnd 4 refh 5 refl 6 refh 7 refl 8 par/ ser 9 gnd 10 gnd 11 v dd 12 36 d10_11 35 dnc 34 d8_9 33 dnc 32 ov dd 31 ognd 30 clkout + 29 clkout C 28 d6_7 27 dnc 26 d4_5 25 dnc 48 v dd 47 v dd 46 sense 45 v ref 44 sdo 43 gnd 42 of 41 dnc 40 d14_15 39 dnc 38 d12_13 37 dnc v dd 13 gnd 14 enc + 15 enc C 16 cs 17 sck 18 sdi 19 gnd 20 dnc 21 d0_1 22 dnc 23 d2_3 24 t jmax = 150c, ja = 29c/w exposed pad (pin 49) is gnd, must be soldered to pcb pin configuration digital output voltage ................ C0.3v to (ov dd + 0.3v) operating temperature range LTC2269c ................................................ 0c to 70c LTC2269i .............................................C40c to 85c storage temperature range .................. C65c to 150c LTC2269 3 2269f order information lead free finish tape and reel part marking* package description temperature range LTC2269cuk#pbf LTC2269cuk#trpbf LTC2269uk 48-lead (7mm 7mm) plastic qfn 0c to 70c LTC2269iuk#pbf LTC2269iuk#trpbf LTC2269uk 48-lead (7mm 7mm) plastic qfn C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ pin configuration double data rate lvds output mode top view 49 gnd uk package 48-lead (7mm = 7mm) plastic qfn v cm 1 a in + 2 a in C 3 gnd 4 refh 5 refl 6 refh 7 refl 8 par/ ser 9 gnd 10 gnd 11 v dd 12 36 d10_11 + 35 d10_11 C 34 d8_9 + 33 d8_9 C 32 ov dd 31 ognd 30 clkout + 29 clkout C 28 d6_7 + 27 d6_7C 26 d4_5 + 25 d4_5C 48 v dd 47 v dd 46 sense 45 v ref 44 sdo 43 gnd 42 of + 41 of C 40 d14_15 + 39 d14_15 C 38 d12_13 + 37 d12_13 C v dd 13 gnd 14 enc + 15 enc C 16 cs 17 sck 18 sdi 19 gnd 20 d0_1 C 21 d0_1 + 22 d2_3 C 23 d2_3 + 24 t jmax = 150c, ja = 29c/w exposed pad (pin 49) is gnd, must be soldered to pcb LTC2269 4 2269f converter characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. parameter conditions min typ max units resolution (no missing codes) l 16 bits integral linearity error differential analog input (note 6) l C2.3 1 2.3 lsb differential linearity error differential analog input l C0.8 0.2 0.8 lsb offset error (note 7) l C7 1.3 7 mv gain error internal reference external reference l C1.5 1.2 C0.2 1.1 %fs %fs offset drift 10 v/c full-scale drift internal reference external reference 30 10 ppm/c ppm/c transition noise external reference 1.44 lsb rms analog input the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 1.7v < v dd < 1.9v l 1 to 2.1 v p-p v in(cm) analog input common mode (a in + + a in C )/2 differential analog input (note 8) l 0.65 v cm v cm + 200mv v v sense external voltage reference applied to sense external reference mode l 0.625 1.250 1.300 v i incm analog input common mode current per pin, 20msps 32 a i in1 analog input leakage current (no encode) 0 < a in + , a in C < v dd l C1 1 a i in2 par/ ser input leakage current 0 < par/ ser < v dd l C1 1 a i in3 sense input leakage current 0.625 < sense < 1.3v l C2 2 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay jitter single-ended encode differential encode 85 100 fs rms fs rms cmrr analog input common mode rejection ratio 80 db bw-3b full power bandwidth figure 5 test circuit 200 mhz dynamic accuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (note 5) symbol p arameter conditions min typ max units snr signal-to-noise ratio 1.4mhz input 5mhz input 30mhz input 70mhz input l 82.1 84.1 84.1 83.8 82.7 dbfs dbfs dbfs dbfs sfdr spurious free dynamic range 2nd harmonic 1.4mhz input 5mhz input 30mhz input 70mhz input l 90 99 98 98 90 dbfs dbfs dbfs dbfs LTC2269 5 2269f dynamic accuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (note 5) symbol p arameter conditions min typ max units sfdr spurious free dynamic range 3rd harmonic 1.4mhz input 5mhz input 30mhz input 70mhz input l 92 99 98 98 96 dbfs dbfs dbfs dbfs sfdr spurious free dynamic range 4th harmonic or higher 1.4mhz input 5mhz input 30mhz input 70mhz input l 95 110 110 105 100 dbfs dbfs dbfs dbfs s/(n+d) signal-to-noise plus distortion ratio 1.4mhz input 5mhz input 30mhz input 70mhz input l 81.7 83.9 83.9 83.7 82 dbfs dbfs dbfs dbfs parameter conditions min typ max units v cm output voltage i out = 0 l 0.5?v dd C 25mv 0.5?v dd 0.5?v dd + 25mv v v cm output temperature drift 25 ppm/c v cm output resistance C600a < i out < 1ma 4 v ref output voltage i out = 0 l 1.230 1.250 1.270 v v ref output temperature drift 25 ppm/c v ref output resistance C400a < i out < 1ma 7 v ref line regulation 1.7v < v dd < 1.9v 0.6 mv/v internal reference characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) digital inputs and outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) differential encode mode (enc C not tied to gnd) v id differential input voltage (note 8) l 0.2 v v icm common mode input voltage internally set externally set (note 8) l 1.1 1.2 1.6 v v v in input voltage range enc + , enc C to gnd l 0.2 3.6 v r in input resistance (see figure 10) 10 k c in input capacitance (note 8) 3.5 pf single-ended encode mode (enc C tied to gnd) v ih high level input voltage v dd = 1.8v l 1.2 v v il low level input voltage v dd = 1.8v l 0.6 v v in input voltage range enc + to gnd l 0 3.6 v r in input resistance (see figure 11) 30 k c in input capacitance (note 8) 3.5 pf LTC2269 6 2269f digital inputs and outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units digital inputs ( cs, sdi, sck in serial or parallel programming mode. sdo in parallel programming mode) v ih high level input voltage v dd = 1.8v l 1.3 v v il low level input voltage v dd = 1.8v l 0.6 v i in input current v in = 0v to 3.6v l C10 10 a c in input capacitance (note 8) 3 pf sdo output (serial programming mode. open drain output. requires 2k pull-up resistor if sdo is used) r ol logic low output resistance to gnd v dd = 1.8v, sdo = 0v 200 i oh logic high output leakage current sdo = 0v to 3.6v l C10 10 a c out output capacitance (note 8) 3 pf digital data outputs (cmos modes: full data rate and double data rate) ov dd = 1.8v v oh high level output voltage i o = C500a l 1.750 1.790 v v ol low level output voltage i o = 500a l 0.010 0.050 v ov dd = 1.5v v oh high level output voltage i o = C500a 1.488 v v ol low level output voltage i o = 500a 0.010 v ov dd = 1.2v v oh high level output voltage i o = C500a 1.185 v v ol low level output voltage i o = 500a 0.010 v digital data outputs (lvds mode) v od differential output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l 247 350 175 454 mv mv v os common mode output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l 1.125 1.250 1.250 1.375 v v r term on-chip termination resistance termination enabled, ov dd = 1.8v 100 symbol parameter conditions min typ max units cmos output modes: full data rate and double data rate v dd analog supply voltage (note 10) l 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.1 1.8 1.9 v i vdd analog supply current dc input sine wave input l 48.9 49.1 54.4 ma ma i ovdd digital supply current sine wave input, ov dd =1.2v 1 ma p diss power dissipation dc input sine wave input, ov dd =1.2v l 88 88 98 mw mw lvds output mode v dd analog supply voltage (note 10) l 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.7 1.8 1.9 v power requirements the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) LTC2269 7 2269f symbol parameter conditions min typ max units i vdd analog supply current sine wave input, 1.75ma mode sine wave input, 3.5ma mode l 50 50.6 56.2 ma ma i ovdd digital supply current (ov dd = 1.8v) sine wave input, 1.75ma mode sine wave input, 3.5ma mode l 21.1 40.9 46 ma ma p diss power dissipation sine wave input, 1.75ma mode sine wave input, 3.5ma mode l 127 161 184 mw mw all output modes p sleep sleep mode power 0.5 mw p nap nap mode power 10 mw p diffclk power increase with differential encode mode enabled (no increase for nap or sleep modes) 20 mw power requirements the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units f s sampling frequency (note 10) l 12 0m h z t l enc low time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 23.5 2 25 25 500 500 ns ns t h enc high time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 23.5 2 25 25 500 500 ns ns t ap sample-and-hold acquisition delay time 0ns symbol parameter conditions min typ max units digital data outputs (cmos modes: full data rate and double data rate) t d enc to data delay c l = 5pf (note 8) l 1.1 1.7 3.1 ns t c enc to clkout delay c l = 5pf (note 8) l 1 1.4 2.6 ns t skew data to clkout skew t d C t c (note 8) l 0 0.3 0.6 ns pipeline latency full data rate mode double data rate mode 6 6.5 6 6.5 cycles cycles digital data outputs (lvds mode) t d enc to data delay c l = 5pf (note 8) l 1.1 1.8 3.2 ns t c enc to clkout delay c l = 5pf (note 8) l 1 1.5 2.7 ns t skew data to clkout skew t d C t c (note 8) l 0 0.3 0.6 ns pipeline latency 6.5 6.5 cycles spi port timing (note 8) t sck sck period write mode readback mode, c sdo = 20pf, r pullup = 2k l l 40 250 ns ns t s cs to sck setup time l 5n s t h sck to cs setup time l 5n s t ds sdi setup time l 5n s t dh sdi hold time l 5n s t do sck falling to sdo valid readback mode, c sdo = 20pf, r pullup = 2k l 125 ns LTC2269 8 2269f electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. note 5: v dd = ov dd = 1.8v, f sample = 20mhz l vds outputs, differential enc + /enc C = 2v p-p sine wave, input range = 2.1v p-p with differential drive, unless otherwise noted. note 6: integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 7: offset error is the offset voltage measured from C0.5 lsb when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2s complement output mode. note 8: guaranteed by design, not subject to test. note 9: v dd = 1.8v, f sample = 20mhz cmos outputs, enc + = single-ended 1.8v square wave, enc C = 0v, input range = 2.1v p-p with differential drive, 5pf load on each digital output unless otherwise noted. note 10: recommended operating conditions. timing diagrams full-rate cmos output mode timing all outputs are single-ended and have cmos levels t h t d t c t l n C 6 n C 5 n C 4 n C 3 n C 2 t ap n + 1 n + 2 n + 4 n + 3 n analog input enc C enc + clkout + clkout C d0Cd15, of 2269 td01 LTC2269 9 2269f double data rate cmos output mode timing all outputs are single-ended and have cmos levels timing diagrams double data rate lvds output mode timing all outputs are differential and have lvds levels t h t d t t t t d t c t c t l of n-6 of n-5 of n-4 of n-3 d0 n-6 d1 n-6 d0 n-5 d1 n-5 d0 n-4 d1 n-4 d0 n-3 d1 n-3 d14 n-6 d15 n-6 d14 n-5 d15 n-5 d14 n-4 d15 n-4 d14 n-3 d15 n-3 t ap n + 1 n + 2 n + 4 n + 3 n analog input enc C enc + d0_1 d14_15 clkout + clkout C of 2269 td02 t h t d t d t c t c t l of n-6 of n-5 of n-4 of n-3 d0 n-6 d1 n-6 d0 n-5 d1 n-5 d0 n-4 d1 n-4 d0 n-3 d1 n-3 d14 n-6 d15 n-6 d14 n-5 d15 n-5 d14 n-4 d15 n-4 d14 n-3 d15 n-3 t ap n + 1 n + 2 n + 4 n + 3 n analog input enc C enc + d0_1 + d0_1 C d14_15 + d14_15 C clkout + clkout C of + of C 2269 td03 t t t LTC2269 10 2269f timing diagrams a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/w sdo high impedance spi port timing (readback mode) spi port timing (write mode) t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 2269 td04 cs sck sdi r/w sdo high impedance LTC2269 11 2269f typical performance characteristics integral non-linearity (inl) differential non-linearity (dnl) 64k point fft, f in = 1.4mhz, C1dbfs, 20msps 64k point fft, f in = 5.1mhz, C1dbfs, 20msps 64k point fft, f in = 10mhz, C1dbfs, 20msps 64k point fft, f in = 30.3mhz, C1dbfs, 20msps 64k point fft, f in = 70.3mhz, C1dbfs, 20msps 64k point 2-tone fft, f in = 14.8, 15.2mhz, C7dbfs, 20msps shorted input histogram output code 0 C2.0 C1.5 C1.0 inl error (lsb) C0.5 0.5 0.0 1.0 1.5 2.0 16384 32768 49152 65536 2269 g01 output code C1.0 C0.4 C0.2 C0.6 C0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 2269 g02 0 16384 32768 49152 65536 frequency (mhz) C100 C140 C120 C60 C80 amplitude (dbfs) C40 0 C20 2269 g03 0 2 6 410 8 frequency (mhz) C100 C140 C120 C60 C80 amplitude (dbfs) C40 C20 0 2269 g04 024 6 810 frequency (mhz) C100 C140 C120 C60 C80 amplitude (dbfs) C40 C20 0 2269 g05 0 2 86 41 0 frequency (mhz) C100 C120 C140 C60 C80 amplitude (dbfs) C40 C20 0 2269 g06 0 2 6 410 8 frequency (mhz) 0 C100 C120 C140 C60 C80 amplitude (dbfs) C40 C20 0 2 6 410 8 2269 g07 frequency (mhz) 0 C120 C140 C80 C100 amplitude (dbfs) C60 0 C20 C40 246810 2269 g08 output code n-6 10000 5000 0 40000 35000 30000 25000 20000 15000 count n-5 n-4 n-3 n-2 n-1 n+6 n+5 n+4 n+3 n+2 n+1 n 2269 g09 LTC2269 12 2269f typical performance characteristics sfdr vs input level, f in = 5mhz, 20msps snr vs sense, f in = 5mhz, C1dbfs sfdr vs analog input common mode, f in = 9.7mhz, 20msps, 2.1v range snr, sfdr vs sample rate, f in = 5mhz, C1dbfs i vdd vs sample rate, 5mhz, C1dbfs sine wave input i ovdd vs sample rate, 5mhz, C1dbfs sine wave input snr vs input frequency, C1dbfs, 20msps, 2.1v range 2nd, 3rd harmonic vs input frequency, C1dbfs, 20msps, 2.1v range 2nd, 3rd harmonic vs input frequency, C1dbfs, 20msps, 1.05v range 0 20 40 60 80 100 120 140 input frequency (mhz) 83 82 81 80 79 85 84 snr (dbfs) 2269 g10 single-ended encode differential encode 0 20 40 60 80 100 120 140 input frequency (mhz) 95 90 85 80 75 70 105 100 2nd and 3rd harmonic (dbfs) 2269 g11 2nd 3rd input frequency (mhz) 0 85 80 75 70 90 2nd and 3rd harmonic (dbfs) 95 105 100 20 40 60 80 100 120 140 2269 g12 2nd 3rd input level (dbfs) C80 40 60 50 80 70 130 120 110 100 90 sfdr (dbc and dbfs) C70 C40C50C60 0C10C20C30 2269 g13 dbfs dbc sense pin (v) 0.6 77 78 79 80 snr (dbfs) 81 82 85 84 83 0.80.7 1 1.21.1 0.9 1.3 2269 g16 80 85 sfdr (dbfs) 90 95 100 2269 g17 input common mode (v) 0.6 0.80.7 0.9 1.11 1.2 v dd 1.9v v dd 1.7v sample rate (msps) 0 80 90 snr, sfdr (dbfs) 100 110 10 51520 2269 g18 sfdr snr sample rate (msps) 0 45 40 50 55 i vdd (ma) 5 101520 2269 g14 3.5ma lvds outputs cmos outputs sample rate (msps) 0 0 10 40 30 20 i ovdd (ma) 5101520 2269 g15 3.5ma lvds 1.75ma lvds 1.8v cmos LTC2269 13 2269f pin functions (pins that are the same for all digital output modes) v cm (pin 1): common mode bias output. nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs. bypass to ground with a 1f ceramic capacitor. a in + (pin 2): positive differential analog input. a in C (pin 3): negative differential analog input. gnd (pins 4, 10, 11, 14, 20, 43, exposed pad pin 49): adc power ground. the exposed pad must be soldered to the pcb ground. refh (pins 5, 7): adc high reference. see the applica- tions information section for recommended bypassing circuits for refh and refl. refl (pins 6, 8): adc low reference. see the applications information section for recommended bypassing circuits for refh and refl. par/ ser (pin 9): programming mode selection pin. con- nect to ground to enable the serial programming mode. cs , sck, sdi, sdo become a serial interface that control the a/d operating modes. connect to v dd to enable the parallel programming mode where cs, sck, sdi, sdo become parallel logic inputs that control a reduced set of the a/d operating modes. par/ ser should be connected directly to ground or v dd and not be driven by a logic signal. v dd (pins 12, 13, 47, 48): analog power supply, 1.7v to 1.9v. bypass to ground with 0.1f ceramic capacitors. adjacent pins can share a bypass capacitor. enc + (pin 15): encode input. conversion starts on the rising edge. enc C (pin 16): encode complement input. conversion starts on the falling edge. tie to gnd for single-ended encode mode. cs (pin 17): serial interface chip select input. in serial programming mode (par/ ser = 0v), cs is the serial in- terface chip select input. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in the parallel programming mode (par/ ser = v dd ), cs controls the clock duty cycle stabilizer (see table 2). cs can be driven with 1.8v to 3.3v logic. sck (pin 18): serial interface clock input. in serial programming mode, (par/ ser = 0v), sck is the serial interface clock input. in the parallel programming mode (par/ ser = v dd ), sck controls the digital output mode (see table 2). sck can be driven with 1.8v to 3.3v logic. sdi (pin 19): serial interface data input. in serial program- ming mode, (par/ ser = 0v), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in the parallel program- ming mode (par/ ser = v dd ), sdi can be used together with sdo to power down the part (table 2). sdi can be driven with 1.8v to 3.3v logic. ognd (pin 31): output driver ground. must be shorted to the ground plane by a very low inductance path. use multiple vias close to the pin. ov dd (pin 32): output driver supply. bypass to ground with a 0.1f ceramic capacitor. sdo (pin 44): serial interface data output. in serial pro- gramming mode, (par/ ser = 0v), sdo is the optional serial interface data output. data on sdo is read back from the mode control registers and can be latched on the fall- ing edge of sck. sdo is an open-drain nmos output that requires an external 2k pull-up resistor to 1.8v C 3.3v. if read back from the mode control registers is not needed, the pull-up resistor is not necessary and sdo can be left unconnected. in the parallel programming mode (par/ ser = v dd ), sdo can be used together with sdi to power down the part (table 2). when used as an input, sdo can be driven with 1.8v to 3.3v logic through a 1k series resistor. v ref (pin 45): reference voltage output. bypass to ground with a 2.2f ceramic capacitor. the output voltage is nominally 1.25v. sense (pin 46): reference programming pin. connecting sense to v dd selects the internal reference and a 1.05v input range. connecting sense to ground selects the internal reference and a 0.525v input range. an external reference between 0.625v and 1.3v applied to sense selects an input range of 0.84 ? v sense . LTC2269 14 2269f pin functions full rate cmos output mode all pins below have cmos output levels (ognd to o vdd ) d0 to d15 (pins 21-28, 33-40): digital outputs. d15 is the msb. clkout C (pin 29): inverted version of clkout + . clkout + (pin 30): data output clock. the digital outputs normally transition at the same time as the falling edge of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. dnc (pin 41): do not connect this pin. of (pin 42): overflow/underflow digital output. of is high when an overflow or underflow has occurred. double data rate cmos output mode all pins below have cmos output levels (ognd to o vdd ) d0_1 to d14_15 (pins 22, 24, 26, 28, 34, 36, 38, 40): double data rate digital outputs. two data bits are mul- tiplexed onto each output pin. the even data bits (d0, d2, d4, d6, d8, d10, d12, d14) appear when clkout + is low. the odd data bits (d1, d3, d5, d7, d9, d11, d13, d15) appear when clkout + is high. dnc (pins 21, 23, 25, 27, 33, 35, 37, 39, 41): do not connect these pins. clkout C (pin 29): inverted version of clkout + . clkout + (pin 30): data output clock. the digital outputs normally transition at the same time as the falling and ris- ing edges of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. of (pin 42): overflow/underflow digital output. of is high when an overflow or underflow has occurred. double data rate lvds output mode all pins below have lvds output levels. the output current level is programmable. there is an optional internal 100 termination resistor between the pins of each lvds output pair. d0_1 C /d0_1 + to d14_15 C /d14_15 + (pins 21/22, 23/24, 25/26, 27/28, 33/34, 35/36, 37/38, 39/40): double data rate digital outputs. two data bits are multiplexed onto each differential output pair. the even data bits (d0, d2, d4, d6, d8, d10, d12, d14) appear when clkout + is low. the odd data bits (d1, d3, d5, d7, d9, d11, d13, d15) appear when clkout + is high. clkout C /clkout + (pins 39/40): data output clock. the digital outputs normally transition at the same time as the falling and rising edges of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. of C /of + (pins 41/42): overflow/underflow digital output. of + is high when an overflow or underflow has occurred. LTC2269 15 2269f functional block diagram diff ref amp ref buf 2.2f 1f 1f clock/duty cycle control range select 1.25v reference enc + refh refl enc C sdo cs ognd of ovdd d15 clkout C clkout + d0 2269 bd sense v ref 2.2f v cm 1f v dd /2 mode control registers output drivers sck par/ ser sdi t t t refl internal clock signals refh s/h analog input 16-bit adc core correction logic v dd gnd figure 1. functional block diagram LTC2269 16 2269f applications information figure 2. equivalent input circuit input drive circuits input filtering if possible, there should be an rc lowpass filter right at the analog inputs. this lowpass filter isolates the drive circuitry from the a/d sample-and-hold switching, and also limits wideband noise from the drive circuitry. figure 3 shows an example of an input rc filter. the rc component values should be chosen based on the applications input frequency. transformer coupled circuits figure 3 shows the analog input being driven by an rf transformer with a center-tapped secondary. the center tap is biased with v cm , setting the a/d input at its optimal dc level. at higher input frequencies a transmission line balun transformer (figures 4 through 5) has better bal- ance, resulting in lower a/d distortion. amplifier circuits figure 6 shows the analog input being driven by a high speed differential amplifier. the output of the amplifier is ac coupled to the a/d so the amplifiers output common mode voltage can be optimally set to minimize distortion. if dc coupling is necessary use a differential amplifier with an output common mode set by the LTC2269 v cm pin (figure 7). figure 3. analog input circuit using a transformer. recommended for input frequencies from 1mhz to 40mhz c sample 17pf r on 24 r on 24 v dd v dd LTC2269 a in + 2269 f02 c sample 17pf v dd a in C enc C enc + 1.2v 10k 1.2v 10k c parasitic 1.8pf c parasitic 1.8pf 10 10 25 25 25 25 50 a in + a in C 12pf 1f v cm LTC2269 analog input 0.1f t1 1:1 t1: ma/com mabaes0060 resistors, capacitors are 0402 package size 2269 f03 0.1f converter operation the LTC2269 is a low power, 16-bit, 20msps a/d converter that is powered by a single 1.8v supply. the analog inputs must be driven differentially. the encode input can be driven differentially or single-ended for lower power consumption. the digital outputs can be cmos, double data rate cmos (to halve the number of output lines), or double data rate lvds (to reduce digital noise in the system). many addi- tional features can be chosen by programming the mode control registers through a serial spi port. analog input the analog inputs are differential cmos sample-and-hold circuits (figure 2). the inputs should be driven differentially around a common mode voltage set by the v cm output pin, which is nominally v dd /2. for the 2.1v input range, the inputs should swing from v cm C 525mv to v cm + 525mv. there should be 180 phase difference between the inputs. LTC2269 17 2269f applications information figure 4. recommended front end circuit for input frequencies from 5mhz to 80mhz figure 5. recommended front end circuit for input frequencies above 80mhz figure 6. front end circuit using a high speed differential amplifier figure 7. dc-coupled amplifier 25 25 50 12 12 0.1f a in + a in C 8.2pf 1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1tl resistors, capacitors are 0402 package size 2269 f04 LTC2269 25 25 50 0.1f a in + a in C 1.8pf 1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1tl resistors, capacitors are 0402 package size 2269 f05 LTC2269 25 25 200 200 0.1f a in + a in C 12pf 1f v cm LTC2269 2269 f06 C + analog input high speed differential amplifier 0.1f 12pf 25 25 a in + a in C 25pf 1f v cm LTC2269 2269 f07 C + analog input 25pf cm LTC2269 18 2269f applications information figure 8a. reference circuit v ref refh refh sense c1 tie to v dd for 2.1v range; tie to gnd for 1.05v range; 3 " / ( & |