december 2011 ?2011 fairchild semiconductor corporation FDMC86116LZ rev.c www.fairchildsemi.com 1 FDMC86116LZ n-channel power trench ? mosfet FDMC86116LZ n-channel power trench ? mosfet 100 v, 7.5 a, 103 m features ? max r ds(on) = 103 m at v gs = 10 v, i d = 3.3 a ? max r ds(on) = 153 m at v gs = 4.5 v, i d = 2.7 a ? hbm esd protection level > 3 kv typical (note 4) ? 100% uil tested ? rohs compliant general description this n-channel logic level mosfets are produced using fairchild semiconductor?s advanced power trench ? process that has been special tailored to minimize the on-state resistance and yet maintain superior switching performance. g-s zener has been added to enhance esd voltage level. application ? dc - dc conversion d d d d s s s g 1 2 3 4 5 d d d d g s s s bottom top mlp 3.3x3.3 6 7 8 mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 100 v v gs gate to source voltage 20 v i d drain current -continuous (package limited) t c = 25 c 7.5 a -continuous (silicon limited) t c = 25 c 9.6 -continuous t a = 25 c (note 1a) 3.3 -pulsed 15 e as single pulse avalanche energy (note 3) 12 mj p d power dissipation t c = 25 c 19 w power dissipation t a = 25 c (note 1a) 2.3 t j , t stg operating and storage junction temperature range -55 to +150 c r jc thermal resistance, junction to case 6.5 c/w r ja thermal resistance, junction to ambient (note 1a) 53 device marking device package reel size tape width quantity fdmc86116z FDMC86116LZ power 33 13 ?? 12 mm 3000 units
www.fairchildsemi.com 2 ?2011 fairchild semiconductor corporation FDMC86116LZ rev.c FDMC86116LZ n-channel power trench ? mosfet electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v 100 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 73 mv/c i dss zero gate voltage drain current v ds = 80 v, v gs = 0 v 1 a i gss gate to source leakage current v gs = 20 v, v ds = 0 v 10 a v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a 1.0 1.8 2.2 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -6 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 3.3 a 79 103 m v gs = 4.5 v, i d = 2.7 a 105 153 v gs = 10 v, i d = 3.3 a, t j = 125 c 136 178 g fs forward transconductance v ds = 5 v, i d = 3.3 a 11 s c iss input capacitance v ds = 50 v, v gs = 0 v, f = 1 mhz 232 310 pf c oss output capacitance 45 60 pf c rss reverse transfer capacitance 2.4 5 pf r g gate resistance 0.7 t d(on) turn-on delay time v dd = 50 v, i d = 3.3 a, v gs = 10 v, r gen = 6 4.5 10 ns t r rise time 1.3 10 ns t d(off) turn-off delay time 10 20 ns t f fall time 1.4 10 ns q g(tot) total gate charge v gs = 0 v to 10 v v dd = 50 v, i d = 3.3 a 46nc q g(tot) total gate charge v gs = 0 v to 4.5 v 2 3 nc q gs total gate charge 0.8 nc q gd gate to drain ?miller? charge 0.7 nc v sd source to drain diode forward voltage v gs = 0 v, i s = 3.3 a (note 2) 0.85 1.3 v v gs = 0 v, i s = 2 a (note 2) 0.82 1.2 t rr reverse recovery time i f = 3.3 a, di/dt = 100 a/ s 33 54 ns q rr reverse recovery charge 23 38 nc notes: 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. starting t j = 25 c; n-ch: l = 1.0 mh, i as = 5.0 a, v dd = 90 v, v gs = 10 v. 4. the diode connected between gate and source serves only as protection against esd. no gate overvoltage rating is implied. 53 c/w when mounted on a 1 in 2 pad of 2 oz copper a. 125 c/w when mounted on a minimum pad of 2 oz copper b. g df ds sf ss g df ds sf ss
www.fairchildsemi.com 3 ?2011 fairchild semiconductor corporation FDMC86116LZ rev.c FDMC86116LZ n-channel power trench ? mosfet typical characteristics t j = 25 c unless otherwise noted figure 1. 012345 0 3 6 9 12 15 pulse duration = 80 p s duty cycle = 0.5% max v gs = 3.5 v v gs = 4.5 v v gs = 10 v v gs = 4 v v gs = 3 v i d , drain current (a) v ds , drain to source voltage (v) on region characteristics figure 2. 03691215 0 1 2 3 4 5 v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4 v v gs = 4.5 v v gs = 3 v v gs = 10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 i d = 3.3 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 24681 0 0 100 200 300 400 500 t j = 125 o c i d = 3.3 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 123456 0 3 6 9 12 15 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 20 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
www.fairchildsemi.com 4 ?2011 fairchild semiconductor corporation FDMC86116LZ rev.c FDMC86116LZ n-channel power trench ? mosfet figure 7. 012345 0 2 4 6 8 10 i d = 3.3 a v dd = 75 v v dd = 25 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 50 v gate charge characteristics figure 8. 0.1 1 10 100 1 10 100 1000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.001 0.01 0.1 1 10 1 2 3 4 5 6 7 8 9 10 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 0 4 8 12 16 20 24 28 32 36 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 v gs = 0 v t j = 125 o c t j = 25 o c v gs , gate to source voltage (v) i g , gate leakage current (a) gate leakage current vs gate to source voltage f i g u r e 1 1 . m a x i m u m c o n t i n u o u s d r a i n c urrent vs case temperature 25 50 75 100 125 150 0 2 4 6 8 10 limited by package v gs = 4.5 v r t jc = 6.5 o c/w v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) figure 12. 0.1 1 10 100 400 0.005 0.01 0.1 1 10 20 100 ms 10 s 10 ms 100 us dc 1 s 1 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 125 o c/w t a = 25 o c f o r w a r d b i a s s a f e operating area typical characteristics t j = 25 c unless otherwise noted
www.fairchildsemi.com 5 ?2011 fairchild semiconductor corporation FDMC86116LZ rev.c FDMC86116LZ n-channel power trench ? mosfet figure 13. single pulse maximum power dissipation 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.5 1 10 100 500 p (pk) , peak transient power (w) single pulse r t ja = 125 o c/w t a = 25 o c t, pulse width (sec) figure 14. 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.001 0.01 0.1 1 single pulse r t ja = 125 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a junction-to-ambient transient thermal response curve typical characteristics t j = 25 c unless otherwise noted
www.fairchildsemi.com 6 ?2011 fairchild semiconductor corporation FDMC86116LZ rev.c FDMC86116LZ n-channel power trench ? mosfet dimensional outlin e and pad layout
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