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[AK1546] AK1546 3ghz low noise integer-n frequency synthesizer 1. overview the AK1546 is an integer-n pll (phase locked loop) freq uency synthesizer, covering a wide range of frequency from 500mhz to 3ghz. consisting of a highly accurate charge pump, a reference divider, a programmable divider and a dual-modulus prescaler (p/p+1), this product provid es high performance, very low phase noise and small footprints. an ideal pll can be achieved by combining the AK1546 with the external loop filter and vco (voltage controlled oscillator). access to the registers is c ontrolled via a 3-wire serial interface. the operating supply voltage is from 2.7v to 3.3v, and the charge pump circuit and the serial interface can be driven by individual supply voltage. 2. features ? operating frequency : 500mhz to 3ghz ? programmable charge pump current : 647 a to 5176 a typical with 8steps the current range can be controlled by an external resistor. ? fast lock mode for improved lock time : the programmable timer can switch two charge pump current setting. ? supply voltage : 2.7 to 3.3 v (pvdd, avdd pins) ? separate charge pump power supply : pvdd to 5.5v (cpvdd pin) ? excellent phase noise : -226dbc/hz ? on-chip lock detection feature of pll : selectab le phase frequency detector (pfd) output or digital filtered lock detect ? package : 20pin qfn (0.5mm pitch, 4mm 4mm 0.75mm) ? operating temperature : -40c to 85c ms1388-e-00 1 2012/3
[AK1546] - table of contents - 1. overview ____________________________________________________________________________ 1 2. features ____________________________________________________________________________ 1 3. block diagram _______________________________________________________________________ 3 4. pin functional description and assignments _____________________________________________ 4 5. absolute maximum ratings ____________________________________________________________ 6 6. recommended operating range ________________________________________________________ 6 7. electrical characteristics ______________________________________________________________ 7 8. block functional descriptions _________________________________________________________ 11 9. register map _______________________________________________________________________ 17 10. function description - registers _______________________________________________________ 19 11. ic interface schematic _______________________________________________________________ 30 12. recommended connection schematic of off-chip component _____________________________ 32 13. block power-up timing chart (recommended flow) ______________________________________ 34 14. frequency change timing chart (recommended flow) ____________________________________ 35 15. typical evaluation board schematic ____________________________________________________ 36 16. outer dimensions ___________________________________________________________________ 37 17. marking ____________________________________________________________________________ 38 in this specification, the following notations ar e used for specific signal and register names. [name] : pin name : register group name (address name) {name} : register bit name ms1388-e-00 2 2012/3
[AK1546] 3. block diagram cp phase freqency detector refin + - prescaler 8/9,16/17,32/ 33,64/65 programable counter 13 bit lock detect rfinp rfinn cpvdd cpvss av d d vref2 av ss pvss ld clk data le register 24 bit n d ivider fa st counter pdn test2 test1 r counter 14 bit bias charge pump swallow counter 6 bit vref1 pvdd vbg ldo ms1388-e-00 3 2012/3
[AK1546] 4. pin functional description and assignments 1. pin functions no. name i/o pin functions power down (note 1) remarks 1 cpvss g charge pump ground 2 test1 di test pin 1 internal pull-down, schmidt trigger input 3 avss g analog ground 4 rfinn ai complementary input to the rf prescaler 5 rfinp ai input to the rf prescaler 6 avdd p power supply for analog blocks 7 vref1 ao connect reference voltage capacitor for ldo ?low? 8 refin ai reference signal input 9 pvss g peripherals ground 10 test2 di test pin 2 internal pull-down, schmidt trigger input 11 pdn di power down schmidt trigger input 12 clk di serial clock input schmidt trigger input 13 data di serial data input schmidt trigger input 14 le di load enable input schmidt trigger input 15 ld do lock detect output ?low? 16 pvdd p power supply for peripherals 17 vref2 ao connect reference voltage capacitor ?low? 18 cpvdd p power supply for charge pump 19 bias aio resistance pin for setting charge pump current 20 cp ao charge pump output ?hi-z? note 1) ?power down? means the state of [pdn]=?low? after power on. the following table shows the meaning of ab breviations used in the ?i/o? column. ai: analog input pin ao: analog output pin aio: analog i/o pin di: digital input pin do: digital output pin p: power supply pin g: ground pin ms1388-e-00 4 2012/3
[AK1546] 2. pin assignments 1 2 3 4 5 6 7 8 9 10 15 14 13 12 11 20 19 18 17 16 to p view cpvss test1 avss rf inp rf inn a vdd vref1 refin pvss test2 pdn clk data le ld pvdd vref2 cpvdd bias cp 20pin qfn (0.5mm pitch, 4mm 4mm) ms1388-e-00 5 2012/3
[AK1546] 5. absolute maximum ratings parameter symbol min. max. unit remarks vdd1 -0.3 3.6 v [avdd], [pvdd] (note 1) supply voltage vdd2 -0.3 6.5 v [cpvdd] (note 1) vss1 0 0 v [avss], [pvss] ground level vss2 0 0 v [cpvss] analog input voltage vain vss1-0.3 vdd1+0.3 v [rfinn], [rfinp], [refin] (notes 1 & 2) digital input voltage vdin vss1-0.3 vdd1+0.3 v [clk], [data], [le], [pdn], [test1], [test2] (notes 1 & 2) input current iin -10 10 ma storage temperature tstg -55 125 c note 1) 0v reference for all voltages. note 2) maximum must not be over 3.6v. exceeding these maximum ratings may result in damage to the AK1546. normal operation is not guaranteed at these extremes. 6. recommended operating range parameter symbol min. typ. max. unit remarks operating temperature ta -40 85 c vdd1 2.7 3.0 3.3 v applied to [avdd],[pvdd] pins supply voltage vdd2 vdd1 5.0 5.5 v applied to [cpvdd] pin note 1) vdd1 and vdd2 can be driven individually within the recommended operating range. note 2) all specifications are applicable within the recommended operating range (operating temperature / supply voltage) . ms1388-e-00 6 2012/3
[AK1546] 7. electrical characteristics 1. digital dc characteristics parameter symbol conditions min. typ. max. unit remarks high level input voltage vih 0.8 vdd1 v note 1) low level input voltage vil 0.2 vdd1 v note 1) high level input current 1 iih1 vih = vdd1=3.3v -1 1 a note 2) high level input current 2 iih2 vih = vdd1=3.3v 17 33 66 a note 3) low level input current iil vil = 0v, vdd1=3.3v -1 1 a note 1) high level output voltage voh ioh = -500 a vdd1-0.4 v note 4) low level output voltage vol iol = 500 a 0.4 v note 4) note 1) applied to [clk], [data], [le], [pdn], [test1] and [test2] pins. note 2) applied to [clk], [data], [le] and [pdn] pins. note 3) applied to [test1] and [test2] pins. note 4) applied to [ld] pin. ms1388-e-00 7 2012/3
[AK1546] 2. serial interface timing le (input ) clk (input ) data (input ) tsu thd tc s u d21 d20 d 2 a0 a1 d0 d1 tc h tc l tlesu tle serial interface timing chart serial interface timing parameter symbol min. typ. max. unit remarks clock l level hold time tcl 25 ns clock h level hold time tch 25 ns clock setup time tcsu 10 ns data setup time tsu 10 ns data hold time thd 10 ns le setup time tlesu 10 ns le pulse width tle 20 ns ms1388-e-00 8 2012/3
[AK1546] 3. analog circuit characteristics the resistance of 27k ? is connected to the [bias] pin. vdd1 2.7v to 3.3v, vdd2=vdd1 to 5.5v, ?40c ta 85c, unless otherwise specified. parameter min. typ. max. unit remarks rf characteristics input sensitivity -10 5 dbm input frequency 500 3000 mhz refin characteristics input sensitivit y 0.4 vdd1 vpp refin 200mhz 0.4 2 vpp refin>200mhz input frequency 10 300 mhz maximum allowable prescaler output frequency 300 mhz phase detector phase detector frequency 104 mhz charge pump charge pump maximum value 5176 a charge pump minimum value 647 a icp tri-state leak current 1 na 0.7 vcpo vdd2-0.7, ta=25c mismatch between source and sink currents (note 1) 10 % vcpo=vdd2/2, ta=25c icp vs. vcpo (note 2) 15 % 0.5 vcpo vdd2-0.5, ta=25c regulator vref1 rise time 10 ms 470 f capacitance connected to vref2 vref2 rise time 10 ms 470 f capacitance connected to vref2 current consumption idd1 10 a [pdn]=?0? idd2 11 19 ma [pdn]=?1?, {pd1}=0, idd for vdd1 idd3 (note3) 0.8 1.6 ma [pdn]=?1?, {pd1}=0, idd for vdd2 idd4 0.55 0.9 ma [pdn]=?1?, {pd1}=1, idd for vdd1 ms1388-e-00 9 2012/3
[AK1546] note 1) mismatch between source and sink currents : [(|isink|-|isource|)/{(|isink|+|isource|)/2}] 100 [%] note 2) see ?charge pump characteristics - voltage vs. current?. vcpo is the output voltage at [cp]. icp vs. vcpo : [{1/2(|i1|-|i2|)}/{1/2(|i1|+|i2|)}]100 [%] note 3) idd3 doesn?t include the current depending on phase detector frequency. idd3 is the current the charge pump circuit consumes constantly. note 4) the test is done with the exposed pad at the center of backsi de connected to vss. resistance connected to the bias pin for setting charge pump output current parameter min. typ. max. unit remarks bias resistance 22 27 33 k ? isink isource vcpo icp cpvdd-0.5 cpvdd/2 0.5 i1 i1 i2 i2 charge pump characteristics - voltage (vcpo) vs. current (icp) ms1388-e-00 10 2012/3
[AK1546] 8. block functional descriptions 1. frequency setup the following formula is used to calculate the frequency setting for the AK1546. frequency setting (external vco output frequency) = f pfd n where : n : dividing number n = [ (p b) + a ] f pfd : phase detector frequency f pfd = [refin] pin input frequency / r counter dividing number p : prescaler value (see < address2>:{pre[1:0]}) b : b (programmable) counter value (see :{b[12:0]}) a : a (swallow) counter value (see :{a[5:0]}) calculation example the output frequency of external refe rence frequency oscillator is 10mhz, and f pfd is 200khz and vco frequency is 2460mhz. AK1546 setting : r (reference counter)=10000000/200000 = 50 (:{r[13:0]}= ?50?) p=32 (:{pre[1:0]}=?10bin?) b=384 (:{b[12:0]}=?384?) a=12 (:{a[5:0]}=?12?) frequency setting = 200khz [ (32384) + 12] = 2460mhz lower limit for setting consecutive dividing numbers in the AK1546, it is impossible to set consecutive dividing numbers below the lower limit. the lower limit is calculated by the following formula; n min =p 2 -p for example, in the case of p=16, it can be se t 240 and over as consecutive dividing numbers. ms1388-e-00 11 2012/3
[AK1546] 2 charge pump, loop filter the current setting of charge pump can switch with the built-in timer for fast lock. c2 phase detector up down tim er vco loop filter c1 c3 r2 r3 cp loop filter schematic the charge pump current for normal operation (cp1) is de termined by the setting in {c p1[2:0]}, which is a 3-bit address of {d[15:13]} in and a value of the re sistance connected to the [bias] pin. the charge pump current for the fast lock up mode operation (cp2) is dete rmined by the setting in {cp2[2:0]}, which is a 3-bit address of d[18:16] in and a value of the resistance connected to the [bias] pin. the following formula shows the relationship among the re sistance value, the register setting and the electric current value. charge pump minimum current (icp_min) [a] =17.46 / resistance connected to the bias pin [ ? ] charge pump current (icp) [a] = icp_min [a] ({cp1} or {cp2} setting +1) the allowed value range for the resistance connec ted to the [bias] pin is from 22 to 33k ? for both normal and fast lock up mode operations. ms1388-e-00 12 2012/3
[AK1546] 3. fast lock up mode setting {fast[1:0]} in to ?11bin? and {cpgain} in to ?1? enables the fast lock up mode for the AK1546. the fast lock up mode is enabled only during the time per iod set by the timer accordi ng to the counter value in {timer[3:0]} in . the charge pump current is set to the value specified by {cp2}. when the specified time period elapses, the fast lock up mode operation is switched to the normal operation, and {cpgain} in is reset to ?0?. {timer[3:0]} in is used to set the time period fo r this mode. the following formula is used to calculate the time period : switchover time = 1/f pfd counter value counter value = 3 + (timer[3:0] setting 4) fast lock up cp2 on normal normal cp1 off cp1 off operation mode charge pump current loop filter switch frequency setting write ?1? into {cpgain} in . fast lock up time s p ecified b y the timer fast lock up mode timing chart ms1388-e-00 13 2012/3
[AK1546] 4 lock detect lock detect output can be selected by {ld[2:0]} in . when {ld} is set to ?101bin", the phase detector outputs an unmanipulated phase detection (c omparison) result. (this is called ?analog lock detect?.) when {ld} is set to ?001bin?, the lock detect signal is output according to the on-chip logic. (this is called ?digital lock detect?.) the lock detect can be done as following: the [ld] pin is in unlocked state (which outputs ?low?) when a frequency setup is made. in the digital lock detect, the [ld] pi n outputs ?high? (which means the locked state) when a phase error smaller than a cycle of [refin] clock (t) is detected for n time s consecutively. when a phase error larger than t is detected for n times consecutively whil e the [ld] pin outputs ?high?, then the [ld] pin outputs ?low? (which means the unlocked state). the counter value n can be set by {ldp} in . the n is different between ?unlocked to locked? and ?locked to unlocked?. {ldp} unlocked to locked locked to unlocked 0 n=15 n=3 1 n=31 n=7 the lock detect signal is shown below: reference clock this is ignored because it cannot be sampled. valid pfd frequency signal divided clock of rf input signal pfd output signal ignored valid i g nored ld output the [ld] pin outputs ?high? when a phase error smaller than t is detected for n times consecutively. case of ?r = 1? reference clock this is ignored because it cannot be sampled. valid pfd frequency signal divided clock of rf input signal pfd output signal ignored valid ignored ld output the [ld] pin outputs ?high? when a phase error smaller than t is detected for n times consecutively. case of ?r > 1? digital lock detect operations ms1388-e-00 14 2012/3
[AK1546] phase error < t flag = flag+1 lock ([ld]=?high?) unlock ([ld]=?low?) y es no flag > n flag=0 y es no unlock to lock operation flow phase error > t y es flag=0 flag = flag+1 flag > n no y es unlock ([ld]=?low?) no lock ([ld]=?high?) address2 write lock to unlock operation flow ms1388-e-00 15 2012/3
[AK1546] 5 reference counter the reference input can be set with a dividing number in t he range of 1 to 16383 using {r [13:0]}, which is an 14-bit address of {d[13:0]} in . 0 cannot be set as a dividing number. 6 prescaler the dual modulus prescaler (p/p + 1) and the swallow counter are used to provide a large dividing ratio. the prescaler is set by {pre[1:0]}, which is a 2-bit latch of {d[21:20]} in . {pre[1:0]}=?00bin?, p=8, dual modulus prescaler 8/9 {pre[1:0]}=?01bin?, p=16, dual modulus prescaler 16/17 {pre[1:0]}=?10bin?, p=32, dual modulus prescaler 32/33 {pre[1:0]}=?11bin?, p=64, dual modulus prescaler 64/65 the maximum allowable prescaler output frequency is 300mhz. ?p? must be set as ?rf input frequency/p 300mhz?. 7 power-down and power-save mode it is possible to operate in the power-down or power-save mode if necessary by using the external control pin. power on follow the power-up sequence. normal operation [pdn] {pd2} {pd1} function ?low? x x power down ?high? x 0 normal operation ?high? 0 1 vbg & ldo : power up synthesizer circuits : asynchronous power down ?high? 1 1 vbg & ldo : power up synthesizer circuits : synchronous power down x : don?t care (?0? is recommended.) ms1388-e-00 16 2012/3
[AK1546] 9. register map name data address r counter 0 0 n counter (a and b) 0 1 function 1 0 initialization d21 - d0 1 1 name d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 addr ess r count 0 0 0 ldp 0 0 low noise 0 r [13] r [12] r [11] r [10] r [9] r [8] r [7] r [6] r [5] r [4] r [3] r [2] r [1] r [0] 0x0 n count 0 0 cp gain b [12] b [11] b [10] b [9] b [8] b [7] b [6] b [5] b [4] b [3] b [2] b [1] b [0] a [5] a [4] a [3] a [2] a [1] a [0] 0x1 func. pre [1] pre [0] pd2 cp2 [2] cp2 [1] cp2 [0] cp1 [2] cp1 [1] cp1 [0] time r [3] time r [2] time r [1] time r [0] fast [1] fast [0] cp hiz cp pola ld [2] ld [1] ld [0] pd1 cntr rst 0x2 initial. pre [1] pre [0] pd2 cp2 [2] cp2 [1] cp2 [0] cp1 [2] cp1 [1] cp1 [0] time r [3] time r [2] time r [1] time r [0] fast [1] fast [0] cp hiz cp pola ld [2] ld [1] ld [0] pd1 cntr rst 0x3 ms1388-e-00 17 2012/3
[AK1546] notes for writing into registers after powers on AK1546, the initial registers value are not defined. it is required to write the data in all addresses in order to commit it. [examples of writing into registers] (ex. 1) power-on - bring [pdn] to ?0 (low)? - apply vdd - program address0, address1 and address2 ({pd1}=?1? is recommended) - bring [pdn] to ?1 (high)? - program {pd1} in address 2 to ?0? (ex. 2) changing frequency settings : initialization - program address3 - program address1 (ex. 3) changing frequency settings : counter reset - program address2. as part of this, load ?1? to both {pd1} and {cntr_rst}. - program address1 - program address2. as part of this, load ?0? to both {pd1} and {cntr_rst}. (ex. 4) changing frequency settings : pdn pin method - bring [pdn] to ?0 (low)? - program address1 - bring [pdn] to ?1 (high)? ms1388-e-00 18 2012/3
[AK1546] 10. function description - registers < address0 : r counter > d[21:19] d18 d[17:16] d15 d14 d[13:0] address 0 ldp 0 low noise 0 r[13:0] 00 d[21:19], d[17:16] , d14 : these bits are set to the following for normal operation. d21 d20 d19 d17 d16 d14 0 0 0 0 0 0 ldp : lock detect precision the counter value for digital lock detect can be set. d18 function remarks 15 times count unlocked to locked 0 3 times count locked to unlocked 31 times count unlocked to locked 1 7 times count locked to unlocked low noise : selects low noise mode d15 function remarks 0 normal mode 1 low noise mode idd2 increases by 1.3ma ms1388-e-00 19 2012/3
[AK1546] r[13:0] : reference clock division number the following settings can be selected for the reference clock division. the allowed range is 1 (1/1 division) to 16383 (1/16383 division). 0 cannot be set. the maximum frequency for f pfd is 104mhz. d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prohibited 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1/1 division 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1/2 division 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1/3 division 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1/4 division data 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1/16381 division 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1/16382 division 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1/16383 division ms1388-e-00 20 2012/3
[AK1546] < address1 : n counter > d[21:20] d19 d[18:6] d[5:0] address 0 cpgain b[12:0] a[5:0] 01 d21, d20 : these bits are set to the following for normal operation d21 d20 0 0 cpgain : sets the charge pump current when {fast[1:0]} is not ?11bin? : d19 function remarks 0 cp1 is enabled 1 cp2 is enabled when {fast[1:0]} is ?11bin? : d19 function remarks 0 cp1 is enabled 1 cp2 is enabled, also timer is enabled fast lock up mode b[12:0] : b (programmable) counter value d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 function remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prohibited 0 0 0 0 0 0 0 0 0 0 0 0 1 1 dec prohibited 0 0 0 0 0 0 0 0 0 0 0 1 0 2 dec prohibited 0 0 0 0 0 0 0 0 0 0 0 1 1 3 dec data 1 1 1 1 1 1 1 1 1 1 1 0 1 8189 dec 1 1 1 1 1 1 1 1 1 1 1 1 0 8190 dec 1 1 1 1 1 1 1 1 1 1 1 1 1 8191 dec ms1388-e-00 21 2012/3
[AK1546] a[5:0] : a (swallow) counter value d5 d4 d3 d2 d1 d0 function remarks 0 0 0 0 0 0 0 0 0 0 0 0 1 1 dec 0 0 0 0 1 0 2 dec 0 0 0 0 1 1 3 dec data 1 1 1 1 0 1 61 dec 1 1 1 1 1 0 62 dec 1 1 1 1 1 1 63 dec * requirements for a[5:0] and b[12:0] the data at a[5:0] and b[ 12:0] must meet the following requirements: a[5:0] 0, b[12:0] 3, b[12:0] a[5:0] see ?frequency setup? in section ?block functional descriptions? for details of the relationship between a frequency division number n and the data at a[ 5:0] and b[12:0]. ms1388-e-00 22 2012/3
[AK1546] < address2 : function > d[21:20] d19 d[18:16] d[15:13] d[12:9] d[8:7] pre[1:0] pd2 cp2[2:0] cp1[2:0] timer[3:0] fast[1:0] d6 d5 d[4:2] d1 d0 address cphiz cppola ld[2:0] pd1 cntr_rst 02 pre[1:0] : selects a dividing ratio for the prescaler the prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 300mhz. d21 d20 function remarks 0 0 p=8, dual modulus prescaler 8/9 0 1 p=16, dual modulus prescaler 16/17 1 0 p=32, dual modulus prescaler 32/33 1 1 p=64, dual modulus prescaler 64/65 pd2, pd1 : power down select [pdn] {pd2} {pd1} function ?low? x x power down ?high? x 0 normal operation ?high? 0 1 vbg & ldo : power up synthesizer circuits : asynchronous power down ?high? 1 1 vbg & ldo : power up synthesizer circuits : synchronous power down x : don?t care (?0? is recommended.) {pd2}=1 and {pd1}=1 : synthesizer circuits powers down at the timing when the phase detector frequency signal reverses. {pd2}=0 and {pd1}=1 : synthesizer circuits goes into power down during the rise up of le signal that latches 1 into {pd1}. ms1388-e-00 23 2012/3
[AK1546] cp2[2:0] : charge pump current setting 2 cp1[2:0] : charge pump current setting 1 AK1546 provides two setting for charge pump current. they can be set by {cp1} and {cp2}. the following formula shows the relationship among t he resistance value, the register setting and the electric current that is used fo r lpf band calculation (tran_icp). tran_icp [a] = icp_min [a] ({cp1} or {cp2} setting +1) charge pump minimum current (icp_min)[a] = (0.851.16415) / resistance connected to the bias pin [ ? ] the following table shows the typical tran_icp for each status. tran_icp (typical) [unit : a] d18 d17 d16 bias resistance d15 d14 d13 33 k ? 27 k ? 22 k ? remarks 0 0 0 450 550 675 0 0 1 900 1100 1350 0 1 0 1350 1650 2025 0 1 1 1800 2200 2700 1 0 0 2250 2750 3375 1 0 1 2700 3300 4050 1 1 0 3150 3850 4725 1 1 1 3600 4400 5400 the following formula shows the relationship among t he resistance value, the register setting and the electric current that can be measured (icp). charge pump minimum current (icp_min)[a] = (1.16415) / resistance connected to the bias pin [ ? ] charge pump current (icp) [a] = icp_min [a] ({cp1} or {cp2} setting +1) ms1388-e-00 24 2012/3
[AK1546] the following table shows the typical icp for each status. icp (typical) [unit : a] d18 d17 d16 bias resistance d15 d14 d13 33 k ? 27 k ? 22 k ? remarks 0 0 0 529 647 794 0 0 1 1058 1294 1588 0 1 0 1587 1941 2382 0 1 1 2116 2588 3176 1 0 0 2645 3235 3970 1 0 1 3174 3882 4764 1 1 0 3703 4529 5558 1 1 1 4232 5176 6352 ms1388-e-00 25 2012/3
[AK1546] timer[3:0] : sets the switchover time for cp2-to-cp1 this is enabled when {fast[1:0]} is ?11bin? and {[cpgain}=?1?. the charge pump current is set into value {cp2[2:0 ]} designate during switchover time. it goes to be {cp1[2:0]} setting value after the time out. the following formula shows the relationship betwe en the switchover time and the counter value. switchover time = 1/f pfd counter value counter value = 3 + timer[3:0] 4 the following table shows the relationship between counter value and {timer[3:0]}. d12 d11 d10 d9 function remarks 0 0 0 0 3 counts 0 0 0 1 7 counts 0 0 1 0 11 counts 0 0 1 1 15 counts 0 1 0 0 19 counts 0 1 0 1 23 counts 0 1 1 0 27 counts 0 1 1 1 31 counts 1 0 0 0 35 counts 1 0 0 1 39 counts 1 0 1 0 43 counts 1 0 1 1 47 counts 1 1 0 0 51 counts 1 1 0 1 55 counts 1 1 1 0 59 counts 1 1 1 1 63 counts ms1388-e-00 26 2012/3
[AK1546] fast[1:0] : enables or disables the fast lock mode when {fast[1:0]} is ?11bin?, {cpgain} of function latch is the fast lock mode bit. when fast lock is enabled, charge pump current is set to the value of {cp2} setting during the switchover time under the control of the timer counter. afte r the timeout, {cpgain} is reset into ?0? and charge pump current goes to be {cp1} setting value. d8 d7 {cpgain} function remarks 0 {cp1} is enabled x 0 1 {cp2} is enabled 0 {cp1} is enabled 0 1 1 {cp2} is enabled 0 {cp1} is enabled 1 1 1 {cp2} is enabled, and switchover operates. {cpgain} is reset to ?0? after timeout. cphiz : tri-state output setting for charge pump d6 function remarks 0 charge pumps are activated. use this setting for normal operation. 1 tri-state note 1) note 1) the charge pump output is turned off and put in the high- impedance (hi-z) state. ms1388-e-00 27 2012/3
[AK1546] cppola : selects positive or negative output polarity for cp1 and cp2 d5 function remarks 0 negative 1 positive high high charge pump output voltage negative positive low low vco frequency ld selects output from [ld] pin d4 d3 d2 function remarks 0 0 1 digital lock detect 1 0 1 analog lock detect cntr_rst : counter reset d0 function remarks 0 normal operation 1 r and n counters are reset. ms1388-e-00 28 2012/3
[AK1546] < address3 : initialization > this function is same as . when this register is accessed, the following occurs : - address3 is loaded. - an internal pulse resets the r counter, n counter and {timer} settings to load-state conditions, and also charge pump to tri-state. - writing address1 activates the r and n counter , {timer} and charge pump. {timer} is enabled when {fast}=?11bin? and {cpgain}=?1?. ms1388-e-00 29 2012/3
[AK1546] 11. ic interface schematic no. pin name i/o r0( ) cur( a) function 11 pdn i 300 12 clk i 300 13 data i 300 14 le i 300 digital input pin r0 2 test1 i 300 10 test2 i 300 digital input pin (pull-down) r0 100k 15 ld o digital output pin 8 refin i 300 analog input pin r0 19 bias io 300 7 vref1 io 300 17 vref2 io 300 analog input/output pin r0 ms1388-e-00 30 2012/3
[AK1546] no. pin name i/o r0( ) cur( a) function 20 cp o analog output pin 4 rfinn i 12k 20 5 rfinp i 12k 20 analog input pin (rf input pin) r0 ms1388-e-00 31 2012/3
[AK1546] 12. recommended connection sche matic of off-chip component 1. power supply pins pvdd cpvdd lsi a vdd 100pf 10 f 0.01 f 0.01 f 0.01 f 100pf 10 f 100pf 10 f 2. vref1, vref2 vref1 lsi 220nf10% vref2 470nf10% ms1388-e-00 32 2012/3
[AK1546] 3. test1, test2 test1,2 lsi 4. refin refin lsi 100pf10% 5. rfinp rfinn lsi rfinp vco output rfinn 100pf10% 100pf10% 51? 6. bias lsi bias 22k ? ~33k ? ms1388-e-00 33 2012/3
[AK1546] 13. block power-up timing chart (recommended flow) power-up sequence (controlled by [pdn] pin) note) after powers on AK1546, the initial registers value are not defined. it is required to write the data in addresses0~2 in order to commit it. it is recommended to bring pdn to high after writing {pd1}=1 on address2. it requires 10msec for ldo rising up after pdn rises up. writing {pd1}=0 should be done after ldo rises up. power-up sequence (vdd1/vdd2/pdn synchronous power-up) note) after powers on AK1546, the initial registers value are not defined. it is required to write the data in addresses0~2 in order to commit it. it requires 10msec for ldo rising up after pdn rises up. writing {pd1}=0 should be done after ldo rises up. address1 setting pdn registers internal ldo cp output address0 setting 0v 1.9v 10ms hi-z 2 vdd1, vdd registers value are defined address2 { pd1 } =0 address2 {pd1}=1 write {pd1}=0 write { pd1 } =1 , then raise pdn u p vdd1,vdd2 address1 settin g 0v output address0 settin g 10ms hi-z re g isters value are defined address2 { pd1 } =0 address2 { pd1 } =1 write {pd1}=0 undefined pdn 1.9v internal ldo registers cp ms1388-e-00 34 2012/3
[AK1546] 14. frequency setting timing chart (recommended flow) high address1 settin g pdn registers cp address0 settin g hi-z vdd1,vdd2 address2 {pd1}=0 address2 { pd1 } =1 high out p ut1 output2 frequency change sequence (controlled by {pd1} bit) high high address1 settin g pdn registers cp address0 settin g hi-z vdd1,vdd2 address3 { pd1 } =0 output1 output2 frequency change sequence (controlled by initialization register) note) setting on address3 is same as address2. but {pd1} should be ?0?. writing address3 bring cp output to hi-z. after that, cp output restarts by the trigger of le pulse for address1 writing to set the frequency. ms1388-e-00 35 2012/3
[AK1546] 15. typical evaluation board schematic c2 AK1546 loop filter c1 c3 r2 r3 cp rfout 51 100pf rfinn vco bias rfinp 100pf 27k refin vref1 220nf 100pf 100pf 18 18 18 vref2 470nf note1) although it is no problem that both of [test1] and [test2] are open, it is recommended that they should be connected to ground. note2) although it is no problem that exposed pad at the center of the backside is open, it is recommended that it should be connected to ground. ms1388-e-00 36 2012/3
[AK1546] 16. outer dimensions note) although it is no problem that exposed pad at the center of the backside is open, it is recommended that it should be connected to ground. ms1388-e-00 37 2012/3
[AK1546] ms1388-e-00 38 2012/3 17. marking a. style qfn b. number of pins 20 c. a1 pin marking d. product number 1546 e. date code ywwl (4 digits) y lower 1 digit of calendar year (year 2012-> 2, 2013-> 3 ...) ww week l lot identification, given to each product lot which is made in a week (a, b, c?) lot id is given in alphabetical order (c) ywwl (e) 1546 (d)
[AK1546] important notice z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustra te the operation and application examples of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipment. asahi kasei microdevices corporation (akm) assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or syst ems containing them, may require an export license or other official approval u nder the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one design ed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assu me any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. ms1388-e-00 39 2012/3

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