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ltc6801 1 6801fb applications n redundant battery monitor n hybrid electric vehicles n battery backup systems n power systems using multiple battery cells l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. n monitors up to 12 li-ion cells in series (60v max) n stackable architecture enables > 1000v systems n 1% maximum overvoltage detection level error n adjustable overvoltage and undervoltage detection n self test features guarantee accuracy n robust fault detection using differential signals n simple pin-strapped con? guration allows battery monitoring without a microcontroller n 15.5ms to monitor all cells in a system n programmable response time n two temperature monitor inputs n low power idle mode n 36-lead ssop package C40 20 95 C10 50 110 125 580 C25 35 65 temperature (c) error (%) 1.0 C0.8 0.8 0.4 0 C0.4 0.6 0.2 C0.2 C0.6 C1.0 6801 ta01b v + = 43.2v ov = 4.116v 5 typical units block diagram description independent multicell battery stack fault monitor the ltc ? 6801 is a multicell battery monitoring ic in- corporating a 12-bit adc, a precision voltage reference, sampled comparator, and a high voltage input multiplexer. the ltc6801 can monitor as many as 12 series con- nected battery cells for overvoltage, undervoltage, and overtemperature conditions, indicating whether the cells are within speci? ed parameters. the ltc6801 generates a clock output when no fault conditions exist. differential clocking provides high noise immunity and ensures that battery stack fault conditions cannot be hidden by frozen bits or short circuit conditions. each ltc6801 can operate with a battery stack voltage up to 60v and multiple ltc6801 devices can be stacked to monitor each individual cell in a long battery string. when multiple devices are stacked, the status signal of each ltc6801 can be daisy-chained, without opto-couplers or isolators, providing a single status output for the entire battery string. the ltc6801 is con? gurable by external pin strapping. adjustable overvoltage and undervoltage thresholds sup- port various li-ion chemistries. selectable measurement times allow users to save power. features 6801 ta01a 1 2 3 12 13 20 22 14 15 16 v ref v temp1 v temp2 ntc ntc c1 c2 c11 c12 v + v C next lower cell pack next higher cell pack 12 mux cells good enable input isolation clock signal input enables the ltc6801 clock signal output indicates system ok status output control logic 17 reference ltc6801 adc 0v detection level error
ltc6801 2 6801fb pin configuration absolute maximum ratings total supply voltage (v + to v C ) .................................60v input voltage (relative to v C ) c1 ............................................................ C0.3v to 9v c12 ...........................................v + C0.3v to v + + 0.3v all other pins (not c inputs) ................... C0.3v to 7v voltage between inputs cn to cn-1* ............................................. C0.3v to 9v c12 to c8 ............................................... C0.3v to 25v c8 to c4 ................................................. C0.3v to 25v c4 to v C ................................................. C0.3v to 25v operating temperature range ltc6801i.............................................. C40c to 85c ltc6801h .......................................... C40c to 125c speci? ed temperature range ltc6801i.............................................. C40c to 85c ltc6801h .......................................... C40c to 125c junction temperature ........................................... 150c storage temperature range ................... C65c to 150c *n = 2 to 12 (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view g package 36-lead plastic ssop 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 v + c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 v C v temp1 v temp2 v ref v reg ov1 ov0 uv1 uv0 hyst cc1 cc0 slt sltok dc eout eout sin sin sout sout ein ein t jmax = 150c, ja = 70c/w order information lead free finish tape and reel part marking* package description specified temperature range ltc6801ig#pbf ltc6801ig#trpbf ltc6801g 36-lead plastic ssop C40c to 85c ltc6801hg#pbf ltc6801hg#trpbf ltc6801g 36-lead plastic ssop C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
ltc6801 3 6801fb electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c, v + = 43.2v, v C = 0v unless otherwise noted. symbol parameter conditions min typ max units dc speci? cations v err overvoltage (ov) or undervoltage (uv) detection level error (note 2) 2.106v v cell 4.498v 2.106v v cell 4.498v 1.531v v cell < 2.106v 1.531v v cell < 2.106v v cell = 0.766v v cell = 0.766v l l l C0.8 C1 C1 C1.3 C1.5 C2 0.8 1 1 1.3 1.5 2 % % % % % % v s supply voltage, v + relative to v C v err speci? cations met l 10 50 v v cell cell voltage range full scale voltage range 5 v v cm common mode voltage range measured relative to v C v err speci? cations met range of inputs cn, n = 3 to 11 range of input c2 range of input c1 l l l 1.8 1.2 0 5 ? n 10 5 v v v v tv temperature input detection level error (relative to v ref /2) 10v < v + < 50v l C13 17 mv hys uv/ov detection hysteresis error (relative to selected value) 10v < v + < 50v l C25 25 % v ref reference pin voltage v ref pin loaded with 100k to v C l 3.043 3.038 3.058 3.058 3.073 3.078 v v reference voltage temperature coef? cient 8 ppm/?c reference voltage hysteresis 50 ppm reference voltage long term drift 60 ppm/ khr v reg regulator pin voltage 10v < v s < 50v, no load ltc6801ig ltc6801hg 10v < v s < 50v, i load = 4ma ltc6801ig ltc6801hg l l l l 4.5 4.5 4.1 4.1 5 5 4.8 4.8 5.5 5.7 v v v v regulator pin short circuit current limit l 59 ma i b input bias current in/out of pins c1 thru c12 when measuring cells during self test when measuring cells when idle l C10 100 1 10 a a na i m supply current, monitor mode current into the v + pin while monitoring for uv and ov conditions, f ena = 10khz continuous monitoring continuous monitoring monitor every 130ms (note 3) monitor every 500ms (note 3) l l l 600 500 110 50 750 750 200 100 1000 1100 320 160 a a a a i qs supply current, idle current into the v + pin when idle, f ena = 0 ltc6801ig ltc6801hg l l 23 20 23 20 30 30 30 30 42 45 42 48 a a a a ltc6801 timing speci? cations t cycle measurement cycle time dc = cc1 = cc0 = v reg l 13 15.5 19 ms f ena valid ein/ ein frequency l 240khz t ena valid ein/ ein period = 1/ f ena l 25 500 s dc ena valid ein/ ein duty cycle f ena = 40khz l 40 60 %
ltc6801 4 6801fb electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c, v + = 43.2v, v C = 0v unless otherwise noted. symbol parameter conditions min typ max units ltc6801 single ended digital i/o speci? cations ( slt , sltok pins) v ih digital input voltage high slt pin l 2v v il digital input voltage low slt pin l 0.5 v v odl digital output voltage low, open drain slt pin, 10k to v reg l 0.3 v v oh digital output voltage high sltok pin, 10k to v C l v reg C 0.3 v v ol digital output voltage low sltok pin, 10k to v reg l 0.3 v i pu-st pull-up current slt pin l 2.5 5 10 a ltc6801 differential digital input speci? cations (sin/ sin , ein/ ein pins) (see figure 1) v idh minimum differential input voltage high differential voltage applied between sin and sin or ein and ein l 1.7 v v idl minimum differential input voltage low l C1.7 v v il valid input voltage low low side of differential signal, ref. to v C l 0 1.2 v v ih valid input voltage high high side of differential signal, ref. to v C l 2.5 6 v v dhys differential input hysteresis 1v v open open circuit voltage l 2 2.5 3 v r incm input resistance, common mode l 100 150 k r indiff input resistance, differential between sin to sin , ein to ein l 200 300 k ltc6801 differential digital output speci? cations (sout/ sout , eout/ eout pins) v odh digital output voltage high output pins loaded with 100k to v C l v reg C 0.4 v v odl digital output voltage low output pins loaded with 100k to v reg l 0.4 v ltc6801 three-level digital input speci? cations (ov0, ov1, uv0, uv1, hyst, dc, cc0 and cc1 pins) v 3ih three-level digital input voltage high l v reg C 0.3 v v 3im three-level digital input voltage mid l v ref C 0.3 v ref + 0.3 v v 3il three-level digital input voltage low l 0.3 v i pu pull-up current pins dc, cc0, cc1, uv0 and uv1 l 0.5 1 2 a i pd pull-down current pins hyst, ov0 and ov1 l 0.5 1 2 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. figure 1. differential input speci? cations 6801 f01 v C = 0v ein ein v idh (valid high when ein C ein v idh ) max, v ih t ena min, v ih max, v il v idl (valid low when ein C ein v idl ) note 2: v cell refers to the voltage applied across the following pin combinations: cn to cn C 1 for n = 2 to 12, c1 to v C . note 3: guaranteed by continuous monitoring supply current speci? cations, not subject to test.
ltc6801 5 6801fb v + (v) 10 i supply (a) 800 620 780 740 700 660 760 720 680 640 600 6801 g01 60 50 20 40 30 dc pin tied to v reg f ena = 10khz C40c 25c 85c typical performance characteristics supply current, monitor mode supply current, monitor mode supply current, idle mode supply current, monitor mode supply current, monitor mode supply current, idle mode uv detection level error 0v detection level error supply current v + (v) 10 i supply (a) 250 200 150 100 50 0 6801 g02 60 50 20 40 30 cc1 = cc0 = v reg f ena = 10khz dc pin = v C dc pin = v ref 85c 25c C40c v + (v) 10 i supply (a) 40 5 35 25 15 30 20 10 0 6801 g03 60 50 20 40 30 C40c 25c 85c C40 20 95 C10 50 110 125 580 C25 35 65 temperature (c) i supply (a) 800 620 780 740 700 660 760 720 680 640 600 6801 g04 dc pin tied to v reg f ena = 10khz v + = 60v v + = 35v v + = 10v C40 20 95 C10 50 110 125 580 C25 35 65 temperature (c) i supply (a) 250 200 150 100 50 0 6801 g05 cc1 = cc0 = v reg f ena = 10khz dc pin = v C dc pin = v ref v + = 60v v + = 35v v + = 10v 40 5 35 25 15 30 20 10 0 C40 20 95 C10 50 110 125 580 C25 35 65 temperature (c) i supply (a) 6801 g06 v + = 60v v + = 35v v + = 10v C40 20 95 C10 50 110 125 580 C25 35 65 temperature (c) error (%) 1.0 C0.8 0.8 0.4 0 C0.4 0.6 0.2 C0.2 C0.6 C1.0 6801 g07 v + = 43.2v uv = 2.106v 5 typical units C40 20 95 C10 50 110 125 580 C25 35 65 temperature (c) error (%) 1.0 C0.8 0.8 0.4 0 C0.4 0.6 0.2 C0.2 C0.6 C1.0 6801 g08 v + = 43.2v ov = 4.116v 5 typical units 1 10 100 f ena (khz) i supply (a) 800 620 780 740 700 660 760 720 680 640 600 6801 g09 v + = 43.2v continuous meas mode C40c 25c 85c
ltc6801 6 6801fb 17.0 16.5 15.5 14.5 16.0 15.0 14.0 C40 20 95 C10 50 110 125 580 C25 35 65 temperature (c) measurement cycle time (ms) 6801 g11 v + = 60v v + = 10v continuous meas mode cc1 = cc0 = v reg external series resistance, r s (k) 0 error relative to r s = 0 (%) 4.0 0.5 3.5 2.5 1.5 3.0 2.0 1.0 0 6801 g10 10 8 26 4 C40c r s in series with cn and cn-1 10nf from cn, cn-1 to v C 85c 25c typical performance characteristics v ref load regulation cell input bias current, idle mode cell voltage measurement hysteresis v ref line regulation uv/ov detection level error measurement cycle time cell input bias current when measuring v ref output voltage v reg line regulation cell voltage (v) 0 sout clock frequency (khz) 12 10 6 2 8 4 0 C2 6801 g14 5 4 13 2 undervoltage detected overvoltage detected uv threshold = 2.106v ov threshold = 4.116v hyst = v reg 8.0 7.5 6.5 4.5 7.0 6.0 4.0 5.5 5.0 C40 20 95 C10 50 110 125 580 C25 35 65 temperature (c) c pin bias current (a) 6801 g12 cell input = 3.6v 50 40 20 30 10 C10 0 C40 20 95 C10 50 110 125 580 C25 35 65 temperature (c) c pin bias current (na) 6801 g13 cell input = 3.6v c2 to c11 v temp1 , v temp2 c12 c1 v + (v) 10 v ref (v) 3.070 3.065 3.060 3.055 3.050 6801 g15 60 50 20 40 30 no load C40c 85c 25c C40 20 95 C10 50 110 125 580 C25 35 65 temperature (c) v ref (v) 3.070 3.065 3.060 3.055 3.050 6801 g16 no load 5 typical units v + (v) 10 v reg (v) 5.5 5.4 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 6801 g17 60 50 20 40 30 idle mode no load C40c 25c 85c 0 100 200 300 50 150 250 i load (a) v ref (v) 3.070 3.065 3.060 3.055 3.050 6801 g20 C40c 85c 25c
ltc6801 7 6801fb status output operating at 10khz uv/ov detection level thermal hysteresis uv/ov detection level thermal hysteresis v reg load regulation v reg output voltage typical performance characteristics v reg line regulation 6801 g22 2v/div 20s/div 100k load to v C sout sout v + (v) 10 v reg (v) 5.5 5.4 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 6801 g18 60 50 20 40 30 idle mode 4ma load to v C C40c 25c 85c 0 10 8 26 4 i load (ma) v reg (v) 5.5 5.0 4.5 4.0 6801 g19 idle mode v + = 60v v + = 10v 85c 25c C40c C40 20 95 C10 50 110 125 580 C25 35 65 temperature (c) v reg (v) 5.5 5.4 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 6801 g21 idle mode no load 4ma load v + = 60v v + = 35v v + = 10v C100 150 C50 50 200 0 100 change in detection level (ppm) number of units 16 14 12 10 8 6 4 2 0 6801 g23 t a = 85c to 25c C100 150 C50 50 200 0 100 change in detection level (ppm) number of units 20 18 16 14 12 10 8 6 4 2 0 6801 g24 t a = C40c to 25c
ltc6801 8 6801fb pin functions v + (pin 1): supply voltage. tied to the most positive po- tential in the battery stack. for example, the same potential as c12 when measuring a stack of 12 cells, or the same potential as c7 when measuring a stack of 7 cells. c12, c11, c1 (pin 2 to pin 13): cell voltage inputs. up to 12 cells can be monitored. the lowest potential is tied to v C . the next lowest potential is tied to c1 and so forth. due to internal overvoltage protection, each c input must be tied to a potential equal to or greater than the next lower numbered c input. see the ? gures in the applications information section for more details on connecting batteries to the ltc6801. see electrical characteristics table for voltage range and input bias current requirements. v C (pin 14): tied to the most negative cell potential (bot- tom of monitored cell stack). v temp1 , v temp2 (pin 15, pin 16): temperature sensor inputs. the adc will measure the voltages on v temp1 and v temp2 relative to v C . the adc measurements are referenced to the v ref pin voltage. therefore a simple thermistor and resistor combination connected to the v ref pin can be used to monitor temperature. these pins have a ? xed undervoltage threshold equal to one half v ref . a ? ltering capacitor to v C is recommended. temperature sensor input pins may be tied to v ref to disable. v ref (pin 17): reference output, nominally 3.058v. re- quires a 1f bypass capacitor to v C . the v ref pin can drive a 100k resistive load connected to v C . v ref must be buffered with an lt6003 ampli? er, or similar device to drive heavier loads. v ref becomes high impedance when the ic is disabled or idle between monitoring events. v reg (pin 18): regulator output, nominally 5v. requires a 1f bypass capacitor to v C . the v reg pin is capable of supplying up to 4ma to an external load and is continu- ally enabled. ein , ein (pin 19, pin 20): differential enable input. a clock signal greater than 2khz will enable the ltc6801. for operation with a single-ended enable signal (up to 10khz), drive ein and connect a 1nf capacitor from ein to v C . sout , sout (pin 21, pin 22): differential status output. swings v C to v reg . this output will toggle at the same fre- quency as ein/ ein when a valid signal is detected at sin/ sin and the battery stack being monitored is within speci? ed parameters, otherwise sout is low and sout high. sin , sin (pin 23, pin 24): differential status input from the ic above. to indicate that the stack is good, sin must be the same frequency and phase as ein. see applications circuits for interfacing sin to the sout above. eout , eout (pin 25, pin 26): a buffered version of ein/ ein . swings v C to v reg . must be capacitively coupled to the ein/ ein inputs of the next higher voltage ltc6801 in a stack, or looped to sin/ sin of the same chip (pins 23, 24). dc (pin 27): duty cycle three-level input. this pin may be tied to v reg , v ref or v C . the dc pin selects the duty cycle of the monitoring function and has an internal pull- up to v reg . see table 3. sltok (pin 28): self test logic output. sltok is held high (v reg voltage) upon reset or successful completion of a self test cycle. a low output level (v C voltage) indicates the last self test cycle failed. slt (pin 29): self test open collector input/output. slt initiates a self test cycle when it is pulled low externally. when a high to low transition is detected, the next scheduled measurement cycle will be a self test cycle. slt indicates a self test cycle is in progress when pulled low internally. a self test is automatically initiated after 1024 measurement cycles. this pin has an internal pull-up to v reg . cc0, cc1 (pin 30, pin 31): cell count three-level inputs. these pins may be tied to v reg , v ref or v C . cc1 and cc0 select the number of cells attached to the device and each pin has an internal pull-up to v reg . see table 5. hyst (pin 32): hysteresis three-level input. this pin may be tied to v reg , v ref or v C . hyst selects the amount of hysteresis applied to the undervoltage and overvoltage threshold settings and has an internal pull-down to v C . see table 4.
ltc6801 9 6801fb pin functions uv0, uv1 (pin 33, pin 34): undervoltage three-level inputs. these pins may be tied to v reg , v ref or v C . uv1 and uv0 select the undervoltage threshold and each pin has an internal pull-up to v reg . see table 2. ov0, ov1 (pin 35, pin 36): overvoltage three-level inputs. these pins may be tied to v reg , v ref or v C . ov1 and ov0 select the overvoltage threshold and each pin has an internal pull-down to v C . see table 1. table 1. overvoltage inputs ov1 ov0 overvoltage threshold (v) v reg v reg 4.498 v reg v ref 4.403 v reg v C 4.307 v ref v reg 4.211 v ref v ref 4.116 v ref v C 4.020 v C v reg 3.924 v C v ref 3.828 v C v C 3.733 table 2. undervoltage inputs uv1 uv0 undervoltage threshold (v) v reg v reg 2.871 v reg v ref 2.680 v reg v C 2.489 v ref v reg 2.297 v ref v ref 2.106 v ref v C 1.914 v C v reg 1.723 v C v ref 1.531 v C v C 0.766 table 3. duty cycle select dc nominal cycle time* v reg 15.5ms v ref approximately 130ms v C approximately 500ms * cycle time based on ltc6801 measuring 12 cells and 2 temperatures. table 4. hysteresis select hyst uv hysteresis* ov hysteresis v reg 500mv 200mv v ref 250mv 100mv v C 0mv 0mv *uv hysteresis is disabled when the undervoltage threshold is set to 0.766v. table 5. cell count select cc1 cc0 cell count v reg v reg 12 v reg v ref 11 v reg v C 10 v ref v reg 9 v ref v ref 8 v ref v C 7 v C v reg 6 v C v ref 5 v C v C 4
ltc6801 10 6801fb block diagram 6801 bd c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 v + regulator digital comparators self test reference (ref2) reference 12 + C C + + C + C v C mux v reg v temp1 v temp2 v ref ov0 ov1 uv0 uv1 hyst cc1 cc0 dc slt sltok ein ein eout eout sin sin sout sout decoder uv/ov flags and control logic good adc the ltc6801 measures between 4 and 12 cell voltages and 2 temperature inputs. if all measurements are within an acceptable window, the ltc6801 will produce a differential clock output signal (sout, sout ). if any of the channels exceed user set upper and lower thresholds, a logic low signal is produced at sout.
ltc6801 11 6801fb block diagram of enable in/out and status in/out the frequency match detect output goes high when sin and ein are the same frequency sout is active when 1) ein is active 2) sin and ein are the same frequency 3) all readings are good the signal is high when all readings are good the clk detect output goes high when ein is 2khz to 40khz 6801 bda v reg v reg C + v reg v reg frequency match detect clk detect C + eout sin 300k 300k 300k 300k 300k 300k 300k 300k ein sout ein sin sout eout
ltc6801 12 6801fb overview the ltc6801 is designed as an easy to implement, low- cost battery stack monitor that provides a simple indica- tion of correct battery stack operation without requiring a microcontroller interface. for battery stack monitoring with cell voltage read back and discharge circuitry, refer to the ltc6802 battery stack monitor data sheet. the ltc6801 contains a 12-bit adc, a precision voltage reference, sampled comparator, high voltage multiplexer and timer/sequencer. during normal operation, the se- quencer multiplexes the adc inputs between each of the channel input pins in turn, performing a single compari- son to the undervoltage and overvoltage thresholds. the v temp inputs are also monitored for an undervoltage at a ? xed threshold of v ref /2. the presence of a status output clock indicates the system is ok. becase the status output is dynamic, it cannot get stuck in the ok state. stacked operation each ltc6801 monitors a group of up to 12 series con- nected cells. groups of cells can be connected in series or parallel to form a large battery pack. the ltc6801s can be daisychained with simple capacitive or transformer coupling. this allows every cell in a large battery pack to be monitored with a single signal. figure 2 illustrates monitoring of 36 series connected cells. to cancel systematic duty cycle distortion through the clock buffers, it is recommended that the clock lines are cross-coupled (eout goes to ein etc.) as they route up and down the stack as shown in figure 2. applications information independent operation figure 3 shows how three groups of 12 cells can be monitored independently. regulated outputs a regulated voltage is provided at the v reg pin, biased from the battery stack. the v reg pin can supply up to 4ma at 5v and may be used to power small external circuits. the regulated output remains at 5v continually, as long as the total stack voltage is between 10v and 50v. a low current, precision reference voltage is provided at the v ref pin, which can drive loads of greater than 100k. the v ref output is high impedance when the ltc6801 is idle. both the v reg and v ref pins must be bypassed to v C with a 1f capacitor. control inputs the ltc6801 thresholds are controlled by the uv1, uv0, ov1 and ov0 pins. these pins are designed to be tied directly to v reg , v ref or v C in order to set the comparison thresholds for all channels simultaneously. the pins are not designed to be variable. in particular, changes made to the pins while the chip is not in idle mode may result in unpredictable behavior. see tables 1 and 2 for setting and threshold information.
ltc6801 13 6801fb applications information enable inputs in order to support stacked operation, the ltc6801 is enabled through a differential signal chain encompassing the ein/ ein , eout/ eout , and sin/ sin pins. the ltc6801 will be enabled if a differential square wave with a frequency between 2khz and 40khz is applied at ein/ ein . otherwise, the ltc6801 will default to a low power idle mode. if the differential signal at sin/ sin is not equal in frequency to the differential signal output at eout/ eout , the ltc6801 will be enabled but sout will be held at 0v and sout will be held at v reg . for the simplest operation in a single chip con? guration, eout should be connected directly to sin and eout should be connected directly to sin , and a square wave with a frequency between 2khz and 40khz should be applied differentially to ein and ein . for enable clock frequencies up to 10khz, a single-ended square wave with a 5v swing may be used at ein while a 1nf capacitor is connected from ein to v C . status output if the chip is properly enabled (ein/ ein , sin/ sin are the same frequency), all cells are within the undervoltage and overvoltage thresholds, and the voltage at v temp1 and v temp2 is over one half v ref , the differential output at sout/ sout will toggle at the same frequency and in phase with the signal at ein/ ein . otherwise, sout will be low and sout will be high. the maximum delay between when a bad cell voltage occurs and when it is detected depends on the measure- ment duty cycle setting. the sout clock turns on or off at the end of each measurement cycle. figure 4 shows the maximum detection delay in continuous monitor mode (dc pin tied to v reg ). fault protection overview care should always be taken when using high energy sources such as batteries. there are countless ways that systems can be [mis-]con? gured during the assembly and service procedures that can impact a batterys long term performance. table 6 shows various situations to consider when planning protection circuitry. battery interconnection integrity please note: the last condition shown in the fmea table could cause catastrophic ic failures. in this case, the bat- tery string integrity is lost within a cell group monitored by an ltc6801. this condition could place excessive stress on certain cell input signal clamp-diodes and probably lead to ic failure. if this scenario seems at all likely in a particular application, series fuses and parallel schottky diodes should be connected as shown in figure 5 to limit stress on the ic inputs. the diodes used in this situation need current ratings suf? cient to open the protective fuse in the battery tap signal.
ltc6801 14 6801fb applications information figure 2. serial connection of status lines for multiple 6801s on the same pcb (simpli? ed schematic, not all components shown) top of stack bottom of stack clock out when all cells good user supplied clock in ov1 ov0 uv1 uv0 hyst cc1 cc0 slt sltok dc eout eout sin sin sout sout ein ein ltc6801 6801 f02 v + c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 v C v temp1 v temp2 v ref v reg ov1 ov0 uv1 uv0 hyst cc1 cc0 slt sltok dc eout eout sin sin sout sout ein ein ltc6801 v + c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 v C v temp1 v temp2 v ref v reg ov1 ov0 uv1 uv0 hyst cc1 cc0 slt sltok dc eout eout sin sin sout sout ein ein ltc6801 v + c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 v C v temp1 v temp2 v ref v reg figure 3. independent status lines for multiple 6801s on the same pcb (simpli? ed schematic, not all components shown) top of stack bottom of stack all clocks out when all cells good programmed conditions: continuous monitor mode ov = 4.116v uv = 2.106v hyst = 250mv (uv), 100mv (ov) cc = 12 user supplied clock in ov1 ov0 uv1 uv0 hyst cc1 cc0 slt sltok dc eout eout sin sin sout sout ein ein ltc6801 6801 f03 v + c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 v C v temp1 v temp2 v ref v reg ov1 ov0 uv1 uv0 hyst cc1 cc0 slt sltok dc eout eout sin sin sout sout ein ein ltc6801 v + c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 v C v temp1 v temp2 v ref v reg ov1 ov0 uv1 uv0 hyst cc1 cc0 slt sltok dc eout eout sin sin sout sout ein ein ltc6801 v + c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 v C v temp1 v temp2 v ref v reg
ltc6801 15 6801fb applications information figure 4. cell uv/ov detection delay in continuous monitor mode c1 c2 c3 c4 c5 c6 c7 complete measurement cycle 15.4 ms (~1.1ms per cell) sout status updated c8 c9 c10 c11 c12 t1 t2 c1 c2 6801 f04 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 t1 t2 c1 c2 c3 worst case error detection delay ~29.7ms note: sout is not to scale see electrical table for min/max specifications all cells good examples sout sout remains active (since nothing abnormal has been detected yet) ltc6801 reads a bad voltage on cell 1 sout stops at end of measurement cycle cell 1 goes bad immediately after it is read sout status updated
ltc6801 16 6801fb table 6. failure mechanism effect analysis (fmea) scenario effect design mitigation cell input open-circuit (random) power-up sequence at ic inputs clamp diodes at each pin to v + & v C (within ic) provide alternate powerpath. cell input open-circuit (random) differential input voltage overstress zener diodes across each cell voltage input pair (within ic) limit stress. top cell input connection loss (v + ) power will come from highest connected cell input clamp diodes at each pin to v + and v C (within ic) provide alternate powerpath. error condition will be indicated by all upstream and downstream units (no clock on sout/ sout ). bottom cell input connection loss (v C ) power will come from lowest connected cell input clamp diodes at each pin to v + and v C (within ic) provide alternate powerpath. error condition will be indicated by all upstream and downstream units (no clock on sout/ sout ). power input disconnection (amongst stacked units) loss of supply connections clamp diodes at each pin to v + and v C (within ic) provide alternate powerpath. error condition will be indicated by all upstream and downstream units (no clock on sout/ sout ). status link disconnection (between stacked units) break of daisy chain communication (no stress to ics) daisy chain will be broken and error condition will be indicated by all upstream and downstream units (no clock on sout/ sout ). short between any two con? guration inputs power supplies connected to pins will be shorted if v ref or v reg is shorted to v C , supply will be removed from internal circuitry and error condition will be indicated by all upstream and downstream units (no clock on sout/ sout ). if v ref is shorted to v reg , a self test error will be ? agged. open connection on con? guration input control input will be pulled towards positive or negative potential depending on pin control input will be pulled to a more stringent condition (larger number of channels, higher uv threshold, lower ov threshold, shorter duty cycle, etc. ensuring either more stringent monitoring or error condition will be indicated by all upstream and downstream units (no clock on sout/ sout ). cell-pack integrity, break between stacked units daisy-chain voltage reversal up to full stack potential full stack potential may appear across status/ enable isolation devices, but will not be seen by the ic. isolation capacitors should therefore be rated to withstand the full stack potential. cell-pack integrity, break within stacked unit cell input reverse overstress add battery tap fuses and schottky diodes in parallel with the cell inputs to limit stress on ic. diode and connections must handle current suf? cient to open fuse applications information
ltc6801 17 6801fb 6801 f06 ltc6801 slt hyst uv0 cc1 cc0 sltok dc c1 c2 c3 c4 c5 c6 c7 ov0 v ref v temp2 v reg ov1 uv1 ein sout sout ein v temp1 eout eout sin sin c8 c9 c10 c11 c12 v + zclamp zclamp zclamp v C applications information figure 5. using fuses and diodes for cell input protection (one cell connection shown) 6801 f05 protect against breaks here cn cn C 1 internal protection structure the ltc6801 incorporates a number of protective struc- tures, including parasitic diodes, zener-like overvoltage suppressors, and other internal features that provide protection against esd and certain overstress conditions that could arise in practice. figure 6 shows a simpli? ed internal schematic that indicates the signi? cant protective structures and their connectivity. the various diodes indi- cate the approximate current versus voltage characteristics that are intrinsic to the part, which is useful in analyzing responses to certain external stresses, such as during a hot-start scenario. self test circuitry the ltc6801 has internal circuitry that performs a periodic self test of all measurement functions. the ltc6801 self test circuitry is intended to prevent undetectable failure modes. accuracy and functionality of the voltage refer- ence and comparator are veri? ed, as well as functionality of the high voltage multiplexer and adc decimation ? lter. additionally, open connections on the cell input pins c1 to c11 are detected (open connections on v C or c12/v + will cause an undervoltage failure during the normal measurement cycle). figure 6. internal protection structures
ltc6801 18 6801fb self test pins the slt pin is used to initiate a self test. it is con? gured as an open collector input/output. the pin should be nor- mally tied to v reg with a resistor greater than or equal to 100k or ? oated. the pin may be pulled low at any time to initiate a self test cycle. the device will automatically initiate a self test if slt has not been externally activated for 1024 measurement cycles, and pull down the slt pin internally to indicate that it is in self test mode. the sltok pin is a simple logic output. if the previous self test failed the output is held low, otherwise the output will be high. the sltok pin is high upon power-up. the sltok output can be connected to a microcontroller through an isolation path. the ltc6801 status output will remain active while the sltok pin is low. the ltc6801 will continue to monitor cells if the self test fails. if the next self test passes, the sltok output returns high. reference and comparator veri? cation a secondary internal bandgap voltage reference (ref2) is included in the ltc6801 to aid in veri? cation of the reference and comparator. during the self test cycle, the comparator and main reference are used to measure the ref2 voltage. to verify the comparator functionality, the upper and lower thresholds are ? rst set in a close window around the expected ref2 voltage and the comparator output is veri? ed. then the upper threshold is set below the ref2 voltage and the comparator output is veri? ed again. lastly, the lower threshold is set above the ref2 voltage and the comparator output is veri? ed a third time. the self test guarantees that v ref is within 5% of the speci? ed nominal value. also, this test guarantees the analog portion of the adc is working. high voltage multiplexer veri? cation the most dangerous failure mode of the high voltage multiplexer would be a stuck bit condition in the address decoder. such a fault would cause some channels to be measured repeatedly while other channels are skipped. a skipped channel could mean a bad cell reading is not detectable. other multiplexer failures, like the simultaneous selection of multiple channels, or shorts in the signal path, would result in an undervoltage or overvoltage condition on at least one of the channels. the ltc6801 incorporates circuitry to ensure that all requested channels are measured during each measurement cycle and none are skipped. if a channel is skipped, an error is ? agged during the self test cycle. adc decimation filter veri? cation the adc decimation ? lter test veri? es that the digital cir- cuits in the adc are working, i.e. there are no stuck bits in the adc output register. during each self test cycle, the ltc6801 feeds two test waveforms into the adc. the internally generated waveforms were designed to generate complementary zebra patterns (alternating 0s and 1s) at the adc output. if either of the waveforms generates an incorrect output value, an error is ? agged during the self test cycle. open cell connection detection the open connection detection algorithm ensures that an open circuit is not misinterpreted as a valid cell reading. applications information
ltc6801 19 6801fb applications information in the absence of external noise ? ltering, the input resis- tance of the adc will cause open wires to produce a near zero reading. this reading will cause an undervoltage failure during the normal measurement cycle. some applications may include external noise ? ltering to improve the quality of the voltage comparisons. when an rc network is used to ? lter noise, an open wire may not produce a zero reading because the comparator input resistance is too large to discharge the capacitors on the input pin. charge may build up on the open pin during successive measurement cycles to the extent that it could indicate a valid cell voltage reading. during each self test cycle, the ltc6801 will sink 100a to v C from each side of the cell being measured. the undervoltage threshold is not checked during the self test because the 100a pull-down current would cause false failures in some cases. if an input is open, this current will discharge any ? ltering capacitors and cause the input to ? oat down to approximately 0.7v below the next lower cell input. in most cases, the cell voltage of the cell above the open input will exceed the overvoltage threshold and ? ag a self test error. during the normal measurement cycle, the ltc6801 will sink 1a to v C from each side of the cell being measured. if the cell voltages are low enough that an open wire is not detected as an overvoltage during self test, this current will cause the cell input to settle to a voltage low enough to trigger an undervoltage condition during the normal measurement cycle. note, an open cell connection may not be detected when the uv = 0.766v setting is used. for all other uv settings, an open cell connection will result in either a self test error or no sout clock. using the ltc6801 with other battery monitors when used in combination with an ltc6802-1, it is possible to check the ltc6801 self test result via the ltc6802-1 and its isolated spi. as shown in figure 7, the sltok output is tied to the gpio2 pin on the ltc6802-1. sltok will remain high as long as it is passing the self test. a self test will occur automatically every 1024 measurement cycles (17 seconds to 9 minutes, depending on measurement duty cycle). a self test can be initiated by a falling edge on slt , via the ltc6802-1 gpio1 line. a self test will start after the current measurement cycle is complete, and the sltok status will be valid when the self test completes. the worst case delay before sltok is valid in continuous monitor mode is approximately 15ms for the current cycle to complete plus 17ms for the self test to complete. the 6802-1 can measure the ltc6801 reference, which will independently test the analog circuitry of the ltc6802. figure 7. interconnection of an ltc6802-1 and ltc6801 for self test. csbo sdoi scko v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 csbi sdo sdi scki v mode gpio2 gpio1 wdtb mmb tos v reg v ref v temp2 v temp1 nc v C s1 c1 s2 c2 s3 c3 ltc6802-1 6801 f07 v + c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 v C v temp1 v temp2 v ref v reg c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 ov1 ov0 uv1 uv0 hyst cc1 cc0 slt sltok dc eout eout sin sin sout sout ein ein ltc6801 in out 1f 1m 1f 100k v ref cmpd6263
ltc6801 20 6801fb 2.2k 10k ntc b = 3380 10k ntc b = 3380 2.2k 0.5f v + c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 v C v temp1 v temp2 v ref v reg ov1 ov0 uv1 uv0 hyst cc1 cc0 slt sltok dc eout eout sin sin sout sout ein ein ltc6801 6801 f10 0.5f + C lt6003 applications information cell-voltage filtering the ltc6801 employs a sampling system to perform its analog-to-digital conversions and provides a conversion result that is essentially an average over the 0.5ms conver- sion window. if there is signi? cant noise at frequencies near 500khz there may be aliasing in the delta-sigma modulator. a lowpass ? lter with 30db attenuation at 500khz may be bene? cial. since the delta-sigma integration bandwidth is about 1khz, the ? lter corner need not be lower than this to assure accurate conversions. series resistors of 1k may be inserted in the input paths without introducing measurement error. shunt capacitors may be added from the cell inputs to v C , creating rc ? lter- ing as shown in figure 8. the combination of 1k and 10nf is recommended as a robust, cost effective noise ? lter. measuring various cell counts the ltc6801 is designed to measure up to 12 cells de- pending on the state of the cc pins (see table 5). when using an ltc6801 con? gured for measuring less than 12 cells, for instance choosing to measure 8 cells by figure 10. buffering v ref for higher-current sensors. two independent probes with a +70c trip point figure 9. driving thermistors directly from v ref . two independent probes with a +60c trip point 100k 500k ntc b = 4567 500k ntc b = 4567 100k 1f v + c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 v C v temp1 v temp2 v ref v reg ov1 ov0 uv1 uv0 hyst cc1 cc0 slt sltok dc eout eout sin sin sout sout ein ein ltc6801 6801 f09 1f figure 8. adding rc filtering to the cell inputs 6801 f08 v C c1 c2 c3 1k 10nf 1k 10nf 1k 10nf tying both cc1 and cc0 to the v ref pin, the highest cell potential (in this case c8) must be connected to the v + pin for proper operation. unused cell connection pins (in this case c9 to c12) may be left ? oating or may also be tied to the highest cell potential.
ltc6801 21 6801fb reading external temperature probes the ltc6801 includes two channels of adc input, v temp1 and v temp2 , that are intended to monitor thermistors (tempco about C4%/c generally) or diodes (C2.2mv/c typical) located within the cell array. sensors can be powered directly from v ref as shown in figure 9 (up to 30a typical). the temperature measurement inputs (v temp1 , v temp2 ) of the ltc6801 are comparator input channels with a voltage threshold of one-half v ref . input voltages above half v ref are considered good. voltages below the one-half v ref threshold are considered a fault condition. the inputs may be used in combination with resistors, thermistors, or diodes to sense both an upper and lower temperature limit. figure 9, figure 10 and figure 11 illustrate some possibilities. to ignore these inputs simply connect v temp1 and v temp2 to v ref . a ? ltering capacitor to v C is recom- mended to minimize the error caused by the approximately 700k input impedance of the adc. for sensors that require higher drive currents, a buffer ampli? er may be used as shown in figure 10. power for the sensor is actually sourced indirectly from the v reg pin in this case. probe loads up to about 1ma maximum are supported in this con? guration. since v ref is shut down while the ltc6801 is idle between measurement cycles, the thermistor drive is also shut off and thus power dis- sipation is minimized. since v reg remains always-on, the buffer op amp (lt6003 shown) is selected for its ultralow current consumption (10a). for circuits that include ? ltering capacitance, note that only the fastest dc setting (v reg connection) will keep v ref steady and allow the v temp voltages to settle. to use the lower power dc settings, v ref must be buffered (see figure 10), so that a low impedance is presented to the adc, with a time constant of no more than about 1ms. advantages of delta-sigma adcs the ltc6801 employs a delta-sigma analog to digital converter for voltage measurement. the architecture of delta-sigma converters can vary considerably, but the common characteristic is that the input is sampled many times over the course of a conversion and then ? ltered or averaged to produce the digital output code. figure 11. sensing both upper and lower temperature thresholds. this example monitors a C20c to +60c window detector. the thermistors should be in close proximity 100k 500k ntc b = 4567 100k ntc b = 4250 1150k 1f v + c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 v C v temp1 v temp2 v ref v reg ov1 ov0 uv1 uv0 hyst cc1 cc0 slt sltok dc eout eout sin sin sout sout ein ein ltc6801 6801 f11 1f applications information
ltc6801 22 6801fb for a given sample rate, a delta-sigma converter can achieve excellent noise rejection while settling completely in a single conversion. this is particularly important for noisy automotive systems. other advantages of delta-sigma converters are that they are inherently monotonic, mean- ing they have no missing codes, and they have excellent dc speci? cations. the ltc6801s adc has a second order delta-sigma modulator followed by a sinc2, ? nite impulse response (fir) digital ? lter, with a lowpass bandwidth of 1khz. the front-end sample rate is 512ksps, which greatly reduces input ? ltering requirements. a simple 16khz, 1 pole ? lter composed of a 1k resistor and a 10nf capacitor at each input will provide adequate ? ltering for most applications. these component values will not degrade the dc accuracy of the adc. each conversion consists of two phases C an autozero phase and a measurement phase. the adc is autozeroed at each conversion, greatly improving cmrr. using transformers for galvanic isolation as shown in figure 12, small gate-drive signal transform- ers can be used to interconnect devices and transport the enable and sense signals safely across an isolation barrier. driving a transformer with a squarewave requires transient currents of several ma and frequency of operation at 20khz or higher. since the output pins of the ltc6801 are current limited at <1ma, a small external gate pair (nc7wz17 dual buffer) is used to provide the needed drive current. 330 resistors are placed in series with each buffer output to optimize current ? ow into the transformer primary and a coupling capacitor provides prevention of current ? ow in static conditions. the secondary side is wired in a cen- ter-tapped con? guration to terminate the common mode voltage and thus suppress noise pickup. the differential signal is terminated into 1500 to optimize the peak signal swing for the ic input (to about 4v p-p ). internal biasing features of the ic inputs maintain an optimal dc common mode level at the transformer secondary. intercommunication using data isolators as shown in figure 13, an inexpensive and compact 2-channel data isolator is used to communicate the enable and the sense clocking signals between devices. the wiring carries isolator power and return plus two single-ended logic signals that are completely isolated at the upper device interface, so the signals are effectively differential from a common mode ingress perspective. the isolator provides excellent rejection of noise between battery groups, but consumes a few ma when operating, so a conventional opto-coupler and a few discretes provide a power-down scheme for periods where no monitoring is needed. since the required current would load down v reg if used directly, the npn transistor is used to form a quasi-regulated 4.3v supply drawing from the full battery group potential, also moving signi? cant thermal loading outside the ic. the pmos fet is a low resistance switch controlled by the opto-coupler output. since the opto-coupler is used to switch only a small current, the led need only be driven with ~500a. powering down the bottom-of-stack isolator on the host p side automatically powers down the entire isolator chain. demo board circuit an ltc6801 demonstration circuit is shown in figure 14. the circuit includes a 10khz oscillator (u2) for the enable excitation and an led (d15, driven by q1) to indicate the state of the status outputs, plus an assortment of important protection components to ensure robust operation and hot-plugging of cell connections. series resistors (r14 to r21) provide a controlled coupling capacitor (c14 to c17) current in the inter-ic connections during startup or other abrupt potential changes, and as- sociated clamp diodes (d13 and d14 quad array devices) redirect charge/surge current around the ic. input ? lters to each cell (r1, c1 to r12, c12) also use 6.2v zener diodes (d1 to d12) to prevent overstress to the internal esd clamps. the v + input ? lter (r13, c13) has the same time constant as the adc input ? lters so that the v + and c12 pins tend to track during start-up or transients, minimizing stress and adc error. applications information
ltc6801 23 6801fb figure 12. using transformers for galvanic isolation applications information ov1 ov0 uv1 uv0 hyst cc1 cc0 slt sltok dc eout eout sin sin sout sout ein ein ltc6801 v + c12 c11 c10 c9 v + nc7wz17 p0544nl p0544nl gnd c8 c7 c6 c5 c4 c3 c2 c1 v C v temp1 v temp2 v ref v reg 10nf 10nf 330 330 v + nc7wz17 gnd 330 330 enc2 + enc2 C s2 + s2 C 1.5k 6801 f12 s_host + en_host C s_host C en_host + ? ? ? 1f 100nf 100nf 1.5k to next circuit ov1 ov0 uv1 uv0 hyst cc1 cc0 slt sltok dc eout eout sin sin sout sout ein ein ltc6801 v + c12 c11 c10 c9 p0544nl c8 c7 c6 c5 c4 c3 c2 c1 v C v temp1 v temp2 v ref v reg 10nf v + nc7wz17 gnd 330 330 enc1 + enc1 C s1 + s1 C 1.5k ? ? ? 1f 100nf ? ? ?
ltc6801 24 6801fb figure 13. ic to ic communication using data isolators to next circuit ov1 ov0 uv1 uv0 hyst cc1 cc0 slt sltok dc eout eout sin sin sout sout ein ein ltc6801 v + c12 c11 c10 c9 v dd2 b1 b2 gnd2 si8421 moc207-m si2351ds v dd1 a1 a2 gnd1 c8 c7 c6 c5 c4 c3 c2 c1 1f 1nf czt5551 1nf 1f v C v temp1 v temp2 v ref v reg 1f 100 33k 100 6.8k com2 enable2 sense2 viso2 ov1 ov0 uv1 uv0 hyst cc1 cc0 slt sltok dc eout eout sin sin sout sout ein ein ltc6801 6801 f13 v + c12 c11 c10 c9 v dd2 b1 b2 gnd2 comhost enablehost sensehost v cchost si8421 moc207-m si2351ds v dd1 a1 a2 gnd1 c8 c7 c6 c5 c4 c3 c2 c1 1f 1nf czt5551 1nf 1f v C v temp1 v temp2 v ref v reg 1f 100 33k 100 6.8k com1 enable1 sense1 viso1 applications information
ltc6801 25 6801fb applications information 1 3 5 se diff 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 c19 1f 50v c18 1f 50v c21 1nf 100v r26 1.15m r25 100k ntc c20 1nf 100v r23 22.6k r24 100k ntc r22 1.5k 1% r27 10k 1% d15 led1 (grn) c22 10nf 50v p1 edge finger j1 header c1 10nf 100v c2 10nf 100v d1 to d12: bzt52c6v28 c3 10nf 100v d1 r1 1k d2 r2 1k d3 1 1 1 3 2 2 r3 1k c4 10nf 100v d4 r4 1k c5 10nf 100v d5 r5 1k c6 10nf 100v d6 r6 1k c7 10nf 100v d7 r7 1k c8 10nf 100v d8 r8 1k c9 10nf 100v d9 r9 1k c10 10nf 100v d10 r10 1k c11 10nf 100v d11 r11 1k c12 10nf 100v d12 r12 1k 1 3 5 1 2 3 2 4 6 6 5 4 out gnd div v + grd set 1 3 5 on off 1 3 5 2 4 6 ltc6801 1 3 5 2 4 6 1 3 5 7 9 11 13 2 4 6 8 10 12 14 v ref jp8 dc jp7 cc0 jp6 cc1 jp5 hyst jp4 uv0 jp3 uv1 jp2 ov0 jp1 ov1 ltc6801ig e1 v reg gnd note: if the dc pin is tied to v ref or v C , v temp1 and v temp2 will have additional measurement error due to insufficient settling (see reading external temperature probes) v C e2 slt e3 sltok jp12 osc jp10 einx jp11 le0 q1 2n7002k d16 cmhd457 off on u2 ltc6906cs6 r29 1m r28 1m e4 e5 e6 e7 sout einx ein soutx d13 prtr5vou4d j3 top jp9 topi/o loop link r14 100 r15 100 r16 100 r17 100 6801 f12 ov1 ov0 uv1 uv0 hyst cc1 cc0 slt sltok dc eout eout sin sin sout sout ein ein v + c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 v C v temp1 v temp2 v ref v reg c23 1nf c13 100nf 100v r13 100 1 3 5 2 4 6 r18 100 r19 100 r20 100 r21 100 1 3 5 2 4 6 1 3 5 7 9 11 13 2 4 6 8 10 12 14 j2 bottom 1 3 5 2 4 6 1 3 5 2 4 6 1 3 5 2 4 6 1 3 5 2 4 6 1 2 3 6 5 4 1 2 3 6 5 4 d14 prtr5vou4d c17 820pf 500v c16 820pf 500v c15 820pf 500v c14 820pf 500v figure 14.schematic of ltc6801 demo circuit
ltc6801 26 6801fb package description g package 36-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640) g36 ssop 0204 0.09 C 0.25 (.0035 C .010) 0 o C 8 o 0.55 C 0.95 (.022 C .037) 5.00 C 5.60** (.197 C .221) 7.40 C 8.20 (.291 C .323) 1234 5 6 7 8 9 10 11 12 14 15 16 17 18 13 12.50 C 13.10* (.492 C .516) 25 26 22 21 20 19 23 24 27 28 29 30 31 32 33 34 35 36 2.0 (.079) max 0.05 (.002) min 0.65 (.0256) bsc 0.22 C 0.38 (.009 C .015) typ millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 p 0.03 0.65 bsc 5.3 C 5.7 7.8 C 8.2 recommended solder pad layout 1.25 p 0.12
ltc6801 27 6801fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 5/10 h-grade part added. re? ected throughout the data sheet. 1 to 28 b 7/10 updated v reg conditions. updated table 3 3 9
ltc6801 28 6801fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0710 rev b ? printed in usa related parts typical application part number description comments ltc6802-1 multi-cell battery stack monitor with a stackable serial interface complete battery monitoring ic with 0.25% cell measurement accuracy. level-shifting serial interface allows multiple ltc6802-1 devices to be daisy- chained without opto-couplers or isolators ltc6802-2 multi-cell battery stack monitor with an individually addressable serial interface functionally equivalent to ltc6802-1: parallel connection between microcontroller and multiple ltc6802-2 devices figure 15. alarm quali? cation filter/status indicator 6801 f15 filtered status (low = ok) 2n7002 1.5k 10k v reg 5v sout led_green cmhd457 1m 10nf

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