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| - 1 - samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference purposes only. all information discussed herein is provided on an "as is" basis, without warranties of any kind. this document and all information discussed herein remain the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered trademarks belong to their respective owners. 2011 samsung electronics co., ltd. all rights reserved. rev. 1.1, dec 2011 klmxgxge4a-a001 samsung emmc product family e.mmc 4.41 specification compatibility datasheet http://
- 2 - datasheet emmc rev.1.1 klmxgxge4a-a001 re v is ion his t ory revision no. history draft date remark editor 0.0 1. initial issue sep. 28, 2011 t arget s.m.lee 1.0 1, initialization time is deleted in table 22 2. performance is updated with measured value in chapter 5.2.3 3. sec_trim_mult is chagend to 0x11 in chapter 6.4 4. write timeout is updated in chapter 7.1 nov. 16, 2011 final s.m.lee 1.1 1. max. enhanced partition size of 16gb is changed in table 25 2. max_enh_size_mult of 16gb is changed to 0xba in chapter 6.4 dec. 12, 2011 final s.m.lee - 3 - datasheet emmc rev.1.1 klmxgxge4a-a001 re v is ion his t ory appendix(1.0) re v is ion his t ory appendix(1.1) before(ver.0.0) after(ver.1.0) before(ver.1.0) after(ver.1.1) table of contents - 5 - datasheet klmxgxge4a-a001 emmc rev. 1.1 1.0 product list ............................................................................................................... ........................................... 4 2.0 key features ............................................................................................................... .......................................... 4 3.0 package configurations ..................................................................................................... ............................ 5 3.1 169 ball pin configuration ................................................................................................. ...................................... 5 3.1.1 12mm x 16mm x 1.0mm package dimension .................................................................................... ............... 6 3.1.2 12mm x 16mm x 1.2mm package dimension .................................................................................... ............... 7 3.2 product architecture ....................................................................................................... ......................................... 8 4.0 e.mmc 4.41 features ........................................................................................................ .......................................... 9 4.1 data write ................................................................................................................. ............................................... 9 4.2 reliable write ............................................................................................................. ............................................. 10 4.3 secure trim ................................................................................................................ ............................................. 10 4.4 high priority interrupt .................................................................................................... ........................................... 10 4.5 background operation ....................................................................................................... ...................................... 12 5.0 technical notes ............................................................................................................ .............................................. 13 5.1 s/w agorithm ............................................................................................................... ........................................... 13 5.1.1 partition management ..................................................................................................... .................................. 13 5.1.1.1 boot area partition and rpmb area partition ............................................................................ ................ 13 5.1.1.2 enhanced partition (area) .............................................................................................. ............................ 13 5.1.2 write protect management ................................................................................................. ............................... 14 5.1.2.1 user area write protection ............................................................................................. ............................ 14 5.1.2.2 boot partition write protection ........................................................................................ ............................ 14 5.1.3 boot operation ........................................................................................................... ........................................ 15 5.1.4 wear leveling ............................................................................................................ ....................................... 16 5.1.5 user density ............................................................................................................. ......................................... 16 5.1.6 auto power saving mode ................................................................................................... ............................... 17 5.1.7 end of life management ................................................................................................... ................................ 17 5.2 smart report ............................................................................................................... ............................................ 17 5.2.1 smart report sequence .................................................................................................... ................................ 17 5.2.2 smart report output data (for customer) .................................................................................. ..................... 18 5.2.3 performance .............................................................................................................. ........................................ 18 6.0 register value ............................................................................................................. ........................................ 19 6.1 ocr register ............................................................................................................... ........................................... 19 6.2 cid register ............................................................................................................... ............................................. 19 6.2.1 product name table (in cid register) ..................................................................................... .......................... 19 6.3 csd register ............................................................................................................... ............................................ 20 6.4 extended csd register ...................................................................................................... .................................... 21 7.0 ac parameter ............................................................................................................... ......................................... 24 7.1 time parameter ............................................................................................................. .......................................... 24 7.2 bus timing parameter ....................................................................................................... ...................................... 24 7.3 bus timing for dat signals during 2x data rate operation ................................................................... .................... 26 7.3.1 dual data rate interface timings ......................................................................................... ............................... 26 7.4 bus signal levels .......................................................................................................... ............................................ 27 7.4.1 open-drain mode bus signal level ......................................................................................... ............................ 27 7.4.2 push-pull mode bus signal level.high-voltage multimediacard .............................................................. ........... 27 7.4.3 push-pull mode bus signal level.dual-voltage multimediacard .............................................................. ........... 27 7.4.4 push-pull mode bus signal level.emmc .................................................................................... ....................... 28 8.0 dc parameter ............................................................................................................... ........................................ 29 8.1 active power consumption during operation .................................................................................. ........................ 29 8.2 standby power consumption in auto power saving mode and standby state ..................................................... ... 29 8.3 sleep power consumption in sleep state .................................................................................... .......................... 29 8.4 supply voltage ............................................................................................................. ........................................... 29 8.5 bus operating conditions ................................................................................................... ..................................... 29 8.6 bus signal line load ....................................................................................................... ........................................ 30 9.0 emmc connection guide ..................................................................................................... ..................................... 31 9.1 x8 support host connection guide ........................................................................................... ............................... 31 9.2 x4 support host connection guide ........................................................................................... ............................... 31 - 4 - datasheet klmxgxge4a-a001 emmc rev. 1.1 introduction the samsung emmc is an embedded mmc solution designed in a bga package form. emmc operation is identical to a mmc card and th erefore is a simple read and write to memory using mmc protocol v4.41 which is a industry standard. emmc consists of nand flash and a mmc controller. 3v supply voltage is required for the nand area (vddf) whereas 1.8v or 3v du al supply voltage (vdd) is supported for the mmc controller. maximum mmc interface frequency of 52mhz and maximum bus widths of 8 bit are support ed. there are several advantages of using emmc. it is easy to use as the mmc interface allows easy integration with any microproce ssor with mmc host. any revision or amendment of nand is invisible to the host as the embedded mmc controller insulates nand technology from the ho st. this leads to faster product development as well as faster times to market. the embedded flash mangement software or ftl(flash transition layer) of emmc manages wear leveling, bad block management and e cc. the ftl supports all features of the samsung nand flash and achieves optimal performance. 1.0 product list [table 1] product list 2.0 key features ?? multimediacard system specification ver. 4.41 compatible. detail description is referenced by jedec standard ?? samsung emmc supports below special features which are being discussed in jedec - high priority interrupt scheme is supported - back ground operation is supported. ? full backward compatibility with previous multimediacard system ( 1bit data bus, multi-emmc systems) ? data bus width : 1bit (default) , 4bit and 8bit ? mmc i/f clock frequency : 0 ~ 52mhz mmc i/f boot frequency : 0 ~ 52mhz ? temperature : operation(-25 ? c ~ 85 ? c), storage without operation (-40 ? c ~ 85 ? c) ? power : interface power vdd (1.70v ~ 1.95v or 2.7v ~ 3.6v) , memory power vddf(2.7v ~ 3.6v) capacities emmc part id nand flash type user density (%) power system package size pin configuration 16gb KLMAG2GE4A-A001 64gb mlc x 2 91.0% - interface power : vdd (1.70v ~ 1.95v or 2.7v ~ 3.6v) - memory power : vddf (2.7v ~ 3.6v) 12mm x 16mm x 1.0mm 169fbga 32gb klmbg4ge4a-a001 64gb mlc x 4 64gb klmcg8ge4a-a001 64gb mlc x 8 12mm x 16mm x 1.2mm - 5 - datasheet klmxgxge4a-a001 emmc rev. 1.1 3.0 package configurations 3.1 169 ball pin configuration [table 2] 169 ball information figure 1. 169-fbga pin no name pin no name k6 vdd aa5 vdd t10 vddf w4 vdd k2 vddi y4 vdd r10 vss aa3 vdd w5 cmd u9 vddf w6 clk m6 vddf h3 dat0 n5 vddf h4 dat1 u8 vss h5 dat2 m7 vss j2 dat3 aa6 vss j3 dat4 p5 vss j4 dat5 y5 vss j5 dat6 k4 vss j6 dat7 y2 vss h6 rfu aa4 vss h7 rfu u5 rstn k5 rfu m5 rfu m8 rfu m9 rfu m10 rfu n10 rfu p3 rfu p10 rfu r5 rfu t5 rfu u6 rfu u7 rfu u10 rfu aa7 rfu aa10 rfu dnu dnu dnu dnu dnu dnu rfu rfu rfu vss vddf rfu rfu vddf rfu vss rfu vss rfu rfu dat7 vdd vddf rfu clk vss dat2 dat6 rfu rfu vddf vss rfu rfu rstn cmd vss vdd dat1 dat5 v ss vdd vdd vss dat4 vdd dat3 vss a b c d e f g h j k l m n p dat0 1 23 4 56 78 9 1 0 1 1 1 2 1 3 1 4 v dd i r t u v w y aa ab ac ad ae af ag ah dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu rfu rfu rfu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu nc - 6 - datasheet klmxgxge4a-a001 emmc rev. 1.1 3.1.1 12mm x 16mm x 1.0mm package dimension 0.08 max 0.90 0.10 top view 12.00 0.10 16.00 0.10 #a1 16.00 0.10 #a1 index mark bottom view 0.22 0.05 14 1 42 765 3 8 9 11 13 12 10 0.50 x 13 = 6.50 12.00 0.10 a b (datum a) 0.50 0.25 0.50 x 13 = 6.50 16.00 0.10 0.50 (datum b) 169- ? 0.30 0.05 0.2 m a b ? 1.75 0.25 0.75 2.75 3.25 5.25 6.25 6.75 a b c e d f h j l k n p g m r t u w v y ab ac ae ad ag ah aa af side view figure 2. 12mm x 16mm x 1.0mm package dimension - 7 - datasheet klmxgxge4a-a001 emmc rev. 1.1 3.1.2 12mm x 16mm x 1.2mm package dimension 0.08 max 1.10 0.10 top view 12.00 0.10 16.00 0.10 #a1 16.00 0.10 #a1 index mark bottom view 0.22 0.05 14 1 42 765 3 8 9 11 13 12 10 0.50 x 13 = 6.50 12.00 0.10 a b (datum a) 0.50 0.25 0.50 x 13 = 6.50 16.00 0.10 0.50 (datum b) 169- ? 0.30 0.05 0.2 m a b ? 1.75 0.25 0.75 2.75 3.25 5.25 6.25 6.75 a b c e d f h j l k n p g m r t u w v y ab ac ae ad ag ah aa af side view figure 3. 12mm x 16mm x 1.2mm package dimension - 8 - datasheet klmxgxge4a-a001 emmc rev. 1.1 3.2 product architecture control signal data bus mmc controller vddf core regulator core memory nand i/o block mmc i/o block logic block (required for 3.3v vdd) vdd reset vddi clk cmd dat[7:0] c reg - emmc consists of nand flash and controller. vdd is for controller power and vddf is for flash power figure 4. emmc block diagram - 9 - datasheet klmxgxge4a-a001 emmc rev. 1.1 4.0 e.mmc 4.41 features 4.1 data write host can configure reliability mode to protect existing data per each partition. this relibility mode has to be set before partitioning is completed. this reliability setting only impacts the reliability of the main user area and the general purpose partitions. [table 3] ext_csd value for reliability setting in write operation explanation of each field in the upper table is mentioned below [table 4] definition of ext_csd value for reliability setting the below table shows each field for we_rel_set [table 5] description of each field for we_rel_set name field size (bytes) cell type ext_csd-slice value data reliability supports wr_rel_param 1 r 166 0x05 data reliability configuration wr_rel_set 1 r/w 167 0x1f fields definitions hs_ctrl_rel 0x0: all the wr_data_rel parameters in the wr_rel_set registers are read only bits. 0x1: all the wr_data_rel parameters in the wr_rel_set registers are r/w. en_rel_wr 0x0: the device supports the previous definition of reliable write. 0x1: the device supports the enhanced definition of reliable write name field bit size type write data reliability (user area) wr_data_rel_usr 0 1 r (if hs_ctrl_rel=0) r/w (if hs_ctrl_rel=1) write data reliability partition 1 wr_data_rel_1 1 1 r (if hs_ctrl_rel=0) r/w (if hs_ctrl_rel=1) write data reliability partition 2 wr_data_rel_2 2 1 r (if hs_ctrl_rel=0) r/w (if hs_ctrl_rel=1) write data reliability partition 3 wr_data_rel_3 3 1 r (if hs_ctrl_rel=0) r/w (if hs_ctrl_rel=1) write data reliability partition 4 wr_data_rel_4 4 1 r (if hs_ctrl_rel=0) r/w (if hs_ctrl_rel=1) reserved - 7:5 - - - 10 - datasheet klmxgxge4a-a001 emmc rev. 1.1 4.2 reliable write [table 6] ext_csd value for reliable write reliable write with en_rel_wr is 0x1 supports atomicity of sector unit. the block size defined by set_blocklen (cmd16) is ignored and reliable write is executed as only 512 byte length. there is no l imit on the size of the reliable write. [table 7] ext_csd value for reliable write 4.3 secure trim secure trim operation consists of secure trim step1 and secure trim step2. in secure trim step 1 the host defines the range of write blocks that it would like to mark for the secure purge. [table 8] ext_csd value for secure trim area marked by secure trim step1 is shown as ext_csd[181](erased_mem_cont) before secure trim step2 is completed. when secure trim step2 is issued, if there is no data marked by secure trim step1, secure trim step2 does not work. 4.4 high priority interrupt high priority interrupt is to stop ongoing operation and perform read operation with high priority command set for high priority interrupt operation is the below [table 9] command list for high priority interrupt interruptible commands by read while write operation are the below. [table 10] list of interruptible command name field size (bytes) cell type csd-slice value data reliability supports wr_rel_param 1 r 166 0x05 name field size (bytes) cell type csd-slice value reliable write sector count rel_wr_sec_c 1 r [222] 0x01 field definitions value sec_trim_mult secure trim step2 timeout = 300ms x erase_timeout_mult x sec_trim_mult 0x11 cmd index type argument resp abbreviation command description cmd12 ac [31:16] ? rca* [15:1] ? stuff bits [0] ? high priority interrupt * *to be used only to send a high priority interrupt r1b stop_transmission if high priority interrupt flag is set the device shall interrupt its internal operations in a well defined timing commands names notes cmd24 write single block - cmd25 write multiple blocks - cmd25 reliable write stopping a reliable write command with ?high priority interrupt? flag set turns that command into a reliable write command cmd38 erase - trim - secure erase - secure trim - cmd6 switch background operation only - 11 - datasheet klmxgxge4a-a001 emmc rev. 1.1 [table 11] ext_csd value for hpi [table 12] definition of ext_csd value for hpi name field size(bytes) cell type csd-slice value hpi features hpi_features 1 r [503] 0x03 number of correctiy programmed sectors correctly_prg_sectors_num 4 r [245:242] 0x00 partition switching timing partition_switch_time 1 r [199] 0x01 out of interrupt busytiming out_of_interrupt_time 1 r [198] 0x02 hpi management hpi_mgmt 1 r/w/e_p [161] 0x00 fields definitions hpi_features bit 0 means hpi_support bit 0 = 0x0 : high priority interrupt mechanism not supported bit 0 = 0x1 : high priority interrupt mechanism supported bit 1 means hpi_implementation 0x0 : hpi mechanism implementation based on cmd13 0x1 : hpi mechanism implementation based on cmd12 correctly_prg_sector_num this field indicates how many 512b sectors were successfully programmed by the last write_multiple_block command (cmd25). correctly_prg_sectors_num=ext_csd[242]*2^0+ext_csd[243]*2^8 +ext_csd[244]*2^16 + ext_csd[245]*2^24 partition_switch_time this field indicates the maximum timeout for the switch command (cmd6) when switching partitions by changing partition_access bits in partition_config field (ext_csd byte [179]). time is expressed in units of 10 milliseconds out_of_interrupt_time this field indicates the maximum timeout to close a command interrupted by hpi - time between the end bit of cmd12 / cmd 13 to the dat0 release by the device. hpi_mgmt bit 0 means hpi_en 0x0 : hpi mechanism not activated by the host 0x1 : hpi mechanism activated by the host - 12 - datasheet klmxgxge4a-a001 emmc rev. 1.1 4.5 background operation when the host is not being serviced, emmc can do internal operation by using ?background operation? command. in this operation which takes long time to complete can be handled later when host ensure enough idle time (in back ground operation) background operation sequence is the following [table 13] background operation sequence [table 14] ext_csd value for background operation [table 15] definition of ext_csd value for bakgrourd operation [table 16] card status register for background operation function command description background operation check cmd8 or card status register if bkops_status is not 0 or 6 th bit of card status register is set, there are something to be performed by background operation background operation start cmd6 background operation starts by bkops_start is set to any value. when background operation is completed bkops_status is set to 0 and bkops_start is set to 0. background operation stop hpi if the background operation is stopped bkops_start is set to 0 name field size(bytes) cell type csd-slice value background operations support bkops_support 1 r [502] 0x01 background operations status bkops_status 1 r [246] 0x00 manually start background operations bkops_start 1 w/e_p [164] 0x00 enable background operations hand shake bkop_en 1 r/w [163] 0x00 fields definitions bkops_support ?0? means background operation is not supported ?1? means background operation is supported bkops_ status ?0? means no background work pending ?1? means pending background work existing. ?2? means pending background work existing & performance being impacted. ?3? means pending background work existing & critical bkops_start background operation start while bkops_start is set to any value. ?0? means background operation is enabled. bkops_en ?0? means host does not support background operation ?1? means host use background operation manually bits identifier type det mode value description clear cond 6 urgent_bkops s r ?0? = not urgent ?1? = urgent if set, device needs to perform background opera- tions urgently. host can check ext_csd field bkops_status for the detailed level ( in case of bkops_status is 2 or 3 ) a - 13 - datasheet klmxgxge4a-a001 emmc rev. 1.1 5.0 technical notes 5.1 s/w agorithm 5.1.1 partition management the device initially consists of two boot partitions and rpmb partition and user data area. the user data area can be divided into four general purpose area partitions and user data area partition. each of the general p urpose area partitions and a section of user data area partition can be configured as enhanced partition. 5.1.1.1 boot area partition and rpmb area partition default size of each boot area partition is 512kb and can be changed by vendor command as multiple of 512kb. default size of rpmb area partition is 128 kb and can be changed by vendor command as multiple of 128kb. boot partition size & rpmb partition size are set by the following command sequence : [table 17] setting sequence of boot area partition size and rpmb area partition size boot partition size is calculated as ( 128kb * boot_size_multi ) boot_size_multi should be set as multiple of 8. the size of boot area partition 1 and 2 can not be set independently. it is set as same value. rpmb partition size is calculated as ( 128kb * rpmb_size_multi ). in rpmb partition, cmd 0, 6, 8, 12, 13, 15, 18, 23, 25 are admitted. access size of rpmb partition is defined as the below: [table 18] rel_wr_sec_c value for write operation on rpmb partition any undefined set of parameters or sequence of commands results in failure access. if the failure is in data programming case, the data is not programmed. and if the failure occurs in data read case, the read d ata is ?0x00?. 5.1.1.2 enhanced partition (area) samsung emmc adopts enhanced user data area as slc mode. therefore when master adopts some portion as enhanced user data area in user data area, that area occupies double size of original set up size. ( ex> if master set 1mb for enhanced mode, total 2mb user da ta area is needed to gen- erate 1mb enhanced area) max enhanced user data area size is defined as (max_enh_size_mult x hc_wp_grp_size x hc_erase_gpr_size x 512kbytes) function command description partition size change mode cmd62(0xefac62ec) enter the partition size change mode partition size set mode cmd62(0x00cbaea7) partition size setting mode set boot partition size cmd62(boot_size_multi) boot partition size value set rpmb partition size cmd62(rpmb_size_multi) rpmb partition size value f/w re-partition is executed in this step. power cycle rel_wr_sec_c description rel_wr_sec_c = 1 access sizes 256b and 512b supported to rpmb partition rel_wr_sec_c > 1 access sizes up to rel_wr_sec_c * 512b supported to rpmb partition with 256b granularity - 14 - datasheet klmxgxge4a-a001 emmc rev. 1.1 5.1.2 write protect management in order to allow the host to protect data against erase or write, the device shall support write protect commands. 5.1.2.1 user area write protection tmp_write_protect (csd[12]) and perm_write_protect(csd[13]) registers allow the host to apply write protection to whole device including boot partition, rpmb partition and user area. [table 19] whole device write protect priority user_wp (ext_csd[171]) register allows the host to apply write protection to all the partitions in the user area. [table 20] user area write protect priority the host has the ability to check the write protection status of segments by using the send_write_prot_type command (cmd31). wh en full card protection is enabled all the segments will be shown as having permanent protection. 5.1.2.2 boot partition write protection boot_wp (ext_csd [173]) register allows the host to apply write protection to boot area partitions. [table 21] boot area write protect priority an attempt to set both the disable and enable bit for a given protection mode (permanent or power-on) in a single switch comman d will have no impact and switch error occurs. setting both b_perm_wp_en and b_pwr_wp_en will result in the boot area being permanently protected. class setting permanent write protect set : one time programmable clr : not available temporary write protect set : multiple programmable clr : multiple programmable class setting permanent write protect set : one time programmable clr : not available power-on write protect set : one time programmable on power-on clr : after power reset temporary write protect set : multiple programmable clr : multiple programmable class setting permanent write protect set : one time programmable clr : not available power-on write protect set : one time programmable on power-on clr : after power reset - 15 - datasheet klmxgxge4a-a001 emmc rev. 1.1 5.1.3 boot operation device supports not only boot mode but also alternative boot mode. device supports high speed timing and dual data rate during boot figure 5. multimediacard state diagram (boot mode) figure 6. multimediacard state diagram (alternative boot mode) [table 22] boot ack, boot data and initialization time note: 1) this initialization time includes partition setting, please refer to ini_timeout_ap in 6.4 extended csd register. normal initialization time (without partition setting) is completed within 1sec minimum function for reading boot data is initialized during boot time and after that full function is initialized during initi alization time. timing factor value (1) boot ack time < 50 ms (2) boot data time < 60 ms (3) initialization time 1) < 3 secs se se 010 512bytes +crc clk cmd dat[0] cmd1 resp cmd2 resp boot terminated min 8 cloks + 48 clocks = 56 clocks required from cmd signal high to next mmc command. (1) (2) *(1) boot ack time (2) boot data time (3) cmd1 time se se 010 512bytes +crc clk cmd dat[0] cmd1 resp cmd2 cmd0 1 cmd0 reset min74 clocks required after power is stable to start boot command *(1) boot ack time (2) boot data time (3) cmd1 time *cmd0 with argument 0xfffffffa (1) (2) boot terminated cmd1 (3) - 16 - datasheet klmxgxge4a-a001 emmc rev. 1.1 5.1.4 wear leveling the partitions in device have the following nand type in case of mlc type nand. [table 23] nand type in each partitions wear leveling means that blocks should be used evenly in order to expand life span of device. wear leveling is executed in each partition locally because of each partition with different attribute. figure 7. wear leveling and then device reserves free block and executes wear-level at each partition respectively. 5.1.5 user density total user density depends on device type. for example, 32mb in the slc mode requires 64mb in mlc. this results in decreasing of user density [table 24] capacity according to partition [table 25] maximum enhanced partition size partitions nand operation mode boot area partition 1 slc mode boot area partition 2 slc mode rpmb area partition slc mode general purpose partition mlc mode or slc mode user data area enhanced area slc mode default area mlc mode boot partition 1 boot partition 2 rpmb mlc min. 2,048kb 2,048kb 128kb max. 16,384kb 16,384kb 4,096kb device max. enhanced partition size 16 gb 7,801,405,440 bytes 32 gb 15,602,810,880 bytes 64 gb 31,247,564,800 bytes boot area partition rpmb area partition user area enhanced area 4 3 2 1 user density enhanced user data area 4 general purpose partitions (gpa) rpmb boot partition #1 - 17 - datasheet klmxgxge4a-a001 emmc rev. 1.1 [table 26] user density size 5.1.6 auto power saving mode if host does not issue any command during a certain duration (1ms), after previously issued command is completed, the device en ters "power saving mode" to reduce power consumption. at this time, commands arriving at the device while it is in power saving mode will be serviced in normal fashion [table 27] auto power saving mode enter and exit [table 28] auto power saving mode and sleep mode 5.1.7 end of life management the end of device life time is defined when there is no more available reserved block for bad block management in the device. w hen the deivice reaches to end of its life time, device shall change its state to permanent write protection state. in this case, write operation is no t allowed any more but read oper- ation are still allowed. but, reliability of the operation can not be guaranteed after end of life 5.2 smart report samsung provides report feature for the host to notice the device state by meta data. samsung calls this smart report. so custo mer can acquire prime factor for understanding at the beginning analysis of error. below table is the information about smart report. [table 29] smart report 5.2.1 smart report sequence [table 30] smart report sequence device user density size 16 gb 15,634,268,160 bytes 32 gb 31,268,536,320 bytes 64 gb 62,537,072,640 bytes mode enter condition escape condition auto power saving mode when previous operation which came from host is completed and no command is issued dur- ing a certain time. if host issues any command auto power saving mode sleep mode nand power on off gotosleep time < 1ms < 1ms mode contents customer report 1. detect error mode 2. detect super block size 3. detect super page size 4. detect optimal write size 5. detect number of banks 6.the number of initial bad block, per bank 7.the number of run time bad block, per bank 8.number of remain block in reserved block 9.max, min, avg erase count 10.number of read reclaim 11.detect optimal trim size 12.hash code 13. max, min, avg erase count (slc) 14. max, min, avg erase count (mlc) functions command description entering smart report mode cmd62h(0xefac62ec) cmd62h(0xccee) after entering smart report mode, the report-related values are able to be checked on read command. confirming smart report cmd17h(0x0) it is possible to confirm smart report after reading sector 1 at address 0. removing smart report mode cmd62h(0xefac62ec) cmd62h(0xdeccee) smart report mode is removed by this command. - 18 - datasheet klmxgxge4a-a001 emmc rev. 1.1 5.2.2 smart report output data (for customer) [table 31] smart report output data (for customer) 5.2.3 performance [table 32] performance * test condition : bus width x8, 52mhz ddr, 4mb file transfer, measured on samsung's internal board, w/o file system overhead data slice field width remark [3:0] error mode 4 bytes normal : 0xd2d2d2d2, openfatalerror : 0x37373737, runtimefatalerror : 0x5c5c5c5c, metabrokenerror : 0xe1e1e1e1 * in case of open error, other fields are not valid. [7:4] super block size 4 bytes total size(in byte) of simultaneously erasable physical blocks (e.g., number of channel * n-way interleaving * physical block size) [11:8] super page size 4 bytes total size(in byte) of simultaneously programmable physical pages (e.g., number of channel * physical page size) [15:12] optimal write size 4 bytes write size(in byte) at which the device performs best (e.g., super page size * n-way interleaving) [19:16] number of banks 4 bytes number of banks connecting to each nand flash. bad blocks are managed by each banks. [23:20] bank0 init bad block 4 bytes number of init defective physical blocks of plane which has the least remaining blocks in ban k0 [27:24] bank0 runtime bad block 4 bytes number of runtime defective physical blocks of plane which has the least remaining blocks in bank0 [31:28] bank0 remain reserved block 4 bytes number of remain reserved blocks of plane which has the least remaining blocks in bank 0 [35:32] bank1 init bad block 4 bytes number of init defective physical blocks of plane which has the least remaining blocks in ban k1 [39:36] bank1 runtime bad block 4 bytes number of runtime defective physical blocks of plane which has the least remaining blocks in bank1 [43:40] bank1 remain reserved block 4 bytes number of remain reserved blocks of plane which has the least remaining blocks in bank 1 [47:44] bank2 init bad block 4 bytes number of init defective physical blocks of plane which has the least remaining blocks in ban k2 [51:48] bank2 runtime bad block 4 bytes number of runtime defective physical blocks of plane which has the least remaining blocks in bank2 [55:52] bank2 remain reserved block 4 bytes number of remain reserved blocks of plane which has the least remaining blocks in bank 2 [59:56] bank3 init bad block 4 bytes number of init defective physical blocks of plane which has the least remaining blocks in ban k3 [63:60] bank3 runtime bad block 4 bytes number of runtime defective physical blocks of plane which has the least remaining blocks in bank3 [67:64] bank3 reserved block 4 bytes number of remain reserved blocks of plane which has the least remaining blocks in bank3 [71:68] max. erase count 4 bytes maximum erase count from among all physical blocks [75:72] min. erase count 4 bytes minimum erase count from among all physical blocks [79:76] avg. erase count 4 bytes average erase count of all physical blocks [83:80] read reclaim cnt 4 bytes number of read reclaim count [87:84] optimal trim size 4 bytes optimal trim size [119:88] hash code 32 byte hash code [123:120] max. erase count (slc) 4 bytes maximum erase count from among all slc physical blocks [127:124] min. erase count (slc) 4 bytes minimum erase count from among all slc physical blocks [131:128] avg. erase count (slc) 4 bytes average erase count of all slc physical blocks [135:132] max. erase count (mlc) 4 bytes maximum erase count from among all mlc physical blocks [139:136] min. erase count (mlc) 4 bytes minimum erase count from among all mlc physical blocks [143:140] avg. erase count (mlc) 4 bytes average erase count of all mlc physical blocks [511:144] reserved density sequential read (mb/s) sequential write (mb/s) 16 gb 80 35 32 gb 64 gb - 19 - datasheet klmxgxge4a-a001 emmc rev. 1.1 6.0 register value 6.1 ocr register the 32-bit operation conditions register stores the vdd voltage profile of the emmc. in addition, this register includes a sta tus information bit. this status bit is set if the emmc power up procedure has been finished. the ocr register shall be implemented by all emmcs. [table 33] ocr register note : 1) this bit is set to low if the emmc has not finished the power up routine 2) the voltage for internal flash memory(vddf) should be 2.7-3.6v regardless of ocr register value. 6.2 cid register [table 34] cid register note : 1),4),5) description are same as e.mmc jedec standard 2) prv is composed of the revision count of controller and the revision count of f/w patch 3) a 32 bits unsigned binary integer. (random number) 6.2.1 product name table (in cid register) [table 35] product name ocr bit vdd voltage window 2 register value [6:0] reserved 00 00000b [7] 1.70 - 1.95 1b [14:8] 2.0-2.6 000 0000b [23:15] 2.7-3.6 1 1111 1111b [28:24] reserved 0 0000b [30:29] access mode 00b (byte mode) 10b (sector mode) -[ *higher than 2gb only] [31] emmc power up status bit (busy) 1 name field width cid-slice cid value manufacturer id mid 8 [127:120] 0x15 reserved 6 [119:114] --- card/bga cbx 2 [113:112] 01 oem/application id oid 8 [111:104] --- 1 product name pnm 48 [103:56] see product name table product revision prv 8 [55:48] --- 2 product serial number psn 32 [47:16] --- 3 manufacturing date mdt 8 [15:8] --- 4 crc7 checksum crc 7 [7:1] --- 5 not used, always ?1? - 1 [0:0] --- part number density product name in cid register (pnm) KLMAG2GE4A-A001 16 gb 0x4d4147324741 klmbg4ge4a-a001 32 gb 0x4d4247344741 klmcg8ge4a-a001 64 gb 0x4d4347384741 - 20 - datasheet klmxgxge4a-a001 emmc rev. 1.1 6.3 csd register the card-specific data register provides information on how to access the emmc contents. the csd defines the data format, erro r correction type, max - imum data access time, data transfer speed, whether the dsr register can be used etc. the programmable part of the register (en tries marked by w or e, see below) can be changed by cmd27. the type of the entries in the table below is coded as follows: r : read only w: one time programmable and not readable. r/w: one time programmable and readable. w/e : multiple writable with value kept after power failure, h/w reset assertion and any cmd0 reset and not readable. r/w/e: multiple writable with value kept after power failure, h/w reset assertion and any cmd0 reset and readable. r/w/c_p: writable after value cleared by power failure and hw/ rest assertion (the value not cleared by cmd0 reset) and readabl e. r/w/e_p: multiple writable with value reset after power failure, h/w reset assertion and any cmd0 reset and readable. w/e/_p: multiple wtitable with value reset after power failure, h/w reset assertion and any cmd0 reset and not readable. [table 36] csd register name field width cell type csd-slice csd value 16gb 32gb 64gb csd structure csd_structure 2 r [127:126] 0x03 system specification version spec_vers 4 r [125:122] 0x04 reserved - 2 r [121:120] - data read access-time 1 t aac 8 r [119:112] 0x27 data read access-time 2 in clk cycles (nsac*100) nsac 8 r [111:104] 0x01 max. bus clock frequency tran_speed 8 r [103:96] 0x32 card command classes ccc 12 r [95:84] 0xf5 max. read data block length read_bl_len 4 r [83:80] 0x09 partial blocks for read allowed read_bl_partial 1 r [79:79] 0x00 write block misalignment write_blk_misalign 1 r [78:78] 0x00 read block misalignment read_blk_misalign 1 r [77:77] 0x00 dsr implemented dsr_imp 1 r [76:76] 0x00 reserved - 2 r [75:74] - card size c_size 12 r [73:62] 0xfff max. read current @ vdd min vdd_r_curr_min 3 r [61:59] 0x06 max. read current @ vdd max vdd_r_curr_max 3 r [58:56] 0x06 max. write current @ vdd min vdd_w_curr_min 3 r [55:53] 0x06 max. write current @ vdd max vdd_w_curr_max 3 r [52:50] 0x06 card size multiplier c_size_mult 3 r [49:47] 0x07 erase group size erase_grp_size 5 r [46:42] 0x1f erase group size multiplier erase_grp_mult 5 r [41:37] 0x1f write protect group size wp_grp_size 5 r [36:32] 0x1f write protect group enable wp_grp_enable 1 r [31:31] 0x01 manufacturer default ecc default_ecc 2 r [30:29] 0x00 write speed factor r2w_factor 3 r [28:26] 0x02 max. write data block length write_bl_len 4 r [25:22] 0x09 partial blocks for write allowed write_bl_partial 1 r [21:21] 0x00 reserved - 4 r [20:17] - content protection application content_prot_app 1 r [16:16] 0x00 file format group file_format_grp 1 r/w [15:15] 0x00 copy flag (otp) copy 1 r/w [14:14] 0x01 permanent write protection perm_write_protect 1 r/w [13:13] 0x00 temporary write protection tmp_write_protect 1 r/w/e [12:12] 0x00 file format file_format 2 r/w [11:10] 0x00 ecc code ecc 2 r/w/e [9:8] 0x00 crc crc 7 r/w/e [7:1] - not used, always ?1? - 1 - [0:0] - - 21 - datasheet klmxgxge4a-a001 emmc rev. 1.1 6.4 extended csd register the extended csd register defines the emmc properties and selected modes. it is 512 bytes long. the most significant 320 bytes are the properties segment, which defines the emmc capabilities and cannot be modified by the h ost. the lower 192 bytes are the modes segment, which defines the configuration the emmc is working in. these modes can be changed by the host by means of the switch command. r : read only w: one time programmable and not readable. r/w: one time programmable and readable. w/e : multiple writable with value kept after power failure, h/w reset assertion and any cmd0 reset and not readable. r/w/e: multiple writable with value kept after power failure, h/w reset assertion and any cmd0 reset and readable. r/w/c_p: writable after value cleared by power failure and hw/ rest assertion (the value not cleared by cmd0 reset) and readabl e. r/w/e_p: multiple writable with value reset after power failure, h/w reset assertion and any cmd0 reset and readable. w/e/_p: multiple wtitable with value reset after power failure, h/w reset assertion and any cmd0 reset and not readable [table 37] extended csd register name field size (bytes) cell type csd- slice csd value 16gb 32gb 64gb properties segment reserved 1 7 - [511:505] - supported command sets s_cmd_set 1 r [504] 0x01 hpi features hpi_features 1 r [503] 0x03 background operations support bkops_support 1 r [502] 0x01 reserved 1 255 - [501:247] - background operations status bkops_status 1 r [246] 0x00 number of correctly programmed sectors correctly_prg_sector s_num 4 r [245:242] 0x00 i st initialization time after partitioning ini_timeout_ap 1 r [241] 0x1e reserved 1 1 - [240] - power class for 52mhz, ddr at 3.6v pwr_cl_ddr_52_360 1 r [239] 0x00 power class for 52mhz, ddr at 1.95v pwr_cl_ddr_52_195 1 r [238] 0x00 reserved 1 2 - [237:236] - minimum write performance for 8 bit at 52mhz in ddr mode min_perf_ddr_w_8_52 1 r [235] 0x00 minimum read performance for 8 bit at 52mhz in ddr mode min_perf_ddr_r_8_52 1 r [234] 0x00 reserved 1 1 - [233] - trim multiplier trim_mult 1 r [232] 0x02 secure feature support sec_feature_support 1 r [231] 0x15 secure erase multiplier sec_erase_mult 1 r [230] 0x1b secure trim multiplier sec_trim_mult 1 r [229] 0x11 boot information boot_info 1 r [228] 0x07 reserved 1 1 - [227] - boot partition size boot_size_multi 2) 1 r/w [226] 0x10 access size acc_size 1 r [225] 0x07 high-capacity erase unit size hc_erase_grp_size 1 r [224] 0x01 high-capacity erase timeout erase_timeout_mult 1 r [223] 0x01 reliable write sector count rel_wr_sec_c 1 r [222] 0x01 high-capacity write protect group size hc_wp_grp_size 1 r [221] 0x50 sleep current (vddf) s_c_vddf 1 r [220] 0x07 sleep current (vdd) s_c_vdd 1 r [219] 0x07 reserved 1 1 - [218] - sleep/awake timeout s_a_timeout 1 r [217] 0x11 - 22 - datasheet klmxgxge4a-a001 emmc rev. 1.1 reserved 1 1 - [216] - sector count sec_count 4 r [215:212] 0x1d1f 000 0x3a3e0 00 0x747c0 00 reserved 1 1 - [211] - minimum write performance for 8bit @52mhz min_perf_w_8_52 1 r [210] 0x00 minimum read performance for 8bit @52mhz min_perf_r_8_52 1 r [209] 0x00 minimum write performance for 8bit @26mhz / 4bit @52mhz min_perf_w_8_26_4_52 1 r [208] 0x00 minimum read performance for 8bit @26mhz / 4bit @52mhz min_perf_r_8_26_4_52 1 r [207] 0x00 minimum write performance for 4bit @26mhz min_perf_w_4_26 1 r [206] 0x00 minimum read performance for 4bit @26mhz min_perf_r_4_26 1 r [205] 0x00 reserved 1 1 - [204] - power class for 26mhz @ 3.6v pwr_cl_26_360 1 r [203] 0x00 power class for 52mhz @ 3.6v pwr_cl_52_360 1 r [202] 0x00 power class for 26mhz @ 1.95v pwr_cl_26_195 1 r [201] 0x00 power class for 52mhz @ 1.95v pwr_cl_52_195 1 r [200] 0x00 partition switching timing partition_switch_time 1 r [199] 0x01 out-of-interrupt busy timing out_of_interrupt_time 1 r [198] 0x02 reserved 1 1 - [197] - card type card_type 1 r [196] 0x07 reserved 1 1 - [195] - csd structure version csd_structure 1 r [194] 0x02 reserved 1 1 - [193] - extended csd revision ext_csd_rev 1 r [192] 0x05 modes segment command set cmd_set 1 r/w [191] 0x00 reserved 1 1 - [190] - command set revision cmd_set_rev 1 r [189] 0x00 reserved 1 1 - [188] - power class power_class 1 r/w [187] 0x00 reserved 1 1 - [186] - high speed interface timing hs_timing 1 r/w [185] 0x00 reserved 1 1 - [184] - bus width mode bus_width 1 w/e_p [183] 0x00 reserved 1 1 - [182] - erased memory content erased_mem_cont 1 r [181] 0x00 reserved 1 1 - [180] - partition configurationn partition_config 1 r/w/e& r/w/e_p [179] 0x00 boot config proteetion boot_config_prpt 1 r/w & r/w/c_p [178] 0x00 boot bus width1 boot_bus_width 1 r/w/e [177] 0x00 reserved 1 1 - [176] - high-density erase group definition erase_group_def 1 r/w/e_p [175] 0x00 reserved 1 1 - [174] - boot area write proection register boot_wp 1 r/w & r/w/c_p [173] 0x00 reserved 1 1 - [172] - - 23 - datasheet klmxgxge4a-a001 emmc rev. 1.1 note : 1) reserved bits should be read as "0." user area write protection register user_wp 1 r/w, r/w/ c_p& r/w/e_p [171] 0x00 reserved 1 1 - [170] - fw configuration fw_config 1 r/w [169] 0x00 rpmb size rpmb_size_mult 1 r [168] 0x01 write reliability setting register wr_rel_set 1 r/w [167] 0x1f write reliability parameter register wr_rel_param 1 r [166] 0x05 reserved 1 1 - [165] - manually start background operations bkops_start 1 w/e_p [164] 0x00 enable background operations handshake bkops_en 1 r/w [163] 0x00 h/w reset function rst_n_function 1 r/w [162] 0x00 hpi management hpi_mgmt 1 r/w/e_p [161] 0x00 partitoning support rartitioning_support 1 r [160] 0x03 max enhanced area size max_enh_size_mult 3 r [159:157] 0xba 0x174 0x2e9 partitions attribute partitions_attribute 1 r/w [156] 0x00 paritioning setting partition_setting_comp leted 1 r/w [155] 0x00 general purpose partition size gp_size_mult 12 r/w [154:143] 0x00 enhanced user data area size enh_size_mult 3 r/w [142:140] 0x00 enhanced user data start address enh_start_addr 4 r/w [139:136] 0x00 reserved 1 1 - [135] - bad block management mode sec_bad_blk_mgmt 1 r/w [134] 0x00 reserved 1 134 - [133:0] - - 24 - datasheet klmxgxge4a-a001 emmc rev. 1.1 7.0 ac parameter 7.1 time parameter [table 38] time parameter note: 1) normal initialization time without partition setting 2) initialization time after partition setting, refer to ini_timeout_ap in 6.4 ext_csd register 3) if 8kb size and address are aligned, max. timeout value is 300ms 7.2 bus timing parameter figure 8. bus signal levels timing paramter max. value unit initialization time (tinit) normal 1) 1s after partition setting 2) 3s read timeout 100 ms write timeout 350 ms erase timeout 15 ms force erase timeout 3 min secure erase timeout 8s secure trim step1 timeout 5s secure trim step2 timeout 3s trim timeout 3) 600 ms partition switching timeout (after init) 100 us data data data invalid invalid t pp t wh t wl t isu t ih t thl t tlh t oh clk input output data must always be sampled on the rising edge of the clock. t osu t odly 50% vdd 50% vdd min (v ih ) min (v oh ) max (v il ) min (v ih ) max (v il ) max (v ol ) data - 25 - datasheet klmxgxge4a-a001 emmc rev. 1.1 [table 39] default (under 26mhz) note : 1)the card must always start with the backward-compatible interface timing mode can be switched to high-speed interface timing by the host sending the switch command (cmd6) with the argument for high-speed interface select. 2) clk timing is measured at 50% of vdd. 3) for compatibility with cards that suport the v4.2 standard or earlier verison, host should not use>20mhz before switching to high-speed interface timing. 4) frequency is periodically sampled and is not 100% tested. 5) clk rise and fall times are measured by min(v ih ) and max(v il ). [table 40] high-speed mode note : 1) clk timing is measured at 50% of vdd. 2) a multimediacard shall support the full frequency range from 0-26mhz, or 0-52mhz 3) frequency is periodically sampled and is not 100% tested. 4) card can operate as high-speed card interface timing at 26mhz clock frequency. 5) clk rise and fall times are measured by min(v ih ) and max(v il ).6) inputs cmd, dat rise and fall times are measured by min(v ih ) and max(v il ), and outputs cmd, dat rise and fall times are measured by min(v oh ) and max(v ol ). parameter symbol min max unit remark 1 clock clk(all values are referred to min(v ih ) and max(v il ) 2 clock frequency data transfer mode3 fpp 0 4 26 mhz cl <= 30 pf tolerance: +100khz clock frequency identification mode f od 0 4 400 khz tolerance: +20khz clock low time t wl 10 ns c l <= 30 pf clock high time t wh 10 clock rise time 5 t tlh 10 ns c l <= 30 pf clock fall time t thl 10 ns c l <= 30 pf inputs cmd, dat (referenced to clk) input set-up time t isu 3n s c l <= 30 pf input hold time t ih 3n s c l <= 30 pf outputs cmd, dat (referenced to clk) output hold time t oh 8.3 ns cl <= 30 pf output set-up time t osu 11.7 ns cl <= 30 pf parameter symbol min max unit remark clock clk(all values are referred to min(v ih ) and max(v il ) 1 clock frequency data transfer mode 2 f pp 0 3 52 4) mhz c l <= 30 pf clock frequency identification mode f od 0 3 400 khz cl <= 30 pf clock low time t wl 6.5 ns c l <= 30 pf clock high time t wh 6.5 ns c l <= 30 pf clock rise time 5 t tlh 3n s c l <= 30 pf clock fall time t thl 3n s c l <= 30 pf inputs cmd, dat (referenced to clk) input set-up time t isu 3n s c l <= 30 pf input hold time t ih 3n s c l <= 30 pf outputs cmd, dat (referenced to clk) output delay time during data transfer mode t odly 13.7 ns cl <= 30 pf output hold time t oh 2.5 c l <= 30 pf signal rise time t rise 3n s c l <= 30 pf signal fall time t fall 3ns c l <= 30 pf - 26 - datasheet klmxgxge4a-a001 emmc rev. 1.1 7.3 bus timing for dat signals during 2x data rate operation these timings applies to the dat[7:0] signals only when the device is configured for dual data mode operation. in this dual dat a mode, the da t signals operates synchronously of both the rising and the falling edges of clk.the cmd signal still operates synchronously of the risin g edge of clk and there fore it complies with the bus timing specified in chapter 7.2, therefore there is no timing change for the cmd signal figure 9. timing diagram: data input/output in dual data rate mode 7.3.1 dual data rate interface timings [table 41] high-speed dual rate interface timing note : 1) clk timing is measuted at 50% of vdd 2) inputs cmd, dat rise and fall times are measured by min (v ih ) and max(v il ), and outputs cmd,datrise and fall times measured by min(v oh ) and max(v ol ) parameter symbol min max. unit remark 1 input clk 1 clock duty cycle 45 55 % includes jitter, phase noise input dat (referenced to clk-ddr mode) input set-up time tisuddr 2.5 ns cl ? 20 pf input hold time tihddr 2.5 ns cl ? 20 pf output dat (referenced to clk-ddr mode) output delay time during data transfer todlyddr 1.5 7 ns cl ? 20 pf signal rise time (all signals) 2 trise 2 ns cl ? 20 pf signal fall time (all signals) tfall 2 ns cl ? 20 pf data t pp t isuddr input output in ddr mode data on dat[7:0] lines are sampled on both edges of the clock t odlyddr(max) min (v ih ) min (v oh ) max (v il ) min (v ih ) max (v il ) max (v ol ) clk data data invalid t ihddr t isuddr t ihddr i data data data t odlyddr(min) t odlyddr(max) t odlyddr(min) (not applicable for cmd line) - 27 - datasheet klmxgxge4a-a001 emmc rev. 1.1 7.4 bus signal levels as the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage. 7.4.1 open-drain mode bus signal level [table 42] open-drain bus signal level the input levels are identical with the push-pull mode bus signal levels. 7.4.2 push-pull mode bus signal level.high-voltage multimediacard to meet the requirements of the jedec standard jesd8c.01, the card input and output voltages shall be within the following spec ified ranges for any v dd of the allowed voltage range: [table 43] push-pull signal level.high-voltage multimediacard 7.4.3 push-pull mode bus signal level.dual-voltage multimediacard the definition of the i/o signal levels for the dual voltage multimediacard changes as a function of v dd . ?? 2.7v - 3.6v: identical to the high voltage multimediacard (refer to chapter 7.4.2 on page27 above). ? 1.95v - 2.7v: undefined. the card is not operating at this voltage range. ?? 1.70v - 1.95v: compatible with eia/jedec standard ?eia/jesd8-7 normal range? as defined in the following table. [table 44] push-pull signal level?dual-voltage multimediacard note: 1) 0.7*v dd for mmc4.3 and older revisions. 2) 0.3*v dd for mmc4.3 and older revisions. parameter symbol min max. unit conditions output high voltage v oh v dd - 0.2 v i oh = -100 ua output low voltage v ol 0.3 v i ol = 2 ma parameter symbol min max. unit conditions output high voltage v oh 0.75*v dd v i oh = -100 ua@v dd min output low voltage v ol 0.125*v dd v i ol = 100 ua@v dd min input high voltage v ih 0.625*v dd v dd + 0.3 v input low voltage v il v ss - 0.3 0.25*v dd v parameter symbol min max. unit conditions output high voltage v oh v dd - 0.45v v i oh = -2ma output low voltage v ol 0.45v v i ol = 2ma input high voltage v ih 0.65*v dd 1) v dd + 0.3 v input low voltage v il v ss - 0.3 0.35*v dd 2) v v t input high level input low level output high level output low level undefined v dd v ih v oh v il v ss v ol - 28 - datasheet klmxgxge4a-a001 emmc rev. 1.1 7.4.4 push-pull mode bus signal level.emmc the definition of the i/o signal levels for the emmc devices changes as a function of vccq. ?? 2.7v-3.6: identical to the high voltage multimediacard (refer to chapter 7.4.2 on page27). ?? 1.95- 2.7v: undefined. the emmcdevice is not operating at this voltage range. ?? 1.65v-1.95v: identical to the 1.8v range for the dual voltage multimediacard (refer to chapter 7.4.3 on page27). ?? 1.3v - 1.65v: undefined. the emmc device is not operating at this voltage range. ?? 1.1v-1.3v: compatible with eia/jedec standard ?jesd8-12a.01 normal range: as defined in the following table. [table 45] push-pull signal level.1.1v-1.3v vccq range emmc parameter symbol min max. unit conditions output high voltage v oh 0.75v ccq v i oh = -2ma output low voltage v ol 0.25v ccq v i ol = 2ma input high voltage v ih 0.65*v ccq v ccq + 0.3 v input low voltage v il v ss - 0.3 0.35*v ccq v - 29 - datasheet klmxgxge4a-a001 emmc rev. 1.1 8.0 dc parameter 8.1 active power consumption during operation [table 46] active power consumption during operation * power measurement conditions: bus configuration =x8 @52mhz * the measurement for max rms current is the average rms current consumption over a period of 100ms. 8.2 standby power consumption in auto power saving mode and standby state [table 47] standby power consumption in auto power saving mode and standby state note: power measurement conditions: bus configuration =x8 @52mhz , no clk *typical value is measured at vcc=3.3v, ta=25c. not 100% tested. 8.3 sleep power consumption in sleep state [table 48] sleep power consumption in sleep state note: power measurement conditions: bus configuration =x8 @52mhz , 1) in auto power saving mode , nand power can not be turned off .however in sleep mode nand power can be turned off. if nand po wer is alive , nand power is same with that of the standby state. 8.4 supply voltage [table 49] supply voltage 8.5 bus operating conditions [table 50] bus operating conditions density nand type ctrl nand unit 16gb 64gb mlc x 2 100 100 ma 32gb 64gb mlc x 4 64gb 64gb mlc x 8 density nand type ctrl nand unit 25 ? c(typ) 85 ? c 25 ? c(typ) 85 ? c 16gb 64gb mlc x 2 100 250 30 100 ua 32gb 64gb mlc x 4 60 200 64gb 64gb mlc x 8 120 400 density nand type ctrl nand unit 25 ? c(typ) 85 ? c 16gb 64gb mlc x 2 100 250 0 1) ua 32gb 64gb mlc x 4 64gb 64gb mlc x 8 item min max unit vdd 1.70 (2.7) 1.95 (3.6) v vddf 2.7 3.6 v vss -0.5 0.5 v parameter min max unit peak voltage on all lines -0.5 3.6 v input leakage current -2 2 ? a output leakage current -2 2 ? a - 30 - datasheet klmxgxge4a-a001 emmc rev. 1.1 8.6 bus signal line load the total capacitance c l of each line of the emmc bus is the sum of the bus master capacitance c host , the bus capacitance c bus itself and the capac - itance c movi of the emmc connected to this line: c l = c host + c bus + c movi the sum of the host and bus capacitances should be under 20pf. [table 51] bus signal line load parameter symbol min typ. max unit remark pull-up resistance for cmd r cmd 4.7 100 kohm to prevent bus floating pull-up resistance for dat0-dat7 r dat 10 100 kohm to prevent bus floating internal pull up resistance dat1-dat7 r int 10 150 kohm to prevent unconnected lines floating single emmc capacitance c movi 71 2 pf maximum signal line inductance 16 nh f pp <= 52 mhz - 31 - datasheet klmxgxge4a-a001 emmc rev. 1.1 a. emmc connection guide this connection guide is an example for customers to adopt emmc more easily ? this appendix is just guideline for emmc connection. this value and schematic can be changed depending on the system environment. ?? coupling capacitor should be connected with vdd and vss as closely as possible. ?? vddi capacitor is min 0.1uf ?? impedance on clk match is needed. ? samsung recommends 27 for resistance on clk line. however 0 ~47 is also available. ?? if host does not have a plan to use h/w reset, it is not needed to put 50k pull-up resistance on h/w rest line. ?? smasung recommends to separate vdd and vddf power. a.1 x8 support host connection guide a.2 x4 support host connection guide emmc vddf c 2.0uf c 0.1uf host controller vdd vdd vdd cmd clk dat0 dat1 dat2 dat3 dat4 dat5 dat6 dat7 r 50k r 50k r 50k r 50k r 50k r 50k r 50k r 50k r 10k r 27 dat0 dat1 dat2 dat3 dat4 dat5 dat6 dat7 cmd clk vddf vdd vss vddi c2 rstn h/w reset r 50k c 0.2uf c 4.7uf c 0.2uf emmc vddf c 0.2uf c 2.0uf c 0.1uf host controller vdd vdd vdd cmd clk dat0 dat1 dat2 dat3 r 50k r 50k r 50k r 50k r 10k r 27 dat0 dat1 dat2 dat3 dat4 dat5 dat6 dat7 cmd clk vddf vdd vss vddi c2 rstn h/w reset r 50k c 0.2uf c 4.7uf |
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