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| thisdocumentisageneralproductdescriptionand issubjecttochangewithoutnotice.hynixdoesnot assumeanyresponsibilityfor useofcircuitsdescribed.nopatentlicensesarei mplied. rev 1.0 / sep. 2009 1 1gb e-nand H26M11001BAR e-nand
rev 1.0 / sep. 2009 2 e-nand document title e-nand revision history revision no. history draft date remark 0.0 initialdraft. jun.24.2009 1.0 released1.0spec.forenand sep.29.2009 rev 1.0 / sep. 2009 3 e-nand multimediacard interface e-nand controller (phison dg2682) nand flash data in/out control 1. introduction 1.1 general description thehynixenandmoduleisaverysmall,flashstor agedevice,designedspecificallyforstorageappli cationsthatput apremiumonsmallformfactor,lowpowerandlowc ost.flashistheidealstoragemediumforportable ,batterypow ereddevices.itfeatureslowpowerconsumptionand isnonvolatile,requiringnopowertomaintainthe storeddata.it alsohasawideoperatingrangefortemperature,sh ockandvibration.enandiswellsuitedtomeetthe needsof small,lowpower,electronicdevices.enandisexp ectedtobeusedinawidevarietyofportabledevi ceslikemobile phones,pmp,smartphones,pda,mediaplayersande tc.tosupportthiswiderangeofapplications,the enandis offeredwithanmmcinterface,fullycompatiblewit hmmcinterface,andprovidesa8bitdatabusfor maximumper formance.theseinterfacesallowforeasyintegrati onintoanydesign,regardlessofwhichtypeofmic roprocessoris used.alldeviceandinterfaceconfigurationdata( suchasmaximumfrequencyandmoduleidentification )arestored onthedevice.inadditiontothemassstoragespec ificflashmemorychip,theenandmoduleincludes anintelligent controller,whichmanagesinterfaceprotocols,data storageandretrieval,errorcorrectioncode(ecc) algorithms, defecthandlinganddiagnostics,powermanagement, wearleveling,andclockcontrol.figure11isab lockdiagramof thehynixenandmodulewithmmcinterface. figure 1-1 : e-nand block diagram rev 1.0 / sep. 2009 4 e-nand 1.2 system features jedecjesd84v4.3compatible backwardcompatiblewithearlierjesd84 maximumdataratewithupto52mb/secinterfacespe ed(using8paralleldatalines) voltagerange: enandsupportedclockfrequencies0~20mhz,0~26mhz ,0~52mhz enandsupportforthreedifferentdatabuswidthm odes:1bit(default),4bitand8bit correctionofmemoryfielderrors simpleerasemechanism passwordprotectionofenand voltage communication 1.71.95or2.73.6 memoryaccess 2.73.6 1.2.1 product list part number density jedec jesd84 spec package H26M11001BAR 1gb v4.3 169fbga(12x16x1.3) rev 1.0 / sep. 2009 5 e-nand 1.3 flash independent technology the512bytesectorsizeofthehynixenandisthe sameasthatinanidemagneticdiskdrive. towriteorreadasector(ormultiplesectors),th ehostcomputersoftwaresimplyissuesareadorwr itecommandtothe enand.thiscommandcontainstheaddressandthen umberofsectorstowrite/read.thehostsoftwaret henwaitsfor thecommandtocomplete.thehostsoftwaredoesnot getinvolvedinthedetailsofhowtheflashmemor yiserased,pro grammedorread.thisisextremelyimportantasfla shdevicesareexpectedtogetmoreandmorecomple xinthefuture. becausetheenandusesanintelligentonboardcon troller,thehostsystemsoftwarewillnotrequire changingasnew flashmemoryevolves. 1.4 defect and error management thehynixenandcontainasophisticateddefectand errormanagementsystem.thissystemisanalogous tothesystems foundinmagneticdiskdrivesandinmanycasesoff ersenhancements.forinstance,diskdrivesdonot typicallyperforma readafterwritetoconfirmthedataiswrittencor rectlybecauseoftheperformancepenaltythatwoul dbeincurred.e nanddoareadafterwriteundermarginconditions toverifythatthedataiswrittencorrectly(excep tinthecaseofa writewithouterasecommand).intherarecasethat abitisfoundtobedefective.enandwillevenr eplacetheentire sectorwithasparesector.thisiscompletelytran sparenttothehostanddoesnotconsumeanyuserd ataspace.thee nandsofterrorratespecificationismuchbettert hanthemagneticdiskdrivespecification.inthee xtremelyrarecasea readerrordoesoccur,enandhaveinnovativealgor ithmstorecoverthedata.thisissimilartousing retriesonadisk drivebutismuchmoresophisticated.thelastline ofdefenseistoemploypowerfulecctocorrectth edata.ifeccis usedtorecoverdata,defectivebitsarereplacedw ithsparebitstoensuretheydonotcauseanyfutu reproblems.these defectanderrormanagementsystemscoupledwithth esolidstateconstructiongiveenandunparalleled reliability. 1.5 sleep mode (cmd5) acardmaybeswitchedbetweenasleepstateanda standbystatebysleep/awake(cmd5).inthesleeps tatethe powerconsumptionofthememorydeviceisminimized .inthisstatethememorydevicereactsonlytoth ecommands reset(cmd0)andsleep/awake(cmd5).alltheother commandsareignoredbythememorydevice.thetime outfor statetransitionsbetweenstandbystateandsleeps tateisdefinedintheext_csdregisters_a_timeout .themaximum currentconsumptionsduringthesleepstatearedef inedintheext_csdregisterss_a_vccands_a_vccq. sleepcommand:thebit15assetto1insleep/awak e(cmd5)argument. awakecommand:thebit15assetto0insleep/awak e(cmd5)argument. thesleepcommandisusedtoinitiatethestatetra nsitionfromstandbystatetosleepstate.thememo rydeviceindicates thetransitionphasebusybypullingdownthedat0 line.nofurthercommandsshouldbesentduringthe busy.thesleep stateisreachedwhenthememorydevicestopspulli ngdownthedat0line. theawakecommandisusedtoinitiatethetransitio nfromsleepstatetostandbystate.thememorydev iceindicatesthe transitionphasebusybypullingdownthedat0line .nofurthercommandsshouldbesentduringthebus y.thestandby stateisreachedwhenthememorydevicestopspulli ngdownthedat0line. duringthesleepstatethevccpowersupplymaybe switchedoff.thisistoenableevenfurthersystem powerconsump tionsaving.thevccsupplyisallowedtobeswitch edoffonlyafterthesleepstatehasbeenreached (thememorydevice hasstoppedtopulldownthedat0line).thevccsu pplyhavetoberampedbackupatleasttothemin operatingvoltage levelbeforethestatetransitionfromsleepstate tostandbystateisallowedtobeinitiated(awake command). rev 1.0 / sep. 2009 6 e-nand 1.6 mmc mode 1.6.1 e-nand standard compliance thehynixenandisfullycompliantwithjedecjesd 84v4.3seriesofspecifications. 1.6.2 negotiating operation conditions theenandsupportstheoperationconditionverific ationsequencedefinedinthejedecjesd84v4.3ser iesofspecifica tions.theenandhostshoulddefineanoperatingv oltagerangethatisnotsupportedbytheenand.i twillputitselfin aninactivestateandignoreanybuscommunication. theonlywaytogettheenandoutoftheinactive stateisbypow eringitdownandupagain.inaddtionthehostcan explicitlysendtheenandtotheinactivestateb yusingthe go_inactive_statecommand. 1.6.3 card status enandstatusisstoredina32bitstatusregister whichissentasthedatafieldinthecardrespon dtohostcommands. statusregisterprovidesinformationaboutthecard scurrentstateandcompletioncodesforthelast hostcommand.the cardstatuscanbeexplicitylyread(polled)withth esend_statuscommand. 1.6.4 memory array partitioning thebasicunitofdatatransferto/fromtheenand isonebyte.alldatatransferoperationswhichreq uireablocksize alwaysdefineblocklenghsasintegermultiplesof bytes.somespecialfunctionsneedotherpartition granularity. forblockorientedcommands,thefollowingdefiniti onisused: block:istheunitwhichisrelatedtotheblockor ientedreadandwritecommands.itssizeisthenum berofbytes whichwillbetransferredwhenon eblockcommandissentbyhost.thesizeofabloc kiseitherprogramable orfixed.theinformationabouta llowedblocksizesandtheprogrammabilityisstore dinthecsd. forr/wcards,specialeraseandwriteprotectcomm andsaredefined: thegranularityoftheerasableunitsistheerase group:thesmallestnumberofconsecutivewriteblo ckswhichcan beaddressedforerase.thesizeoftheeras egroupiscardspecificandstoredinthecsd. thegranularityofthewriteprotectedunitsisthe wpgroup:theminimalunitwhichmaybeindividual lywrite protected.itssizeisdefinedinunitsof erasegroups.thesizeofawpgroupiscardspecif icandstoredinthecsd. rev 1.0 / sep. 2009 7 e-nand 1.6.5 read and write operations theenandsupportstworead/writemodes. single block mode inthismodethehostreadorwriteonedatablock inaprespecifiedlengthblocktransmissionispro tectedwith16bit crcwhichisgeneratedbythesendingunitandchec kedbythereceiveingunit.misalignmentisnotall owed.everydata blockmustbecontainedinasinglememroysector. theblocklengthforwriteopertaionmustbeidenti caltothesector sizeandthestartaddressalignedtoasectorboun dary. multiple block mode thismodeissimilartothesingleblockmode,but thehostcanread/writemultipledatablocks(allh avethesamelength) whichwillbestoredorretrivedfromcontiguousme moryaddressesstartingattheaddressspecifiedin thecommand. theoperationisterminatedwithastoptransmissio ncommand.misalignmentandblocklengthrestrictio nsapplytomultiple blocksaswellandareidenticaltothesinglebloc kread/writeoperations.multipleblockreadwithp redefinedblockissup ported. 1.6.6 data protection in the e-nand everysectorisprotectedwithanerrorcorrection code(ecc).theeccisgenerated(intheenand)wh enthe sectorsarewrittenandvalidatedwhenthedatais read.ifdefectsarefound,thedataiscorrectedp riortotransmissionto thehost.theenandcanbeconsiderederrorfreea ndnoadditionaldataprotectionisneeded.however ,ifanapplication usesadditional,external,eccprotection,thedata oragnizationisdefinedintheuserwriteablesect ionofthecsdregister. 1.6.7 erase thesmallesterasableunitintheenandisaerase group.inordertospeeduptheeraseprocedure,m ultipleerasegroups canbeerasedinthesametime.theeraseoperation isdividedintotwostages. tagging - selecting the sectors for erasing tofacilitateselection,afirstcommandwiththes tartingaddressisfollowedbyasecondcommandwit hthefinaladdress, andallerasegroupswithinthisrangewillbesele ctedforerase. erasing - starting the erase process taggingcanaddresserasegroups.anarbitrarysele ctionoferasegroupsmaybeerasedatonetime.ta gginganderasing mustfollowastrictcommandsequence(refertothe enandstandardsepcificationfordatails). 1.6.8 write protection twocardlevelwriteprotectionoptionsareavailab le:permanentandtemporary.bothcanbesetusing theprogram_csd command(refertocsdprogramming,section4.2.8). thepermanentwriteprotectbit,onceset,cannotb eclearded.this featureisimplementedintheenandcontrollerfir mwareandnotwithaphysicalotpcell. 1.6.9 copy bit thecontentofanenandcanbemarkedasanorigin aloracopyusingthecopybitinthecsdregister .oncethecopybit isset(makedasoriginal)itcannotbecleared.th ecopybitoftheenandisprogrammed(duringtest andformattingon themanufacturingfloor)asacopy.theenandcan bepurchasedwiththecopybitset(copy)orcleare d,indicatingthe cardisamaster.theonetimeprogrammable(otp)c haracteristicofthecopybitisimplementedinthe enandcontroller firmwareandnotwithaphysicalotpcell. rev 1.0 / sep. 2009 8 e-nand 1.6.10 the csd register alltheconfigurationinformationoftheenandis storedinthecsdregister. thehostcanreadthecsdregisterandaltertheho stcontrolleddatabytesusingthesend_csdandpro gram_csd commands. rev 1.0 / sep. 2009 9 e-nand 2. product specifications 2.1 environmental characteristics vddiforinternalpowerstability parameter value unit operationtemperature 25to85 storagetemperature 40to85 rev 1.0 / sep. 2009 10 e-nand ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & ' $ 7 1 & 1 & 1 & 1 & 1 & 9 6 6 4 9 ' ' l , q g h [ ' $ 7 ' $ 7 ' $ 7 ' $ 7 ' $ 7 ' $ 7 ' $ 9 & & 4 1 & 1 & 1 & 1 & 1 & 9 6 6 9 6 6 9 6 6 9 & & 9 & & 9 & & 9 & & 9 6 6 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 9 & & 4 9 6 6 4 & / . 9 & & 4 9 & & 4 9 & & 4 & 0 ' 9 6 6 4 9 6 6 4 9 6 6 4 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & ' 1 8 $ % & ' ( ) * + - . / 0 1 3 7 r s 9 l h z w k u r x j k 3 d f n d j h ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 ' 1 8 3. interface description 3.1 physical description 3.1.1 pin assignments figure 3-1 : e-nand pin configuration rev 1.0 / sep. 2009 11 e-nand table 3-1 : pin description note: 1.s:powersupply;i:input;o:output;pp:pushp ull;od:opendrain; 2.thedat0dat7pinsforreadonlycardsareoutpu tonly pins mmc interface name io type (1) description m5 cmd i/o/pp/od command/response m6 clk i clock e7,g5,h10,k8 vss s flashmemorysupplyvoltage ground c4,n2,n5,p4,p6 vssq s coresupplyvoltageground c6,m4,n4,p3,p5 vccq s coresupplyvoltage e6,f5,j10,k9 vcc s flashmemorysupplyvoltage a3 data0 i/o/pp data a4 dat1 i/o/pp data a5 dat2 i/o/pp data b2 dat3 i/o/pp data b3 dat4 i/o/pp data b4 dat5 i/o/pp data b5 dat6 i/o/pp data b6 dat7 i/o/pp data c2 vddi thecapacitor(0.1 ? )mustbe connectedforinternalpower stability. nc notconnected dnu donotuse rev 1.0 / sep. 2009 12 e-nand multimediacardhost r od 1 r dat r clk dat[7:0] c 2 c 3 c cmd cmd multimediacard 3.2 e-nand bus topology theenandbushastencommunicationlines: cmd:commandisabidirectionalsignal.thehostan denanddriversareoperatingintwomodes,opend rainand pushpull. dat07:datalinesarebidirectionalsignals.hos tandenanddriversareoperatinginpushpullmod e clk:clockisahosttoenandsignal.clkoperat esinpushpullmode vccq:vccqisthepowersupplylineforcoresign al vcc:vccisthepowersupplylineforflashmemor y vddi:thecapacitor(0.1 ? min.)mustbeconnectedtovddiforinternalpower stability vss,vssqaretwogroundlines figure 4-3 : bus circuitry diagram ther od isswitchedonandoffbythehostsynchronouslyt otheopendrainandpushpullmodetransitions.th ehost doesnothavetohaveopendraindrivers,butmust recognizethismodetoswitchonther od .r dat andr cmd arepull upresistorsprotectingthecmdandthedatlinesa gainstbusfloatingwhennocardisinsertedorwhe nallcarddrivers areinahighimpedancemode. aconstantcurrentsourcecanreplacether od byachievingabetterperformance(constantslopes forthesignalrising andfallingedges).ifthehostdoesnotallowthe switchabler od implementation,afixedr cmd canbeused(themini mumvalueisdefinedinthechapter).consequently themaximumoperatingfrequencyintheopendrain modehasto bereducediftheusedr cmd valueishigherthantheminimalonegivenintabl e34. thehostisrecommendedtoconnectcapacitortovdd iforenandsinternalpowerstability. rev 1.0 / sep. 2009 13 e-nand optional repetitions of cmd1 until the card is responding with busy bit set. power up time the longest of: 1ms, 74 clock cycles, the supply ramp up time, or the boot operation perlod. ccq (max) n cc n cc n cc v supply ramp up time first cmd1 to card ready memory field working voltage range z ? ? ? ? ? g ? ? ? ? ? ? ? cc v o t h p ccq (min) v cc (min) v control logic working voltage range ccq v cmd1 initialization sequence cmd1 cmd2 cmd1 initialization delay: 1 3.3.2 e-nand power-up theenandbuspowerupishandledlocallyineach deviceandinthebusmaster.figure34showsthe powerup sequenceandisfollowedbyspecificinstructionsr egardingthepowerupsequence. figure 3-4 : e-nand power-up diagram rev 1.0 / sep. 2009 14 e-nand 3.3.3 e-nand power-up guidelines theenandpowerupmustadheretothefollowinggu idelines: ? whenpowerupisinitiated,eithervccorvccqcan berampedupfirst,orbothcanberampedupsimul taneously. ? afterpowerup,theenandentersthepreidlesta te. ? iftheenanddoesnotsupportbootmodeoritsbo ot_partition_enablebitiscleared,theenandmove simmediately totheidlestate.whileintheidlestate,theen andignoresallbustransactionsuntilcmd1isrece ived.ifthe enandsupportsonlyspecificationv4.2orearlier versions,thedeviceenterstheidlestateimmediat elyfollowing powerup. ? iftheboot_partition_enablebitisset,theenan dmovestotheprebootstate,andtheenandwaits forthe bootinitiationsequence.followingthebootoperat ionperiod,theenandenterstheidlestate.durin gthepreboot state,iftheenandreceivesanycmdlinetransact ionotherthanthebootinitiationsequence(keepin gcmdlinelowfor atleast74clockcycles,orissuingcmd0withthe argumentof0xfffffffa)andcmd1,theenandmoves totheidle state.iftheenandreceivesthebootinitiations equence(keepingthecmdlinelowforatleast74c lockcycles,orissuing cmd0withtheargumentof0xfffffffa),theenandb eginsbootoperation.ifbootacknowledgeisenable d,the enandshallsendacknowledgepattern010tothe hostwithinthespecifiedtime.afterbootoperatio nisterminated, theenandenterstheidlestateandshallbeready forcmd1operation.iftheenandreceivescmd1in thepreboot state,itbeginsrespondingtothecommandandmove stothecardidentificationmode. ? whileintheidlestate,theenandignoresallbu stransactionsuntilcmd1isreceived. ? cmd1isaspecialsynchronizationcommandusedto negotiatetheoperationvoltagerangeandtopollt hedeviceuntil itisoutofitspowerupsequence.inadditionto theoperationvoltageprofileofthedevice,there sponsetocmd1 containsabusyflagindicatingthatthedeviceis stillworkingonitspowerupprocedureandisnot readyforidentification. thisbitinformsthehostthatthedeviceisnotre ady,andthehostmustwaituntilthisbitisclear ed.thedevice mustcompleteitsinitializationwithin1secondof thefirstcmd1issuedwithavalidocrrange. ? thebusmastermovesthedeviceoutoftheidlest ate.becausethepoweruptimeandthesupplyramp uptime dependonapplicationparameterssuchasthebusle ngthandthepowersupplyunit,thehostmustensur ethatpower isbuiltuptotheoperatinglevel(thesamelevel thatwillbespecifiedincmd1)beforecmd1istran smitted. ? afterpowerup,thehoststartstheclockandsend stheinitializingsequenceonthecmdline.these quencelengthis thelongestof:1ms,74clocks,thesupplyrampup time,orthebootoperationperiod.anadditional1 0clocks(beyond the64clocksofthepowerupsequence)areprovide dtoeliminatepowerupsynchronizationproblems. ? everybusmastermustimplementcmd1. rev 1.0 / sep. 2009 15 e-nand command input prohibited ccq (max) v sleep mode command input prohibited supply voltage cc v cc (min) v ccq v time 3.3.4 e-nand power cycling themastercanexecuteanysequenceofvccandvccq powerup/powerdown.however,themasterwithhost must notissueanycommandsuntilvccandvccqarestabl ewithineachoperatingvoltagerange.afterthesl avewiththee nandenterssleepmode,themasterwithhostcanpo werdownvcctoreducepowerconsumption.itisnec essaryfor theslavewithenandtoberampeduptovcc figure 3-5: the e-nand power cycle rev 1.0 / sep. 2009 16 e-nand 3.3.5 bus operating conditio ns general parameter symbol min max. unit remark peakvoltageonlines bga 0.5 vccq+0.5 v all inputs inputleakagecurrent (beforeini tializationsequenceand/ortheinternal pullupresistorsconnected) 100 100 ? inputleakagecurrent (afterinitial izationsequenceandtheinternalpullup resistorsdisconnected) 10 10 ? all inputs outputleakagecurrent current (beforeinitializationsequence) 100 100 ? outputleakagecurrent (after initializationsequence) 10 10 ? table 3-2 : bus operating conditions parameter symbol min max. unit remark supplyvoltage(nand) vcc 2.7 3.6 v supplyvoltage(i/o) vccq 2.7 3.6 v 1.7 1.95 v power supply voltage - e-nand table 3-3 : power supply voltage rev 1.0 / sep. 2009 17 e-nand 3.3.6 bus signal line load thetotalcapacitancec l ofeachlineoftheenandbusisthesumofthebu smastercapacitancec host ,thebus capacitancec bus itselfandthecapacitancec enand ofthecardconnectedtothisline: c l =c host +c bus +c enand requiringthesumofthehostandbuscapacitances nottoexceed20pf: parameter symbol min typ max. unit remark pullupresistanceforcmd r cmd 4.7 100 kohm topreventbusfloating pullupresistancefordat07 r dat 50 100 kohm topreventbusfloating bussignallinecapacitance c l 30 pf singlecard enandcapacitance c bga 7 12 maximumsignallineinductance 16 nh fpp<=52mhz table 3-4 : host and bus capacities rev 1.0 / sep. 2009 18 e-nand multimediacardhost r od 1 r dat r clk dat[7:0] c 2 c 3 c cmd cmd multimediacard parameter symbol min max. unit conditions 1.7 - 1.95v 2.7 - 3.6v 1.7 - 1.95v 2.7 - 3.6v outputhighvoltage v oh v ccq 0.2v 0.75*v ccq v i oh =100ma@v ccq min outputlowvoltage v ol 0.2v 0.125*v ccq v i ol =100ma@v ccq min inputhighvoltage v ih 0.7*v ccq 0.625*v ccq v ccq +0.3 v ccq +0.3 v inputlowvoltage v il vss0.3 vss0.3 0.3*v ccq 0.25*v ccq v 3.3.7 bus signal levels asthebuscanbesuppliedwithavariablesupplyv oltage,allsignallevelsarerelatedtothesupply voltage. figure 43: bus circuitry diagram 3.3.9 push-pull mode bus signal level - e-nand tomeettherequirementsofthejedecspecification jesd81a,thecardinputandoutputvoltagesshall be withinthefollowingspecifiedrangesforanyv ccq oftheallowedvoltagerange: table 3-6 : push-pull mode bus signal level - vccq rev 1.0 / sep. 2009 19 e-nand clk data data data data invalid invalid input output t wl t osu t oh dd tlh t thl t v 50% pp t wh t isu t ih t t odly dd v 50% min (v ) ih max (v ) il min (v ) ih max (v ) il min (v ) oh max (v ) ol 3.3.10 bus & e-nand interface timing datamustalwaysbesampledontherisingedgeoft heclock. figure 3-7 : timing diagram: data input/output rev 1.0 / sep. 2009 20 e-nand parameter symbol min max. unit remark clock clk clockfrequencydatatransfermode (pp) b f pp 0 52 mhz c l <=30pf tolerance:+100khz clockfrequencyidentificationmode (od) f od 0 400 khz tolerance:+20khz clocklowtime t wl 6.5 ns c l <=30pf clockrisetime d t tlh 3 ns c l <=30pf clockfalltime t thl 3 ns c l <=30pf inputs cmd, dat (referencedtoclk) inputsetuptime t isu 3 ns c l <=30pf inputholdtime t ih 3 ns c l <=30pf outputs cmd, dat (referencedtoclk) outputdelaytimeduringdatatransfer t odly 13.7 ns c l <=30pf outputholdtime t oh 2.5 ns c l <=30pf signalrisetime e t rise 3 ns c l <=30pf signalfalltime t fall 3 ns c l <=30pf a.alltimingvaluesaremeasuredrelativeto50%of voltagelevel b.theenandsupportsfullfrequencyrangefrom0 26mhz,or052mhz c.cardcanoperateashighspeedcardinterfacetim ingat26mhzclockfrequency. d.clkriseandfalltimesaremeasuredbymin(vih) andmax(vil). e.inputscmd,datriseandfalltimesaremeasured bymin(vih)andmax(vil),andoutputscmd, datriseandfalltimesaremeasuredbymin(voh)a ndmax(vol). table 3-6 : high speed e-nand interface timings c a rev 1.0 / sep. 2009 21 e-nand a.thecardmustalwaysstartwiththebackwardcomp atibleinterfacetiming.thetimingmodecanbeswi tchedto highspeedinterfacetimingbythehostsendingthe switchcommand(cmd6)withtheargumentforhighs peed interfaceselect. b.alltimingvaluesaremeasuredat50%ofvoltage level. c.forcompatibilitywithcardsthatsupportthev4. 2standardorearlier,hostshouldnotuse>20mhz beforeswitching tohighspeedinterfacetiming. d.clkriseandfalltimesaremeasuredbymin(vih) andmax(vil). table 3-7 : backwards compatible e-nand interface parameter symbol min max. unit remark clock clk b clockfrequencydatatransfermode (pp) f pp 0 26 mhz cl<=30pf clockfrequencyidentificationmode (od) f od 0 400 khz clocklowtime t wl 10 ns cl<=30pf clockrisetime d t tlh 10 ns cl<=30pf clockfalltime t thl 10 ns cl<=30pf inputs cmd, dat (referencedtoclk) inputsetuptime t isu 3 ns cl<=30pf inputholdtime t ih 3 ns cl<=30pf outputs cmd, dat (referencedtoclk) outputsetuptime t osu 11.7 ns cl<=30pf outputholdtime t oh 8.3 ns cl<=30pf a c rev 1.0 / sep. 2009 22 e-nand 3.4 e-nand registers withintheenandinterfacesixregistersaredefin ed:ocr,cid,csd,ext_csd,rcaanddsr.thesecan beaccessed onlybycorrespondingcommands.theocr,cidandcs dregisterscarrytheenand/contentspecificinfor mation, whilethercaanddsrregistersareconfigurationr egistersstoringactualconfigurationparameters.t he ext_csdregistercarriesboth,enandspecificinfo rmationandactualconfigurationparameters. 3.4.1 ocr register the32bitoperationconditionsregisterstoresthe vccqvoltageprofileoftheenand.inaddition,t hisregisterincludes astatusinformationbit.thisstatusbitissetif theenandpowerupprocedurehasbeenfinished.t heocrregister shallbeimplementedbyenand. ocr bit vccq voltage window e-nand [6:0] reserved 0000000b [7] 1.71.95 1b [14:8] 2.02.6 0000000b [23:15] 2.73.6 111111111b [28:24] reserved 0000000b [30:29] accessmode 00b(bytemode) 10b(sectormode) [31] enandpowerupstatusbit(busy) a a.thisbitissettolowiftheenandhasnotfini shedthepoweruproutine thesupportedvoltagerangeiscodedasshowninta ble,forenand.aslongastheenandisbusy,th ecorrespond ingbit(31)issettolow,thewiredandoperati on,describedinchapter4.2.2yieldslow,ifatle astoneenandis stillbusy. rev 1.0 / sep. 2009 23 e-nand 3.4.2 cid register thecardidentification(cid)registeris128bits wide.itcontainstheenandidentificationinforma tionusedduring thecardidentificationphase(enandprotocol).ev eryindividualflashorenandshallhaveanunique identification number.themsbbytesoftheregistercontainmanuf acturerdataandtwoleastsignificantbytescontai nsthehostcon trolleddatathecardcopyandwriteprotectiona ndtheusereccregister.everytypeofenandrom cards(defined bycontent)shallhaveanuniqueidentificationnum ber. thestructureofthecidregisterisdefinedinthe followingparagraphs: name field width cid-slice cid value comment manufacturerid mid 8 [127:120] 0x90 hynixmanufacturei d reserved 6 [119:114] card/bga cbx 2 [113:112] 01b oem/applicationid oid 8 [111:104] 0x4a productname pnm 48 [103:56] hynix 6asciicharacters productrevision prv 8 [55:48] 0x01 productserialnumber psn 32 [47:16] randomnumber manufacturingdate mdt 8 [15:8] 6c crc7checksum crc 7 [7:1] 2b notused,always1 1 [0:0] 1 table 3-8 : the cid fields a.theywillbechangedbymanufacturingdataandc ontents.allvaluesarenotfixedyet.pleaserefer tocurrentvalue rev 1.0 / sep. 2009 24 e-nand mid an8bitbinarynumberthatidentifiesthemanufact urer.themidnumberiscontrolled,definedandall ocatedtoae nandmanufacturerbythemmca.thisprocedureises tablishedtoensureuniquenessofthecidregister. cbx cbxindicatesthedevicetype. oid a8bitbinarynumberthatidentifiesthecardoem and/orthecardcontents(whenusedasadistributi onmediaeither onromorflashcards).theoidnumberiscontrolle d,definedandallocatedtoaenandmanufacturerb ythe mmca.thisprocedureisestablishedtoensureuniqu enessofthecidregister. pnm theproductnameisastring,6asciicharacterslo ng. prv theproductrevisioniscomposedoftwobinarycode ddecimal(bcd)digits,fourbitseach,representin gann.mrevi sion number.thenisthemostsignificantnibbleandm istheleastsignificantnibble. asanexample,theprvbinaryvaluefieldforprodu ctrevision6.2willbe:01100010 psn a32bitsunsignedbinaryinteger. mdt themanufacturingdateiscomposedoftwohexadecim aldigits,fourbitseach,representingatwodigit sdatecode m/y;themfield,mostsignificantnibble,isthem onthcode.1=january. theyfield,leastsignificantnibble,istheyear code.0=1997. asanexample,thebinaryvalueofthemdtfieldfo rproductiondateapril2000willbe:01000011 crc crc7checksum(7bits).thisisthechecksumofthe cidcontentscomputedaccordingtochapter6.4. 3.4.3 csd register thecardspecificdataregisterprovidesinformatio nonhowtoaccesstheenandcontents.thecsddef inesthe dataformat,errorcorrectiontype,maximumdataac cesstime,datatransferspeed,whetherthedsrreg istercanbe usedetc.theprogrammablepartoftheregister(en triesmarkedbywore,seebelow)canbechangedb ycmd27. thetypeoftheentriesinthetablebelowiscoded asfollows: [113:112] type 00 card(removable) 01 bga(embedded) 10,11 reserved rev 1.0 / sep. 2009 25 e-nand r=readable,w=writableonce,e=erasable(mult iplewritable). name field width cell type csdslice csd value csdstructure csd_structure 2 r [127:126] 2 systemspecificationversion spec_vers 4 r [125:122] 4 reserved 2 r [121:120] 0 datareadaccesstime1 taac 8 r [119:112] 4f datareadaccesstime2 inclkcycles(nsac*100) nsac 8 r [111:104] 1 max.busclockfrequency tran_speed 8 r [103:96] 32 enandcommandclasses ccc 12 r [95:84] f5 max.readdatablocklength read_bl_len 4 r [83:80] 9 partialblocksforreadallowed read_bl_partial 1 r [79: 79] 1 writeblockmisalignment write_blk_misalign 1 r [78:78] 0 readblockmisalignment read_blk_misalign 1 r [77:77] 0 dsrimplemented dsr_imp 1 r [76:76] 0 reserved 2 r [75:74] 0 devicesize c_size 12 r [73:62] f0f max.readcurrent@v ccq min v ccq _r_curr_min 3 r [61:59] 7 max.readcurrent@v ccq max v ccq _r_curr_max 3 r [58:56] 7 max.writecurrent@v ccq min v ccq _w_curr_min 3 r [55:53] 7 max.writecurrent@v ccq max v ccq _w_curr_max 3 r [52:50] 7 devicesizemultiplier c_size_mult 3 r [49:47] 7 erasegroupsize erase_grp_size 5 r [46:42] 1f erasegroupsizemultiplier erase_grp_mult 5 r [41:37] 1 f writeprotectgroupsize wp_grp_size 5 r [36:32] 1 writeprotectgroupenable wp_grp_enable 1 r [31:31] 1 manufacturerdefaultecc default_ecc 2 r [30:29] 0 writespeedfactor r2w_factor 3 r [28:26] 2 max.writedatablocklength write_bl_len 4 r [25:22] a partialblocksforwriteallowed write_bl_partial 1 r [21 :21] 0 reserved 4 r [20:17] 0 contentprotectionapplication content_prot_app 1 r [16: 16] 0 fileformatgroup file_format_grp 1 r/w [15:15] 0 copyflag(otp) copy 1 r/w [14:14] 0 permanentwriteprotection perm_write_protect 1 r/w [13:13] 0 temporarywriteprotection tmp_write_protect 1 r/w/e [12:12] 0 fileformat file_format 2 r/w [11:10] 0 ecccode ecc 2 r/w/e [9:8] 0 crc crc 7 r/w/e [7:1] 4d notused,always1 1 [0:0] 1 rev 1.0 / sep. 2009 26 e-nand thefollowingsectionsdescribethecsdfieldsand therelevantdatatypes.ifnotexplicitlydefined otherwise,allbit stringsareinterpretedasbinarycodednumberssta rtingwiththeleftbitfirst. csd_structure describestheversionofthecsdstructure. csd_structure csd structure version valid for system specification version 0 csdversionno.1.0 allocatedbymmca 1 csdversionno.1.1 allocatedbymmca 2 csdversionno.1.2 version4.14.24.3 3 versioniscodedinthecsd_structurebyteinthe ext_csdregister spec_vers system specification version number 0 allocatedbymmca 1 allocatedbymmca 2 allocatedbymmca 3 allocatedbymmca 4 version4.14.24.3 515 reserved taac definestheasynchronouspartofthedataaccessti me. taac bit position code 2:0 timeunit 0=1ns,1=10ns,2=100ns,3=1s,4=10s,5=100s,6=1 ms,7=10ms 6:3 multiplierfactor 0=reserved,1=1.0,2=1.2,3=1.3,4=1.5,5=2.0,6=2. 5,7=3.0,8=3.5,9=4.0,a=4.5, b=5.0,c=5.5,d=6.0,e=7.0,f=8.0 7 reserved nsac definesthetypicalcasefortheclockdependentfa ctorofthedataaccesstime.theunitfornsacis 100clockcycles. therefore,themaximalvaluefortheclockdependen tpartofthedataaccesstimeis25.5kclockcycle s. thetotalaccesstimenacasexpressedintabletaa ciscalculatedbasedontaacandnsac.ithastob ecomputed bythehostfortheactualclockrate.thereadacc esstimeshouldbeinterpretedasatypicaldelayf orthefirstdatabit ofadatablockorstream. spec_vers definesthejedecjesd84v4.3seriesofspecificati onssupportedbytheenand. rev 1.0 / sep. 2009 27 e-nand tran_speed thefollowingtabledefinestheclockfrequencywhe nnotinhighspeedmode.forenansupportingvers ion4.3,the valueshallbe 26mhz(0x32). taac bit position code 2:0 frequencyunit 0=100khz,1=1mhz,2=10mhz,3=100mhz, 4...7=reserved 6:3 multiplierfactor 0=reserved,1=1.0,2=1.2,3=1.3,4=1.5,5=2.0,6=2. 6,7=3.0,8=3.5,9=4.0, a=4.5,b=5.2,c=5.5,d=6.0,e=7.0,f=8.0 7 reserved ccc theenandcommandsetisdividedintosubsets(com mandclasses).theenandcommandclassregistercc c defineswhichcommandclassesaresupportedbythis card.avalueof1inacccbitmeansthatthecor responding commandclassissupported.forcommandclassdefin itionrefertotable48. ccc bit supported card command class 0 class0 1 class1 ...... 11 class11 read_bl_len thedatablocklengthiscomputedas2read_bl_len. theblocklengthmightthereforebeintherange 1b, 2b,4b...16kb. bytes(seechapter4.10fordetails): read_bl_len supported card command class 0 2 0 =1byte 1 2 1 =2bytes ...... 11 2 11 =2048bytes 12 2 12 =4096bytes 13 2 13 =8192bytes 14 2 14 =16kbytes 15 2 15 =extention newregistertbdtoext_csd rev 1.0 / sep. 2009 28 e-nand read_bl_partial defineswhetherpartialblocksizescanbeusedin blockreadcommands. upto2gbofdensity(byteaccessmode): read_bl_partial=0meansthatonlythe512bandthe read_bl_lenblocksizecanbeusedforblockorient ed datatransfers. read_bl_partial=1meansthatsmallerblockscanbe usedaswell.theminimumblocksizewillbeequal tomini mumaddressableunit(onebyte). higherthan2gbofdensity(sectoraccessmode): read_bl_partial=0meansthatonlythe512bandthe read_bl_lenblocksizescanbeusedforblockorien ted datatransfers. read_bl_partial=1meansthatsmallerblocksthanin dicatedinread_bl_lencanbeusedaswell.themin imum blocksizewillbeequaltominimumaddressableuni t,onesector(512b). rev 1.0 / sep. 2009 29 e-nand write_blk_misalign definesifthedatablocktobewrittenbyonecomm andcanbespreadovermorethanonephysicalblock ofthe memorydevice.thesizeofthememoryblockisdefi nedinwrite_bl_len. write_blk_misalign=0signalsthatcrossingphysical blockboundariesisinvalid. write_blk_misalign=1signalsthatcrossingphysical blockboundariesisallowed. read_blk_misalign definesifthedatablocktobereadbyonecommand canbespreadovermorethanonephysicalblockof themem orydevice.thesizeofthememoryblockisdefined inread_bl_len. read_blk_misalign=0signalsthatcrossingphysical blockboundariesisinvalid. read_blk_misalign=1signalsthatcrossingphysical blockboundariesisallowed. dsr_imp definesiftheconfigurabledriverstageisintegra tedontheenand.ifset,adriverstageregister (dsr)mustbe implementedalso(seechapter3.5.6). dsr_imp dsr type 0 dsrisnotimplemented 1 dsrimplemented c_size thisparameterisusedtocomputetheenandcapaci ty.thememorycapacityoftheenandiscomputedf romthe entriesc_size,c_size_multandread_bl_lenasfoll ows: enandcapacity=blocknr*block_len where blocknr=(c_size+1)*mult mult=2 c_size_mult+2 (c_size_mult<8) block_len=2 read_bl_len ,(read_bl_len<12) therefore,themaximalcapacitywhichcanbecoded is4096*512*2048=4gbytes.example:a4mbyteen and withblock_len=512canbecodedbyc_size_mult= 0andc_size=2047. vccq_r_curr_min, vccq_w_curr_min themaximumvaluesforreadandwritecurrentsatt heminimalpowersupplyv ccq arecodedasfollows: vccq_r_curr_min vccq_w_curr_min codeforcurrentconsumption@vccq 2:0 0=0.5ma;1=1ma;2=5ma;3=10ma;4=25ma;5=35ma;6=60 ma;7=100ma thevaluesinthesefieldsarevalidwhenthevccq isnotinhighspeedmode.whenthevccqisinhigh speed mode,thecurrentconsumptionischosenbythehost ,fromthepowerclassesdefinedinthepwr_ff_vvv registers, intheext_csdregister. rev 1.0 / sep. 2009 30 e-nand vccq_r_curr_max, vccq_w_curr_max themaximumvaluesforreadandwritecurrentsatt hemaximalpowersupplyvccqarecodedasfollows: vccq_r_curr_min vccq_w_curr_min codeforcurrentconsumption@v ccq 2:0 0=1ma;1=5ma;2=10ma;3=25ma;4=35ma;5=45ma;6=80m a;7=200ma thevaluesinthesefieldsarevalidwhentheenan disnotinhighspeedmode.whentheenandisin highspeed mode,thecurrentconsumptionischosenbythehost ,fromthepowerclassesdefinedinthepwr_ff_vvv registers,in theext_csdregister. c_size_mult thisparameterisusedforcodingafactormultfor computingthetotaldevicesize(seec_size).the factormultis definedas2 c_size_mult+2 . c_size_mult mult 0 2 2 =4 1 2 3 =8 2 2 4 =16 3 2 5 =32 4 2 6 =64 5 2 7 =128 6 2 8 =256 7 2 9 =512 erase_grp_size thecontentsofthisregisterisa5bitbinarycod edvalue,usedtocalculatethesizeoftheerasabl eunitofthe enand.thesizeoftheeraseunit(alsoreferredt oaserasegroup)isdeterminedbytheerase_grp_si zeandthe erase_grp_multentriesofthecsd,usingthefollow ingequation: sizeoferasableunit=(erase_grp_size+1)*(era se_grp_mult+1) thissizeisgivenasminimumnumberofwriteblock sthatcanbeerasedinasingleerasecommand. erase_grp_mult a5bitbinarycodedvalueusedforcalculatingthe sizeoftheerasableunitoftheenand.seeerase _grp_size sectionfordetaileddescription. wp_grp_size thesizeofawriteprotectedgroup.thecontentso fthisregisterisa5bitbinarycodedvalue,defi ningthenumber oferasegroupswhichcanbewriteprotected.thea ctualsizeiscomputedbyincreasingthisnumberby one.a valueofzeromeans1erasegroup,31means32eras egroups. rev 1.0 / sep. 2009 31 e-nand wp_grp_enable avalueof0meansnogroupwriteprotectionpossib le. default_ecc setbythemanufacturer.itdefinestheecccodewh ichisrecommendedforuse.thefielddefinitionis thesameas fortheeccfielddescribedlater. r2w_factor definesthetypicalblockprogramtimeasamultipl eofthereadaccesstime.thefollowingtabledefi nesthefield format. c_size_mult multiples of read access time 0 1 1 2(writehalfasfastasread) 2 4 3 8 4 16 5 32 6 64 7 128 write_bl_len blocklengthforwriteoperations.seeread_bl_len forfieldcoding. notethatthesupportfor512bwriteaccessismand atoryforallcards.andthatthecardshastobei n512bblock lengthmodebydefaultafterpoweron,orsoftware reset.thepurposeofthisregisteristoindicate thesupported maximumwritedatablocklength. write_bl_partial defineswhetherpartialblocksizescanbeusedin blockwritecommands. upto2gbofdensity(byteaccessmode): write_bl_partial=0meansthatonlythe512bandt hewrite_bl_lenblocksizecanbeusedforblockor i enteddatawrite. write_bl_partial=1meansthatsmallerblockscan beusedaswell.theminimumblocksizeisonebyte . higherthan2gbofdensity(sectoraccessmode): write_bl_partial=0meansthatonlythe512bandt hewrite_bl_lenblocksizecanbeusedforblockor i enteddatawrite. write_bl_partial=1meansthatsmallerblockscan beusedaswell.theminimumblocksizewillbeequ alto minimumaddressableunit,onesector(512b). rev 1.0 / sep. 2009 32 e-nand file_format_grp indicatestheselectedgroupoffileformats.this fieldisreadonlyforrom.theusageofthisfield isshownin table325(seefile_format). copy definesifthecontentsisoriginal(=0)orhasbe encopied(=1).thecopybitforotpandmtpdevice s,soldto endconsumers,issetto1whichidentifiesthecar dcontentsasacopy.thecopybitisanonetimep rogrammable bit. perm_write_protect permanentlyprotectsthewholecardcontentagainst overwritingorerasing(allwriteanderasecomman dsforthis cardarepermanentlydisabled).thedefaultvaluei s0,i.e.notpermanentlywriteprotected. rev 1.0 / sep. 2009 33 e-nand tmp_write_protect temporarilyprotectsthewholecardcontentfrombe ingoverwrittenorerased(allwriteanderasecomm andsfor cardaretemporarilydisabled).thisbitcanbeset andreset.thedefaultvalueis0,i.e.notwrite protected. content_prot_app thisfieldinthecsdindicateswhetherthecontent protectionapplicationissupported.enandwhich implementthe contentprotectionapplicationwillhavethisbits etto1; file_format indicatesthefileformatonthecard.thisfieldi sreadonlyforrom.thefollowingformatsaredefi ned: file_format_grp file_format type 0 0 harddisklikefilesystemwithpartitiontable 0 1 dosfat(floppylike)withbootsectoronly(nop artitiontable) 0 2 universalfileformat 0 3 others/unknown 1 0,1,2,3 reserved amoredetaileddescriptionisgivenin"fileforma tsspecificationsforenand". ecc definestheecccodethatwasusedforstoringdata onthecard.thisfieldisusedbythehost(orap plication)to decodetheuserdata.thefollowingtabledefinest hefieldformat.: ecc file_format maximum number of correctable bits per block 0 none (default) none 1 bch (542,512) 3 2,3 reserved - crc thecrcfieldcarriesthechecksumforthecsdcon tents.itiscomputedaccordingtochapter6.4.the checksum hastoberecalculatedbythehostforanycsdmodi fication.thedefaultcorrespondstotheinitialcs dcontents. rev 1.0 / sep. 2009 34 e-nand thefollowingtableliststhecorrespondencebetwee nthecsdentriesandthecommandclasses.a+en tryindicates thatthecsdfieldaffectsthecommandsoftherela tedcommandclass. command classes csd field 0 1 2 3 4 5 6 7 8 9 csd_structure + + + + + + + + + + spec_vers + + + + + + + + + + taac + + + + + + + + nsac + + + + + + + + tran_speed + + + + ccc + + + + + + + + + + read_bl_len + read_bl_partial + write_blk_misalign + read_blk_misalign + dsr_imp + + + + + + + + + + c_size_mant + + + + + + + + c_size_exp + + + + + + + + vccq_r_curr_min + + vccq_r_curr_max + + vccq_w_curr_min + + + + + + vccq_w_curr_max + + + + + + erase_grp_size + + + + wp_grp_size + + + wp_grp_enable + + + default_ecc + + + + + + + + r2w_factor + + + + + + write_bl_len + + + + + + write_bl_partial + + + + + + file_format_grp copy + + + + + + + + + + perm_write_protect + + + + + + + + + + tmp_write_protect + + + + + + + + + + file_format ecc + + + + + + + + crc + + + + + + + + + + rev 1.0 / sep. 2009 35 e-nand 3.4.4 extended csd register theextendedcsdregisterdefinestheenandproper tiesandselectedmodes.itis512byteslong. themostsignificant320bytesarethepropertiess egment,whichdefinestheenandcapabilitiesandc annotbe modifiedbythehost.thelower192bytesarethem odessegment,whichdefinestheconfigurationthee nandis workingin.thesemodescanbechangedbythehost bymeansoftheswitchcommand name field size (bytes) cell type csd-slice reserved value properties segment reserved 1 7 [511:505] supportedcommandsets s_cmd_set 1 r [504] 1 reserved 1 275 tbd [503:229] bootinformation boot_info 1 r [228] 1 reserved 1 1 tbd [227] bootpartitionsize boot_size_multi 1 r [226] 2 accesssize acc_size 1 r [225] 0 highcapacityeraseunitsize hc_erase_grp_size 1 r [224] 0 highcapacityerasetimeout erase_timeout_mult 1 r [223] 0 reliablewritesectorcount rel_wr_sec_c r [222] 1 highcapacitywriteprotect groupsize hc_wp_grp_size 1 r [221] 0 sleepcurrent(vcc) s_c_vcc 1 r [220] 04h sleepcurrent(vccq) s_c_vccq 1 r [219] 08h reserved 1 1 tbd [218] sleep/awaketimeout s_a_timeout 1 r [217] 0bh reserved 1 1 tbd [216] 0 sectorcount sec_count 4 r [215:212] 0 reserved 1 1 [211] minimumwriteperformancefor 8bit@52mhz min_perf_w_8_52 1 r [210] 08h minimumreadperformancefor 8bit@52mhz min_perf_r_8_52 1 r [209] 08h minimumwriteperformancefor 8bit@26mhz/4bit@52mhz min_perf_w_8_26_4_52 1 r [208] 08h rev 1.0 / sep. 2009 36 e-nand name field size (bytes) cell type csd-slice reserved value minimumreadperformancefor 8bit@26mhz/4bit@52mhz min_perf_w_8_26_4_52 1 r [207] 08h minimumwriteperformancefor 4bit@26mhz min_perf_w_4_26 1 r [206] 08h minimumreadperformancefor 4bit@26mhz min_perf_w_4_26 1 r [205] 08h reserved 1 1 r [204] powerclassfor26mhz@3.6v pwr_cl_26_360 1 r [203] 0 powerclassfor52mhz@3.6v pwr_cl_52_360 1 r [202] 0 powerclassfor26mhz@ 1.95v pwr_cl_26_195 1 r [201] 0 powerclassfor52mhz@ 1.95v pwr_cl_52_195 1 r [200] 0 reserved 1 3 [199:197] cardtype card_type 1 r [196] 3 reserved 1 1 [195] csdstructureversion csd_structure 1 r [194] 2 reserved 1 1 [193] extendedcsdrevision ext_csd_rev 1 r [192] 03h commandset cmd_set 1 r/w [191] 0 reserved 1 1 [190] commandsetrevision cmd_set_rev 1 ro [189] 0 reserved 1 1 [188] powerclass power_class 1 r/w [187] 0 reserved 1 1 [186] highspeedinterfacetiming hs_timing 1 r/w [185] 0 reserved 1 1 [184] buswidthmode bus_width 1 wo [183] 1 reserved 1 1 [182] rev 1.0 / sep. 2009 37 e-nand bit command set 75 reserved 4 allocatedbymmca 3 allocatedbymmca 2 allocatedbymmca 1 allocatedbymmca 0 standardmmc note: 1.reservedbitsshouldreadas0 table 3-27 : extended csd s_cmd_set thisfielddefineswhichcommandsetsaresupported bytheenand. name field size (bytes) cell type csd-slice reserved value erasedmemorycontent erased_mem_cont 1 ro [1817] 0 reserved 1 1 [180] bootconfiguration boot_config 1 r/w [179] 0 reserved 1 1 [178] bootbuswidth boot_bus_wodth 1 r/w [177] 0 reserved 1 1 [176] highdensityerasegroup definition erase_group_def 1 r/w [175] 0 reserved 1 175 [174:0] rev 1.0 / sep. 2009 38 e-nand boot_info bit[7:1]:reserved bit[0]:alt_boot_mode 0:devicedoesnotsupportalternatebootmet 1:devicesupportsalternatebootmethod. boot_size_mult thebootpartitionsizeiscalculatedfromtheregi sterbyusingthefollowingequation: boot partition size 128kbytes boot_size_mult bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved alt_boot_mode acc_size bit[7:4]:reserved bit[3:0]:super_page_size thisregisterdefinesoneormultipleofprogrammab leboundaryunitwhichisprogrammedatthesame time.thisvaluecanbeusedbythemasterforthe followingcases: asaguideforformatclusters topreventformatpagemisalignment asaguideforminimumdatatransfersize superpagesize=5122(super_page_size1):0 rev 1.0 / sep. 2009 40 e-nand rel_wr_sec_c thereliablewritefeaturerequiresmandatorysecto rcount1(512b)support. withthisregisteritisalsopossibletoindicate anadditionalsupportedsectorcount. inapplicationswhereonlythesinglesectorwrite issupported,thevalueintheregistershouldbe 1.otherwise,the valueshouldbethemultipleofthenumberofsecto rssupported. hc_wp_grp_size thisregisterdefinesthewriteprotectgroupsize forhighcapacitymemory.iftheenablebitineras e_group_def issettohigh,thewriteprotectgroupsizewould bedefinedasfollows: writeprotectgroupsize=512kb*hc_erase_grp_siz e*hc_wp_grp_size. value timeout values 0x00 nosupportforhighcapacityerasetimeout 0x01 300msx1=300ms 0x02 300msx2=600ms : : 0xff 300msx255=76,500ms name field size cell type reliablewritesectorcount rel_wr_sec_c 1 r value timeout values 0x00 nosupportforhighcapacitywriteprotectgrou psize 0x01 1highcapacityeraseunitsize 0x02 2highcapacityeraseunitsize 0x03 3highcapacityeraseunitsize : : 0xff 255highcapacityeraseunitsize rev 1.0 / sep. 2009 41 e-nand iftheenablebitinerase_group_defisclearedto loworhc_wp_grp_sizeissetto0x00,thewritepro tect groupsizedefinitionwouldbetheoriginalcase. s_c_vcc, s_c_vccq thes_c_vccands_c_vccqregistersdefinethemaxv cccurrentconsumptionduringthesleepstate(slp) .the formulatocalculatethemaxcurrentvalueis: sleepcurrent=1a*2x:registervalue=x>0 sleepcurrent=novalue(legacy):registervalue =0 maxregistervaluedefinedis0x0dwhichequals8.1 92ma.valuesbetween0x0eand0xffarereserved. s_a_timeout thisregisterdefinesthemaxtimeoutvalueforsta tetransitionsfromstandbystate(stby)tosleeps tate(slp)and fromsleepstate(slp)tostandbystate(stby).the formulatocalculatethemaxtimeoutvalueis: sleep/awaketimeout=100ns*2s_a_timeout maxregistervaluedefinedis0x17whichequals838 .86mstimeout.valuesbetween0x18and0xffareres erved. sec_count thedevicedensityiscalculatedfromtheregister bymultiplyingthevalueoftheregister(sectorco unt)by512b/sector. themaximumdensitypossibletobeindicatedisthu s2terabytes(4294967296x512b).theleastsi gnificant byte(lsb)ofthesectorcountvalueisthebyte[2 12]. value value definition 0x00 notdefined 0x01 1uax2 1 =2ua 0x02 1uax2 2 =4ua : : 0x17 1uax2 13 =8.192ma 0x180xff reserved value value definition 0x00 notdefined 0x01 100nsx2 1 =200ns 0x02 100nsx2 2 =400ns : : 0x17 100nsx2 23 =838.86ns 0x180xff reserved rev 1.0 / sep. 2009 42 e-nand min_perf_a_b_ff thesefieldsdefinestheoverallminimumperformanc evalueforthereadandwriteaccesswithdifferen tbuswidth andmaxclockfrequencymodes.thevalueinthereg isteriscodedasfollows.otherthandefinedvalue sareillegal. value value definition 0x00 forcardsnotreachingthe2.4mb/svalue 0x08 classa:2.4mb/sandisthenextallowedvalue (16x150kb/s) 0x0a classa:2.4mb/sandisthenextallowedvalue (16x150kb/s) 0x0f classc:4.5mb/sandisthenextallowedvalue (30x150kb/ 0x14 classd:6.0mb/sandisthenextallowedvalue (40x150kb/s) 0x1e classe:9.0mb/sandisthenextallowedvalue(60x 150kb/s) thisisalsothehighestclasswhichanymmcplusor mmcmobilecardisneededtosupportinlow buscategoryoperationmode(26mhzwith4bitdatab us). ammcplusormmcmobilecardsupportinganyhigherc lassthanthishavetosupportthisclassalso (inlowcategorybusoperationmode). 0x28 classd:12.0mb/sandisthenextallowedvalu e(80x150kb/s) 0x32 classd:15.0mb/sandisthenextallowedvalu e(100x150kb/s) 0x3c classd:18.0mb/sandisthenextallowedvalu e(120x150kb/s) 0x46 classd:21.0mb/sandisthenextallowedvalue(14 0x150kb/s) thisisalsothehighestclasswhichanymmcplusor mmcmobilecardisneededtosupportinmid buscategoryoperationmode(26mhzwith8bitdatab usor52mhzwith4bitdatabus). ammcplusormmcmobilecardsupportinganyhigherc lassthanthishavetosupportthisclass(in midcategorybusoperationmode)andclassealso( inlowcategorybusoperationmode) 0x50 classd:24.0mb/sandisthenextallowedvalu e(160x150kb/s) 0x64 classd:30.0mb/sandisthenextallowedvalu e(200x150kb/s) 0x78 classd:36.0mb/sandisthenextallowedvalu e(240x150kb/s) 0x8c classd:42.0mb/sandisthenextallowedvalu e(280x150kb/s) 0x40 classd:48.0mb/sandisthelastdefinedvalu e(320x150kb/s) rev 1.0 / sep. 2009 43 e-nand pwr_cl_ff_vvv thesefieldsdefinethesupportedpowerclassesby theenand.bydefault,theenandhastooperatea tmaximum frequencyusing1bitbusconfiguration,withinthe defaultmaxcurrentconsumption,asstatedinthe tablebelow.if4 bit/8bitsbusconfigurations,requireincreasedcu rrentconsumption,ithastobestatedinthesereg isters. byreadingtheseregistersthehostcandeterminet hepowerconsumptionoftheenandindifferentbus modes.bits [7:4]codethecurrentconsumptionforthe8bitbu sconfiguration.bits[3:0]codethecurrentconsum ptionforthe4 bitbusconfigurationthepwr_52_vvvregistersare notdefinedfor26mhzenand. voltage value max rms current max peak current remarks 3.6v 0 100ma 200ma defaultcurrentconsumptionforhighv oltagecards 1 120ma 220ma 2 150ma 250ma 3 180ma 280ma 4 200ma 300ma 5 220ma 320ma 6 250ma 350ma 7 300ma 400ma 8 350ma 450ma 9 400ma 500ma 10 450ma 550ma 1115 reservedforfutureuse rev 1.0 / sep. 2009 44 e-nand themeasurementformaxrmscurrentisdoneasaver agermscurrentconsumptionoveraperiodof100ms. maxpeakcurrentisdefinedasabsolutemaxvaluen ottobeexceededatall. theconditionsunderwhichthepowerclassesarede finedare: maximumbusfrequency maximumoperatingvoltage worstcasefunctionaloperation worstcaseenvironmentalparameters(temperature,.. .) theseregistersdefinethemaximumpowerconsumptio nforanyprotocoloperationindatatransfermode, ready stateandidentificationstate. card_type thisfielddefinesthetypeoftheenand.theonly currentlyvalidvaluesforthisfieldare0x01and 0x03. bit card type 7:2 reserved 1 highspeedenand@52mhz 0 highspeedenand@26mhz csd_structure thisfieldisacontinuationofthecsd_structuref ieldinthecsdregister csd_structure csd structure version valid for system specification version 0 csdversionno.1.0 allocatedbymmca 1 csdversionno.1.1 allocatedbymmca 2 csdversionno.1.2 version4.14.24.3 3255 reservedforfutureuse ext_csd_rev definesthefixedparameters.relatedtotheext_cs d,accordingtoitsrevision ext_csd_rev extended csd revision 2554 reserved 3 revision1.3 2 revision1.2 1 revision1.1 0 revision1.0 rev 1.0 / sep. 2009 45 e-nand cmd_set containsthebinarycodeofthecommandsetthatis currentlyactiveinthecard.itissetto0(stan dardmmc)after powerupandcanbechangedbyaswitchcommand.no tethatwhilechangingthecommandsetwiththeswi tch command,bitindexvaluesaccordingtothes_cmd_se tregistershouldbeused.forbackwardcompatibili ty,the cmd_setissetto0x00(standardmmc)followingpow erup.afterswitchingbacktothestandardmmccom mand setwiththeswitchcommand,thevalueofthecmd_s etis0x01. cmd_set_rev containsabinarynumberreflectingtherevisionof thecurrentlyactivecommandset.forstandardmmc .command setitis: code mmc revisions 2551 reserved 0 v4.0 thisfield,thoughinthemodessegmentoftheext_ csd,isreadonly. bits description [7:4] reserved [3:0] cardpowerclasscode(seetable32) hs_timing thisfieldis0afterpoweron,orsoftwarereset, thusselectingthebackwardscompatibilityinterfac etimingforthe enand.ifthehostwrites1tothisfield,theen andchangesitstimingtohighspeedinterfacetimi ng bus_width itissetto0(1bitdatabus)afterpowerupand canbechangedbyaswitchcommand. erased_mem_cont thisfielddefinesthecontentofanexplicitlyera sedmemoryrange. value bus mode 2553 reserved 2 8bitdatabus 1 4bitdatabus 0 1bitdatabus power_class rev 1.0 / sep. 2009 46 e-nand boot_config thisregisterdefinestheconfigurationforbootop eration. bit7:reserved bit6:boot_ack(nonvolatile) 0x0:nobootacknowledgesent(default) 0x1:bootacknowledgesentduringbootoperation bit[5:3]:boot_partition_enable(nonvolatile) userselectsbootdatathatwillbesenttomaster 0x0:devicenotbootenabled(default) 0x1:bootpartition1enabledforboot 0x2:bootpartition2enabledforboot 0x3C0x6:reserved 0x7:userareaenabledforboot bit[2:0]:boot_partition_access userselectsbootpartitionforreadandwriteoper ation 0x0:noaccesstobootpartition(default) 0x1:r/wbootpartition1 0x2:r/wbootpartition2 0x3C0x7:reserved boot_bus_width thisregisterdefinestheconfigurationforbootop eration. value erased memory content 2552 reserved 1 erasedmemoryrangeshallbe1 2 erasedmemoryrangeshallbe0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved boot_ack boot_partition_enable boot_partition _access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reset_boot_bus_width boot_bus_width rev 1.0 / sep. 2009 47 e-nand bit[7:3]:reserved bit2:reset_boot_bus_width(nonvolatile) 0x0:resetbuswidthtox1afterbootoperation(d efault) 0x1:retainbootbuswidthafterbootoperation bit[1:0]:boot_bus_width(nonvolatile) 0x0:x1buswidthinbootoperationmode(default) 0x1:x4buswidthinbootoperationmode 0x2:x8buswidthinbootoperationmode 0x3:reserved erase_group_def thisregisterallowsmastertoselecthighcapacity eraseunitsize,timeoutvalue,andwriteprotect group size.bitdefaultsto0onpoweron. bit[7:1]:reserved bit0:enable 0x0:useolderasegroupsizeandwriteprotect groupsizedefinition(default) 0x1:usehighcapacityeraseunitsize,highcap acityerasetimeout,andhighcapacitywriteprotec t groupsizedefinition. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved enable rev 1.0 / sep. 2009 48 e-nand 3.4.5 rca register thewritable16bitrelativeenandaddressregiste rcarriestheenandaddressassignedbythehostd uringthe enandidentification.thisaddressisusedforthe addressedhostenandcommunicationaftertheena ndidentifi cationprocedure.thedefaultvalueofthercaregi steris0x0001.thevalue0x0000isreservedtoset allenandinto thestandbystatewithcmd7. 3.4.6 dsr register the16bitdriverstageregistercanbeoptionally usedtoimprovethebusperformanceforextendedop eratingcondi tions(dependingonparameterslikebuslength,tra nsferrateornumberofcards).thecsdregisterca rriestheinfor mationaboutthedsrregisterusage.thedefaultva lueofthedsrregisteris0x404. rev 1.0 / sep. 2009 49 e-nand 4. e-nand protocol description allcommunicationbetweenhostandenandiscontro lledbythehost(master).thehostsendscommands oftwo types: broadcastandaddressed(pointtopoint)commands. broadcastcommands:broadcastcommandsareintende dforenandinammccardsystem 1 .someofthese commandsrequirearesponse. addressed(pointtopoint)commands:theaddressed commandsaresenttotheaddressedenandandcaus e aresponsefromthisenand. ageneraloverviewofthecommandflowisshownin figure41fortheenandidentificationmodeandi nfigure42 forthedatatransfermode.thecommandsarelisted inthecommandtables(table48table417).th edependen ciesbetweencurrentstate,receivedcommandandfo llowingstatearelistedintable418.inthefoll owingsections, thedifferentcardoperationmodesaredescribedfi rst.thereafter,therestrictionsforcontrollingt heclocksignalare defined.allenandcommandstogetherwiththecorr espondingresponses,statetransitions,errorcondi tionsand timingsarepresentedinthesucceedingsections. threeoperationmodesaredefinedfortheenandsy stem(hostsandenand): cardidentificationmode thehostwillbeinenandidentificationmod eafterreset,whileitislookingforaenandon thebus. theenandwillbeinthismodeafterreset, untiltheset_rcacommand(cmd3)isreceived. interruptmode hostandenandenterandexitinterruptmod esimultaneously.ininterruptmodethereisnodat atransfer.the onlymessageallowedisaninterruptservice requestfromtheenandorthehost. datatransfermode theenandwillenterdatatransfermodeonceanrc aisassignedtoit.thehostwillenterdatatrans fermode afteridentifyingtheenandonthebus. thefollowingtableshowsthedependenciesbetween busmodes,operationmodesandenandstates.each statein theenandstatediagram(seefigure45andfigure 46)isassociatedwithonebusmodeandoneopera tionmode: card state operation mode bus mode inactivestate inactive opendrain preidlestate bootmode prebootstate idlestate enandidentificationmode readystate identificationstate standbystate datatransfermode pushpull sleepstate transferstate busteststate sendingdatastate receivedatastate programmingstate disconnectstate rev 1.0 / sep. 2009 50 e-nand 1.broadcastcommandsarekeptforbackwardscompati bilitytopreviousmmccardsystems,wheremoretha none enandwasallowedonthebus. card state operation mode bus mode bootstate bootmode pushpull waitirqstate interruptmode opendrain rev 1.0 / sep. 2009 51 e-nand 0x00000000 maximum boot partition size 0x00000000 maximum boot partition size boot area partition 1 boot area partition 2 user area 0x00000000 4.1 boot operation mode inbootoperationmode,themaster(enandhost)ca nreadbootdatafromtheslave(mmcdevice)bykeep ingcmd linelowafterpoweron,orsendingcmd0withargum ent+0xfffffffa(optionalforslave),beforeissuin gcmd1.the datacanbereadfromeitherbootareaoruserarea dependingonregistersetting. 4.1.1 boot partition therearetwopartitionregions.theminimumsizeo feachbootpartitionis128kb.bootpartitionsize iscalculatedas follows: maximumbootpartitionsize=128kbytexboot_size _mult boot_size_mult:thevalueinextendedcsdregister byte[226] thebootpartitionsareseparatedfromtheuserare aasshowninfigure41. figure 4-1: memory partition slavehasbootconfigurationinextendedcsdregist erbyte[179].themastercanchoosetheconfigurat ionbysetting theregisterusingcmd6(switch).slavealsocanbe configuredtobootfromtheuserareabysettingt he boot_partition_enablebitsintheext_csdregister ,byte[179]to111b rev 1.0 / sep. 2009 52 e-nand clkcmd dat[0] s 010 e s e 512bytes +crc s 512bytes +crc e cmd1 resp cmd2 resp cmd3 resp 50ms max 1 sec max boot terminated min & clocks = 48 clocks = 56 clocks required fromcmd signal high to next mmc conmand. 4.1.2 boot operation ifthecmdlineisheldlowfor74clockcyclesand moreafterpowerupbeforethefirstcommandisis sued,theslave recognizesthatbootmodeisbeinginitiatedandst artspreparingbootdatainternally.thepartition fromwhichthe masterwillreadthebootdatacanbeselectedina dvanceusingext_csdbyte179,bits[5:3].thedata sizethatthe mastercanreadduringbootoperationcanbecalcul atedas128kbboot_size_mult(ext_csdbyte226). within 1secondafterthecmdlinegoeslow,theslavesta rtstosendthefirstbootdatatothemasteronth edatline(s). themastermustkeepthecmdlinelowtoreadallo fthebootdata.themastermustusepushpullmode untilboot operationisterminated. themastercanusethebackwardcompatibleinterfac etimingshownintable37. themastercanchoosetoreceivebootacknowledgef romtheslavebysetting1inext_csdregister,b yte179,bit 6,sothatthemastercanrecognizethattheslave isoperatinginbootmode. ifbootacknowledgeisenabled,theslavehastose ndacknowledgepattern010tothemasterwithin5 0msafterthe cmdlinegoeslow.ifbootacknowledgeisdisabled, theslavewillnotsendoutacknowledgepattern0 10. themastercanterminatebootmodewiththecmdlin ehigh.ifthemasterpullsthecmdlinehighinth emiddleof datatransfer,theslavehastoterminatethedata transferoracknowledgepatternwithinnstclockcy cles(onedata cycleandendbitcycle).ifthemasterterminates bootmodebetweenconsecutiveblocks,theslavemus treleasethe dataline(s)withinnstclockcycles. bootoperationwillbeterminatedwhenallcontents oftheenabledbootdataaresenttothemaster.a fterbootoper ationisexecuted,theslaveshallbereadyforcmd 1operationandthemasterneedstostartanormal mmcinitializa tionsequencebysendingcmd1. figure 4-2: e-nand state diagram (boot mode) rev 1.0 / sep. 2009 53 e-nand detailedtimingsareshownin section4.17 .min8clocks+48clocks=56clocksrequiredfro mcmdsignalhighto nextmmccommand. ifthecmdlineisheldlowforlessthan74clock cyclesafterpowerupbeforecmd1isissued,orthe mastersends anynormalmmccommandotherthancmd1andcmd0wit hargument0xfffffffa(ifthedevicesupportsalter nate bootoperation)beforeinitiatingbootmode,thesl avedoesnotrespondandwillbelockedoutofboot modeuntilthe nextpowercycleandenteridlestate. whenboot_partition_enablebitsaresetandmaster sendcmd1(send_op_cond),slavemustentercard identificationmodeandrespondtothecommand. iftheslavedoesnotsupportbootoperationmode, whichiscompliantwithv4.2orbefore,or boot_partition_enablebitiscleared,slaveautomat icallyenteridlestateafterpoweron. 4.1.3 alternative boot operation (device optional) thisbootfunctionisoptionalforthedevice.ifb it0intheextendedcsdbyte[228]issetto1,t hedevicesupports thealternativebootoperation. afterpowerup,ifthehostissuescmd0withthear gumentof0xfffffffaafter74clockcycles,before cmd1is issuedorthecmdlinegoeslow,theslaverecogniz esthatbootmodeisbeinginitiatedandstartspre paringbootdata internally.thepartitionfromwhichthemasterwil lreadthebootdatacanbeselectedinadvanceusi ngext_csd byte179,bits[5:3].thedatasizethatthemaster canreadduringbootoperationcanbecalculateda s128kb boot_size_mult(ext_csdbyte226.within1seconda ftercmd0withtheargumentof0xfffffffaisissued ,the slavestartstosendthefirstbootdatatothemas teronthedatline(s).themastermustusepushpu llmodeuntil bootoperationisterminated.themastercanuseth ebackwardcompatibleinterfacetimingshowninr2w _factor tableonpage31. themastercanchoosetoreceivebootacknowledgef romtheslavebysetting1inext_csdregister,b yte179,bit 6,sothatthemastercanrecognizethattheslave isoperatinginbootmode.ifbootacknowledgeise nabled,the slavehastosendtheacknowledgepattern010to themasterwithin50msafterthecmd0withtheargu mentof 0xfffffffaisreceived.ifbootacknowledgeisdisa bled,theslavewillnotsendoutacknowledgepatte rn010.the mastercanterminatebootmodebyissuingcmd0(res et).ifthemasterissuescmd0(reset)inthemiddl eofadata transfer,theslavehastoterminatethedatatrans feroracknowledgepatternwithinnstclockcycles (onedatacycle andendbitcycle).ifthemasterterminatesbootm odebetweenconsecutiveblocks,theslavemustrele asethedata line(s)withinnstclockcycles. bootoperationwillbeterminatedwhenallcontents oftheenabledbootdataaresenttothemaster.a fterbootopera tionisexecuted,theslaveshallbereadyforcmd1 operationandthemasterneedstostartanormalm mcinitialization sequencebysendingcmd1.sequencebysendingcmd1. rev 1.0 / sep. 2009 54 e-nand clkcmd dat[0] s 010 e s e 512bytes +crc s 512bytes +crc e cmd1 resp cmd2 resp cmd3 resp 50ms max 1 sec max min 74clocks required after power is stable to start boot conmand. cmd0/reset cmd 1 detailedtimingsareshownin section7.17.1. . ifthecmdlineisheldlowforlessthan74clock cyclesafterpowerupbeforecmd1isissued,orthe mastersends anynormalmmccommandotherthancmd1andcmd0wit hargument0xfffffffa(ifthedevicesupportsalter nate bootoperation)beforeinitiatingbootmode,thesl avedoesnotrespondandwillbelockedoutofboot modeuntilthe nextpowercycleandenteridlestate. whenboot_partition_enablebitsaresetandmaster sendcmd1(send_op_cond),slavemustentercard identificationmodeandrespondtothecommand.if theslavedoesnotsupportbootoperationmode,whi chiscompliant withv4.2orbefore,orboot_partition_enablebiti scleared,slaveautomaticallyenteridlestateaft erpoweron. note1.cmd0withargument0xfffffffa figure 4-3: e-nand state diagram (alternative boot mode) 0 rev 1.0 / sep. 2009 55 e-nand figure 4-4: e-nand state diagram (boot mode) rev 1.0 / sep. 2009 56 e-nand 4.1.4 access to boot partition afterputtingaslaveintotransferstate,masters endscmd6(switch)tosettheboot_partition_access bitsin theext_csdregister,byte[179].afterthat,maste rcanusenormalmmccommandstoaccessabootpart ition. mastercanprogrambootdataondatline(s)usingc md24(write_block)orcmd25(write_multiple_block) withslavesupportedaddressingmodei.e.byteaddr essingorsectoraddressing.ifthemasterusescmd 25 (write_multiple_block)andthewritespastthesele ctedpartitionboundary,theslavewillreportan address_out_of_rangeerror.datathatiswithint hepartitionboundarywillbewrittentotheselect edbootpar tition. mastercanreadbootdataondatline(s)usingcmd1 7(read_single_block)orcmd18(read_multiple_block ) withslavesupportedaddressingmodei.e.byteaddr essingorsectoraddressing.ifthemasterpageuse scmd18 (read_multiple_block)andthenreadspasttheselec tedpartitionboundary,theslavewillreportan address_out_of_rangeerror.afterfinishingdata accesstothebootpartition,theboot_partition_ac cess bitsshouldbecleared.then,nonvolatileboot_par tition_enablebitsintheext_csdregistershouldb esetto indicatewhichpartitionisenabledforbooting.th iswillpermittheslavetoreaddatafromtheboot partitionduring bootoperation. masteralsocanaccessuserareabyusingnormalco mmandbyclearingboot_partition_accessbitsinthe ext_csdregister,byte[179]to000b. ifuserareaislockedandenabledforboot,dataw illnotbesentouttomasterduringbootoperation mode. however,iftheuserareaislockedandoneofthe twopartitionsisenabled,datawillbesentoutto themasterduring bootoperationmode. 4.1.5 boot bus width configuration duringbootoperation,buswidthcanbeconfigured bynonvolatileconfigurationbitsintheextendcs dregister byte[177]bit[0:1].bit2inregisterbyte[177]dete rminesiftheslavereturnstox1buswidthaftera bootoperationor ifitremainsintheconfiguredbootbuswidthduri ngnormaloperation.ifbootoperationisnotexecu ted,theslave willinitializeinnormalx1buswidthregardlesso ftheregistersetting. rev 1.0 / sep. 2009 57 e-nand 4.2 e-nand identification mode whileinenandidentificationmodethehostresets theenand,validatesoperationvoltagerange,ide ntifiesthee nandandassignsarelativecardaddress(rca)tot heenandonthebus.alldatacommunicationinthe enand identificationmodeusesthecommandline(cmd)onl y. 4.2.1 card reset afterpoweronbythehost,theenand(evenifit hasbeenininactivestate)isinmodeandinidle state. commandgo_idle_state(cmd0)isthesoftwarereset commandandputstheenandintoidlestate. afterpoweron,orcmd0,theenandoutputbusdriv ersareinhighimpedancestateandtheenandisi nitialized withadefaultrelativeenandaddress(?0x0001)a ndwithadefaultdriverstageregistersetting(lo westspeed, highestdrivingcurrentcapability).thehostclock sthebusattheidentificationclockratefod(see chapter3.3.10). cmd0isvalidinallstates,withtheexceptionof inactivestate.whileininactivestatetheenand doesnotaccept cmd0. 4.2.2 operating voltage range validation enandshallbeabletoestablishcommunicationwit hthehost,aswellasperformtheactualenandfu nction(e.g. accessingmemory),usinganyoperatingvoltagewith inthevoltagerangespecifiedinthisstandard,fo rthegivene nandtype(seechapter3.3.5). thesend_op_cond(cmd1)commandisdesignedtoprov ideenandhostswithamechanismtoidentifyandr eject enandwhichdonotmatchthevccqrangedesiredby thehost.thisisaccomplishedbythehostsending the requiredvccqvoltagewindowastheoperandofthis command(seechapter3.4.1).iftheenandcannot perform datatransferinthespecifiedrangeitmustdiscar ditselffromfurtherbusoperationsandgointoin activestate.other wise, thecardshallrespondsendingbackitsvccqrange. forthis,thelevelsintheocrregistershallbe defined accordingly(seechapter3.4). rev 1.0 / sep. 2009 58 e-nand cmd1 idle state (idle) idle state from all states except (ina) state (ina) identification ready state (ready) e-nand-identification made data-transfer mode stand-by state (stby) wait-irq state interrupt mode data-transfer mode host omitted voltage range e-nand is busy or power on e-nand looses bus e-nand wins bus e-nand with non compatible voltage range (irq) from all states indata-transfer-mode state (ident) cmd0 cmd15 cmd2 cmd3 cmd40 any start bit detected on the bus figure 4-5 : e-nand state diagram (e-nand identific ation mode) rev 1.0 / sep. 2009 59 e-nand thebusybitinthecmd1responsecanbeusedbya enandtotellthehostthatitisstillworkingon itspowerup/ resetprocedure(e.g.downloadingtheregisterinfo rmationfrommemoryfield)andisnotreadyyetfor communication. inthiscasethehostmustrepeatcmd1untilthebu sybitiscleared. duringtheinitializationprocedure,thehostisno tallowedtochangetheoperatingvoltagerange.su chchangesshall beignoredbytheenand.ifthereisarealchange intheoperatingconditions,thehostmustresett heenand(using cmd0)andrestarttheinitializationprocedure.how ever,foraccessingenandalreadyininactivestat e,ahardreset mustbedonebyswitchingthepowersupplyoffand backon. thecommandgo_inactive_state(cmd15)canbeusedt osendanaddressedenandintotheinactivestate. this commandisusedwhenthehostexplicitlywantstod eactivateaenand(e.g.hostischangingvccqinto arange whichisknowntobenotsupportedbythisenand). thecommandcmd1shallbeimplementedbyallcards defined bythisstandard. 4.2.3 e-nand identification process thefollowingexplanationreferstoaenandworkin ginamulticardenvironment,asdefinedinversio nsofthisstandard previoustov4.0,anditismaintainedforbackward scompatibilitytothosesystems. thehoststartstheenandidentificationprocessi nopendrainmodewiththeidentificationclockrat efod(seechapter 3.3.10).theopendraindriverstagesonthecmdli neallowparallelenandoperationduringenandid entification. afterthebusisactivated,thehostwillrequestt heenandtosenditsvalidoperationconditions(c md1).the responsetocmd1isthewiredandoperationonth econditionrestrictionsofallenandsinthesyst em.incompatible enandsaresentintoinactivestate.thehostthen issuesthebroadcastcommandall_send_cid(cmd2), askingall enandsforitsuniquecardidentification(cid)nu mber.allunidentifiedenands(i.e.thosewhichar einreadystate) simultaneouslystartsendingtheircidnumbersseri ally,whilebitwisemonitoringtheiroutgoingbits tream.those enands,whoseoutgoingcidbitsdonotmatchthec orrespondingbitsonthecommandlineinanyoneof thebit periods,stopsendingtheircidimmediatelyandmus twaitforthenextidentificationcycle(remaining intheready state).sincecidnumbersareuniqueforeachenan d,thereshouldbeonlyoneenandwhichsuccessful lysendsits fullcidnumbertothehost.thisenandthengoes intoidentificationstate.thereafter,thehostiss uescmd3 (set_relative_addr)toassigntothiscardarelati vecardaddress(rca),whichisshorterthancidan dwhichwill beusedtoaddresstheenandinthefuturedatatr ansfermode(typicallywithahigherclockratetha nfod).oncethe rcaisreceivedtheenandstatechangestothesta ndbystate,andtheenanddoesnotreacttofurth eridentification cycles.furthermore,theenandswitchesitsoutput driversfromopendraintopushpull. thehostrepeatstheidentificationprocess,i.e.t hecycleswithcmd2andcmd3aslongasitreceives aresponse(cid) toitsidentificationcommand(cmd2).ifnomoree nandrespondstothiscommand,allenandshavebee nidentified. thetimeoutconditiontorecognizecompletionofth eidentificationprocessistheabsenceofastart bitformore thannidclockcyclesaftersendingcmd2(seetimin gvaluesinchapter4.13). rev 1.0 / sep. 2009 60 e-nand 4.2.4 intrrupt mode theinterruptmodeonthemultimediacardsystemena blesthemaster(multimediacardhost)tograntthe transmission allowancetotheslaves(card)simultaneously.this modereducesthepollingloadforthehostandhen ce,thepower consumptionofthesystem,whilemaintainingadequa teresponsivenessofthehosttoacardrequestfor service.supporting multimediacardinterruptmodeisanoption,bothfo rthehostandthecard. thesystembehaviorduringtheinterruptmodeisde scribedinthestatediagramin figure46 . ? thehostmustensurethatthecardisinstandby statebeforeissuingthego_irq_state(cmd40)comma nd. whilewaitingforaninterruptresponsefromtheca rd,thehostmustkeeptheclocksignalactive.clo ckratemaybe changedaccordingtotherequiredresponsetime. ? thehostsetsthecardintointerruptmodeusingg o_irq_state(cmd40)command. ? acardinwaitirqstateiswaitingforaninterna linterrupttriggerevent.oncetheeventoccurs,t hecardstartsto senditsresponsetothehost.thisresponseissen tintheopendrainmode. ? whilewaitingfortheinternalinterruptevent,th ecardisalsowaitingforastartbitonthecomma ndline.upon detectionofastartbit,thecardwillabortinter ruptmodeandswitchtothestandbystate. ? regardlessofwinningorlosingbuscontrolduring cmd40response,thecardsswitchestostandbysta te(as opposedtocmd2). ? aftertheinterruptresponsewasreceivedbytheh ost,thehostreturnstothestandarddatacommunic ationprocedure. rev 1.0 / sep. 2009 61 e-nand 4.3 data transfer mode whentheenandisinstandbystate,communication overthecmdanddatlineswillbeperformedinpu shpull mode.untilthecontentsofthecsdregisteriskno wnbythehost,thefppclockratemustremainatf od(seechapter 3.3.10).thehostissuessend_csd(cmd9)toobtain thecardspecificdata(csdregister),e.g.blockl ength, enandstoragecapacity,maximumclockrate,etc. figure 4-6 : e-nand state diagram (data transfer mo de) thebroadcastcommandset_dsr(cmd4)configuresthe driverstagesoftheenand.itprogramsitsdsrr egister correspondingtotheapplicationbuslayout(length )andthedatatransferfrequency.theclockratei salsoswitched fromfodtofppatthatpoint. cmd7isusedtoselecttheenandandputitintot hetransferstate.iftheenandwaspreviouslysel ectedandwas intransferstateitsconnectionwiththehostisr eleasedanditwillmovebacktothestandbystate .whencmd7is issuedwiththereservedrelativeenandaddress0 x0000,theenandisputbacktostandbystate.a fterthe enandisassignedanrcaitwillnotrespondtoid entificationcommands(cmd1,cmd2,cmd3,seechapte r4.2.3). rev 1.0 / sep. 2009 62 e-nand alldatacommunicationinthedatatransfermodeis pointtopointbetweenthehostandtheselectede nand(using addressedcommands).alladdressedcommandsgetack nowledgedbyaresponseonthecmdline. therelationshipbetweenthevariousdatatransfer modesissummarizedbelow(seefigure46): alldatareadcommandscanbeabortedanytimebyt hestopcommand(cmd12).thedatatransferwillter minate andtheenandwillreturntothetransfersta te.thereadcommandsare:blockread(cmd17),mult ipleblock read(cmd18)andsendwriteprotect(cmd30). alldatawritecommandscanbeabortedanytimeby thestopcommand(cmd12).thewritecommandsmustb e stoppedpriortodeselectingtheenandbycmd 7.thewritecommandsare:blockwrite(cmd24andc md25), writecid(cmd26),andwritecsd(cmd27). assoonasthedatatransferiscompleted,theen andwillexitthedatawritestateandmoveeither tothe programmingstate(transferissuccessful)or transferstate(transferfailed). ifablockwriteoperationisstoppedandthebloc klengthandcrcofthelastblockarevalid,thed atawillbe programmed. theenandmayprovidebufferingforstreamandblo ckwrite.thismeansthatthenextblockcanbesen ttothe enandwhilethepreviousisbeingprogrammed . ifallwritebuffersarefull,andaslongasthe cardisinprogrammingstate(seeenandstatediag ramfigure2), thedat0linewillbekeptlow. thereisnobufferingoptionforwritecsd,writec id,writeprotectionanderase.thismeansthatwhi lethee nandisbusyservicinganyoneofthesecomman ds,nootherdatatransfercommandswillbeaccepte d.dat0line willbekeptlowaslongastheenandisbusy andintheprogrammingstate. parametersetcommandsarenotallowedwhileenan disprogramming. parametersetcommandsare:setblocklength (cmd16),anderasegroupselection(cmd3536). readcommandsarenotallowedwhileenandisprogr amming. movinganotherenandfromstandbytotransfersta te(usingcmd7)willnotterminateaprogramming opeation.theenandwillswitchtothediscon nectstateandwillreleasethedat0line. acardcanbereselectedwhileinthedisconnectst ate,usingcmd7.inthiscasetheenandwillmove tothe programmingstateandreactivatethebusyindicatio n. resettingaenand(usingcmd0orcmd15)willtermi nateanypendingoractiveprogrammingoperation.t his maydestroythedatacontentsontheenand.i tisuptothehostsresponsibilitytopreventthis . priortoexecutingthebustestingprocedure(cmd1 9,cmd14),itisrecommendedtosetuptheclockfr equency usedfordatatransfer.thiswaythebustest givesatrueresult,whichmightnotbethecasei fthebustesting procedureisperformedwithlowerclockfrequencyt hanthedatatransferfrequency. inthefollowingformatdefinitions,alluppercase flagsandparametersaredefinedinthecsd(chapt er3.4.3),and theotherstatusflagsintheenandstatus(chapte r4.11). rev 1.0 / sep. 2009 63 e-nand 4.3.1 command sets and extended settings theenandoperatesinagivencommandset,bydefa ult,afterapowercycleorresetbycmd0,itisth emmccard standardcommandset,usingasingledataline,dat 0.thehostcanchangetheactivecommandsetbyis suingthe switchcommand(cmd6)withthecommandsetaccess modeselected. thesupportedcommandsets,aswellasthecurrentl yselectedcommandset,aredefinedintheext_csd register. theext_csdregisterisdividedintwosegments,a propertiessegmentandamodessegment.thepropert iessegment containsinformationabouttheenandcapabilities. themodessegmentreflectsthecurrentselectedmo desof theenand. thehostreadstheext_csdregisterbyissuingthe send_ext_csdcommand.thecardsendstheext_csdre gister asablockofdata,512byteslong.anyreserved,o rwriteonlyfield,readsas0. thehostcanwritethemodessegmentoftheext_csd registerbyissuingaswitchcommandandsettingo neofthe accessmodes.allthreemodesaccessandmodifyone oftheext_csdbytes,thebytepointedbytheinde xfield 1 access bits access name operation 00 commandset thecommandsetischangedaccordingt othecmdsetfieldoftheargument 01 setbits thebitsinthepointedbyteareset,acc ordingtothe1bitsinthevaluefield. 10 clearbits thebitsinthepointedbytearecleare d,accordingtothe1bitsinthevaluefield. 11 writebyte thevaluefieldiswrittenintothepoi ntedbyte. table 4-1 : ext_csd access modes theswitchcommandcanbeusedeithertowritethe ext_csdregisterortochangethecommandset.ift he switchcommandisusedtochangethecommandset,t heindexandvaluefieldareignored,andtheext_c sdisnot written.iftheswitchcommandisusedtowritethe ext_csdregister,thecmdsetfieldisignored,an dthecom mandsetremainsunchanged. theswitchcommandresponseisoftyper1b,therefo re,thehostshouldreadtheenandstatus,using send_statuscommand,afterthebusysignalisdeas serted,tochecktheresultoftheswitchoperation . 4. 3 .2 high speed mode selection afterthehostverifiesthattheenandcomplieswi thversion4.0,orhigher,ofthisstandard,ithas toenablethehigh speedmodetimingintheenand,beforechangingth eclockfrequencytoafrequencyhigherthan20mhz. afterpoweron,orsoftwarereset,theinterfaceti mingoftheenandissetasspecifiedintable37 ,chapter5.for thehosttochangetoahigherclockfrequency,it hastoenablethehighspeedinterfacetiming.the hostusesthe switchcommandtowrite0x01tothehs_timingbyte, inthemodessegmentoftheext_csdregister. thevalidvaluesforthisregisteraredefinedin hs_timing,inpage37.ifthehosttriestowrite aninvalidvalue,the hs_timingbyteisnotchanged,thehighspeedinter facetimingisnotenabled,andtheswitch_errorbi tisset. rev 1.0 / sep. 2009 64 e-nand 4. 3 .3 power class selection afterthehostverifiesthattheenandcomplieswi thversion4.0,orhigher,ofthisstandard,itmay changethepower classoftheenand. afterpoweron,orsoftwarereset,theenandpower classisclass0,whichisthedefault,minimumcu rrentconsump tionclassforthecardtype,eitherhighvoltagee nand.thepwr_cl_ff_vvvbytes,intheext_csdregi ster,reflect thepowerconsumptionlevelsoftheenand,fora4 bitsbus,an8bitbus,atthesupportedclockfre quencies (26mhzor52mhz). thehostreadsthisinformation,usingthesend_ext _csdcommand,anddeterminesifitwillallowthee nandto useahigherpowerclass.ifapowerclasschangei sneeded,thehostusestheswitchcommandtowrite thepow er_classbyte,inthemodessegmentoftheext_csd register. thevalidvaluesforthisregisteraredefinedin pwr_cl_ff_vvv,inpage84ifthehosttriestowri teaninvalidvalue, thepower_classbyteisnotchangedandtheswitch_ errorbitisset. 4. 3 .4 bus testing procedure byissuingcommandscmd19andcmd14thehostcande tectthefunctionalpinsonthebus.inafirstste p,thehost sendscmd19totheenand,followedbyaspecificd atapatternoneachselecteddatalines.thedatap atterntobe sentperdatalineisdefinedinthetablebelow.a sasecondstep,thehostsendscmd14torequestth eenandto sendbackthereverseddatapattern.withthedata patternsentbythehostandwiththereversedpatt ernsentback bytheenand,thefunctionalpinsonthebuscanb edetected. startbit datapattern endbit 0 10xxxx...xx 1 theenandignoresallbutthetwofirstbitsofth edatapattern.therefore,theenandbuffersizei snotlimitingthe maximumlengthofthedatapattern.theminimumlen gthofthedatapatternistwobytes,ofwhichthe firsttwobits ofeachdatalinearesentback,bytheenand,rev ersed.thedatapatternsentbythehostmayoption allyincludea crc16checksum,whichisignoredbytheenand. theenanddetectsthestartbitondat0andsynchr onizesaccordinglythereadingofallitsdatainpu ts. thehostignoresallbutthetwofirstbitsofthe reversedatapattern.thelengthofthereversedat apatterniseight bytesandisalwayssentusingalltheenandsdat lines(seetablethroughtable).thereversedata patternsentby theenandmayoptionallyincludeacrc16checksum, whichisignoredbythehost. theenandhaspullupsinalldatainputs.incase swherethecardisconnectedtoonly1bitoronly 4bithsmmcsys tem,theinputvalueoftheupperbits(e.g.dat1d at7ordat4dat7)aredetectedaslogical1byth eenand. rev 1.0 / sep. 2009 65 e-nand data line data pattern sent by the host reversed pattern sent by the e-nand notes dat0 0,10xxxxxxxxxx,[crc16],1 0,01000000,[crc16],1 sta rtbitdefinesbeginningofpattern dat1 0,01000000,[crc16],1 nodatapatternsent dat2 0,01000000,[crc16],1 nodatapatternsent dat3 0,01000000,[crc16],1 nodatapatternsent dat4 0,01000000,[crc16],1 nodatapatternsent dat5 0,01000000,[crc16],1 nodatapatternsent dat6 0,01000000,[crc16],1 nodatapatternsent dat7 0,01000000,[crc16],1 nodatapatternsent table 4-2 : 1-bit bus testing pattern data line data pattern sent by the host reversed pattern sent by the e-nand notes dat0 0,10xxxxxxxxxx,[crc16],1 0,01000000,[crc16],1 sta rtbitdefinesbeginningofpattern dat1 0,10xxxxxxxxxx,[crc16],1 0,01000000,[crc16],1 dat2 0,10xxxxxxxxxx,[crc16],1 0,01000000,[crc16],1 dat3 0,10xxxxxxxxxx,[crc16],1 0,01000000,[crc16],1 dat4 0,01000000,[crc16],1 nodatapatternsent dat5 0,01000000,[crc16],1 nodatapatternsent dat6 0,01000000,[crc16],1 nodatapatternsent dat7 0,01000000,[crc16],1 nodatapatternsent table 4-3: 4-bit bus testing pattern rev 1.0 / sep. 2009 66 e-nand data line data pattern sent by the host reversed pattern sent by the e-nand notes dat0 0,10xxxxxxxxxx,[crc16],1 0,01000000,[crc16],1 sta rtbitdefinesbeginningofpattern dat1 0,10xxxxxxxxxx,[crc16],1 0,01000000,[crc16],1 dat2 0,10xxxxxxxxxx,[crc16],1 0,01000000,[crc16],1 dat3 0,10xxxxxxxxxx,[crc16],1 0,01000000,[crc16],1 dat4 0,10xxxxxxxxxx,[crc16],1 0,01000000,[crc16],1 dat5 0,10xxxxxxxxxx,[crc16],1 0,01000000,[crc16],1 dat6 0,10xxxxxxxxxx,[crc16],1 0,01000000,[crc16],1 dat7 0,10xxxxxxxxxx,[crc16],1 0,01000000,[crc16],1 table 4-4 : 8-bit bus testing pattern rev 1.0 / sep. 2009 67 e-nand 4. 3 .5 bus width selection afterthehosthasverifiedthefunctionalpinson thebusitshouldchangethebuswidthconfiguratio naccordingly, usingtheswitchcommand. thebuswidthconfigurationischangedbywritingt othebus_widthbyteinthemodessegmentoftheex t_csd register(usingtheswitchcommandtodoso).after poweron,orsoftwarereset,thecontentsoftheb us_width byteis0x00. thevalidvaluesforthisregisteraredefinedin bus_width,inpage45.ifthehosttriestowrite aninvalidvalue, thebus_widthbyteisnotchangedandtheswitch_er rorbitisset.thisregisteriswriteonly. 4. 3 .6 data read thedat0dat7buslinelevelsarehighwhennodata istransmitted.atransmitteddatablockconsists ofastartbit (low),oneachdatline,followedbyacontinuousd atastream.thedatastreamcontainsthepayloadda ta(and errorcorrectionbitsifanoffcardeccisused). thedatastreamendswithanendbit(high),oneac hdatline(see figure412figure414).thedatatransmissioni ssynchronoustotheclocksignal. thepayloadforblockorienteddatatransferispro tectedbyacrcchecksum,oneachdatline(seech apter6.4). block read blockreadissimilartostreamread,excepttheba sicunitofdatatransferisablockwhosemaximum sizeisdefined inthecsd(read_bl_len).ifread_bl_partialisset ,smallerblockswhosestartingandendingaddress are entirelycontained withinonephysicalblock(asdefinedbyread_bl_le n)mayalsobetransmitted.unlikestreamread,ac rcis appendedtotheendofeachblockensuringdatatra nsferintegrity.cmd17(read_single_block)initiate sablock readandaftercompletingthetransfer,thecardre turnstothe transferstate . cmd18(read_multiple_block)startsatransferofse veralconsecutiveblocks.twotypesofmultipleblo ckread transactionsaredefined(thehostcanuseeithero neatanytime): openendedmultipleblockread thenumberofblocksforthereadmultipleblo ckoperationisnotdefined.theenandwillcontin uouslytransfer datablocksuntilastoptransmissioncommandi sreceived. multipleblockreadwithpredefinedblockcount theenandwilltransfertherequestednumber ofdatablocks,terminatethetransactionandretur nto transfer state.stopcommandisnotrequiredattheend ofthistypeofmultipleblockread,unlesstermin atedwithan error.inordertostartamultipleblockread withpredefinedblockcountthehostmustusethe set_block_countcommand(cmd23)immediatelypr ecedingtheread_multiple_block(cmd18) command.otherwisetheenandwillstartano penendedmultipleblockreadwhichcanbestopped usingthe stop_transmisioncommand. rev 1.0 / sep. 2009 68 e-nand thehostcanabortreadingatanytime,withinamu ltipleblockoperation,regardlessoftheitstype. transactionabortis donebysendingthestoptransmissioncommand. ifeitheroneofthefollowingconditionsoccur,th eenandwillrejectthecommand,remainin tran stateandrespondwith therespectiveerrorbitset. thehostprovidesanoutofrangeaddressasanarg umenttoeithercmd17orcmd18. address_out_of_rangeisset. thecurrentlydefinedblocklengthisillegalfora readoperation.block_len_errorisset. theaddress/blocklengthcombinationpositionsthe firstdatablockmisalignedtothecardphysicalbl ocks. address_misalignisset. iftheenanddetectsanerror(e.g.outofrange, addressmisalignment,internalerror,etc.)during amultipleblock readoperation(bothtypes)itwillstopdatatrans missionandremaininthedatastate.thehostmust thenabortthe operationbysendingthestoptransmissioncommand. thereaderrorisreportedintheresponsetothe stoptransmission command. ifthehostsendsastoptransmissioncommandafter theenandtransmitsthelastblockofamultiple blockoperation withapredefinednumberofblocks,itisregarded asanillegalcommand,sincetheenandisnolong erindatastate. ifthehostusespartialblockswhoseaccumulatedl engthisnotblockaligned,andblockmisalignment isnotallowed, theenandshalldetectablockmisalignmenterror conditionduringthetransmissionofthefirstmisa lignedblockand thecontentofthefurthertransferredbitsisunde fined.asthehostsendscmd12thecardwillrespon dwiththe address_misalignbitsetandreturntotranstate. ifthehostsetstheargumentoftheset_block_coun tcommand(cmd23)toall0s,thenthecommandisac cepted; however,asubsequentreadwillfollowtheopenend edmultipleblockreadprotocol(stop_transmission command cmd12isrequired). ifahosthadsentacmd16forpasswordsettingto ahigherthan2gbofdensityofcard,thenthishos tmustresend cmd16beforereaddatatransfer;otherwise,thecar dwillresponseablk_len_errorandstayintranss tatewithout datatransfersincethedatablock(exceptinpassw ordapplication)transferissectorunit(512b).s ameerror appliestoupto2gbofdensityofcardsincasepa rtialreadaccessarenotsupported. rev 1.0 / sep. 2009 69 e-nand 4. 3 .7 data write thedatatransferformatofwriteoperationissimi lartothedataread.forblockorientedwritedata transfer,thecrc checkbitsareaddedtoeachdatablock.theenand performsacrcparitycheck(seechapter6.4)for eachreceived datablockpriortothewriteoperation.bythisme chanism,writingoferroneouslytransferreddataca nbeprevented. block write duringblockwrite(cmd2427)oneormoreblocks ofdataaretransferredfromthehosttotheenand withacrc appendedtotheendofeachblockbythehost.ae nandsupportingblockwriteshallalwaysbeableto acceptablock ofdatadefinedbywrite_bl_len.ifthecrcfails, theenandshallindicatethefailureonthedat0l ine(seebelow); thetransferreddatawillbediscardedandnotwrit ten,andallfurthertransmittedblocks(inmultipl eblockwritemode) willbeignored. cmd25(write_multiple_block)startsatransferofs everalconsecutiveblocks.twotypesofmultiplebl ockwrite transactions,identicaltothemultipleblockread, aredefined(thehostcanuseeitheroneatanyti me): openendedmultipleblockwrite thenumberofblocksforthewritemultiplebl ockoperationisnotdefined.theenandwillconti nuouslyacceptand programdatablocksuntilastoptransmission commandisreceived. multipleblockwritewithpredefinedblockcount theenandwillaccepttherequestednumberof datablocks,terminatethetransactionandreturn to transferstate. stopcommandisnotrequiredattheendofthi stypeofmultipleblockwrite,unlessterminatedw ithanerror.in ordertostartamultipleblockwritewithpre definedblockcountthehostmustusetheset_bloc k_countcom mand(cmd23)immediatelyprecedingthewrite_m ultiple_block(cmd25)command.otherwisetheenand willstartanopenendedmultipleblockwrite whichcanbestoppedusingthestop_transmisionco mmand. reliablewrite:multipleblockwritewithpredefin edblockcountandreliablewriteparameters. thistransactionissimilartothebasicpredefine dmultipleblockwrite(definedinpreviousbullet) withthefollowing exceptions.theolddatapointedtobyalogicalad dressmustremainunchangedaslongasthenewdata writtento samelogicaladdresshasbeensuccessfullyprogramm ed.thisistoensurethatthetargetaddressupdat edbythereli able writetransactionnevercontainsundefineddata.da tamustremainvalidevenifasuddenpowerlossoc cursdur ing theprogramming.amaximumoftwodifferentsizeso freliablewritetransactionsaresupported:512ba ndthe reliablewritesectorcountparameterinext_csd(r el_wr_sec_c)multipliedby512b.thefunctionisac tivatedby settingthereliablewriterequestparameter(bit3 1)to1intheset_block_countcommand(cmd23)ar gument. thereliablewritesectorcountparameterinext_cs dindicatesthesupportedwritesectorcount.ther eliablewrite functionisonlypossibleunderthefollowingcondi tions:thelengthofthewriteoperationequalsthe supportedreliable writesizeor512b,andthereliablewriterequest isactive.otherwisethetransactionishandledas basicpredefined multipleblockcase.whenthelengthofthewriteo perationissetto0,theoperationisexecuteda sabasic, openended, multipleblockwritecase,evenwhenthereliablewr iterequestisactive. rev 1.0 / sep. 2009 70 e-nand thehostcanabortwritingatanytime,withinamu ltipleblockoperation,regardlessoftheitstype. transactionabort isdonebysendingthestoptransmissioncommand.i famultipleblockwritewithpredefinedblockcou ntisaborted, thedataintheremainingblocksisnotdefined. ifeitheroneofthefollowingconditionsoccur,th eenandwillrejectthecommand,remainintranst ateandrespond withtherespectiveerrorbitset. thehostprovidesanoutofrangeaddressasanarg umenttoeithercmd24orcmd25. address_out_of_rangeisset. thecurrentlydefinedblocklengthisillegalfora writeoperation.block_len_errorisset. theaddress/blocklengthcombinationpositionsthe firstdatablockmisalignedtotheenandphysical blocks. address_misalignisset. iftheenanddetectsanerror(e.g.writeprotect violation,outofrange,addressmisalignment,inte rnalerror,etc.) duringamultipleblockwriteoperation(bothtypes )itwillignoreanyfurtherincomingdatablocksa ndremaininthe receivestate. thehostmustthenaborttheoperationbysendingt hestoptransmissioncommand.thewriteerrorisre portedinthe responsetothestoptransmissioncommand. ifthehostsendsastoptransmissioncommandafter theenandreceivedthelastdatablockofamulti pleblockwrite withapredefinednumberofblocks,itisregarded asanillegalcommand,sincetheenandisnolong erindata state. ifthehostusespartialblockswhoseaccumulatedl engthisnotblockaligned,andblockmisalignment isnotallowed (csdparameterwrite_blk_misalignisnotset),the enandshalldetecttheblockmisalignmenterrordu ringthe receptionofthefirstmisalignedblock,abortthe writeoperation,andignoreallfurtherincomingda ta.asthehost sendscmd12,theenandwillrespondwiththeaddre ss_misalignbitsetandreturntotranstate. ifthehostsetstheargumentoftheset_block_coun tcommand(cmd23)toall0s,thenthecommandisac cepted; however,asubsequentwritewillfollowtheopenen dedmultipleblockwriteprotocol(stop_transmissio ncom mand cmd12isrequired). programmingofthecidandcsdregistersdoesnotr equireapreviousblocklengthsetting.thetransfe rreddatais alsocrcprotected.ifapartofthecsdorcidreg isterisstoredinrom,thenthisunchangeablepart mustmatchthe correspondingpartofthereceivebuffer.ifthism atchfails,thenthecardwillreportanerrorand notchangeanyreg ister contents. enandmayrequirelongandunpredictabletimesto writeablockofdata.afterreceivingablockofd ataandcomplet ing thecrccheck,theenandwillbeginwritingandho ldthedat0linelowifitswritebufferisfullan dunableto acceptnewdatafromanewwrite_blockcommand.the hostmaypollthestatusoftheenandwithasend _ statuscommand(cmd13)atanytime,andtheenand willrespondwithitsstatus.thestatusbitready_ for_ dataindicateswhethertheenandcanacceptnewda taorwhetherthewriteprocessisstillinprogres s).thehost maydeselecttheenandbyissuingcmd7whichwill displacetheenandintothedisconnectstateandr eleasethe dat0linewithoutinterruptingthewriteoperation. whenreselectingtheenand,itwillreactivatebus yindicationbypullingdat0tolowifprogramming isstillin progress andthewritebufferisunavailable. rev 1.0 / sep. 2009 71 e-nand 4. 3 .8 csd programming programmingofthecsdregisterdoesnotrequirea previousblocklengthsetting.aftersendingcmd27 andreceiving anr1response,thestartbit(=0)issent,themodi fiedcsdregister(=16bytes),crc16(=2bytes),and endbit(=1). thehostcanchangeonlytheleastsignificant16bi ts[15:0]ofthecsd.therestofthecsdregister contentmust matchtheenandcsdregister.iftheenanddetect sacontentinconsistencybetweentheoldandnewc sdregis ter,itwillnotreprogramthecsdinordertoensu revalidityofthecrcfieldinthecsdregister. bits[7:1]arethecrc7ofbits[127:8]ofthecsd register,whichshouldberecalculatedoncethereg isterchanges. aftercalculatingcrc7,thecrc16shouldalsobeca lculatedforallofthecsdregister[127:0]. rev 1.0 / sep. 2009 72 e-nand 4. 3 .9 erase enand,inadditiontotheimpliciteraseexecuted bytheenandaspartofthewriteoperation,provi desahost expliciterasefunction.theerasableunitofthee nandistheerasegroup;erasegroupismeasured inwriteblocks whicharethebasicwritableunitsoftheenand.t hesizeoftheerasegroupisaenandspecificpar ameterand definedinthecsd.thecontentofanexplicitlyer asedmemoryrangeshallbe0. thehostcaneraseacontiguousrangeoferasegrou ps.startingtheeraseprocessisathreestepsseq uence.firstthe hostdefinesthestartaddressoftherangeusingt heerase_group_start(cmd35)command,nextitdefin esthe lastaddressoftherangeusingtheerase_group_end (cmd36)commandandfinallyitstartstheerasepr ocessby issuingtheerase(cmd38)command.theaddressfiel dintheerasecommandsisanerasegroupaddressi nbyte units.theenandwillignorealllsbsbelowthee rasegroupsize,effectivelyroundingtheaddressd owntotheerase groupboundary. ifanerasecommand(eithercmd35,cmd36,cmd38)is receivedoutofthedefinederasesequence,thee nandshall settheerase_seq_errorbitinthestatusregister andresetthewholesequence. ifthehostprovidesanoutofrangeaddressasan argumenttocmd35orcmd36,theenandwillreject thecom mand,respondwiththeaddress_out_of_rangebitset andresetthewholeerasesequence. ifannonerasecommand(neitherofcmd35,cmd36, cmd38orcmd13)isreceived,theenandshallresp ondwith theerase_resetbitset,resettheerasesequencea ndexecutethelastcommand.commandsnotaddressed tothe selectedenanddonotaborttheerasesequence. iftheeraserangeincludeswriteprotectedblocks, theyshallbeleftintactandonlythenonprotect edblocksshallbe erased.thewp_erase_skipstatusbitinthestatus registershallbeset. asdescribedaboveforblockwrite,theenandwill indicatethataneraseisinprogressbyholdingd at0low.the actualerasetimemaybequitelong,andthehostm ayissuecmd7todeselecttheenand. 4. 3 .10 write protect management inordertoallowthehosttoprotectdataagainst eraseorwrite,theenandshallsupporttwolevels ofwriteprotect commands: theentireenandmaybewriteprotectedbysetting thepermanentortemporarywriteprotectbitsint hecsd. specificsegmentsoftheenandmaybewriteprotec ted.thesegmentsizeisdefinedinunitsofwp_grp _size erasegroupsasspecifiedinthecsd.theset _write_protcommandsetsthewriteprotectionofth eaddre writeprotectgroup,andtheclr_write_protc ommandclearsthewriteprotectionoftheaddressed writeprotectgroup. thesend_write_protcommandissimilartoasingle blockreadcommand.thecardshallsendadatabloc kcon taining32writeprotectionbits(representing32w riteprotectgroupsstartingatthespecifiedaddre ss)followedby16 crcbits. theaddressfieldinthewriteprotectcommandsis agroupaddressinbyteunits.thecardwillignore alllsbsbelow thegroupsize. ifthehostprovidesanoutofrangeaddressasan argumenttocmd28,cmd29orcmd30,thecardwillre jectthe command,respondwiththeaddress_out_of_rangebit setandremaininthetranstate. rev 1.0 / sep. 2009 73 e-nand 4. 3 .11 card lock/unlock operation thepasswordprotectionfeatureenablesthehostto locktheenandbyprovidingapassword,whichlat erwillbe usedforunlockingtheenand.thepasswordandits sizeiskeptinan128bitpwdand8bitpwd_lenr egisters, respectively.theseregistersarenonvolatilesot hatapowercyclewillnoterasethem. alockedenandrespondsto(andexecutes)allcomm andsinthebasiccommandclass(class0)andlo ckenand commandclass.thusthehostisallowedtoreset,i nitialize,select,queryforstatus,etc.,butnot toaccessdataonthe enand.ifthepasswordwaspreviouslyset(theval ueofpwd_lenisnot0)theenandwillbelocked automati callyafterpoweron. similartotheexistingcsdandcidregisterwrite commandsthelock/unlockcommandisavailableint ransferstate only. thismeansthatitdoesnotincludeanaddressargu mentandtheenandhastobeselectedbeforeusing it. theenandlock/unlockcommandhasthestructurean dbustransactiontypeofaregularsingleblockwr itecom mand.thetransferreddatablockincludesallther equiredinformationofthecommand(passwordsettin gmode,pwd itself,cardlock/unlocketc.).thefollowingtable describesthestructureofthecommanddatablock. byte# bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 reserved erase lock_unlock clr_pwd set_pwd 1 pwd_len 2 passworddata ... pwd_len+1 table 4-5 : lock card data structure erase: 1definesforcederaseoperation(allotherbitssh allbe0)andonlythecmdbyteissent. lock/unlock :1=lockstheenand.0=unlocktheenand(note thatitisvalidtosetthisbittogetherwith set_pwdbutiti snotallowedtosetittogetherwithclr_pwd). clr_pwd :1=clearspwd. set_pwd :1=setnewpasswordtopwd pwd_len :definesthefollowingpasswordlength(inbytes). validpasswordlengthare1to16bytes. pwd: thepassword(neworcurrentlyuseddependingonth ecommand). thedatablocksizeshallbedefinedbythehostbe foreitsendstheenandlock/unlockcommand.this willallowdif ferentpasswordsizes. thefollowingparagraphsdefinethevariouslock/un lockcommandsequences: setting the password selectthe7d(cmd7),ifnotpreviouslyselectedal ready rev 1.0 / sep. 2009 74 e-nand definetheblocklength(cmd16),givenbythe8bit enandlock/unlockmode,the8bitspasswordsize (inbytes),andthenumberofbyt esofthenewpassword.incasethatapassword replacement isdone, thentheblocksizeshallconside rthatbothpasswords,theoldandthenewone,are sentwiththe command. sendenandlock/unlockcommandwiththeappropriat edatablocksizeonthedatalineincluding16bit crc.thedatablockshallindicat ethemode(set_pwd),thelength(pwd_len)andthe password itself.incasethatapassword replacement isdone,thenthelengthvalue(pwd_len)shallincl udeboth passwords,theoldandthenewon e,andthepwdfieldshallincludetheoldpassword (currentlyused) followedbythenewpassword. incasethatapasswordreplacementisattemptedwi thpwd_lensettothelengthoftheoldpassword only,thelock_unlock_failederror bitissetinthestatusregisterandtheoldpass wordisnot changed. incasethatthesentoldpasswordisnotcorrect( notequalinsizeandcontent)thenlock_unlock_ failederrorbitwillbesetinth estatusregisterandtheoldpassworddoesnotcha nge. incasethatpwdmatchesthesen toldpasswordthenthegivennewpasswordandits sizewillbesaved inthepwdandpwd_lenfields,res pectively. notethatthepasswordlengthregister(pwd_len)in dicatesifapasswordiscurrentlyset.whenitequ als0thereis nopasswordset.ifthevalueofpwd_lenisnotequ altozerotheenandwilllockitselfafterpower up.itispossible tolocktheenandimmediatelyinthecurrentpower sessionbysettingthelock/unlockbit(whilesett ingthepass word)orsendingadditionalcommandforcardlock. reset the password: selectthecard(cmd7),ifnotpreviouslyselected already definetheblocklength(cmd16),givenbythe8bit enandlock/unlockmode,the8bitpasswordsize (inbytes),andthenumberofbytes ofthecurrentlyusedpassword. sendtheenandlock/unlockcommandwiththeapprop riatedatablocksizeonthedatalineincluding16 bitcrc.thedatablockshallindi catethemodeclr_pwd,thelength(pwd_len)andthe password (pwd)itself(lock/unlockbitisd ontcare).ifthepwdandpwd_lencontentmatchthe sent passwordanditssize,thenthec ontentofthepwdregisterisclearedandpwd_len issetto0.ifthe passwordisnotcorrectthenthelo ck_unlock_failederrorbitwillbesetinthestatu sregister. locking a e-nand: selecttheenand(cmd7),ifnotpreviouslyselecte dalready definetheblocklength(cmd16),givenbythe8bit enandlock/unlockmode,the8bitpasswordsize (inbytes),andthenumberofbytes ofthecurrentlyusedpassword. sendthecardlock/unlockcommandwiththeappropri atedatablocksizeonthedatalineincluding16 bitcrc.thedatablockshallind icatethemodelock,thelength(pwd_len)andthep assword(pwd) itself. rev 1.0 / sep. 2009 75 e-nand ifthepwdcontentequalstothesentpasswordthen theenandwillbelockedandtheenandlockedst atusbitwill besetinthestatusregister.ifthepasswordisn otcorrectthenlock_unlock_failederrorbitwillb esetinthesta tusregister. notethatitispossibletosetthepasswordandto locktheenandinthesamesequence.insuchcase thehostshall performalltherequiredstepsforsettingthepass word(asdescribedabove)includingthebitlockse twhilethenew passwordcommandissent. ifthepasswordwaspreviouslyset(pwd_lenisnot 0),thentheenandwillbelockedautomatically afterpoweron reset.anattempttolockalockedenandortoloc kaenandthatdoesnothaveapasswordwillfail andthe lock_unlock_failederrorbitwillbesetinthesta tusregister. unlocking the card: selecttheenand(cmd7),ifnotpreviouslyselecte dalready. definetheblocklength(cmd16),givenbythe8bit enandlock/unlockmode,the8bitpasswordsize (inbytes),andthenumberofbytes ofthecurrentlyusedpassword. sendtheenandlock/unlockcommandwiththeappro priatedatablocksizeonthedatalineincluding 16bitcrc.thedatablockshall indicatethemodeunlock,thelength(pwd_len)and thepassword (pwd)itself. ifthepwdcontentequalstothesentpasswordthen theenandwillbeunlockedandtheenandlocked statusbit willbeclearedinthestatusregister.ifthepass wordisnotcorrectthenthelock_unlock_failederr orbitwillbe setinthestatusregister. notethattheunlockingisdoneonlyforthecurren tpowersession.aslongasthepwdisnotcleared theenandwill belockedautomaticallyonthenextpowerup.theo nlywaytounlocktheenandisbyclearingthepas sword. anattempttounlockanunlockedenandwillfaila ndlock_unlock_failederrorbitwillbesetinthe statusregister. forcing erase: incasethattheuserforgotthepassword(thepwd content)itispossibletoerasealltheenanddat acontentalong withthepwdcontent.thisoperationiscalled forcederase . selecttheenand(cmd7),ifnotpreviouslyselecte dalready. definetheblocklength(cmd16)to1byte(8bitcar dlock/unlockcommand).sendtheenandlock/unlock commandwiththeappropriatedata blockofonebyteonthedatalineincluding16bi tcrc.thedata blockshallindicatethemodeerase (theerasebitshallbetheonlybitset). iftheerasebitisnottheonlybitinthedatafi eldthenthelock_unlock_failederrorbitwillbes etinthestatus registerandtheeraserequestisrejected. ifthecommandwasacceptedthenalltheenandcon tentwillbeerasedincludingthepwdandpwd_len registercontentandthelockedenandwillgetunl ocked.inaddition,iftheenandistemporarywrit eprotectedit willbeunprotected(writeenabled),thetemporary writeprotectbitinthecsdandallwriteprotect groupswillbe cleared.anattempttoforceeraseonanunlockede nandwillfailandlock_unlock_failederrorbitwi llbesetin thestatusregister.ifaforceerasecommandisis suedonapermanentlywriteprotectmediathecomma ndwillfail(e nandstayslocked)andthelock_unlock_failederror bitwillbesetinthestatusregister. theforceerasetimeoutisspecifiedinchapter4. 6.2 rev 1.0 / sep. 2009 76 e-nand 7.3.12 sleep (cmd5) acardmaybeswitchedbetweenasleepstateanda standbystatebysleep/awake(cmd5).inthesleeps tatethe powerconsumptionofthememorydeviceisminimized .inthisstatethememorydevicereactsonlytoth ecommands reset(cmd0)andsleep/awake(cmd5).alltheother commandsareignoredbythememorydevice.thetime out forstatetransitionsbetweenstandbystateandsle epstateisdefinedintheext_csdregisters_a_tim eout.themaxi mum currentconsumptionsduringthesleepstatearedef inedintheext_csdregisterss_a_vccands_a_vccq. sleepcommand:thebit15assetto1insleep/awak e(cmd5)argument. awakecommand:thebit15assetto0insleep/awak e(cmd5)argument. thesleepcommandisusedtoinitiatethestatetra nsitionfromstandbystatetosleepstate.thememo rydeviceindi cates thetransitionphasebusybypullingdownthedat0 line.nofurthercommandsshouldbesentduringthe busy. thesleepstateisreachedwhenthememorydevices topspullingdownthedat0line. theawakecommandisusedtoinitiatethetransitio nfromsleepstatetostandbystate.thememorydev iceindicates thetransitionphasebusybypullingdownthedat0 line.nofurthercommandsshouldbesentduringthe busy.the standbystateisreachedwhenthememorydevicesto pspullingdownthedat0line. duringthesleepstatethevccpowersupplymaybe switchedoff.thisistoenableevenfurthersystem powercon sumption saving.thevccsupplyisallowedtobeswitchedof fonlyafterthesleepstatehasbeenreached(the memory devicehasstoppedtopulldownthedat0line).the vccsupplyhavetoberampedbackupatleasttot hemin operatingvoltagelevelbeforethestatetransition fromsleepstatetostandbystateisallowedtobe initiated(awake command). rev 1.0 / sep. 2009 77 e-nand 4.4 clock control theenandbusclocksignalcanbeusedbythehost toputtheenandintoenergysavingmode,ortoc ontrolthe dataflow(toavoidunderrunoroverruncondition s)onthebus.thehostisallowedtolowertheclo ckfrequencyor shutitdown. thereareafewrestrictionsthehostmustfollow: thebusfrequencycanbechangedatanytime(under therestrictionsofmaximumdatatransferfrequenc y, definedbytheenand,andtheidentification frequencydefinedbythespecificationdocument). itisanobviousrequirementthattheclockmustbe runningfortheenandtooutputdataorresponse tokens. aftethelastenandbustransaction,thehost isrequired,toprovide 8 (eight) clockcyclesfortheenandto completetheoperationbeforeshuttingdownth eclock.followingisalistofthevariousbustra nsactions: acommandwithnoresponse.8clocksafterthehost commandendbit. acommandwithresponse.8clocksafterthecardre sponseendbit. areaddatatransaction.8clocksaftertheendbit ofthelastdatablock. awritedatatransaction.8clocksafterthecrcst atustoken. thehostisallowedtoshutdowntheclockofabus yenand.thecardwillcompletetheprogrammingop eration regardlessofthehostclock.however,theho stmustprovideaclockedgefortheenandtoturn offitsbusy signal.withoutaclockedgetheenand(unles spreviouslydisconnectedbyadeselectcommandcm d7)willforce thedat0linedown,forever. 4.5 cyclic redundancy codes (crc) thecrcisintendedforprotectingenandcommands, responsesanddatatransferagainsttransmissione rrorsonthe enandbus.onecrcisgeneratedforeverycommand andcheckedforeveryresponseonthecmdline. fordatablocksonecrcpertransferredblock,per dataline,isgenerated.thecrcisgeneratedandc heckedas describedinthefollowing. crc7 thecrc7checkisusedforallcommands,forallre sponsesexcepttyper3,andforthecsdandcidreg isters.the crc7isa7bitvalueandiscomputedasfollows: generatorpolynomial g(x) = x 7 + x 3 + 1 m(x) = (firstbit) x x n + (secondbit) x x n1 +...+ (lastbit) x x 0 crc[6...0] = remainder[(m(x) ? x 7 )/g(x)] allcrcregistersareinitializedtozero.thefirs tbitisthemostleftbitofthecorrespondingbit string(ofthecom mand,response,cidorcsd).thedegree n ofthepolynomialisthenumberofcrcprotectedbi tsdecreasedbyone. thenumberofbitstobeprotectedis40forcomman dsandresponses(n=39),and120forthecsdand cid(n= 119). rev 1.0 / sep. 2009 78 e-nand figure 4- 7 : crc7 generator/checker crc16 thecrc16isusedforpayloadprotectioninblockt ransfermode.thecrcchecksumisa16bitvaluea ndis computedasfollows: generatorpolynomial g(x) = x 16 + x 12 + x 5 + 1 m(x) = (firstbit) x x n + (secondbit) x x n1 +...+ (lastbit) x x 0 crc[15...0] = remainder[(m(x) ? x 16 )/g(x)] allcrcregistersareinitializedtozero.thefirs tbitisthefirstdatabitofthecorrespondingbl ock.thedegree n ofthe polynomialdenotesthenumberofbitsofthedatab lockdecreasedbyone(e.g.n=4095forablockle ngthof512 bytes). thegeneratorpolynomialg(x)isastandardccittp olynomial.thecodehasaminimaldistanced=4and isusedfora payloadlengthofupto2048bytes(n<=16383). thesamecrc16calculationisusedforallbusconf igurations.in4bitand8bitbusconfigurations, thecrc16iscal culatedforeachlineseparately.sendingthecrci ssynchronizedsothecrccodeistransferredatth esametimeinall lines. g d w d l q g d w d r x w rev 1.0 / sep. 2009 79 e-nand g d w d l q g d w d r x w figure 4- 8 : crc16 generator/checker 4.6 error conditions 4. 6 .1 crc and illegal command allcommandsareprotectedbycrc(cyclicredundanc ycheck)bits.iftheaddressedenandscrccheck fails,the enanddoesnotrespond,andthecommandisnotexe cuted;theenanddoesnotchangeitsstate,and com_crc_errorbitissetinthestatusregister. similarly,ifanillegalcommandhasbeenreceived, theenandshallnotchangeitsstate,shallnotr espondandshallset theillegal_commanderrorbitinthestatusregiste r.onlythenonerroneousstatebranchesareshown inthestate diagrams(seefigure41tofigure42).table41 8containsacompletestatetransitiondescription. therearedifferentkindsofillegalcommands: commandswhichbelongtoclassesnotsupportedbyt heenand(e.g.writecommandsinreadonlyenand) . commandsnotallowedinthecurrentstate(e.g.cmd 2intransferstate). commandswhicharenotdefined(e.g.cmd44). 4.6.2 read, write, erase and force erase time-out c onditions thetimesafterwhichatimeoutconditionforread /write/eraseoperationsoccursare(enandindepend ent) 10 times longer thanthetypicalaccess/programtimesfortheseope rationsgivenbelow.aenandshallcompletetheco mmand withinthistimeperiod,orgiveupandreturnane rrormessage.ifthehostdoesnotgetaresponsew ithinthedefined timeoutitshouldassumetheenandisnotgoingt orespondanymoreandtrytorecover(e.g.resetth eenand, powercycle,reject,etc.).thetypicalaccessand programtimesaredefinedasfollows: read thereadaccesstimeisdefinedasthesumofthet wotimesgivenbythecsdparameterstaacandnsac (seechapter 4.13).theseenandparametersdefinethetypicald elaybetweentheendbitofthereadcommandandth estartbitof thedatablock. rev 1.0 / sep. 2009 80 e-nand write ther2w_factorfieldinthecsdisusedtocalculat ethetypicalblockprogramtimeobtainedbymultip lyingthe readaccesstimebythisfactor.itappliestoall write/erasecommands(e.g.set(clear)_write_protect , program_csd(cid)andtheblockwritecommands). erase thedurationofanerasecommandwillbe(orderof magnitude)thenumberofwriteblockstobeerased multipliedby theblockwritedelay. force erase thedurationoftheforceerasecommandusingcmd42 isspecifiedtobeafixedtimeoutof3minutes. 4.7 minimum performance theenandhastofullfilltherequirementssetfor thereadandwriteaccessperformance. 4.7.1 speed class definition thespeedclassdefinitionisforindicationofthe minimumperformanceofaenand.theclassesared efinedbased onthe150kb/sbasevalue.theminimumperformance oftheenandcanthenbemarkedbydefinedmultipl esof thebasevaluee.g.2.4mb/s.onlyfollowingspeedc lassesaredefined(notethatenandsarealwaysin cluding8bit databusandthecategoriesbelowstatestheconfig urationwithwhichtheenandisoperated): lowbuscategoryclasses(26mhzclockwith4bitdat abusoperation) 2.4mb/sclassa 3.0mb/sclassb 4.5mb/sclassc 6.0mb/sclassd 9.0mb/sclasse midbuscategoryclasses(26mhzclockwith8bitdat abusor52mhzclockwith4bitdatabusoperation): 12.0mb/sclassf 15.0mb/sclassg 18.0mb/sclassh 21.0mb/sclassj highbuscategoryclasses(52mhzclockwith8bitda tabusoperation): 24.0mb/sclassk 30.0mb/sclassm 36.0mb/sclasso 42.0mb/sclassr 48.0mb/sclasst theperformancevaluesforbothwriteandreadacce ssesarestoredintotheext_csdregisterforelect ricalreading (seechapter3.4.5onpage48).onlythedefinedva luesandclassesareallowedtobeused. rev 1.0 / sep. 2009 81 e-nand 4.7.2 absolute minimum absoluteminimumreadandwriteaccessperformance whichallenandhastofullfillis2.4mb/s.thisi stheclassa. 4.7.3 measurement of the performance theprocedureforthemeasurementoftheperformanc eoftheenandisdefinedindetailinthecomplia ncedocu mentation. initialstateofthememoryinpriortothetestis :filledwithrandomdata.thetestisperformedby writing/readinga 64kbchunkofdatato/fromrandomlogicaladdresses (alignedtophysicalblockboundaries)oftheenan d.apre definedmultipleblockwrite/readisusedwithbloc kcountof128(64kbas512bblocksareused).the performance iscalculatedasaverageoutofseveral64kbaccess es. sametestisperformedwithallapplicableclockfr equencyandbuswidthoptionsasfollows: 52mhz,8bitbus(if52mhzclockfrequencyissuppor tedbytheenand) 52mhz,4bitbus(if52mhzclockfrequencyissuppor tedbytheenand) 26mhz,8bitbus 26mhz,4bitbus incasetheminimumperformanceoftheenandexcee dsthephysicallimitofoneoftheabovementioned options theenandhastoalsofulfillaccordinglytheperf ormancecriteriaasdefinedin min_perf_a_b_ff onpage42. rev 1.0 / sep. 2009 82 e-nand bit position 47 46 [45:40] [39:8] [7:1] 0 width(bits) 1 1 6 32 7 1 value 0 1 x x x 1 description startbit transmissionbit commandindex argument crc7 endbit table 4-6 : format acommandalwaysstartswithastartbit(always0 ),followedbythebitindicatingthedirectionof transmission (host=1). thenext6bitsindicatetheindexofthecommand, thisvaluebeinginterpretedasabinarycodednumb er(between 0and63).somecommandsneedanargument(e.g.an address),whichiscodedby32bits.avaluedenote dbyxin thetableaboveindicatesthisvariableisdependen tonthecommand.allcommandsareprotectedbyac rc(see chapter4.5forthedefinitionofcrc7).everycomm andcodewordisterminatedbytheendbit(always 1).allcom mandsandtheirargumentsarelistedintable47 table417. 4.8.3 command classes thecommandsetoftheenandisdividedintosever alclasses(seetable47).eachclasssupportsa subsetofenandfunctions. class0ismandatoryandshallbesupportedbyall enands.theotherclassesareeithermandatoryonl yforspecific enandtypesoroptional.thesupportedcardcomman dclasses(ccc)arecodedasaparameterinthecar d specificdata(csd)registerofeachenand,provid ingthehostwithinformationonhowtoaccessthe enand. 4.8 commands 4.8.1 command types therearefourkindsofcommandsdefinedtocontrol theenand: *broadcastcommands(bc),noresponse *broadcastcommandswithresponse(bcr) *addressed(pointtopoint)commands(ac),no datatransferondatlines *addressed(pointtopoint)datatransfercomm ands(adtc),datatransferondatlines *allcommandsandresponsesaresentoverthe cmdlineoftheenandbus.thecommandtransmissio n alwaysstartswiththeleftbitofthebitstr ingcorrespondingtothecommandcodeword. 4.8.2 command format allcommandshaveafixedcodelengthof48bits,n eedingatransmissiontimeof0.92microsec@52mh z rev 1.0 / sep. 2009 83 e-nand card command class (ccc) class description supported commands 0 1 2 3 4 5 6 7 8 9 1 0 11 12 13 14 15 16 17 18 19 20 class0 basic + + + + + + + + + + + + + + + + class1 streamread + class2 blockread + + + class3 streamwrite + class4 blockwrite + class5 erase class6 writeprotection class7 lockcard + class8 applicationspecific class9 i/omode class1011 reserved card command class (ccc) class description supported commands 23 24 25 26 27 28 29 30 35 36 38 39 40 42 55 56 class0 basic class1 streamread class2 blockread + class3 streamwrite class4 blockwrite + + + + + class5 erase + + + class6 writeprotection + + + class7 lockcard + class8 applicationspecific + + class9 i/omode + + class1011 reserved table 4-7 : card command classes (ccc) note: supportmmccommandclass: class0,2,4,5,6,7,8 4.8.4 detailed command description thefollowingtablesdefineindetailallenandsb uscommands.theresponsesr1r5aredefinedincha pter4.10.the registerscid,csd,ext_csdanddsraredescribedi nchapter3.4. rev 1.0 / sep. 2009 84 e-nand cmd index type argument resp abbreviation command description cmd0 bc [31:0]stuffbits go_idle_state resetstheenan dtoidlestate cmd1 bcr [31:0]ocrwithout busy r3 send_op_cond askstheenand,inidlestate,tosenditsoperat ingconditionsregistercontentsintheresponse onthecmdline. cmd2 bcr [31:0]stuffbits r2 all_send_cid askstheenandtosenditscidnumberonthe cmdline cmd3 ac [31:16]rca [15:0]stuffbits r1 set_relative_addr set_relative_addr cmd4 ac [31:16]dsr [15:0]stuffbits set_dsr programsthedsrofthecard cmd5 ac [31:16]rca [15]sleep/awake [14:0]stuffbits r1b sleep_awake togglesthecardbetweensleepstate and standbystate.(seesection7.3.12) cmd6 ac [31:26]setto0 [25:24]access [23:16]index [15:8]value [7:3]setto0 [2:0]cmdset r1b switch switchesthemodeofoperationoftheselected enandormodifiestheext_csdregisters. (seechapter4.3.1) cmd7 ac [31:16]rca [15:0]stuffbits r1b a select/ deselect_enand commandtogglesaenandbetweenthestand byandtransferstatesorbetweentheprogram minganddisconnectstates.inbothcasesthe enandisselectedbyitsownrelativeaddress andgetsdeselectedbyanyotheraddress; address0deselectstheenand. cmd8 adtc [31:0]stuffbits r1 send_ext_csd theenandsendsitsext_csdregisterasa blockofdata. cmd9 ac [31:16]rca [15:0]stuffbits r2 send_csd addressedenandsendsitscardspecificdata (csd)onthecmdline. cmd10 ac [31:16]rca [15:0]stuffbits r2 send_cid addressedenandsendsitscardidentification (cid)oncmdtheline. cmd11 notsupported cmd12 ac [31:0]stuffbits r1b stop_transmission forcestheenandtostoptransmission cmd13 ac [31:16]rca [15:0]stuffbits r1 send_status addressedenandsendsitsstatusregister. cmd14 adtc [31:0]stuffbits r1 bustest_r ahostreadsthereversedbustestingdata patternfromaenand. rev 1.0 / sep. 2009 85 e-nand cmd index type argument resp abbreviation command description cmd16 ac [31:0]blocklength r1 set_blocklen setstheblocklength(inbytes)forallfollowing blockcommands(readandwrite).defaultblock lengthisspecifiedinthecsd. cmd17 adtc [31:0]dataaddress r1 read_single_block readsablockofthesizeselectedbythe set_blocklencommand. a cmd18 adtc [31:0]dataaddress r1 read_multiple_blo ck continuouslytransfersdatablocksfromenandto hostuntilinterruptedbyastopcommand,orthe requestednumberofdatablocksistransmitted table 4-9 : block oriented read commands (class 2) a.thetransferreddatamustnotcrossaphysicalbl ockboundary,unlessread_blk_misalignissetinth ecsdregister cmd index type argument resp abbreviation command description cmd20 ac [31:0]dataaddress r1 write_dat_until_s top writesadatastreamfromthehost,starting atthegivenaddress,untila stop_transmissionfollows. cmd21 ... cmd22 reserved a.dataaddressformedia=<2gbisa32bitbyteadd ressanddataaddressformedia>2gbisa32bitse ctor(512b) address. table 4-10 : stream write commands (class 3) cmd15 ac [31:16]rca [15:0]stuffbits go_inactive_state setstheenandtoinactivestate cmd19 adtc [31:0]stuffbits r1 bustest_w ahostsendsthebustestdatapatterntoa enand. table 4-8 : basic commands and read stream commands (class 0 and class 1) a.r1whileselectingfromstandbystatetotransf erstate;r1bwhileselectingfromdisconnectedsta tetoprogramming state. b.dataaddressformedia=<2gbisa32bitbyteadd ressanddataaddressformedia>2gbisa32bitse ctor(512b) address. c.r1forreadcasesandr1bforwritecases. rev 1.0 / sep. 2009 86 e-nand cmd index type argument resp abbreviation command description cmd23 ac [31]reliablewrite request[30:16]set to0[15:0]number ofblocks r1 set_block_count definesthenumberofblockswhicharegoing tobetransferredintheimmediatelysucceeding multipleblockreadorwritecommand. iftheargumentisall0s,thesubsequentread/ writeoperationwillbeopenended. cmd24 adtc [31:0]dataaddress r1 write_block writesablockofthesizeselectedbythe set_blocklencommand .a cmd25 adtc [31:0]dataaddress r1 write_multiple_bl ock continuouslywritesblocksofdatauntila stop_transmissionfollowsorthe requestednumberofblockreceived. cmd26 adtc [31:0]stuffbits r1 program_cid programmingofthecardidentificationregister. thiscommandshallbeissuedonly once.thecardcontainshardwaretoprevent thisoperationafterthefirstprogramming. normallythiscommandisreserved forthemanufacturer. cmd27 adtc [31:0]stuffbits r1 program_csd programmingoftheprogrammablebitsofthe csd. table 4-11 : block oriented write commands (class 4 ) a.thetransferreddatamustnotcrossaphysicalbl ockboundaryunlesswrite_blk_misalignissetinth ecsd rev 1.0 / sep. 2009 87 e-nand cmd index type argument resp abbreviation command description cmd28 ac [31:0]dataaddress r1b set_write_prot iftheenandhaswriteprotectionfeatures,this commandsetsthewriteprotectionbitofthe addressedgroup.thepropertiesofwriteprotec tionarecodedinthecardspecificdata (wp_grp_size). cmd29 ac [31:0]dataaddress r1b clr_write_prot iftheenandprovideswriteprotectionfeatures, thiscommandclearsthewriteprotectionbitof theaddressedgroup. cmd30 adtc [31:0]writeprotect dataaddress r1 send_write_prot iftheenandprovideswriteprotectionfeatures, thiscommandaskstheenandtosendthesta tusofthewriteprotectionbits. a cmd31 reserved table 4-13 : block oriented write protection comman ds (class 6) a.32writeprotectionbits(representing32write protectgroupsstartingatthespecifiedaddress)f ollowedby16 crcbitsaretransferredinapayloadformatviath edatalines.thelast(leastsignificant)bitoft heprotectionbits correspondstothefirstaddressedgroup.ifthead dressesofthelastgroupsareoutsidethevalidra nge,thenthe correspondingwriteprotectionbitsshallbesetto zero. rev 1.0 / sep. 2009 88 e-nand cmd index type argument resp abbreviation command description cmd32 ... cmd34 reserved. thesecommandindexescannotbeusedinordertoma intainbackwardscompatibilitywitholderversions of theenand cmd35 ac [31:0]dataaddress r1 erase_group_start setstheaddressofthefirsterasegroup withinarangetobeselectedforerase cmd36 ac [31:0]dataaddress r1 erase_group_end setstheaddressofthelasterasegroup withinacontinuousrangetobeselected forerase cmd37 reserved. thiscommandindexcannotbeusedinordertomaint ainbackwardscompatibilitywitholderversionsof the enand cmd38 ac [31:0]stuffbits r1b erase erasesallpreviouslyselectedwriteblocks table 4-14 : erase commands (class 5) cmd index type argument resp abbreviation command description cmd39 cmd40 mmcaoptionalcommand,currentlynotsupported. cmd41 reserved table 4-15 : i/o mode commands (class 9) cmd index type argument resp abbreviation command description cmd42 adtc [31:0]stuffbits. r1b lock_unlock usedtoset/resetthepasswordorlock/unlock theenand.thesizeofthedatablockissetby theset_block_lencommand. cmd43... cmd54 reserved table 4-16 : lock e-nand (class 7) rev 1.0 / sep. 2009 89 e-nand cmd index type argument resp abbreviation command description cmd55 cmd56 mmcaoptionalcommand,currentlynotsupported. cmd57 ... cmd59 reserved cmd60 ... cmd63 reservedformanufacturer table 4-17 : application specific commands (class 8 ) allfuturereservedcommandsshallhaveacodeword lengthof48bits,aswellastheirresponses(ift hereareany). rev 1.0 / sep. 2009 90 e-nand 4.9 e-nand state transition tabledefinestheenandstatetransitionsindepen dencyofthereceivedcommand. current state idle ready ident stby tran data btst rcv prg dis ina slp irq command changesto class independent crcerror stby commandnotsupported stby class 0 cmd0 idle idle idle idle idle idle idle idle idle idle idle st by cmd1,enandvccqrange compatible ready stby cmd1,enandisbusy idle stby cmd1,enandvccqrange notcompatible ina stby cmd2,enandwinsbus ident stby cmd2,enandlosesbus ready stby cmd3 stby stby cmd4 stby stby cmd5 slp stby stby cmd6 prg stby cmd7, cardisaddressed tran prg stby cmd7, cardisnotaddressed stby stby dis stby cmd8 data stby cmd9 stby stby cmd10 stby stby cmd12 tran prg stby cmd13 stby tran data btst rcv prg dis stby cmd14 tran stby cmd15 ina ina ina ina ina ina ina stby cmd19 btst stby class 1 cmd11 data stby class 2 cmd16 tran stby cmd17 data stby cmd18 data stby cmd23 tran stby table 4-18 : e-nand state transition table rev 1.0 / sep. 2009 91 e-nand current state idle ready ident stby tran data btst rcv prg dis ina irq class 3 cmd20 rcv stby class 4 cmd16 seeclass2 cmd23 seeclass2 cmd24 rcv rcv stby cmd25 rcv rcv stby cmd26 rcv stby cmd27 rcv stby class 6 cmd28 prg stby cmd29 prg stby cmd30 data stby class 5 cmd35 tran stby cmd36 tran stby cmd38 prg stby class 7 cmd16 seeclass2 cmd42 rcv stby class 8 cmd55 stby tran data btst rcv prg dis irq cmd56;rd/wr=0 rcv stby cmd56;rd/wr=1 data stby class 9 cmd39 cmd40 mmcaoptionalcommand,currentlynotsupported class1011 cmd41;cmd43...cmd54, cmd57cmd59 reserved cmd60...cmd63 reservedformanufacturer table 4-19 : card state transition table 4.10 responses allresponsesaresentviathecommandlinecmd.th eresponsetransmissionalwaysstartswiththeleft bitofthebit stringcorrespondingtotheresponsecodeword.the codelengthdependsontheresponsetype. aresponsealwaysstartswithastartbit(always 0),followedbythebitindicatingthedirectiono ftransmission(card =0).avaluedenotedbyxinthetablesbelow indicatesavariableentry.allresponsesexceptfo rthetyper3(see below)areprotectedbyacrc(seechapter4.5for thedefinitionofcrc7).everycommandcodewordis terminated bytheendbit(always1). rev 1.0 / sep. 2009 92 e-nand therearefivetypesofresponses.theirformatsar edefinedasfollows: r1 (normalresponsecommand):codelength48bit.the bits45:40indicatetheindexofthecommandtobe respondedto,thisvaluebeinginterpretedasabin arycodednumber(between0and63).thestatusof theenand iscodedin32bits. theenandstatusisdescribedinchapter4.11 bit position 47 46 [45:40] [39:8] [7:1] 0 width(bits) 1 1 6 32 7 1 value 0 0 x x x 1 description startbit transmission bit command index enand status crc7 endbit table 4-20 : response r1 r1b isidenticaltor1withanoptionalbusysignaltra nsmittedonthedatalinedat0.theenandmaybeco me busyafterreceivingthesecommandsbasedonitsst atepriortothecommandreception.refertosectio nfordetailed descriptionandtimingdiagrams. r2 (cid,csdregister):codelength136bits.thecont entsofthecidregisteraresentasaresponseto thecom mandscmd2andcmd10.thecontentsofthecsdregis teraresentasaresponsetocmd9.onlythebits[ 127...1] ofthecidandcsdaretransferred,thereservedbi t[0]oftheseregistersisreplacedbytheendbit oftheresponse. bit position 47 46 [45:40] [39:8] [7:1] width(bits) 1 1 6 127 1 value 0 0 111111 x 1 description startbit transmissionbit checkbits cidorcsdregisterincl. internalcrc7 endbit table 4-21 : response r2 r3 (ocrregister):codelength48bits.thecontentso ftheocrregisterissentasaresponsetocmd1.t he level coding isasfollows:restrictedvoltagewindows=low,card busy=low. rev 1.0 / sep. 2009 93 e-nand bit position 47 46 [45:40] [39:8] [7:1] 0 width(bits) 1 1 6 32 7 1 value 0 0 111111 x 1111111 1 description startbit transmission bit checkbits ocrregister checkbits endbit table 4-22 : response r3 r4andr5:responsesarenotsupported. 4.11 e-nand status theresponseformatr1containsa32bitfieldname d enandstatus .thisfieldisintendedtotransmittheenands statusinformation. threedifferentattributesareassociatedwitheach oneoftheenandstatusbits: bittype. twotypesofenandstatusbitsaredefined: (a) error bit .signalsanerrorconditiondetectedbytheenand .thesebitsareclearedassoonastheresponse (reportingtheerror)issentout. (b) status bit .thesebitsserveasinformationfieldsonly,and donotaltertheexecutionofthecommandbeing respondedto.thesebitsaresetandclearedinacc ordancewiththeenandstatus. thetypefieldoftable423definesthetypeofea chbitintheenandstatusregister.thesymbole isusedtodenote anerrorbitwhilethesymbolsisusedtodenotea statusbit. detectionmodeoferrorbits. exceptionsaredetectedbytheenandeitherduring thecommandinterpretationandvalidationphase(r esponse mode)orduringcommandexecutionphase(execution mode).responsemodeexceptionsarereportedinthe responsetoastop_transmissioncommandusedtoter minatetheoperationorintheresponsetoaget_st atus commandissuedaftertheoperationiscompleted. thedetmodefieldoftable423definesthedetect ionmodeofeachbitinthecardstatusregister.t hesymbolris usedtodenotearesponsemodedetectionwhilethe symbolxisusedtodenoteanexecutionmodedetect ion. whenanerrorbitisdetectedinrmodetheenand willreporttheerrorintheresponsetothecomman dthatraised theexception.thecommandwillnotbeexecutedand theassociatedstatetransitionwillnottakeplac e.whenan errorisdetectedinxmodetheexecutionistermin ated.theerrorwillbereportedintheresponseto thenextcom mand.theaddress_out_of_rangeandaddress_misalign exceptionsmaybedetectedbothinresponseand executionmodes.theconditionsforeachoneofthe modesareexplicitlydefinedinthetable423. clearcondition: aaccordingtothecardcurrentstate balwaysrelatedtothepreviouscommand.recepti onofavalidcommandwillclearit(withadelayo fonecommand) cclearbyread. rev 1.0 / sep. 2009 94 e-nand bits identifier type det- mode value descript clear cond 31 address_ out_of_range e r 0=noerror 1=error thecommandsaddressargumentwasout oftheallowedrangeforthisenand. c x amultipleblockorstreamread/writeopera tionis(althoughstartedinavalidaddress) attemptingtoreadorwritebeyondthe enandcapacity 30 address_misalign e r 0=noerror 1=error thecommandsaddressargument(in accordancewiththecurrentlysetblock length)positionsthefirstdatablockmis alignedtotheenandphysicalblocks. c x amultipleblockread/writeoperation (althoughstartedwithavalidaddress/block lengthcombination)isattemptingtoreador writeadatablockwhichdoesnotalignwith thephysicalblocksoftheenand. 29 block_len_error e r 0=noerror 1=error eithertheargumentofaset_blocklen commandexceedsthemaximumvalue allowedfortheenand,orthepreviously definedblocklengthisillegalforthecurrent command(e.g.thehostissuesawritecom mand,thecurrentblocklengthissmaller thantheenandsmaximumandwritepar tialblocksisnotallowed) c 28 erase_seq_error e r 0=noerror 1=error anerrorinthesequenceoferasecommands occurred. c 27 erase_param e x 0=noerror 1=error aninvalidselectionoferasegroupsforerase occurred. c 26 wp_violation e x 0=noerror 1=error attempttoprogramawriteprotectedblock. c 25 card_is_locked s r 0=card unlocked1= cardlocked whenset,signalsthatthecardislockedby thehost a 24 lock_unlock_ failed e x 0=noerror 1=error setwhenasequenceorpassworderrorhas beendetectedinlock/unlockcardcommand c 23 com_crc_error e r 0=noerror 1=error thecrccheckofthepreviouscommand failed. b 22 illegal_command e r 0=noerror 1=error commandnotlegalfortheenandstate b 21 card_ecc_failed e x 0=success 1=failure cardinternaleccwasappliedbutfailedto correctthedata. c 20 cc_error e r 0=noerror 1=error (undefinedbythestandard) acarderroroccurred,whichisnotrelatedto thehostcommand. c table 4-23 : e-nand status rev 1.0 / sep. 2009 95 e-nand bits identifier type det- mode value descript clear cond 19 error e x 0=noerror 1=error (undefinedbythestandard) agenericenanderrorrelatedtothe(and detectedduring)executionofthelasthost command(e.g.readorwritefailures). c 18 17 notapplicable.thisbitisalwayssetto0. 16 cid/ csd_overwrite e x 0=noerror 1=error canbeeitheroneofthefollowingerrors: thecidregisterhasbeenalreadywritten andcannotbeoverwritten thereadonlysectionofthecsddoesnot matchtheenandcontent. anattempttoreversethecopy(setasorig inal)orpermanentwp(unprotected)bits wasmade. c 15 wp_erase_skip e x 0=notpro tected 1=protected onlypartialaddressspacewaseraseddueto existingwriteprotectedblocks. c 14 reserved,mustbesetto0 13 erase_reset e r 0=cleared 1=set anerasesequencewasclearedbeforeexe cutingbecauseanoutoferasesequence commandwasreceived(commandsother thancmd35,cmd36,cmd38orcmd13 c 12:9 current_state s r 0=idle 1=ready 2=ident 3=stby 4=tran 5=data 6=rcv 7=prg 8=dis 9=btst 10=slp 1115= reserved thestateoftheenandwhenreceivingthe command. ifthecommandexecutioncausesastate change,itwillbevisibletothehostin theresponseonthenextcommand.thefour bitsareinterpretedasabinarynumber between0and15. b 8 ready_for_data s r 0=notready 1=ready correspondstobufferemptysignallingon thebus a 7 switch_error e x 0=noerror 1=switcherror ifset,theenanddidnotswitchtothe expectedmodeasrequestedbytheswitch command c 6 reserved 5 notapplicable.thisbitisalwayssetto0. 4 reserved 3:2 reservedforapplicationspecificcommands 1:0 reservedformanufacturertestmode table 4-24 : e-nand status rev 1.0 / sep. 2009 96 e-nand : u l w h % o r f n ( u d v h * u r x s ( u d v h * u r x s ( u d v h * u r x s ( u d v h * u r x s ( u d v h * u r x s q : u l w h 3 u r w h f w * u r x s : u l w h 3 u r w h f w * u r x s : u l w h 3 u r w h f w * u r x s : u l w h 3 u r w h f w * u r x s q h 1 $ 1 ' : u l w h % o r f n : u l w h % o r f n : u l w h % o r f n : u l w h % o r f n q 4.12 memory array partitioning thebasicunitofdatatransferto/fromtheenand isonebyte.alldatatransferoperationswhichreq uireablocksize alwaysdefineblocklengthsasintegermultiplesof bytes.somespecialfunctionsneedotherpartition granularity. forblockorientedcommands,thefollowingdefiniti onisused: block :istheunitwhichisrelatedtotheblockoriente dreadandwritecommands.itssizeisthenumbero fbytes whichwillbetransferredwhenoneblockcommandis sentbythehost.thesizeofablockiseitherpr ogrammableor fixed.theinformationaboutallowedblocksizesan dtheprogrammabilityisstoredinthecsd. forr/wenands,specialeraseandwriteprotectco mmandsaredefined: thegranularityoftheerasableunitsisthe erase group: thesmallestnumberofconsecutivewriteblockswhi chcan beaddressedforerase.thesizeoftheerasegroup isenandspecificandstoredinthecsd when erase_group_def is enabled. thegranularityofthewriteprotectedunitsisthe wp-group: theminimalunitwhichmaybeindividuallywritepr o tected. itssizeisdefinedinunitsoferasegroups.thes izeofawpgroupisenandspecificandstoredin thecsd when erase_group_def is disabled, and in the ext_csd whe n erase_group_def is enabled. figure 4-9 : memory array partitioning rev 1.0 / sep. 2009 97 e-nand cmd s t content crc e z * * * t s z content z z z host command n id cycles cid or ocr 4.13 timing diagrams alltimingdiagramsusethefollowingschematicsan dabbreviations: symbol definition s startbit(=0) t transmitterbit(host=1,enand=0) p onecyclepullup(=1) e endbit(=1) l onecyclepulldown(=0) z highimpedancestate(>=1) x drivenvalue,1or0 d databits * repetition crc cyclicredundancycheckbits(7bits) enandactive hostactive table 4-25 : timing diagram symbols thedifferencebetweenthepbitandzbitisthat apbitisactivelydriventohighbytheenandre spectivelyhost outputdriver,whilezbitisdrivento(respective lykept)highbythepullupresistorsrcmdrespect ivelyrdat. activelydrivenpbitsarelesssensitivetonoise. alltimingvaluesaredefinedintable425. 4.13.1 command and response bothhostcommandandenandresponseareclockedo utwiththerisingedgeofthehostclock. e-nand identification and e-nand operation conditio ns timing thecard(enand)identification(cmd2)andcard(e nand)operationconditions(cmd1)timingareproce ssedin theopendrainmode.theenandresponsetothehos tcommandstartsafterexactlynidclockcycles. figure 4-10 : identification timing (e-nand identif ication mode) rev 1.0 / sep. 2009 98 e-nand cmd s s t t z * * * z crc e e crc content content host command n cycles cr response z z z cmd s t z z z e crc content host command z z z z z z z q g q g q g q g q g q g q g q g q g q g q g q g q g q g q z zzz z z z z z z z z z z z z z z z z z z z z z z s l x q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g e z z x z z z z 8 n : st e-nand is busy dat0 dat1-7 cmd host command z q g q g q g content n cr cycles response s t content crc e z p s p t z z z e crc assign a e-nand relative address theset_rca(cmd3)isalsoprocessedintheopend rainmode.theminimumdelaybetweenthehostcomma nd andenandresponseisncrclockcycles. figure 4-11 : set_rca timing (e-nand identification mode) data transfer mode. afteraenandreceivesitsrcaitwillswitchtod atatransfermode.inthismodethecmdlineisdri venwithpush pulldrivers. thecommandisfollowedbyaperiodoftwozbits( allowingtimefordirectionswitchingonthebus)a ndthanbyp bitspushedupbytherespondingenand.thistimin gdiagramisrelevantforallrespondedhostcomman dsexcept cmd1,2,3: figure 4-12 : command response timing (data transfe r mode) r1b responses somecommands,likecmd6,mayassertthebusysigna lafterrespondingwithr1.ifthebusysignalisa sserted,it isdonetwoclockcyclesaftertheendbitofthec ommand.thedat0lineisdrivenlow,dat1dat7line saredriven bytheenandthoughtheirvalueisnotrelevant. figure 4-13 : r1b response timing rev 1.0 / sep. 2009 99 e-nand e content host command z * * * content n cr cycles host command z crc s t e z s t z cmd crc cmd content host command * * * content n cc cycles host command crc s t crc s t z e z z e z last e-nand response - next host command timing afterreceivingthelastenandresponse,thehost canstartthenextcommandtransmissionafteratle astnrcclock cycles.thistimingisrelevantforanyhostcomman d. figure 4-14 : timing response end to next command s tart (data transfer mode) last host command - next host command timing afterthelastcommandhasbeensent,thehostcan continuesendingthenextcommandafteratleastnc cclock periods. iftheall_send_cidcommandisnotrespondedbythe enandafternid+1clockperiods,thehostcanc onclude thereisnoenandpresentinthebus. figure 4-15 : timing of command sequences (all mode s) rev 1.0 / sep. 2009 100 e-nand cmd s t z e e crc content host command p content z p p n cr cycles response * * z z z e z p z z d * * * * * * * * * * * * * z p t s crc * * * * * p p s d d z d * * * * z p p * * * * * * p s p p p p d d d d n ac cycles read data n ac cycles read data dat0-7 cmd s t z e e crc content host command content z p p n cr cycles response * * z z z z z z * * * * * * * z t s crc * * * * * p p s d d d * * * n ac cycles read data dat0-7 4.14 data read single block read thehostselectsoneenandfordatareadoperation bycmd7,andsetsthevalidblocklengthforblock orienteddata transferbycmd16.thebasicbustimingforaread operationisgiveninfigure416.thesequencesta rtswithasingle blockreadcommand(cmd17)whichspecifiesthestar taddressintheargumentfield.theresponseisse ntonthe cmdlineasusual. figure 4-16 : single block read timing datatransmissionfromtheenandstartsafterthe accesstimedelaynacbeginningfromtheendbitof theread command. afterthelastdatabit,thecrccheckbitsaresuf fixedtoallowthehosttocheckfortransmissione rrors. multiple block read inmultipleblockreadmode,theenandsendsacon tinuousflowofdatablocksfollowingtheinitialh ostreadcom mand.thedataflowisterminatedbyastoptransmi ssioncommand(cmd12).figure417describestheti mingofthe datablocksandfigure418theresponsetoastop command.thedatatransmissionstopstwoclockcycl esafterthe endbitofthestopcommand. figure 4-17 : multiple block read timing rev 1.0 / sep. 2009 101 e-nand t~u ? ? ? v v t?t ????? y?qt?????? ????? ? ? ? t? ?a??? ?????? q g q g q g u u u u u v u ? ? t?t q g q g q g q g q g q g q ? n ?? ur?a^h ? q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g q g : ?????q????q??? : figure 4-18 : stop command timing (cmd12, data tran sfer mode) 4.15 data write single block write thehostselectstheenandfordatawriteoperatio nbycmd7. thehostsetsthevalidblocklengthforblockorie nteddatatransfer(astreamwritemodeisalsoava ilable)bycmd16. thebasicbustimingforawriteoperationisgiven infigure419.thesequencestartswithasingle blockwritecom mand(cmd24)whichdetermines(intheargumentfiel d)thestartaddress.itisrespondedbytheenand onthecmd lineasusual. thedatatransferfromthehoststartsnwrclockcy clesaftertheenandresponsewasreceived. thedataissuffixedwithcrccheckbitstoallowt heenandtocheckitfortransmissionerrors.the enandsendsback thecrccheckresultasacrcstatustokenondat0. inthecaseoftransmissionerror,occurringonan yoftheactive datalines,theenandsendsanegativecrcstatus (101)ondat0.inthecaseofsuccessfultransmissi on,overall activedatalines,theenandsendsapositivecrc status(010)ondat0andstartsthedataprogrammin gprocedure figure 4-19 : block write command timing whilethecardisprogrammingitindicatesbusyby pullingdownthedat0line.thisbusystatusisdir ectlyrelatedtopro grammingstate.assoonasthecardcompletesthep rogrammingitstopspullingdownthedat0line. multiple block write inmultipleblockwritemode,theenandexpectsco ntinuousflowofdatablocksfollowingtheinitial hostwritecom mand.thedataflowisterminatedbyastoptransmi ssioncommand(cmd12).figure420describestheti mingofthe datablockswithandwithoutenandbusysignal. rev 1.0 / sep. 2009 102 e-nand figure 4-20 : multiple block write timing thestoptransmissioncommandworkssimilarasint hereadmode.figure421tofigure424describet hetimingof thestopcommandindifferentenandstates. figure 4-21 : stop transmission during data transfe r from the host theenandwilltreatadatablockassuccessfully receivedandreadyforprogrammingonlyifthecrc dataoftheblock wasvalidatedandthecrcstatustokenssentbackt othehost.figure421isanexampleofaninterru pted(byahoststop command)attempttotransmitthecrcstatusblock. thesequenceisidenticaltoallotherstoptransmi ssionexamples. theendbitofthehostcommandisfollowed,onthe datalines,withonemoredatabit,anendbitand twozclocksfor switchingthebusdirection.thereceiveddatabloc k,inthiscaseisconsideredincompleteandwilln otbeprogrammed. figure 4-22 : stop transmission during crc status t ransfer from the e-nand allpreviousexamplesdealtwiththescenarioofth ehoststoppingthedatatransmissionduringanact ivedatatransfer. thefollowingtwodiagramsdescribeascenarioofr eceivingthestoptransmissionbetweendatablocks. inthefirst exampletheenandisbusyprogrammingthelastblo ckwhileinthesecondtheenandisidle.however, therearestill unprogrammeddatablocksintheinputbuffers.thes eblocksarebeingprogrammedassoonasthestopt ransmission commandisreceivedandtheenandactivatesthebu sysignal. enandresponse busy(enandisprogramming) rev 1.0 / sep. 2009 103 e-nand figure 4-23 : stop transmission after last data blo ck. e-nand is busy programming. figure 4-24 : stop transmission after last data blo ck. e-nand becomes busy. erase, set and clear write protect timing thehostmustfirstselecttheerasegroupstobee rasedusingtheerasestartandendcommand(cmd35, cmd36).the erasecommand(cmd38),onceissued,willeraseall selectederasegroups.similarly,setandclearwri teprotectcom mandsstartaprogrammingoperationaswell.thee nandwillsignalbusy(bypullingthedat0linelow )forthedura tionoftheeraseorprogrammingoperation.thebus transactiontimingsareidenticaltothevariation ofthestop transmissiondescribedinfigure424. reselecting a busy e-nand whenabusyenandwhichiscurrentlyinthedisst ateisreselecteditwillreinstateitsbusysignal ingonthedataline dat0. thetimingdiagramforthiscommand/response/bu sytransactionisgiveninfigure424. rev 1.0 / sep. 2009 104 e-nand 4.16 bus test procedure timing afterreachingthetranstateahostcaninitiatet hebustestingprocedure.ifthereisnoresponset othecmd19sent bythehost,thehostshouldreadthestatusfromt heenandwithcmd13.iftherewasnoresponsetoc md19,the hostmayassumethatthisfunctionisnotsupported bytheenand. figure 4-25 : 4 bit system bus testing procedure 4.17 boot operation figure 4-26: boot operation, termination between co nsecutive data blocks rev 1.0 / sep. 2009 105 e-nand figure 4-27: boot operation, termination during tra nsfer figure 4-28: bus mode change timing (push-pull to o pen drain) 4.17.1 alternative boot operation (device optional) figure 4-29: alternative boot operation, terminatio n between consecutive data blocks figure428 rev 1.0 / sep. 2009 106 e-nand a.f op istheenandclockfrequencythehostisusingfo rthereadoperation. followingisacalculationexample: csdvaluefortaacis0x26;thisisequalto1.5 msec; csdvaluefornsacis0; thehostfrequencyf op is10mhz n ac= 10x(1.5x10 3 x10x10 6 +0)=150,000clockcycles symbol min max unit n ac 2 10 * (taac * f op +100*nsac) a clockcycles n cc 8 clockcycles n cd 56 clockcycles n cp 74 clockcycles n cr 2 64 clockcycles n id 5 5 clockcycles n rc 8 clockcycles n sc 8 clockcycles n st 2 2 clockcycles n wr 2 clockcycles ba 50 ms bd 1 s 4.18 timing values rev 1.0 / sep. 2009 107 e-nand 12.0000.100 (3.000) b a 16.0000.100 (4.000) 3.0 x 5.0 min flat area 1 a1 corner index area 0.2000.050 +0.070 1.230-0.100 0.10 c 1 seating plane c 0.10 c pkg mechnical drowing rev 1.0 / sep. 2009 108 e-nand 14 3 12 11 10 9 8 7 6 5 4 3 2 1 2.00 0.500 0.500 a1 bal l mark 0.500 x 13 = 6.500 0.500 x 27 = 13.500 2.7500.100 a b dh j k l m n p t r v u w y aa ae ah ag 169 x ?0.300 0.050 ?0.15 m c a b 12.50 0.100 |
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