View ZIOL2202_7635836.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 1 of 90 data sheet rev. 2.2.1 / january 2012 ziol2xxx ic family io-link compliant hv line driver ic family
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 2 of 90 contents 1 the ziol2xxx ic family over view .......................................................................................6 2 electrical char acterist ics ..................................................................................................... .7 2.1. absolute maxi mum rati ngs ............................................................................................7 2.2. operating c onditi ons ......................................................................................................8 2.3. electrical pa rameters ......................................................................................................9 3 detailed de scripti on........................................................................................................... .15 3.1. block schem atic ............................................................................................................15 3.2. dual channel transceiv er.............................................................................................16 3.2.1. ic data path c onfigurat ion ......................................................................................16 3.2.2. transmitte r ..............................................................................................................20 3.2.3. receiv er ..................................................................................................................22 3.3. system c ontrol .............................................................................................................24 3.3.1. general ....................................................................................................................24 3.3.2. io-link master and device mode ............................................................................25 3.3.3. internal e xcepti ons ..................................................................................................25 3.3.4. io-link specific wake-up (w urq)..........................................................................25 3.3.5. ic self-protecti on ? lock mode ...............................................................................27 3.3.6. channel locking in ma ster/devic e mode ................................................................29 3.3.7. memory unit ............................................................................................................29 3.3.8. serial peripheral in terface ( spi) ..............................................................................31 3.3.9. register table / registers for ic configuration and monito ring...............................36 3.3.10. interrupt and ic lo ck mode cont rol.........................................................................46 3.3.11. die temperature measurem ent ...............................................................................54 3.4. smart power supply .....................................................................................................54 3.5. the power fail detector ...............................................................................................56 3.5.1. overvi ew..................................................................................................................56 3.5.2. line-fault de tector ..................................................................................................56 3.5.3. under-voltage detect or............................................................................................57 3.5.4. channel locking and inte rrupt gener ation ..............................................................57 3.5.5. downward com patibility ..........................................................................................57
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 3 of 90 3.6. dc/dc conver ter ..........................................................................................................57 3.6.1. principle of operation ..............................................................................................57 3.6.2. principle of operation ..............................................................................................58 3.6.3. dimensioning of exte rnal devi ces............................................................................59 3.6.4. pcb layout cons iderati ons .....................................................................................61 4 application in formation .......................................................................................................6 3 5 pin configuration, latch -up and esd pr otection ...............................................................68 5.1. pin configuration and latch-up cond itions ...................................................................68 5.2. esd-protect ion .............................................................................................................69 6 pack age........................................................................................................................ ......70 6.1. pin hardware configurat ions ........................................................................................70 6.2. pin diagr am ..................................................................................................................70 6.3. optimal pc b layout ......................................................................................................71 6.4. package out line ............................................................................................................72 6.5. device ma rking .............................................................................................................73 7 ordering in formati on........................................................................................................... 74 8 related docu ments ............................................................................................................75 9 glossary ....................................................................................................................... ......76 9.1. terms and abbreviations ..............................................................................................76 9.2. symbols used in th is data sheet ....................................................................................76 10 document revisi on history ................................................................................................78 appendix a ziol2xxx diagnosti c techni ques .....................................................................80 a.1. general re marks ..........................................................................................................80 a.2. overload counter behavior and peak register access................................................80 a.3. overload counter and lock reset me thods .................................................................84 appendix b ziol2xxx configurat ion techni ques.................................................................87 appendix c ziol2xxx line fa il dete ctor .............................................................................89
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 4 of 90 list of figures figure 2.1 max. total power dissipation ................................................................................................................7 figure 2.2 efficiency of the dc/dc converte r for vout=5v, c=10f and l=10h ............................................14 figure 3.1 functional block diagram of the ziol2xxx .........................................................................................15 figure 3.2 ziol24xx transceiver data path in principle ......................................................................................16 figure 3.3 ziol22xx transceiver data path in principle ......................................................................................17 figure 3.4 ziol21xx transceiver data path in principle ......................................................................................18 figure 3.5 ziol24xx in device and master mode application ..............................................................................21 figure 3.6 typical io-link device configuration with hs driver only ...................................................................24 figure 3.7 wake-up signal recognition ...............................................................................................................26 figure 3.8 the basic scheme of the ic self protection .......................................................................................28 figure 3.9 memory unit ............................................................................................................................... .......... 30 figure 3.10 general timing of a byte transfer .........................................................................................................32 figure 3.11 structure of spi accesses ...................................................................................................................33 figure 3.12 spi command structure ......................................................................................................................34 figure 3.13 spi timing ............................................................................................................................... ............ 36 figure 3.14 interrupt (int_l pin) and wake-up (wurq_l pin) signaling .............................................................47 figure 3.15 com channel lock control .................................................................................................................49 figure 3.16 aux channel lock control ..................................................................................................................50 figure 3.17 over-temperature lock control ..........................................................................................................51 figure 3.18 internal ic sensors and related overload and over-temperature detection circuits ........................53 figure 3.19 low voltage supply concept ...............................................................................................................55 figure 3.20 pfd working principle .........................................................................................................................56 figure 3.21 dc/dc converter in principle ..............................................................................................................58 figure 3.22 dc/dc converter output voltage as function of r1 (r2 = 10kohms) ..............................................60 figure 3.23 high frequency critical loops of dc/dc converter for pcb layout .......................................................61 figure 3.24 pcb layout of evaluation board as an example ..................................................................................62 figure 4.1 simplified application circuit with the ziol2xxx in device mode .......................................................63 figure 4.2 simplified application circuit with the ziol2xxx in master mode .......................................................64 figure 4.3 power line fail detection ....................................................................................................................65 figure 4.4 pcb layout recommendations ...........................................................................................................66 figure 6.1 pin diagram of the ziol2xxx ...............................................................................................................71 figure 6.2 package dimensions ...........................................................................................................................72 figure 6.3 top marking of the ziol2xxx ..............................................................................................................73 figure 9.1 register representation in principle (example) ..................................................................................77 figure 10.1 peak register access scenarios .........................................................................................................81 figure 10.2 overload counter behavior in pe rmanent over-current situations ....................................................82 figure 10.3 overload counter behavior in permanent over-temperature situations ...........................................83 figure 10.4 overload counter behavior in typical over-temperature situations ..................................................84 figure 10.5 partial reset of overload counter or the entire lock circuit ...............................................................85
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 5 of 90 figure 10.6 configuration checker report of the ziol2xxx application kit (example) .........................................87 list of tables table 1.1 ziol2xxx product matrix and product naming convention ..................................................................6 table 2.1 absolute maximum ratings ...................................................................................................................7 table 2.2 operating conditions .............................................................................................................................8 table 2.3 electrical characteristics .......................................................................................................................9 table 3.1 master-device-mode function table ...................................................................................................19 table 3.2 driver configurations ............................................................................................................................22 table 3.3 receiver configurations .......................................................................................................................23 table 3.4 sink mode configuration in detail .......................................................................................................24 table 3.5 example for building the shift byte ...................................................................................................34 table 3.6 valid address and length combinations ............................................................................................34 table 3.7 register table ............................................................................................................................... ....... 37 table 3.8 temperature sensor levels ................................................................................................................54 table 3.9 examples for the resistors r1 an d r2 using e96 resistor series ........................................................59 table 4.1 recommended external components .................................................................................................67 table 5.1 pin configuration and latch-up conditions ........................................................................................68 table 6.1 availability of pin interconnections ......................................................................................................70 table 6.2 package dimensions in mm ................................................................................................................72 table 10.1 abnormal power supply situations .....................................................................................................89
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 6 of 90 1 the ziol2xxx ic family overview zmdi provides a universal and io-link compatible cable driv er ic by issuing the ziol2401 integrated circuit. the ziol2401 is highly configurable and suitable for a wide ran ge of applications in process and factory automation. in order to fulfill the requirements of specific applicati ons stripped down versions of the ic were required. the ziol2xxx ic family is derived from the ziol2401 by modifi cation (elimination or disab ling) of certain functional building blocks. in this combination the following building blocks or functions are affected: ? the transceiver channels com and aux ? the availability of the integrated dc/dc converter ? the activation of a read-only data access via the spi interface this datasheet describes the ent ire ic family ziol2xxx. respective notes or footnotes describe the availability the above mentioned building blocks or functionality with respect to certain ic family members. table 1.1 shows an overview concerning the ziol2xxx ic family and the used naming convention. table 1.1 ziol2xxx product matrix and product naming convention ziol2xxx member transceiver channel dc/dc converter spi access remarks ziol2401 com + aux yes r/w base type - released ziol2201 com yes r/w released ziol2101 aux yes r/w 1) ziol2411 com + aux no r/w released ziol2211 com no r/w released ziol2111 aux no r/w 1) ziol2402 com + aux yes r 1) ZIOL2202 com yes r 1) ziol2102 aux yes r 1) ziol2412 com + aux no r 1) ziol2212 com no r 1) ziol2112 aux no r 1) 1) for future product releases, please c ontact zmdi's sales representative
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 7 of 90 2 electrical characteristics 2.1. absolute maximum ratings parameters apply in operation temperature range and without time limitations. table 2.1 absolute maximum ratings symbol parameter min max unit conditions v dd_hv supply voltage -0.3 40 v v hv voltage at hv pins -0.3 v dd_hv +0.3 v v lv voltage at lv pins -0.3 v dd_lv +0.3 v 2) v imp impulse voltage withstand 60 v according to iec 60947-5-2 v esd abs. esd test voltage 2k v according to hbm t s junction temperature 125 c 1) t a storage temperature -50 150 c p tot average total power dissipation 2.6 w integration period < 10ms 3) 1) average die-temperature. 2) exceptions are the di gital input pins (c interface) which tolerate 5v logic signals (refer to table 5.1 ). 3) the allowed total power dissipation depends on the in the pcb design achieved thermal resistance r th (package/ambient) and the ambient operation temperature as shown in figure 2.1 . in order to obtain optimal heat distribution (r th < 35k/w) certain pcb layout rules shall be applied. those rules are described in the application note for the used qfn package (refer to chapter 8, [4] ). figure 2.1 max. total power dissipation 0 0,5 1 1,5 2 2,5 3 -40-20 0 20406080 t amb /c p tot /w rth = 45k/w rth = 35k/w
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 8 of 90 2.2. operating conditions table 2.2 operating conditions symbol parameter min typ 1) max unit conditions v dd_hv supply voltage 8.0 24 36 v v in linear regulator input voltage 4. 75 36 v lr_in can be connected to v dd_hv or dc/dc output voltage. v dd_lv linear regulator output voltage 3.0 3.3 3.6 v voltage lr_out ? gnd pin i out linear regulator output current 10 ma lr_out provides supply current for external applications. 2) t startup startup timing @ v dd_hv = 8v 5 ms time for system start up including loading of configuration registers from eeprom t amb operating ambient tem perature -40 +85 c f osc internal oscillator frequency 4.5 5.5 mhz internal clock is not available externally. all digital circuit timing parameters of the ic are derived from the internal clock. 1) the mentioned typical values of ic prope rties are provided for information only. 2) while start-up (until the voltage at lr_out has reached 1v) the output current may be limited to 5ma.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 9 of 90 2.3. electrical parameters all parameter values are valid under oper ating conditions specified in chapter 2.2 if no other conditions are mentione d. table 2.3 electrical characteristics symbol parameter min typ 1) max unit conditions transmitter output stages (com 1 /aux 2 ) i dal_0 50 i dout_0 ma i dal_1 100 i dout_1 ma i dal_2 200 i dout_2 ma i dal_3 alarm level threshold corresponding to configurable output current limitation 2) dual driver mode 250 i dout_3 ma dual mode the active setting is defined in the configuration registers i mal_0 100 i mout_0 ma i mal_1 200 i mout_1 ma i mal_2 400 i mout_2 ma i mal_3 alarm level threshold corresponding to configurable output current limitation 2) tandem driver mode 500 i mout_3 ma tandem mode the active setting is defined in the configuration registers. i dout_0 56 95 ma i dout_1 112 180 ma i dout_2 224 330 ma i dout_3 configurable output current limit 2) dual driver mode 280 410 ma dual mode the active setting is defined in the configuration registers. i mout_0 112 180 ma i mout_1 224 360 ma i mout_2 448 660 ma i mout_3 configurable output current limit 2) tandem driver mode 560 820 ma tandem mode the active setting is defined in the configuration registers. sr 38 6 10 14 5) v/s referring to io-link spec.: 38,4kbaud (com2), sr 230 slew rate 3) 40 60 80 5) v/s referring to io-link spec.: 230.4kbaud (com3) t tlhdelaycom3 propagation delay l-h edge 250 ns time from lv l-h edge till hv edge begins to rise (com3 baud rate) t thldelaycom3 propagation delay h-l edge 250 ns time from lv h-l edge till hv edge begins to fall (com3 baud rate) 1 the com transmitter is only avail able inside the products ziol24xx/22xx 2 the aux transmitter is only availabl e inside the products ziol24xx/21xx
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 10 of 90 symbol parameter min typ 1) max unit conditions t tlhdelaycom2 propagation delay l-h edge 700 ns time from lv l-h edge till hv edge begins to rise (com2 baud rate) t thldelaycom2 propagation delay h-l edge 700 ns time from lv h-l edge till hv edge begins to fall (com2 baud rate) receiver input channels (com 3 /aux 4 ) v ih1 io-link specific threshold, high 10.75 12.75 v v il1 io-link specific threshold, low 8.75 10.75 v v ihyst1 io-link specific thresholds, hysteresis 1.5 2.5 v v ih2 ratiometric threshold, high 52 57 % ? v dd_hv v il2 ratiometric threshold, low 43 47.7 % ? v dd_hv v ihyst2 ratiometric thresholds, hysteresis 7 11.6 % ? v dd_hv r in input resistance 150 kohms c in input capacitance 20 pf t rdelay propagation delay without filtering 80 100 200 ns ns ns no filter within signal path. input edge with: >30v/s (com3) >5v/s (com2) >0.75v/s (com1) t frdelay propagation delay with analog filtering 750 850 950 ns @v dd_hv = 24v, input edge with: >30v/s (com3) t rpulse minimal propagated pulse width without filtering 25 ns t frpulse minimal propagated pulse width with analog filtering 1.1 s t digdelay additional propagation delay with digital filtering 180 440 ns f cut input filter ? cut off frequency (-3db) com and aux channel 100 250 khz filter characteristic: 1 st order i sink1 sink strength 1 2 2.5 3 ma line input voltage >5v i sink2 sink strength 2 5 6 7 ma according to io-link specification r pull configurable pull-up/pull-down resistor @ com_o/aux_o 100k 250k ohms 3 the com receiver is only availabl e inside the products ziol24xx/22xx 4 the aux receiver is only availabl e inside the products ziol24xx/21xx
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 11 of 90 symbol parameter min typ 1) max unit conditions wurq detection t wurql lower pulse width limit of signal evaluated as io-link wake-up 60 68 75 s refer to chapter 3.3.4 t wurqu upper pulse width limit of signal evaluated as io-link wake-up 85 94 109 s refer to chapter 3.3.4 dc/dc converter 5 v out output voltage range 6) 3 15 v @ v dd_hv > v out + 2v (step down function only) i load output load current 5 4) 50 ma current that flows to the application and the r-divider i pk over current limit for output transistor 240 ma averaged current over complete short at dcdc converter output f osc operating frequency 2.25 2.75 mhz v ref reference/feedback voltage 1.225 v at fb pin in steady state v out_line dc output line regulation 8 mv/v @v out =5v, i load = 5ma filter: c=10f, l=10h dc output load regulation mv/ma @vout=3.3v 0.7 1.4 v out_load @vout=15v 3.3 6.9 filter: c=10f, l=10h v out = 5v ripple of output voltage @ vdd_hv >= 24v 65 7) v ripple @ vdd_hv < 24v 25 7) mv pp filter: c=10f, l=10h v out = 5v t strt settling time after por is released 1 ms for c=10f, l=10h higher c may result in higher t strt t dly digital delay for dc_rdy signal 45 50 55 ms if enabled in configuration efficiency 8) % filter: c=10f, l=10h 5 the dc/dc converter is only available in side the products ziol2401/2402/2201/2202/2101/2102
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 12 of 90 symbol parameter min typ 1) max unit conditions microcontroller interface 9) v lih voltage range for input ?high? level 2.5 5.5 v @ v dd_lv = 3.6v, otherwise v lih-min = 0.7 ? v dd_lv v lil voltage range for input ?low? level -0.3 0.9 v @ v dd_lv = 3.0v, otherwise v lil-max = 0.3 ? v dd_lv i lih logic ?high? input current -1 1 a @ v lih = v dd_lv i lil logic ?low? input current @ pins without pull-up/pull-down resistors: int_l, wurq_l -1 1 a @ v lil = 0v i lih_pd logic ?high? input current -300 -150 a @ v lih = v dd_lv-max = 3.6v @ v lih = 5.5v, v dd_lv-max = 3.6v i lil_pd logic ?low? input current @ pins with pull- down resistors: tx_en/spi_clk, tx/mosi, aux_en, aux_tx, dc_rdy -1 1 a @ v lil = 0v, v dd_lv-max = 3.6v @ v lil = 0v, v dd_lv-max = 3.0v i lih_pu logic ?high? input current -1 1 a @ v lih-min = v dd_lv-max = 3.0v @ v lih-max = v dd_lv-max = 3.6v i lil_pu logic ?low? input current @ pins with pull- up resistors: rst_l, spi_en_l -150 250 a @ v lil = 0v, v dd_lv-max = 3.6v @ v lil = -0.3v, v dd_lv-max = 3.6v v lol logic ?high? output voltage 0 5 % ? v dd_lv @ i lil = 1ma v loh logic ?high? output voltage @ output pins: rx/miso, aux_rx 95 100 % ? v dd_lv @ i lih = -1ma internal current consumption 10) i vdd current into vdd 1.7 2.5 ma spi_en=3.3v i lr_in current into lr_in 2.2 3.4 ma spi_en=3.3v
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 13 of 90 symbol parameter min typ 1) max unit conditions 1) the mentioned typical values of ic properties are provided for information only and shall not be considered as statistical guaranteed mean values. typical values are not subject for measurement while the electric al test of each ic ? they are correct by design. 2) if the output current exceeds the configured current limit, the ic will raise an overload signal which causes up-counting of t he overload counter (if configured) and which definitely limits the output curr ent. however, the current limit will be performed a fter a certain settling time in order to ensure the configured slope of the output signal. 3) absolute edge rise and fall times are proportional to v dd_hv 4) a minimum of the output current must be provided by the app lication circuit. otherwise the dc/dc converter shall be unused by interconnecting the fb pin with the lr_out pin. the required voltage divider (refer to figure 3.21 ) may provide this current partly or in full. 5) slew-rate measured after settlement time of the output signal 6) configurable with an external voltage divider (refer to chapter 3.5 ) 7) the ripple on the output voltage depends significantly on both the external components and the pcb layout. reference pcb layouts are available from zmdi. the layout s used in the application kits are shown in figure 4.4 ; detailed layout data of the application kits a re availabl e from zmdi upon request. 8) the efficiency of the dc/dc converter is depending on the exte rnal components and the used pcb layout. moreover, there is an influence from several operati onal conditions which is illu strated in the diagram of figure 2.2 9) microcontroller interface pins are : rst_l, spi_en_l, in t_l, wurq_l, tx_en/spi_clk, tx/mosi, rx/miso, aux_en, aux_tx, aux_rx, dc_rdy 10) current consumption is measured by applying the maximum supply voltage at the supply pins vdd and lr_in (v vdd_hv =36v, v in =36v) and using a decoupling cap of 10 f between lr_out and ground. both vdd and both vss pins are interconnected, respectively. pins tx_en/spi_clk, aux_tx, tx_en, aux_en, pfd, com_i, aux_i are connected to ground.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 14 of 90 figure 2.2 efficiency of the dc/dc 6 converter for vout=5v, c=10f and l=10h 6 the dc/dc converter is only available in side the products ziol2401/2402/2201/2202/2101/2102
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 15 of 90 3 detailed description 3.1. block schematic figure 3.1 functional block diagram of the ziol2xxx lv interface hv interface en = function (building block) can be enabled/disabled by the configuration settings. = function (building block) can be configured/parameterized by the configuration settings. analog block digital block = building block functionality/availability depends on the ziol2xxx product definition, please refer to the ziol2xxx product matrix. aux analog filter pfd rst_l vdd int_l spi_en_l wurq_l internal supply lr_out sw fb dc_rdy aux_i aux_o tx_en/ spi_clk tx/ mosi rx/ miso com_o com_i aux_tx aux_en vss aux_rx en analog filter dual channel transceiver com lr_in en config register status register config eeprom spi digital filter digital filter system control osc en en en en dc / dc converter under-voltage and line-fail detector
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 16 of 90 3.2. dual channel transceiver 3.2.1. ic data path configuration the ziol2xxx ics contains one (ziol22 xx/21xx) or two (ziol24 xx) transceiver channel s. the channels inside the product versions with two channels can work ind ependently in the ?dual mode? or coordinated in ?tandem mode?. the data path of the zi ol24xx ics is illustrated in figure 3.2 . both channels, which are designed identically, are wi dely configurable. due to configurati on and the range of supported supply voltages the ics can be used in a broad field of applications. example applications can be level shifter for standard sensor applications or driver for resistive, capacitive or inductive loads. figure 3.2 ziol24xx transceiver data path in principle maximum driver capability of minimum 500m a can be achieved by combining both drivers. in this case the drivers work in parallel (tandem mode).
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 17 of 90 in order to gain optimal emc behavior the slew rate of the output signals of both drivers can be adjusted. the input threshold levels of the receiver can be set to ratiometric or to io-link conform levels, which enables the ic to be used in applications having a wide supply voltage range. the configuration of the transceiver can be changed during operation. a fter power-on this configuration is automatically loaded from the on-chip eeprom. driver and receiver are kept totally separated, so full duplex mode in data communication systems is supported. the ability to enable/disable the drivers output also enables applications in half duplex mode, where output and input are connected. having the i/o-pins separated also enables additional external input filtering. the com channel send and receive signals (tx_en, tx , rx) are multiplexed with the signals of the spi functional unit of the ic (spi_clk, mosi, miso) as shown in figure 3.2 . the spi unit is used for ic configuration and dia gnostic purposes (refer to chapter 3.3.8 ). as long the spi unit is active (spi_en_l = low), the send status of the com chann el is kept (for information refer to chapter 3.3.8 and figure 3.10 ). figure 3.3 ziol22xx transceiver data path in principle d e v i c e legend: af: analog filter (on/off configurable) cs: current sink (on/off/strength configurable) df: digital filter (on/off configurable) i1, i2: transmit/receive data inverter (on/off configurable) l: data latch, stores channel transmit status spi: serial peripheral interface analog block digital block af aux_i aux_o tx_en/ spi_clk tx/ mosi rx/ miso com_o com_i aux_tx aux_en aux_rx single channel transceiver com spi spi_en_l df i2 clk i1 d e v i c e df i2 i1 cs ziol22xx data path rst_l int_l wurq_l control mosi miso l l conf.reg[7][7:5] s0 s1 s2 s3 a b b b a b a a c en tx rx out in n.c. n.c. n.c. n.c.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 18 of 90 the (stripped down) ic versions ziol22xx/21xx contain only one channel. figure 3.3 and figure 3.4 show the data path of the ziol2 2xx versions and ziol21xx versions, respectively. the following chapters regarding details of the transmitter and receiver apply to ic versions with two channels (ziol24xx). the in the following described functionality applies to ic versions with one channel (ziol22xx/21xx) correspondingly. with the implicit understanding that one channel ic versions cannot perform tandem (master) mode operations or coordinated transceiver operations no exp licit statement in the followi ng chapters will reflect this. figure 3.4 ziol21xx transceiver data path in principle the master mode configuration flags master_m ode, en_follow_prim_ch and primary_master_ch located in the master_sens_ctrl c onfiguration register (refer to table 3.7 ) control the switches s0, s1, s2 and s3 ( figure 3.2 , figure 3.3 and figure 3.4 ) thus they control the actually used d ata path. in principle, the ziol2xxx ic family supports five dat a path types which are mentioned in table 3.1 . in case the master_mode flag is cleared (=0), the ic operates in device mode. fo r more information about the operation in device/master mode, please refer to chapter 3.2.2.1 .
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 19 of 90 table 3.1 master-device-mode function table data path configuration data path switch position t y p e global ic function master_sens _ctrl[7:5] [7] = master_mode [6] = en_follow_prim_ch [5] = primary_master_ch s 0 s 1 s 2 s 3 receiver available 1) rx/ miso state control remarks 0 device mode 0 x x a a a a com 2) aux push/ pull equivalent to ic rev a device mode 1 master mode, com = prim channel, aux enable not following prim-ch 1 0 0 b a a a com 2) aux push/ pull equivalent to ic rev a master mode 2 master mode, com = prim channel, aux enable is following prim-ch 1) 1 1 0 b b a a com 2) aux push/ pull saves one interconnection wire (aux_en) to c 3 master mode, aux = prim channel, com enable is following prim-ch 3) 1 1 1 a a b b 4 master mode, aux = prim channel, com is disabled 4) 1 0 1 a a b c aux push/ pull high-z if spi_en_l = high process (io- link) and service (spi) data separation ? spi pin bus wiring! 1) if aux_en is permanently wired to gnd, the total driver str ength can be controlled by toggling the master_sens_ctrl[6] bit (0: aux disabled using just com/ 1: aux enabled if com is enabled = double strength). ? switching between type 1 and 2 via spi access. 2) the logic value of the com receiver output (rx) is ava ilable if the spi communication is disabled (spi_en_l = 1). 3) driver strength is ?double? ? ?wake_up_mode?. the total driver strength can be decreased by switching to type 4 (single streng th). 4) driver strength is ?single?. the to tal driver strength can be increased by switching to type 3 (double strength)
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 20 of 90 3.2.2. transmitter 3.2.2.1. general functionality the ic versio ns ziol24xx consists of two 7 independent driver stages. each dr iver (com/aux) is configurable as regards the parameter ? output current limitation ? output slew rate ? driver function (push, pull, pull ups/downs) several modes of operation are supported ? as independent or as combined driver outputs. 3.2.2.2. modes of operation (io-link specific operation) operating b oth on-chip drivers indepe ndently or in parallel ensures the ic utilization in a wide range of applications. an example can be the different requirements of driver capability in master or device mode regarding the io-link specification (refer also to chapter 3.3.2 ). both modes are supported by the zio l2xxx ics. the active mode is defined in the configuration register [7] bit 7. t he chosen mode influences the ic?s driver behavior as well as the handling of overload exceptions. both input channels do not depend on the operational mode. in master mode 8 the data inputs (tx) of both driver s are connected internally. as regards their functionality both drivers work in parallel. therefore, the driver outputs have to be interconnected externally in master mode. in device mode both drivers are working independently. a respective current overload signal will be generated if at one or at both drivers the output cu rrent exceeds the set current limit fo r longer than the configured amount of time. figure 3.5 shows a simplified application circuit includi ng zi ol24xx ics in device and in master mode, respectively. although both drivers are cont rolled by the same ?tx? signal in ma ster mode, the driver strength can be influenced with the com_en and aux_en signal thus the resulting driver strength can be reduced in this mode. starting with rev b of the ic the master_mode flag (c onfiguration register master_sens_ctrl[7] replaces the formerly used control via an input pin. summarizing the above, the master_mode flag controls: ? the data path; it controls whether both channels use an individual or common tx signal ? the current sinks at the receiver?s inputs in the io-link sink mode (refer to table 3.4) for mo re information about the data path configuration of the ic in device an d in mode master, please refer to chapter 3.2.1 . 7 note: the ic versions ziol22xx/21xx have ju st one channel. with respect to those ic versions the statements concerning the exi stence of two channels shall be ignored or interpreted analogously. 8 not applicable for the ic versions ziol22xx/21xx
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 21 of 90 figure 3.5 ziol24xx in device and master mode application com aux bidirectional communication direct signalling com aux l+ l- ziol24xx ziol24xx device master aux_rx aux_en (wurq) com_en rx tx com_en tx rx aux_en aux_tx the illustration in figure 3.5 shows the principal way of using the z iol2xxx integrated circuit in master and device mode. figure 3.5 does not include all required electronic co mpon ents of the application circuit which are mentioned in chapter 4 ( figure 4.1 and figure 4.2 ). 3.2.2.3. configuration the com and aux drivers are built identically. their featur es can be configured in a wide range. the behavior of the output stages can be set to push, pull or push/pu ll. current limitation and the overload timing can be set individually. in order to improve the emc system behavior the slew rate of the output signal is controlled and can be set according to the needs of the application. the following table gives an overview of the possible configurations for the com and aux driver in master and device mode, respectively.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 22 of 90 table 3.2 driver configurations parameter config.-register reg.- addr. bit- field ranges & coding unit remarks 1) com and aux driver output current limitation com_param, aux_param 2 4 4:2 0b000: 50 0b010: 100 0b100: 200 0b110: 250 0bxx1: limitation off 2) ma ma ma ma ic in device mode: both drivers work independently combined driver output current limitation com_param, aux_param 2 4 4:2 0b000: 100 0b010: 200 0b100: 400 0b110: 500 0bxx1: limitation off 2) ma ma ma ma ic in master mode: both drivers work in parallel both drivers shall be set to identical driver capability. slew rate control com_ctrl, aux_ctrl 1 3 4:3 0b00: 10 0b10: 60 0b01: slow control off 0b11: fast control off v/s v/s limitation of maximal edge steepness. limitation turned off! limitation turned off! output characteristic com_ctrl, aux_ctrl 1 3 1:0 0b00: off 0b01: pull 0b10: push 0b11: push+pull overload time base ? com, aux com_mon_ctrl, aux_mon_ctrl 11 13 6:5 0b00: 0.2 0b01: 1000 0b10: 8000 0b11: 16000 s defines the clock frequency for com/aux overload counters overload counter compare value ? com, aux com_assert_time, aux_assert_time 10 12 7:0 byte if overload counter value equals compare value an overload will be asserted pull up/down enable ? com, aux com_param, aux_param 2 4 6:5 bit 6: pull-up bit 5: pull-down enables resistor of typical 150kohms 1) for a summary of all configuration registers, please refer to table 3.7 . 2) not recommended due to chance of overheating 3.2.3. receiver 3.2.3.1. general functionality in prin ciple, the ziol2xxx ic family has two 9 identical input channels with a configurable feature set. the input threshold levels can be set ratiometric or absolute. the absolute values are compatible with definition of type 1 digital inputs in iec61131-2 and conform to t he io-link specification. the ratiometric levels 10 are proportional to the hv power supply voltage. the ratiom etric level configuration allows the i nput channels to function down to a 9 note: the ic versions ziol22xx/21xx have only one receiver. 10 note: ripple on the supply voltage may have influence to the tr ip-point of the input stage. another influence to be considered is that an enabled analog input filter is reducing the ripple on the on the received signal.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 23 of 90 supply voltage of 8v. for each input channel an analog and a digital filter are implemented, which can separately be enabled. 3.2.3.2. configuration the followi ng table gives an overview of the possibl e configurations for the com and aux input channels. table 3.3 receiver configurations parameter config.- register reg.- addr. bit- field setting / range unit remarks 1) threshold level for com and aux com_ctrl, aux_ctrl 1 3 5 0b0: absolute 0b1: ratiometric absolute = io-link compliant thresholds analogue filter com_ctrl, aux_ctrl 1 3 2 0b0: disabled 0b1: enabled digital filter com_ctrl, aux_ctrl 1 3 7 0b0: disabled 0b1: enabled i sink , sink strength com_param, aux_param 2 4 7 0b0: 2 ? 3 0b1: 5 ? 7 ma sink mode com_param, aux_param 2 4 1:0 0b00: off 0b01: io-link 0b10: follow driver 0b11: on following driver: if driver is enabled then sink = off if driver is disabled then sink = on 1) for a summary of all configuration registers, please refer to table 3.7 . 3.2.3.3. sink modes the io-lin k standard defines a possible configuration option, in which the device drives the signal line only with a high side driver thus the logic low level will be gene rated with a current sink on the master side ( figure 3.6 ). the ziol2xxx support s the current sinks in different modes on master side (for details refer to table 3.4 ).
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 24 of 90 figure 3.6 typical io-link device c onfiguration with hs driver only table 3.4 sink mode configuration in detail register[2][1:0] register[4][1:0] mode sink enabling remark 00 n.a. sink steady disabled off device mode 1) sink steady disabled 01 master mode 2) sink enabled if: ? tx_en/spi_clk = low (com) ? aux_en = low (aux) typical application mode for the io-link channel: device : no sink master : sink enabled contrary to the corresponding driver enable signal 10 n.a. sink enabled if: ? tx_en/spi_clk = low (com) ? aux_en = low (aux) enabling contrary to the driver enable signal; sink is only enabled while the driver is disabled. (helps to reduce the system?s power dissipation) 11 n.a. steady enabled on 1) master_mode flag (configuration register master_sens_ctrl[7] is cleared (=0). 2) master_mode flag (configuration regist er master_sens_ctrl[7] is set (=1). 3.3. system control 3.3.1. general the system control provides device configuration, status signaling and spi data transfer functionality. implemented are several register area s which contain configuration data and wh ich provide status information. in order to gain read/write access to these register areas, the standard se rial peripheral interface (spi) is
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 25 of 90 impleme nted. since the pin count of the package is limit ed to 24 pins, the spi specific pins (clk, mosi, and miso) are multiplexed with io-pins of the com driver. a dedicated pin spi_en_l is used to switch between spi (logic low) and com transceiver functionality (logic high) . the low voltage (lv) interface works with 3.3v supply voltage (refer to figure 3.1 ). the lv outputs drive 3.3v as high lev el, the inputs are 5v tolerant. if the spi communication channel of the ziol2xxx ics is active (spi_en_l = low) , the status of the com channel drivers is kept. this means while spi_en_l = low the output driver status (driving low, driving high, or high-z) is the same as defined by the pins tx_en/spi_clk and tx /mosi at the point of time of the spi_en_l high-low transition. the aux channel is not affected by the activity of the spi communication. for more information, please refer to chapter 3.3.8 and figure 3.10 . 3.3.2. io-link master 11 and device mode the ic architecture is suitable for both io-link applicati on cases, the physical layer transceiver at an io-link master port and at an io-link device port. in the first case the ic shall operate in its ?master mode? which is the case if configuration register [7] bit 7 is set (=1). if the ic shall operate in ?device mode ?, configuration register [7] bit 7 shall be cleared (=0). details regarding the cont rol of both driver channels are described in chapter 3.2.1 , 3.2.2.2 and 3.2.3.3 . the io-li nk specific wurq detection (detection of an io-link master?s wake-up request, refer to io-link communication specification ? chapter 8 , [2] ) works only in device mode. 3.3.3. internal exceptions depending on the ic configuration the ziol2xxx can detect several critical situations and rise internal exceptions accordingly. also depending on the ic configuration an occurred internal exception can be indicated externally by changing the logic level of the int-l pin to ?low?. the si tuations that cause an inter nal exception are channel locks (channel driver protection), detected io-link specific wa ke-up pulses and several issues concerning the internal eeprom as described in chapter 3.3.10. 3.3.4. io-link specific wake-up (wurq) in device mode the ic can detect the io-link specific wake-up request (wurq) of the io-link master and can therefore help to save resources in the microcontroller of io-link device. as regards the io-link specific ?wake- up (wurq)? specification, please refer to the io-lin k communication specification issued by the io-link consortium (refer to chapter 8 , [2] ). the wurq can be detected on the com or on the aux channel. the chosen channel is defined in a configuration register (irq_w urq_ctrl, refer to chapter 3.3.9 ). in orde r to establish an io-link specific communication, the master will generate the wurq event. in this case the master overdrives the devices out put level for a determined period. the ziol2xxx can detect that event which physically occurs in two ways: ? a current overload in the drivers output for a certain period ? a contradiction of the tx and rx lin es of the device for a certain period 11 not applicable for the ic versions ziol22xx/21xx.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 26 of 90 the ic configuration register (i rq_wurq_ctrl, re fer to chapter 3.3.9 ) defines if the ?overload? or the ?co ntradiction? or both events shall be chosen for the wurq detection. both ways of detection can be enabled independently. if at least one of both events appears for a sp ecific time, the incident will be regarded as wurq request from master side and the ic will generate an internal exception (issue an interrupt) in order to signal this to the interconnected c. besides the configurable signaling on the int_l pin (refer to chapter 3.3.10.1 ) this spe cial exception will be displayed on the therefore dedicated wurq_l pin. details of the signaling via the wurq_l and/or the int_l pin and the pin driver confi guration of the wurq_l pin can be defined in the configuration registers which are described in detail in chapter 3.3.9 . the logi c level of the wurq_l pin (a wake-up causes l ogic low) or the st ored wurq event w ill be reset as soon as the drivers direction is set to input (tx_en=0), which equals the wurq acknowledge from the io-link device side. the on logic level based wurq detection works only for level-changes which are driven by the master. that means a wurq will not be detected if a level change has been initiated by the device itself, even if the signal timing is equivalent to a wurq event. this prevents the in sio mode operating io-link device to misinterpret the situation caused for instance by capacitive loads. if the ziol2xxx operates in master mode (physical interface for io-link master port) and a wake-up pulse (wurq) shall be issued, the c has to control the required driver strength by activating both channels (via com_en and aux_en, refer to figure 3.5 ) and has to provide the correct timing . figure 3.7 wake-up signal recognition t wurql 0 68 75 80 85 94 s -10% +10% 60 110 accepted wake-up pulse width range if osc runs at lowest possible frequency accepted pulse width range if osc runs at highest possible frequency overdriven output overdriven output t wurqu accepted wake-up pulse width range (device) -10% +10% tolerance range due tolerant osc frequency - 6 / + 25 clocks min: wake-up pulse width max: wake-up pulse width the wurq pulse recognition of the ziol2xxx in device m ode is ? in contrast to that ? based on a time base derived from the internal oscillator (osc). therefore t he as wurq recognized pulse width range of an received wake-up signal is dependent on the frequency toleranc e of the internal oscillator as illustrated in figure 3.7 . a wa ke-up signal (pulse width according to the io-link communication specification, refer to chapter 8 , [2] ) shall have a pulse width between 75s and 85 s (variation 10s). the ziol2xxx wake -up signal detection will always recognize such a signal securely considering a frequency tolerance of the internal oscillator of 10% (refer to parameter f osc in table 2.3 ).
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 27 of 90 3.3.5. ic self-protection ? lock mode in order to prevent serious ic damage due to overloaded or overheated driver transistors, the ic has a build-in protection mechanism. if a critical situation occurs for a certain configurable time, the ic can protect itself in transferring its control in a special mode, called lock mode, in which the driver of the related channel is turned-off in case of over-current, or in case of over-temperature the dr ivers of both channels are turned-off, respectively. figure 3.8 shows the basic scheme of the ic self protection. in prin ciple, this scheme is five times implemented in order to tread: ? over-current situations separately at the high side and at the low side switch of the com channel as described in figure 3.15 ? over-current situations separately at the high side and at the low side switch of the aux channel as described in figure 3.16 ? over-temperature situations of the silicon die as described in figure 3.17 in case of an over-curre nt or over-t emperature situation occurs (in the fo llowing called overload) the related over- current/over-temperature counter (overload counter) will co unt up. since the overload counter counts down to zero in case of no overload is existent, the circuit perform s an integrator function. this integrator function makes sure that overloads which temporarily occur are not accumulated thus will no t lead to an unwanted driver locks. if the overload counter has reached the (in the related c onfiguration register) defined maximum value, the ic will generate an internal exception. this exception will lock the associated channel or both channels in case of an over-temperature situation. the ?assert time? (refer to figure 3.8 ) which is the elapsed time in until reaching the config ured maximum of the overload counter depends on the used clock period for the overload counter. this clock period can be defined separately for the lock control circuit of each channel ( figure 3.15 , figure 3.16 ) and the temperature lo ck control circuit ( figure 3.17 ) in the associated configuration register. to ea ch overload counter is a peak register associated. the value of the overload counters can not be retrieved via the spi port. however, the value of the overload counter will be copied in the related peak register if the value of the overload counter is greater than the value of the peak register. the peak registers can be read via the spi port. the content of the peak register will be cleared after each read access. however, within the next cycle of the ic control circuit the peak register will be set to the over load counter value again if this value is greater than zero. the above described peak register update is only performed if an overload situation is present. in case of overload situation the peak register is an important instrument to perform an ic diagnostic. for more information about techniques to operate the peak, please refer to appendix a . a due to an overload raised internal exception will cause in ca se of over-current a lock of the related channel or a lock of both channels in case of a over-temperature situation. there are three signals (displayed in status register[20] which indicate the lock activator. the other five bits of this status register indicate what ic sensor has detected an over-current or if the configured maximum of the die temperature has been exceeded.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 28 of 90 figure 3.8 the basic scheme of the ic self protection any internal exception will be stored in status register [18]. this status register will be cleared by reading the register but the appr opriated bit will be set again (within the next cycle of the ic control circuit) if an exception is still present. a lock can be reset by using the build-in and configurable lock counter (defined in the associated configuration registers). as shown in figure 3.8 the lock reset will be performed when t he lock time has be en elapsed. the lock cou nter is using the same clock as the associated over load counter(s). alternativel y a lock can be reset by performing an write access to status re gister[16] (for more details refer to appendix a ).
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 29 of 90 dep ending on the ic configuration the any exception or stored exception can cause the int_l pin to logic low. as shown in figure 3.8 int_l can follow the state signals (internal exc eption s) or the stored exception which is also depending on the ic configuration. 3.3.6. channel locking in master/device mode there are three independent lock mechanisms implemented. for each channel (com and aux) a separate lock can be generated if an over-current at t he high side or low side switch has occurr ed. therefore it is implied that for the considered switch a current limit had been configured. the third lock mechanism which is affecting both channels is related to over-temperature situations. as regards the ic operation as io-link master or device phy (master/device mode, refer to chapter 3.3.2 ) the lock mechani sms of both channels are really sepa rated or coordinated as following described: master 12 mode (com and aux driver work in parallel ? tandem mode): ? assumed that both channels (com and au x) are enabled and the configuration flag both_channel_lock (register[14]) is set (=1), both hs or both ls driver of both channels need to be overloaded simultaneously for longer as a configured ti me in order to generate an ic-internal overload exception which is indicated at the int_l pin (logic low). ? in the case the ic works in tandem mode and the configuration flag both_channel_lock (register 14) is set (=1), but only one of the channels (com or aux) is enabled, the protection of the enabled channel is performed analogous to the device mode. ? if single hs or a single ls driver is disabled, t hen its overload signal is not needed to create a general overload signal, in that case just the other (enabled) hs or ls driver can gener ate the overload exception. ? if the die temperature exceeds the configured limit thus a temperature overload exception is detected, the ic locks both channels and signals and according to t he ic?s configuration an interrupt can be signaled at the int_l pin. device mode: ? any single overloaded hs or ls driver of the co m or aux channel leads to a lock and an interrupt signaling (int_l pin) according to the configuration of the ic. ? if the die temperature exceeds the configured limit thus a temperature overload exception is detected, the ic locks both driver channels and signals and according to the ic?s configuration an interrupt is signaled at the int_l pin. ? if both drivers are configured parallel, t he interrupt behavior equals the master mode the lock mode is associated with ic-internal exceptions that are signaled to the interconnected c as an interrupt. the details for building and clearing an exception are described in the chapter 3.3.10 which deals with the interrupt han dling and lock mode operation. 3.3.7. memory unit the memory unit of the ic provides several ic confi guration options. those configuration options define the properties of the ics driver channels and define the ic monitoring and protection functions with respect to the over-current and over-t emperature handling. 12 not applicable for the ic versions ziol22xx/21xx
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 30 of 90 the currently applied configuration data of the ic is stored in the configuration-register area which is implemented as a register file. the configurat ion-register area can be uploaded via spi command into an on-chip eeprom for non-volatile storage. while power-on-reset or also via spi command the eeprom content will be downloaded to the configuration-register area. besides data for ic configuration the ic has certain status regist ers that can be used to monitor the internal status of the ic. the status registers reflect the ic status as re gards the occurrence of different driver channel overload situations and their duration. mor eover, four alert phases (green, yellow, orange and red) indicate the die temperature of the ic and in this combination the die te mperature margin prior a ther mal shut down of certain ic building blocks. in principle, status registers are read-onl y registers. some status registers are reset by reading the register?s value. furthermore, a write access to some status registers will cause certain control actions (for more information refer to table 3.7 ). the read/write access to the ics memory unit is provided by an spi interface (refer to chapter 3.3.8 ). in order to acce ss a certain register or range of consecutive regist ers (block access) an 8-bit-address has to be applied which consists of segment address (2bits) and register address (6 bits) as illustrated in figure 3.9 . figure 3.9 memory unit status register segment 0 segment 1 register file eeprom address config- register 0 15 16 non-volatile configuration data 26 reserved segment 2 and 3 must not be used upload download memory block boundaries which cannot be exceeded while bock accesses ee memory control valid-flag 31 in case of a collapsing supply voltage while writing data into the eeprom, the eepr om data shall be suspected to be corrupt. there is an additional build-in security featur e to indicate this situation and to avoid that corrupt eeprom data is used for the ic configuration. in this combination a non-volatile flag (one bit eeprom) is used to indicate possibly not valid (corrupt) eeprom data. this flag which is called valid-flag is set if the data are valid or is cleared if the data are suspected to be corrupt. as shown in figure 3.14 corrupt eeprom data or any other eeprom problems can cause an internal exception. the above mentioned feature is us ing the following procedure while performing an eeprom write access: 1. clearing the valid-flag.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 31 of 90 2. write access to the eeprom. this is the critical step which can lead to corrupt dat a if interrupted at certain points in time. since the valid-flag is cleared the ic ca n detect this and make sure that no corrupt data are going to be used unintentionally. 3. set the valid-flag. from now on the data are declared as valid. if the power supply of the ic collapse s while writing to the eeprom or the write access is interrupted by any other reason, the ic can detect this while power-up due to the cleared valid-flag and can an d block the eeprom data against further use. ju st in case the ic has detected possibl y corrupt eeprom data the configuration registers will be load with default values which are e qual to the initial state (reset values) mentioned in table 3.7 . 3.3.7.1. eeprom error correction features the phys ical memory array of the eeprom contains 16 word s of 13 bits. in addition to the eight ?real? data bits there are five parity bits which are used as error correction code (ecc). in case one of the data bits changes its information an automatic singl e-error correction will be done. thus the data word (read by the ic system control) is still correct if this one-bit-error occurs. in order to si gnal this incident the exception ?eeprom-error? is generated (stored in bit 4 of the status register[18]). if a two-bit-error occurs (two bits of the data word are wrong) the ecc cannot correct the memory failure. this means the in such a situation read data is corrupt. in order to signal this non-recoverable memory failure the exception ?eeprom_2_error? is generated (sto red in bit 3 of the status register[18]). in summary the ecc features of t he eeprom allow to recognize problems (single bit errors) of the eeprom (eeprom_error exception) without jeopardizing the entire system application. only for the case that there are multiple-bit-errors, which are signaled with the ?e eprom_2_error? exception, it is recommended to stop the application and maintain the application circuit. 3.3.8. serial peripheral interface (spi) 3.3.8.1. spi features the p urpose of the spi interface is to provide access to the memory unit of the ic. within communication pauses of the transceiver channels the spi can be used to retrie ve diagnostic data from the ic and/or to reconfigure the ic, respectively. an active spi co mmunication causes that the com communication channel, which shares its control pins with the spi interface, cannot change its output value and output status and cannot forward received signals for exactly the period spi_en_l is low (refer to figure 3.10 ).
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 32 of 90 figure 3.10 general timing of a byte transfer spi feature summary: ? the interface works in spi-slave mode only ? the timing follows the scheme in figure 3.10 which defines ? clock polarity cpol = 1 (clock is idle high) ? clock phase cpha = 1 (data captured with 2 nd clock edge after spi_en_l went low; data are read on clock?s rising edge and data are changed on a falling edge) ? maximum clock frequency of the spi _clk shall not exceed 4 mhz for accessing the on-chip eeprom and 10 mhz for other spi accesses ? spi clock duty cycle: 40?60% ? msb will be transmitted first ? if access exceeds last byte, a wrap will not happen ? t he last byte will be written correctly, rest will be disregarded ? block write (access to more than one address location) is only supported for the configuration-register area but not for the eeprom area. ? block read is supported for both the eeprom and configuration-register area. ? during enabling the spi (spi_en_l = low ) the input lines of the com driver are latched, so the com driver does not change its output state while spi is enabled. the spi telegram structure can be divid ed into three types of spi accesses: ? read: read access to register file or eeprom, block access possible
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 33 of 90 ? write 13 : write access to register file (if applicable) or eeprom, block access only supported with the access to register file ? command: commands to achieve an ic (soft-)reset or up- or download of configuration data figure 3.11 illustrates the structure of support ed spi acce sses. the in this figure illustrated write access works only with the ic versions ziol2xx1 figure 3.11 structure of spi accesses 3.3.8.2. spi access details the timin g of the three spi access types is illustrated in figure 3.13 . as shown in this figure the 1 st byte, which is called destination byte, is composed out of the segment add ress (bit 7:6) and the r egister address (bit 5:0). a command is always using the address 0xff which is a not physically implemented memory location within the ic memory unit. 13 note: ic versions ziol2xx2 do not allow any write access.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 34 of 90 the read a nd write 14 access is defined in the value of bit 7 (0=write; 1=read) of the 2 nd byte which is called the shift byte. bit 6:0 represent the repeat count. this va lue defines the number of additional consecutive bytes to be accessed. in case of a write access the shift byte fo llowing bytes are the actual data to be written into the memory location(s). table 3.5 illustrates the building of the sh ift byte in using an example. table 3.5 example for building the shift byte number of bytes to be accessed shift byte value in case of a write access shift byte value in case of a read access 1 0000 0000 1000 0000 2 0000 0001 1000 0001 3 0000 0010 1000 0010 ? ? ? 16 0000 1111 1000 1111 if the transferred data stream of one telegram exceeds the border line of the chosen memory block, all following accesses will be disregarded. no wrap will happen! for more details refer to table 3.6 . table 3.6 valid address and length combinations segment address length = shift[6:0] comment 00 0000 ? 00 1111 000 0000?000 1111 ? 000 0000?000 0000 configuration-register block 00 01 0000 ? 01 1001 01 1111 000 0000?000 1111 ? 000 0000?000 0101 000 0000?000 0000 status register block although status registers can be accessed up to address 31 the useful range is only up to address 25 01 00 0000 ? 00 1110 000 0000 ? 000 0000 eeprom is directly accessi ble via spi but there is no block operation allowed figure 3.12 spi command structure 14 note: ic versions ziol2xx2 do not allow any write access.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 35 of 90 the structure of an spi command is shown in figure 3.12 . there are three commands implemented which are: ? mem_download code: 0x01 description: if the eeprom data is valid (valid-flag = 1 ? data is not corrupt) the mem_download copies the eeprom data into the configuration register s. if the data are suspected to be corrupt (valid-flag = 0), the eeprom data are not downloaded and an interrupt (int_l pin) will be asserted. ? mem_upload code: 0x02 description: the command copies the entire configurati on register data into the eeprom memory. the command execution starts with clearing the valid-flag and then with reading the c onfiguration registers and writing the data into the eeprom. at the end of cycle the valid-flag is set to 1. ? soft_reset code: 0x07 description : the command execution generates a reset for the entire ic. this reset occurs asynchronously with reference to the system clock bu t is released synchronously. when this spi command is being executed, the system is hold in the reset st ate for about 2s. the system reset state is indicated with active low on the int_l pin.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 36 of 90 figure 3.13 spi timing 15 3.3.9. register table / registers for ic configuration and monitoring the following table 3.7 shows a summary of the configurat io n- and status registers of the ziol2xxx . the address space from address 0 to 15 is implemented in both the register file area and the eeprom area. registers with addresses great er than 15 (status registers) are implem ented in the register file area only. 15 note: ic versions ziol2xx2 do not allow any write access.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 37 of 90 as regards the access type to a particular register the following four types have been implemented: 1. r/w normal read/write 16 2. r read only 3. r/rst read only, clear by read 4. w/pulse writing to such type of registers causes a partial reset of certain ic functions which correspond to the assigned bit of the write ac cessed register; reading is possible but will return no useful information in order to illustrate for in stance the w/pulse type a writ e access to status regist er mon_rst_lock_wurq shall be explained. the bits of this register are assigned to ? the power fail event (bit 4) and ? the io-link specific wake-up request event (bit 3) and ? the com/aux driver over-cur rent event (bit 2 and 1) and ? the over-temperature event (bit 0). writing the value 0x08 (mon_rst_wurq = 1) to the register would cause a reset of t he previously detected and stored wake-up request. in doing so the to the ic inte rconnected c acknowledges the occurred wake-up request thus the ic is ready to detect the next wake-up request. table 3.7 register table reg.-name addr. bit-field bit reset- value r/w comment reference configuration register irq_enable 0 7:0 255 r/w figure 3.14 0 irq_en_power_fail 7 1 r/w power fail interrupt enable added in rev b 0 irq_en_wurq 6 1 r/w wurq interrupt enable 0 irq_en_valid_flag_err 5 1 r/w valid-flag error interrupt enable 0 irq_en_eeprom_err 4 1 r/w single bit error interrupt enable 0 irq_en_eeprom2_err 3 1 r/w multiple bit error interrupt enable 16 note: ic versions ziol2xx2 do not allow any write access.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 38 of 90 reg.-name addr. bit-field bit reset- value r/w comment reference 0 irq_en_lock_aux 2 1 r/w interrupt enable for over-load lock of aux line driver 0 irq_en_lock_com 1 1 r/w interrupt enable for over-load lock of com line driver 0 irq_en_lock_ovt 0 1 r/w interrupt enable for over-temperature lock of both, aux and com, line drivers com_ctrl 1 7:0 0 r/w iolink-control- register 1 com_dig_filter 7 0 r/w enable digital rx- filter 1 com_inv_send 6 0 r/w invert receive and send (implemented in digital part) 1 com_ratio 5 0 r/w disables the receiver io-link levels and enables ratiometric 1 com_com3 4 0 r/w com3-mode (slope- control), 0: com2 1: com3 1 com_noedge 3 0 r/w disables edge control 1 com_filter 2 0 r/w filter-enable 0=off / 1 = on 1 com_ls_on 1 0 r/w lowside-driver 0=off / 1=on 1 com_hs_on 0 0 r/w highside-driver 0=off / 1=on com_param 2 7:0 0 r/w iolink-control- parameters 2 com_sink_strength 7 0 r/w sink_strength 2 com_pullup_en 6 0 r/w pull-up enable for com-channel
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 39 of 90 reg.-name addr. bit-field bit reset- value r/w comment reference 2 com_pulldown_en 5 0 r/w pull-down enable for com-channel 2 com_culi 4:3 0 r/w current limit 2 com_noculi 2 0 r/w current-limiting disabled 2 com_sink_mode 1:0 0 r/w sink-mode aux_ctrl 3 7:0 0 r/w iolink-control- register 3 aux_dig_filter 7 0 r/w digital rx-filter 3 aux_inv_send 6 0 r/w invert receive and send ( implemented in digital part) 3 aux_ratio 5 0 r/w disables the receiver io-link levels and enables ratiometric 3 aux_com3 4 0 r/w com3-mode (slope- control) 3 aux_noedge 3 0 r/w disables edge control 3 aux_filter 2 0 r/w filter-enable 0=off / 1 = on 3 aux_ls_on 1 0 r/w lowside-driver 0=off / 1=on 3 aux_hs_on 0 0 r/w highside-driver 0=off / 1=on aux_param 4 7:0 0 r/w iolink-control- parameters 4 aux_sink_strength 7 0 r/w sink strength 4 aux_pullup_en 6 0 r/w pull-up enable for aux-channel
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 40 of 90 reg.-name addr. bit-field bit reset- value r/w comment reference 4 aux_pulldown_en 5 0 r/w pull-down enable for aux-channel 4 aux_culi 4:3 0 r/w current limit 4 aux_noculi 2 0 r/w current-limiting disabled 4 aux_sink_mode 1:0 0 r/w sink-mode ovt_lock_time 5 7:0 200 r/w over-temperature: time until lock is released figure 3.17 com_lock_time 6 7:0 100 r/w overload: time until lock is released figure 3.15 figure 3.16 master_sens_ctrl 7 7:0 1 r/w over-temperature figure 3.18 7 master_mode 7 0 r/w master mode enabled, influences the data path and the receiver?s current sinks in io-link mode added in rev b 7 en_follow_prim_ch 6 0 r/w the secondary channel: 0 = uses a separate enable signal 1 = uses the enable of the prim. ch. added in rev b 7 primary_master_ch 5 0 r/w defines the primary channel: 0 = com 1 = aux added in rev b 7 reserved 4 0 r/w reserved 7 ovt_red 3 0 r/w ovt level set to ?red? 7 ovt_orange 2 0 r/w ovt level set to ?orange? 7 ovt_yellow 1 0 r/w ovt level set to ?yellow?
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 41 of 90 reg.-name addr. bit-field bit reset- value r/w comment reference 7 ovt_green 0 1 r/w ovt level set to ?green? ovt_assert_time 8 7:0 100 r/w over-temperature: time until lock is asserted figure 3.17 ovt_pfd_ctrl 9 6:0 15 r/w ovt and power-fail control figure 3.17 9 line_fault_en 6 0 r/w enables line-fault (lf) detection added in rev b 9 under_voltage_en 5 0 r/w enables under- voltage (uv) detection added in rev b 9 ovt_tbase 4:3 1 r/w over-temperature: time base 9 ovt_lock_time_rst 2 1 r/w over-temperature: reset lock (also) time based 9 ovt_lock_en 1 1 r/w over-temperature: enable lock 9 ovt_en 0 1 r/w over-temperature: enable ovt- measurement and control com_assert_time 10 7:0 50 r/w com-overload: time until lock is asserted figure 3.15 com_mon_ctrl 11 6:0 63 r/w figure 3.15 11 com_ovl_tbase 6:5 1 r/w com-overload: time base 11 com_lock_time_rst 4 1 r/w com-overload: reset lock (also) time based 11 com_hs_lock_en 3 1 r/w com-overload: enable highside-lock 11 com_ls_lock_en 2 1 r/w com-overload: enable lowside-lock
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 42 of 90 reg.-name addr. bit-field bit reset- value r/w comment reference 11 com_ovl_hs_en 1 1 r/w com-overload: enable highside- control, to be set if wake-up shell be detected via over- current activity 11 com_ovl_ls_en 0 1 r/w com-overload: enable lowside- control, to be set if wake-up shell be detected via over- current activity aux_assert_time 12 7:0 50 r/w aux-overload: time until lock is asserted figure 3.17 aux_mon_ctrl 13 6:0 63 r/w figure 3.17 13 aux_ovl_tbase 6:5 1 r/w aux-overload: time base 13 aux_lock_time_rst 4 1 r/w aux-overload: reset lock (also) time based 13 aux_hs_lock_en 3 1 r/w aux-overload: enable highside-lock 13 aux_ls_lock_en 2 1 r/w aux-overload: enable lowside-lock 13 aux_ovl_hs_en 1 1 r/w aux-overload: enable highside- control, to be set if wake-up shell be detected via over- current activity 13 aux_ovl_ls_en 0 1 r/w aux-overload: enable lowside- control, to be set if wake-up shell be detected via over- current activity irq_wurq_ctrl 14 7:0 35 r/w figure 3.14 14 irq_pad_mode 7 0 r/w irq_pad_mode: 0 = open-drain / 1 = push-pull
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 43 of 90 reg.-name addr. bit-field bit reset- value r/w comment reference 14 wurq_pad_mode 6 0 r/w wurq_pad_mode: 0 = open-drain / 1 = push-pull 14 dcdc_ready_delay 5 1 r/w dcdc-ready-delay- enable / 0 = no delay / 1 = delay 50 ms 14 both_channel_lock 4 0 r/w lock only, when both channel are in ovl- alarm recommended to be set (=1) in tandem mode 14 irq_noreg 3 0 r/w 0 = irq-port follows state-reg / 1 = irq follows state-signals 14 wurqsource 2 0 r/w source for wurq- detection 0 = com / 1 = aux 14 wurqdetect_current 1 1 r/w wurq detection on current (overload) 14 wurqdetect_lvl 0 1 r/w wurq detection on levels (can be combined with current) aux_lock_time 15 7:0 100 r/w overload: time until lock is released added in rev b status register mon_rst_lock_wurq 16 4:0 0 w/pulse figure 3.14 16 mon_rst_power_fail 4 0 w/pulse reset for power fail due to line-fault or under-voltage added in rev b 16 mon_rst_wurq 3 0 w/pulse reset for wake up request 16 mon_rst_aux_lock 2 0 w/pulse reset for channel 2 lock 16 mon_rst_com_lock 1 0 w/pulse reset for channel 1 lock
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 44 of 90 reg.-name addr. bit-field bit reset- value r/w comment reference 16 mon_rst_ovt_lock 0 0 w/pulse reset for temperature lock mon_rst_counter 17 0 17 mon_rst_aux_hs 4 0 w/pulse reset channel2 ovl-hs-counter 17 mon_rst_aux_ls 3 0 w/pulse reset channel2 ovl-ls-counter 17 mon_rst_com_hs 2 0 w/pulse reset channel1 ovl-hs-counter 17 mon_rst_com_ls 1 0 w/pulse reset channel1 ovl-ls-counter 17 mon_rst_ovt 0 0 w/pulse reset ovt counter irq_status 18 7:0 0 r/rst interrupt-status figure 3.14 18 irq_power_fail 7 0 r/rst power_fail interrupt request added in rev b 18 irq_wurq 6 0 r/rst wake-up request 18 irq_valid_flag_err 5 0 r/rst valid-flag error occurred 18 irq_eeprom_err 4 0 r/rst single error has been corrected 18 irq_eeprom2_err 3 0 r/rst multiple bit error occurred 18 irq_lock_aux 2 0 r/rst over-load lock of aux line driver 18 irq_lock_com 1 0 r/rst over-load lock of com line driver 18 irq_lock_ovt 0 0 r/rst over-temperature lock of both line drivers, aux and com
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 45 of 90 reg.-name addr. bit-field bit reset- value r/w comment reference mon_device_temp 19 3:0 0 r device temperature mon_stat 20 7:0 0 r 20 mon_aux_lock 7 0 r lock on aux due to aux-overload 20 mon_com_lock 6 0 r lock on com due to com-overload 20 mon_ovt_lock 5 0 r lock on com + aux due to over- temperature 20 mon_stat_aux_hs_ovl 4 0 r aux-highside-ovl 20 mon_stat_aux_ls_ovl 3 0 r aux-lowside-ovl 20 mon_stat_com_hs_ovl 2 0 r com-highside-ovl 20 mon_stat_com_ls_ovl 1 0 r com-lowside-ovl 20 mon_stat_ovt 0 0 r over-temperature mon_com_ls_peak 21 7:0 0 r/rst longest com-ls- overload mon_com_hs_peak 22 7:0 0 r/rst longest com-hs- overload mon_aux_ls_peak 23 7:0 0 r/rst longest aux-ls- overload mon_aux_hs_peak 24 7:0 0 r/rst longest aux-hs- overload mon_ovt_peak 25 7:0 0 r/rst longest over- temperature duration mon_pow_detect 26 1:0 0 r/rst power monitor added in rev b
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 46 of 90 reg.-name addr. bit-field bit reset- value r/w comment reference 26 reserved 7:2 0 r/rst reserved 26 mon_line_fault 0 r/rst line fault occurred 26 mon_under_voltage 0 r/rst under voltage occurred manufacture use only 27:30 7:0 0 r read returns 0 product_id 31 7:0 id r allows to retrieve product and revision information added in rev b 3.3.10. interrupt and ic lock mode control 3.3.10.1. interrupt handling the int _l pin provides indication functionality for a se t of ic-internal exceptions. once an exception had occurred, expressed as logic low of the int_l signal, the actual cause can be evaluated by reading the ic?s status register via the spi interface. depending on the condition ? a reset of t he exception by reading the corresponding status register can be performed. the following exceptions are combined in the int indication functionality: ? lock caused by power fail detector (refer to chapter 3.5 ) ? lock caused by com-overload (refer to chapter 3.3.10) ? lock caused by aux-overload (refer to chapter 3.3.10) ? lock caused by over-temperature (refer to chapter 3.3.10) ? eeprom-single-bit-error (refer to chapter 3.3.7 ) ? eeprom-2bit-error (refer to chapter 3.3.7 ) ? valid-flag-cleared due to possibly corrupt eeprom (refer to chapter 3.3.7 ) ? wurq detected (refer to chapter 3.3.4 ) figure 3.14 illustrates the handling of the above mentioned except i ons and their monitoring. it also shows how to configure the interrupt (int_l pin) and wake-up (wurq_l pin) signal generation. besides several exceptions concerning channel overload, die over-temperature and io-l ink specific wake-up situations the ic can also signal problems as regards the eeprom. since the configuration registers ge t their content initially from the eeprom, the data should be correct. the following described features make sure that no corr upt eeprom data can cause unwanted ic configurations.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 47 of 90 an eeprom s ingle bit error indicate s a one bit problem in the content of the eeprom. since the eeprom includes a self correction, o ne bit errors will be detected and corrected automat ically. however, the indication shall trigger a rewrite 17 of the entire eeprom content. the eeprom 2-bit error indicates a two bit problem in the content of the eeprom. that error is not automatically corrected, so the content of the eeprom can not be considered as correct. thus a reprogramming is absolutely required. the valid-flag is used to indicate that the last writ e access to the eeprom was successful. if the valid-flag indicates a problem, then the chip configuration has to be regarded as faulty ? no save ic function can be guaranteed. rewriting of the entire eepr om content is necessary. in case of a regular write process to the eeprom is not completed, for instan ce by an interruption of the ic s upply power within the ongoing write process, the valid-flag will indicate this as a problem because of the eeprom content might be corrupt. besides the signalization of ic-internal exceptions the in_l pin signals also the system reset state. the system reset state is indicated with active low on the int_l pin. figure 3.14 interrupt (int_l pin) and wake-up (wurq_l pin) signaling 18 reset ovl/ovt counter only com off if irq_lock_com == 1 aux off if irq_lock_aux == 1 both off if irq_lock_ovt == 1 or (com and irq_power_fail == 1 aux) 1 0 and (8x) 8 8 nor 8 irq int_l pin (low active) mon_rst_lock_ovt mon_rst_lock_com mon_rst_lock_aux mon_rst_wurq mon_rst_power_fail reserved reserved reserved 0 7 bit reset 0 6 5 4 3 2 1 0 0 0 0 0 0 0 w / pulse memory control 8 irq_en_lock_ovt irq_en_lock_com irq_en_lock_aux irq_en_eeprom2_err irq_en_eeprom_err irq_en_valid_flag_err irq_en_wurq irq_en_power_fail 0 7 bit reset 1 6 5 4 3 2 1 1 1 1 1 1 1 1 r / w wurq_l pin config dc/dc converter aux_lock circuit com_lock circuit ovt_lock circuit power fail detection set clear set clear set clear set clear a write access to the mon_rst_lock_wurq/mon_rst_count register leads to a reset of the circuit that is associated with the for this partial functionality assigned register bit if the write-data contain a 1 at to this bit corresponding bit position. for example, writing 0x08 to mon_rst_lock_wurq will reset a detected wurq exception but not a possibly performed lock with respect to the com-channel, aux-channel, and the over-temp detection circuit. wurq int_l pin (low active) inl_l pin config wurqdetect_lvl wurqdetect_current wurqsource irq_noreg both_channel_lock dcdc_ready_delay wurq_pad_mode irq_pad_mode 0 7 bit reset 0 6 5 4 3 2 1 0 1 0 0 0 0 0 r / w driver off p a r t i a l r e s e t v i a s p i irq_lock_ovt irq_lock_com irq_lock_aux irq_eeprom2_err irq_eeprom_err irq_valid_flag_err irq_wurq irq_power_fail 0 7 bit reset 0 6 5 4 3 2 1 0 0 0 0 0 0 0 r / rst internal ic sensors for overload and over- temperature dectection lock circuit reset (influences also reg[18]) mon_rst_ovt mon_rst_com_ls mon_rst_com_hs mon_rst_aux_ls mon_rst_aux_hs reserved reserved reserved 0 7 bit reset 0 6 5 4 3 2 1 0 0 0 0 0 0 0 w / pulse driver protection circuit 4 state signals wurq detection set clear 17 note: ic versions ziol2xx2 do not allow any write access. 18 the in this an in the following figures used symbols for the ic registers are explained in figure 9.1.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 48 of 90 the wurq indication is a dedicated io-link functionality. a wurq event is indicated if an over current situation with a determined timing ? regarding to io-link comm unication specification happened on one of the output driver stages (refer to chapter 3.3.4 , 3.3.10.1 and 8 ). a wurq event will be created if there is either a timely limited (typical 80s) different logical va lue between the logical output value of the driver and the received logical value from the line or an also timely limited (typical 80s) over-current at the considered channel. it can be configured whether the first or the last or both conditions lead to a wurq event. 3.3.10.2. ic lock mode configuration and monitoring if the current through the out put driver exceeds the configured limit, an exception will be generated. in addition to that and depending on the ics configuration, the lo ck mode operation which corresponds to the overloaded channel can be performed (refer to figure 3.15 and figure 3.16 ). the above mentioned lock mode operation is activated if either one driver stage (hs or ls) or both drivers stages (hs and ls st age) are overloaded, means the output current exceeds the configured limit. if the event occurs, the corresponding driver stage will be set to a save state, meaning it will be disabled. the lock mode configuration as shown in the following figures ( figure 3.15 , figure 3.16 , figure 3.17 ) is based on config urable current limits and time periods.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 49 of 90 figure 3.15 com channel lock control 19 com_ovl_ls_en com_ovl_hs_en com_ls_lock_en com_hs_lock_en com_lock_time_rst com_ovl_tbase reseved 0 7 bit reset 0 6 5 4 3 2 1 0 0 0 0 0 0 0 r / w com_assert_time 0 7 bit reset 1 6 5 4 3 2 1 1 1 1 1 0 1 0 r / w mom_com_hs_peak 0 7 bit reset 0 6 5 4 3 2 1 0 0 0 0 0 0 0 r / rst mom_com_ls_peak 0 7 bit reset 0 6 5 4 3 2 1 0 0 0 0 0 0 0 r / rst low side stage com_ls (8bit) comparator 8 peak values 8 high side stage com_hs (8bit) 8 and count com_hs_ovl and count com_ls_ovl counter == assert_time counter == assert_time and and or 8 comparator lock counter com_lock_time 0 7 bit reset 1 6 5 4 3 2 1 1 1 1 1 0 1 0 r / w aux-channel 8 set clear and 8 peak values to register irq_status enables time based lock reset [6:5] 0b00: 200 ns 0b01: 1 ms 0b10: 8 ms 0b11: 16 ms 2 rst 1 1 2 : if input signal ==1 : if input signal == 0 - no overrun - no underrun counter reset with - write access to mon_rst_counter [17] data = 0bxxxxx1xx - 01 transition of com_ovl_hs_en counter reset with - write access to mon_rst_counter [17] data = 0bxxxxxx1x - 01 transition of com_ovl_ls_en from com_ls overload detector from com_hs overload detector spi rst 2 spi driver off 19 the com transmitter is only avail able inside the products ziol24xx/22xx
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 50 of 90 figure 3.16 aux channel lock control 20 low side stage aux_ls (8bit) comparator 8 peak values 8 high side stage aux_hs (8bit) 8 and count aux_hs_ovl and count aux_ls_ovl counter == assert_time counter == assert_time and and or 8 comparator lock counter aux_lock_time 0 7 bit reset 1 6 5 4 3 2 1 1 1 1 1 0 1 0 r / w com-channel 8 set clear 8 peak values to register irq_status enables time based lock reset [6:5] 0b00: 200 ns 0b01: 1 ms 0b10: 8 ms 0b11: 16 ms 2 rst 1 1 2 : if input signal ==1 : if input signal == 0 - no overrun - no underrun counter reset with - write access to mon_rst_counter [17] data = 0bxxx1xxxx - 01 transition of aux_ovl_hs_en counter reset with - write access to mon_rst_counter [17] data = 0bxxxx1xxx - 01 transition of aux_ovl_ls_en from aux_ls overload detector from aux_hs overload detector spi rst 2 spi aux_assert_time 0 7 bit reset 1 6 5 4 3 2 1 1 1 1 1 0 1 0 r / w aux_ovl_ls_en aux_ovl_hs_en aux_ls_lock_en aux_hs_lock_en aux_lock_time_rst aux_ovl_tbase reseved 0 7 bit reset 0 6 5 4 3 2 1 0 0 0 0 0 0 0 r / w mom_aux_hs_peak 0 7 bit reset 0 6 5 4 3 2 1 0 0 0 0 0 0 0 r / rst mom_aux_ls_peak 0 7 bit reset 0 6 5 4 3 2 1 0 0 0 0 0 0 0 r / rst driver off and 20 the aux transmitter is only availabl e inside the products ziol24xx/21xx
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 51 of 90 figure 3.17 over-temperature lock control comparator 8 peak values 8 over- temperature counter (8bit) and count ovt counter == assert_time and 8 set to register irq_status enables time based lock reset ovt_time_base [6:5] 0b00: 200 ns 0b01: 1 ms 0b10: 8 ms 0b11: 16 ms 2 rst 1 1 over-temperature counter count-up : if input signal count ==1 count-down : if input signal count == 0 - no overrun - no underrun counter reset with - write access to mon_rst_counter [17] data = 0bxxxxxxx1 -0 1 transition of ovt_en from over-temperature detector spi ovt_lock_time ovt_lock_time [05] >c< 0 7 bit reset 1 6 5 4 3 2 1 1 1 1 1 0 1 0 r / w mon_ovt_peak mon_ovt_peak [25] >s< 0 7 bit reset 0 6 5 4 3 2 1 0 0 0 0 0 0 0 r / rst ovt_en ovt_lock_en ovt_lock_time_rst ovt_tbase reseved ovt_pfd_ctrl [09] >c< 0 7 bit reset 0 6 5 4 3 2 1 0 0 0 0 0 0 0 r / w line_fault_en under_voltage_en 8 ovt_assert_time ovt_assert_time [08] >c< 0 7 bit reset 1 6 5 4 3 2 1 1 1 1 1 0 1 0 r / w lock counter 8 clear and 2 power fail detector the lock caused by an over-temperature displays that the die temperature has reached a critical level. that forces a self protecting save state, it causes disabling the com and the aux channel by turning off all the hv driver output stages ( figure 3.17 ). the i c configuration allows disabling the lock mode operation for overload exceptions from both channels (com/aux) and the exception from the die over-temperature detector. sinc e the lock mode operation prevents the ic to be destroyed due to physical stress situation, the disabling is not recommended or shall be done with particular caution only. disabled lock mode operations for the above menti oned building blocks will prevent generating the related contribution to the interrupt signal at the int_l pin. however, those except ions can be retrieved by reading the status register mon_stat[20] (refer to chapter 3.3.9 and/or figure 3.18 ). not d epending on the lock mode operation the ic allows retrieving diagnostic information about the duration of an exception (peak values). the corresponding ic configuratio n that is required for retrieving such diagnostic data is illustrated above figures ( figure 3.15 , figure 3.16 , and figure 3.17 ).
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 52 of 90 3.3.10.3. overload and over-temperature configuration and monitoring the ziol2xxx is dedicated to work in harsh industrial environ ments. several situations can cause serious stress to the ic which may lead to partly or complete damage of the ic. in order to minimize the impact of physical stress the ic generates exceptions if the hv drivers exceed the configur ed current limits or if finally the die temperature exceeds a certain configured value (f or more details refer to chapter 3.3.11 ). the status register mon_stat[20] reflect s all currently occurred except ions. status register mon_device_tem p[19] allows reading of the current die temperature.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 53 of 90 figure 3.18 internal ic sensors and related overload and over-temperature detection circuits 21 aux_lock circuit ovt_lock circuit s r a v dd a v ss high side current limit exceeded low side current limit exceeded a v dd a v ss high side current limit exceeded low side current limit exceeded com_lock circuit s r aux_hs_ovl com_hs_ovl com_ls_ovl aux_ls_ovl set set set set s r mon_stat_ovt mon_stat_com_ls_ovl mon_stat_com_hs_ovl mon_stat_aux_ls_ovl mon_stat_aux_hs_ovl mon_ovt_lock mon_com_lock mon_aux_lock 0 7 bit reset 0 6 5 4 3 2 1 0 0 0 0 0 0 0 r die temperature red orange yellow green die_temp reserved reserved reserved reserved 0 7 bit reset 0 6 5 4 3 2 1 0 0 0 0 0 0 0 r [3:0] 0b0000: blue 0b0001: green 0b0011: yellow 0b0111: orange 0b1111: red over_temp reserved primary_master_ch en_follow_prim_ch master_mode 0 7 bit reset 0 6 5 4 3 2 1 0 0 0 0 0 0 1 r / w set over-temperature (ovt) master mode control (data path switches) 21 the com transmitter is only available in side the products ziol24xx/22xx and the aux transmitter is only available inside the p roducts ziol24xx/22xx, respectively
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 54 of 90 3.3.11. die temperature measurement figure 3.18 illustrates the die temperat ure measurement of the ziol2xxx ic. the die temperature is measured with an on-chip sensor right in the center of the silic on die. since there is one temperature sensor which has a certain distance to all the different locations that produc e heat (due to dissipated electrical power), the sensor can only indicate a rough average value of the die temperature. this shall be considered in defining the alarm values for the over-temperature counter and in defin ing the over-temperature lock mode duration. in combination with four comparators the temperature s ensor circuit provides five temperature levels that correspond to certain temperatures as described in table 3.8 . the current die temperature (level) can be retrieved in readi ng the status register mon_device_temp[19]. table 3.8 temperature sensor levels temperature level typical trigger temperature value 1) min. trig. 2) max. trig. 2) unit mon_device_temp[19] value remarks / over_temp value for over- temperature exception blue < 95 c 0b0000 no comparator level reached green > 100 95 105 c 0b0001 0b0001 yellow > 110 105 115 c 0b0011 0b0010 orange > 120 115 125 c 0b0111 0b0100 red > 130 125 135 c 0b1111 0b1000 software-test n.a. n.a. n.a. n.a. 0bxxxx 0b0000 4) 1) the mentioned typical values of ic properties shall not be considered as statistical guaranteed mean values. 2) the tolerance (deviation from the typical trigger value) is 5c. the deviation is fo r all trigger values the same. this means for example that in extreme situations all trigger levels equal t he min. temperature or the max. temperature trigger value. 3) setting configuration register[7][3:0] = 0b1111 will cause an over-temperature excepti on immediately. this setting is supposed to be used while software development and not supp osed to be used in regular operation. 4) there is a deviating code 0b1111for the software test which valid for rev a only. the configuration-register ovt_temperature defines what temperature level causes an over-temperature exception ( figure 3.18 / table 3.8 ). this configuration featur e ensures a flexibility of the ic in various application ca ses. depending on the ic configuration an over-temperature c an cause disabled hv drivers in order to prevent the ic against damage. besides the dc/dc converter all other ic building feature will still function, also if a over- temperature exception has been detected 22 . thus all control and diagnostic func tions are still available if the ic is being overheated. 3.4. smart power supply the internal low voltage supply of the chip is 3.3v and generated by an on chip linear regulator. in order to decouple this voltage a capacitor needs to be connected ex ternally. since the regulator supports more load current than the ic requires itself, a certain current can be drawn by the external application ( table 2.2 ). 22 this security shutdown of the dc/dc converter is not implem ented in the ic revision a but prearranged for later easy implement ation.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 55 of 90 in orde r to reduce power dissipation, caused by the volt age drop above the regulating transistor, the regulator can be powered with an input voltage less than v dd_hv . if for example the on-chip dc/dc converter is in use and its output voltage is set to at least 5v, then the linear regulator can be powered with this output voltage. the electrical characteristics are shown in the chapter ?operating conditions? (chapter 1 ). the foll owing block schematic ( figure 3.19 ) shows the principle of the low voltage generation in conjunction with a p ossible usage of the on chip dc/dc converter. for more information about required external components refer to chapter 4 . figure 3.19 low voltage supply concept
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 56 of 90 3.5. the power fail detector 3.5.1. overview the power-fail detector function is split in to two tasks. the first task is the ?line-fault? (lf) detection which shall recognize a situation in which the ziol2xxx is not powered regularly. this sit uation can happen if for instance the wiring between device and host port is not performed in the right way (interchanged wires, broken wires). the second task is the ?under-voltage? (uv) detector wh ich monitors the supply voltage at the vdd pin of the ziol2xxx . the purpose of this detector is ensure a proper working of the hv drivers com and aux which is not guaranteed if the supply voltage at vdd dr ops below the allowed minimum value. figure 3.20 illustrated the working pr inciple of both the lf and the uv detec tor in combination with the further processing to the detected events (line_fault and und er_voltage). based on the ic configuration (lf_enable, uv_enable flags) each event (or both events) may activate the lock for both channels exactly for the period the respective event is present. the new status re gister [26] allows diagnosing what event is present or was present in the past. figure 3.20 pfd working principle 3.5.2. line-fault detector the line-fault (lf) detection feature as sumes the utilization of both channels in device mode. in the case one channel is used only, the number of detectable failures be reduced accordingly. for more information about detectable failures, please refer to the appendix c . the o ptional (configurable) detection of the situation of an abnormal power supply of the ic will be achieved by a ratiometric working voltage sensor. as sensor input work s the pfd pin (formerly m_en) in combination with two
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 57 of 90 ?se nse? resistors which are interconnected to the l+ and l- pin of the sensor/actuator device. those resistors provide a voltage divider. the so downscaled supply volt age (voltage at the pin pfd) is compared with the output voltage of an ic-internal voltage divider. in case of abnormal power supply of the ic (refer to figure 3.20 ) a window comparator will detect this situation as line_fault event. the fu rther processing of the line_fault event depends on the lf_enable configuration flag ( figure 3.20 ). a power-fail lock (lock_pf ) will be generated only if the duration of the so detected abnormal power supply (or break of power supply) is longer than 10ms ( figure 3.20 ). 3.5.3. under-voltage detector the ic has a power-on-reset circuit whic h puts the ic in reset state while power-on, or if the internal (core) supply voltage of 3.3v (voltage at lr_out) drops below a cr itical value. for example with vdd = 5v the internal 3.3v power supply may not be jeopardized thus the ic cont rol will work as usual. in this situation the under- voltage detection shall protect the hv driver which may not work correctly with vdd < 8v and which might have a chance to get damaged in this situation. if configured the under-voltage detector will avoid this situation by locking both driver channels. 3.5.4. channel locking and interrupt generation as mentioned in chapter 3.5.1 both channels can be locked if one or both of the events line_fault and under_voltage occur. in this case t he resulting signal lock_pf (refer to figure 3.20 ) will be stored in the irq_stat us status register [18][7] (refer to table 3.7 ). depending on the irq_enable configuration register [0][7] or on irq_nore g (configuration register [14 ][3]) and interrupt (pin int_l ) can be issued. 3.5.5. downward compatibility the introduction of the pfd in ic rev b goes in parallel with the conversion of the fo rmerly master enable (m_en) pin to a voltage sense pin (pfd pin). therefore the master enable /disable function must be defined by using a configuration flag. since ol d pcb designs are using the m_en interconnection either to vdd/lr_out or vss (enabling/disabling the master functiona lity), the lf feature cannot be used. 3.6. dc/dc converter 23 3.6.1. principle of operation the on chip dc/dc converter is a constant frequency (2.5 mhz) buck converter with an adjustable output voltage. the wide input voltage range of 8v to 36v, a minimize d output ripple (< 25mvpp), and the maximum output current of 50ma make the converter suitable for standard se nsor/actuator applications. the output voltage can be adjusted with an external voltage divider. the electrical characteristics are shown in the chapter ?operating conditions? (chapter 1 ). the dc/dc converte r can be disabled if the application does not require this func tionality. in order to do this the fb pin shall be connected to the 3.3v lv power supply output (pin lr_out). 23 only available with ic versions ziol240x/220x/210x
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 58 of 90 the converter runs independently from the two driver channels (com/aux) and their digital control state machine. a reset has no influence on the dc/dc converter. 3.6.2. principle of operation figure 3.21 shows the working principle of the dc/dc co nverter. required external components are described in chapter 3.6.3 . figure 3.21 dc/dc converter in principle the dc/dc converter senses the output voltage divided by the resistors r1 and r2 at pin fb. the difference between this signal and the reference voltage is amplified and then transformed into a pwm signal by comparing it with a triangular waveform. the pwm signal now enables and disables the output transistor. this results in a pulse length modulated signal with an amplitude of v dd_hv and ?v d (the schottky diode forward drop) which is then been filter via a second order lc filter to generate the output voltage v out .
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 59 of 90 the capa bility of the output driver of the dc/dc converter is limited to 200ma (refer to parameter i pk in table 2.3 ). operating at this limit must be limited in time. since the dc/dc is not shut down when the die-temperature exceeds the configured limit, the application circuit har dware and software design must make sure that no ic damage can occur. in the start-up phase of the ic (pow er-on-reset) the dc/dc converter contro l moves to a soft-st art regime which limits the current that char ges the capacitor at the v out voltage. this is done by increasing the reference voltage and thus the output voltage follows that reference in a controlled manner. the dc_rdy pin provides information on the state of the output voltage. if the dc/dc converter is overloaded (v out drops below 85% of the nominal value), dc_rdy is low. in addition to that dc_rdy is kept on logic low level if the ic is in power-on-reset. in this power-on-reset case and only in this case the converter is restarted. the rising edge of dc_rdy signal can be delayed by 50ms (+/- 5%). this delay function is configurable with bit 5 of the configuration-register irq_wurq_ctrl[14] (refer to figure 3.14 ). the ic manufacturer default value for this bit is ? 1? thus the delay function is enabled by def ault. if dc_rdy is low during re-configuration of the ic and the delay is not yet finished, it stay s low. the falling edge of the dc_rdy si gnal will not be delayed thus is not affected by bit 5 of the configuration-register irq_wurq_ctrl[14]. 3.6.3. dimensioning of external devices the output capacitor c1 acts as filter capacitor. it has to have low equal series resistance (esr) thus a ceramic capacitor with a 10f capacitance has to be chosen. the esr has influence on the output ripple. the higher the esr the higher is the output ripple. the self-resonant frequency of the capacito r shall be as high as possible. it is possible to have a 100nf block capacitor (c2) in pa rallel to c1 to increase its frequency behaviour. the schottky diode acts as freewheeling diode. th erefore, it shall have a low volt age drop to increase efficiency. a low parasitic capacity or a fast reverse recovery time increase the efficiency by preventing a large shoot-through current through the output transistor and the diode when switching on the transistor. the voltage divider provides the feedback voltage for t he dc/dc converter. r2 shall be ~10k ? . r1 can be calculated by ? ? ? ? ? ? ? ? ??? 1 225,1 , 21 v v rr setout . the tolerance of the resistors affect the tolerance of the output voltage thus resist ors with 1% tolerance are preferred. figure 3.22 illustrates the dc/dc converter output voltage (in cluding its tolerance range) as function of r1 for r2 = 10kohms. table 3.9 examples for the resistors r1 and r2 using e96 resistor series v out,set r1 r2 3.3v 18.2k ? 10.5 k ? 5v 38.3 k ? 12.4 k ?
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 60 of 90 figure 3.22 dc/dc converter output voltage as function of r1 (r2 = 10kohms) 3,00 4,00 5,00 6,00 7,00 8,00 9,00 10,00 11,00 12,00 13,00 14,00 15,00 10 20 30 40 50 60 70 80 90 100 110 120 130 r1 /kohms v out /v min max the inductor stores energy when the output transistor is condu cting and releases the energy if the transistor is switched off. for most applications a 10h inductor is sufficient. to reduce th e electromagnetic interference or to reduce the ripple voltage of the output voltage, the required inductance is calculated by
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 61 of 90 min, , max,_ , min 2 1 outsw setout hvdd setout if v v v l ?? ? ? ? ? ? ? ? ? ? ?? , where i out,min is the lowest output current, v dd_hv,max is the highest input voltage and f sw is the switching frequency of the dc/dc converter. 3.6.4. pcb layout considerations to achieve optimal parameters for the dc/dc converter (e.g . efficiency or ripple voltage), attention has to be given to the pcb layout. figure 3.23 shows the dc/dc converte r, its external elements and two high frequency loops. the length of each loop has to be as short as po ssible. furthermore, the distance between sw and fb has to be as large as possible to decrease the interference. it is recommended to have ground planes in between each signal line. figure 3.23 high frequency critical loops of dc/dc converter for pcb layout l1 d1 c1 r1 r2 c5 sw fb vdd c2 loop 1 loop 2 v dd_hv v out
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 62 of 90 figure 3.24 pcb layout of evaluation board as an example
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 63 of 90 4 application information ziol2xxx application circuits contain usually external components, which are required for overvoltage and reverse polarity protection. table 4.1 provides a summary about requires components. the in the following figures use d external components, in particular the special component type and it parameters are mentioned in this table.. the following schematics show standard application ci rcuits in principle with the focus to the interface part of the physical level transceiver performed by the ziol2xxx ics.. figure 4.1 simplified application circui t with the ziol2xxx in device mode in principle an io-link device cable interface (or the in terface for a standard sensor/a ctuator) requires four (one channel) or six (two channels) protection diodes. the diodes d4 ? d7 are fast clipping schottky diodes. those highly recommended diodes damp signal overshoots and make su re that in io-link device applications the device can detect supply power fa ilures as illustrated in figure 4.3 . d2 and d3 provide the reverse polarity protection for the device u nit as shown in figure 4.1 . since there is normally no chance in io-link master appl ications to apply the supply voltage in reverse manner, the reverse polarity protection diodes d2 and d3 can be omitted in master applications ( figure 4.2 ). with respect to figure 4.1 and figure 4.2 the pfd pin (prior ic rev b called m_en pin) is connected to power or ground as it wa s required in using rev a. using this way of interconne ctions of the pfd pin requires disabling of the line-fail
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 64 of 90 feature (refer to chapter 3.5 ). in case the line fail feature is intended to be use the pfd shall be connected to a voltage divide r as described in chapter 3.5 or illustrated in figure 4.3 . figure 4.2 simplified application circuit with the ziol2xxx in master mode in case of (io-link) device applications the ic might be powered not correctly via the l+/l- line. the circuit in figure 4.3 illustrates how to detect this power fail situati on by usin g a voltage divider as ?sensor?. since the voltage at the pfd pin is compared with an internal voltage divider resistors with low tolerace range (<= 1%) shall be used.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 65 of 90 figure 4.3 power line fail detection ziol2401 aux_en aux_tx wurq rx tx tx_en int_l rst_l pfd sw fb vdd com_o vss lr_in lr_out com_i aux_o standard cable device (sensor) l1 r1 r2 c1 c3 c5 d1 c4 d2 d3 d6 d5 vout dc_rdy l+ l- c/q d7 d4 aux_i aux_rx c2 r4 r3 r3 and r4 which perform the line voltage sensor shall connected directly to the cable (l+/l-). the pcb layout design requires considering several reco mmendations. in particular the placement of decoupling capacitors and the placement external components that perform the dc/dc converter circuits shall be done carefully. recommendations are: ? low resistive and low inductive ground interconnectio ns due to metal ground areas surrounding the ic or/and using a special ?ground? pcb layer. ? the wiring of the channel driver output shall consider that the wires are designed for currents up to 500ma (depending on the ic configur ation) and in combination with that wiring for vdd and vss shall designed for currents up to 1a. ? decoupling capacitors related to the ic pins vd d and lr_out (and lr_in if applicable) shall placed as close as possible to the ic pin. ? the dc/dc converter requires an external scho ttky-diode as free-wheel diode. its anode shall be interconnected to the sw pin. it is important that its cathode has good (short ) ground connection. with respect to all to the sw pin interconnected devices (free-wheel diode and inductor l1) all wires have to be kept as short as possible. moreover, the pcb des ign shall make sure that the parasitic coupling between the node belonging to the sw pin and the n ode belonging to the fb pin of the ic is minimized.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 66 of 90 ? the voltage divider r1/r2 shall interconnected to the fb (feedback pin) in that way that the electromagnetic coupling to the wire interconnected to the sw pin is low as possible. ? in order to achieve an optimal heat distribution form the ic to the environment it is strongly recommended to place via?s underneath the qfn package. an example as regards this pcb design detail is illustrated in figure 4.4 (2-layer pcb example). please refer to applications notes of the packa ge manufacturer amkor for more details how to place cooling via?s underneath the ic package (please visit the link mentioned in chapter 8 , [4] ). figure 4.4 pcb layout recommendations ziol2401 aux_en aux_tx wurq rx tx tx_en int_l rst_l m_en sw fb vdd com_o vss lr_in lr_out com_i aux_o l1 r1 r2 c1 c3 c5 d1 c4 vout = 5v dc_rdy aux_i aux_rx c2 d1 l1 d1 l1 c2 c1 r2/r1 ziol 2401 c6 c5 c6 c3 d1 schottky diode tmmbat42 l1 10h (close to pin 21 of ziol2401) r1 38.3kw ( dc/dc converter output r2 12.4kw voltage vout = 5v ) c1 10f / 10v (low esr) c2 100nf c3 10f / 10v (low esr) c4 100nf c5 10f / 50v (low esr) c6 100nf c6 c6 c5 c1 c3 c4 application example 2-layer pcb 4-layer pcb
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 67 of 90 figure 4.4 shows two layout variants as regards the component pla cement in the case the dc/dc converter is used in the application circuit. the in th is figure shown pcbs are the pcbs of the ziol2xxx application kits ( ziol2xxx labkit: 2-layer-pcb/ ziol2xxx usb-stick: 4-layer-pcb). the complete pcb documentation of the applications kit is available at zmdi upon request and is part of the documentation package of the application kits. another more optimized pcb layout recommendation for utilizing the on-chip dc/dc-c onverter shows figure 3.24 in c hapter 3.6.4 . an appropriated explanation about the considerations b ehind this recommendation is give in this chapter as well and illustrated in figure 3.23 . table 4.1 recommended external components symbol parameter min typ max unit notes r1 r 14 1) 112 2) k ? value depends on desired output voltage. r2 r 10 k ? r3 r -1% 49.9 +1% k ? low tolerance range resistor (1% class) r4 r -1% 210 +1% k ? low tolerance range resistor (1% class) l1 l 10 50 h optimal value depends on application requirements. c1 c 10 50 f low esr recommended c2 c 100 nf low esr required c3 c 10 f low esr recommended c4 c 100 nf low esr required c5 c 10 f low esr recommended schottky diode v rrm 40 v d1 i f 0.2 a recommended: small signal low cap schottky diode, e.g. tmmbat48 (sgs-thomson) or similar device schottky diode v rrm 40 v d2, d3 i f 1.0 3) a only in device applications recommended: 10bq040pbf (vishay) or similar device schottky diode v rrm 40 v d4 ? d7 i f 0.1 a recommended: bat64-04w ( [ nfineon) or similar device, the bat64-04w has a sot323 package with two diodes in series. thus there only one component for one channel (one dual diode for d4/d5 and one dual diode for d6/d7). q1 optocoupler acpl-217 (avago technologies) 1) r2 = 10k ? , please refer to minimum output voltage v out in table 2.3 2) r2 = 10k ? , please refer to maximum output voltage v out in table 2.3 3) two channels in operation, each channel drives max. current 4) important: the ratio r4/r3 shall be 4.2084 +/- 2%
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 68 of 90 5 pin configuration, latch-up and esd protection 5.1. pin configuration and latch-up conditions table 5.1 pin configuration and latch-up conditions pin name 1) description remarks usage 1) / connection 3) application circuit restrictions and/or remarks 11, 20 vdd (x2) positive external supply voltage pins (hv 4) ) supply in required/- both pins must be interconnected using a low impedance wiring 14, 17 vss (x2) negative external supply voltage pins ground required/- both pins and the exposed die paddle must be interconnected using a low impedance wiring n.a. vss exposed die paddle ground required requirements: - to be connected to vss - cooling via?s underneath the die paddle (refer to application note from amkor (refer to [4] in chapter 8 ) 24 rst_l reset input digital in l-active required or open/- pin tolerates 5v logic signals 15 pfd power fail detector (sense input of the line- fail detector) analog in required/ vdd, lr_out or vss (rev a compatibility) or voltage divider hv analog input pin, avoid long wires in order to optimize the emc behavior 7 spi_en_l spi enable digital in l-active required/- pin tolerates 5v logic signals 8 int_l overload indication digital out l-active required or open/- 9 wurq_l wake up detect signal digital out l-active required or open/- 4 tx_en/spi_clk com driver enable digital in h-active required/- pin tolerates 5v logic signals 5 tx/mosi tx: data input mosi: spi in digital in required or open/- pin tolerates 5v logic signals 6 rx/miso rx: data output miso: spi out digital out required or open/- 12 com_i com driver in hv 4) in required or open/- 13 com_o com driver out hv 4) out required or open/- 1 aux_en aux driver enable digital in h-active required/- pin tolerates 5v logic signals
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 69 of 90 pin name 1) description remarks usage 1) / connection 3) application circuit restrictions and/or remarks 2 aux _tx tx: data input digital in required or open/- pin tolerates 5v logic signals 3 aux _rx rx: data output digital out required or open/- 18 aux_o aux driver out hv 4) out required or open/- 19 aux _i aux driver in hv 4) in required or open/- 23 dc_rdy dc/dc ready signal digital out required or open/- 21 sw dc/dc switch out hv out required or open/- 22 fb dc/dc feed back analog in required / either interconnected voltage divider or to lr_out in operation mode of the dc/dc converter the voltage divider shall provide 1.225v at the fb pin. interconnecting fb to lr_out will disable the dc/dc converter. 16 lr_in linear regulator input voltage (hv 4) ) supply in hv required/- 10 lr_out linear regulator output voltage (lv 5) ) supply out lv required/ block cap to vss 1) names of low active digital i/o pins end with ?_l? 2) usage: if ?required? is specified, an electrical connection is necessary ? refer to the application circuits 3) connection: to be connected to this potential, if not used or no application/configuration related constraints are given 4) hv: high voltage ? the primary supply voltage of the ic or t he voltage swing of the cable signal, typically 24v (>8v, <36v) 5) lv: low voltage ? the supply voltage for the internal building bl ocks of the ic or control signals of the ic, typically 3.3v 5.2. esd-protection all pins have an esd protection of >2000 v. esd protection referred to the human body model (hbm ) is tested with devices in qfn24 packages during product qualification. the esd test fo llows the human body model with 1.5 k ? /100 pf, based on mil 883, method 3015.7.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 70 of 90 6 package 6.1. pin hardware configurations in contrast to the integrated circuit product ziol2401 wh ich is base ic for the ziol2401 ic family, not all derived ics provide all electrical pin interconne ctions as provided with the ziol2401. table 6.1 shows what pins are not c onnected (n.c.). table 6.1 availability of pin interconnections pin number pin name ziol 240x 1) 2) ziol 241x 1) 2) ziol 220x 1) 2) ziol 221x 1) 2) ziol 210x 1) 2) ziol 211x 1) 2) pcb design recommendations for not connected (n.c.) pins 12 com_i + + + + n.c. n.c. connect to vss 13 com_o + + + + n.c. n.c. connect to vss 19 aux_i + + n.c. n.c. + + connect to vss 18 aux_o + + n.c. n.c. + + connect to vss 21 sw + n.c. + n.c. + n.c. do not connect 22 fb + n.c. + n.c. + n.c. do not connect 1) ?+?: pin is in connected, regular use as mentioned in this datasheet 2) ?n.c.?: pin is not connected, the pc design recommendations shall be considered 6.2. pin diagram the standard package of the ziol2xxx is a ?sawn type? 24 pin microleadframe package (amkor, qfn24): it is a green package having a 4mm body width and a lead pitch of 0.5 mm (refer to [3] in chapter 8 ). w it respect to the different pin hardware configurations of certain ics of the product family ziol2xxx not all pins are interconnected with the silicon die (for more information refer to table 6.1 ). the pin diagram shown in figure 6.1 does not reflect this or can be considered as the pin diagram of the ziol2401.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 71 of 90 figure 6.1 pin diagram of the ziol2xxx 6.3. optimal pcb layout in order to obtain optimal heat distribution (minimized thermal resistance between package and board) certain pcb layout rules shall be applied. those rules are desc ribed in the application note for the used qfn package (refer to chapter 8 , [4] ). crucial for optimal heat distribution is the corre ct number, diameter and placement of via?s underneath the exposed die paddle as described in the above mentioned application note.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 72 of 90 6.4. package outline the ic is packaged in a 24 pin qfn package ( figure 6.2 , based on jedec mo-220) having dimensions as sho wn in table 6.2 . figure 6.2 package dimensions table 6.2 package dimensions in mm dimensions min max a 0.80 0.90 a 1 0.00 0.05 b 0.18 0.30 e 0,5nom h d 3.90 4.10 h e 3.90 4.10 l 0.35 0.45
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 73 of 90 6.5. device marking figure 6.3 illustrates the device top marking which reflects: ? first line: the product type ( ziol2xxx , xxx: refer to table 1.1 ) and product revision identification (last letter, e.g. ?b? for rev b) ? second line: the date code (?yyww? = year / workweek), ?e? stands for ?engineering sample? if applicable ? third line: ic manufacture?s traceability code (xxxxx) figure 6.3 top marking of the ziol2xxx the ziol2xxx has no bottom marking.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 74 of 90 7 ordering information product sales code 1 description package ziol2xxx #r 1) ziol2xxx, ziol2xx - io-link compli ant hv line driver ic family, packing: 13?? reel qfn24, 4x4 ziol2xxx #w 1) ziol2xxx, ziol2xx - io-link compli ant hv line driver ic family, packing: 7?? reel qfn24, 4x4 ziol2401 -lab kit ziol2401 labkit for detailed lab evaluation (suitable for ziol2xxx ) (configurable ic-/communication/controller pcb, software, usb-cable) ziol2401 -starter kit ziol2401 introduction tool (usb stick, extension board, software) (suitable for ziol2xxx ) 1) # stands for the device revision xxx stands for the device der ivate (refer to chapter 1)
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 75 of 90 8 related documents document reference/file name [1] iec61131-2 iec61131-2, third edition 2007-7 [2] io-link communication specification iol-comm-spec_10002_v10_090118.pdf, downloadable from www.io-link.com [3] datasheet microleadframe (qfn package) microleadframe.pdf, downloadable form www.amkor.com [4] application note qfn package mlfapplicationnotes0908revg.pdf , downloadable form www.amkor.com visit zmdi?s website http://www.zmdi.com/ or contact your nearest sales office for the latest version of these documents.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 76 of 90 9 glossary 9.1. terms and abbreviations term description aux auxiliary communication channel of the ic ziol2xxx com default communication channel of the ic ziol2xxx com1 io-link specific communication channel speed com2 io-link specific communication channel speed com3 io-link specific communication channel speed hs high-side, meant is the high side swit ch of a driver channel (push function) ls low-side, meant is the low side switch of a driver channel (pull function) ovl overload (current or temperature) exception ovl_hs current overload exception at hs ovl_ls current overload exception at ls ovt over-temperature exception pfd power fail detection phy physical layer transceiver 9.2. symbols used in this datasheet symbol description xx yy physical value (physical variable) as used in operation conditions, ic parameters and functional descriptions xx_yy_l digital i/o low active ic pin xx_yy any other ic pin (analog, supply or digital i/o high active ic pin) xx_yy[nn] register names, nn = address selected examples for physical values: v dd_hv primary ic supply voltage of nominal 24v (called high_voltage) = cable supply voltage v dd_lv secondary supply voltage for all a nalog and digital bu ilding blocks of the ic of nominal 3.3v. vdd_lv is equivalent to the supply voltage provided by the internal linear regulator. it can also be used to supply external electronic circuits.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 77 of 90 figure 9.1 register representation in principle (example) lock_ovt lock_com lock_aux eeprom_2_err eeprom_err valid_flag_err wurq reserved 0 7 bit reset 1 6 5 4 3 2 1 1 1 1 1 1 1 1 r / w lock_ovt lock_com lock_aux eeprom_2_err eeprom_err valid_flag_err wurq reserved 0 7 bit reset 0 6 5 4 3 2 1 0 0 0 0 0 0 0 r / rst register name [address] status register config-register access type access type inputs inputs outputs outputs reset values register/bit functional assigment access types: r/w read /write r read only r/rst read only / clear by read w/pulse partial reset of certain ic functions
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 78 of 90 10 document revision history revision date description 0.6 december 8, 2008 first draft 0.7-0.9 internal revisions 1.0 july 2009 completely reworked datasheet 1.0.1 1.0.2 august 2009 developer feedback processed 1.0.3 august 2009 internal revision 1.0.4 august 2009 1 st release under nda 1.0.5 september 2009 internal revision 1.0.6 november 2009 reworked due to internal/external feedback 1.0.7 december 2009 reworked due to internal/external feedback (correction of typing errors and wrongly described ic functions) - register description in overview drawings - ic properties - external components dcdc converter 1.0.8 december 2009 channel configuration coding tables and figur e concerning the description of channel locking corrected; 1.1.0 .. 1.1.4 february 2010 internal revisions 1.1.5 1.1.6 1.1.8 march 2010 significant re-work of all datasheet chapters - parameters dc/dc converter and com/aux driver adjusted - external clamping diodes changed from z-diodes to schottky diodes - ic configuration more in detail - detailed application examples 1.1.8 1.1.9 april 2010 internal revisions 1.1.10 april 2010 update of package related info rmation, improvement of comprehensibility 1.1.11 may 2010 - improvement of comprehensibility on base of a detailed data path description - typing error correction reg[18] (interrupt and wake-up signaling - more detailed descriptions in register list - electrical interconnection of exposed paddle of the ics package 1.1.12 may 2010 - text layout 1.1.13 june 2010 - pin name error correction in figure 5-1 pin diagram of the ziol2401 - recommendation for the external diode d1 of the dc/dc converter changed from tmmbat42 to tmmbat48 1.2.0 june 2010 final version for ic revision a - consequently using the term io-link ?device?, term ?slave? replaced - dc/dc converter parameters
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 79 of 90 revision date description 1.2.1 1.2.2 june 2010 internal revision 1.2.3 july 2010 general change (rework) of the dc/dc-converter description and adding of further pcb layout recommendation in combination with the utilizat ion of the dc/dc- converter 1.2.4 august 2010 - changes regarding zmdi?s corporate identity police - dc/dc converter: more detailed dc_rdy description 2.0.1 september 2010 - datasheet ziol2401 rev1.2.4 transferred to ic family datasheet ziol2xxx - included all ic rev b enhancements (upgrades) 2.0.2 november 2010 - considered feedback from the ic development team, in particular as regards the rev b functionality and functionality of the different ic family members - revised the description of the tr ansceivers in order to higher the comprehensibility (focusing to the terms: device/master mode and dual/tandem mode 2.0.3 january 2011 internal review results considered - new (more comprehensive) description of the driver channel and their configuration and operating modes - both channels: introduction of separated descriptions of alarm levels (causing an exception) and the corresponding current limitation of the considered driver. 2.1.0 april 2011 first release of ziol2xxx ic fami ly data sheet 2.2.0 october 2011 just for internal reviews 2.2.1 january 2012 - changed upper limits for confi gurable output current limits ( table 2.3 ) - added power consumption informati on (current into vss, lr_in) - added package drawing sales and further information www.zmdi.com sales@zmdi.com zentrum mikroelektronik dresden ag grenzstrasse 28 01109 dresden germany zmd america, inc. 8413 excelsior drive suite 200 madison, wi 53717 usa zentrum mikroelektronik dresden ag, japan office 2nd floor, shinbashi tokyu bldg. 4-21-3, shinbashi, minato-ku tokyo, 105-0004 japan zmd far east, ltd. 3f, no. 51, sec. 2, keelung road 11052 taipei taiwan phone +49 (0)351.8822.7465 fax +49 (0)351.8822.87465 phone +1 (608) 829-1987 fax +1 (631) 549-2882 phone +81.3.6895.7410 fax +81.3.6895.7301 phone +886 2 2377 8189 fax +886 2 2377 8199 disclaimer : this information applies to a product under development. its characteristics and specifications are preliminary and subject to change without notice. zentrum mikroelektronik dresden ag (zmd ag) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. t he information furnished hereby is believed to be true and accurate. however, under no circumstances shall zmd ag be liable to any customer, licensee, or any other third party for an y special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical dat a. zmd ag hereby expressly disclaims any liability of zmd ag to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of zmd ag for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 80 of 90 appendix a z iol2xxx diagnostic techniques a.1. general remarks since chapter 3.3 described the basic principles in terms of ic co ntrol circuit, this chapter deals with details of techniques for analyzing the internal ic state in order to prevent ic damage or unwanted system operation. the following description references to figure 3.8 ( the basic scheme of the ic self protection ) of the ziol2xxx datasheet. a.2. overload counter behavior and peak register access the ziol2xxx contains five peak registers (status regi sters) which are associated with overload counters as follows: ? over-current counter assigned to the ls driver of the com channel ? register[21] ? over-current counter assigned to the hs driver of the com channel ? register[22] ? over-current counter assigned to the ls driver of the aux channel ? register[23] ? over-current counter assigned to the hs driver of the aux channel ? register[24] ? over-temperature counter? register[25] only in case an overload is present, thus the overload co unter is in the count up mode, the value of the overload counter will be copied into the peak register if the overl oad counter value is greater than the peak register value. this conditional copy operation is performed within each cycle of ic control circuit as illustrated in figure 10.1 . figure 10.1 shows two different scenarios of the behavior of a pea k register. scenario a shows the development of the peak register value if no read access happened. in contrast to that scenario b shows several read accesses within the same sequence of consecutive overload peri ods. since the peak register is cleared after each read access, it resumes within the next cycl e of the ic control circuit to the present overload counter value only if overload is present. a lock will be generated if the overload counter reaches a configured maximum value which is representing according to the following formula the related ?assert time? of the lock circuit (refer to figure 3.15 , figure 3.16 , figure 3.17 ). val asserttime t t clk asserttime ? ? where t clk is the for the lock circuit conf igured counter clock (refer to figure 3.15 , figure 3.16 , figure 3.17 ) having a perio d of 200ns, 1ms, 8ms, or 16ms and where asserttimeval is the in the related as sert time register stored value. similarly to that, thus using a similar formula t he lock time of the related lock circuit (refer to figure 3.15 , figure 3.16 , figure 3.17 ) can be calculated. l locktimeva t t clk locktime ? ?
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 81 of 90 whe re t clk is the for the lock circuit configured counter clock (which is the same clock as used for the overload counter, refer to figure 3.15 , figure 3.16 , figure 3.17 ) having a period of 200ns, 1ms, 8ms, or 16ms and where locktim eval is the in the related assert time register stored value. figure 10.1 peak register access scenarios in contrast to figure 10.1 in where the overload situation stops at t he point in time in whi ch the driver has been locked figure 10.2 shows a situation in which the ove rload situation, especially an over-current situation is kept. this situation occurs for instance due to a low impedanc e load which is permanently interconnected to the driver output. in addition to that the lock reset is configured in that way that its period is significantly shorter compared with the assert time period. in this case the overload count er does not reach the zero value at the point in time the lock is reset. this in the following time the assert time is shortened and equals approximately the lock time that even passed by.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 82 of 90 figure 10.2 overload counter behavior in permanent over-current situations since a locked channel is in high-impedance (high-z) state, no over-current can occur while a channel is locked. therefore overload counter starts immediately counting down when the lock is enabled. in case of a permanent over-temperature situation the die temperature may not decrease at the point in time the channel control started locking both channels as shown in figure 10.3 . in this case the overload counter does not
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 83 of 90 stop countin g up if the configur ed assert time is expired. finally the overload counter reaches its maximum value of 255 (0xff). figure 10.3 overload counter behavior in permanent over-temperature situations in this situation a lock reset due to an elapsed internal lock counter of the temper ature lock control circuit ( figure 3.17 ) will not release the locks which are in effect on bot h cha nnels. however, the locks can be released by writing into register[16] (write pulse function). in typical over-temperature situations the overload count er may reach a value that is greater as the configured limit. this is due to the thermal inertia of the system since the temperature sensor and the thermal sources are not on the same place on the silicon die. when the lock has been released, the there is a little difference in the
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 84 of 90 behavio r when reading the peak register as shown in figure 10.4 . the peak register is loaded with the overload cou nter value again as long the ove r-temperature situation is present. figure 10.4 overload counter behavior in typical over-temperature situations a.3. overload counter and lock reset methods the ziol2xxx has two special status registers (register[ 16:17]). those status register s do not contain information about the ic status. thus reading those registers will always result to the value zero for each register. however those registers are used to perform special resets within the com, aux, and temperature lock circuits. in addition to that register[16] can also reset the wurq exception. the way to perform a particular reset operation is writing into the register (write 24 pulse access; please refer to chapter 3.3.9 ) the bit-value ?1? at a certain bit position wh i ch is assigned to the desired reset operation. register[16] performs the following reset operations by writing a ?1? into the following bit positions: ? bit[0]: reset over-temperature counter and reset of the internal and stored over-temperature (ovt) exception ? bit[1]: reset the com over-current counter and reset of the internal and stored com 24 note: ic versions ziol2xx2 do not allow any write access.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 85 of 90 over-cu rrent (ovt) exception ? bit[2]: reset the aux com over-current co unter and reset of the internal and stored aux over-current (ovt) exception ? bit[3]: reset of the stored wurq exception figure 10.5 partial reset of overload counter or the entire lock circuit channel driver unlocked over-load / over-temp reg[20] peak counter reg[21:25] overload counter stored exception reg[18] int_l lock reset (lock counter elapsed) assert time exception (state signal) reg[20] by ?read & clear? reset of the peak counter assert time expired, exception causes int_l = 0 (if configured) unlocked locked monitored physical value exceeds the configured limit time time time time time time overload counter equals configured limit configured lock time write pulse to reg[16] or reg[17] will reset the overload counter only since there is no exception present write pulse to reg[16] = reset lock circuit a write pulse access to register [17] works similar but performs only a partial reset of the overload counter as in the following described:
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 86 of 90 ? bit[0]: reset of the over-temperature counter ? bit[1]: reset of the over-current coun ter assigned to the com ls driver ? bit[2]: reset of the over-current coun ter assigned to the com hs driver ? bit[3]: reset of the over-current coun ter assigned to the aux ls driver ? bit[4]: reset of the over-current coun ter assigned to the aux hs driver figure 10.5 illustrates the effect of a write 25 pulse access to register[16] and register[17]. as shown in this figure a write pulse to register[16] does only reset the overload counter if no exception is present. if an exception is present (or still stored in re gister[18]) the write pulse access to regist er[16] will also reset related exceptions. in the special case the write pulse access to register[16] is performed while a temperature overload is still present the exception will by cleared but set again within the next cycle of the ic control circuit. accordingly to the configuration of the int_l pint the int_l pin will perfor m the configured transitions again (refer to chapter a.2 ). dep ending on the byte-value written in register[16] or register[17] the above mentioned reset operation are performed separately or in parallel. sales and further information www.zmdi.com sales@zmdi.com zentrum mikroelektronik dresden ag grenzstrasse 28 01109 dresden germany zmd america, inc. 8413 excelsior drive suite 200 madison, wi 53717 usa zentrum mikroelektronik dresden ag, japan office 2nd floor, shinbashi tokyu bldg. 4-21-3, shinbashi, minato-ku tokyo, 105-0004 japan zmd far east, ltd. 3f, no. 51, sec. 2, keelung road 11052 taipei taiwan phone +49 (0)351.8822.7465 fax +49 (0)351.8822.87465 phone +1 (608) 829-1987 fax +1 (631) 549-2882 phone +81.3.6895.7410 fax +81.3.6895.7301 phone +886 2 2377 8189 fax +886 2 2377 8199 disclaimer : this information applies to a product under development. its characteristics and specifications are preliminary and subject to change without notice. zentrum mikroelektronik dresden ag (zmd ag) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. t he information furnished hereby is believed to be true and accurate. however, under no circumstances shall zmd ag be liable to any customer, licensee, or any other third party for an y special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical dat a. zmd ag hereby expressly disclaims any liability of zmd ag to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of zmd ag for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise. 25 note: ic versions ziol2xx2 do not allow any write access.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 87 of 90 appendix b z iol2xxx configuration techniques the ziol2xxx allow various co nfigurations to work optimal in severa l applications. basically the ziol2xxx can be configured to work in applic ations with or without c. figure 10.6 configuration checker report of the ziol2xxx application kit (example) application kit - zio2401 (c) zmdi - v2.1, built 28.04.2011 10:06:42 (utc) ziol2211 rev.b - configuration check on: 29-apr-2011 09:52:11 number of warnings: 1 number of errors: 1 io-link wake-up (wurq) detection wurq detection is assigned to channel: com wurq detection method: - wurq detection on current (overload) - wurq detection on antivalent levels com channel transmitter current limit: 50 ... 65 ma high-side: enabled low-side: enabled slew rate control: 10 v/s 150k-resistor usage: off signal inverter: off com channel receiver receiver logic input levels: absolute (io-link conform) analog filter: off digital filter: off signal inverter: off sink mode: off sink strength: 2 ... 3 ma com channel protection settings assert time (persist overload during this period will lead to locked driver): 0 ms >>> warning: zero assert time can lead to immediately locked driver! lock time (period after lock will be removed automatically): 100 ms high-side: overload and wake-up detection: enabled driver lock due to hs overload exceeds assert time: enabled low-side: overload and wake-up detection: enabled driver lock due to ls overload exceeds assert time: enabled aux channel transmitter current limit: 50 ... 65 ma high-side: enabled low-side: enabled slew rate control: 10 v/s 150k-resistor usage: off signal inverter: off aux channel receiver receiver logic input levels: absolute (io-link conform) analog filter: off digital filter: off signal inverter: off sink mode: off sink strength: 2 ... 3 ma aux channel protection settings assert time (persist overload during this period will lead to locked driver): 50 ms lock time (period after lock will be removed automatically): 0 ms high-side: overload and wake-up detection: enabled driver lock due to hs overload exceeds assert time: enabled low-side: overload and wake-up detection: enabled driver lock due to ls overload exceeds assert time: enabled over-temperature protection settings over-temperature protection: enabled channel locking: enabled max. allowed die temperature: >>> error: multiple or no temperature level selected assert time (persist over-temperature during this period will lock both drivers): 100 ms lock time (period after lock will be removed automatically): 200 ms power-fail protection settings under-voltage protection (channel locking): disabled line-fail protection (channel locking): disabled master/device mode settings ic mode: device mode pin configuration settings wurq_l pin (io-link wake-up signaling): push/pull int_l pin (for exception signaling settings refer below): push/pull dc_rdy pin: delay 50 ms exception signaling interrupt (int_l) will be active if one of the following exceptions occurred: - both channels are locked due to power-fail - wake-up has been detected (wurq) - the eeprom is corrupt (valid-latch error) - there is a general eeprom error - there is a 2-bit eeprom error - the aux channel is locked due to over-current - the com channel is locked due to over-current - both channels are locked due to over- temperature irq_port (int_l pin) follows: state signals configuration register summary configreg[0] = 0xff configreg[1] = 0x03 configreg[2] = 0x00 configreg[3] = 0x03 configreg[4] = 0x00 configreg[5] = 0xc8 configreg[6] = 0x64 configreg[7] = 0x06 configreg[8] = 0x64 configreg[9] = 0x0f configreg[10] = 0x00 configreg[11] = 0x3f configreg[12] = 0x32 configreg[13] = 0x3f configreg[14] = 0xeb configreg[15] = 0x00 summary data path configuration recommendations as regards the optimal configuration of the ic are provided by zmdi in application notes and associated xml-data-files. those xml-data can be loade d into the ic using the also by zmdi provided ziol2xxx application kits. moreover, the user interface program of the ziol2xxx application kit provides a ?configuration checker tool? which allows reviewing the ic configuration in a plain text report and which provides error and warning me ssages in case of wrong or critical ic configurations as illustrated in figure 10.6 .
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 88 of 90 the followi ng configurations are considered as critical thus not recommended to use: ? assert time = 0 ? set both the driver no-current-limit bit and in parallel one or two bit t hat define current limits sales and further information www.zmdi.com sales@zmdi.com zentrum mikroelektronik dresden ag grenzstrasse 28 01109 dresden germany zmd america, inc. 8413 excelsior drive suite 200 madison, wi 53717 usa zentrum mikroelektronik dresden ag, japan office 2nd floor, shinbashi tokyu bldg. 4-21-3, shinbashi, minato-ku tokyo, 105-0004 japan zmd far east, ltd. 3f, no. 51, sec. 2, keelung road 11052 taipei taiwan phone +49 (0)351.8822.7465 fax +49 (0)351.8822.87465 phone +1 (608) 829-1987 fax +1 (631) 549-2882 phone +81.3.6895.7410 fax +81.3.6895.7301 phone +886 2 2377 8189 fax +886 2 2377 8199 disclaimer : this information applies to a product under development. its characteristics and specifications are preliminary and subject to change without notice. zentrum mikroelektronik dresden ag (zmd ag) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. t he information furnished hereby is believed to be true and accurate. however, under no circumstances shall zmd ag be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical dat a. zmd ag hereby expressly disclaims any liability of zmd ag to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of zmd ag for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 89 of 90 appendix c ziol2xxx line fail detector the following description of the line-fail (lf) detectio n feature assumes the utilization of both channels in device mode. in the case one channel is used only, the number of failures that can be detected with the lf detector will be reduced accordingly. the following supply failures ( table 10.1 ) shall be detected or shall not cause undefined or malfun ctions of the device (sensor/ actuator). for more information about the line-fail detector as part of the power-fail detection feature of the ziol2xxx ics, please refer to chapter 3.5 . table 10.1 abnormal power supply situations number failure ic supply ic function f1 l+ break f2 l- break f3 l+ and l- break after the break occurred the ic is supplied by the decoupling caps which are between vdd and vss and lr_out and vss, respectively. in addition to that the ic might get ?supply power? via incoming (toggling) cable signals. as long as the ic has sufficient supply power (which is normally - at least for some milliseconds - the case), the lf function will detect this as line_fault event and will rise an exception. this exception can be signaled to the c via the int_l signal if configured accordingly. customer recommendation: subsequently the c shall stop any communication and shall handle (e.g. signal) the power fail situation. f4 24v power supply falsely interconnected to com/aux in combination with f1, f2, or f3. the ic is permanently powered via the com/aux external protection diodes (and internal parasitic diodes). the lf function will detect this as line_fault event and will raise an exception. this exception can be signaled to the c via the int_l signal if configured accordingly. customer recommendation: subsequently the c shall stop any communication and shall handle (e.g. signal) the power fail situation (e.g. by influencing signaling leds). f5 correct interconnection of the 24v power supply to l+ and l- but in addition to that is the 24v power supply falsely interconnected no difference to the regular power supply situation. the lf detector will not act in this situation. however, the ic protec tion is provided by the overload and over temperature protection feature.
ziol2xxx ? ic family io-link compliant hv line driver ic family data sheet january 31, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 90 of 90 number failure ic supply ic function to com/aux. f6 reverse interconnection of the 24v power supply to l+ and l-. the reverse polarity protection diodes prevent a power supply of the ic. no power ? no function. f7 reverse interconnection of the 24v power supply to l+ and l- but in addition to that is the 24v power supply falsely interconnected to com/aux. also in combination with f1 or f2. the ic is permanently powered via the com/aux external protection diodes (and internal parasitic diodes). a similar situation is if the ic gets ?supply power? via incoming (toggling) cable signals. the lf function will detect this as line_fault event and will raise an exception. this exception can be signaled to the c via the int_l signal if configured accordingly. customer recommendation: subsequently the c shall stop any communication and shall handle (e.g. signal) the power fail situation. f8 the voltage of the regular 24v power supply drops under 8v the control circuit of the ic is powered regularly but the hv driver may cause malfunction since the voltage at the vdd pin dropped below 8v. the uv function will detect this as under_voltage event and will raise an exception unconditionally. sales and further information www.zmdi.com sales@zmdi.com zentrum mikroelektronik dresden ag grenzstrasse 28 01109 dresden germany zmd america, inc. 8413 excelsior drive suite 200 madison, wi 53717 usa zentrum mikroelektronik dresden ag, japan office 2nd floor, shinbashi tokyu bldg. 4-21-3, shinbashi, minato-ku tokyo, 105-0004 japan zmd far east, ltd. 3f, no. 51, sec. 2, keelung road 11052 taipei taiwan phone +49 (0)351.8822.7465 fax +49 (0)351.8822.87465 phone +1 (608) 829-1987 fax +1 (631) 549-2882 phone +81.3.6895.7410 fax +81.3.6895.7301 phone +886 2 2377 8189 fax +886 2 2377 8199 disclaimer : this information applies to a product under development. its characteristics and specifications are preliminary and subject to change without notice. zentrum mikroelektronik dresden ag (zmd ag) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. t he information furnished hereby is believed to be true and accurate. however, under no circumstances shall zmd ag be liable to any customer, licensee, or any other third party for an y special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical dat a. zmd ag hereby expressly disclaims any liability of zmd ag to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of zmd ag for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise.
mouser electronics authorized distributor click to view pricing, inventory, delivery & lifecycle information: zmdi: ? ziol2201bi1r? ziol2201bi1w? ziol2211bi1r? ziol2211bi1w? ziol2401bi1r? ziol2401bi1w? ziol2411bi1r? ziol2411bi1w

▲Up To Search▲

Price & Availability of ZIOL2202

	To Download ZIOL2202 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .