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| 71713hkpc 20111124-s00003 no.a2197-1/35 http://onsemi.com semiconductor components industries, llc, 2013 july, 2013 ver.1.02 lc87f1k64a overview the lc87f1k64a is an 8-bit microcontroller that, integrates on a single chip a number of hardware features such as 64k-byte flash rom, 8192-byte ram, an on-chip debugger, a sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer (may be divided into 8-bit timer s or pwms), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, two channels of synchronou s sio interface with automatic data transfer capabilities, an asynchronous/synchr onous sio interface, a single-master i 2 c/synchronous sio interface, a uart interface (full duplex), a full/low-speed usb interface (host control function) 2 ports, a 12-bit 12-channel ad converter, two channels of 12-bit pwm, a system clock frequency divider, an infrared remote control receiver circuit, an internal reset circuit, and a 44-source 10-vector interrupt feature. features flash rom ? 65536 8 bits ? capable of on-board programming with a wide range of supply voltage from 3.0 to 5.5v ? block-erasable in 128-byte units ? data written in 2-byte units ram ? 8192 9 bits package form ? sqfp48 (7 7): lead-/halogen-free product bus cycle time ? 83.3ns (when cf=12mhz) note: the bus cycle time here refers to the rom read speed. minimum instruction cycle time (tcyc) ? 250ns (when cf=12mhz) cmos ic 8-bit microcontroller with usb-host controller 64k-byte flash rom / 8k-byte ram / 48-pin orderin g numbe r : ena2197 sqfp48(7x7) sqfp48(7x7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (0.75) 112 13 24 25 36 37 48 ordering information see detailed ordering and shipping informat ion on page 35 of this data sheet. * this product is licensed from silicon storage technology, inc. (usa).
lc87f1k64a no.a2197-2/35 ports ? i/o ports ports whose input/output can be specified in 1-bit units: 34 (p00 to p07, p10 to p17, p20 to p25, p30 to p34, p70 to p73, pwm0, pwm1, xt2) ? usb ports 4 (uhad+, uhad?, uhbd+, uhbd?) ? dedicated oscillator ports 2 (cf1, cf2) ? input-only port (also used for the oscillator) 1 (xt1) ? reset pin 1 ( res ) ? power supply pins 6 (v ss 1 to 3, v dd 1 to 3) timers ? timer 0: 16-bit timer/counter with 2 capture registers mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) mode 2: 16-bit timer with an 8-bit programmabl e prescaler (with two 16- bit capture registers) mode 3: 16-bit counter (with two 16-bit capture registers) ? timer 1: 16-bit timer/counter that supports pwm/toggle output mode 0: 8-bit timer with an 8-bit prescaler (with toggle output) + 8-bit timer/counter with an 8-bit prescaler (with toggle output) mode 1: 8-bit pwm with an 8-bit prescaler 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle output) (toggle output also possible from low-order 8 bits.) mode 3: 16-bit timer with an 8-bit prescaler (with toggle output) (low-order 8 bits can be used as a pwm output.) ? timer 4: 8-bit timer with a 6-bit prescaler ? timer 5: 8-bit timer with a 6-bit prescaler ? timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) ? timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) ? base timer 1) the clock can be selected fr om among a subclock (32.768khz crystal oscillator), low-speed rc oscillator clock, system clock, and timer 0 prescaler output. 2) interrupts programmable in 5 different time schemes. serial interfaces ? sio0: synchronous serial interface 1) lsb first/msb first selectable 2) transfer clock cycle: 4/3 to 512/3 tcyc 3) continuous automatic data transmission (1 to 256 bits can be specified in 1-bit units) (suspension and resumption of data transfer possible in 1-byte units) ? sio1: 8-bit asynch ronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clock) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrate) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clock) mode 3: bus mode 2 (start detection, 8 data bits, stop detection) ? sio4: synchronous serial interface 1) lsb first/msb first selectable 2) transfer clock cycle: 4/3 to 1020/3 tcyc 3) continuous automatic data transmission (1 to 8192 bytes can be specified in 1-byte units) (suspension and resumption of data transmission possible in 1-byte units or in word units) 4) clock polarity can be selected. 5) crc16 calculator circuit built- in ? smiic0: single-master i 2 c/8-bit synchronous sio mode 0: communication in single-master mode. mode 1: 8-bit synchronous serial i/o (data msb first) lc87f1k64a no.a2197-3/35 full duplex uart 1) data length: 7/8/9 bits selectable 2) stop bits: 1 bit (2 bits in continuous transmission mode) 3) parity bits: none/even/odd selectable (for 8-bit data only) 4) baudrate: 16/3 to 8192/3 tcyc ad converter: 12 bits 12 channels pwm: variable frequency 12-bit pwm 2 channels infrared remote control receiver circuit 1) noise rejection function (noise filter time constant: approx. 120 s when the 32.768khz crystal oscillator is selected as the reference clock) 2) supports data encoding systems such as ppm (pulse position modulation) and manchester encoding. 3) x'tal hold mode release function usb interface (host control function) 2 ports 1) supports full-speed (12mbps) and low-speed (1.5mbps) specifications. 2) supports four transfer types (contro l transfer, bulk transfer , interrupt transfer, and isochronous transfer). audio interface 1) sampling frequencies (fs): 8khz/11.025khz/12khz/16khz/22.05khz/24khz/32khz/44.1khz/48khz 2) master clock: 256fs/384fs 3) bit clock: 48fs/64fs 4) data bit length: 16bits/18bits/20bits/24bits 5) lsb first/msb first selectable. 6) left justified/right justified/i2s format selectable watchdog timer ? external rc time constant type 1) interrupt generation/reset generation selectable 2) operation in halt/hold mode can be selected from ?continue operation? and ?suspend operation.? ? internal timer type 1) capable of generating a internal reset signal on an overflow of the timer running on the low-speed rc oscillator clock, or subclock. 2) operation in halt/hold mode can be selected from among ?continue count operation,? ?suspend operation,? and ?retain the count value.? clock output function 1) can output a clock with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillator clock selected as the system clock. 2) can output the source oscillator clock for the subclock. lc87f1k64a no.a2197-4/35 interrupts ? 44 sources, 10 vectors 1) provides three levels (low (l), high (h), and highest (x)) of multiplex interrupt contro l. any interrupt request of the level equal to or lower than the current interrupt level is not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the lowest vector address is given priority. no. vector level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4/uhc-a bus active/uhc-b bus active/remote control receive 4 0001bh h or l int3/int5/base timer 5 00023h h or l t0h/int6/uhc-a device connected, disconnected, resumed 6 0002bh h or l t1l/t1h/int7/aif start/smiic0/uhc-b device connected, disconnected, resumed 7 00033h h or l sio0/uart1 reception completed 8 0003bh h or l sio1/sio4/uart1 buffer em pty/uart1 transmission completed/aif end 9 00043h h or l adc/t6/t7/uhc-ack/uhc-nak/uhc error/uhc-stall 10 0004bh h or l port 0/pwm0/pwm1/t4/t5/uhc-sof ? priority levels x > h > l ? when interrupts of the same level occur at the same time, the interrupt with the lowest vector address is given priority. subroutine stack levels: up to 4096 leve ls (the stack is allocated in ram.) high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) oscillator circuit and pll ? medium-speed rc oscillator circuit (internal): for system clock (approx. 1mhz) ? low-speed rc oscillator circuit (internal): for system clock, timer, and watchdog timer (approx. 30khz) ? cf oscillator circuit: for system clock ? crystal oscillator circuit: for system clock and time-of-day clock ? pll circuit (internal): for usb interface (s ee fig. 5) and audio interface (see fig. 6) internal reset functions ? power-on reset (por) function 1) por is activated at power-on. 2) por release voltage can be selected from 8 levels (1.67v, 1.97v, 2.07v, 2.37v, 2.57v, 2.87v, 3.86v, and 4.35v) by setting options. ? low voltage detection reset (lvd) function 1) lvd and por functions are combined to generate resets when power is turned on and when power voltage falls below a threshold level. 2) the use/disuse of the lvd function and the low voltage threshold level (7 levels: 1.91v, 2.01v, 2.31v, 2.51v, 2.81v, 3.79v, and 4.28v) can be selected by setting options. lc87f1k64a no.a2197-5/35 standby function ? halt mode: halts instruction execution while allowi ng the peripheral circuits to continue operation. 1) oscillators do not stop automatically. 2) there are three ways of releasing hold mode. (1) setting the reset pin to a low level. (2) generating a reset signal by watchdog timer or low-voltage detection (3) occurrence of an interrupt ? hold mode: suspends instruction execution and operation of the peripheral circuits. 1) the pll, cf, rc and crystal oscilla tors automatically stop operation. note: low-speed rc oscillator is controlled directly by th e watchdog timer and its oscillation in standby mode is also controlled. 2) there are five ways of releasing hold mode. (1) setting the reset pin to a low level (2) generating a reset signal by the watchdog timer or low-voltage detection (3) establishing an interrupt source at one of int0, int1, int2, int4, and int5 pins * int0 and int1 hold mode release is available only when level detection is configured. (4) establishing an interrupt source at port 0 (5) establishing an bus active interrupt source in the usb host control circuit ? x'tal hold mode: suspends instruction execution and the oper ation of the peripheral circ uits except the base timer and infrared remote control receiver circuit. 1) the pll, cf and rc oscillators automatically stop operation. note: low-speed rc oscillator is controlled directly by the watchdog timer and its oscillation in standby mode is also controlled. note: the low-speed rc oscillator retains the state that is established on entry into x'tal hold mode if the base timer is running with the low-speed rc oscillator selected as the base timer input clock source. 2) the state of crystal oscillator established when the x'tal hold mode is entered is retained. 3) there are seven ways of releasing x'tal hold mode. (1) setting the reset pin to a low level (2) generating a reset signal by the watchdog timer or low-voltage detection (3) establishing an interrupt source at one of int0, int1, int2, int4, and int5 pins * int0 and int1 x'tal hold mode release is ava ilable only when level detection is configured. (4) establishing an interrupt source at port 0 (5) establishing an interrupt source in the base timer circuit (6) establishing an interrupt source in th e infrared remote control receiver circuit (7) establishing an bus active interrupt source in the usb host control circuit development tools ? on-chip debugger: tcb87?type b + lc87f1k64a or tcb87?type c (3-wire communication cable) + lc87f1k64a flash rom programming board package programming board sqfp48 (77) w87f55256sq lc87f1k64a no.a2197-6/35 flash rom programmer maker model supported version device flash support group company (fsg) single af9709c rev.03.32 and later 87F064JU af9101/af9103 (main unit) (fsg model) flash support group company (fsg) + our company (note 1) onboard single/ganged sib87 type c (interface driver) (our company model) (note 2) lc87f1k64a single/ganged skk/skk type c (sanyo fws) our company onboard single/ganged skk-dbg type c (sanyo fws) application version 1.07 and later chip data version 2.39 and later lc87f1k64 (further information on the af series) flash support group company (toa electronics, inc.) phone: 053-459-1050 e-mail: sales@j- fsg.co.jp note 1: pc-less standalone onboard programming is possible using the fsg onboard programmer (af9101/af9103) and the serial interface driver (sib87 type c) provided by our company in pair. note 2: dedicated programming device and program are required depending on the programming conditions. contact our company or fsg if you have any questions or difficulties regarding this matter. lc87f1k64a no.a2197-7/35 package dimensions unit : mm (typ) 3163b pin assignment sqfp48 (77) (lead-/halogen-free product) sqfp48(7x7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (0.75) 112 13 24 25 36 37 48 uhbd+ uhbd- p25/int5 p24/int5/int7/sck4 p23/int4/si4 p22/int4/so4 p21/int4 p20/int4/int6 p07/an7/t7o/lrck p06/an6/t6o/bclk p05/an5/cko/sdat p04/an4/dbgp2 p73/int3/t0in/rmin res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p10/so0 p11/si0/sb0 p12/sck0 p13/so1/sm0ck1 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 uhad- uhad+ v dd 3 v ss 3 p34/ufilt p33/afilt p32 p31/urx1 p30/utx1 p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in 24 23 22 21 20 19 18 17 16 15 14 13 p03/an3/dbgp1 p02/an2/dbgp0 p01/an1 p00/an0 v ss 2 v dd 2 pwm0/mclko pwm1/mclki p17/t1pwmh/buz/sm0ck0 p16/t1pwml/sm0da0 p15/sck1/sm0do p14/si1/sb1/sm0da1 37 38 39 40 41 42 43 44 45 46 47 48 lc87f1k64a top view lc87f1k64a no.a2197-8/35 sqfp48 name sqfp48 name 1 p73/int3/t0in/rmin 25 p04/an4/dbgp2 2 res 26 p05/an5/cko/sdat 3 xt1/an10 27 p06/an6/t6o/bclk 4 xt2/an11 28 p07/an7/t7o/lrck 5 v ss 1 29 p20/int4/int6 6 cf1 30 p21/int4 7 cf2 31 p22/int4/so4 8 v dd 1 32 p23/int4/si4 9 p10/so0 33 p24/int5/int7/sck4 10 p11/si0/sb0 34 p25/int5 11 p12/sck0 35 uhbd- 12 p13/so1/sm0ck1 36 uhbd+ 13 p14/si1/sb1/sm0da1 37 uhad- 14 p15/sck1/sm0do 38 uhad+ 15 p16/t1pwml/sm0da0 39 v dd 3 16 p17/t1pwmh/buz/sm0ck0 40 v ss 3 17 pwm1/mclki 41 p34/ufilt 18 pwm0/mclko 42 p33/afilt 19 v dd 2 43 p32 20 v ss 2 44 p31/urx1 21 p00/an0 45 p30/utx1 22 p01/an1 46 p70/int0/t0lcp/an8 23 p02/an2/dbgp0 47 p71/int1/t0hcp/an9 24 p03/an3/dbgp1 48 p72/int2/t0in lc87f1k64a no.a2197-9/35 system block diagram interrupt control rom standby control clock generator cf x?tal rc ir pla pc bus interface port 0 port 1 acc b register c register alu psw rar ram stack pointer watchdog timer base timer pwm1 int0 to int7 noise filter sio0 port 2 usb pll port 7 port 3 adc sio1 timer 0 timer 1 pwm0 timer 6 timer 7 uart1 on-chip debugger usb host timer 4 timer 5 sio4 audio interface ifr control receiver circuit wdt reset control reset circuit (lvd/por) res smiic0 lc87f1k64a no.a2197-10/35 pin description pin name i/o description option v ss 1, v ss 2, v ss 3 - -power supply no v dd 1, v dd 2 - +power supply no v dd 3 - usb reference voltage yes port 0 p00 to p07 i/o ? 8-bit i/o port ? i/o can be specified in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? hold release input ? port 0 interrupt input ? pin functions ad converter input port: an0 to an7 (p00 to p07) on-chip debugger pins: dbgp0 to dbgp2 (p02 to p04) p05: system clock output / audio interface sdat i/o p06: timer 6 toggle output / audio interface bclk i/o p07: timer 7 toggle output / audio interface lrck i/o yes port 1 p10 to p17 i/o ? 8-bit i/o port ? i/o can be specified in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p10: sio0 data output p11: sio0 data input / bus i/o p12: sio0 clock i/o p13: sio1 data output / smiic0 clock i/o p14: sio1 data input / bus i/o / smiic0 bus i/o / data input p15: sio1 clock i/o / smiic0 data ou tput (used in 3-wire sio mode) p16: timer 1 pwml output / smiic0 bus i/o / data input p17: timer 1 pwmh output / buzz er output / smiic0 clock i/o yes port 2 ? 6-bit i/o port ? i/o can be specified in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p20 to p23: int4 input / hold re lease input / timer 1 event input / timer 0l capture input / timer 0h capture input p24 to p25: int5 input / hold re lease input / timer 1 event input / timer 0l capture input / timer 0h capture input p20: int6 input / timer 0l capture 1 input p22: sio4 data i/o p23: sio4 data i/o p24: int7 input / timer 0h ca pture 1 input / sio4 clock i/o interrupt acknowledge types rising falling rising & falling h level l level int4 enable enable enable disable disable int5 enable enable enable disable disable int6 enable enable enable disable disable int7 enable enable enable disable disable p20 to p25 i/o yes port 3 p30 to p34 i/o ? 5-bit i/o port ? i/o can be specified in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p30: uart1 transmit p31: uart1 receive p33: connected to audio interface pll filter circuit (see fig. 6). p34: connected to usb interface pl l filter circuit (see fig. 5). yes continued on next page. lc87f1k64a no.a2197-11/35 continued from preceding page. pin name i/o description option port 7 ? 4-bit i/o port ? i/o can be specified in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p70: int0 input / hold release input / timer 0l capture input / watchdog timer output p71: int1 input / hold release input / timer 0h capture input p72: int2 input / hold release input / timer 0 event input / timer 0l capture input / high-speed clock counter input p73: int3 input (input with noise filter) / timer 0 event input / timer 0h capture input / infrared remote control receiver input ad converter input port: an8 (p70), an9 (p71) interrupt acknowledge types rising falling rising & falling h level l level int0 enable enable disable enable enable int1 enable enable disable enable enable int2 enable enable enable disable disable int3 enable enable enable disable disable p70 to p73 i/o no pwm0 pwm1 i/o pwm0 and pwm1 output port general-purpose input port ? pin functions pwm0: audio interface master clock output pwm1: audio interface master clock input no uhad- uhad+ i/o usb-a port data i/o pin / general-purpose i/o port no uhbd- uhbd+ i/o usb-b port data i/o pin / general-purpose i/o port no res i/o external reset input / internal reset output no xt1 i ? 32.768khz crystal resonator input ? pin functions general-purpose input port ad converter input port: an10 no xt2 i/o ? 32.768khz crystal resonator output ? pin functions general-purpose i/o port ad converter input port: an11 no cf1 i ceramic/crystal resonator input no cf2 o ceramic/crystal resonator output no lc87f1k64a no.a2197-12/35 on-chip debugger pin treatment for the treatment of the on-chip debugger pins, refer to the separately available documents entitled "rd87 on-chip debugger installation manual." recommended unused pin treatment recommended unused pin treatment pin name board software p00 to p03, p05 to p07 open set output low. p04 pull-down with a 100k resistor. - p10 to p17 open set output low. p20 to p25 open set output low. p30 to p34 open set output low. p70 to p73 open set output low. pwm0, pwm1 open set output low. uhad+, uhad- open set output low. uhbd+, uhbd- open set output low. xt1 pull-down with a resistor of 100k or lower. - xt2 open set output low. note: since p34 is multiplexed with ufilt, it must be configured for input when the usb function is to be used. since p33 is multiplexed with afilt, it must be configured for input when the audio in terface pll circuit is to be used. port output types the table below lists the type of port output and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in output mode. port name option selected in units of option type output type pull-up resistor 1 cmos programmable p00 to p07 p10 to p17 p20 to p25 p30 to p34 1 bit 2 n-channel open drain programmable p70 - no n-channel open drain programmable p71 to p73 - no cmos programmable pwm0, pwm1 - no cmos no uhad+, uhad- uhbd+, uhbd- - no cmos no xt1 - no input only no xt2 - no 32.768khz crystal resonator output (n-channel open drain when in general-purpose output mode) no lc87f1k64a no.a2197-13/35 user option table option name option to be applied on flash-rom version option selected in units of option selection cmos p00 to p07 1 bit n-channel open drain cmos p10 to p17 1 bit n-channel open drain cmos p20 to p25 1 bit n-channel open drain cmos port output type p30 to p34 1 bit n-channel open drain 00000h program start address - - 0fe00h use usb regulator - non-use use usb regulator (hold mode) - non-use use usb regulator usb regulator (halt mode) - non-use enable main clock 8mhz selection - - disable enable: use detection function - disable: non-use low-voltage detection reset function detection level - 7 levels power-on reset function power-on reset level - 8 levels lc87f1k64a no.a2197-14/35 usb reference power option when a voltage 4.5 to 5.5v is supplied to v dd 1 and the internal usb reference voltage circuit is activated, the reference voltage for usb port output is generated. the ac tive/inactive state of the reference voltage circuit can be switched by selecting an option. the procedure for making the option selection is described below. (1) (2) (3) (4) usb regulator use use use non-use usb regulator at hold mode use non-use n on-use non-use option settings usb regulator at halt mode use non-use use non-use normal mode active active active inactive hold mode active inactive inactive inactive reference voltage circuit state halt mode active inactive active inactive ? when the usb reference voltage circuit is made inactive, th e level of the reference voltage for the usb port output is equal to v dd 1. ? selection (2) or (3) can be used to set the refe rence voltage circuit inactive in hold or halt mode. ? when the reference voltage circuit is activated, the current drain increases by approximately 100 a compared with when the reference voltage circuit is inactive. example 1: v dd 1=v dd 2=3.3v ? inactivating the reference voltage circuit (selection (4)). ? connecting v dd 3 to v dd 1 and v dd 2. example 2: v dd 1=v dd 2=5.0v ? activating the reference volta ge circuit (selection (1)). ? isolating v dd 3 from v dd 1 and v dd 2, and connecting capacitor between v dd 3 and v ss . v ss 1 v ss 2v ss 3 v dd 1 v dd 2 v dd 3 power supply 3.3v ic uhad+ /uhbd+ uhad- / uhbd- ufilt 15k to usb connector 33 5pf 0 2.2 2.2 to usb connector 33 5pf 2.2 (note: do not apply the voltage of more than 3.6v to uhad+, uhad-, uhbd+ and uhbd- when the refere nce voltage circuit is active . lc87f1k64a no.a2197-15/35 absolute maximum ratings at ta = 25 c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1=v dd 2=v dd 3 -0.3 +6.5 input voltage v i (1) xt1, cf1, res -0.3 v dd +0.3 input/output voltage v io (1) ports 0, 1, 2, 3, 7 pwm0, pwm1 xt2 -0.3 v dd +0.3 v ioph(1) ports 0, 1, 2 ? when cmos output type is selected ? per 1 applicable pin -10 ioph(2) pwm0, pwm1 ? per 1 applicable pin -20 peak output current ioph(3) port 3 p71 to p73 ? when cmos output type is selected ? per 1 applicable pin -5 iomh(1) ports 0, 1, 2 ? when cmos output type is selected ? per 1 applicable pin -7.5 iomh(2) pwm0, pwm1 per 1 applicable pin -15 average output current (note 1-1) iomh(3) port 3 p71 to p73 ? when cmos output type is selected ? per 1 applicable pin -3 ioah(1) ports 0, 2 to tal current of all applicable pins -25 ioah(2) port 1 pwm0, pwm1 total current of all applicable pins -25 ioah(3) ports 0, 1, 2 pwm0, pwm1 total current of all applicable pins -45 ioah(4) port 3 p71 to p73 total current of all applicable pins -10 high level output current total output current ioah(5) uhad+, uhad- uhbd+, uhbd- total current of all applicable pins -50 iopl(1) p02 to p07 ports 1, 2 pwm0, pwm1 per 1 applicable pin 20 iopl(2) p00, p01 per 1 applicable pin 30 peak output current iopl(3) ports 3, 7 xt2 per 1 applicable pin 10 ioml(1) p02 to p07 ports 1, 2 pwm0, pwm1 per 1 applicable pin 15 ioml(2) p00, p01 per 1 applicable pin 20 average output current (note 1-1) ioml(3) ports 3, 7 xt2 per 1 applicable pin 7.5 ioal(1) ports 0, 2 total current of all applicable pins 45 ioal(2) port 1 pwm0, pwm1 total current of all applicable pins 45 ioal(3) ports 0, 1, 2 pwm0, pwm1 total current of all applicable pins 80 ioal(4) ports 3, 7 xt2 total current of all applicable pins 15 low level output current total output current ioal(5) uhad+, uhad- uhbd+, uhbd- total current of all applicable pins 50 ma allowable power dissipation pd max sqfp48(7 7) ta=-40 to +85c 140 mw operating ambient temperature topr -40 +85 storage ambient temperature tstg -55 +125 c note 1-1: the average output current is an average of current values measured over 100ms intervals. stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty. lc87f1k64a no.a2197-16/35 allowable operating conditions at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit 0.245 s tcyc 200 s 3.0 5.5 0.245 s tcyc 0.383 s usb circuit active. 3.0 5.5 operating supply voltage (note 2-1) v dd (1) v dd 1=v dd 2=v dd 3 0.490 s tcyc 200 s except for onboard programming mode 2.7 5.5 memory retention supply voltage vhd v dd 1=v dd 2=v dd 3 ram and register contents are retained in hold mode 2.0 5.5 v ih (1) ports 0, 1, 2, 3, 7 pwm0, pwm1 2.7 to 5.5 0.3v dd +0.7 v dd high level input voltage v ih (2) xt1, xt2, cf1, res 2.7 to 5.5 0.75v dd v dd v il (1) 4.0 to 5.5 v ss 0.1v dd +0.4 v il (2) ports 1, 2, 3, 7 2.7 to 4.0 v ss 0.2v dd v il (3) 4.0 to 5.5 v ss 0.15v dd +0.4 v il (4) port 0 pwm0, pwm1 2.7 to 4.0 v ss 0.2v dd low level input voltage v il (5) xt1, xt2, cf1, res 2.7 to 5.5 v ss 0.25v dd v 3.0 to 5.5 0.245 200 usb circuit active. 3.0 to 5.5 0.245 0.383 instruction cycle time (note 2-2) tcyc except for onboard programming mode 2.7 to 5.5 0.490 200 s ? cf2 pin open ? system clock frequency division ratio =1/1 ? external system clock duty =505% 3.0 to 5.5 0.1 12 external system clock frequency fexcf(1) cf1 ? cf2 pin open ? system clock frequency division ratio =1/1 ? external system clock duty =505% 2.7 to 5.5 0.1 6 mhz fmcf cf1, cf2 12mhz ceramic oscillation mode see fig. 1. 3.0 to 5.5 12 fmrc internal medium-speed rc oscillation 2.7 to 5.5 0.5 1.0 2.0 mhz fmsrc internal low-speed rc oscillation 2.7 to 5.5 15 30 60 oscillation frequency range (note 2-3) fsx'tal xt1, xt2 32.768khz crystal oscillation mode see fig. 2. 2.7 to 5.5 32.768 khz note 2-1: v dd must be held greater than or equal to 3.0v in the flash rom onboard programming mode. note 2-2: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. note 2-3: see tables 1 and 2 for the oscillation constants. lc87f1k64a no.a2197-17/35 electrical characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit i ih (1) ports 0, 1, 2, 3, 7 res pwm0, pwm1 output disabled pull-up resistor off v in =v dd (including output tr's off leakage current) 2.7 to 5.5 1 i ih (2) xt1, xt2 input port configuration v in =v dd 2.7 to 5.5 1 high level input current i ih (3) cf1 v in =v dd 2.7 to 5.5 15 i il (1) ports 0, 1, 2, 3, 7 res pwm0, pwm1 output disabled pull-up resistor off v in =v ss (including output tr's off leakage current) 2.7 to 5.5 -1 i il (2) xt1, xt2 input port configuration v in =v ss 2.7 to 5.5 -1 low level input current i il (3) cf1 v in =v ss 2.7 to 5.5 -15 a v oh (1) i oh =-1ma 4.5 to 5.5 v dd -1 v oh (2) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (3) ports 0, 1, 2, 3 p71 to p73 i oh =-0.2ma 2.7 to 5.5 v dd -0.4 v oh (4) i oh =-10ma 4.5 to 5.5 v dd -1.5 v oh (5) i oh =-1.6ma 3.0 to 5.5 v dd -0.4 high level output voltage v oh (6) pwm0, pwm1 p05 to p07 (note 3-1) i oh =-1ma 2.7 to 5.5 v dd -0.4 v ol (1) i ol =30ma 4.5 to 5.5 1.5 v ol (2) i ol =5ma 3.0 to 5.5 0.4 v ol (3) p00, p01 i ol =2.5ma 2.7 to 5.5 0.4 v ol (4) i ol =10ma 4.5 to 5.5 1.5 v ol (5) i ol =1.6ma 3.0 to 5.5 0.4 v ol (6) ports 0, 1, 2 pwm0, pwm1 xt2 i ol =1ma 2.7 to 5.5 0.4 v ol (7) i ol =1.6ma 3.0 to 5.5 0.4 low level output voltage v ol (8) ports 3, 7 i ol =1ma 2.7 to 5.5 0.4 v rpu(1) 4.5 to 5.5 15 35 80 pull-up resistance rpu(2) ports 0, 1, 2, 3, 7 v oh =0.9v dd 2.7 to 4.5 18 50 150 k hysteresis voltage vhys res ports 1, 2, 3, 7 2.7 to 5.5 0.1v dd v pin capacitance cp all pins for pins other than those under test: v in =v ss f=1mhz ta=25c 2.7 to 5.5 10 pf note 3-1: when the cko system clock out put function (p05) or the audio interface output function (p05 to p07) is used. lc87f1k64a no.a2197-18/35 serial i/o characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit frequency tsck(1) 2 low level pulse width tsckl(1) 1 tsckh(1) see fig. 9. 1 tsckha(1a) ? continuous data transmission/ reception mode ? usb, aif, sio4 not used at the same time. ? see fig. 9. ? (note 4-1-2) 4 tsckha(1b) ? continuous data transmission/ reception mode ? usb used at the same time ? aif, sio4 not used at the same time. ? see fig. 9. ? (note 4-1-2) 7 input clock high level pulse width tsckha(1c) sck0(p12) ? continuous data transmission/ reception mode ? usb, aif, sio4 used at the same time. ? see fig. 9. ? (note 4-1-2) 2.7 to 5.5 9 frequency tsck(2) 4/3 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) ? when cmos output type is selected. ? see fig. 9. 1/2 tsck tsckha(2a) ? continuous data transmission/ reception mode ? usb, aif, sio4 not used at the same time. ? when cmos output type is selected. ? see fig. 9. tsckh(2) +2tcyc tsckh(2) + (10/3)tcyc tsckha(2b) ? continuous data transmission/ reception mode ? usb used at the same time ? aif, sio4 not used at the same time. ? when cmos output type is selected. ? see fig. 9. tsckh(2) +2tcyc tsckh(2) + (19/3)tcyc serial clock output clock high level pulse width tsckha(2c) sck0(p12) ? continuous data transmission/ reception mode ? usb, aif, sio4 used at the same time ? when cmos output type is selected. ? see fig. 9. 2.7 to 5.5 tsckh(2) +2tcyc tsckh(2) + (25/3)tcyc tcyc note 4-1-1: these specifications are theoretical values. ma rgins must be allowed according to the actual operating conditions. note 4-1-2: in an application where the serial clock input is to be used in continuous data transmission/reception mode, the time from si0run being set when serial clock is high to the falling edge of the first serial clock must be longer than tsckha. continued on next page. lc87f1k64a no.a2197-19/35 continued from preceding page. specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit data setup time tsdi(1) 0.03 serial input data hold time thdi(1) sb0(p11), si0(p11) ? must be specified with respect to rising edge of sioclk ? see fig. 9. 2.7 to 5.5 0.03 tddo(1) ? continuous data transmission/ reception mode ? (note 4-1-3) (1/3)tcyc +0.05 input clock tddo(2) ? synchronous 8-bit mode ? (note 4-1-3) 1tcyc +0.05 serial output output clock output delay time tddo(3) so0(p10), sb0(p11) (note 4-1-3) 2.7 to 5.5 (1/3)tcyc +0.05 s note 4-1-3: must be specified with respect to falling edge of sioclk. must be defined as the time up to the beginning of output state change in open drain output mode. see fig. 9. 2. sio1 serial i/o characteristics (note 4-2-1) specification parameter symbol pins/ remarks conditions v dd [v] min typ max unit frequency tsck(3) 2 low level pulse width tsckl(3) 1 input clock high level pulse width tsckh(3) sck1(p15) ? see fig. 9. 2.7 to 5.5 1 frequency tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ? when cmos output type is selected. ? see fig. 9. 2.7 to 5.5 1/2 tsck data setup time tsdi(2) 0.03 serial input data hold time thdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig. 9. 2.7 to 5.5 0.03 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time up to the beginning of output state change in open drain output mode. ? see fig. 9. 2.7 to 5.5 (1/3)tcyc +0.05 s note 4-2-1: these specifications are theoretical values. ma rgins must be allowed according to the actual operating conditions. lc87f1k64a no.a2197-20/35 3. sio4 serial i/o characteristics (note 4-3-1) specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit frequency tsck(5) 2 low level pulse width tsckl(5) 1 tsckh(5) see fig. 9. 1 tsckha(5a) ? usb, sio0 continuous transfer mode, aif not used at the same time. ? see fig. 9. ? (note 4-3-2) 4 tsckha(5b) ? usb used at the same time. ? sio0 continuous transfer mode, aif not used at the same time. ? see fig. 9. ? (note 4-3-2) 7 input clock high level pulse width tsckha(5c) sck4(p24) ? usb, sio0 cont inuous transfer mode used at the same time. ? aif not used at the same time. ? see fig. 9. ? (note 4-3-2) 2.7 to 5.5 10 frequency tsck(6) 4/3 tcyc low level pulse width tsckl(6) 1/2 tsckh(6) ? when cmos output type is selected. ? see fig. 9. 1/2 tsck tsckha(6a) ? usb, sio0 continuous transfer mode aif not used at the same time. ? when cmos output type is selected. ? see fig. 9. tsckh(6) + (5/3)tcyc tsckh(6) + (10/3)tcyc tsckha(6b) ? usb used at the same time. ? sio0 continuous transfer mode aif not used at the same time. ? when cmos output type is selected. ? see fig. 9. tsckh(6) + (5/3)tcyc tsckh(6) + (19/3)tcyc serial clock output clock high level pulse width tsckha(6c) sck4(p24) ? usb, sio0 cont inuous transfer mode used at the same time ? aif not used at the same time. ? when cmos output type is selected. ? see fig. 9. 2.7 to 5.5 tsckh(6) + (5/3)tcyc tsckh(6) + (28/3)tcyc tcyc data setup time tsdi(3) 0.03 serial input data hold time thdi(3) so4(p22), si4(p23) ? must be specified with respect to rising edge of sioclk. ? see fig. 9. 2.7 to 5.5 0.03 serial output output delay time tddo(5) so4(p22), si4(p23) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time up to the beginning of output state change in open drain output mode ? see fig. 9. 2.7 to 5.5 (1/3)tcyc +0.05 s note 4-3-1: these specifications are theoretical values. ma rgins must be allowed according to the actual operating conditions. note 4-3-2: in an application where the serial clock input is to be used, the time from si4run being set when serial clock is high to the falling edge of the first serial clock must be longer than tsckha when continuous data transmission/reception is started. lc87f1k64a no.a2197-21/35 4-1. smiic0 simple sio mode i/o characteristics (note 4-4-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit frequency tsck(7) 4/3 low level pulse width tsckl(7) 2/3 input clock high level pulse width tsckh(7) sm0ck0(p17), sm0ck1(p13) see fig. 9. 2.7 to 5.5 2/3 frequency tsck(8) 4/3 tcyc low level pulse width tsckl(8) 1/2 serial clock output clock high level pulse width tsckh(8) sm0ck0(p17), sm0ck1(p13) ? when cmos output type is selected. ? see fig. 9. 2.7 to 5.5 1/2 tsck data setup time tsdi(4) 0.03 serial input data hold time thdi(4) sm0da0(p16), sm0da1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig. 9. 2.7 to 5.5 0.03 serial output output delay time tddo(6) sm0do(p15), sm0da0(p16), sm0da1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change. ? see fig. 9. 2.7 to 5.5 (1/3)tcyc +0.05 s note 4-4-1: these specifications are theoretical values. ma rgins must be allowed according to the actual operating conditions. lc87f1k64a no.a2197-22/35 4-2. smiic0 i 2 c mode i/o characteristics (note 4-5-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit frequency tscl 5 low level pulse width tscll 2.5 input clock high level pulse width tsclh sm0ck0(p17), sm0ck1(p13) see fig. 11. 2.7 to 5.5 2 frequency tsclx 10 tfilt low level pulse width tscllx 1/2 serial clock output clock highlevel pulse width tsclhx sm0ck0(p17), sm0ck1(p13) must be specified as the time up to the beginning of output state change. 2.7 to 5.5 1/2 tscl sm0ck, sm0da pin input spike suppression time tsp sm0ck0(p17), sm0ck1(p13), sm0da0(p16), sm0da1(p14) see fig. 11. 2.7 to 5.5 1 tfilt input tbuf see fig. 11. 2.5 tfilt ? standard clock mode ? must be specified as the time up to the beginning of output state change. 5.5 bus relinquish time between start and stop output tbufx sm0ck0(p17), sm0ck1(p13), sm0da0(p16), sm0da1(p14) ? high-speed clock mode ? must be specified as the time up to the beginning of output state change. 2.7 to 5.5 1.6 s ? when smiic register control bit shds=0 ? see fig. 11. 2.0 input thd; sta ? when smiic register control bit shds=1 ? see fig. 11. 2.5 tfilt ? standard clock mode ? must be specified as the time up to the beginning of output state change. 4.1 start, restart condition hold time output thd; stax sm0ck0(p17), sm0ck1(p13), sm0da0(p16), sm0da1(p14) ? high-speed clock mode ? must be specified as the time up to the beginning of output state change. 2.7 to 5.5 1.0 s input tsu; sta see fig. 11. 1.0 tfilt ? standard clock mode ? must be specified as the time up to the beginning of output state change. 5.5 restart condition setup time output tsu; stax sm0ck0(p17), sm0ck1(p13), sm0da0(p16), sm0da1(p14) ? high-speed clock mode ? must be specified as the time up to the beginning of output state change. 2.7 to 5.5 1.6 s continued on next page. lc87f1k64a no.a2197-23/35 continued from preceding page. specification parameter symbol pin/remarks conditions v dd [v] min typ max unit input tsu; sto see fig. 11. 1.0 tfilt ? standard clock mode ? must be specified as the time up to the beginning of output state change. 4.9 stop condition setup time output tsu; stox sm0ck0(p17), sm0ck1(p13), sm0da0(p16), sm0da1(p14) ? high-speed clock mode ? must be specified as the time up to the beginning of output state change. 2.7 to 5.5 1.1 s input thd; dat see fig. 11. 0 data hold time output thd; datx sm0ck0(p17), sm0ck1(p13), sm0da0(p16), sm0da1(p14) must be specified as the time up to the beginning of output state change. 2.7 to 5.5 1 1.5 tfilt input tsu; dat see fig. 11. 1 data setup time output tsu; datx sm0ck0(p17), sm0ck1(p13), sm0da0(p16), sm0da1(p14) must be specified as the time up to the beginning of output state change. 2.7 to 5.5 1tscl- 1.5tfilt tfilt note 4-5-1: these specifications are theoretical values. ma rgins must be allowed according to the actual operating conditions. note 4-5-2: the value of tfilt is determined by bits 7 and 6 (brp1 and brp0) of the smic0brg register and the system clock frequency. brp1 brp0 tfilt 0 0 (1/3) tcyc 1 0 1 (1/3) tcyc 2 1 0 (1/3) tcyc 3 1 1 (1/3) tcyc 4 set the value of the brp1 and brp0 bits so that the va lue of tfilt falls within the following value range: 250ns tfilt > 140ns note 4-5-3: for standard clock mode operation, set up the smic0brg register so that the following conditions are satisfied: 250ns tfilt > 140ns brdq (bit5) = 1 scl frequency value 100khz for high-speed clock mode operation, set up the smic 0brg register so that the following conditions are satisfied: 250ns tfilt > 140ns brdq (bit5) = 1 scl frequency value 400khz lc87f1k64a no.a2197-24/35 pulse input conditions at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72), int4(p20 to p23), int5(p24 to p25), int6(p20), int7(p24) ? interrupt source flag can be set. ? event inputs for timer 0/1 are enabled. 2.7 to 5.5 1 tpih(2) tpil(2) int3(p73) when noisefilter time constant is 1/1. ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 2 tpih(3) tpil(3) int3(p73) when noisefilter time constant is 1/32. ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 64 tpih(4) tpil(4) int3(p73) when noisefilter time constant is 1/128. ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 256 tcyc tpil(5) rmin(p73) recognized as a signal by infrared remote control receiver circuit 2.7 to 5.5 4 rmck (note 5-1) high/low level pulse width tpil(6) res resetting is enabled. 2.7 to 5.5 200 s note 5-1: denotes the reference frequency of the infrared re mote control receiver circuit (1tcyc to 128tcyc or source oscillation frequency of the subclock) lc87f1k64a no.a2197-25/35 ad converter characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = 0v <12-bit ad converter mode> specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 12 bit absolute accuracy et (note 6-1) 3.0 to 5.5 16 lsb 4.0 to 5.5 32 115 conversion time tcad see conversion time calculation formulas. (note 6-2) 3.0 to 5.5 64 115 s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(p00) to an7(p07) an8(p70) an9(p71) an10(xt1) an11(xt2) vain=v ss 3.0 to 5.5 -1 a <8-bit ad converter mode> specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 8 bit absolute accuracy et (note 6-1) 3.0 to 5.5 1.5 lsb 4.0 to 5.5 20 90 conversion time tcad see conversion time calculation formulas. (note 6-2) 3.0 to 5.5 40 90 s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 a analog port input current iainl an0(p00) to an7(p07) an8(p70) an9(p71) an10(xt1) an11(xt2) vain=v ss 3.0 to 5.5 -1 a conversion time calculation formulas : 12-bits ad converter mode : tcad (conversion time) = ((52/(ad division ratio))+2) (1/3) tcyc 8-bits ad converter mode : tcad (conversion time) = ((32/(ad division ratio))+2) (1/3) tcyc lc87f1k64a no.a2197-26/35 power-on reset (por) characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol conditions option selected voltage min typ max unit 1.67v 1.55 1.67 1.79 1.97v 1.85 1.97 2.09 2.07v 1.95 2.07 2.19 2.37v 2.25 2.37 2.49 2.57v 2.45 2.57 2.69 2.87v 2.75 2.87 2.99 3.86v 3.73 3.86 3.99 por release voltage porrl select from option (note 7-1) 4.35v 4.21 4.35 4.49 detection voltage unknown state pouks see fig. 13 (note 7-2) 0.7 0.95 v power supply rise time poris power supply rise time from v dd =0v to 1.6v 100 ms note 7-1: the por release level can be selected out of 8 levels only when ldv reset function is disabled. note 7-2: por is in unknown state before transistors start operation. low voltage detection (lvd) characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol conditions option selected voltage min typ max unit 1.91v 1.81 1.91 2.01 2.01v 1.91 2.01 2.11 2.31v 2.21 2.31 2.41 2.51v 2.41 2.51 2.61 2.81v 2.71 2.81 2.91 3.79v 3.69 3.79 3.89 lvd reset voltage (note 8-2) lvdet 4.28v 4.18 4.28 4.38 v 1.91v 55 2.01v 55 2.31v 55 2.51v 55 2.81v 55 3.79v 60 lvd hysteresis width lvhys select from option. see fig. 14. (note 8-1) (note 8-3) 4.28v 65 mv detection voltage unknown state lvuks see fig. 14. (note 8-4) 0.7 0.95 v low voltage detection minimum width (reply sensitivity) tlvdw lvdet-0.5v see fig. 15. 0.2 ms note 8-1: the lvd reset level can be selected out of 7 levels only when the lvd reset function is enabled. note 8-2: lvd reset voltage specification values do not include hysteresis voltage. note 8-3: lvd reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. note 8-4: lvd is in an unknown state before transistors start operation. lc87f1k64a no.a2197-27/35 consumption current characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit 4.5 to 5.5 9.8 18 iddop(1) ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation stopped ? internal low-/medium-speed rc oscillation stopped ? usb circuit stopped ? 1/1 frequency division ratio 3.0 to 3.6 5.7 11 4.5 to 5.5 15 28 iddop(2) ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation mode active ? internal low-/medium-speed rc oscillation stopped ? usb circuit active ? 1/1 frequency division ratio 3.0 to 3.6 8.1 15 4.5 to 5.5 6.7 12 3.0 to 3.6 4.2 7.1 iddop(3) ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 6mhz side ? internal low-/medium-speed rc oscillation stopped ? 1/2 frequency division ratio 2.7 to 3.0 3.5 5.8 4.5 to 5.5 0.77 2.8 3.0 to 3.6 0.46 1.5 iddop(4) ? external oscillation fmcf stopped ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to internal medium-speed rc oscillation ? internal low-speed rc oscillation stopped ? 1/2 frequency division ratio 2.7 to 3.0 0.39 1.3 ma 4.5 to 5.5 28 170 3.0 to 3.6 18 100 iddop(5) ? external oscillation fsx'tal /fmcf stopped ? system clock set to internal low-speed rc oscillation ? internal medium-speed rc oscillation stopped ? 1/1 frequency division ratio 2.7 to 3.0 16 87 4.5 to 5.5 45 124 3.0 to 3.6 18 60 normal mode consumption current (note 9-1) (note 9-2) iddop(6) ? external oscillation fmcf stopped ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz side ? internal low-/medium-speed rc oscillation stopped ? 1/2 frequency division ratio 2.7 to 3.0 14 48 a 4.5 to 5.5 4.0 7.0 halt mode consumption current (note 9-1) (note 9-2) iddhalt(1) v dd 1 =v dd 2 =v dd 3 ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation stopped ? internal low-/medium-speed rc oscillation stopped ? usb circuit stopped ? 1/1 frequency division ratio 3.0 to 3.6 2.2 3.8 ma note 9-1: the consumption current value do not include current that flows into the output transistors and internal pull-up resistors. note 9-2: the consumption current values do not include oper ational current of lvd (low voltage detection) function if not specified. continued on next page. lc87f1k64a no.a2197-28/35 continued from preceding page. specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit 4.5 to 5.5 9.2 18 iddhalt(2) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation active ? internal low-/medium-speed rc oscillation stopped ? usb circuit active ?1/1 frequency division ratio 3.0 to 3.6 4.7 8.6 4.5 to 5.5 2.5 4.5 3.0 to 3.6 1.3 2.3 iddhalt(3) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 6mhz side ? internal low-/medium-speed rc oscillation stopped ? 1/2 frequency division ratio 2.7 to 3.0 1.1 1.8 4.5 to 5.5 0.41 1.5 3.0 to 3.6 0.20 0.72 iddhalt(4) ? halt mode ? external oscillation fmcf stopped ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to internal medium-speed rc oscillation ? internal low-speed rc oscillation stopped ?1/2 frequency division ratio 2.7 to 3.0 0.17 0.53 ma 4.5 to 5.5 7.2 95 3.0 to 3.6 4.0 51 iddhalt(5) ? halt mode ? external oscillation fsx'tal /fmcf stopped ? system clock set to internal low-speed rc oscillation ? internal medium-speed rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.0 3.4 43 4.5 to 5.5 30 112 3.0 to 3.6 8.4 51 halt mode consumption current (note 9-1) (note 9-2) iddhalt(6) ? halt mode ? external oscillation fmcf stopped ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz side ? internal low-/medium-speed rc oscillation stopped. ? 1/2 frequency division ratio 2.7 to 3.0 5.8 40 4.5 to 5.5 0.28 67 3.0 to 3.6 0.22 35 iddhold(1) ? hold mode ? cf1=v dd or open (external clock mode) 2.7 to 3.0 0.21 30 4.5 to 5.5 2.8 70 3.0 to 3.6 2.3 38 iddhold(2) ? hold mode ? lvd option selected ? cf1=v dd or open (external clock mode) 2.7 to 3.0 2.1 33 4.5 to 5.5 0.98 68 3.0 to 3.6 0.62 36 hold mode consumption current (note 9-1) (note 9-2) iddhold(3) ? hold mode ? internal timer type watchdog timer active (internal low-speed rc oscillation circuit active) ? cf1=v dd or open (external clock mode) 2.7 to 3.0 0.51 31 4.5 to 5.5 26 106 3.0 to 3.6 6.1 49 iddhold(4) ? x'tal hold mode ? cf1=v dd or open (external clock mode) ? fsx'tal=32.768khz crystal oscillation mode 2.7 to 3.0 3.8 38 4.5 to 5.5 1.0 68 3.0 to 3.6 0.64 36 x'tal hold mode consumption current (note 9-1) (note 9-2) iddhold(5) v dd 1 =v dd 2 =v dd 3 ? x'tal hold mode ? cf1=v dd or open (external clock mode) ? fmsrc=30khz internal low-speed rc oscillation mode 2.7 to 3.0 0.53 31 a note 9-1: the consumption current value do not include current that flows into the output transistors and internal pull-up resistors. note 9-2: the consumption current values do not include oper ational current of lvd (low voltage detection) function if not specified. lc87f1k64a no.a2197-29/35 usb characteristics and timing at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = 0v conditions parameter symbol pin/remarks min typ max unit high level output v oh(usb) ? 15k 5% to gnd 2.8 3.6 v low level output vol(usb) ? 1.5k 5% to 3.6v 0.0 0.3 v output signal crossover voltage v crs 1.3 2.0 v differential input sensitivity v di ? | (uhad+) ? (uhad?) | ? | (uhbd+) ? (uhbd?) | 0.2 v differential input common mode range v cm 0.8 2.5 v high level input v ih(usb) 2.0 3.6 v low level input v il(usb) 0.0 0.8 v rise time (full-speed) t fr r s =33 , c l =50pf 4 20 ns fall time (full-speed) t ff r s =33 , c l =50pf 4 20 ns rise time (low-speed) t lr r s =33 , c l =200 to 600pf 75 300 ns fall time (low-speed) t lf r s =33 , c l =200 to 600pf 75 300 ns f-rom programming characteristics at ta = +10 c to +55 c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? excluding power dissipation in the microcontroller block 3.0 to 5.5 5 10 ma tfw(1) ? erase operation 20 30 ms programming time tfw(2) ? write operation 3.0 to 5.5 40 60 s lc87f1k64a no.a2197-30/35 main system clock oscillation the characteristics of a sample main system clock oscilla tor circuit shown in table 1 are measured using a our specification oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the resonator vendor confirmed normal and stable oscillation. table 1 shows the characteristics of a oscillator circuit when usb host function is not used. if usb host function is to be used, it is absolutely recommended to use a resonator that satisfies the precision and stability according to the usb standards ( 500ppm) table 1 characteristics of a sample main system clock oscillator circuit with a ceramic resonator circuit constant oscillation stabilization time nominal frequency vendor name resonator name c1 [pf] c2 [pf] rd1 [ ] operating voltage range [v] typ [ms] max [ms] remarks 12mhz murata cstce12m0gh5l**-r0 (33) (33) 470 3.0 to 5.5 0.1 0.5 c1 and c2 integrated smd type the oscillation stabilization time is required for the oscillator to get stabilized in the following cases (see figure 4): ? until oscillation is stabilized after v dd goes above the operating voltage lower limit ? until oscillation is stabilized after the instruction for starting the main clock oscillator circuit is executed ? until oscillation is stabilized after hold mode is released. ? until oscillation is stabilized after x'tal hold mode is re leased with cfstop (ocr register, bit 0) set to 0 and oscillation is started. subsystem clock oscillation table 2 shows the characteristics of a sample subsystem clock oscillator circuit that are measured using a our specification oscillation characteristics evaluation board and ex ternal components with circuit constant values with which the resonator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem clock oscillator circuit with a crystal resonator circuit constant oscillation stabilization time nominal frequency vendor name resonator name c3 [pf] c4 [pf] rf [ ] rd2 [ ] operating voltage range [v] typ [s] max [s] remarks 32.768khz epson toyocom mc-306 18 18 open 680k 2.7 to 5.5 1.1 3.0 applicable cl value=12.5pf smd type the oscillation stabilization time is required for the oscillator to get stabilized in the following cases (see figure 4): ? until oscillation is stabilized after the instruction for starting the subclock oscillator circuit is executed ? until oscillation is stabilized after hold mode is released with extosc (ocr register, bit 6) set to 1 and oscillation is started. note: the components that are involved in oscillation should be placed as clos e to the ic and to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 cf oscillator circuit figure 2 crystal oscillator circuit rf rd2 xt1 xt2 c4 x?tal c3 rd1 cf1 cf2 c2 cf c1 lc87f1k64a no.a2197-31/35 figure 3 ac timing measurement point reset time and oscillation stabilization time hold release signal and oscillation stabilization time figure 4 oscillation stabilization time operating v dd lower limit power supply res internal medium-speed rc oscillation cf1, cf2 xt1, xt2 operating mode reset time tmscf tmsx?tal unknown reset instruction execution v dd gnd execute oscillation enable instruction internal medium-speed rc oscillation cf1, cf2 xt1, xt2 operating mode hold release signal hold release signal valid tmscf tmsx?tal hold halt * if operation is enabled before entry into hold mode 0.5v dd lc87f1k64a no.a2197-32/35 figure 5 external filter circuit for the internal usb-dedicated pll circuit figure 6 external filter circuit for audio interface (used with in ternal pll circuit) figure 7 usb port peripheral circuit rd 0k cd 2.2 f p34/ufilt + - when using the internal pll circuit to generate the 48mhz clock for usb, it is necessary to connect a filter circuit as shown in the left figure to the p34/ufilt pin. after pll is set, stabilization time of 20ms or longer must be secured. 5pf 33 uhad+ / uhbd+ 5pf 33 15k 15k it is necessary to adjust th e circuit constant of the usb port peripheral circuit for each mounting board. uhad- / uhbd- to generate the master clock for the audio interface using the intern al pll circuit, it is necessary to connect a filter circuit as shown in the left figure to the p33 pin. rd 150 cd 4.7 f p33/afilt + - cp 1 f + - lc87f1k64a no.a2197-33/35 figure 8 sample reset circuit figure 9 serial i/o waveform figure 10 pulse input timing waveform c res v dd r res res data ram transfer period (sio0, 4 only) data ram transfer period (sio0, 4 only) sioclk: di0 di7 di2 di3 di4 di5 di6 di8 di1 datain: do0 do7 do2 do3 do4 do5 do6 do8 do1 dataout: dataout: datain: sioclk: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo n ote: the external circuit differs depending on which of the power-on reset and low-voltage reset functions is to be used. refer to the section on the reset functions in the user's manual. tpil tpih lc87f1k64a no.a2197-34/35 tbuf thd;sta tlow tr thd;dat thigh tf tsu;dat tsu;sta thd;sta tsp tsu;sto p s sr p s: start condition p: stop condition sr: restart condition sda sck figure 11 i 2 c timing figure 12 usb data signal timing and voltage levels figure 13 sample waveforms for por-only (lvd de selected) operation (reset pin: pull-up resistor p res only) ? the por function generates a reset only when the power is turned on starting at the v ss level. ? no stable reset will be generated if power is turned on again if the power level does not go down to the v ss level as shown in (a). if such a case is anticipated, use the lvd function together with the por function as explained below or implement an external reset circuit. ? a reset is generated only when power level goes down to the v ss level as shown in (b) and power is turned on again after this condition continues for 100 s or longer. t r t r d+ d- 10% 10% 90% 90% v oh v crs v ol por release voltage ( porrl ) v dd res reset unknown state (pouks) (a) (b) reset period reset period 100 lc87f1k64a ps no.a2197-35/35 figure 14 sample waveforms for por+lvd operation (reset pin: pull-up resistor p res only) ? a reset is generated both when power is tu rned on and when the power level lowers. ? a hysteresis width (lvhys) is provided to prevent repetitions of reset release and entry cycles near the detection level. figure 15 minimum low voltage detection width (sam ple temporary power interruption/fluctuation waveform) ordering information device package shipping (qty / packing) lc87f1k64auwa-2h sqfp48(7x7) (pb-free / halogen free) 250 / tray foam v dd res reset unknown state (lvuks) v dd lvd detection voltage tlvdw lvd reset voltage lvdet-0.5v v ss lvd hysteresis width (lvhys) lvd detection voltage (lvdet) reset period lvd release voltage (lvdet+lvhy) reset period reset period on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner. |
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