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fedl7202-001-01 issue date: sep. 08, 2004 ML7202-001 2-channel echo canceler with multifunction adpcm transcoder 1/65 general description the ML7202-001 is an lsi supporting 2-channel transmit/r eceive. each channel of tr ansmit/receive has a built-in line echo canceler and full-duplex adpcm transcoder. the ML7202-001, which performs functions such as the dtmf tone and single tone ge neration, and tone detection, transmit/receive data mute, gain control, and vox, is ideally suited to applications such as basestati ons of adpcm-based cordless telephone systems like asian-prevailing ph s (personal handyphone system). features ? single 3.3 v power supply (dvdd1, 2, avdd: 3.0 to 3.6 v) ? adpcm: itu-t recommendation g.726 (32 kbps) ? pcm interface code format: itu-t recommendation g.711 (64 kbps), ? -law or a-law selectable ? built-in echo canceler echo attenuation: 30 db typ. white noise cancelable echo delay time: 64ms max ? serial adpcm and pcm transmission rate: 64 to 2048 kbps ? digital interface synchronization mode: long frame sync ? time slot assignment ? -law/a-law setting: supports 32 slots (b clk setting: 2.048 mhz external input) ? transmit/receive mute function and tr ansmit/receive programmable gain setting ?? built-in dtmf tone and single tone generators ?? single tone detector 2100 hz (default) ?? ?? built-in vox functions transmit side : voice/silence detection receive side : background noise generation during silence ?? parallel microcontroller interface ?? master clock frequency: 19.2 mhz ?? hardware and software power-down mode ?? operating temperature range: ?40c to +85c ? package: 64-pin plastic tqfp (tqfp64-p-1010-0.50-k) (ML7202-001tb)
fedl7202-001-01 ML7202-001 2/65 block diagram adpcm transcoder (channel 1) echo canceller (channel 2) line adaptive fir filter (laff) power calc howling detector double talk det center clip a ttrl2 gainl2 a ttsl2 gpadl2 lpadl2 sinl2 soutl2 routl2 rinl2 a dpcm coder1 a dpcm decoder1 noise gen2 voice det. tone gen2(dtmf etc.) i/o controller p/s & s/p p/s & s/p timing gen. p/s & s/p timing gen. pcmado2 pcmadi2 pcmaco2 pcmaci2 pcmlno2 pcmlni2 is2 ir2 bclka synca bclkl syncl a tttgtx2 a tttgrx2 voxi1 voxo1 p/s & s/p pcmlni1 pcmlno1 echo canceller (channel 1) line adaptive fir filter (laff) power calc howling detector double talk det. center clip a ttrl1 gainl1 a ttsl1 gpadl1 lpadl1 sinl1 soutl1 routl1 rinl1 tone gen1(dtmf etc.) a tttgtx1 a tttgrx1 voice det. noise gen1 i/o controller p/s & s/p pcmado1 p dn/rst pcmaco1 pcmaci1 adpcm transcoder (channel 2) a dpcm coder2 a dpcm decoder2 p/s & s/p is1 ir1 voxi2 voxo2 mcu i/f mtype c s r d w r a 4-0 d7-0 i nt vref te s t i / f tsti0-9 sg 5 8 10 vbg vout1-2 dgnd1-2 dvdd1-2 a gnd a vdd clock generator pcmadi1 mck tone det. tone det. tone det. tone det. tx_mute1 rx_mute1 tx_mute2 rx_mute2 * transmit side : direction from the pcmlni1-pin (or t he pcmlni2-pin) toward the is1-pin (or the is2-pin) receive side : direction from the ir1-pin (or the ir 2-pin) toward the pcmlno1-pin (or the pcmlno2-pin)
fedl7202-001-01 ML7202-001 3/65 pin configuration (top view) d0 d2 d3 d4 w r a gnd d1 dgnd1 r d c s p dn/rst tsti7 tsti8 synca voxo1 voxi1 sg a vdd tsti1 tsti2 is1 ir1 tsti3 tsti4 tsti5 i nt vout2 dvdd2 pcmlni1 pcmlno1 pcmaci2 tsti9 pcmaco1 pcmadi1 pcmado2 syncl bclkl dgnd2 a 1 tsti6 vout1 dvdd1 vbg a 4 a 3 a 2 a 0 27 28 25 26 17 18 19 20 29 30 21 22 23 24 32 31 43 42 41 40 39 48 47 46 45 44 38 37 36 35 34 33 6 7 8 9 10 1 2 3 4 5 11 12 13 14 15 16 54 53 56 55 64 63 62 61 52 51 60 59 58 57 49 50 mtype tsti0 is2 ir2 voxo2 voxi2 pcmado1 pcmaco2 pcmlno2 pcmlni2 pcmaci1 pcmadi2 d5 d6 d7 bclka mck 64-pin plastic tqfp
fedl7202-001-01 ML7202-001 4/65 pin descriptions pin symbol i/o state when pdn/rst =?0? description 1 dgnd1 ? ? digital ground pin 2 d0 i/o i 3 d1 i/o i 4 d2 i/o i 5 d3 i/o i 6 d4 i/o i 7 d5 i/o i 8 d6 i/o i 9 d7 i/o i data i/o pins for accessing control registers. this lsi contains 32-byte control registers and reads/writes by an external microcontroller are via the wr , rd , and cs pins. see ?microcontroller interfac e write/read timing? in the ?electrical characteristics? section. 10 wr i i write enable input pin for accessing the control registers 11 rd i i read enable input pin for accessing the control registers. this pin is enabled when the mtype pin is set to ?0? and is disabled when the mtype pin is set to ?1?. when this pi n is disabled, fix this pin to ?1?. 12 cs i i chip select input pin for the control registers 13 pdn/rst i ?0? power-down and reset control input pin. when this pin is set to ?0?, the lsi is powered down. in power down mode, all of the control registers, internal data memories, coefficients in the echo canceler and the adpcm transcoder are reset. for normal operation, set this pin to ?1?. since the power-down reset function is determined by the or?ed va lue of a negative logic of this pin and the cr0-b7 (spdn), set the cr0-b7 (spdn) to ?0? when using the pin. when applying power, hold the pin in ?0? for 250 ? s or longer from the master clock input (20 clocks minimum) after the digital supply (dvdd1 and dvdd2) voltage and the analog supply (avdd) voltage reach 90% of their nominal value. see ?reset function? in the ?timing diagram? section. note that the specificati ons prescribed in this data sheet may not be satisfied until the requirements of inputting a minimum of 20 master clock pulses and holding the pin in ?0? for 250 ? s or more are met. 14 tsti7 i i input pin for lsi manufacturer?s tests. fix this pin to ?0?. 15 mck i i master clock input pin. the input frequency shall be 19.2 mhz. the master clock can be asynchronized to syncl, synca, bclkl, and bclka. 16 agnd ? ? analog ground pin 17 sg o ?0? output pin for analog signal ground in the lsi. the output voltage is about 1.4 v. connect 10 ? f and 0.1 ? f (ceramic type) bypass capacitors between this pin and the agnd pin. this output cannot be directly used as analog signal ground. a buffer should be placed when this output is used. 18 avdd ? ? +3.3 v analog power supply pin
fedl7202-001-01 ML7202-001 5/65 pin symbol i/o pdn/rst =?0? description 19 voxo1 o ?0? output pin for the vox function on th e transmit side of channel 1. this pin is enabled when cr21-b7 (vox_on1) is set to ?1?. this pin is used for identifying the voice/silenc e state by detecting the power of the transmit signal. at detection of vo ice, a logic ?1? is output to this pin and at detection of silence, logic ?0? is output. cr21-b6 and b5 (vox_on_lvl11 and_ vox_on_lvl01) are used for setting the threshold to be identified. this signal is also output to cr5-b2 (vox_out1). figure 4 shows the timing diagram for the vox function. the transmit signal refers to the pcmlni1 pin input signal. 20 voxi1 i i input pin for the vox function on the receive side (line echo canceler rinl1 side) of channel 1. this pin is enabled when cr21-b7 (vox_on1) is set to ?1?. when this pin is a logic ?1?, receive side speech signals are fed to the rinl1. when this pin is a logic ?0?, the background noise generator?s output is fed to the rinl1 instead of the receive side speech signals. use cr21-b1 and b0 (rx_noise_lvl11 and rx_noise_lvl01) for setting the level of the background noise. set cr21-b2 (vox_in1) to ?0? when using this pin, since this pin is or ed with cr21-b2 (v ox_in1) internally. when the application has a means to detect silence with the receive side speech signals, this function could be made use of as comfort noise generator. 21 voxo2 o ?0? output pin for the vox function on th e transmit side of channel 2. this pin is enabled when cr22-b7 (vox_on2) is set to ?1?. this pin is used for identifying the voice/silenc e state by detecting the power of the transmit signal. at detection of vo ice, a logic ?1? is output to this pin and at detection of silence, logic ?0? is output. cr22-b6 and b5 (vox_on_lvl12 and_ vox_on_lvl02) are used for setting the threshold to be identified. this signal is also output to cr5-b6 (vox_out2). figure 4 shows the timing diagram for the vox function. the transmit signal refers to the pcmlni2 pin input signal. 22 voxi2 i i input pin for the vox function on the receive side (line echo canceler rinl2 side) of channel 2. this pin is enabled when cr22-b7 (vox_on2) is set to ?1?. when this pin is a logic ?1?, receive side speech signals are fed to the rinl2. when this pin is a logic ?0?, the background noise generator?s output is fed to the rinl2 instead of the receive side speech signals. use cr22-b1 and b0 (rx_noise_lvl12 and rx_noise_lvl02) for setting the level of the background noise. set cr22-b2 (vox_in2) to ?0? when using this pin, since this pin is or ed with cr22-b2 (v ox_in2) internally. when the application has a means to detect silence with the receive side speech signals, this function could be made use of as comfort noise generator. 23 int o ?1? interrupt request output pin. an interrupt is generated when the transmit/receive tone detector in each channel detects a tone signal of 2100 hz (default). an interrupt also is generated when the state changes from tone detection to non-detection of 2100 hz (default). when an interrupt event occurs, t he pin outputs a logic ?0? for 0.7 ? s. when the interrupt event remains unchanged, the pin outputs a logic ?1?. by reading cr4-b3 to b0, it is possible to identify the detected channel and the path (on the transmit side/receive side).
fedl7202-001-01 ML7202-001 6/65 pin symbol i/o pdn/rst =?0? description 24 tsti8 i i input pin for testing. fix this pin to ?0?. 25 bclka i i shift clock input pin for adpcm data (is1, is2, ir1, and ir2). the frequency is within the range of 64 to 2048 khz. 26 synca i i 8 khz synchronous signal input pin for adpcm data. this signal must be synchronized with the bclka signal. this signal indicates the location of msb of adpcm data. 27 ir1 i i 4-bit adpcm data input pin on the re ceive side of channel 1. the signal that is input to this pin is output to the pcmado1 pin when cr0-b3 (iosel) is set to ?1? and the signal is output to the pcmlno1 pin when cr0-b3 is set to ?0?. this adpcm data is shifted on the falling edge of bclka, synchronized to synca and input serially starting from msb. when cr2-b7 (conta1) is set to ?1?, this pin is configured as an 8-bit pcm data input and the data is processed skipping the adpcm transcoder. when cr2-b5 (dthr1) is set to ?1?, the output pin set by cr0-b3 iosel is configured as a 4-bit adpcm data output and the 4-bit adpcm input data is output as it is. when cr2-b5 (dthr1) is set to ?1?, the mute function is disabled and, even if cr2-b7 (conta1) is set to ?1?, the pin is not configured as an 8-bit pcm data input. 28 ir2 i i 4-bit adpcm data input pin on the re ceive side of channel 2. the signal that is input to this pin is output to the pcmado2 pin when cr0-b3 (iosel) is set to ?1? and the signal is output to the pcmlno2 pin when cr0-b3 is set to ?0?. this adpcm data is shifted on the falling edge of bclka, synchronized to synca and input serially starting from msb. when cr3-b7 (conta2) is set to ?1?, this pin is configured as an 8-bit pcm data input and the data is processed skipping the adpcm transcoder. when cr3-b5 (dthr2) is set to ?1?, the output pin set by cr0-b3 iosel is configured as a 4- bit adpcm data output and the 4-bit adpcm input data is output as it is. when cr3-b5 (dthr2) is set to ?1?, the mute function is disabled, and even if cr3-b7 (conta2) is set to ?1?, the pin is not configured as an 8-bit pcm data input. 29 is1 o hi-z adpcm data output pin on the trans mit side of channel 1. when cr0-b3 (iosel) is set to ?1?, the signal that is input from the pcmadi1 pin is output from this pin. when cr0-b3 is set to ?0?, the signal that is input from the pcml nii1 pin is output. adpcm data is output serially starting from msb, synchronized to the rising edges of bclka and synca, and this pin gets in a high impedance state except when the 4-bit adpcm data is being output. also during power-down/reset and initial mode, this pin is put in a high impedance state. when cr2-b7 (conta1) is set to ?1?, this pin is configured as an 8-bit pcm data output skipping the adpcm transcoder. this pin gets in a high impedance state except when the 8-bit pcm data is being output. when cr2-b5 (dthr1) is set to ?1?, the 4-bit adpcm input data from the input pin set by cr0-b3 (iosel) is output from this pin as it is. this pin gets in a high impedance st ate except when the 4-bit adpcm data is being output. when cr2-b5 (dthr1) is set to ?1?, the mute function is disabled, and the pin is not configured as an 8-bit pcm data output even if cr2-b7 (conta1) is set to ?1?.
fedl7202-001-01 ML7202-001 7/65 pin symbol i/o pdn/rst =?0? description 30 is2 o hi-z adpcm data output pin on the trans mit side of channel 2. when cr0-b3 (iosel) is set to ?1?, the signal that is input from the pcmadi2 pin is output from this pin. when cr0-b3 is set to ?0?, the signal that is input from the pcml nii2 pin is output. adpcm data is output serially starting from msb, synchronized to the rising edges of bclka and synca, and this pin gets in a high impedance state except when the 4-bit adpcm data is being output. also during power-down/reset and initial mode, this pin is put in a high impedance state. when cr3-b7 (conta2) is set to ?1?, this pin is configured as an 8-bit pcm data output skipping the adpcm transcoder. this pin gets in a high impedance state except when the 8-bit pcm data is being output. when cr3-b5 (dthr2) is set to ?1?, the 4-bit adpcm input data from the input pin set by cr0-b3 (iosel) is output from this pin as it is. this pin gets in a high impedance st ate except when the 4-bit adpcm data is being output. when cr3-b5 (dthr2) is set to ?1?, the mute function is disabled, and the pin is not configured as an 8-bit pcm data output even if cr3-b7 (conta2) is set to ?1?. 31 dvdd2 ? ? +3.3 v digital power supply pin 32 vout2 o about 2.6 v regulator output pin. the out put voltage is about 2.6 v. connect 10 ? f and 0.1 ? f bypass capacitors between this pin and the dgnd2 pin. 33 dgnd2 ? ? digital ground pin 34 pcmado1 o hi-z pcm data output pin of channel 1. this pin is enabled when cr0-b3 (iosel) is set to ?1? and is put in a high impedance state when cr0-b3 is set to ?0?. the pcm data is output serially starting from msb, synchronized to the rising edges of bclkl and syncl, and the pin gets in a high impedance state ex cept when the 8-bit pcm data is being output. also during power-down reset and initial mode, the pin is also put in a high impedance. when cr2-b5 (dthr1) is set to ?1?, this pin is configured as a 4-bit adpcm data output and 4-bit adpcm input data from the ir1 pin is output as it is. this pin gets in a high impedance state except when the 4-bit adpcm data is being output. when cr2-b7 (conta1) is set to ?1?, the adpcm transcoder goes into a through mode and 8-bit pcm input data from the ir1 pin is outpu t as it is from this pin. the pin gets in a high impedance state exce pt when the 8-bit pcm data is being output. when cr2-b5 (dthr1) is set to ?1?, the mute function is disabled and the pin is not configured as an 8-bit pcm data output even if cr2-b7 (conta1) is set to ?1?.
fedl7202-001-01 ML7202-001 8/65 pin symbol i/o pdn/rst =?0? description 35 pcmado2 o hi-z pcm data output pin of channel 2. this pin is enabled when cr0-b3 (iosel) is set to ?1? and is put in a high impedance state when cr0-b3 is set to ?0?. the pcm data is output serially starting from msb, synchronized to the rising edges of bclkl and syncl, and the pin gets in a high impedance state ex cept when the 8-bit pcm data is being output. also during power-down reset and initial mode, the pin is also put in a high impedance. when cr3-b5 (dthr2) is set to ?1?, this pin is configured as a 4-bit adpcm data output and 4-bit adpcm in put data itself from the ir2 pin is output. this pin gets in a hi gh impedance state except when the 4-bit adpcm data is being output. when cr3-b7 (conta2) is set to ?1?, the adpcm transcoder goes into a through mode and 8-bit pcm input data from the ir2 pin is output as it is from this pin. the pin gets in a high impedance state except when the 8-bit pcm data is being output. when cr3-b5 (dthr2) is set to ?1?, the mute function is disabled and the pin is not configured as an 8-bit pcm data output even if cr3-b7 (conta2) is set to ?1?. 36 pcmaco1 o hi-z pcm data output pin of channel 1 line echo canceler. this pin is enabled when cr0-b3 (iosel) is set to ?1?. when cr0-b3 is set to ?0?, the pin is put in a high imped ance. pcm data is output serially starting from msb, synchronized to the rising edges of bclkl and syncl, and the pin gets in a high impedance state except when the 8-bit pcm data is being output. also during power-down reset and initial mode, the pin is put in a high impedance. during an end-to-end 4-bit adpcm transparent mode defined by cr2-b5 (dthr1) set to ?1?, this pin is configured as 4-bit adpcm data output, and the line echo canceler, the vox function, and the tone detector are disabled. the 4-bit adpcm input data from the pcmlni1 pin is output as it is, and the pin gets in a high impedance state except when the 4-bit adpcm data is being output. note that the pin is not configur ed as an 8-bit pcm data output when cr2-b5 (dthr1) is set to ?1? even if cr2-b7 (conta1) is set to ?1?. 37 pcmaco2 o hi-z pcm data output pin of channel 2 line echo canceler. this pin is enabled when cr0-b3 (iosel) is set to ?1?. when cr0-b3 is set to ?0?, the pin is put in a high imped ance. pcm data is output serially starting from msb, synchronized to the rising edges of bclkl and syncl, and the pin gets in a high impedance state except when the 8-bit pcm data is being output. also during power-down reset and initial mode, the pin is put in a high impedance. during an end-to-end 4-bit adpcm transparent mode defined by cr3-b5 (dthr2) set to ?1?, this pin is configured as 4-bit adpcm data output, the vox function, and the tone detector are disabled. the 4-bit adpcm input data from the pcmlni2 pi n is output as it is, and the pin gets in a high impedance state exce pt when the 4-bit adpcm data is being output. note that the pin is not configur ed as an 8-bit pcm data output when cr3-b5 (dthr2) is set to ?1? even if cr3-b7 (conta2) is set to ?1?.
fedl7202-001-01 ML7202-001 9/65 pin symbol i/o pdn/rst =?0? description 38 pcmlno1 o hi-z pcm data output pin of line echo canc eler of channel 1. the pcm data is output serially starting from msb, synchronized to the rising edges of bclkl and syncl. the pin gets in a high impedance state except when the 8-bit pcm data is being output. also during power-down reset and initial mode, the pin is put in a high impedance. during an end-to-end 4-bit adpcm transparent mode defined by cr2-b5 (dthr1) set to ?1?, this pin is configured as 4-bit adpcm data output, and the line echo canceler, the vox function, and the tone detector are disabled. the 4-bit adpcm input data from the input pin set by cr0-b3 (iosel) is output as it is from this pin. the pin gets in a high impedance state except when the 4-bit adpcm data is being output. note that the pin is not configur ed as an 8-bit pcm data output when cr2-b5 (dthr1) is set to ?1? even if cr2-b7 (conta1) is set to ?1?. 39 pcmlno2 o hi-z pcm data output pin of line echo canc eler of channel 2. the pcm data is output serially starting from msb, synchronized to the rising edges of bclkl and syncl. the pin gets in a high impedance state except when the 8-bit pcm data is being output. also during power-down reset and initial mode, the pin is put in a high impedance. during an end-to-end 4-bit adpcm transparent mode defined by cr3-b5 (dthr2) set to ?1?, this pin is configured as 4-bit adpcm data output, and the line echo canceler, the vox function, and the tone detector are disabled. the 4-bit adpcm input data from the input pin set by cr0-b3 (iosel) is output as it is from this pin. the pin gets in a high impedance state except when the 4-bit adpcm data is being output. note that the pin is not confi gured as an 8-bit pcm data output when cr3-b5 (dthr2) is set to ?1? even if cr3-b7 (conta2) is set to ?1?. 40 tsti9 i i input pin for testing. fix this pin to ?0?. 41 pcmlni1 i i pcm data input pin of line echo cancel er of channel 1. this pcm input signal is shifted on the falling edge of bclkl and is input starting from msb. the start of pcm data (msb) is identified by the rising edge of syncl. when cr2-b5 (dthr1) is set to ?1?, the pin is configured as a 4-bit adpcm data input and the input data from this pin is output as it is to the output pin set by cr0-b3 (iosel). 42 pcmlni2 i i pcm data input pin of line echo cancel er of channel 2. this pcm input signal is shifted on the falling edge of bclkl and is input starting from msb. the start of pcm data (msb) is identified by the rising edge of syncl. when cr3-b5 (dthr2) is set to ?1?, the pin is configured as a 4-bit adpcm data input and the input data from this pin is output as it is to the output pin set by cr0-b3 (iosel). 43 pcmaci1 i i pcm data input pin of line echo canceler of channel 1. this pin is enabled when cr0-b3 (iosel) is set to ?1? and when cr0-b3 is set to ?0?, input to the pin is disabled. when the input is disabled, fix the pin to ?0? or ?1?. the pcm input signal is shifted on the rising edge of bclkl and is input starting from m sb. the start of pcm data (msb) is identified by the rising edge of syncl. when cr2-b5 (dthr1) is set to ?1?, the pin is configured as a 4-bit adpcm data input and 4-bit adpcm data input from the pcmlno1 is output from this pin as it is. 44 pcmaci2 i i pcm data input pin of line echo cancel er of channel 2. this pin is enabled when cr0-b3 (iosel) is set to ?1? and when cr0-b3 is set to ?0?, input to the pin is disabled. when the input is disabled, fix the pin to ?0? or ?1?. the pcm input signal is shifted on the rising edge of bclkl and is input starting from m sb. the start of pcm data (msb) is identified by the rising edge of syncl. when cr3-b5 (dthr2) is set to ?1?, the pin is configured as a 4-bit adpcm data input and 4-bit adpcm data input from the pcmlno2 is output from this pin as it is.
fedl7202-001-01 ML7202-001 10/65 pin symbol i/o pdn/rst =?0? description 45 pcmadi1 i i pcm data input pin of channel 1. when cr0-b3 (iosel) is set to ?1?, input to this pin is enabled; and when cr0-b3 is set to ?0?, input to the pin is disabled. when the pin input is disabled, fix the pin to ?0? or ?1?. the pcm input signal is shifted on the falling edge of bclkl and is input starting from msb. t he beginning of pcm data (msb) is identified by the rising edge of syncl. when cr2-b5 (dthr1) is set to ?1?, the pin is configured as a 4-bit adpcm data input and the 4-bit adpcm data input from this pin is out put to the is1 pin as it is. when cr2-b7 (conta1) is set to ?1?, the adpcm transcoder goes into a through mode and 8-bit pcm data input from this pin is output to the is1 pin as it is. 46 pcmadi2 i i pcm data input pin of channel 2. when cr0-b3 (iosel) is set to ?1?, input to this pin is enabled; and when cr0-b3 is set to ?0?, input to the pin is disabled. when the pin input is disabled, fix the pin to ?0? or ?1?. the pcm input signal is shifted on the falling edge of bclkl and is input starting from msb. t he beginning of pcm data (msb) is identified by the rising edge of syncl. when cr3-b5 (dthr2) is set to ?1?, the pin is configured as a 4-bit adpcm data input and the 4-bit adpcm data input from this pin is out put to the is2 pin as it is. when cr3-b7 (conta2) is set to ?1?, the adpcm transcoder goes into a through mode and 8-bit pcm data input from this pin is output to the is2 pin as it is. 47 bclkl i i shift clock input pin for pcm data (pcmlno1/pcmlni1, pcmaco1 /pcmaci1, pcmado1/pcmadi1, pcmlno2/pcmlni2, pcmaco2 /pcmaci2, and pcmado2/pcmadi2). the input frequency is 64 to 2048 khz. 48 syncl i i 8 khz synchronous signal input pin for pcm data. this signal must be synchronized to the bclkl signal. 49 tsti0 i i input pin for testing. fix this pin to ?0?. 50 mtype i i microcontroller interface select pin. when the pin is set to ?0?, the pin is in read/write independent control mo de; and when it is set to ?1?, the pin is in read/write shared (r/w) control mode. when this pin is set to ?1?, fix the rd pin to ?1?. 51 tsti1 i i 52 tsti2 i i 53 tsti3 i i 54 tsti4 i i 55 tsti5 i i input pins for lsi manufacturer?s te sting. fix these pins to ?0?. 56 a0 i i 57 a1 i i 58 a2 i i 59 a3 i i 60 a4 i i address input pins for accessing the control register 61 vbg o about 1.2 v regulator reference voltage output pin. the output voltage is about 1.2 v. connect a 150 pf bypass capacitor between this pin and the dgnd1 pin. 62 dvdd1 ? ? +3.3 v digital power supply pin 63 vout1 o about 2.6 v regulator output pin. the out put voltage is about 2.6 v. connect 10 ? f and 0.1 ? f bypass capacitors between this pin and the dgnd1 pin. 64 tsti6 i i input pin for lsi manufacturer?s testing. fix this pin to ?0?.
fedl7202-001-01 ML7202-001 11/65 (64ms) (64ms) (e) (e) (f) (f) (a) (a) (b) (b) (d) (d) (c) (c) (c) (d) (a) (b) (d) (c) (b) (a) channel 1 echo cancelle r (64ms) pcmlno1 pcmlni1 input control output control syncl, bclkl pcmaco1 pcmaci1 pcmado1 pcmadi1 is1 ir1 channel 1 a dpcm transcode r input control output control input control output control input control output control channel 2 echo cancelle r (64ms) input control output control channel 2 a dpcm transcode r input control output control input control output control input control output control synca, bclka pcmlno2 pcmlni2 pcmaco2 pcmaci2 pcmado2 pcmadi2 is2 ir2 iosel(cr0-b3)=0 control (a): conta1 (channel 1 adpcm through control)...cr2-b7 control (b): conta2 (channel 2 adpcm through control)...cr3-b7 control (c): dthr1 (channel 1 end-to-end 4-bit adpcm transparent control)...cr2-b5 control (d): dthr2 (channel 2 end-to-end 4-bit adpcm transparen t control)...cr3-b5 control (e): lthr1 (channel 1 echo canceller through control)...cr27-b7 control (f): lthr2 (channel 2 echo canceller through control)...cr28-b7 channel 1 adpcm codec time slot setting: cr13-b4 to b0 channel 2 adpcm codec time slot setting: cr14-b4 to b0 channel 1 pcm codec time slot setting: cr11-b4 to b0 channel 2 pcm codec time slot setting: cr12-b4 to b0 (c) (c) (d) (d) "0" "0" "1" "1" "1" "1" "0" "0" "1" "0" "1" "0" "1" "0" "1" "0" "0" "1" "0""1" "0" "0" "1" "1" note: fix the input pins, pcmaci1, pcmadi1, pcmaci2, and pcmadi2 to ?1? or ?0?. the outputs of pcmaco1, pcmado1, pcmaco2 and pcmado2 are all in high impedance. figure 1 signal input/output control 1
fedl7202-001-01 ML7202-001 12/65 (64ms) (64ms) (d) (d) (c) (c) (e) (f) (e) (f) (a) (c) (c) (a) (b) (d) (d) (b) (a) (b) (a) (b) (d) (c) (d) (c) (d) (d) (c) (c) channel 2 pcm codec time slot setting: cr12-b4 to b0 channel 1 pcm codec time slot setting: cr11-b4 to b0 channel 2 adpcm codec time slot setting: cr14-b4 to b0 channel 1 adpcm codec time slot setting: cr13-b4 to b0 channel 1 echo cancelle r (64ms) pcmlno1 pcmlni1 input control output control syncl, bclkl pcmaco1 pcmaci1 pcmado1 pcmadi1 is1 ir1 channel 1 a dpcm transcoder input control output control input control output control input control output control channel 2 echo cancelle r (64ms) input control output control channel 2 a dpcm transcoder input control output control input control output control input control output control synca, bclka pcmlno2 pcmlni2 pcmaco2 pcmaci2 pcmado2 pcmadi2 is2 ir2 (c) (c) (c) (c) (d) (d) (d) (d) iosel(cr0-b3)=1 control (a): conta1 (channel 1 adpcm transcoder enable/through control)...cr2-b7 control (b): conta2 (channel 2 adpcm transcoder enable/through control)...cr3-b7 control (c): dthr1 (channel 1 end-to-end 4-bit adpcm transparent control)...cr2-b5 control (d): dthr2 (channel 2 end-to-end 4-bit adpcm transparent control)...cr3-b5 control (e): lthr1 (channel 1 echo canceller through control)...cr27-b7 control (f): lthr2 (channel 2 echo canceller through control)...cr28-b7 "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" figure 2 signal input/output control 2
fedl7202-001-01 ML7202-001 13/65 syncl/synca time slot bclkl/bclka pcm(*1) i/o data (dthr1, dthr2=0) (conta1, conta2=0) time s lot 1 time s lot 2 ti me sl ot 3 ti me sl ot 32 ti me sl ot 1 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 1 2 3 4 5 6 7 8 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 is1, is2, ir1, ir2 data (dthr1, dthr2=0) (conta1, conta2=0) 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 pcm(*1) i/o data (dthr1, dthr2=1) (conta1, conta2 =don't care) pcm(*1) i/o data (dthr1, dthr2=0) (conta1, conta2=1) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 1 2 3 4 5 6 7 8 is1, is2, ir1, ir2 data (dthr1, dthr2=0) (conta1, conta2=1) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 1 2 3 4 5 6 7 8 is1, is2, ir1, ir2 data (dthr1, dthr2=1) (conta1, conta2=don?t care) *1: pcmlni1, pcmlno1, pcmaci1, pcmaco1, pcmadi1, pcmado1, pcmlni2, pcmlno2, pcmaci2, pcmaco2, pcmadi2, pcmado2 figure 3 pcm-adpcm time slot assignment voice voice silence silence silence voice detection time silence detection time (hang-over time) t voxon t voxoff receive signal echo canceler rinl1/rinl2 (analog image) voxi1/voxi2 pin (b) vox function timing on the reception side. voice voice silence silence silence playback signal time internal background noise generation time voxo1/voxo2 pin transmit signal pcmlni1/pcmlni2 pin (analog image) (a) vox function timing on the transmission side vox_moni11/01 (cr5: b1, b0) vox_moni12/02 (cr5: b5, b4) silence level detection internal processing delay t voxoff silence detection time (hang-over time) t voxon voice detection time silence level detection internal processing delay silence level detection internal processing delay figure 4 vox function
fedl7202-001-01 ML7202-001 14/65 on guard timer non-detection internal detection signal (transmit side) detection non-detection off guard timer detection non-detection non-detection on guard timer off guard timer internal detection signal (receive side) ttdet1 (cr4-b1) /ttdet2 (cr4-b3) rtdet1 (cr4-b0) /rtdet2 (cr4-b2) i nt pin output transmit side input signal(*1) (analog image) receive side input signal(*2) (analog image) interrupt signal output duration *1: transmit side input pin pcmlni1, pcmlni2 *2: receive side input pin pcmaci1, pcmaci2, ir1, ir2 figure 5 tone detector function channel 1 transmit side tone_a tone_b channel 1 receive side a tttgtx1 (cr16:b7-b4) a tttgrx1 (cr16:b3-b0) (for high tone group) cr17:b5 cr17:b7 [tone_gen1] tgen_gain_h1 (internal data memory) tgen_gain_l1 (internal data memory) cr17:b6 channel 2 transmit side tone_c tone_d channel 2 receive side a tttgtx2 (cr18:b7-b4) a tttgrx2 (cr18:b3-b0) cr19:b5 cr19:b7 [tone_gen2] tgen_gain_h2 (internal data memory) tgen_gain_l2 (internal data memory) cr19:b6 (for low tone group) (for low tone group) (for high tone group) figure 6 tone generator block diagram
fedl7202-001-01 ML7202-001 15/65 in the explanation below, since the tone generation procedures of tone_gen1 and tone_gen2 are the same, tone_gen1has been taken as the example. tgen_gain_h1 freq_a channel 1 side single tone output (transmit side) fin/fout function: off freqa fin fout tgen_gain_h1 channel 1 side single tone output (transmit side) fin/fout function: on ? single tone generation (cr17-b7="0") a nalog image tgen_gain_l1 freq_a (tone_a) channel 1 side dtmf tone output (transmit side) fin/fout function: off freq_b fin fout freq_b ? dtmf generation (cr17-b7="1") a nalog image tgen_gain_h1 a ddition output tx_tone_send1 "on" tgen_gain_l1 freq_a channel 1 side dtmf tone output (transmit side) fin/fout function: on tgen_gain_h1 a ddition output tx_tone_send1 "off" tx_tone_send1 "on" tx_tone_send1 "off" tx_tone_send1 "on" tx_tone_send1 "off" (tone_b) tx_tone_send1 "on" tx_tone_send1 "off" (tone_a) (tone_b) notes: ? the initial setting of fin (fade in)/fout (fade out) function is off. ? when the output frequency setting is altered using the control register (cr17), sound stoppage or noises may occur at the change of the frequency. ? when the fin (fade in)/fout (fade out) function is enabled, tone output does not stop immediately even if tone output stop is set by rewriting the contents of cr17-b6 and cr17-b5 to ?0? and the tome output becomes silent for only after expiration of the fade out time that is set here. therefore, for b7 (tone type setting) and b4 to b0 (frequency setting), it is recommended to rewrite rewrite b6 and b5 to ?0? while overwriting the same contents as those that are being output when tone ouptut is intended to be stopped. figure 7 tone generator function (tone_gen1)
fedl7202-001-01 ML7202-001 16/65 absolute maximum ratings parameter symbol condition rating unit power supply voltage v dd ? ?0.3 to +4.6 v digital input voltage v din ? ?0.3 to vdd+0.3 v storage temperature t stg ? ?65 to +150 c recommended operating conditions (v dd = 3.0 to 3.6 v, ta = ?40 to +85c) parameter symbol conditio n min. typ. max. unit power supply voltage v dd ? 3.0 3.3 3.6 v operating temperature range ta ? ?40 ? +85 c high level input voltage v ih all the digital input pins 0.75 ? v dd ? v dd + 0.3 v low level input voltage v il all the digital input pins ?0.3 ? 0.22 ?? v dd v digital input rise time t ir ? 2 20 ns digital input fall time t if all the digital input pins ? 2 20 ns digital output load capacitance c dl digital output pins ? ? 50 pf digital output load resistance pull-up resistor r dl digital output pins (open drain pins (*1) ) 500 ? ? ?? sg bypass capacitor c sg between sg and agnd 10 + 0.1 ? ? ? f vbg bypass capacitor c vout between and vbg and dgnd 150 ? ? pf vout bypass capacitor c vbg between vout1 and dgnd1 and beween vout2 and dgnd2 10 + 0.1 ? ? ? f master clock frequency f mck ? ?100 ppm 19.2 +100 ppm mhz master clock duty ratio d mck mck 40 50 60 % bit clock frequency f bck bclkl, bclka 64 ? 2048 khz synchronous signal frequency (*2) f sync syncl, synca ? 1000 ppm 8 +1000 ppm khz clock duty cycle (*3) d ck bclkl, bclka 40 50 60 % t bs bclkl to syncl, bckla to synca 100 ? ? ns transmit/receive synchronous timing t sb syncl to bclkl, synca to bclka 100 ? ? ns synchronous signal width t ws syncl, synca 1 bclk ? 100 ? s pcm and adpcm setup time t ds ? 100 ? ? ns pcm and adpcm hold time t dh ? 100 ? ? ns *1: open drain pins: pcmlno1, pcmlno2, pcmado1, pcmado2, pcmaco1, pcmaco2, is1, and is2 *2: if generating syncl and synca with different clocks, do not corrupt the sequence of the rising edges of syncl and synca (which rises first) after a reset is released. *3: it is not necessary to satisfy this specification as long as the digital interface specifications are satisfied.
fedl7202-001-01 ML7202-001 17/65 electrical characteristics dc characteristics (v dd = 3.0 to 3.6 v, ta = ?40 to +85c) parameter symbol conditio n min. typ. max. unit power supply current 1 i dd1 at operation, no signal (v dd = 3.3 v) ? 35 40 ma power supply current 2 i dd2 at power-down v dd = 3.3 v, mck input ? 0.1 1.0 ma i ih v in = dvdd ? 0.01 50 ? a digital input pin input leakage current i il v in = 0.0 v ?50 ?0.01 ? ? a i ozh v in = dvdd ? 0.01 50 ? a digital i/o pin input leakage current i ozl v in = 0.0 v ?50 ?0.01 ? ? a high level output voltage v oh digital output pins and digital i/o pis i oh = 4.0 ma 2.35 ? ? v low level output voltage v ol digital output pins and digital i/o pins i ol = ?4.0 ma ? ? 0.45 v c in1 input pins ? 6 12 pf input capacitance c in i/o pins ? 10 20 pf analog interface characteristics (v dd = 3.0 to 3.6 v, ta = ?40 to +85c) parameter symbol conditio n min. typ. max. unit sg output voltage v sg sg 1.30 1.4 1.50 v reset timing characteristics (v dd = 3.0 to 3.6 v, ta = ?40 to +85c) parameter symbol conditio n min. typ. max. unit reset signal time at power on t frst 90% or more of a nominal power supply voltage 250 ? ? ? s reset signal width t rstw ? 1 ? ? ? s reset start time t rsts ? 0 ? 1 ? s reset end time t rste ? ? ? 200 ms digital interface characteristics (v dd = 3.0 to 3.6 v, ta = ?40 to +85c) parameter symbol conditio n min. typ. max. unit t sdx 0 ? 100 ns t xd1 0 ? 100 ns t xd2 0 ? 100 ns digital output delay time pcm, adpcm interface t xd3 r dl = 500 ? , c dl = 50 pf 0 ? 100 ns
fedl7202-001-01 ML7202-001 18/65 microcontroller interface characteristics ( wr and rd pin independent control) (v dd = 3.0 to 3.6 v, ta = ?40 to +85c) parameter symbol condition min. typ. max. unit address & chip select setup time (with respect to wr ? ) t cws 10 ? ? ns address & chip select setup time (with respect to wr ? ) t cwh 3 ? ? ns wr pulse width t ww 20 ? ? ns data input setup time t dws 15 ? ? ns data input hold time t dwh 5 ? ? ns address & chip select setup time (with respect to rd ? ) t crs 10 ? ? ns address & chip select setup time (with respect to rd ? ) t crh 3 ? ? ns rd pulse width t rw 20 ? ? ns data output delay time t dod ? ? 15 ns data output hold time t doh 0 ? ? ns cs disable time t cd mtype = 0 c dl = 50 pf 10 ? ? ns microcontroller interface characteristics ( wr and rd pin shared control) (v dd = 3.0 to 3.6 v, ta = ?40 to +85c) parameter symbol condition min. typ. max. unit address setup time (with respect to wr ? ) t wrws 10 ? ? ns address setup time (with respect to wr ? ) t wrwh 3 ? ? ns wr pulse width t wrw 20 ? ? ns address setup time with respect to cs ? t csws 10 ? ? ns address setup time (with respect to cs ? ) t cswh 3 ? ? ns cs pulse width t csw 20 ? ? ns data input setup time t dws 15 ? ? ns data input hold time t dwh 5 ? ? ns address setup time (with respect to cs ? ) t csrs 10 ? ? ns address setup time (with respect to cs ? ) t csrh 3 ? ? ns data output delay time t dod ? ? 15 ns data output hold time t doh 0 ? ? ns cs disable time t cd mtype = 1 c dl = 50 pf 10 ? ? ns
fedl7202-001-01 ML7202-001 19/65 ac characteristics (dtmf and single tone) (v dd = 3.0 to 3.6 v, ta = ?40 to +85c) parameter symbol condit ion min. typ. max. unit df t1 dtmf tone ?1.5 ? +1.5 % frequency deviation df t2 single tone ?1.5 ? +1.5 % v tl dtmf (low tone group) ?10 ?8 ?6 dbm0 v th transmit side tone (gain setting: ?6db) dtmf (high tone group), single tone ?8 ?6 ?4 dbm0 v rl dtmf (low tone group) ?10 ?8 ?6 dbm0 tone reference output level v rh receive side tone (gain setting: ?6db) dtmf (high tone group), single tone ?8 ?6 ?4 dbm0 dtmf tone level relative value r dtmf v th /v tl , v rh /v rl 1 2 3 db ac characteristics (gain setting) (v dd = 3.0 to 3.6 v, ta = ?40 to +85c) parameter symbol condit ion min. typ. max. unit transmit/receive gain setting accuracy d g for all the gain setting values ?1 0 +1 db ac characteristics (vox function) (v dd = 3.0 to 3.6 v, ta = ?40 to +85c) parameter symbol conditio n min. typ. max. unit t vxon silence ?? voice ? 5 ? ms transmit vox detection time (voice/silence detection time) t vxoff voice ?? silence voxo1 and voxo2 pins see figure 4. difference beween voice/silence: 10 db 140/300 160/320 180/340 ms transmit vox detection threshold precision (voice detection threshold) d vx for the detection threshold setting value by cr21-b6, b5 (vox1 side) and cr22-b6, b5 (vox2 side) ?2.5 0 +2.5 db ac characteristics (tone detector function) (v dd = 3.0 to 3.6 v, ta = ?40 to +85c) parameter symbol condit ion min. typ. max. unit detection threshold precision d lac for set detection threshold ?2.5 0 +2.5 db detection frequency range d fr detection threshold: ?5.3dbm0 detection frequency setting: 2100hz ?10 0 +10 hz d nfrl ? ? ?80 hz non-detection frequency range d nfrh non-detect threshold setting: ?5.3dbm0 detection frequency setting: 2100hz +80 ? ? hz
fedl7202-001-01 ML7202-001 20/65 timing diagrams reset function dvdd1,2 a vdd p dn/rst internal processing t rste (90% or more) vout1,2 t srst t rstw reset initial mode 0 v vdd 0 v a bout 2.6 v "1" "0" reset initial mode normal operation t rste t frst 90% dvdd1,2 avdd 0 ns or longer input timing of pcm and adpcm bclka 1 t sb 2 10 9 8 76543 0 synca t bs t ws t ds t dh msb lsb ir1,ir2 bclkl 1 t sb 2 10 9 8 76543 0 syncl t bs t ws t ds t dh msb lsb pcm (*1) *1: pcmlni1, pcmlni2, pcmadi 1, pcmadi2, pcmaci1, pcmaci2
fedl7202-001-01 ML7202-001 21/65 output timing of pcm and adpcm bclka 1 t sb 2 10 9 8 7 6 5 4 3 0 synca t bs t ws t sdx t xd1 msb lsb is1, is2 bclkl 1 t sb 2 10 9 8 7 6 5 4 3 0 syncl t bs t ws pcm(*1) msb lsb t xd2 t xd3 t sdx t xd1 t xd2 t xd3 t sdx t sdx high-z high-z high-z high-z *1: pcmlno1, pcmlno2, pcmado1, pcmado2, pcmaco1, pcmaco2 microcontroller interface write/read ti ming (wr/rd independent control) r d t crs t crh t rw t doh t dod a 4 ? 0 c s wr d7 ? 0 t cws t cwh t ww t dwh t dws high-z high-z high-z t cd write timing read timing
fedl7202-001-01 ML7202-001 22/65 microcontroller interface write/read timing (wr/rd shared control) t csrs t csrh t csw t doh t dod t csws t cswh t csw t wrws t wrwh t wrw r d a 4 ? 0 c s wr d7 ? 0 t dwh t dws high-z high-z high-z t cd "1" write timing read timing
fedl7202-001-01 ML7202-001 23/65 functional description control registers table 1 shows a map of control registers. table 1-1 control register map address data contents register name a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr0 0 0 0 0 0 spdn ? ? #pcmsel #iosel ? ? #ope_ stat r/w cr1 0 0 0 0 1 dmwr ? ? ? ? ? ? ? r/w cr2 0 0 0 1 0 conta1 adpcm_ rst1 dthr1 tx_ mute1 rx_ mute1 rx_ mlv21 rx_ mlv11 rx_ mlv01 r/w cr3 0 0 0 1 1 conta2 adpcm_ rst2 dthr2 tx_ mute2 rx_ mute2 rx_ mlv22 rx_ mlv12 rx_ mlv02 r/w cr4 0 0 1 0 0 int ready ? ? ttdet2 rtdet2 ttdet1 rtdet1 r cr5 0 0 1 0 1 tgen_exe _flag2 vox_ out2 vox_ moni12 vox_ moni02 tgen_exe _flag1 vox_ out1 vox_ moni11 vox_ moni01 r cr6 0 0 1 1 0 a15 a14 a13 a12 a11 a10 a9 a8 r/w cr7 0 0 1 1 1 a7 a6 a5 a4 a3 a2 a1 a0 r/w cr8 0 1 0 0 0 d15 d14 d13 d12 d11 d10 d9 d8 r/w cr9 0 1 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 r/w cr10 0 1 0 1 0 ? ? ? ? ? ? ? ? ? cr11 0 1 0 1 1 ? ? ? #pcm_ sel41 #pcm_ sel31 #pcm_ sel21 #pcm_ sel11 #pcm_ sel01 r/w cr12 0 1 1 0 0 ? ? ? #pcm_ sel42 #pcm_ sel32 #pcm_ sel22 #pcm_ sel12 #pcm_ sel02 r/w cr13 0 1 1 0 1 ? ? ? #adpcm _sel41 #adpcm _sel31 #adpcm _sel21 #adpcm _sel11 #adpcm _sel01 r/w cr14 0 1 1 1 0 ? ? ? #adpcm _sel42 #adpcm _sel32 #adpcm _sel22 #adpcm _sel12 #adpcm _sel02 r/w cr15 0 1 1 1 1 ? ? ? ? ? ? ? ? ? note: in the r/w column, r/w: read/write enable, r: read only, ?: read/write inhibit note: in the data contents column, ?: reserved bit. do not change the initial value. #: control bit that can be changed only in initial mode
fedl7202-001-01 ML7202-001 24/65 table 1-2 control register map address data contents register name a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr16 1 0 0 0 0 tx_tone _gain31 tx_tone _gain21 tx_tone _gain11 tx_tone _gain01 rx_tone _gain31 rx_tone _gain21 rx_tone _gain11 r x_tone _gain01 r/w cr17 1 0 0 0 1 dtmf_ sel1 tx_tone _send1 rx_ton e_send1 tone41 tone31 tone21 tone11 tone01 r/w cr18 1 0 0 1 0 tx_tone _gain32 tx_tone _gain22 tx_tone _gain12 tx_tone _gain02 rx_tone _gain32 rx_tone _gain22 rx_tone _gain12 rx_tone _gain02 r/w cr19 1 0 0 1 1 dtmf_ sel2 tx_tone_ send2 rx_tone_ send2 tone42 tone32 tone22 tone12 tone02 r/w cr20 1 0 1 0 0 ? ? ? ? ? ? tdet_ en2 tdet_ en1 r/w cr21 1 0 1 0 1 vox_on 1 vox_on _lvl11 vox_on _lvl01 vox_off _time1 ? vox_in 1 rx_noise _lvl11 rx_noise _lvl01 r/w cr22 1 0 1 1 0 vox_on 2 vox_on _lvl12 vox_on _lvl02 vox_of f_time2 ? vox_in 2 rx_noise _lvl12 rx_noise _lvl02 r/w cr23 1 0 1 1 1 ? ? ? ? ? ? ? ? ? cr24 1 1 0 0 0 ? ? ? ? ? ? ? ? ? cr25 1 1 0 0 1 ? ? ? ? lpadl 11 lpadl 01 gpadl 11 gpadl 01 r/w cr26 1 1 0 1 0 ? ? ? ? lpadl 12 lpadl 02 gpadl 12 gpadl 02 r/w cr27 1 1 0 1 1 lthr1 laff_ rst1 lhld1 lhd1 lclp1 ? latt1 lgc1 r/w cr28 1 1 1 0 0 lthr2 laff_ rst2 lhld2 lhd2 lclp2 ? latt2 lgc2 r/w cr29 1 1 1 0 1 ? ? ? ? ? ? ? ? ? cr30 1 1 1 1 0 ? ? ? ? ? ? ? ? ? cr31 1 1 1 1 1 ? ? ? ? ? ? ? ? ? note: in the r/w column, r/w: read/write enable, r: read only, ?: read/write inhibit note: in the data contents column, ?: reserved bit. do not change the initial value. #: control bit that can be changed only in initial mode
fedl7202-001-01 ML7202-001 25/65 (1) cr0 (basic operation mode setting) b7 b6 b5 b4 b3 b2 b1 b0 cr0 spdn ? ? pcmsel iosel ? ? ope_ stat initial value (*1) 0 0 0 0 0 0 0 0 *1: the initial value refers to the value that is set when this lsi is reset by the pdn/rst pin. (also when reset by spdn of b7, the bits othe r than cr0-b7 are set to their initial value.) b7: software power-down control 0: normal operation 1: power-down/reset at power-down/reset, this lsi enters a power-down state. in this case, each bit of the control register, internal variables including internal data memories, and the echo canceler coefficients are reset. this lsi enters the initial mode about 200 ms after the release of power-down/reset. this bit is or?ed with the inverted pdn/rst signal internally. b6?b5: resrved bits b4: pcm coding format selection 0: ? -law 1: a-law pcm coding format selection bit fo r digital speech signals. set th is bit to ?0? to select the ? -law pcm coding format; set this bit to ?1? to select a-law pcm coding form at. the setting of this bit can be changed in initial mode only. b3: pcm signal i/o control pcm signal i/o control setting bit. (see figure 1 and figure 2) b2?b1: reserved bits b0: operation start control 0: initial mode 1: operation start initial mode: this lsi enters the initial mode about 200 ms after releas e of reset/power-down. start modification of the control registers and internal data memories after readin g ready(cr4-b6) consecutively and detecting ?1?. this lsi has several control registers and internal data memories which could be tuned only in this initial mode. for more details, please refer to table 1-1, table 1-2, figure 9, table 26, table 27 and table 28. in this mode, the pcm output pin is in a high impedance state. the pcm input pin is processed internally as idle pattern input and the line echo canceler, adpcm transcod er, tone generator, tone detector, and the mute and vox functions are disabled. operation start: by setting this bit to ?1?, ready (cr4-b6) is set to ?0? and the lsi enters a normal operation mode. the line echo canceler, adpcm transcoder, tone generator, tone detector, and mute and vox functions are enabled dependent upon the control register setting.
fedl7202-001-01 ML7202-001 26/65 (2) cr1 (internal data memory write control) b7 b6 b5 b4 b3 b2 b1 b0 cr1 dmwr ? ? ? ? ? ? ? initial value 0 0 0 0 0 0 0 0 b7: internal data memory write control 0: write inhibit 1: write enable this is a write command bit for internal data memory. by writing ?1? into this bit, data specified in cr8 (d1 5?d8) and cr9 (d7?d0) is written into the internal data memory whose address is specified by cr6 (a15?a8) and cr7 (a7?a0). for more details, please refer to descriptions under internal data memory access method. b6?b0: reserved bits
fedl7202-001-01 ML7202-001 27/65 (3) cr2 (channel 1 adpcm section operation mode and i/o signal setting) b7 b6 b5 b4 b3 b2 b1 b0 cr2 conta1 adpcm_ rst1 dthr1 tx_ mute1 rx_ mute1 rx_ mlv21 rx_ mlv11 rx_ mlv01 initial value 0 0 0 0 0 0 0 0 b7: channel 1 adpcm transcoder enable/through control 0: adpcm transcoder enabled mode 1: adpcm transcoder-through end-to-end 8-bit pcm mode when this bit is set to ?1?, the adpcm transcoder enters a through mode and the is1 pin is configured to be an 8-bit serial input and the ir1 pin an 8-bit serial output. b6: adpcm reset on the channel 1 transmit/receive side (accordin g to the g.726 specifications) 0: normal operation 1: reset when this bit is set to ?1?, the adpcm transcoder is rese t. while the transcoder is reset, inputs from ir1 pin and pcmadi1 pin become invalid and is1 pin and pcmado1 pin output idle patterns. b5: channel 1 end-to-end 4-bit adpcm transparent control 0: normal mode 1: end-to-end 4-bit adpcm transparent mode in through mode, end-to-end 4-bit adpcm transparent mode is applied and the pcm i/o pin is configured to be a 4-bit serial input/output. the line echo canceler, adpcm transcoder, tone generator, tone detector, and mute and vox functions are all disabled. b4: channel 1 transmit side adpcm data mute control 0: normal operation 1: mute when this bit is set to ?1?, is1 pin outputs idle patterns. b3: channel 1 receive side adpcm data mute enable control 0: normal operation 1: mute enabled the mute level set in b2, b1 and b0 is enabled. b2?b0: channel 1 receive side speech data mute level setting the voice bus mute level on the receive si de can be set by controlling this bit. table 2 channel 1 receive voice bus mute level setting rx_mlv21 rx_mlv11 rx_mlv01 level 0 0 0 through 0 0 1 ?6db 0 1 0 ?12db 0 1 1 ?18db 1 0 0 ?24db 1 0 1 ?30db 1 1 0 ?36db 1 1 1 mute
fedl7202-001-01 ML7202-001 28/65 (4) cr3 (channel 2 adpcm section operation mode and i/o signal setting) b7 b6 b5 b4 b3 b2 b1 b0 cr3 conta2 adpcm_ rst2 dthr2 tx_mut e2 rx_mut e2 rx_mlv 22 rx_mlv 12 rx_mlv 02 initial value 0 0 0 0 0 0 0 0 b7: channel 2 adpcm transcoder enable/through control 0: adpcm transcoder enabled mode 1: adpcm transcoder-through end-to-end 8-bit pcm mode when this bit is set to ?1?, the adpcm transcoder enters a through mode and the is2 pin is configured to be an 8-bit serial input and the ir2 pin an 8-bit serial output. b6: adpcm reset on the channel 2 transmit/receive side (accordin g to the g.726 specifications) 0: normal operation 1: reset when this bit is set to ?1?, the adpcm transcoder is rese t. while the transcoder is reset, inputs from ir1 pin and pcmadi2 pin become invalid and is2 pin and pcmado2 pin output idle patterns. b5: channel 2 end-to-end 4-bit adpcm transparent control 0: normal mode 1: end-to-end 4-bit adpcm transparent mode in through mode, end-to-end 4-bit adpcm transparent mode is applied and the pcm i/o pin is configured to be a 4-bit serial input/output. the line echo canceler, adpcm transcoder, tone generator, tone detector, and mute and vox functions are all disabled. b4: channel 2 transmit side adpcm data mute control 0: normal operation 1: mute when this bit is set to ?1?, is2 pin outputs idle patterns. b3: channel 2 receive side adpcm data mute enable control 0: normal operation 1: mute enabled the mute level set in b2, b1 and b0 is enabled. b2?b0: channel 2 receive side speech data mute level setting the voice bus mute level on the receive si de can be set by controlling this bit. table 3 channel 2 receive voice bus mute level setting rx_mlv22 rx_mlv12 rx_mlv02 level 0 0 0 through 0 0 1 ?6db 0 1 0 ?12db 0 1 1 ?18db 1 0 0 ?24db 1 0 1 ?30db 1 1 0 ?36db 1 1 1 mute
fedl7202-001-01 ML7202-001 29/65 (5) cr4 (ready and detection register, read only) b7 b6 b5 b4 b3 b2 b1 b0 cr4 int ready ? ? ttde t2 rtdet2 ttdet1 rtdet1 initial value 0 1 0 0 0 0 0 0 b7: interrupt status register 0: when the int pin is ?1? 1: when the int pin is ?0? register where the logic of the int pin is inverted. this regi ster reflects a status of the int pin. when the int pin is ?0?, ?1? is read. in other cases, ?0? is read. b6: initial mode status register 0: in normal operation mode (not in the initial mode) 1: in initial mode this lsi goes into the initial mode about 200 ms after release of power-down/reset. in initial mode, this bit becomes ?1?, which shows th at the internal data access is possible. by setting ope_stat (cr0-b0)="1", this lsi gets out of the initial mode and goes into normal operation mode as well as this bit is automatically set to ?0?. it could be known by checking this bit if the lsi is currently in the initial mode. b5?b4: reserved bits b3: channel 2 transmit side tone detection status register 0: not detected 1: detected detected/not detected status register bit of the tone detector on the channel 2 transmit side. for more details, please refer to figure 5. b2: channel 2 receive side tone detection status register 0: not detected 1: detected detected/not detected status register bit of the tone detector on the channe l 2 receive side. for more details, please refer to figure 5. b1: channel 1 transmit side tone detection status register 0: not detected 1: detected detected/not detected status register bit of the tone detector on the channel 1 transmit side. for more details, please refer to figure 5. b0: channel 1 receive side tone detection status register 0: not detected 1: detected detected/not detected status register bit of the tone detector on the channe l 1 receive side. for more details, please refer to figure 5.
fedl7202-001-01 ML7202-001 30/65 (6) cr5 (vox function status register, read only) b7 b6 b5 b4 b3 b2 b1 b0 cr5 tgen_exe _flag2 vox_ out2 vox_ moni12 vox_ moni02 tgen_exe _flag1 vox_ out1 vox_ moni11 vox_ moni01 initial value 0 0 0 0 0 0 0 0 b7: channel 2 tone generator execution status register 0: inactive 1: operating channel 2 tone generator execution status register bit. at th e start of tone generation, this bit is set to ?1? and when tone is not generated, the bit is set to ?0?. when the fade in/fade out function is enabled, this bit does not go back to ?0? at the change of tx_tone_send2 (cr19-b6) or rx_tone_send2 (cr19-b5 ) from ?1? to ?0?, and retains ?1? till the completion of fade out, and after the comp letion of fade out, the bit is set to ?0?. even after this bit has changed to ?0?, generation of tone signals may be continued for several sync cycles due to the lsi-internal processing delay. b6: channel 2 transmit side voice/silence detection 0: silence 1: voice b5?b4: channel 2 transmit side detected power indicator indicator bits for channel 2 transmit side power. by reading these bits, power of signals on channel 2 transmit side relative to voice/silence threshold set by cr22-b6, b5 can be known. this function is enabled when cr22-b7 is set to ?1?, that is, vox function is on. when cr22-b7 is set to ?0?, that is, vox function is off, these bits stay ?0? independently upon channel 2 transmit side power. table 4 channel 2 transmit side relative power vox_moni12 vox_moni02 relative power against the transmit side voice/silence threshold set by cr22-b6 and ?b5 0 0 ?10 db or lower, or vox disabled 0 1 ?5 to ?10 db 1 0 0 to ?5 db 1 1 0 db or higher b3: channel 1 tone generator execution status register 0: inactive 1: operating channel 1 tone generator execution status register bit. at th e start of tone gernation, this bit is set to ?1? and when tone is not generated, the bit is set to ?0?. when the fade in/fade out function is enabled, this bit does not go back to ?0? at the change of tx_tone_send1 (cr17-b6) or rx_tone_send1 (cr17-b5 ) from ?1? to ?0?, and retains ?1? till the completion of fade out, and after the comp letion of fade out, the bit is set to ?0?. even after this bit has changed to ?0?, generation of tone signals may be continued for several sync cycles due to the lsi-internal processing delay. b2: channel 1 transmit side voice/silence detection 0: silence 1: voice
fedl7202-001-01 ML7202-001 31/65 b1?b0: channel 1 transmit side detected power indicator indicator bits for channel 1 transmit side power. by reading these bits, power of signals on channel 1 transmit side relative to voice/silence threshold set by cr21-b6, b5 can be known. this function is enabled when cr21-b7 is set to ?1?, that is, vox function is on. when cr21-b7 is set to ?0?, that is, vox function is off, these bits stay ?0? independently upon channel 1 transmit side power. table 5 channel 1 transmit side relative power vox_moni11 vox_moni01 relative power against the transmit side voice/silence threshold set by cr21-b6 and ?b5 0 0 ?10 db or lower, or vox disabled 0 1 ?5 to ?10 db 1 0 0 to ?5 db 1 1 0 db or higher
fedl7202-001-01 ML7202-001 32/65 (7) cr6 (internal data memory write register) b7 b6 b5 b4 b3 b2 b1 b0 cr6 a15 a14 a13 a12 a11 a10 a9 a8 initial value 0 1 1 1 0 0 1 0 b7?0: upper address control for internal data memory upper address setting register for internal data memory. see the internal data memory access for how to write into internal data memory. the initial value of cr6 indicates the upper two digits of ?ml7202?. (8) cr7 (internal data memory write register) b7 b6 b5 b4 b3 b2 b1 b0 cr7 a7 a6 a5 a4 a3 a2 a1 a0 initial value 0 0 0 0 0 0 1 0 b7?0: lower address control for internal data memory lower address setting register for internal data memory. see the internal data memory access method for how to write into internal data memory. the initial value of cr7 indicates the lower two digits of ?ml7202?. (9) cr8 (internal data memory write register) b7 b6 b5 b4 b3 b2 b1 b0 cr8 d15 d14 d13 d12 d11 d10 d9 d8 initial value 0 0 0 0 0 0 0 1 b7?0: upper data control for internal data memory upper data setting register for internal data memory. see the internal data memory access method for how to write into internal data memory. the initial value of cr8 indicates ?-001? of ?ML7202-001?. (10) cr9 (internal data memory write register) b7 b6 b5 b4 b3 b2 b1 b0 cr9 d7 d6 d5 d4 d3 d2 d1 d0 initial value 0 0 0 0 0 0 0 1 b7?0: lower data control for internal data memory lower data setting register for internal data memory. see the internal data memory access method for how to write into internal data memory. (11) cr10 (reserved register) b7 b6 b5 b4 b3 b2 b1 b0 cr10 ? ? ? ? ? ? ? ? initial value 0 0 0 0 0 0 0 0 b7?b0: reserved bits
fedl7202-001-01 ML7202-001 33/65 (12) cr11 (channel 1 pcm i/o time slot assignment) b7 b6 b5 b4 b3 b2 b1 b0 cr11 ? ? ? pcm_ sel41 pcm_ sel31 pcm_ sel21 pcm_ sel11 pcm_ sel01 initial value 0 0 0 0 0 0 0 0 b7?b5: reserved bits b4?b0: pcm codec time slot assignment control registers to control time pcm data slot assignment for channel 1. the setting of thse bits can be changed only in initial mode.the pcm data can be assigned to an arbitrary time slot as per table 6 herebelow. the pcm i/o pins subject to this time slot assignment are as follo ws: pcmlni1, pcmlno1, pcmaci1, pcmaco1, pcmadi1, and pcmado1. table 6 pcm codec time slot assignment b4 b3 b2 b1 b0 assigned time slot b4 b3 b2 b1 b0 assigned time slot 0 0 0 0 0 time slot 1 1 0 0 0 0 time slot 17 0 0 0 0 1 time slot 2 1 0 0 0 1 time slot 18 0 0 0 1 0 time slot 3 1 0 0 1 0 time slot 19 0 0 0 1 1 time slot 4 1 0 0 1 1 time slot 20 0 0 1 0 0 time slot 5 1 0 1 0 0 time slot 21 0 0 1 0 1 time slot 6 1 0 1 0 1 time slot 22 0 0 1 1 0 time slot 7 1 0 1 1 0 time slot 23 0 0 1 1 1 time slot 8 1 0 1 1 1 time slot 24 0 1 0 0 0 time slot 9 1 1 0 0 0 time slot 25 0 1 0 0 1 time slot 10 1 1 0 0 1 time slot 26 0 1 0 1 0 time slot 11 1 1 0 1 0 time slot 27 0 1 0 1 1 time slot 12 1 1 0 1 1 time slot 28 0 1 1 0 0 time slot 13 1 1 1 0 0 time slot 29 0 1 1 0 1 time slot 14 1 1 1 0 1 time slot 30 0 1 1 1 0 time slot 15 1 1 1 1 0 time slot 31 0 1 1 1 1 time slot 16 1 1 1 1 1 time slot 32
fedl7202-001-01 ML7202-001 34/65 (13) cr12 (channel 2 pcm i/o time slot assignment) b7 b6 b5 b4 b3 b2 b1 b0 cr12 ? ? ? pcm_ sel42 pcm_ sel32 pcm_ sel22 pcm_ sel12 pcm_ sel02 initial value 0 0 0 0 0 0 0 0 b7?b5: reserved bits b4?b0: pcm codec time slot assignment control registers to control pcm data time slot assignment for channel 2. the setting of these bits can be changed only in initial mode. the pcm data can be assigned to an arbitrar y time slot as per table 7 herebelow. the pcm i/o pins subject to this time slot assignment are as follo ws: pcmlni2, pcmlno2, pcmaci2, pcmaco2, pcmadi2, and pcmado2. table 7 pcm codec time slot assignment b4 b3 b2 b1 b0 assigned time slot b4 b3 b2 b1 b0 assigned time slot 0 0 0 0 0 time slot 1 1 0 0 0 0 time slot 17 0 0 0 0 1 time slot 2 1 0 0 0 1 time slot 18 0 0 0 1 0 time slot 3 1 0 0 1 0 time slot 19 0 0 0 1 1 time slot 4 1 0 0 1 1 time slot 20 0 0 1 0 0 time slot 5 1 0 1 0 0 time slot 21 0 0 1 0 1 time slot 6 1 0 1 0 1 time slot 22 0 0 1 1 0 time slot 7 1 0 1 1 0 time slot 23 0 0 1 1 1 time slot 8 1 0 1 1 1 time slot 24 0 1 0 0 0 time slot 9 1 1 0 0 0 time slot 25 0 1 0 0 1 time slot 10 1 1 0 0 1 time slot 26 0 1 0 1 0 time slot 11 1 1 0 1 0 time slot 27 0 1 0 1 1 time slot 12 1 1 0 1 1 time slot 28 0 1 1 0 0 time slot 13 1 1 1 0 0 time slot 29 0 1 1 0 1 time slot 14 1 1 1 0 1 time slot 30 0 1 1 1 0 time slot 15 1 1 1 1 0 time slot 31 0 1 1 1 1 time slot 16 1 1 1 1 1 time slot 32
fedl7202-001-01 ML7202-001 35/65 (14) cr13 (channel 1 adpcm i/o time slot assignment) b7 b6 b5 b4 b3 b2 b1 b0 cr13 ? ? ? adpcm_ sel41 adpcm_ sel31 adpcm_ sel21 adpcm_ sel11 adpcm_ sel01 initial value 0 0 0 0 0 0 0 0 b7?b5: reserved bits b4?b0: adpcm codec time slot assignment control registers to control adpcm data time assignment for channel 1. the setting of these bits can be changed only in initial mode. the adpcm data can be assigned to an arbitrary time slot as per table 8. the adpcm i/o pins subject to this time slot assignment are the is1and ir1 pins. table 8 adpcm codec time slot assignment b4 b3 b2 b1 b0 assigned time slot b4 b3 b2 b1 b0 assigned time slot 0 0 0 0 0 time slot 1 1 0 0 0 0 time slot 17 0 0 0 0 1 time slot 2 1 0 0 0 1 time slot 18 0 0 0 1 0 time slot 3 1 0 0 1 0 time slot 19 0 0 0 1 1 time slot 4 1 0 0 1 1 time slot 20 0 0 1 0 0 time slot 5 1 0 1 0 0 time slot 21 0 0 1 0 1 time slot 6 1 0 1 0 1 time slot 22 0 0 1 1 0 time slot 7 1 0 1 1 0 time slot 23 0 0 1 1 1 time slot 8 1 0 1 1 1 time slot 24 0 1 0 0 0 time slot 9 1 1 0 0 0 time slot 25 0 1 0 0 1 time slot 10 1 1 0 0 1 time slot 26 0 1 0 1 0 time slot 11 1 1 0 1 0 time slot 27 0 1 0 1 1 time slot 12 1 1 0 1 1 time slot 28 0 1 1 0 0 time slot 13 1 1 1 0 0 time slot 29 0 1 1 0 1 time slot 14 1 1 1 0 1 time slot 30 0 1 1 1 0 time slot 15 1 1 1 1 0 time slot 31 0 1 1 1 1 time slot 16 1 1 1 1 1 time slot 32
fedl7202-001-01 ML7202-001 36/65 (15) cr14 (channel 2 adpcm i/o time slot assignment) b7 b6 b5 b4 b3 b2 b1 b0 cr14 ? ? ? adpcm_ sel42 adpcm_ sel32 adpcm_ sel22 adpcm_ sel12 adpcm_ sel02 initial value 0 0 0 0 0 0 0 0 b7?b5: reserved bits b4?b0: adpcm codec time slot assignment control registers to control adpcm data time slot assignment for channel 2. the setting of these bits can be changed only in initial mode. the adpcm data can be assigned to an ar bitrary time slot as per ta ble 9 herebelow. the adpcm i/o subject to this time slot assignment are the is2 and ir2 pins. table 9 adpcm codec time slot assignment b4 b3 b2 b1 b0 assigned time slot b4 b3 b2 b1 b0 assigned time slot 0 0 0 0 0 time slot 1 1 0 0 0 0 time slot 17 0 0 0 0 1 time slot 2 1 0 0 0 1 time slot 18 0 0 0 1 0 time slot 3 1 0 0 1 0 time slot 19 0 0 0 1 1 time slot 4 1 0 0 1 1 time slot 20 0 0 1 0 0 time slot 5 1 0 1 0 0 time slot 21 0 0 1 0 1 time slot 6 1 0 1 0 1 time slot 22 0 0 1 1 0 time slot 7 1 0 1 1 0 time slot 23 0 0 1 1 1 time slot 8 1 0 1 1 1 time slot 24 0 1 0 0 0 time slot 9 1 1 0 0 0 time slot 25 0 1 0 0 1 time slot 10 1 1 0 0 1 time slot 26 0 1 0 1 0 time slot 11 1 1 0 1 0 time slot 27 0 1 0 1 1 time slot 12 1 1 0 1 1 time slot 28 0 1 1 0 0 time slot 13 1 1 1 0 0 time slot 29 0 1 1 0 1 time slot 14 1 1 1 0 1 time slot 30 0 1 1 1 0 time slot 15 1 1 1 1 0 time slot 31 0 1 1 1 1 time slot 16 1 1 1 1 1 time slot 32 (16) cr15 (reserved register) b7 b6 b5 b4 b3 b2 b1 b0 cr15 ? ? ? ? ? ? ? ? initial value 1 0 1 0 0 0 0 0 b7?b0: reserved bits
fedl7202-001-01 ML7202-001 37/65 (17) cr16 (channel 1 tone generator gain adjustment) b7 b6 b5 b4 b3 b2 b1 b0 cr16 tx_tone _gain31 tx_tone _gain21 tx_tone _gain11 tx_tone _gain01 rx_tone _gain31 rx_tone _gain21 rx_tone _gain11 rx_tone _gain01 initial value 0 0 0 0 0 0 0 0 b7?b4: tone generator transmit side gain adjustment bits for adjusting the transmit side attenuator (atttgtx1) gain on the channel 1 tone generator. transmit side gain can be changed by controlling these bits. table 10 transmit side tone generator gain setting b7 b6 b5 b4 tone generator gain b7 b6 b5 b4 tone generator gain 0 0 0 0 ?36 db 1 0 0 0 ?20 db 0 0 0 1 ?34 db 1 0 0 1 ?18 db 0 0 1 0 ?32 db 1 0 1 0 ?16 db 0 0 1 1 ?30 db 1 0 1 1 ?14 db 0 1 0 0 ?28 db 1 1 0 0 ?12 db 0 1 0 1 ?26 db 1 1 0 1 ?10 db 0 1 1 0 ?24 db 1 1 1 0 ?8 db 0 1 1 1 ?22 db 1 1 1 1 ?6 db b3?b0: tone generator recei ve side gain adjustment bits for adjusting the receive side atte nuator (atttgtx1) gain on the channel 1 tone generator. receive side gain can be changed by controlling these bits. table 11 receive side tone generator gain setting b3 b2 b1 b0 tone generator gain b3 b2 b1 b0 tone generator gain 0 0 0 0 ?36 db 1 0 0 0 ?20 db 0 0 0 1 ?34 db 1 0 0 1 ?18 db 0 0 1 0 ?32 db 1 0 1 0 ?16 db 0 0 1 1 ?30 db 1 0 1 1 ?14 db 0 1 0 0 ?28 db 1 1 0 0 ?12 db 0 1 0 1 ?26 db 1 1 0 1 ?10 db 0 1 1 0 ?24 db 1 1 1 0 ?8 db 0 1 1 1 ?22 db 1 1 1 1 ?6 db
fedl7202-001-01 ML7202-001 38/65 the original level of output tone from tone_a (high-tone group) generator and tone_b (low-tone group) generator are fixed as follows (see figure 6): dtmf tone (low-tone group) : ?2 dbm0 dtmf tone (high-tone group) and single tone : 0 dbm0 hence, for instance, assuming tgen_g ain_h1 and tgen_gain_l1 are set to 0 db (default), if you set the cr16-b3, b2, b1, b0 to [1, 1, 1, 1] (= -6db), then, the output level from the pcmlno1 pin will be as follows; dtmf tone (low-tone group) : ?8 dbm0 dtmf tone (high-tone group) and single tone : ?6 dbm0 note: as shown in figure 6, the atttgtx1 and the atttgrx1 ar e attenuators to tune a level of tones after addition of output of tone_a generator and that of tone_b generator. on the other hand, levels of tones before addition of output of tone_a generator and that of tone_b generator can be tuned by the tgen_gain_h1 and the tgen_gain_l1. each gain of the tgen_gain_h1 and the tgen_gain_ l1 can be changed through internal data memory access. see the write method of the internal da ta memory access method and table 26 internal data memory related control registers for the way to change the internal data memory setting. (18) cr17 (channel 1 tone generator operation mode and frequency setting) b7 b6 b5 b4 b3 b2 b1 b0 cr17 dtmf_ sel1 tx_tone _send1 rx_tone _send1 tone41 tone31 tone21 tone11 tone01 initial value 0 0 0 0 0 0 0 0 b7: selection between dtmf tone and single tone 0: single tone 1: dtmf tone a register bit to select between single tone and dtmf tone for channel 1 tone generator. when this bit is set to ?1?, dtmf tone is selected and when this bit is set to ?0 ?, single tone is selected. the frequency of tone can be changed by cr17-b4, b3, b2, b1, b0 and internal data memory access. b6: execution of tone generation toward the transmit side 0: does not execute tone generation 1: executes tone generation selection bit for execution of tone generation toward the transmit side on the channel 1. this lsi does not have tone generators respectively toward transmit side and toward receive side but shares the common tone generators toward both directions. hence, if the execution of tone generation toward the transmit side gets enabled while tone generation on the receive side is being enabled, the transmit side would start receiving tone signals at an arbitrary and perhaps odd timing in terms of a phase of the waveform of the tone so that slight noises may take place dependent upon the timing. when using the tone generator in such a manner, it is recommended to utilize the tone fade function to minimize the noises. b5: execution of tone genera tion toward the receive side 0: does not execute tone generation 1: executes tone generation selection bit for execution of tone generation toward the receive side on the channel 1. this lsi does not have tone generators respectively toward transmit side and toward receive side but shares the common tone generators toward both directions. hence, if the execution of tone generation toward the receive side gets enabled while tone generation on the transmit side is being enabled, the receive side would start receiving tone signals at an arbitrary and perhaps odd timing in terms of a phase of the waveform of the tone so that slight noises may take place dependent upon the timing. when using the tone generator in such a manner, it is recommended to utilize the tone fade function to minimize the noises.
fedl7202-001-01 ML7202-001 39/65 b4?b0: tone frequency setting output frequency setting bit of channel 1 tone generator table 12 tone generator output frequency setting (when cr17-b7=?1?) b4 b3 b2 b1 b0 frequency * 0 0 0 0 697 hz + 1209 hz (1) * 0 0 0 1 697 hz + 1336 hz (2) * 0 0 1 0 697 hz + 1477 hz (3) * 0 0 1 1 697 hz + 1633 hz (a) * 0 1 0 0 770 hz + 1209 hz (4) * 0 1 0 1 770 hz + 1336 hz (5) * 0 1 1 0 770 hz + 1477 hz (6) * 0 1 1 1 770 hz + 1633 hz (b) * 1 0 0 0 852 hz + 1209 hz (7) * 1 0 0 1 852 hz + 1336 hz (8) * 1 0 1 0 852 hz + 1477 hz (9) * 1 0 1 1 852 hz + 1633 hz (c) * 1 1 0 0 941 hz + 1209 hz (*) * 1 1 0 1 941 hz + 1336 hz (0) * 1 1 1 0 941 hz + 1477 hz (#) * 1 1 1 1 941 hz + 1633 hz (d) table 13 tone generator output frequency setting (when cr17-b7=?0?) the following table shows default single tone frequencies. b4 b3 b2 b1 b0 frequency b4 b3 b2 b1 b0 frequency 0 0 0 0 0 440 hz 1 0 0 0 0 1109 hz 0 0 0 0 1 466 hz 1 0 0 0 1 1175 hz 0 0 0 1 0 494 hz 1 0 0 1 0 1245 hz 0 0 0 1 1 523 hz 1 0 0 1 1 1319 hz 0 0 1 0 0 554 hz 1 0 1 0 0 1397 hz 0 0 1 0 1 587 hz 1 0 1 0 1 1480 hz 0 0 1 1 0 622 hz 1 0 1 1 0 1568 hz 0 0 1 1 1 659 hz 1 0 1 1 1 1661 hz 0 1 0 0 0 698 hz 1 1 0 0 0 1760 hz 0 1 0 0 1 740 hz 1 1 0 0 1 400 hz 0 1 0 1 0 784 hz 1 1 0 1 0 1000 hz 0 1 0 1 1 831 hz 1 1 0 1 1 2000 hz 0 1 1 0 0 880 hz 1 1 1 0 0 2667 hz 0 1 1 0 1 932 hz 1 1 1 0 1 1300 hz 0 1 1 1 0 988 hz 1 1 1 1 0 2080 hz 0 1 1 1 1 1047 hz 1 1 1 1 1 3000 hz the frequency for a single tone can be tuned in initial mode th rough internal data memory access. see the write method of the internal data memory access method and table 26 internal data memory related control registers for the way to change the internal data memory setting.
fedl7202-001-01 ML7202-001 40/65 (19) cr18 (channel 2 tone generator gain adjustment) b7 b6 b5 b4 b3 b2 b1 b0 cr18 tx_tone _gain32 tx_tone _gain22 tx_tone _gain12 tx_tone _gain02 rx_tone _gain32 rx_tone _gain22 rx_tone _gain12 rx_tone _gain02 initial value 0 0 0 0 0 0 0 0 b7?b4: tone generator transmit side gain adjustment bits for adjusting the transmit side attenuator (atttgtx2) gain on the channel 2 tone generator. transmit side gain can be changed by controlling these bits. table 14 transmit side tone generator gain setting b7 b6 b5 b4 tone generator gain b7 b6 b5 b4 tone generator gain 0 0 0 0 ?36 db 1 0 0 0 ?20 db 0 0 0 1 ?34 db 1 0 0 1 ?18 db 0 0 1 0 ?32 db 1 0 1 0 ?16 db 0 0 1 1 ?30 db 1 0 1 1 ?14 db 0 1 0 0 ?28 db 1 1 0 0 ?12 db 0 1 0 1 ?26 db 1 1 0 1 ?10 db 0 1 1 0 ?24 db 1 1 1 0 ?8 db 0 1 1 1 ?22 db 1 1 1 1 ?6 db b3?b0: tone generator recei ve side gain adjustment bits for adjusting the receive side atte nuator (atttgtx2) gain on the channel 2 tone generator. receive side gain can be changed by controlling these bits. table 15 transmit side tone generator gain setting b3 b2 b1 b0 tone generator gain b3 b2 b1 b0 tone generator gain 0 0 0 0 ?36 db 1 0 0 0 ?20 db 0 0 0 1 ?34 db 1 0 0 1 ?18 db 0 0 1 0 ?32 db 1 0 1 0 ?16 db 0 0 1 1 ?30 db 1 0 1 1 ?14 db 0 1 0 0 ?28 db 1 1 0 0 ?12 db 0 1 0 1 ?26 db 1 1 0 1 ?10 db 0 1 1 0 ?24 db 1 1 1 0 ?8 db 0 1 1 1 ?22 db 1 1 1 1 ?6 db
fedl7202-001-01 ML7202-001 41/65 the original level of output tone from tone_c (high-tone group) generator and tone_d (low-tone group) generator are as follows (see figure 6): dtmf tone (low-tone group) : ?2 dbm0 dtmf tone (high-tone group) and single tone : 0 dbm0 hence, for instance, assuming tgen_g ain_h2 and tgen_gain_l2 are set to 0 db (default), if you set the cr18-b3, b2, b1, b0 to [1, 1, 1, 1] (= -6db), then, the output level from the pcmlno2 pin will be as follows; dtmf tone (low-tone group) : ?8 dbm0 dtmf tone (high-tone group) and single tone : ?6 dbm0 note: as shown in figure 6, the atttgtx2 and the atttgrx2 ar e attenuators to tune a level of tones after addition of output of tone_c generator and that of tone_d generator. on the other hand, levels of tones before addition of output of tone_c generator and that of tone_d generator can be tuned by the tgen_gain_h2 and the tgen_gain_l2. each gain of the tgen_gain_h2 and the tgen_gain_ l2 can be changed through internal data memory access. see the write method of the internal da ta memory access method and table 26 internal data memory related control registers for the way to change the internal data memory setting.
fedl7202-001-01 ML7202-001 42/65 (20) cr19 (channel 2 tone generator operation mode and frequency setting) b7 b6 b5 b4 b3 b2 b1 b0 cr19 dtmf_ sel2 tx_tone _send2 rx_tone _send2 tone42 tone32 tone22 tone12 tone02 initial value 0 0 0 0 0 0 0 0 b7: selection between dtmf tone and single tone 0: single tone 1: dtmf tone a register bit to select between single tone and dtmf tone for channel 2 tone generator. when this bit is set to ?1?, dtmf tone is selected and when this bit is set to ?0 ?, single tone is selected. the frequency of tone can be changed by cr19-b4, b3, b2, b1, b0 and internal data memory access. b6: execution of tone generation toward the transmit side 0: does not execute tone generation 1: executes tone generation selection bit for execution of tone generation toward the transmit side on the channel 2. this lsi does not have tone generators respectively toward transmit side and toward receive side but shares the common tone generators toward both directions. hence, if the execution of tone generation toward the transmit side gets enabled while tone generation on the receive side is being enabled, the transmit side would start receiving tone signals at an arbitrary and perhaps odd timing in terms of a phase of the waveform of the tone so that slight noises may take place dependent upon the timing. when using the tone generator in such a manner, it is recommended to utilize the tone fade function to minimize the noises. b5: execution of tone genera tion toward the receive side 0: does not execute tone generation 1: execute tone generation selection bit for execution of tone generation toward the receive side on the channel 2. this lsi does not have tone generators respectively toward transmit side and toward receive side but shares the common tone generators toward both directions. hence, if the execution of tone generation toward the receive side gets enabled while tone generation on the transmit side is being enabled, the receive side would start receiving tone signals at an arbitrary and perhaps odd timing in terms of a phase of the waveform of the tone so that slight noises may take place dependent upon the timing. when using the tone generator in such a manner, it is recommended to utilize the tone fade function to minimize the noises. b4?b0: tone frequency setting output frequency setting bit of channel 2 tone generator table 16 tone generator output frequency setting (when cr19-b7=?1?) b4 b3 b2 b1 b0 frequency * 0 0 0 0 697 hz + 1209 hz (1) * 0 0 0 1 697 hz + 1336 hz (2) * 0 0 1 0 697 hz + 1477 hz (3) * 0 0 1 1 697 hz + 1633 hz (a) * 0 1 0 0 770 hz + 1209 hz (4) * 0 1 0 1 770 hz + 1336 hz (5) * 0 1 1 0 770 hz + 1477 hz (6) * 0 1 1 1 770 hz + 1633 hz (b) * 1 0 0 0 852 hz + 1209 hz (7) * 1 0 0 1 852 hz + 1336 hz (8) * 1 0 1 0 852 hz + 1477 hz (9) * 1 0 1 1 852 hz + 1633 hz (c) * 1 1 0 0 941 hz + 1209 hz (*) * 1 1 0 1 941 hz + 1336 hz (0) * 1 1 1 0 941 hz + 1477 hz (#) * 1 1 1 1 941 hz + 1633 hz (d)
fedl7202-001-01 ML7202-001 43/65 table 17 tone generator output frequency setting (when cr19-b7=?0?) the following table shows default single tone frequencies. b4 b3 b2 b1 b0 frequency b4 b3 b2 b1 b0 frequency 0 0 0 0 0 440 hz 1 0 0 0 0 1109 hz 0 0 0 0 1 466 hz 1 0 0 0 1 1175 hz 0 0 0 1 0 494 hz 1 0 0 1 0 1245 hz 0 0 0 1 1 523 hz 1 0 0 1 1 1319 hz 0 0 1 0 0 554 hz 1 0 1 0 0 1397 hz 0 0 1 0 1 587 hz 1 0 1 0 1 1480 hz 0 0 1 1 0 622 hz 1 0 1 1 0 1568 hz 0 0 1 1 1 659 hz 1 0 1 1 1 1661 hz 0 1 0 0 0 698 hz 1 1 0 0 0 1760 hz 0 1 0 0 1 740 hz 1 1 0 0 1 400 hz 0 1 0 1 0 784 hz 1 1 0 1 0 1000 hz 0 1 0 1 1 831 hz 1 1 0 1 1 2000 hz 0 1 1 0 0 880 hz 1 1 1 0 0 2667 hz 0 1 1 0 1 932 hz 1 1 1 0 1 1300 hz 0 1 1 1 0 988 hz 1 1 1 1 0 2080 hz 0 1 1 1 1 1047 hz 1 1 1 1 1 3000 hz the frequency for a single tone can be tuned in initial mode th rough internal data memory access. see the write method of the internal data memory access method and table 26 internal data memory related control registers for the way to change the internal data memory setting.
fedl7202-001-01 ML7202-001 44/65 (21) cr20 (tone detector operation setting) b7 b6 b5 b4 b3 b2 b1 b0 cr20 ? ? ? ? ? ? tdet_ en2 tdet_ en1 initial value 0 0 0 0 0 0 0 0 b7?b2: reserved bits b1: channel 2 tone detector on/off control 0: off 1: on channel 2 tone detector on/off selection bit. when this bit is set to ?1?, the detector is set to on and cr4-b3 and b2 (ttdet2 and rtdet2) is enabled to shows the tone detection results. the tone detector consists of a detection section, an on guard timer, and an off guard timer. the default of the detection frequency is 2100 hz, the default of the detectio n threshold is ?5.3 dbm0, the default of the on guard timer is 5 ms, and that of the off guard timer is 5 ms. th e detection frequency, detection threshold, and on guard and off guard times can be changed th rough internal data memory access. b0: channel 1 tone detector on/off control 0: off 1: on channel 1 tone detector on/off selection bit. when this bit is set to ?1?, the detector is set to on and cr4-b1 and b0 (ttdet1 and rtdet1) is enabled to shows the tone detection results. the tone detector consists of a detection section, an on guard timer, and an off guard timer. the default of the detection frequency is 2100 hz, the default of the detectio n threshold is ?5.3 dbm0, the default of the on guard timer is 5 ms, and that of the off guard timer is 5 ms. the detection frequency, detection threshold, and on guard and off guard times can be changed through internal data memory access.
fedl7202-001-01 ML7202-001 45/65 (22) cr21 (channel 1 vox function control) b7 b6 b5 b4 b3 b2 b1 b0 cr21 vox_on 1 vox_on _lvl11 vox_on _lvl01 vox_off _time1 ? vox_in1 rx_noise _lvl11 rx_noise _lvl01 initial value 0 0 0 0 0 0 0 0 b7: channel 1 vox function on/off control 0: off 1: on channel 1 vox function on/off selection bit. by setting th is bit to ?1?, on the transmit side, the voice/silence detection is enabled; on the receive side, background noise generation as per an input into the voxi1 pin is enabled. when this bit is set to ?0?, the settings of the cr21-b6 to b4, b2 to b0 become invalid and the cr5-b1 to b0 stays ?0?. b6?b5: voice/silence detection threshold setting on the channel 1 transmit side bits for setting the voice/silence detection threshold on the channel 1 transmit side table 18 channel 1 transmit side voice/silence detection threshold setting vox_on_lvl11 vox_on_lvl01 threshold 0 0 ?20 dbm0 0 1 ?25 dbm0 1 0 ?30 dbm0 1 1 ?35 dbm0 note: for the detection threshold, a pad from ?1 db to ?5 db can be inserted for the values indicated above. the value of the adjusting pad can be changed in initial mode only. see the internal data memory access method and table 26 internal data memory related control registers for the way to change the internal data memory setting. b4: channel 1 hang-over time (see figure 4) setting 0: 160 ms 1: 320 ms channel 1 hang-over time selection bit. by controlling this bit, a silence detection guard time from voice to silence can be set. b3: reserved bit b2: vox input signal setting on the channel 1 receive side 0: internal background noise transmit 1: voi ce receive signal transmit vox input signal setting bit on the channel 1 transmit side. when this bit is set to ?1?, receive side speech signals are fed to the rinl1. when this bit is set to ?0?, the background noise generator?s output is fed to the rinl1 instead of the receive side speech signals. when using this bit, set th e voxi1 pin to ?0?. when the application has a means to de tect silence with the receive side sp eech signals, this function could be made use of as comfort noise generator. b1?b0: channel 1 external setting background noise level table 19 channel 1 receive side background noise level setting rx_noise_lvl11 rx_noise_lvl01 level 0 0 no noise 0 1 ?55 dbm0 1 0 ?45 dbm0 1 1 ?35 dbm0
fedl7202-001-01 ML7202-001 46/65 (23) cr22 (channel 2 vox function control) b7 b6 b5 b4 b3 b2 b1 b0 cr22 vox_on 2 vox_on _lvl12 vox_on _lvl02 vox_off _time2 ? vox_in2 rx_noise _lvl12 rx_noise _lvl02 initial value 0 0 0 0 0 0 0 0 b7: channel 2 vox function on/off control 0: off 1: on channel 2 vox function on/off selection bit. by setting th is bit to ?1?, on the transmit side, the voice/silence detection is enabled; on the receive side, background noise generation as per an input into the voxi2 pin is enabled. when this bit is set to ?0?, the settings of the cr22-b6 to b4, b2 to b0 become invalid and the cr5-b5 to b4 stays ?0?. b6?b5: voice/silence detection threshold setting on the channel 2 transmit side bits for setting the voice/silence detection threshold on the channel 2 transmit side table 20 channel 2 transmit side voice/silence detection threshold setting vox_on_lvl12 vox_on_lvl02 threshold 0 0 ?20 dbm0 0 1 ?25 dbm0 1 0 ?30 dbm0 1 1 ?35 dbm0 note: for the detection threshold, a pad from ?1 db to ?5 db can be inserted for the value indicated above. the value of the adjusting pad can be changed in initial mode only. see the internal data memory access method and table 26 internal data memory related control registers for the way to change the internal data memory setting. b4: channel 2 hang-over time (see figure 4) setting 0: 160 ms 1: 320 ms channel 2 hang-over time selection bit. by controlling this bit, a silence detection guard time from voice to silence can be set. b3: reserved bit b2: vox input signal setting on the channel 2 receive side 0: internal background noise transmit 1: voi ce receive signal transmit vox input signal setting bit on the channel 2 transmit side. when this bit is set to ?1?, receive side speech signals are fed to the rinl2. when this bit is set to ?0?, the background noise generator?s output is fed to the rinl2 instead of the receive side speech signals. when using this bit, set th e voxi2 pin to ?0?. when the application has a means to de tect silence with the receive side sp eech signals, this function could be made use of as comfort noise generator. b1?b0: channel 2 external setting background noise level table 21 channel 2 receive side background noise level setting rx_noise_lvl12 rx_noise_lvl02 level 0 0 no noise 0 1 ?55 dbm0 1 0 ?45 dbm0 1 1 ?35 dbm0
fedl7202-001-01 ML7202-001 47/65 (24) cr23 (reserved register) b7 b6 b5 b4 b3 b2 b1 b0 cr23 ? ? ? ? ? ? ? ? initial value 0 0 0 0 0 0 0 0 b7?b0: reserved bits (25) cr24 (reserved register) b7 b6 b5 b4 b3 b2 b1 b0 cr24 ? ? ? ? ? ? ? ? initial value 0 0 0 0 0 0 0 0 b7?b0: reserved bits (26) cr25 (channel 1 line echo canceler i/o level control) b7 b6 b5 b4 b3 b2 b1 b0 cr25 ? ? ? ? lpadl11 lpadl01 gpadl11 gpadl01 initial value 0 0 0 0 0 0 0 0 b7?b4: reserved bits b3?b2: line side input level control bits for setting the level of pad (lpadl1) for line echo canceler input sinl1 loss table 22 channel 1 loss pad level setting lpadl11 lpadl01 level 0 0 0 db 0 1 ?6 db 1 0 ?12 db 1 1 ?18 db b1?b0: line side output level control bits for setting the level of pad (gpadl1) for line echo canceler output soutl1 gain table 23 channel 1 gain pad level setting gpadl11 gpadl01 level 0 0 0 db 0 1 +6 db 1 0 +12 db 1 1 +18 db
fedl7202-001-01 ML7202-001 48/65 (27) cr26 (channel 2 line echo canceler i/o level control) b7 b6 b5 b4 b3 b2 b1 b0 cr26 ? ? ? ? lpadl12 lpadl02 gpadl12 gpadl02 initial value 0 0 0 0 0 0 0 0 b7?b4: reserved bit b3?b2: line side input level control bits for setting the level of pad (lpadl2) for line echo canceler input sinl2 loss table 24 channel 2 loss pad level setting lpadl12 lpadl02 level 0 0 0 db 0 1 ?6 db 1 0 ?12 db 1 1 ?18 db b1?b0: line side output level control bits for setting the level of pad (gpadl2) for line echo canceler output soutl2 gain table 25 channel 2 gain pad level setting gpadl12 gpadl02 level 0 0 0 db 0 1 +6 db 1 0 +12 db 1 1 +18 db
fedl7202-001-01 ML7202-001 49/65 (28) cr27 (channel 1 line echo canceler operation mode) b7 b6 b5 b4 b3 b2 b1 b0 cr27 lthr1 laff_ rst1 lhld1 lhd1 lclp1 ? latt1 lgc1 initial value 0 0 0 0 0 0 0 0 b7: through mode control 0: normal mode (echo cancellation operation) 1: through mode when this bit is set to ?0?, an echo ca nceler works. when this bit is set to ?1?, data of rinl1 and sinl1 are output to routel1 and soutl1 respectively as they are without echo cance llation. the echo canceler coefficients are kept frozen during through mode and not reset. b6: fir filter (laff) coefficients reset control 0: normal operation 1: rest of coefficients a bit to reset the adaptive fir filter (laff) coefficients of the line echo canceler. b5: coefficients updating control 0: normal mode (updates coeffi cients) 1: freezes coefficients when this bit is set to ?0?, the adaptive fir filter (laf f) keeps updating its own coefficients adaptively as per a state of the echo path between echo-originating signals at the routl1 and returning echo signals at the sinl1, which is normal operation with an echo canceler. when this bit is set to ?1?, the adap tive fir filter (laff) freezes its own coefficients and keeps echo cancellation operation with the frozen coefficients . hence, note that echo cancellation is not done if this bit is set to ?1? from the be ginning since the initial values of coefficients are all zero. this function is enabled when lthr1 is in normal mode. b4 howling director control 0: off 1: on this function detects and tries to suppress howling. th is function is enabled when lthr1 is in normal mode. b3: center clip control 0: off 1: on when the attsl1 output of the line echo canceler is ?57 dbm0 or less, the center clip function forcibly makes it mute by transforming the pcm codes to the minimum positive value (ffh in ? -law; b5h in a-law). this function is enabled when lthr1 is in normal mode. b2: reserved bit b1: attenuator control 0: on 1: off this bit is used to select on/off of the att function that complements echo attenuation which is by the adaptive fir filter and prevents howlin g with the attenuators (attsl1 and attrl1 ) that are provided for rinl1 input and soutl1 output of the line echo can celer. when signals are input to ri nl1 only, an attofsoutl1 (attsl1) is inserted. when signals are input to sinl1 only or both sinl1 and rinl1, an att of rinl1 input (attrl1) is inserted. each att value is about 6 db. this function is enabled when lthr1 is in normal mode. b0: gain controller control 0: off 1: on this bit is used to select on/off of the gain control function that controls the rinl1 input level and prevents howling and an excessive input to rinl1 which may bring decrease in echo attenuation through the gain controller that is provided for rinl1 input of the line echo canceler. this function becomes effective from about ?24 dbm0 as the rinl1 level and the rinl1 level is controlled within the range of 0 to ?8.5 db. this function is enabled when lthr1 is in normal mode.
fedl7202-001-01 ML7202-001 50/65 (29) cr28 (channel 2 line echo canceler operation mode) b7 b6 b5 b4 b3 b2 b1 b0 cr28 lthr2 laff_ rst2 lhld2 lhd2 lclp2 ? latt2 lgc2 initial value 0 0 0 0 0 0 0 0 b7: through mode control 0: normal mode (echo cancellation operation) 1: through mode when this bit is set to ?0?, an echo ca nceler works. when this bit is set to ?1?, data of rinl2 and sinl2 are output to routel2 and soutl2 respectively as they are without echo cance llation. the echo canceler coefficients are kept frozen during through mode and not reset. b6: fir filter (laff) coefficients reset control 0: normal operation 1: rest of coefficients a bit to reset the adaptive fir filter (laff) coefficients of the line echo canceler. b5: coefficients updating control 0: normal mode (coefficients updating) 1: fixed coefficients when this bit is set to ?0?, the adaptive fir filter (laf f) keeps updating its own coefficients adaptively as per a state of the echo path between echo-originating signals at the routl2 and returning echo signals at the sinl2, which is normal operation with an echo canceler. when this bit is set to ?1?, the adap tive fir filter (laff) freezes its own coefficients and keeps echo cancellation operation with the frozen coefficients . hence, note that echo cancellation is not done if this bit is set to ?1? from the be ginning since the initial values of coefficients are all zero this function is enabled when lthr2 is in normal mode. b4 howling director control 0: off 1: on this function detects and tries to suppress howling. th is function is enabled when lthr2 is in normal mode. b3: center clip control 0: off 1: on when the attsl2 output of the line echo canceler is ?57 dbm0 or less, the center clip function forcibly makes it mute by transforming the pcm codes to the minimum positive value (ffh in ? -law; b5h in a-law). this function is enabled when lthr2 is in normal mode. b2: reserved bit b1: attenuator control 0: on 1: off this bit is used to select on/off of the att function that complements echo attenuation which is by the adaptive fir filter and prevents howlin g with the attenuators (attsl2 and attrl2 ) that are provided for rinl2 input and soutl2 output of the line echo cancel er. when signals are input to rinl2 only, an att of soutl2 (attsl2) is inserted. when signals are input to sinl2 only or both sinl2 and rinl2, an att of rinl2 input (attrl2) is inserted. each att value is about 6 db. this function is enabled when lthr2 is in normal mode. b0: gain controller control 0: off 1: on this bit is used to select on/off of the gain control function that controls the rinl2 input level and prevents howling through the gain controller that is provided for rinl2 input of the line echo canceler. this function becomes effective from about ?24 dbm0 as the rinl2 level and the rinl2 level is controlled within the range of 0 to ?8.5 db. this function is enabled when lthr2 is in normal mode.
fedl7202-001-01 ML7202-001 51/65 (30) cr29 (reserved register) b7 b6 b5 b4 b3 b2 b1 b0 cr29 ? ? ? ? ? ? ? ? initial value 0 0 0 0 0 0 0 0 b7?b0: reserved bit (31) cr30 (reserved register) b7 b6 b5 b4 b3 b2 b1 b0 cr30 ? ? ? ? ? ? ? ? initial value 0 0 0 0 0 0 0 0 b7?b0: reserved bit (32) cr31 (reserved register) b7 b6 b5 b4 b3 b2 b1 b0 cr31 ? ? ? ? ? ? ? ? initial value 0 0 0 0 0 0 0 0 b7?b0: reserved bit
fedl7202-001-01 ML7202-001 52/65 microcontroller control method the following flowchart shows the mi crocontroller control method by th e parallel microcontroller interface. start cr6 (set high-order address) cr7 (set low-order address) cr8 (set high-order data) cr9 (set low-order data) set cr1-b7= ?1? set consecutively ye s no turn on the power supply power supply voltage (90% or more) set pdn/rst release pdn/rst cr4-b6=1? ( read ) ye s no execute internal data memory access ye s no set cr (other than cr0) set cr0 ye s no start normal operation internal data memory access initial mode cr1-b7="0" (read) ye s no *the content of cr1-b7 is cleared automatically after the internal memory is updated. cr4-b6="0"? (read) wait for about 200ms figure 8 flowchart of microcontroller control
fedl7202-001-01 ML7202-001 53/65 internal data memory access method write method the 8-bit registers (cr6?cr9) that were mapped in the control registers are assigned as follows. 16-bit address of the internal data memory a15?a0 16-bit write data d15?d0 the initial mode is entered about 200 ms after release of power-down reset by the pdn / rst pin or the spdn bit (cr0-b7) and the ready bit (cr4-b6) is set to ?1?. in this write enabled state and after the internal memory address and write data are set in cr6 to cr9, the internal data memory write operation for one word is completed by setting dmwr (cr1-b7) to ?1?. after completion of write operation, dmwr (cr1-b7) is cleared to ?0? automatically. figure 9 shows the internal data memory setting method. when rewriting multiple memories, repeat the write operatio n indicated above. operation starts when ope_stat (cr0-b0) is set to ?1? after termination of all the write operations. internal data memory can be rewritten in a mode other than the initial mode. in that case, use the same method as above for changing the contents of the internal data memory. tables 26 to 28 list internal data memory related registers. note: when data is set in the internal data memory during operation, data is read in the lsi internal section synchronized with the sync signal (8k hz). th erefore, retain the stat e for 250s or more. start end cr6 (set high-order address) cr7 (set low-order address) cr8 (set high-order data) cr9 (set low-order data) set cr1-b7 = ?1? set consecutively ye s no cr1-b7="0"? (read) ye s no *the content of cr1-b7 is cleared automatically after the internal memory is updated. figure 9 internal data memory access flowchart (write)
fedl7202-001-01 ML7202-001 54/65 internal data memory related registers table 26 internal data memory related control registers (page 1 of 3) initial value change enable mode function internal data memory name address data data value in initial mode when stopped in operation single tone frequency (tgen_freq_t0_1 / cr17:b4-b0=00000) 0000h 0e14h 440 hz yes no no single tone frequency (tgen_freq_t1_1 / cr17:b4-b0=00001) 0001h 0ee9h 466 hz yes no no single tone frequency (tgen_freq_t2_1 / cr17:b4-b0=00010) 0002h 0fcfh 494 hz yes no no single tone frequency (tgen_freq_t3_1 / cr17:b4-b0=00011) 0003h 10bch 523 hz yes no no single tone frequency (tgen_freq_t4_1 / cr17:b4-b0=00100) 0004h 11bah 554 hz yes no no single tone frequency (tgen_freq_t5_1 / cr17:b4-b0=00101) 0005h 12c9h 587 hz yes no no single tone frequency (tgen_freq_t6_1 / cr17:b4-b0=00110) 0006h 13e7h 622 hz yes no no single tone frequency (tgen_freq_t7_1 / cr17:b4-b0=00111) 0007h 1517h 659 hz yes no no single tone frequency (tgen_freq_t8_1 / cr17:b4-b0=01000) 0008h 1656h 698 hz yes no no single tone frequency (tgen_freq_t9_1 / cr17:b4-b0=01001) 0009h 17aeh 740 hz yes no no single tone frequency (tgen_freq_t10_1 / cr17:b4-b0=01010) 000ah 1917h 784 hz yes no no single tone frequency (tgen_freq_t11_1 / cr17:b4-b0=01011) 000bh 1a98h 831 hz yes no no single tone frequency (tgen_freq_t12_1 / cr17:b4-b0=01100) 000ch 1c29h 880 hz yes no no single tone frequency (tgen_freq_t13_1 / cr17:b4-b0=01101) 000dh 1dd3h 932 hz yes no no single tone frequency (tgen_freq_t14_1 / cr17:b4-b0=01110) 000eh 1f9eh 988 hz yes no no single tone frequency (tgen_freq_t15_1 / cr17:b4-b0=01111) 000fh 2181h 1047 hz yes no no single tone frequency (tgen_freq_t16_1 / cr17:b4-b0=10000) 0010h 237dh 1109 hz yes no no single tone frequency (tgen_freq_t17_1 / cr17:b4-b0=10001) 0011h 259ah 1175 hz yes no no single tone frequency (tgen_freq_t18_1 / cr17:b4-b0=10010) 0012h 27d7h 1245 hz yes no no single tone frequency (tgen_freq_t19_1 / cr17:b4-b0=10011) 0013h 2a35h 1319 hz yes no no single tone frequency (tgen_freq_t20_1 / cr17:b4-b0=10100) 0014h 2cb4h 1397 hz yes no no single tone frequency (tgen_freq_t21_1 / cr17:b4-b0=10101) 0015h 2f5ch 1480 hz yes no no single tone frequency (tgen_freq_t22_1 / cr17:b4-b0=10110) 0016h 322dh 1568 hz yes no no single tone frequency (tgen_freq_t23_1 / cr17:b4-b0=10111) 0017h 3527h 1661 hz yes no no single tone frequency (tgen_freq_t24_1 / cr17:b4-b0=11000) 0018h 3852h 1760 hz yes no no single tone frequency (tgen_freq_t25_1 / cr17:b4-b0=11001) 0019h 0ccdh 400 hz yes no no single tone frequency (tgen_freq_t26_1 / cr17:b4-b0=11010) 001ah 2000h 1000 hz yes no no single tone frequency (tgen_freq_t27_1 / cr17:b4-b0=11011) 001bh 4000h 2000 hz yes no no single tone frequency (tgen_freq_t28_1 / cr17:b4-b0=11100) 001ch 5558h 2667 hz yes no no tone_gen1 single tone frequency (tgen_freq_t29_1 / cr17:b4-b0=11101) 001dh 299ah 1300 hz yes no no
fedl7202-001-01 ML7202-001 55/65 table 27 internal data memory related control registers (page 2 of 3) initial value change enable mode function internal data memory name address data data value in initial mode when stopped in operation single tone frequency (tgen_freq_t30_1 / cr17:b4-b0=11110) 001eh 428fh 2080 hz yes no no single tone frequency (tgen_freq_t31_1 / cr17:b4-b0=11111) 001fh 6000h 3000 hz yes no no tone output gain (tgen_gain_h1) 0020h 0100h 0 db yes yes no tone output gain (tgen_gain_l1) 0021h 0100h 0 db yes yes no fade control (tgen_fade_cont1) 0022h 0000h stop yes yes no fade in step (tgen_fade_in_st1) 0023h 4c10h +1.5 db yes yes no fade out step (tgen_fade_out_st1) 0024h 35d9h ?1.5 db yes yes no tone_gen1 tone fade out time (tgen_fade_out_tim1) 0025h 0021h 33sync yes yes no single tone frequency (tgen_freq_t0_2 / cr19:b4-b0=00000) 0030h 0e14h 440 hz yes no no single tone frequency (tgen_freq_t1_2 / cr19:b4-b0=00001) 0031h 0ee9h 466 hz yes no no single tone frequency (tgen_freq_t2_2 / cr19:b4-b0=00010) 0032h 0fcfh 494 hz yes no no single tone frequency (tgen_freq_t3_2 / cr19:b4-b0=00011) 0033h 10bch 523 hz yes no no single tone frequency (tgen_freq_t4_2 / cr19:b4-b0=00100) 0034h 11bah 554 hz yes no no single tone frequency (tgen_freq_t5_2 / cr19:b4-b0=00101) 0035h 12c9h 587 hz yes no no single tone frequency (tgen_freq_t6_2 / cr19:b4-b0=00110) 0036h 13e7h 622 hz yes no no single tone frequency (tgen_freq_t7_2 / cr19:b4-b0=00111) 0037h 1517h 659 hz yes no no single tone frequency (tgen_freq_t8_2 / cr19:b4-b0=01000) 0038h 1656h 698 hz yes no no single tone frequency (tgen_freq_t9_2 / cr19:b4-b0=01001) 0039h 17aeh 740 hz yes no no single tone frequency (tgen_freq_t10_2 / cr19:b4-b0=01010) 003ah 1917h 784 hz yes no no single tone frequency (tgen_freq_t11_2 / cr19:b4-b0=01011) 003bh 1a98h 831 hz yes no no single tone frequency (tgen_freq_t12_2 / cr19:b4-b0=01100) 003ch 1c29h 880 hz yes no no single tone frequency (tgen_freq_t13_2 / cr19:b4-b0=01101) 003dh 1dd3h 932 hz yes no no single tone frequency (tgen_freq_t14_2 / cr19:b4-b0=01110) 003eh 1f9eh 988 hz yes no no single tone frequency (tgen_freq_t15_2 / cr19:b4-b0=01111) 003fh 2181h 1047 hz yes no no single tone frequency (tgen_freq_t16_2 / cr19:b4-b0=10000) 0040h 237dh 1109 hz yes no no single tone frequency (tgen_freq_t17_2 / cr19:b4-b0=10001) 0041h 259ah 1175 hz yes no no single tone frequency (tgen_freq_t18_2 / cr19:b4-b0=10010) 0042h 27d7h 1245 hz yes no no single tone frequency (tgen_freq_t19_2 / cr19:b4-b0=10011) 0043h 2a35h 1319 hz yes no no single tone frequency (tgen_freq_t20_2 / cr19:b4-b0=10100) 0044h 2cb4h 1397 hz yes no no tone_gen2 single tone frequency (tgen_freq_t21_2 / cr19:b4-b0=10101) 0045h 2f5ch 1480 hz yes no no
fedl7202-001-01 ML7202-001 56/65 table 28 internal data memory related control registers (page 3 of 3) initial value change enable mode function internal data memory name address data data value in initial mode when stopped in operation single tone frequency (tgen_freq_t22_2 / cr19:b4-b0=10110) 0046h 322dh 1568 hz yes no no single tone frequency (tgen_freq_t23_2 / cr19:b4-b0=10111) 0047h 3527h 1661 hz yes no no single tone frequency (tgen_freq_t24_2 / cr19:b4-b0=11000) 0048h 3852h 1760 hz yes no no single tone frequency (tgen_freq_t25_2 / cr19:b4-b0=11001) 0049h 0ccdh 400 hz yes no no single tone frequency (tgen_freq_t26_2 / cr19:b4-b0=11010) 004ah 2000h 1000 hz yes no no single tone frequency (tgen_freq_t27_2 / cr19:b4-b0=11011) 004bh 4000h 2000 hz yes no no single tone frequency (tgen_freq_t28_2 / cr19:b4-b0=11100) 004ch 5558h 2667 hz yes no no single tone frequency (tgen_freq_t29_2 / cr19:b4-b0=11101) 004dh 299ah 1300 hz yes no no single tone frequency (tgen_freq_t30_2 / cr19:b4-b0=11110) 004eh 428fh 2080 hz yes no no single tone frequency (tgen_freq_t31_2 / cr19:b4-b0=11111) 004fh 6000h 3000 hz yes no no tone output gain (tgen_gain_h2) 0050h 0100h 0 db yes yes no tone output gain (tgen_gain_l2) 0051h 0100h 0 db yes yes no fade control (tgen_fade_cont2) 0052h 0000h stop yes yes no fade in step (tgen_fade_in_st2) 0053h 4c10h +1.5 db yes yes no fade out step (tgen_fade_out_st2) 0054h 35d9h ?1.5 db yes yes no tone_gen2 tone fade out time (tgen_fade_out_tim2) 0055h 0021h 33sync yes yes no tone detection threshold (main signal) (tdet_s_th1) 0084h 1ebbh ?5.3 dbm0 yes yes no tone detection threshold (noise) (tdet_n_th1) 0099h 1ebbh ?5.3 dbm0 yes yes no on guard timer (tdet_on_tim1) 009ah 0028h 5 ms yes yes no off guard timer (tdet_off_tim1) 009bh 0028h 5 ms yes yes no tdet1 detection frequency (tdet_freq1) ----h ? 2100 hz yes ? no tone detection threshold (main signal) (tdet_s_th2) 00b4h 1ebbh ?5.3 dbm0 yes yes no tone detection threshold (noise) (tdet_n_th2) 00c9h 1ebbh ?5.3 dbm0 yes yes no on guard timer (tdet_on_tim2) 00cah 0028h 5 ms yes yes no off guard timer (tdet_off_tim2) 00cbh 0028h 5 ms yes yes no tdet2 detection frequency (tdet_freq2) ----h ? 2100 hz yes no no vox1 voice/silence detection threshold adjusting pad (vox_lpad1) 0061h 4000h 0 db yes no no vox2 voice/silence detection threshold adjusting pad (vox_lpad2) 0069h 4000h 0 db yes no no
fedl7202-001-01 ML7202-001 57/65 tone generator function a. single tone frequency internal data memory address: 0000h to 001fh address: 0030h to 004fh use the following expression when changing the tone frequency. calculation expression: a 8.192 (where a is the desired frequency after change) when the desired frequency is 2100 hz: 2100 8.192 = 17203.2 = 17203d = 4333h (round off to the nearest whole number) upper limit value: 3000 hz (data: 6000h) lower limit value: 30 0 hz (data: 099ah) b. internal data memory for tone output gain control address: 0020h, initial value: 0100h (0 db) address: 0021h, initial value: 0100h (0 db) address: 0050h, initial value: 0100h (0 db) address: 0051h, initial value: 0100h (0 db) the default of the output gain is 0 db. use the following expression to change the output gain (x). calculation expression: 10^(x/20) 256 setting the gain to ?6 db 10^(?6/20) 256 = 128.3d = 128d = 0080h (round off to the nearest whole number) upper limit value: +12 db (data: 03fbh) lower limit value: ?12 db (data: 0040h) note: if the setting has been so made that tgen_gain_h1, tgen_gain_l1, tgen_gain_h2, or tgen_gain_l2 individually or th e result of adding them exceeds +3 dbm0, the tone will be saturated regardless of the setting of atttgtxt1, atttgrx1, atttgtx2, and attgrx2 of the succeeding stage, and as a result, the related ac char acteristics specified in this sp ecification are not satisified. c. internal data memory for tone fade control address: 0022h, initial value: 0000h (stop) address: 0052h, initial value: 0000h (stop) setting ?0001h? in this data memory enables the fa de in/fade out function of tone fade control. 0000h: disable fade in/fade out 0001h: enable fade in/fade out note: when using this control, set a correct fade out time. d. fade in step address: 0023h, initial value: 4c10h (+1.5 db) address: 0053h, initial value: 4c10h (+1.5 db) use the following expressing to change step amount x. calculation expression: 10^(x/20) 16384 setting the step value to +1.5 db 10^(1.5/20) 16384=19472.42=19472d=4c10h (round off to the nearest whole number) maximum step value: approx. +6.0 db (data: 7fffh) minimum step value: approx. +0.1 db (data: 40beh)
fedl7202-001-01 ML7202-001 58/65 e. fade out step address: 0024h, initial value: 35d9h (?1.5 db) address: 0054h, initial value: 35d9h (?1.5 db) use the following expression to change step amount x. calculation expression: 10^(x/20) 16384 setting the step value to ?1.5 db 10^(?1.5/20) 16384 = 13785.41 = 13785d = 35d9h (round off to the nearest whole number) maximum step value: approx. ?6.0 db (data: 2000h) minimum step value: approx. ?0.1 db (data: 3f44h) f. internal data memory for tone fade out time control address: 0025h, initial value: 002bh (33sync) address: 0055h, initial value: 002bh (33sync) use the following expression to change the fade out time. calculation expression: 48.2 db/ ?fade out step value? db when the step value is 1.5 db: 48.2/1.5 = 32.13 = 33d = 0021h (round up to the nearest whole number) upper limit value: 482 sync (data: 01e2h) lower limit: 9 sync (data: 0009h) tone detection function a. internal data memory for detection threshold (main signal) control address: 0084h, initial value: 1ebbh (?5.3 dbm0) address: 00b4h, initial value: 1ebbh (?5.3 dbm0) use the following expression to change the value when using x as the main signal detection threshold. calculation expression: 10^((x ? 3.17)/20) 2/pi 32768 when detection threshold = ?5.3 dbm0 10^((?5.3 ? 3.17)/20) 2/pi 32768 = 7867.37d = 1ebbh (round off to the nearest whole number) upper limit value: ?5.3 dbm0 (data: 1ebbh) lower limit value: ?30 dbm0 (data: 01cah) b. internal data memory for detection threshold (noise) control address: 0099h, initial value: 1ebbh (?5.3 dbm0) address: 00c9h, initial value: 1ebbh (?5.3 dbm0) use the following expression to change the value when using x as the main signal detection threshold. calculation expression: 10^((x?3.17)/20) 2/pi 32768 when detection threshold = ?5.3 dbm0 10^((?5.3 ? 3.17)/20) 2/pi 32768 = 7867.37d = 1ebbh (round off to the nearest whole number) upper limit value: ?5.3 dbm0 (data: 1ebbh) lower limit value: ?30 dbm0 (data: 01cah) to stop the noise detection function, write 7fffh in the internal data memory (tdet_n_th1/tdet_n_th2) that is indicated above.
fedl7202-001-01 ML7202-001 59/65 c. internal data memory for on guard timer address: 009ah, initial value: 0028h (5 ms) address: 00cah, initial value: 0028h (5 ms) use the following expression to change the timer value. calculation expression: guard timer value (ms)/0.125(ms) on guard timer = 5 ms 5/0.125 = 40d = 0028h upper limit value: 4095.875 ms (data: 7fffh) lower limit value: 0.125 ms (data: 0001h) d. internal data memory for off guard timer address: 009bh, initial value: 0028h (5 ms) address: 00cbh, initial value: 0028h (5 ms) use the following expression to change the timer value. calculation expression: guard timer value (ms)/0.125(ms) on guard timer = 5 ms 5/0.125 = 40d = 0028h upper limit value: 4095.875 ms (data: 7fffh) lower limit value: 0.125 ms (data: 0001h) e. internal data memory for detection frequency control address:----h, initial value: D address:----h, initial value: D this function is used for changing a detection frequency. contact rohm's responsible sales person when changing the detection frequency. vox function a. voice/silence detection threshold adjusting pad (for loss) address: 0061h, initial value: 4000h (0 db) address: 0069h, initial value: 4000h (0 db) use the following expression to change the voice/silence detection threshold adjusting value calculation expression: 10^(?x/20) 16384 setting the voice/silence detection threshold adjusting value to ?1 db 10^(?(?1.0)/20) 16384 = 18383.15 = 18383d = 47cfh (round off to the nearest whole number) upper limit value: ?1.0 db (data: 47cfh) lower limit value: ?5.0 db (data: 71cfh)
fedl7202-001-01 ML7202-001 60/65 data communication set the following parameters for data communication. 1. 4-bit (32 kbps) data communication dthr1 (cr2-b5) = ?1? :channel 1 dthr2 (cr3-b5) = ?1? :channel 2 2. 8-bit (64 kbps) data communication conta1 (cr2-b7) = ?1?, lthr1 (cr27-b7) = ?1? :channel 1 conta2 (cr3-b7) = ?1?, lthr2 (cr28-b7) = ?1? :channel 2 notes: 1. at the start and switching of data/voice communication, a data loss/data errors of several sync cycles occur. 2. in data through of lthr1/2 only, pcm data ??0? is changed to ?+0? when it is output. 3. dthr1 = ?1?, dthr2 = ?1?, conta1 = ?1?+lthr1 = ?1?, and conta2 = ?1?+lthr2 = ?1? are set, the line echo canceler, tone generator, tone detection, vox function, and mute function are disabled. table 29 full scale table ( ? -law, a-law) ? ? -law a-law input level msb msb + full scale 1 0 0 000001010 1 0 10 +0 1 1 1 111111101 0 1 01 ?0 0 1 1 111110101 0 1 01 ? full scale 0 0 0 000000010 1 0 10
fedl7202-001-01 ML7202-001 61/65 notes on use 1. to prevent operation errors and deterioration of the characteristics of the lsi, use a stable power supply of low noise (in particular high-frequency spark noise or pulse noise). 2. to guarantee the electrical characteristics, use a pow er supply byass capacitor with better high frequency characteristics and install it in the proximity of the lsi pins. 3. to guarantee the electrical charact eristics, use an analog signal ground (sg pin) bypass capacitor with better high frequency characteristics and install it in the proximity of the lsi pins. 4. to guarantee the electrical charact eristics, use a bypass capacitor with a better high frequency characteristics for regulator reference voltage output (vbg pin) and regulator output (vout1 and vout2 pins), and install it in the proximity of the lsi pins. 5. connect the agnd, dgnd1, and dgnd2 pins with the system ground as close as possible under low impedance. 6. turn on the analog power supply and digital power supply simulatneously or digital power supply prior to analog power supply. 7. after turning on the power supply, execute reset using the pdn/rst pin immediately, with the master clock being input without fail. (for instance, when this ls i is maintained in a power-down state while the device waits for originating call or terminating call, first ex ecute the reset described above and then wait for the originating call or terminating call.) 8. pcm output pins and adpcm output pins require an external pull-up resistor since they are open drain pins. 9. make the setting of the e.r.l (echo return loss) so that it will be attenuated. if the e.r.l is to be amplified, it is recommended to use the function of the loss pad and gain pad that are provided in the i/o section of the line echo canceler. e.r.l refers to attenuation of echo amount from an echo canceler output (routl1/routl2) to an echo canceler input (sinl1/sinl2). 10. the recommended input level to the lin e echo canceler is ?10 to ?20 dbm0.
fedl7202-001-01 ML7202-001 62/65 application circuit ml7202 d0 d2 d3 d4 w r a gnd d1 dgnd1 r d c s p dn/rst synca vox1o vox1i sg a vdd tsti6 tsti7 is1 ir1 tsti8 tsti9 tsti0 i nt vout2 dvdd2 pcm1lni pcm1lno pcm2aci pcm1aco pcm1adi pcm2ado syncl bclkl dgnd2 a 1 vout1 dvdd1 vbg a 4 a 3 a 2 a 0 mtype is2 ir2 vox2o vox2i pcm1ado pcm2aco pcm2lno pcm2lni pcm1aci pcm2adi d5 d6 d7 bclka mck 10 ? f 0.1 ? f 0.1 ? f 10 ? f +3.3v(va) 10 ? f 0.1 ? f 10 ? f 150pf 0.1 ? f 0.1 ? f 10 ? f +3.3v(vd) +3.3v(vd) +3.3v(vd) reset master clock input (19.2mhz) bit clock input (128khz to 2.048mhz) 8khz synchronous signal input reception side adpcm signal input transmission side adpcm signal input microcontroller interface bit clock input (128khz to 2.048mhz) 8khz synchronous signal input reception side pcm signal input transmission side pcm signal output channel 1 reception side vox input channel 1 transmission side vox output channel 2 reception side vox input channel 2 transmission side vox output (floating) (floating) (floating) (floating) 500 ? 500 ? tsti1 tsti2 tsti3 tsti4 tsti5 +3.3v(vd) 10 ? f 0.1 ? f +3.3v(vd) 10k ? setting conditions ? iosel setting: cr0-b3 = ?0? ? when pcm time slot is assigned (setup control registers: cr11 and cr12) ? when adpcm time slot is assigned (setup control registers: cr13 and cr14) note ? the bit clock frequency varies according to the pcm-adpcm time slot assignment conditions.
fedl7202-001-01 ML7202-001 63/65 package dimensions tqfp64-p-1010-0.50-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5 m) package weight (g) 0.26 typ. 5 rev. no./last revised 4/oct. 28, 1996 notes for mounting the su rface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humi dity absorbed in storage. therefore, before you perform reflow mounting, contact rohm's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (unit: mm)
fedl7202-001-01 ML7202-001 64/65 revision history page document no. date previous edition current edition description fedl7202-001-01 sep. 08 2004 ? 65 final edition 1
fedl7202-001-01 ML7202-001 65/65 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, pleas e be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants an d any other information contained herein illustrate the standard usage and operations of the products. the peri pheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the info rmation specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended on ly to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatso ever for any dispute arising from the use of such technical information. the products specified in this docu ment are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe design s. lapis semiconductor shall bear no responsibility whatsoever for your use of any produc t outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malf unction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety devi ce). lapis semiconductor shall bear no responsibility in any way for use of any of the prod ucts for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you w ill be required to obtain a license or permit under the law. copyright 2011 lapis semiconductor co., ltd.

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