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integrated circuit systems, inc. ics97u877 0792a?04/15/04 block diagram 1.8v wide range frequency clock driver pin configuration 40-pin mlf recommended application: ddr2 memory modules / zero delay board fan out provides complete ddr dimm logic solution with icssstu32864 product description/features: low skew, low jitter pll clock driver 1 to 10 differential clock distribution (sstl_18) feedback pins for input to output synchronization spread spectrum tolerant inputs auto pd when input signal is at a certain logic state switching characteristics: period jitter: 40ps half-period jitter: 60ps cycle - cycle jitter 40ps output - output skew: 40ps a b 123456 c d e f g h j k vddq clkc2 clkt2 clk_int clk_inc vddq agnd avdd vddq gnd clkc7 clkt7 vddq fb_int fb_inc fb_outc fb_outt vddq oe os clkt3 clkc3 clkc4 clkt4 vddq clkt9 clkc9 clkc8 clkt8 vddq clkc1 clkt1 clkt0 clkc0 vddq clkc5 clkt5 clkt6 clkc6 vddq 1 10 11 20 21 31 30 40 ics97u877 52-ball bga top view clkt0 clkc0 clkt1 clkc1 clkt2 clkc2 clkt3 clkc3 clkt4 clkc4 clkt5 clkc5 clkt6 clkc6 clkt7 clkc7 clkt8 clkc8 clkt9 clkc9 fb_outt fb_outc av dd fb_int clk_int clk_inc fb_inc pll powerdown control and test logic oe ld* or oe pll bypass ld* ld*, os or o e os gnd 10k-100 k * the logic detect (ld) powers down the device when a logic low is applied to both clk_int and clk_inc. 12345 6 a clkt1 clkt0 clkc0 clkc5 clkt5 clkt6 b clkc1 gnd gnd gnd gnd clkc6 c clkc2 gnd nb nb gnd clkc7 d clkt2 vddq vddq vddq os clkt7 e clk_int vddq nb nb vddq fb_int f clk_inc vddq nb nb oe fb_inc g agnd vddq vddq vddq vddq fb_outc h avdd gnd nb nb gnd fb_outt j clkt3 gnd gnd gnd gnd clkt8 k clkc3 clkc4 clkt4 clkt9 clkc9 clkc8
2 ics97u877 0792a?04/15/04 pin descriptions l a n i m r e t e m a n n o i t p i r c s e d l a c i r t c e l e s c i t s i r e t c a r a h c d n g ad n u o r g g o l a n a d n u o r g v a d d r e w o p g o l a n a l a n i m o n v 8 . 1 t n i _ k l cr o t s i s e r n w o d l l u p ) m h o k 0 0 1 - k 0 1 ( a h t i w t u p n i k c o l c t u p n i l a i t n e r e f f i d c n i _ k l c r o t s i s e r n w o d l l u p ) m h o k 0 0 1 - k 0 1 ( a h t i w t u p n i k c o l c y r a t n e l p m o c t u p n i l a i t n e r e f f i d t n i _ b ft u p n i k c o l c k c a b d e e f t u p n i l a i t n e r e f f i d c n i _ b ft u p n i k c o l c k c a b d e e f y r a t n e m e l p m o c t u p n i l a i t n e r e f f i d t t u o _ b ft u p t u o k c o l c k c a b d e e f t u p t u o l a i t n e r e f f i d c t u o _ b ft u p t u o k c o l c k c a b d e e f y r a t n e m e l p m o c t u p t u o l a i t n e r e f f i d e o) s u o n o r h c n y s a ( e l b a n e t u p t u o t u p n i s o m c v l s ov r o d n g o t d e i t ( t c e l e s t u p t u o q d d )t u p n i s o m c v l d n gd n u o r g d n u o r g v q d d r e w o p t u p t u o d n a c i g o l l a n i m o n v 8 . 1 ] 9 : 0 [ t k l cs t u p t u o k c o l c s t u p t u o l a i t n e r e f f i d ] 9 : 0 [ c k l cs t u p t u o k c o l c y r a t n e m e l p m o c s t u p t u o l a i t n e r e f f i d b nl l a b o n the pll clock buffer, ics97u877 , is designed for a v ddq of 1.8 v, a av dd of 1.8 v and differential data input and output levels. package options include a plastic 52-ball vfbga and a 40-pin mlf. ics97u877 is a zero delay buffer that distributes a differential clock input pair (clk_int, clk_inc) to ten differential pair of clock outputs (clkt[0:9], clkc[0:9]) and one differential pair feedback clock outputs (fb_outt, fboutc). the clock outputs are controlled by the input clocks (clk_int, clk_inc), the feedback clocks (fb_int, fb_inc), the lvcmos program pins (oe, os) and the analog power input (avdd). when oe is low, the outputs (except fb_outt/ fb_outc) are disabled while the internal pll continues to maintain its locked-in frequency. os (output select) is a program pin that must be tied to gnd or v ddq . when os is high, oe will function as described above. when os is low, oe has no effect on clkt7/clkc7 (they are free running in addition to fb_outt/fb_outc). when av dd is grounded, the pll is turned off and bypassed for test purposes. when both clock signals (clk_int, clk_inc) are logic low, the device will enter a low power mode. an input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the pll are off. when the inputs transition from both being logic low to being differential signals, the pll will be turned back on, the inputs and outputs will be enabled and the pll will obtain phase lock between the feedback clock pair (fb_int, fb_inc) and the input clock pair (clk_int, clk_inc) within the specified stabilization time t stab . the pll in ics97u877 clock driver uses the input clocks (clk_int, clk_inc) and the feedback clocks (fb_int, fb_inc) to provide high-performance, low-skew, low-jitter output differential clocks (clkt[0:9], clkc[0:9]). ics97u877 is also able to track spread spectrum clocking (ssc) for reduced emi. ics97u877 is characterized for operation from 0c to 70c.
3 ics97u877 0792a?04/15/04 function table s t u p n is t u p t u o l l p d d v ae os ot n i _ k l ct n i _ k l ct k l cc k l ct t u o _ b fc t u o _ b f d n ghxl h l h l h f f o / d e s s a p y b d n ghxh l h l h l f f o / d e s s a p y b d n glhl h ) z ( l *) z ( l *lh f f o / d e s s a p y b d n gllh l , ) z ( l * 7 t k l c e v i t c a , ) z ( l * 7 c k l c e v i t c a h lf f o / d e s s a p y b ) m o n ( v 8 . 1lhlh ) z ( l *) z ( l *lh n o ) m o n ( v 8 . 1llhl , ) z ( l * 7 t k l c e v i t c a , ) z ( l * 7 c k l c e v i t c a hl n o ) m o n ( v 8 . 1hxlhlhlh n o ) m o n ( v 8 . 1hxhlhlhl n o ) m o n ( v 8 . 1xxll ) z ( l *) z ( l *) z ( l *) z ( l *f f o ) m o n ( v 8 . 1xxhh d e v r e s e r *l(z) means the outputs are disabled to a low stated meeting the i odl limit.
4 ics97u877 0792a?04/15/04 absolute maximum ratings supply voltage (vddq & avdd) . . . . . . . . . -0.5v to 2.5v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.5v to v ddq + 0.5v ambient operating temperature . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . -65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input /supply/common output parameters ta = 0 - 70c; supply voltage avddq, vddq = 1.8 v +/- 0.1v (unless otherwise stated) parameter symbol conditions min typ max units input high current ( clk_int, clk_inc ) i ih v i = v ddq or gnd 250 a input low current (oe, os, fb_int, fb_inc ) i il v i = v ddq or gnd 10 a output disabled low current i odl oe = l, v odl = 100mv 100 a i dd1.8 c l = 0pf @ 270mhz 300 ma i ddld c l = 0pf 500 a input clamp voltage v ik v ddq = 1.7v iin = -18ma -1.2 v i oh = -100
5 ics97u877 0792a?04/15/04 notes: 1. unused inputs must be held high or low to prevent them from floating. 2. dc input signal voltage specifies the allowable dc execution of differential input. 3. differential inputs signal voltages specifies the differential voltage [vtr-vcp] required for switching, where vtr is the true input level and vcp is the complementary input level. 4. differential cross-point voltage is expected to track variations of v ddq and is the voltage at which the differential signal must be crossing. recommended operating condition (see note1) t a = 0 - 70c; supply voltage avdd, vddq = 1.8 v +/- 0.1v (unless otherwise stated) parameter symbol conditions min typ max units supply voltage v ddq , a vdd 1.7 1.8 1.9 v clk_int, clk_inc, fb_inc, fb_int 0.35 x v ddq v oe, os 0.35 x v ddq v clk_int, clk_inc, fb_inc, fb_int 0.65 x v ddq v oe, os 0.65 x v ddq v dc input signal voltage (note 2 ) v in -0.3 v ddq + 0.3 v dc - clk_int, clk_inc, fb_inc, fb_int 0.3 v ddq + 0.4 v ac - clk_int, clk_inc, fb_inc, fb_int 0.6 v ddq + 0.4 v output differential cross- volta g e ( note 4 ) v ox v ddq /2 - 0.10 v ddq /2 + 0.10 v input differential cross- volta g e ( note 4 ) v ix v ddq /2 - 0.15 v dd /2 v ddq 2 + 0.15 v high level output current i oh -9 ma low level output current i ol 9ma operating free-air tem p erature t a 070c differential input signal voltage (note 3) v id low level input voltage v il high level input voltage v ih
6 ics97u877 0792a?04/15/04 notes: 1. switching characteristics guaranteed for application frequency range. 2. static phase offset shifted by design. timing requirements t a = 0 - 70c supply voltage avdd, vddq = 1.8 v +/- 0.1v (unless otherwise stated) parameter symbol conditions min max units max clock frequency freq op 1.8v+ 0.1v @ 25c 95 370 mhz application frequency range freq app 1.8v+ 0.1v @ 25c 160 350 mhz input clock duty cycle d tin 40 60 % clk stabilization t stab 15 s switching characteristics 1 t a = 0 - 70c supply voltage avdd, vddq = 1.8 v +/- 0.1v (unless otherwise stated) parameter symbol condition min typ max units output enable time t en oe to any output 4.73 8 ns output disable time t dis oe to any output 5.82 8 ns period jitter t j it (p er ) -30 30 ps half-period jitter t j it ( h p er ) -60 60 ps in p ut clock 1 2.5 4 v/ns out p ut enable ( oe ) , ( os ) 0.5 v/ns out p ut clock slew rate slr1 ( o ) 1.5 2.5 3 v/ns t j it ( cc+ ) 040ps t j it ( cc- ) 0 -40 ps dynamic phase offset t ( ) d y n -20 20 ps static phase offset t spo 2 -50 0 50 ps output to output skew t skew 40 ps ssc modulation fre q uenc y 30.00 33 khz ssc clock input frequency deviation 0.00 -0.50 % pll loop bandwidth (-3 db from unit y g ain ) 2.0 mhz cycle-to-cycle period jitter input slew rate slr1(i)
7 ics97u877 0792a?04/15/04 gnd ics97u877 v dd v (clkc) v (clkc) scope c=10p f -vdd/2 gnd - gnd vdd/2 z=6 z = 2.97" z = 120 ? z = 2.97" 0 ? z=60 ? z=50 ? z=50 ? r=10 ? r=10 ? v (tt) v (tt) c=10pf note: v tt = gnd t c(n) t c(n+1) t jit(cc) =t c(n) t c(n+1) figure 1. ibis model output load figure 2. output load test circuit y , fb_outc x y , fb_outt x parameter measurement information ics97u877 figure 3. cycle-to-cycle jitter r = 1m ? c = 1 pf r = 1m ? c = 1 pf
8 ics97u877 0792a?04/15/04 (n is a large number of samples) t ( ) n+1 t ()n t () = 1 n= n t ()n n clk_inc clk_int fb_inc fb_int t (skew) y # x y , fb_outc x y , fb_outt x y , fb_outc x y , fb_outt x y , fb_outc x y , fb_outt x y x parameter measurement information figure 4. static phase offset figure 5. output skew 1 f o t = t - (jit_per) t c(n) c(n) 1 f o figure 6. period jitter
9 ics97u877 0792a?04/15/04 clock inputs and outputs 80% 20% 80% 20% t slr t slf v id ,v od figure 8. input and output slew rates parameter measurement information t jit(hper_n) t jit(hper_n+1) 1 f o y , fb_outc x y , fb_outt x figure 7. half-period jitter t jit(hper) t jit(hper_n) 1 2xf o =-
10 ics97u877 0792a?04/15/04 figure 9. dynamic phase offset figure 10. time delay between oe and clock output (y, y) t ( ) t ( ) fbin fbi n ck ck t ( )dyn t ( )dyn t ( )dyn t ( )dyn ssc of f ssc on ssc on ssc off 5 0 % vddq t en t dis oe oe y/ y y 50 % vddq y y y 5 0 % vddq 50 % vd dq
11 ics97u877 0792a?04/15/04 figure 11. av dd filtering - place the 2200pf capacitor close to the pll. - use a wide trace for the pll analog power & ground. connect pll & caps to agnd trace & connect trace to one gnd via (farthest from pll). - recommended bead: fair-rite p/n 2506036017y0 or equivalent (0.8 ohm dc max, 600 ohms @ 100 mhz).
12 ics97u877 0792a?04/15/04 ordering information 97u877 y hlf-t - e - typ b ref b ref alpha designations for vertical grid (letters i, o, q & s not used) alpha designations for vertical grid (letters i, o, q & s not used) numeric designations for horizontal grid numeric designations for horizontal grid h typ h typ c ref c ref a b c d top view a1 3 2 1 4 seating plane seating plane c t 0.12 c d typ e d d1 d1 d1d1d1 - e -- e - - e - e1 typ typ d e t e horiz vert total d h d1 e1 b c min/max min/max min/max 7.00 bsc 4.50 bsc 0.86/1.00 0.65 bsc 6 10 60 0.35/0.45 0.15/0.21 5.85 bsc 3.25 bsc 0.575 0.625 ** * source ref.: jedec publication 95, 10-0055 all dimensions in millimeters ref. dimensions ----- ball grid ----- max. note: ball g rid total indicates maximum ball count for p acka g e. lesser q uantit y ma y be used. mo-205*, mo-225** example: designation for tape and reel packaging lead free (optional) package type h = bga revision designator (will not correlate with datasheet revision) device type xxxx y h lf- t
13 ics97u877 0792a?04/15/04 ordering information 97u877 yklf-t example: designation for tape and reel packaging lead free (optional) package type k = mlf revision designator (will not correlate with datasheet revision) device type xxxx y k lf- t to p vi e w index area 1 e d sawn singulation anvil singulation o r a 0.08 c c a3 a1 seating p lane e2 e2 2 l (n -1)x e (ref.) d (ref.) n&n even d e n e d2 2 d2 d e (ref.) n&n odd 1 2 e 2 (typ.) if n & n are even (n -1)x e (ref.) e e d b thermal base 2 n all dimensions in millimeters n symbol min. max. n d a 0.80 1.00 n e a1 0 0.05 d x e basic a3 d2 min. / max. b 0.18 0.30 e2 min. / max. e l min. / max. special non-jedec all dim. same except as below: 4.35 / 4.65 5.05 / 5.35 10-0053 source reference: mlf2? se r thermally enhanced, very thin, fine pitch quad flat / no lead plastic package 0.30 / 0.50 d2 min. / max. e2 min. / max. 0.25 reference 0.50 basic 6.00 x 6.00 2.75 / 3.05 2.75 / 3.05 40 10 10

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