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cyclone v device overview 2013.12.26 cv-51001 subscribe send feedback the cyclone ? v devices are designed to simultaneously accommodate the shrinking power consumption, cost, and time-to-market requirements; and the increasing bandwidth requirements for high-volume and cost-sensitive applications. enhanced with integrated transceivers and hard memory controllers, the cyclone v devices are suitable for applications in the industrial, wireless and wireline, military, and automotive markets. related information cyclone v device handbook: known issues lists the planned updates to the cyclone v device handbook chapters. key advantages of cyclone v devices table 1: key advantages of the cyclone v device family supporting feature advantage ? built on tsmc's 28 nm low-power (28lp) process technology and includes an abundance of hard intellectual property (ip) blocks ? up to 40% lower power consumption than the previous generation device lower power consumption ? 8-input adaptive logic module (alm) ? up to 13.59 megabits (mb) of embedded memory ? variable-precision digital signal processing (dsp) blocks improved logic integration and differentiation capabilities ? 3.125 gigabits per second (gbps) and 6.144 gbps transceivers ? hard memory controllers increased bandwidth capacity ? tight integration of a dual-core arm cortex-a9 mpcore processor, hard ip, and an fpga in a single cyclone v system- on-a-chip (soc) ? supports over 128 gbps peak bandwidth with integrated data coherency between the processor and the fpga fabric hard processor system (hps) with integrated arm ? cortex ? -a9 mpcore processor iso 9001:2008 registered ? 2013 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera corporation and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 innovation drive, san jose, ca 95134
supporting feature advantage ? requires only two core voltages to operate ? available in low-cost wirebond packaging ? includes innovative features such as configuration via protocol (cvp) and partial reconfiguration lowest system cost summary of cyclone v features table 2: summary of features for cyclone v devices description feature ? tsmc's 28-nm low-power (28lp) process technology ? 1.1 v core voltage technology ? wirebond low-halogen packages ? multiple device densities with compatible package footprints for seamless migration between different device densities ? rohs-compliant and leaded (1) options packaging enhanced 8-input alm with four registers high-performance fpga fabric ? m10k10-kilobits (kb) memory blocks with soft error correction code (ecc) ? memory logic array block (mlab)640-bit distributed lutram where you can use up to 25% of the alms as mlab memory internal memory blocks ? native support for up to three signal processing precision levels (three 9 x 9 , two 18 x 18 , or one 27 x 27 multiplier) in the same variable-precision dsp block ? 64-bit accumulator and cascade ? embedded internal coefficient memory ? preadder/subtractor for improved efficiency variable-precision dsp embedded hard ip blocks ddr3, ddr2, and lpddr2 with 16 and 32 bit ecc support memory controller pci express ? ( pcie ? ) gen2 and gen1 (x1, x2, or x4) hard ip with multifunction support, endpoint, and root port embedded transceiver i/o ? up to 550 mhz global clock network ? global, quadrant, and peripheral clock networks ? clock networks that are not used can be powered down to reduce dynamic power clock networks (1) contact altera for availability. cyclone v device overview altera corporation send feedback cv-51001 summary of cyclone v features 2 2013.12.26
description feature ? precision clock synthesis, clock delay compensation, and zero delay buffering (zdb) ? integer mode and fractional mode phase-locked loops (plls) ? 875 megabits per second (mbps) lvds receiver and 840 mbps lvds transmitter ? 400 mhz / 800 mbps external memory interface ? on-chip termination (oct) ? 3.3 v support with up to 16 ma drive strength fpga general-purpose i/os (gpios) ? 614 mbps to 6.144 gbps integrated transceiver speed ? transmit pre-emphasis and receiver equalization ? dynamic partial reconfiguration of individual channels low-power high-speed serial interface ? single or dual-core arm cortex-a9 mpcore processor-up to 925 mhz maximum frequency with support for symmetric and asymmetric multiprocessing ? interface peripherals10/100/1000 ethernet media access control (emac), usb 2.0 on-the-go (otg) controller, quad serial peripheral interface (qspi) flash controller, nand flash controller, secure digital/multimediacard (sd/mmc) controller, uart, controller area network (can), serial peripheral interface (spi), i 2 c interface, and up to 85 hps gpio interfaces ? system peripheralsgeneral-purpose timers, watchdog timers, direct memory access (dma) controller, fpga configuration manager, and clock and reset managers ? on-chip ram and boot rom ? hpsCfpga bridgesinclude the fpga-to-hps, hps-to-fpga, and lightweight hps-to-fpga bridges that allow the fpga fabric to issue transactions to slaves in the hps, and vice versa ? fpga-to-hps sdram controller subsystemprovides a configurable interface to the multiport front end (mpfe) of the hps sdram controller ? arm coresight ? jtag debug access port, trace port, and on-chip trace storage hps ( cyclone v se , sx, and st devices only) ? tamper protectioncomprehensive design protection to protect your valuable ip investments ? enhanced advanced encryption standard (aes) design security features ? cvp ? partial and dynamic reconfiguration of the fpga ? active serial (as) x1 and x4, passive serial (ps), jtag, and fast passive parallel (fpp) x8 and x16 configuration options configuration altera corporation cyclone v device overview send feedback 3 summary of cyclone v features cv-51001 2013.12.26
cyclone v device variants and packages table 3: device variants for the cyclone v device family description variant optimized for the lowest system cost and power requirement for a wide spectrum of general logic and dsp applications cyclone v e optimized for the lowest cost and power requirement for 614 mbps to 3.125 gbps transceiver applications cyclone v gx the fpga industrys lowest cost and lowest power requirement for 6.144 gbps transceiver applications cyclone v gt soc with integrated arm-based hps cyclone v se soc with integrated arm-based hps and 3.125 gbps transceivers cyclone v sx soc with integrated arm-based hps and 5 gbps transceivers cyclone v st cyclone v e this section provides the available options, maximum resource counts, and package plan for the cyclone v e devices. the information in this section is correct at the time of publication. for the latest information and to get more details, refer to the altera product selector. related information altera product selector provides the latest information about altera products. cyclone v device overview altera corporation send feedback cv-51001 cyclone v device variants and packages 4 2013.12.26
available options figure 1: sample ordering code and available options for cyclone v e devices maximum resources table 4: maximum resource counts for cyclone v e devices member code resource a9 a7 a5 a4 a2 301 149.5 77 49 25 logic elements (le) (k) 113,560 56,480 29,080 18,480 9,434 alm 454,240 225,920 116,320 73,920 37,736 register 12,200 6,860 4,460 3,080 1,760 m10k memory (kb) 1,717 836 424 303 196 mlab 342 156 150 66 25 variable-precision dsp block 684 312 300 132 50 18 x 18 multiplier 8 7 6 4 4 pll 480 480 240 224 224 gpio 120 120 60 56 56 transmitter lvds 120 120 60 56 56 receiver 2 2 2 1 1 hard memory controller altera corporation cyclone v device overview send feedback 5 available options cv-51001 2013.12.26 family signature embedded hard ips package type package code operating temperature fpga fabric speed grade optional suffix indicates specific device options or shipment method e : enhanced logic/memory b : no hard pcie or hard memory controller f : no hard pcie and maximum 2 hard memory controllers 5c : cyclone v f : fineline bga (fbga) u : ultra fineline bga (ubga) m : micro fineline bga (mbga) fbga package type 17 : 256 pins 23 : 484 pins 27 : 672 pins 31 : 896 pins ubga package type 15 : 324 pins 19 : 484 pins mbga package type 13 : 383 pins 15 : 484 pins c : commercial (t j = 0 c to 85 c) i : industrial (t j = -40 c to 100 c) a : automotive (t j = -40 c to 125 c) 6 (fastest) 7 8 n : lead-free packaging contact altera for availability of leaded options es : engineering sample 5c e f a9 f 31 c 7 n member code family variant a2 : 25k logic elements a4 : 49k logic elements a5 : 77k logic elements a7 : 149.5k logic elements a9 : 301k logic elements
related information i/o features in cyclone v devices provides the number of lvds channels in each device package. package plan table 5: package plan for cyclone v e devices f896 (31 mm) f672 (27 mm) f484 (23 mm) u484 (19 mm) f256 (17 mm) u324 (15 mm) m484 (15 mm) m383 (13 mm) member code gpio gpio gpio gpio gpio gpio gpio gpio 224 224 128 176 223 a2 224 224 128 176 223 a4 240 224 175 a5 480 336 240 240 240 a7 480 336 224 240 a9 cyclone v gx this section provides the available options, maximum resource counts, and package plan for the cyclone v gx devices. the information in this section is correct at the time of publication. for the latest information and to get more details, refer to the altera product selector. related information altera product selector provides the latest information about altera products. available options the following figure shows sample ordering code and lists the options available for cyclone v gx devices. cyclone v device overview altera corporation send feedback cv-51001 package plan 6 2013.12.26
figure 2: sample ordering code and available options for cyclone v gx devices maximum resources table 6: maximum resource counts for cyclone v gx devices member code resource c9 c7 c5 c4 c3 301 149.5 77 50 31.5 logic elements (le) (k) 113,560 56,480 29,080 18,868 11,900 alm 454,240 225,920 116,320 75,472 47,600 register 12,200 6,860 4,460 2,500 1,190 m10k memory (kb) 1,717 836 424 295 159 mlab 342 156 150 70 51 variable-precision dsp block 684 312 300 140 102 18 x 18 multiplier 8 7 6 6 4 pll 12 9 6 6 3 3 gbps transceiver 560 480 336 336 208 gpio (2) 140 120 84 84 52 transmitter lvds 140 120 84 84 52 receiver (2) the number of gpios does not include transceiver i/os . in the quartus ii software, the number of user i/os includes transceiver i/os . altera corporation cyclone v device overview send feedback 7 maximum resources cv-51001 2013.12.26 family signature embedded hard ips transceiver count transceiver speed grade package type package code operating temperature fpga fabric speed grade optional suffix indicates specific device options or shipment method gx : 3-gbps transceivers b : no hard pcie or hard memory controller f : maximum 2 hard pcie and 2 hard memory controllers 5c : cyclone v c3 : 31.5k logic elements c4 : 50k logic elements c5 : 77k logic elements c7 : 149.5k logic elements c9 : 301k logic elements b : 3 f : 4 a : 5 c : 6 d : 9 e : 12 6 : 3.125 gbps 7 : 2.5 gbps f : fineline bga (fbga) u : ultra fineline bga (ubga) m : micro fineline bga (mbga) fbga package type 23 : 484 pins 27 : 672 pins 31 : 896 pins 35 : 1,152 pins ubga package type 15 : 324 pins 19 : 484 pins mbga package type 11 : 301 pins 13 : 383 pins 15 : 484 pins c : commercial (t j = 0 c to 85 c) i : industrial (t j = -40 c to 100 c) a : automotive (t j = -40 c to 125 c) 6 (fastest) 7 8 n : lead-free packaging contact altera for availability of leaded options es : engineering sample 5c gx f c9 e 6 f 35 c 7 n member code family variant
member code resource c9 c7 c5 c4 c3 2 2 2 2 1 pcie hard ip block 2 2 2 2 1 hard memory controller related information i/o features in cyclone v devices provides the number of lvds channels in each device package. package plan table 7: package plan for cyclone v gx devices f1152 (35 mm) f896 (31 mm) f672 (27 mm) f484 (23 mm) u484 (19 mm) u324 (15 mm) m484 (15 mm) m383 (13 mm) m301 (11 mm) member code xcvr gpio xcvr gpio xcvr gpio xcvr gpio xcvr gpio xcvr gpio xcvr gpio xcvr gpio xcvr gpio 3 208 3 208 3 144 c3 6 336 6 240 6 224 6 175 4 129 c4 6 336 6 240 6 224 6 175 4 129 c5 9 480 9 336 6 240 6 240 3 240 c7 12 560 12 480 9 336 6 224 5 240 c9 cyclone v gt this section provides the available options, maximum resource counts, and package plan for the cyclone v gt devices. the information in this section is correct at the time of publication. for the latest information and to get more details, refer to the altera product selector. related information altera product selector provides the latest information about altera products. available options the following figure shows sample ordering code and lists the options available for cyclone v gt devices. cyclone v device overview altera corporation send feedback cv-51001 package plan 8 2013.12.26
figure 3: sample ordering code and available options for cyclone v gt devices maximum resources table 8: maximum resource counts for cyclone v gt devices member code resource d9 d7 d5 301 149.5 77 logic elements (le) (k) 113,560 56,480 29,080 alm 454,240 225,920 116,320 register 12,200 6,860 4,460 m10k memory (kb) 1,717 836 424 mlab 342 156 150 variable-precision dsp block 684 312 300 18 x 18 multiplier 8 7 6 pll 12 9 6 6 gbps transceiver 560 480 336 gpio (3) 140 120 84 transmitter lvds 140 120 84 receiver 2 2 2 pcie hard ip block (3) the number of gpios does not include transceiver i/os . in the quartus ii software, the number of user i/os includes transceiver i/os . altera corporation cyclone v device overview send feedback 9 maximum resources cv-51001 2013.12.26 family signature embedded hard ips transceiver count transceiver speed grade package type package code operating temperature fpga fabric speed grade gt : 6-gbps transceivers f : maximum 2 hard pcie and 2 hard memory controllers 5c : cyclone v d5 : 77k logic elements d7 : 149.5k logic elements d9 : 301k logic elements b : 3 f : 4 a : 5 c : 6 d : 9 e : 12 5 : 6.144 gbps f : fineline bga (fbga) u : ultra fineline bga (ubga) m : micro fineline bga (mbga) fbga package type 23 : 484 pins 27 : 672 pins 31 : 896 pins 35 : 1,152 pins ubga package type 19 : 484 pins mbga package type 11 : 301 pins 13 : 383 pins 15 : 484 pins c : commercial (t j = 0 c to 85 c) i : industrial (t j = -40 c to 100 c) a : automotive (t j = -40 c to 125 c) 6 (fastest) 7 8 5c gt f d9 e 5 f 35 c 7 n member code family variant optional suffix indicates specific device options or shipment method n : lead-free packaging contact altera for availability of leaded options es : engineering sample
member code resource d9 d7 d5 2 2 2 hard memory controller related information i/o features in cyclone v devices provides the number of lvds channels in each device package. package plan table 9: package plan for cyclone v gt devices f1152 (35 mm) f896 (31 mm) f672 (27 mm) f484 (23 mm) u484 (19 mm) m484 (15 mm) m383 (13 mm) m301 (11 mm) member code xcvr gpio xcvr gpio xcvr gpio xcvr gpio xcvr gpio xcvr gpio xcvr gpio xcvr gpio 6 336 6 240 6 224 6 175 4 129 d5 9 (4) 480 9 (4) 336 6 240 6 240 3 240 d7 12 (5) 560 12 (5) 480 9 (4) 336 6 224 5 240 d9 cyclone v se this section provides the available options, maximum resource counts, and package plan for the cyclone v se devices. the information in this section is correct at the time of publication. for the latest information and to get more details, refer to the altera product selector. related information altera product selector provides the latest information about altera products. available options the following figure shows sample ordering code and lists the options available for cyclone v se devices. (4) if you require cpri (at 6.144 gbps) and pcie gen2 transmit jitter compliance, altera recommends that you use only up to three full-duplex transceiver channels for cpri, and up to six full-duplex channels for pcie gen2. the cmu channels are not considered full-duplex channels. (5) if you require cpri (at 6.144 gbps) and pcie gen2 transmit jitter compliance, altera recommends that you use only up to three full-duplex transceiver channels for cpri, and up to eight full-duplex channels for pcie gen2. the cmu channels are not considered full-duplex channels. cyclone v device overview altera corporation send feedback cv-51001 package plan 10 2013.12.26
figure 4: sample ordering code and available options for cyclone v se devices maximum resources table 10: maximum resource counts for cyclone v se devices member code resource a6 a5 a4 a2 110 85 40 25 logic elements (le) (k) 41,509 32,075 15,094 9,434 alm 166,036 128,300 60,376 37,736 register 5,570 3,970 2,700 1,400 m10k memory (kb) 621 480 231 138 mlab 112 87 84 36 variable-precision dsp block 224 174 168 72 18 x 18 multiplier 6 6 5 5 fpga pll 3 3 3 3 hps pll 288 288 145 145 fpga gpio 181 181 181 181 hps i/o 72 72 32 32 transmitter lvds 72 72 37 37 receiver 1 1 1 1 fpga hard memory controller 1 1 1 1 hps hard memory controller single- or dual-core single- or dual- core single- or dual-core single- or dual-core arm cortex-a9 mpcore processor altera corporation cyclone v device overview send feedback 11 maximum resources cv-51001 2013.12.26 family signature embedded hard ips package type package code operating temperature fpga fabric speed grade optional suffix indicates specific device options or shipment method se : soc with enhanced logic/memory 5c : cyclone v f : fineline bga (fbga) u : ultra fineline bga (ubga) fbga package type 31 : 896 pins ubga package type 19 : 484 pins 23 : 672 pins c : commercial (t j = 0 c to 85 c) i : industrial (t j = -40 c to 100 c) a : automotive (t j = -40 c to 125 c) 6 (fastest) 7 8 processor cores omit for dual-core s : single-core n : lead-free packaging contact altera for availability of leaded options es : engineering sample 5c se m a6 f 31 c 6 s n member code family variant a2 : 25k logic elements a4 : 40k logic elements a5 : 85k logic elements a6 : 110k logic elements b : no hard pcie or hard memory controller m : no hard pcie and 1 hard memory controller
related information i/o features in cyclone v devices provides the number of lvds channels in each device package. package plan table 11: package plan for cyclone v se devices the hps i/o counts are the number of i/os in the hps and does not correlate with the number of hps-specific i/o pins in the fpga. each hps-specific pin in the fpga may be mapped to several hps i/os . f896 (31 mm) u672 (23 mm) u484 (19 mm) member code hps i/o fpga gpio hps i/o fpga gpio hps i/o fpga gpio 181 145 151 66 a2 181 145 151 66 a4 181 288 181 145 151 66 a5 181 288 181 145 151 66 a6 cyclone v sx this section provides the available options, maximum resource counts, and package plan for the cyclone v sx devices. the information in this section is correct at the time of publication. for the latest information and to get more details, refer to the altera product selector. related information altera product selector provides the latest information about altera products. available options the following figure shows sample ordering code and lists the options available for cyclone v sx devices. cyclone v device overview altera corporation send feedback cv-51001 package plan 12 2013.12.26
figure 5: sample ordering code and available options for cyclone v sx devices maximum resources table 12: maximum resource counts for cyclone v sx devices member code resource c6 c5 c4 c2 110 85 40 25 logic elements (le) (k) 41,509 32,075 15,094 9,434 alm 166,036 128,300 60,376 37,736 register 5,570 3,970 2,700 1,400 m10k memory (kb) 621 480 231 138 mlab 112 87 84 36 variable-precision dsp block 224 174 168 72 18 x 18 multiplier 6 6 5 5 fpga pll 3 3 3 3 hps pll 9 9 6 6 3 gbps transceiver 288 288 145 145 fpga gpio (6) 181 181 181 181 hps i/o 72 72 32 32 transmitter lvds 72 72 37 37 receiver (6) the number of gpios does not include transceiver i/os . in the quartus ii software, the number of user i/os includes transceiver i/os . altera corporation cyclone v device overview send feedback 13 maximum resources cv-51001 2013.12.26 family signature embedded hard ips transceiver count transceiver speed grade package type package code operating temperature fpga fabric speed grade optional suffix indicates specific device options or shipment method sx : soc with 3-gbps transceivers f : maximum 2 hard pcie controllers and 1 hard memory controller 5c : cyclone v c2 : 25k logic elements c4 : 40k logic elements c5 : 85k logic elements c6 : 110k logic elements c : 6 d : 9 6 : 3.125 gbps f : fineline bga (fbga) u : ultra fineline bga (ubga) fbga package type 31 : 896 pins ubga package type 23 : 672 pins c : commercial (t j = 0 c to 85 c) i : industrial (t j = -40 c to 100 c) a : automotive (t j = -40 c to 125 c) 6 (fastest) 7 8 n : lead-free packaging contact altera for availability of leaded options es : engineering sample 5c sx f c6 d 6 f 31 c 6 n member code family variant
member code resource c6 c5 c4 c2 2 (7) 2 (7) 2 2 pcie hard ip block 1 1 1 1 fpga hard memory controller 1 1 1 1 hps hard memory controller dual-core dual-core dual-core dual-core arm cortex-a9 mpcore processor related information i/o features in cyclone v devices provides the number of lvds channels in each device package. package plan table 13: package plan for cyclone v sx devices the hps i/o counts are the number of i/os in the hps and does not correlate with the number of hps-specific i/o pins in the fpga. each hps-specific pin in the fpga may be mapped to several hps i/os . f896 (31 mm) u672 (23 mm) member code xcvr hps i/o fpga gpio xcvr hps i/o fpga gpio 6 181 145 c2 6 181 145 c4 9 181 288 6 181 145 c5 9 181 288 6 181 145 c6 cyclone v st this section provides the available options, maximum resource counts, and package plan for the cyclone v st devices. the information in this section is correct at the time of publication. for the latest information and to get more details, refer to the altera product selector. related information altera product selector provides the latest information about altera products. available options the following figure shows sample ordering code and lists the options available for cyclone v st devices. (7) 1 pcie hard ip block in u672 package. cyclone v device overview altera corporation send feedback cv-51001 package plan 14 2013.12.26
figure 6: sample ordering code and available options for cyclone v st devices maximum resources table 14: maximum resource counts for cyclone v st devices member code resource d6 d5 110 85 logic elements (le) (k) 41,509 32,075 alm 166,036 128,300 register 5,570 3,970 m10k memory (kb) 621 480 mlab 112 87 variable-precision dsp block 224 174 18 x 18 multiplier 6 6 fpga pll 3 3 hps pll 9 9 5 gbps transceiver 288 288 fpga gpio (8) 181 181 hps i/o 72 72 transmitter lvds 72 72 receiver 2 2 pcie hard ip block 1 1 fpga hard memory controller (8) the number of gpios does not include transceiver i/os . in the quartus ii software, the number of user i/os includes transceiver i/os . altera corporation cyclone v device overview send feedback 15 maximum resources cv-51001 2013.12.26 family signature embedded hard ips transceiver count transceiver speed grade package type package code operating temperature fpga fabric speed grade optional suffix indicates specific device options or shipment method st : soc with 5-gbps transceivers f : 2 hard pcie controllers and 1 hard memory controller 5c : cyclone v d5 : 85k logic elements d6 : 110k logic elements d : 9 5 : 5 gbps f : fineline bga (fbga) 31 : 896 pins c : commercial (t j = 0 c to 85 c) i : industrial (t j = -40 c to 100 c) a : automotive (t j = -40 c to 125 c) 6 (fastest) 7 8 n : lead-free packaging contact altera for availability of leaded options es : engineering sample 5c st f d6 d 5 f 31 c 6 n member code family variant
member code resource d6 d5 1 1 hps hard memory controller dual-core dual-core arm cortex-a9 mpcore processor related information i/o features in cyclone v devices provides the number of lvds channels in each device package. package plan table 15: package plan for cyclone v st devices the hps i/o counts are the number of i/os in the hps and does not correlate with the number of hps-specific i/o pins in the fpga. each hps-specific pin in the fpga may be mapped to several hps i/os . f896 (31 mm) member code xcvr hps i/o fpga gpio 9 (9) 181 288 d5 9 (9) 181 288 d6 (9) if you require cpri (at 4.9152 gbps) and pcie gen2 transmit jitter compliance, altera recommends that you use only up to seven full-duplex transceiver channels for cpri, and up to six full-duplex channels for pcie gen2. the cmu channels are not considered full-duplex channels. cyclone v device overview altera corporation send feedback cv-51001 package plan 16 2013.12.26
i/o vertical migration for cyclone v devices figure 7: vertical migration capability across cyclone v device packages and densities the arrows indicate the vertical migration paths. the devices included in each vertical migration path are shaded. you can also migrate your design across device densities in the same package option if the devices have the same dedicated pins, configuration pins, and power pins. you can achieve the vertical migration shaded in red if you use only up to 175 gpios. this migration path is not shown in the quartus ii software pin migration view. to verify the pin migration compatibility, use the pin migration view window in the quartus ? ii software pin planner. note: adaptive logic module cyclone v devices use a 28 nm alm as the basic building block of the logic fabric. the alm, as shown in following figure, uses an 8-input fracturable look-up table (lut) with four dedicated registers to help improve timing closure in register-rich designs and achieve an even higher design packing capability than previous generations. altera corporation cyclone v device overview send feedback 17 i/o vertical migration for cyclone v devices cv-51001 2013.12.26 v ariant member code package m301 m383 m484 f256 u324 u484 f484 u672 f672 f896 f 1 152 cyclone v e a2 a4 a5 a7 a9 cyclone v gx c3 c4 c5 c7 c9 cyclone v gt d5 d7 d9 cyclone v se a2 a4 a5 a6 cyclone v sx c2 c4 c5 c6 cyclone v st d5 d6
figure 8: alm for cyclone v devices you can configure up to 25% of the alms in the cyclone v devices as distributed memory using mlabs. related information embedded memory capacity in cyclone v devices on page 20 lists the embedded memory capacity for each device. variable-precision dsp block cyclone v devices feature a variable-precision dsp block that supports these features: ? configurable to support signal processing precisions ranging from 9 x 9, 18 x 18 and 27 x 27 bits natively ? a 64-bit accumulator ? a hard preadder that is available in both 18- and 27-bit modes ? cascaded output adders for efficient systolic finite impulse response (fir) filters ? internal coefficient register banks, 8 deep, for each multiplier in 18- or 27-bit mode ? fully independent multiplier operation ? a second accumulator feedback register to accommodate complex multiply-accumulate functions ? efficient support for single-precision floating point arithmetic ? the inferability of all modes by the quartus ii design software table 16: variable-precision dsp block configurations for cyclone v devices dsp block resource multiplier size (bit) usage example 1 three 9 x 9 low precision fixed point for video applications 1 two 18 x 18 medium precision fixed point in fir filters 1 two 18 x 18 with accumulate fir filters and general dsp usage cyclone v device overview altera corporation send feedback cv-51001 variable-precision dsp block 18 2013.12.26 fpga device 1 2 3 4 5 6 7 8 adaptive lut full adder reg reg full adder reg reg
dsp block resource multiplier size (bit) usage example 1 one 27 x 27 with accumulate high precision fixed- or floating-point implementations you can configure each dsp block during compilation as independent three 9 x 9 , two 18 x 18 , or one 27 x 27 multipliers. with a dedicated 64 bit cascade bus, you can cascade multiple variable-precision dsp blocks to implement even higher precision dsp functions efficiently. table 17: number of multipliers in cyclone v devices the table lists the variable-precision dsp resources by bit precision for each cyclone v device. 18 x 18 multiplier adder summed with 36 bit input 18 x 18 multiplier adder mode independent input and output multiplications operator variable- precision dsp block member code variant 27 x 27 multiplier 18 x 18 multiplier 9 x 9 multiplier 25 25 25 50 75 25 a2 cyclone v e 66 66 66 132 198 66 a4 150 150 150 300 450 150 a5 156 156 156 312 468 156 a7 342 342 342 684 1,026 342 a9 51 51 51 102 153 51 c3 cyclone v gx 70 70 70 140 210 70 c4 150 150 150 300 450 150 c5 156 156 156 312 468 156 c7 342 342 342 684 1,026 342 c9 150 150 150 300 450 150 d5 cyclone v gt 156 156 156 312 468 156 d7 342 342 342 684 1,026 342 d9 36 36 36 72 108 36 a2 cyclone v se 84 84 84 168 252 84 a4 87 87 87 174 261 87 a5 112 112 112 224 336 112 a6 36 36 36 72 108 36 c2 cyclone v sx 84 84 84 168 252 84 c4 87 87 87 174 261 87 c5 112 112 112 224 336 112 c6 altera corporation cyclone v device overview send feedback 19 variable-precision dsp block cv-51001 2013.12.26
18 x 18 multiplier adder summed with 36 bit input 18 x 18 multiplier adder mode independent input and output multiplications operator variable- precision dsp block member code variant 27 x 27 multiplier 18 x 18 multiplier 9 x 9 multiplier 87 87 87 174 261 87 d5 cyclone v st 112 112 112 224 336 112 d6 embedded memory blocks the embedded memory blocks in the devices are flexible and designed to provide an optimal amount of small- and large-sized memory arrays to fit your design requirements. types of embedded memory the cyclone v devices contain two types of memory blocks: ? 10 kb m10k blocksblocks of dedicated memory resources. the m10k blocks are ideal for larger memory arrays while still providing a large number of independent ports. ? 640 bit memory logic array blocks (mlabs)enhanced memory blocks that are configured from dual- purpose logic array blocks (labs). the mlabs are ideal for wide and shallow memory arrays. the mlabs are optimized for implementation of shift registers for digital signal processing (dsp) applications, wide shallow fifo buffers, and filter delay lines. each mlab is made up of ten adaptive logic modules (alms). in the cyclone v devices, you can configure these alms as ten 32 x 2 blocks, giving you one 32 x 20 simple dual-port sram block per mlab. embedded memory capacity in cyclone v devices table 18: embedded memory capacity and distribution in cyclone v devices total ram bit (kb) mlab m10k member code variant ram bit (kb) block ram bit (kb) block 1,956 196 314 1,760 176 a2 cyclone v e 3,383 303 485 3,080 308 a4 4,884 424 679 4,460 446 a5 7,696 836 1338 6,860 686 a7 13,917 1,717 2748 12,200 1,220 a9 1,349 159 255 1,190 119 c3 cyclone v gx 2,795 295 472 2,500 250 c4 4,884 424 679 4,460 446 c5 7,696 836 1338 6,860 686 c7 13,917 1,717 2748 12,200 1,220 c9 cyclone v device overview altera corporation send feedback cv-51001 embedded memory blocks 20 2013.12.26
total ram bit (kb) mlab m10k member code variant ram bit (kb) block ram bit (kb) block 4,884 424 679 4,460 446 d5 cyclone v gt 7,696 836 1338 6,860 686 d7 13,917 1,717 2748 12,200 1,220 d9 1,538 138 221 1,400 140 a2 cyclone v se 2,460 231 370 2,700 270 a4 4,450 480 768 3,970 397 a5 5,761 621 994 5,570 557 a6 1,538 138 221 1,400 140 c2 cyclone v sx 2,460 231 370 2,700 270 c4 4,450 480 768 3,970 397 c5 5,761 621 994 5,570 557 c6 4,450 480 768 3,970 397 d5 cyclone v st 5,761 621 994 5,570 557 d6 embedded memory configurations table 19: supported embedded memory block configurations for cyclone v devices this table lists the maximum configurations supported for the embedded memory blocks. the information is applicable only to the single-port ram and rom modes. programmable width depth (bits) memory block x16, x18, or x20 32 mlab x40 or x32 256 m10k x20 or x16 512 x10 or x8 1k x5 or x4 2k x2 4k x1 8k clock networks and pll clock sources cyclone v devices have 16 global clock networks capable of up to 550 mhz operation. the clock network architecture is based on altera's global, quadrant, and peripheral clock structure. this clock structure is supported by dedicated clock input pins and fractional plls. to reduce power consumption, the quartus ii software identifies all unused sections of the clock network and powers them down. note: altera corporation cyclone v device overview send feedback 21 embedded memory configurations cv-51001 2013.12.26
pll features the plls in the cyclone v devices support the following features: ? frequency synthesis ? on-chip clock deskew ? jitter attenuation ? programmable output clock duty cycles ? pll cascading ? reference clock switchover ? programmable bandwidth ? user-mode reconfiguration of plls ? low power mode for each fractional pll ? dynamic phase shift ? direct, source synchronous, zero delay buffer, external feedback, and lvds compensation modes fractional pll in addition to integer plls, the cyclone v devices use a fractional pll architecture. the devices have up to eight plls, each with nine output counters. you can use the output counters to reduce pll usage in two ways: ? reduce the number of oscillators that are required on your board by using fractional plls ? reduce the number of clock pins that are used in the device by synthesizing multiple clock frequencies from a single reference clock source if you use the fractional pll mode, you can use the plls for precision fractional-n frequency synthesisremoving the need for off-chip reference clock sources in your design. the transceiver fractional plls that are not used by the transceiver i/os can be used as general purpose fractional plls by the fpga fabric. fpga general purpose i/o cyclone v devices offer highly configurable gpios. the following list describes the features of the gpios: ? programmable bus hold and weak pull-up ? lvds output buffer with programmable differential output voltage (v od ) and programmable pre- emphasis ? on-chip parallel termination ( r t oct ) for all i/o banks with oct calibration to limit the termination impedance variation ? on-chip dynamic termination that has the ability to swap between series and parallel termination, depending on whether there is read or write on a common bus for signal integrity ? easy timing closure support using the hard read fifo in the input register path, and delay-locked loop (dll) delay chain with fine and coarse architecture pcie gen1 and gen2 hard ip cyclone v gx, gt, sx, and st devices contain pcie hard ip that is designed for performance and ease-of-use . the pcie hard ip consists of the mac, data link, and transaction layers. cyclone v device overview altera corporation send feedback cv-51001 fpga general purpose i/o 22 2013.12.26
the pcie hard ip supports pcie gen2 and gen1 end point and root port for up to x4 lane configuration. the pcie gen2 x4 support is pcie-compatible. the pcie endpoint support includes multifunction support for up to eight functions, as shown in the following figure. the integrated multifunction support reduces the fpga logic requirements by up to 20,000 les for pcie designs that require multiple peripherals. figure 9: pcie multifunction for cyclone v devices the cyclone v pcie hard ip operates independently from the core logic. this independent operation allows the pcie link to wake up and complete link training in less than 100 ms while the cyclone v device completes loading the programming file for the rest of the device. in addition, the pcie hard ip in the cyclone v device provides improved end-to-end datapath protection using ecc. external memory interface this section provides an overview of the external memory interface in cyclone v devices. hard and soft memory controllers cyclone v devices support up to two hard memory controllers for ddr3, ddr2, and lpddr2 sdram devices. each controller supports 8 to 32 bit components of up to 4 gigabits (gb) in density with two chip selects and optional ecc. for the cyclone v soc devices, an additional hard memory controller in the hps supports ddr3, ddr2, and lpddr2 sdram devices. all cyclone v devices support soft memory controllers for ddr3, ddr2, and lpddr2 sdram devices for maximum flexibility. external memory performance table 20: external memory interface performance in cyclone v devices the maximum and minimum operating frequencies depend on the memory interface standards and the supported delay-locked loop (dll) frequency listed in the device datasheet. minimum frequency (mhz) maximum frequency (mhz) voltage (v) interface soft controller hard controller 303 303 400 1.5 ddr3 sdram 303 303 400 1.35 altera corporation cyclone v device overview send feedback 23 external memory interface cv-51001 2013.12.26 pcie link external system fpga device host cpu memory controller root complex local peripheral 1 local peripheral 2 pcie rp pcie ep can gbe ata bridge to pcie spi gpio i 2 c usb
minimum frequency (mhz) maximum frequency (mhz) voltage (v) interface soft controller hard controller 167 300 400 1.8 ddr2 sdram 167 300 333 1.2 lpddr2 sdram related information external memory interface spec estimator for the latest information and to estimate the external memory system performance specification, use altera's external memory interface spec estimator tool. hps external memory performance table 21: hps external memory interface performance the hard processor system (hps) is available in cyclone v soc devices only. hps hard controller (mhz) voltage (v) interface 400 1.5 ddr3 sdram 400 1.35 400 1.8 ddr2 sdram 333 1.2 lpddr2 sdram related information external memory interface spec estimator for the latest information and to estimate the external memory system performance specification, use altera's external memory interface spec estimator tool. low-power serial transceivers cyclone v devices deliver the industrys lowest power 6.144 gbps transceivers at an estimated 88 mw maximum power consumption per channel. cyclone v transceivers are designed to be compliant with a wide range of protocols and data rates. transceiver channels the transceivers are positioned on the left outer edge of the device. the transceiver channels consist of the physical medium attachment (pma), physical coding sublayer (pcs), and clock networks. cyclone v device overview altera corporation send feedback cv-51001 hps external memory performance 24 2013.12.26
figure 10: device chip overview for cyclone v gx and gt devices the figure shows a cyclone v fpga with transceivers. different cyclone v devices may have a different floorplans than the one shown here. pma features to prevent core and i/o noise from coupling into the transceivers, the pma block is isolated from the rest of the chipensuring optimal signal integrity. for the transceivers, you can use the channel pll of an unused receiver pma as an additional transmit pll. table 22: pma features of the transceivers in cyclone v devices capability features driving capability up to 6.144 gbps backplane support superior jitter tolerance pll-based clock recovery flexible deserialization width and configurable word alignment pattern programmable deserialization and word alignment ? up to 14.37 db of pre-emphasis and up to 4.7 db of equalization ? no decision feedback equalizer (dfe) equalization and pre-emphasis 614 mbps to 6.144 gbps ring oscillator transmit plls 20 mhz to 400 mhz input reference clock range altera corporation cyclone v device overview send feedback 25 pma features cv-51001 2013.12.26 i/o, lvds, and memory interface i/o, lvds, and memory interface i/o, lvds, and memory interface transceiver pma blocks fractional plls hard pcs blocks fractional pll fractional plls pcie hard ip blocks hard memory controller hard memory controller core logic fabric and mlabs variable-precision dsp blocks m10k internal memory blocks transceiver pma transceiver pma transceiver pma hard pcs hard pcs hard pcs clock networks transceiver individual channels
capability features allows the reconfiguration of a single channel without affecting the operation of other channels transceiver dynamic reconfigura- tion pcs features the cyclone v core logic connects to the pcs through an 8, 10, 16, 20, 32, or 40 bit interface, depending on the transceiver data rate and protocol. cyclone v devices contain pcs hard ip to support pcie gen1 and gen2, gbps ethernet (gbe), serial rapidio ? (srio), and common public radio interface (cpri). most of the standard and proprietary protocols from 614 mbps to 6.144 gbps are supported. table 23: transceiver pcs features for cyclone v devices receiver data path feature transmitter data path feature data rates(gbps) pcs support ? word aligner ? deskew fifo ? rate-match fifo ? 8b/10b decoder ? byte deserializer ? byte ordering ? receiver phase compensa- tion fifo ? phase compensation fifo ? byte serializer ? 8b/10b encoder ? transmitter bit-slip 0.614 to 6.144 3-gbps and 6-gbps basic ? dedicated pcie phy ip core ? pipe 2.0 interface to the core logic ? dedicated pcie phy ip core ? pipe 2.0 interface to the core logic 2.5 and 5.0 pcie gen1 (x1, x2, x4) pcie gen2 ( x1, x2, x4) (10) ? custom phy ip core with preset feature ? gbe receiver synchroniza- tion state machine ? custom phy ip core with preset feature ? gbe transmitter synchroniza- tion state machine 1.25 gbe ? dedicated xaui phy ip core ? xaui synchronization state machine for realigning four channels ? dedicated xaui phy ip core ? xaui synchronization state machine for bonding four channels 3.125 xaui (11) 3.75 higig (10) pcie gen2 is supported only for cyclone v gt devices. the pcie gen2 x4 support is pcie-compatible . (11) xaui is supported through the soft pcs. cyclone v device overview altera corporation send feedback cv-51001 pcs features 26 2013.12.26
receiver data path feature transmitter data path feature data rates(gbps) pcs support ? custom phy ip core with preset feature ? srio version 2.1-compliant x2 and x4 deskew state machine ? custom phy ip core with preset feature ? srio version 2.1-compliant x2 and x4 channel bonding 1.25 to 3.125 srio 1.3 and 2.1 custom phy ip core with preset feature custom phy ip core with preset feature 0.27 (12) , 1.485, and 2.97 sdi, sd/hd , and 3g- sdi 0.3125 (13) to 3.125 jesd204a ? custom phy ip core with preset feature ? signal detect ? wider spread of asynchronous ssc ? custom phy ip core with preset feature ? electrical idle 1.5 and 3.0 serial ata gen1 and gen2 ? dedicated deterministic latency phy ip core ? receiver (rx) deterministic latency state machine ? dedicated deterministic latency phy ip core ? transmitter (tx) manual bit-slip mode 0.6144 to 6.144 cpri 4.1 (14) 0.768 to 3.072 obsai rp3 ? custom phy ip core ? wider spread of asynchronous ssc custom phy ip core up to 3.75 v-by-one hs 1.62 and 2.7 displayport 1.2 (15) soc with hps each soc combines an fpga fabric and an hps in a single device. this combination delivers the flexibility of programmable logic with the power and cost savings of hard ip in these ways: ? reduces board space, system power, and bill of materials cost by eliminating a discrete embedded processor ? allows you to differentiate the end product in both hardware and software, and to support virtually any interface standard ? extends the product life and revenue through in-field hardware and software updates (12) the 0.27-gbps data rate is supported using oversampling user logic that you must implement in the fpga fabric. (13) the 0.3125-gbps data rate is supported using oversampling user logic that you must implement in the fpga fabric. (14) high-voltage output mode ( 1000-base-cx ) is not supported. (15) pending characterization. altera corporation cyclone v device overview send feedback 27 soc with hps cv-51001 2013.12.26
hps features the hps consists of a dual-core arm cortex-a9 mpcore processor, a rich set of peripherals, and a shared multiport sdram memory controller, as shown in the following figure. figure 11: hps with dual-core arm cortex-a9 mpcore processor system peripherals and debug access port each ethernet mac, usb otg, nand flash controller, and sd/mmc controller module has an integrated dma controller. for modules without an integrated dma controller, an additional dma controller module provides up to eight channels of high-bandwidth data transfers. peripherals that communicate off-chip are multiplexed with other peripherals at the hps pin level. this allows you to choose which peripherals to interface with other devices on your pcb. the debug access port provides interfaces to industry standard jtag debug probes and supports arm coresight debug and core traces to facilitate software development. cyclone v device overview altera corporation send feedback cv-51001 hps features 28 2013.12.26 fpga fabric hps hps-to-fpga lightweight hps-to-fpga fpga-to-hps fpga-to-hps sdram configuration controller fpga manager 64 kb on-chip ram 64 kb boot rom level 3 interconnect ethernet mac (2x) usb otg (2x) nand flash controller sd/mmc controller dma controller stm etr (trace) debug access port arm cortex-a9 mpcore mpu subsystem cpu0 arm cortex-a9 with neon/fpu, 32 kb instruction cache, 32 kb data cache, and memory management unit cpu1 arm cortex-a9 with neon/fpu, 32 kb instruction cache, 32 kb data cache, and memory management unit scu acp level 2 cache (512 kb) multiport ddr sdram controller with optional ecc peripherals (uart, timer, i 2 c, watchdog timer, gpio, spi, clock manager, reset manager, scan manager, system manager, and quad spi flash controller)
hpsCfpga axi bridges the hpsCfpga bridges, which support the advanced microcontroller bus architecture ( amba ? ) advanced extensible interface ( axi ? ) specifications, consist of the following bridges: ? fpga-to-hps axi bridgea high-performance bus supporting 32, 64, and 128 bit data widths that allows the fpga fabric to issue transactions to slaves in the hps. ? hps-to-fpga axi bridgea high-performance bus supporting 32, 64, and 128 bit data widths that allows the hps to issue transactions to slaves in the fpga fabric. ? lightweight hps-to-fpga axi bridgea lower latency 32 bit width bus that allows the hps to issue transactions to slaves in the fpga fabric. this bridge is primarily used for control and status register (csr) accesses to peripherals in the fpga fabric. the hpsCfpga axi bridges allow masters in the fpga fabric to communicate with slaves in the hps logic, and vice versa. for example, the hps-to-fpga axi bridge allows you to share memories instantiated in the fpga fabric with one or both microprocessors in the hps, while the fpga-to-hps axi bridge allows logic in the fpga fabric to access the memory and peripherals in the hps. each hpsCfpga bridge also provides asynchronous clock crossing for data transferred between the fpga fabric and the hps. hps sdram controller subsystem the hps sdram controller subsystem contains a multiport sdram controller and ddr phy that are shared between the fpga fabric (through the fpga-to-hps sdram interface), the level 2 (l2) cache, and the level 3 (l3) system interconnect. the fpga-to-hps sdram interface supports amba axi and avalon ? memory-mapped (avalon-mm) interface standards, and provides up to six individual ports for access by masters implemented in the fpga fabric. to maximize memory performance, the sdram controller subsystem supports command and data reordering, deficit round-robin arbitration with aging, and high-priority bypass features. the sdram controller subsystem supports ddr2, ddr3, or lpddr2 devices up to 4 gb in density operating at up to 400 mhz ( 800 mbps data rate). fpga configuration and processor booting the fpga fabric and hps in the soc are powered independently. you can reduce the clock frequencies or gate the clocks to reduce dynamic power, or shut down the entire fpga fabric to reduce total system power. you can configure the fpga fabric and boot the hps independently, in any order, providing you with more design flexibility: ? you can boot the hps independently. after the hps is running, the hps can fully or partially reconfigure the fpga fabric at any time under software control. the hps can also configure other fpgas on the board through the fpga configuration controller. ? you can power up both the hps and the fpga fabric together, configure the fpga fabric first, and then boot the hps from memory accessible to the fpga fabric. although the fpga fabric and hps are on separate power domains, the hps must remain powered up during operation while the fpga fabric can be powered up or down as required. note: altera corporation cyclone v device overview send feedback 29 hpsCfpga axi bridges cv-51001 2013.12.26
related information cyclone v device family pin connection guidelines provides detailed information about power supply pin connection guidelines and power regulator sharing. hardware and software development for hardware development, you can configure the hps and connect your soft logic in the fpga fabric to the hps interfaces using the qsys system integration tool in the quartus ii software. for software development, the arm-based soc devices inherit the rich software development ecosystem available for the arm cortex-a9 mpcore processor. the software development process for altera socs follows the same steps as those for other soc devices from other manufacturers. support for linux, vxworks ? , and other operating systems is available for the socs. for more information on the operating systems support availability, contact the altera sales team. you can begin device-specific firmware and software development on the altera soc virtual target. the virtual target is a fast pc-based functional simulation of a target development systema model of a complete development board that runs on a pc. the virtual target enables the development of device-specific production software that can run unmodified on actual hardware. related information altera worldwide sales support dynamic and partial reconfiguration the cyclone v devices support dynamic reconfiguration and partial reconfiguration (16) . dynamic reconfiguration the dynamic reconfiguration feature allows you to dynamically change the transceiver data rates, pma settings, or protocols of a channel, without affecting data transfer on adjacent channels. this feature is ideal for applications that require on-the-fly multiprotocol or multirate support. you can reconfigure the pma and pcs blocks with dynamic reconfiguration. partial reconfiguration partial reconfiguration is an advanced feature of the device family. if you are interested in using partial reconfiguration, contact altera for support. note: partial reconfiguration allows you to reconfigure part of the device while other sections of the device remain operational. this capability is important in systems with critical uptime requirements because it allows you to make updates or adjust functionality without disrupting services. apart from lowering cost and power consumption, partial reconfiguration increases the effective logic density of the device because placing device functions that do not operate simultaneously is not necessary. instead, you can store these functions in external memory and load them whenever the functions are required. this (16) partial reconfiguration is an advanced feature of the device family. if you are interested in using partial reconfiguration, contact altera for support. cyclone v device overview altera corporation send feedback cv-51001 hardware and software development 30 2013.12.26
capability reduces the size of the device because it allows multiple applications on a single devicesaving the board space and reducing the power consumption. altera simplifies the time-intensive task of partial reconfiguration by building this capability on top of the proven incremental compile and design flow in the quartus ii design software. with the altera ? solution, you do not need to know all the intricate device architecture details to perform a partial reconfiguration. partial reconfiguration is supported through the fpp x16 configuration interface. you can seamlessly use partial reconfiguration in tandem with dynamic reconfiguration to enable simultaneous partial reconfiguration of both the device core and transceivers. enhanced configuration and configuration via protocol cyclone v devices support 1.8 v , 2.5 v , 3.0 v , and 3.3 v programming voltages and several configuration modes. table 24: configuration modes and features supported by cyclone v devices remote system update partial reconfigura- tion (17) design security decompres- sion max data rate (mbps) max clock rate (mhz) data width mode yes yes yes 100 1 bit, 4 bits as through the epcs and epcq serial configura- tion device yes yes 125 125 1 bit ps through cpld or external microcontroller parallel flash loader yes yes 125 8 bits fpp yes yes yes 125 16 bits yes yes yes x1, x2, and x4 lanes cvp (pcie) 33 33 1 bit jtag instead of using an external flash or rom, you can configure the cyclone v devices through pcie using cvp. the cvp mode offers the fastest configuration rate and flexibility with the easy-to-use pcie hard ip block interface. the cyclone v cvp implementation conforms to the pcie 100 ms power-up-to-active time requirement. related information configuration via protocol (cvp) implementation in altera fpgas user guide provides more information about cvp. (17) partial reconfiguration is an advanced feature of the device family. if you are interested in using partial reconfiguration, contact altera for support. altera corporation cyclone v device overview send feedback 31 enhanced configuration and configuration via protocol cv-51001 2013.12.26
power management leveraging the fpga architectural features, process technology advancements, and transceivers that are designed for power efficiency, the cyclone v devices consume less power than previous generation cyclone fpgas: ? total device core power consumptionless by up to 40%. ? transceiver channel power consumptionless by up to 50%. additionally, cyclone v devices contain several hard ip blocks that reduce logic resources and deliver substantial power savings of up to 25% less power than equivalent soft implementations. document revision history changes version date ? corrected single or dual-core arm cortex-a9 mpcore processor-up to 925 mhz from 800 mhz. ? removed "preliminary" texts from ordering code figures, maximum resources, package plan and i/o vertical migration tables. ? removed the note "the number of gpios does not include transceiver i/os. in the quartus ii software, the number of user i/os includes transceiver i/os." for gpios in the maximum resource counts table for cyclone v e and se. ? added link to altera product selector for each device variant. 2014.12.26 december 2013 ? updated embedded hard ips for cyclone v gt devices to indicate maximum 2 hard pcie and 2 hard memory controllers. ? added leaded package options. ? removed the note "the number of plls includes general-purpose fractional plls and transceiver fractional plls." for all plls in the maximum resource counts table. ? corrected max lvds counts for transmitter and receiver for cyclone v e a5 device from 84 to 60. ? corrected max lvds counts for transmitter and receiver for cyclone v e a9 device from 140 to 120. ? corrected variable-precision dsp block, 27 x 27 multiplier, 18 x 18 multiplier adder mode and 18 x 18 multiplier adder summed with 36 bit input for cyclone v se devices from 58 to 84. ? corrected 18 x 18 multiplier for cyclone v se devices from 116 to 168. ? corrected 9 x 9 multiplier for cyclone v se devices from 174 to 252. ? corrected lvds transmitter for cyclone v se a2 and a4 as well as sx c2 and c4 devices from 31 to 32. ? corrected lvds receiver for cyclone v se a2 and a4 as well as sx c2 and c4 devices from 35 to 37. ? corrected transceiver speed grade for cyclone v st devices ordering code from 4 to 5. cyclone v device overview altera corporation send feedback cv-51001 power management 32 2013.12.26
changes version date ? updated the ddr3 sdram for the maximum frequency's soft controller and the minimum frequency from 300 to 303 for voltage 1.35v. ? added links to altera's external memory spec estimator tool to the topics listing the external memory interface performance. ? corrected xaui is supported through the soft pcs in the pcs features for cyclone v . ? added decompression support for the cvp configuration mode. ? added link to the known document issues in the knowledge base. ? moved all links to the related information section of respective topics for easy reference. ? corrected the title to the pcie hard ip topic. cyclone v devices support only pcie gen1 and gen2. ? updated supporting feature in table 1 of increased bandwidth capacity to ' 6.144 gbps '. 2013.05.06 may 2013 ? updated description in table 2 of low-power high-speed serial interface to ' 6.144 gbps '. ? updated description in table 3 of cyclone v gt to ' 6.144 gbps '. ? updated the m386 package to m383 for figure 1, figure 2 and figure 3. ? updated figure 2 and figure 3 for transceiver count by adding 'f : 4'. ? updated lvds in the maximum resource counts tables to include transmitter and receiver values. ? updated the package plan with m383 for the cyclone v e device. ? removed the m301 and m383 packages from the cyclone v gx c4 device. ? updated the gpio count to '129' for the m301 package of the cyclone v gx c5 device. ? updated 5 gbps to ' 6.144 gbps ' for cyclone v gt device. ? updated hps i/o for u484 (19 mm) in table 11 with '151' for a2, a4, a5 and a6. ? updated memory (kb) for maximum resource counts for cyclone v se a4 and a6, sx c4 and c6, st d6 devices. ? updated fpga pll for maximum resource counts for cyclone v se a2, sx c2, devices. ? removed '36 x 36' from the variable-precision dsp block. ? updated variable-precision dsp blocks and 18 x 18 multiplier for maximum resource counts for cyclone v sx c4 device. ? updated the hps i/o counts for cyclone v se, sx, and st devices. ? updated figure 7 which shows the i/o vertical migration table. ? updated table 17 for cyclone v sx c4 device. ? updated embedded memory capacity and distribution table for cyclone v se a4 and a6, sx c4 and c6, st d6 devices. ? removed 'counter reconfiguration' from the pll features. altera corporation cyclone v device overview send feedback 33 document revision history cv-51001 2013.12.26
changes version date ? updated low-power serial transceivers by replacing 5 gbps with 6.144 gbps . ? removed 'distributed memory' symbol. ? updated the capability in table 22 of backplane support to ' 6.144 gbps '. ? updated capability in table 22 of ring oscillator transmit plls with 6.144 gbps . ? updated the pcs support in table 23 from 5 gbps to ' 6 gbps '. ? updated the data rates (gbps) in table 23 of 3 gbps and 6 gbps basic to ' 6.144 gbps '. ? updated the data rates (gbps) in table 23 of cpri 4.1 to ' 6.144 gbps '. ? clarified that partial reconfiguration is an advanced feature. contact altera for support of the feature. ? updated the pin counts for the mbga packages. ? updated the gpio and transceiver counts for the mbga packages. ? updated the gpio counts for the u484 package of the cyclone v e a9, gx c9, and gt d9 devices. ? updated the vertical migration table for vertical migration of the u484 packages. ? updated the mlab supported programmable widths at 32 bits depth. 2012.12.28 december 2012 ? added new mbga packages and additional u484 packages for cyclone v e , gx, and gt. ? added ordering code for five-transceiver devices for cyclone v gt and st. ? updated the vertical migration table to add mbga packages. ? added performance information for hps memory controller. ? removed ddr3u support. ? updated cyclone v st speed grade information. ? added information on maximum transceiver channel usage restrictions for pci gen2 and cpri at 4.9152 gbps transmit jitter compliance. ? added note on the differences between gpio reported in overview with user i/o numbers shown in the quartus ii software. ? updated template. 2012.11.19 november 2012 added support for pcie gen2 x4 lane configuration (pcie-compatible) 2.1 july 2012 cyclone v device overview altera corporation send feedback cv-51001 document revision history 34 2013.12.26
changes version date ? restructured the document. ? added the embedded memory capacity and embedded memory configurations sections. ? added table 1, table 3, table 16, table 19, and table 20. ? updated table 2, table 4, table 5, table 6, table 7, table 8, table 9, table 10, table 11, table 12, table 13, table 14, table 17, and table 18. ? updated figure 1, figure 2, figure 3, figure 4, figure 5, figure 6, and figure 10. ? updated the fpga configuration and processor booting and hardware and software development sections. ? text edits throughout the document. 2.0 june 2012 ? updated table 1C2, table 1C3, and table 1C6. ? updated cyclone v family plan on page 1C4 and clock networks and pll clock sources on page 1C15. ? updated figure 1C1 and figure 1C6. 1.2 february 2012 ? updated table 1C1, table 1C2, table 1C3, table 1C4, table 1C5, and table 1C6. ? updated figure 1C4, figure 1C5, figure 1C6, figure 1C7, and figure 1C8. ? updated system peripherals on page 1C18, hpsCfpga axi bridges on page 1C19, hps sdram controller subsystem on page 1C19, fpga configuration and processor booting on page 1C19, and hardware and software development on page 1C20. ? minor text edits. 1.1 november 2011 initial release. 1.0 october 2011 altera corporation cyclone v device overview send feedback 35 document revision history cv-51001 2013.12.26

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