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summary datasheet ibm powerprs c48 advance common switch interface prsc48sds.00.fm september 9, 2002 general information page 1 of 12 general information features ? companion to the ibm powerprs ? 64gu packet routing switch chip csix interface attachment to the powerprs 64gu switch core csix-l1 interface: oc-48 adapter, compliant with the common switch interface specification - l1 dual-switch attachment for redundant switch- plane operation, including programmable scheduled switchover (packet lossless) and hot standby switchover redundant switch port attachment at 4 gbps using 2.5-gbps serial links compatible with infiniband ? physical layer standards supports 8 8, 16 16, 32 32, and 64 64 switch fabrics powerprs 64gu interface: 16- to 20-byte logical unit (lu) packet processing shared buffer capacity of up to 1024 ingress packets (512 per switch plane) and up to 256 egress packets (shared between switch planes) configurable number of traffic priorities (from one to four) packet header parity generation and checking end-to-end packet payload protection, with optional cyclic re dundancy check (crc) insertion programmable generation and detection of link- liveness messages in service packets eight-bit parallel processor interface to access all registers for control and error reporting internal loopback support for both the csix interface and switch interface internal logic built-in self-test (bist) and memory bist ieee ? standard 1149.1 bou ndary scan to facili- tate circuit-board testing cmos 7sf (sa-27e) technology (l drawn = 0.18 m, l eff = 0.11 m): ? 1.8-v core voltage ? 2.5-v lvcmos-compatible (3.3-v tolerant) i/os for the csix-l1 and microprocessor interfaces 25-mm, 360-ball ceramic ball grid array (cbga) package description the ibm powerprs c48 common switch interface is a companion device to the ibm powerprs 64gu packet routing switch. it functions as the switch core access layer between the protocol engine?s oc-48 csix interface and the switch core. the powerprs c48 switch in terface is comprised of two 2.5-gbps high-speed serializer/deserializer (hss) pairs that provide a total throughput of 5 gbps. the switch port payload throughput is only 4 gbps because of the fibre channel standard 8b/10b encoding on the hss links. the powerprs c48 attaches directly to the hss- compatible 64gu. when connected to the power- prs 64gu, the c48 packet length is programmable from 64 to 80 bytes, in 4-byte increments. ingress and egress packets are divided into four lus of 16 to 20 bytes each. the powerprs c48 provides attachment to a redundant switch fabric. two independent data paths (x and y) can be clocked, reset, and controlled separately to activate or deactivate each switch plane independently. powerprs c48 hard- ware-assist functions perform scheduled switchover without packet loss as well as asynchronous (or hot standby) switchover.
summary datasheet ibm powerprs c48 common switch interface advance general information page 2 of 12 prsc48sds.00.fm september 9, 2002 the powerprs c48 processes data traffic using one to four priorities, depending on register configuration. an in-band flow control mechanism, carried in the packet header, controls the traffic flow. in-band flow control is performed per priority and destination. when powerp rs c48 ingress traffic congestion occurs, flow control information is propagated through the csix interfac e to the protocol engine on the egress path. when protocol engine egress traffic congestion occurs, flow control information is transmitted in band to the powerprs c48 csix inte rface according to the csix-l1 specification . the powerprs c48 also features an optional out-of-band flow control mechanism. activation of either the in-band or out-of-band flow control mechanism is selected during powerprs c48 configuration. ordering information part number description throughput IBM3247P4448 ibm common switch interface 2.5 gbps
summary datasheet ibm powerprs c48 advance common switch interface prsc48sds.00.fm september 9, 2002 architecture page 3 of 12 architecture figure 1 illustrates the integration of a powerprs c48 in a 32-port 64gu redundan t switching system. an integrated high-speed serdes (hss) interface enables the powerprs c48 to directly connect to the 64gu switch core. the powerprs c48 supports the 64gu packet length of 64, 72, or 80 bytes. when attached to a powerprs 64gu master/slave pair, the c48 is used to build a 32-port switching system. with a 64-port desti- nation capability, the powerprs c48 will be able to accommodate next-genera tion powerprs switching systems. the attachment of a powerprs c48 to a redundant switch core allows the balancing of traffic loads between two switch planes. in addition, the powerprs c48 an d the 64gu can jointly execute scheduled switchover without packet loss. the powerprs c48 csix-l1 interface enables direct a ttachment to a 2.5-gbps protocol engine (32 bits wide). powerprs c48 ingress and egress data paths provide end-to-end flow control as well as access to a 64-k entry multicast table. the powerprs c48 multicast table is updated by either the switch local processor (in 64gu applications) or the c48 eight-bit parallel processor. the internal structure of the powerprs c48 is presented in figure 2 on page 4. figure 1. system view of the powerprs c48 with the 64gu (configured with redundant 128-gbps switch planes) x plane powerprs 64gu (active) oc-48 port adapter local processor switch core (n n) switch fabric 00 31 31 backplane protocol engine (egress) physical layer device two paired hsss powerprs c48 (egress) atm, sonet, or ethernet layer n protocol engine local processor y plane powerprs 64gu (backup) 00 31 31 oc-48 optical port protocol engine (ingress) physical layer device powerprs c48 (ingress) oc-48 optical port oc-48 port adapter csix-l1 data format csix-l1 data format 4 gbps
summary datasheet ibm powerprs c48 common switch interface advance architecture page 4 of 12 prsc48sds.00.fm september 9, 2002 ingress data flow ingress packets received from the protocol engine are color-coded and queued for transmission on either the x or y switch path. the powerprs c48 ingress buffer stores up to 1024 incoming packets (512 per switch plane), and implements programmable filtering to prevent packet duplication and wasted buffer space. packets are queued (or dequeued) using a first-in-first-out (fifo) mechanism per priority. the destination queue status (empty or occupied), packet priority, and ta rget switch output queue status flow control informa- tion are reported to the ingress scheduler. the ingres s scheduler uses a flywheel mechanism to select the next packet for transmission to the switch interface. the highest-priority packets of granted destinations are generally transmitted first. however, an ingress credit table can be programmed at system initialization to guarantee minimum bandwidth to low-priority packets. when activated via the corresponding register, the credit table alters the scheduler selection. alternativ ely, a flywheel weighted in favor of the low-priority packets can be used to offset the transmission of higher-priority packets. egress data flow egress packets received from the switch are queued by switch plane in up to eight output queues (4 priorities 2 switch planes) for transmission to the csix interface. the powerprs c48 egress buffer is shared between the x and y switch paths, and can store up to 256 outgoing packets. the egress queue status, packet priority, and csix port destination flow control information are reported to the egress sched- uler. the egress scheduler uses a flywheel mechanism to select the next packet for transmission to the csix interface. the highest-priority packets of granted de stinations are generally transmitted first, unless the egress credit table has been programmed to guarantee minimum bandwidth to low-priority packets. figure 2. powerprs c48 block diagram powerprs c48 2.5-gbps serial 2.5-gbps serial csix csix ingress data flow egress data flow output input 2 hsss 2 hsss hss interface packet processing and buffer management csix resynchro- nization hss interface packet processing and buffer management csix resynchro- nization powerprs 64gu protocol engine
summary datasheet ibm powerprs c48 advance common switch interface prsc48sds.00.fm september 9, 2002 programming interface and registers page 5 of 12 programming interface and registers the powerprs c48 employs an eight-bit parallel processor programming interface. this interface provides read/write access to all powerprs c48 internal registers and diagnostic functions, such as online error detection and reporting, and built-in self-test (bist). table 1 summarizes the registers that provide the mechanism for powerprs c48 configuration specification and status reporting. table 1. register summary (page 1 of 3) register name address access x plane y plane csix interface control registers csix mode control register x?00? read/write csix checking enable register x?01? read/write csix interface error/stat us register x?02? read/write csix interface error/status interrupt register x?06? read/write switch interface conf iguration registers switch interface system configuration 1 register x?74? x?b4? read/write switch interface system configuration 2 register x?64? x?a4? read/write switchover control register x?09? read/write hss synchronization 1 register x?c2? x?e2? read only hss synchronization 3 register x?c4? x?e4? read/write ingress data count register x?62? x?a2? read/clear egress data count register x?63? x?a3? read/clear hss control register x?c0? x?e0? read/write switch interface event/error register x?61? x?a1? read/clear switch interface interrupt register x?5a? x?9a? read/write switch interface checking enable register x?5b? x?9b? read/write payload crc error counter register x?40? x?80? read/clear yellow packet transmit counter register x?41? x?81? read/write yellow packet receive counter register x?42? x?82? read/write hss debug control register x?75? x?b5? read/write hss test register x?76? x?b6? read/write hss error 1 register x?c7? x?e7? read/write hss error 2 register x?c8? x?e8? read/write
summary datasheet ibm powerprs c48 common switch interface advance programming interface and registers page 6 of 12 prsc48sds.00.fm september 9, 2002 ingress byte-shuffling table register x?1c? read/write ingress byte-shuffling table byte location register x?1d? read/write egress byte-shuffling table register x?44? x?84? read/write egress byte-shuffling table byte loc ation register x?45? x?85? read/write flow control and packet scheduling control registers ingress credit table access register x?46? x?86? read/write egress credit table access register x?03? read/write ingress buffer flow control high threshold registers x?04? to x?05? read/write ingress buffer flow control low threshold registers x?07? to x?08? read/write ingress voq flow control high threshol d registers x?1e? to x?20? read/write ingress voq flow control low threshol d registers x?21? to x?23? read/write egress buffer flow control threshold registers x?0a? to x?0b? read/write ingress filter 1 registers x?47? to x?48? x?87? to x?88? read/write ingress filter 2 registers x?49? to x?4a? x?89? to x?8a? read/write ingress filter command register x?4b? x?8b? read/write internal status registers ingress queue status 1 register x?4c? x?8c? read/write ingress queue status 2 register (powerprs 64gu only) x?4d? x?8d? read/write ingress queue status selection register x?4e? x?8e? read/write egress queue status register x?4f? x?8f? read/write local multicast table access registers multicast table access 1 register x?10? read/write multicast table access 2 register x?11? read/write multicast table access 3 register (powerprs 64gu only) x?12? read/write internal resource monitoring registers ingress free buffer list register x?50? x?90? read/write egress free buffer list register x?13? read/write ingress link list register x?51? x?91? read/write ingress first-last table access register x?52? x?92? read/write egress link list 1 register x?14? read/write egress link list 2 register x?15? read/write table 1. register summary (page 2 of 3) register name address access x plane y plane
summary datasheet ibm powerprs c48 advance common switch interface prsc48sds.00.fm september 9, 2002 programming interface and registers page 7 of 12 egress first-last table acce ss register x?16? read/write ingress flow control register x?17? read/write egress flow control register x?18? read/write switch fabric environment status registers card/slot id register x?70? x?b0? read/write remote card availability 1 register x?71? x?b1? read only remote card availability 2 register (powerprs 64gu only) x?72? x?b2? read only clock configuration registers switch clock pll register x?73? x?b3? read/write switch clock pll observe register x?ca? x?ea? read only local clock pll register x?78? read/write local clock pll observe register x?1a? read only reset and test registers reset control register x?54? x?94? read/write memory bist status register x?26? read/write chip id register x?24? read only logic bist 1 register x?79? read/write test configuration register x?55? x?95? read/write internal hardware checking registers event 1 register x?56? x?96? read only event 1 mask register x?57? x?97? read/write event 1 interrupt enable register x?5e? x?9e? read/write event 2 register x?58? x?98? read only event 2 mask register x?59? x?99? read/write event 2 interrupt enable register x?5f? x?9f? read/write table 1. register summary (page 3 of 3) register name address access x plane y plane
summary datasheet ibm powerprs c48 common switch interface advance electrical information page 8 of 12 prsc48sds.00.fm september 9, 2002 electrical information table 2. absolute maximum ratings symbol parameter rating units minimum typical maximum v dd (1.8 v) power supply voltage 1.8 1.95 v v dd (2.5 v) power supply voltage for lvcmos-level signals 2.5 2.75 v t a operating ambient temperature -40 100 c t j operating junction temperature 0 125 c t s storage temperature -65 150 c electrostatic discharge 3000 v note: permanent device damage may occur if the above absolute maximu m ratings are exceeded. extended exposure to absolute maximum rating conditions may affect device reliability. table 3. recommended operating conditions symbol parameter rating units minimum typical maximum v dd (1.8 v) power supply voltage 1.71 1.8 1.89 v v dd (2.5 v) power supply voltage for lvcmos-level signals 2.375 2.5 2.625 v table 4. total power requirements core clock frequency (mhz) power (w) current (a) 1.8 v 2.5 v (lvcmos) typical maximum typical maximum typical maximum 166 10.312.04.955.760.520.60 table 5. thermal performance thermal resistance ( c/w) thermal resistance ja ( c/w) at air flow rate jc jb 0 lfpm 100 lfpm 200 lfpm 300 lfpm 400 lfpm 600 lfpm 0.51 3.5 14.1 12.7 11.5 10.4 9.6 8.5 notes: ja = junction-to-ambient thermal resistance jc = junction-to-case thermal resistance jb = junction-to-board thermal resist ance lfpm = linear feet per minute
summary datasheet ibm powerprs c48 advance common switch interface prsc48sds.00.fm september 9, 2002 electrical information page 9 of 12 figure 3. pinout (360-ball cbga package, top view) 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 a p b 1 1 1 1 1 c d 2 2 3 3 e f 1 1 1 1 g 2 2 3 3 h 2 1 1 1 1 1 3 j 2 2 3 3 k 1 1 1 1 l 5 5 4 4 m 5 1 1 1 1 1 4 n 5 5 4 4 p 1 1 1 1 r t 5 5 4 4 u v 1 1 1 1 1 p w p p i/o pin ground ac test dc test p dc test (pll) 1v dd (1.8 v) 2v dd2 (2.5 v) 3v dd3 (2.5 v) viewed through top of package 4v dd4 (2.5 v) 5v dd5 (2.5 v)
summary datasheet ibm powerprs c48 common switch interface advance mechanical information page 10 of 12 prsc48sds.00.fm september 9, 2002 mechanical information note: this document contains information on products in the design, sampling and/or initial production phases of development. this informat ion is subject to change without notice. verify with your ibm field applications engineer that you have the latest version of this document before finalizing a design. figure 4. package mechanical square 22.86 0.20 0.8 minimum package type is 360-ball cbga with dla, package size is 25 25 mm, and array size is 19 19. all dimensions are in millimeters. 01 18 19 17 16 15 14 13 12 08 11 10 09 07 06 05 04 03 02 bottom view 0.80 minimum 2.638 minimum top view 1.00 maximum 1.27 3.022 maximum 22.86 square vutrpnmlk jhgfe ba 2.25 direct lid attach (dla) w terminal a01 identifier no i/o pin at location a01 c d 25.00 0.20 square 25.00 square
summary datasheet ibm powerprs c48 advance common switch interface prsc48sds.00.fm september 9, 2002 revision log page 11 of 12 revision log revision date contents of modification sept. 9, 2002 initial release (00).
? copyright ? copyright international business machines corporation 2002 all rights reserved printed in the united states of america september 2002 the following are trademarks of the international business machines corporation in the united states, or other countries, or both. ibm powerprs ibm logo ieee is a registered trademark of the institute of electrical and electronics engineers (ieee). infiniband is a trademark of the infiniband trade association. other company, product, and service names ma y be trademarks or service marks of others. all information contained in this document is subject to ch ange without notice. the products described in this document are not intended for use in applications su ch as implantation, life support, or other hazardous uses where malfunction could result in death, bodily injury, or catastrophic property damage. the information contained in this document does not affect or change ibm product specifications or warranties. no thing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third partie s. all information contained in this docu- ment was obtained in specific environment s, and is presented as an illustration . the results obtained in other operating environments may vary. while the information contained herein is believed to be a ccurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representati ons or warranties of accuracy or completeness are made. the information contained in this document is prov ided on an ?as is? basis. in no event will ibm be liable for damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6351 the ibm home page can be found at http://www.ibm.com the ibm microelectronics division home page can be found at http://www.ibm.com/chips prsc48sds.00.fm september 9, 2002 note: this document contains information on products in the design, sampling and/or initial production phases of development. this information is subject to change without notice. verify with your ibm field applications engineer that you have the latest ve rsion of this document before finalizing a design.

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