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gm71vs65403cl 16,777,216 words x 4 bit cmos dynamic ram description features * 16,777,216 words x 4 bit * extended data out (edo) mode capability * fast access time & cycle time * power dissipation - active : 504mw/468mw(max) - standby : 1.8 mw ( cmos level : max ) 0.54 mw ( l-version : max) *edo page mode capability *access time : 50ns/60ns (max) *refresh cycles - ras only refresh 4096 cycles/64 ms (gm71v65403c) 4096 cycles/128ms (gm71vs65403cl)(l_version) *cbr & hidden refresh 4096 cycles/64 ms (gm71v65403c) 4096 cycles/128 ms (gm71vs65403cl)( l-version ) *4 variations of refresh -ras-only refresh -cas-before-ras refresh -hidden refresh -self refresh (l-version) *single power supply of 3.3v+/-10 % with a built-in vbb generator *battery back up operation ( l-version ) ( unit: ns) pin configuration the gm71v(s)65403c/cl is the new generation dynamic ram organized 16,777,216 words by 4bits. the gm71v(s)65403c/cl utilizes advanced cmos silicon gate process technology as well as advanced circuit techniques for wide operating margins, both internally and to the system user. system oriented features include single power supply of 3.3v+/-10% tolerance, direct interfacing capability with high performance logic families such as schottky ttl. the gm71v(s)65403c/cl offers extended data out(edo) mode as a high speed access mode. gm71v(s)65403c/cl-5 gm71v(s)65403c/cl-6 t rac t aa t rc t hpc 50 60 25 30 84 104 20 25 13 15 t cac 32 soj / tsop ii gm71v65403c nc ( top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vcc io0 io1 nc nc vcc / we / ras a0 a1 a2 a3 a4 a5 vcc 32 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 vss a6 a7 a8 a9 a10 a11 nc / oe / cas vss io2 io3 vss nc nc rev 0.1 / apr ? 01
pin description pin function pin function a0-a11 a0-a11 ras cas we v cc v ss nc address inputs refresh address inputs row address strobe column address strobe write enable power (+3.3v) ground no connection absolute maximum ratings* symbol parameter rating unit t stg v t v cc i out -55 to 125 -0.5 to v cc + 0.5 (max ; 4.6v) -0.5 to 4.6 50 storage temperature (plastic) voltage on any pin relative to v ss voltage on v cc relative to v ss short circuit output current c v v ma p t 1.0 power dissipation w * note : operation at or above absolute maximum ratings can adversely affect device reliability. recommended dc operating conditions (t a = 0 ~ 70c) symbol parameter unit v cc v ih v il supply voltage input high voltage input low voltage v v v max 3.6 vcc +0.3 0.8 typ 3.3 - - min 3.0 2.0 -0.3 oe output enable i/o0 - i/o3 data input / output ordering information type no. access time package gm71v(s)65403c/clj-5 gm71v(s)65403c/clj-66 50 ns 60ns 400 mil 32pin plastic soj gm71v(s)65403c/clt-5 gm71v(s)65403c/clt-6 50 ns 60ns 400 mil 32pin plastic tsop ii notes 1,2 1 1 v ss supply voltage v 0 0 0 2 t a 70 ambient temperature under bias c - 0 gm71vs65403cl gm71v65403c rev 0.1 / apr ? 01
dc electrical characteristics: (v cc = 3.3v+/-10%, t a = 0 ~ 70c) symbol parameter note v oh v ol output level output level voltage (i out = -2 ma ) unit v v max v cc 0.4 min 2.4 0 output level output level voltage (i out = 2 ma ) i cc1 140 - operating current ( t rc = t rc min) 50 ns ma 60 ns 130 - i cc2 ma standby current (ttl interface) power supply standby current (ras, cas= v ih , d out = high-z) 2 - i cc3 ma ras-only refresh current ( t rc = t rc min) i cc4 ma extended data out page mode current (ras = v il , cas, address cycling: t hpc = t hpc min) - 50 ns 60 ns - 110 - 50 ns 60 ns 100 - i cc6 ma cas-before-ras refresh current ( t rc = t rc min) - 50 ns 60 ns - i cc8 ma standby current (cmos) power supply standby current ras = v ih , cas = v il , d out = enable 5 - i i(l) 5 -5 i o(l) 5 -5 input leakage current, any input (0v<=v in <= vcc ) output leakage current (d out is disabled, 0v<=v out <= vcc ) note: 1. i cc depends on output load condition when the device is selected. i cc(max) is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. measured with one sequential address change per edo cycle, t hpc . 4. v ih >=v cc -0.2v, 0v<=v il <=0.2v 5. l-version 140 130 140 130 500 400 battery back up operating current(standby with cbr) ( trc =31.25us, tras =300ns, dout =high-z) self refresh current (ras, cas <=0.2v, dout =high-z) i cc7 i cc9 standby current(l_version) ua 300 - ua ma cmos interface (ras, cas>=v cc -0.2v, d out = high-z) 0.5 - - - i cc5 1,2 2 1 1,3 4, 5 ua ua ua 4 5 gm71vs65403cl gm71v65403c rev 0.1 / apr ? 01
symbol parameter note c i1 c i2 c i/o input capacitance (address) input capacitance (clocks) output capacitance (data-in,data-out) 1 1 1, 2 unit pf pf pf max 5 7 7 typ - - - note: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. ras, cas = v ih to disable d out . capacitance (v cc = 3.3v+/-10%, t a = 25c) read, write, read-modify-write and refresh cycles (common parameters) ac characteristics (v cc = 3.3v+/-10%, t a = 0 ~ 70c, notes 1, 2,19) test conditions input rise and fall times : 2ns output timing reference levels : v ol /v oh = 0.8/2.0v input level : v il /v ih = 0.0/3.0v output load : 1 ttl gate+c l (100 pf ) input timing reference levels : v il /v ih = 0.8/2.0v (including scope and jig) symbol parameter min gm71v(s)65403c/cl-5 max t rc random read or write cycle time t rp ras precharge time t ras ras pulse width t cas cas pulse width t asr row address set-up time t rah row address hold time t asc column address set-up time t cah column address hold time t rcd ras to cas delay time 4 t rad ras to column address delay time 3 t rsh ras hold time t csh cas hold time t crp cas to ras precharge time max min 84 104 40 60 10 0 10 0 10 14 12 15 40 5 30 50 8 0 8 0 8 12 10 13 35 5 - - - 25 37 - - - - 10000 - - - - 10000 - - - - 45 30 - - - unit notes ns ns ns ns ns ns ns ns ns ns ns ns ns t t transitiontime (rise and fall) 2 2 50 50 ns t odd oe to d in delay time t dzo oe delay time from d in t dzc cas delay time from d in 15 0 0 13 0 0 - - - - - - ns ns ns gm71v(s)65403c/cl-6 t cp cas precharge time 10 8 - - ns 10000 10000 5 6 6 7 t ref refresh period - - 64 64 ms refresh period ( l-version ) - - 128 128 ms 4096 cycles 4096 cycles gm71vs65403cl gm71v65403c rev 0.1 / apr ? 01
read cycles symbol parameter min gm71v(s)65403c/cl-5 gm71v(s)65403c/cl-6 max max min - - - - 0 0 0 30 - - 0 0 0 25 - - - 25 13 50 60 15 30 - - - unit notes ns ns ns ns ns ns ns ns - - t rac t cac t aa t rcs t rch t rrh t ral t cal access time from ras access time from cas access time from column address read command set-up time read command hold time to cas read command hold time to ras column address to ras lead time column address to cas lead time 8,9 t oac access time from oe - 13 - 15 ns 15 - 18 - 9,10,17 9,11,17 ns ns t rdd t wdd ras to d in delay time ns t ofr output buffer turn-off delay time from ras ns t wez output buffer turn-off delay time from we 13 13 - - 13 - 15 13 - 15 - 15 - - 15 - 13 ns ns ns t clz t oh t cdd cas to output in low - z output data hold time cas to d in delay time - 15 - ns ns t ohr t oez output data hold time from ras output buffer turn-off delay time from oe ns t off 0 3 - - 13 15 13 - 15 - - - 3 - - - - we to d in delay time 13,21 13 ns t rchr read command hold time from ras 50 - 60 - ns t oho output data hold time from oe 3 - 3 - 0 output buffer turn-off delay time from cas 12 9 12 13,21 13 3 3 21 5 21 gm71vs65403cl gm71v65403c rev 0.1 / apr ? 01
write cycles read-modify-write cycles t rwc read-modify-write cycle time t rwd ras to we delay time t cwd cas to we delay time t awd column address to we delay time refresh cycle symbol parameter min max max min 116 140 79 34 49 67 30 42 - - - - - - - - unit notes ns ns ns ns refresh cycles t csr cas set-up time (cas-before-ras refresh cycle) t chr cas hold time (cas-before-ras refresh cycle) t rpc ras precharge to cas hold time symbol parameter min max max min 5 5 - - unit notes ns 8 10 - - 5 5 - - ns ns t oeh oe hold time from we 15 13 - - ns 14 gm71v(s)65403c/cl-5 gm71v(s)65403c/cl-6 gm71v(s)65403c/cl-5 gm71v(s)65403c/cl-6 t wcs write command set-up time t wch write command hold time t wp write command pulse width t rwl write command to ras lead time t cwl write command to cas lead time t ds data-in set-up time t dh data-in hold time symbol parameter min max max min 0 0 10 10 10 0 10 8 8 8 0 8 - - - - - - - - - - - - unit notes ns ns ns ns ns ns ns - - 14 15 15 gm71v(s)65403c/cl-5 gm71v(s)65403c/cl-6 15 13 14 14 t wrp we setup time (cas-before-ras refresh cycle) 0 0 - - ns t wrh we hold time (cas-before-ras refresh cycle) 8 10 - - ns gm71vs65403cl gm71v65403c rev 0.1 / apr ? 01
extended data out mode cycles t hpc edo page mode cycle time t wpe write pulse width during cas precharge t rasp edo mode ras pulse width t acp symbol min max max min 20 25 10 - - 8 - - 28 100000 - - - - 35 unit notes ns ns ns ns parameter gm71v(s)65403c/cl-5 gm71v(s)65403c/cl-6 access time from cas precharge - ras hold time from cas precharge t cpw edo page mode read-modify-write cycle cas precharge to we delay time t hprwc 28 35 54 68 45 57 - - - - 100000 - ns ns ns - edo read-modify-write cycle time t rhcp t col cas hold time referred oe t cop 10 5 8 5 - - - - ns ns cas to oe set-up time read command hold time from cas precharge t doh output data hold time from cas low 28 35 - - ns ns t rchp 3 3 - - 20 9,17 self refresh cycles (l_version) t rass ras pulse width(self-refresh) t rps symbol parameter min max max min 100 - - unit notes gm71v(s)65403c/cl-5 gm71v(s)65403c/cl-6 t chs 100 ras precharge time(self-refresh) 90 - - ns 110 cas hold time(self-refresh) -50 - - ns -50 26 26 16 9,22 14 t oep oe precharge time ns 10 8 - - symbol min max max min unit notes parameter gm71v(s)65403c/cl-5 gm71v(s)65403c/cl-6 edo page mode read-modify-write cycle us gm71vs65403cl gm71v65403c rev 0.1 / apr ? 01
notes: ac measurements assume t t = 2 ns . ac initial pause of 200 us is required after power up followed by a minimum of eight initialization cycles ( any combination of cycles containing ras-only refresh or cas-before- ras refresh) operation with the t rcd ( max) limit insures that t rac ( max) can be met, t rcd ( max) is specified as a reference point only: if t rcd is greater than the specified t rcd ( max) limit, then access time is controlled exclusively by t cac . operation with the t rad ( max) limit insures that t rac ( max) can be met, t rad ( max) is specified as a reference point only: if t rad is greater than the specified t rad ( max) limit, then access time is controlled exclusively by t aa . either t oed or t cdd must be satisfied. either t dzo or t dzc must be satisfied. v ih ( min) and v il ( max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih ( min) and v il ( max). assumes that t rcd t rcd ( max) and t rad t rad ( max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. measured with a load circuit equivalent to 1 ttl loads and 100 pf . assumes that t rcd 3 t rcd ( max) and t rcd + t cac ( max) 3 t rad + t aa ( max). assumes that t rad 3 t rad ( max) and t rcd + t cac ( max) t rad + t aa ( max). either t rch or t rrh must be satisfied for a read cycles. t off ( max), t oez( max), t ofr ( max) and t wez ( max) define the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels. t wcs , t rwd , t cwd, t awd, and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only: if t wcs 3 t wcs ( min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if t rwd 3 t rwd ( min), t cwd 3 t cwd ( min), t awd 3 t awd ( min) and t cpw 3 t cpw ( min), the cycle is a read- modify-write and the data output will contain data read from the selected cell: if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. t ds and t dh are referred to cas leading edge in early write cycles and to we leading edge in delayed write or read-modify-write cycles. t rasp defines ras pulse width in extended data out mode cycles. access time is determined by the longest among t aa, t cac and t cpa . in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. when output buffers are enabled once, sustain the low impedance state until valid daa is obtained. when output buffer is turned on and off within a very short time, generally it causes large v cc / v ss line noise, which causes to degrade v ih min/v il max level. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. gm71vs65403cl gm71v65403c rev 0.1 / apr ? 01
t hpc ( min) can be achieved during a series of edo mode early write cycles or edo mode read cycles. if both write and read operation are mixed in a edo mode, ras cycle { edo mode mix cycle (1),(2) } minimum value of cas cycle t hpc ( t cas + t cp + 2 t t ) becomes greater than the specified t hpc ( min) value. data output turns off and becomes high impedance from later rising edge of ras and cas. hold time and turn off time are specified by the timing specifications of later rising edge of ras and cas between t ohr and t oh , and between t ofr and t off . t doh defines the time at which the output level go cross. v ol =0.8 v, v oh =2.0 v of output timing reference level. before and after self refresh mode, execute cbr refresh to all refresh addresses in or within 64 ms period on the condition a and b below. a. enter self refresh mode within 15.6 us after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. b. start burst refresh or distributed refresh at equal interval to all refresh addressed within 15.6 us after exiting from self refresh mode. in case of entering from ras-only-refresh, it is necessary to execute cbr refresh before and after self refresh mode according as note 23. for l_version, it is available to apply each 128 ms and 31.2 us instead of 64 ms and 15.6 us at note 23. at t rass > 100 us , self refresh mode is activated, and not active at t rass < 10 us it is undefined within the range of 10 us < t rass < 100 us . for t rass > 10 us , it is necessary to satisfy t rps . xxx: h or l ( h : v ih ( min) <= v in <= v ih ( max), l: v ih ( min) <= v in <= v ih ( max)) ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il. 20. 21. 22. 23. 24. 25. 26. 27. the value of cas cycle time of mixed edo page mode is shown in edo page mode mix cycle (1) and (2). gm71vs65403cl gm71v65403c rev 0.1 / apr ? 01
soj 32 pin pkg dimension unit: mm 21.38 max 20.95 min min 0.53 max 0.33 min 1.27 10.29 max 0.49 max 0.33 min 9.15 min 9.65 max 0.64 min 2.09 min 11.05 min 11.31 max 10.03 min 3.01 max 1.16 max 3.76 max 3.24 min 1.165 max 0.10 gm71vs65403cl gm71v65403c rev 0.1 / apr ? 01
tsopii 32 pin package dimension unit: mm normal type 10.16 21.35 max 20.95 min 0.42 0.08 1.27 0.18 max 0.08 min 0.60 max 0.40 min 0.125 0.04 0 ~ 5 o 0.145 0.05 1.15 max 0.40 0.06 1.20 max 0.10 11.96 max 11.56 min 0.80 0.68 dimension including the plating thickness base material dimension gm71vs65403cl gm71v65403c rev 0.1 / apr ? 01

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