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s3c9654/c9658/p9658 product overview 1- 1 1 product overview sam8 8rc ri product family samsung's sam88rcri family of 8-bit single-chi p cmos microcontrollers offer fast and efficient cpu, a wide range of integrated peripherals, and supports otp device . a dual address/data bus architecture and bit- or nibble-configurable i/o ports provide a flexible programming environment for applications with varied memory and i/o requirements. timer/counters with selectable operating modes are included t o support real-time operations. s3c9654/c9658/p9658 microcontroller the s3c9654/c9658/p9658 microcontroller with usb function can be used in a wide range of general purpose applications. it is especially suitable for mouse or joystick controller and is available in 16, 18, 20 -pin dip and so p package. the s3c9654/c9658/p9658 single-chip 8-bit microcontroller is fabricated using an advanced cmos process. it is built around the powerful sam88rcri cpu core. stop and idle power-down modes were implemented to reduce power consumption. to increase on-chip register space, the size of the internal register file was logically expanded. the s3c9654/c9658/p9658 has 4/8 kbytes of program memory on-chip (s3c9654/c9658), and 208 bytes of ram including 16 bytes of working register . using the sam 88rcri design approach, the following peripherals were integrated with the sam88rcri core: ? three configurable i/o ports (14 pin, at 20 pin ) ? 14-bit programmable pins for external interrupts (at 20 pin) ? 8-bit timer/counter with two operating modes otp the s3c9654/c9658 microcontroller is also available in otp (one time programmable) version. s3p9658 microcontroller has an on-chip 4/8 kbyte one-time-programmable eprom instead of masked rom. the s3p9658 is comparable to s3c9654/c9658 , both in function and in pin configuration.
product overview s3c9654/c9658/p9658 1- 2 features cpu sam88rcri cpu core memory 4 -k byte internal program memory (rom s3c9654 ) 8-k byte internal program memory (rom s3p9658/c9658 ) 208-b yte ram 16 bytes of working register instruction set 41 instructions idle and stop instructions added for power- down modes instruction execution time 0.66 m s at 6 mhz f osc interrupts 14 interrupt sources with one vector (20 pin) 12 interrupt sources with one vector (18 pin) 10 interrupt sources with one vector (16 pin) one level, one vector interrupt structure oscillation circuit options 6 mhz crystal/ceramic oscillator external clock source rc oscillator embedded oscillation capacitor (xi, xo, 33pf) general i/o 14 bit-programmable i/o pins (20 pin) 12 bit-programmable i/o pins (18 pin) 10 bit-programmable i/o pins (16 pin) sub oscillator internal rc sub oscillator auto interrupt wake-up timer/counter one 8-bit basic timer for watchdog function and programmable oscillation stabilization interval generation function one 8-bit timer/counter with compare/overflow counter usb serial bus compatible to usb low speed (1.5 mbps) device 1.0 specification. serial bus interface engine (sie) ? packet decoding/generation ? crc generation and checking ? nrzi encoding/decoding and bit-stuffing two 8-byte receive/transmit usb buffer operating temperature range ? 0 c to + 85 c operating voltage range 4. 0 v to 5.25 v package types 16, 18, 20 pin dip 16, 18, 20 pin sop comparator 6-channel mode, 32 step resolution 5-channel mode, external reference low emi design low voltage reset low voltage reset power on reset high sink current pin for led p0.0 (v ol : 0.4 v, 50ma)
s3c9654/c9658/p9658 product overview 1- 3 block diagram sam88rcri cpu port i/o and interrupt control 8k (4k) rom 208 byte ram sub osc basic timer timer 0 x in x out osc test reset not e: 16, 18, 20 dip and sop. lvr usb sie p2.1/d+/int2 p2.0/d-/int2 port 1/ compa -rator p1.0/cin0/int1 p1.1/cin0/int1 p1.2/cin0/int1 p1.3/cin0/int1 p1.4/cin0/int1 p1.5/cin0/int1 port 0 p0.2/int0 (note) p0.3/int0 (note) p0.4/int0 (note) p0.5/int0 (note) p0.0/int0 p0.1/int0 figure 1-1. block diagram
product overview s3c9654/c9658/p9658 1- 4 pin assignments s3c9654/ s3c9658 p0.3/int0 v dd p2.0/d-/int2 p2.1/d+/int2 reset x in x out test p0.1/int0 p0.5/int0 20 19 18 17 16 15 14 13 12 11 p0.2/int0 v ss p0.0/int0 p1.0/com0/int1 p1.1/com1/int1 p1.2/com2/int1 p1.3/com3/int1 p1.4/com4/int1 p1.5/com5/int1 p0.4/int0 1 2 3 4 5 6 7 8 9 10 p0.2/int0 v ss p0.0/int0 p1.0/com0/int1 p1.1/com1/int1 p1.2/com2/int1 p1.3/com3/int1 p1.4/com4/int1 p1.5/com5/int1 p0.4/int0 figure 1-2. pin assignment (20 pin )
s3c9654/c9658/p9658 product overview 1- 5 s3c9654/ s3c9658 p0.3/int0 v dd p2.0/d-/int2 p2.1/d+/int2 reset x in x out test p0.1/int0 18 17 16 15 14 13 12 11 10 p0.2/int0 v ss p0.0/int0 p1.0/com0/int1 p1.1/com1/int1 p1.2/com2/int1 p1.3/com3/int1 p1.4/com4/int1 p1.5/com5/int1 1 2 3 4 5 6 7 8 9 figure 1-3. pin assignment (18 pin) s3c9654/ s3c9658 v dd p2.0/d-/int2 p2.1/d+/int2 reset x in x out test p0.1/int0 16 15 14 13 12 11 10 9 v ss p0.0/int0 p1.0/com0/int1 p1.1/com1/int1 p1.2/com2/int1 p1.3/com3/int1 p1.4/com4/int1 p1.5/com5/int1 1 2 3 4 5 6 7 8 figure 1-4. pin assignment (16 pin)
product overview s3c9654/c9658/p9658 1- 6 table 1- 1 . signal descriptions pin names pin type pin description circuit number pin numbers share pins p0.0 i/o bit-programmable i/o port for schmitt trigger input or n- ch open drain output (50 ma). pull-up resistor is assignable to input pin by software and is automatically disabled for output pin. port 0 can be individually configured as external interrupt input. sk 3 int0 p0.1?p0.5 i/o bit-programmable i/o port for schmitt trigger input or push-pull output. pull-up resistors individually assignable to input pins by software and are automatically disabled for output pins. port 0 can be individually configured as external interrupt inputs. d 1, 10, 11, 12, 20 int0 p1.0?p1.5 i/o bit-programmable i/o port for schmitt trigger input or push-pull output. pull-up resistors are individually assignable to input pins by software. port 1 can be configured as comparator input or external interrupt inputs. pull-down resistors are individually assignable. (in comparator input) cp 4?9 cin0-5 int1 p2.0/d- ? p2.1/d+ i/o bit-programmable i/o port for schmitt trigger input or n- ch open drain output. pull-up resistors are individually assignable to input pins by software and are automatically disabled for output pins. port 2 can be individually configured as external interrupt inputs. also it can be configured as an usb ports. cp 17, 18 int2 x out , x in ? system clock input and output pin (crystal/ceramic oscillator, or external clock source) ? 14, 15 ? int 0 i external interrupt for bit-programmable port 0 d 1, 3, 10, 11, 12, 20 port 0 int1 i external interrupt for bit-programmable port 1 d 4?9 port 1 int2 i external interrupt for bit-programmable port 2 d 17, 18 port 2 v dd ? power input pin ? 19 ? v ss ? v ss is a ground power for cpu core. ? 2 ? reset 1 reset input pin (pull-up register embedded) ? 16 ?
s3c9654/c9658/p9658 product overview 1- 7 table 1- 2 . pin circuit assignments for the s3c9654/c9658/p9658 circuit number circuit type s3c9654/c9658/p9658 assignments c o d i/o port 0.1?5, int0, int1, int2 sk i/o port 0.0 cp i/o port 1, port 2 note : diagrams of circuit types c?d, and f-8 are presented below. p-channel n-channel v dd out output disable data figure 1-5. pin circuit type c i/o output disable data circuit type c pull-up enable v dd data figure 1-6. pin circuit type d
product overview s3c9654/c9658/p9658 1- 8 v ss pull-up registor v dd i/o pull-up enable output disable output data mode input data output input d0 d1 mux d0 d1 input data figure 1-7. pin circuit type sk i/o circuit type c v dd output disable data pull-up enable data input enable analog/ external v ref input d+/d- figure 1-8. pin circuit type cp
s3c9654/c9658/p9658 product overview 1- 9 dm1 s3c9654/ s3c9658/s3p9658 x i x out 14 v dd v ss 19 2 c_bulk + - p0.1/int0 p0.3/int0 20 p0.2/int0 1 15 12 17 p2.1/d+/int2 18 p2.0/d-/int2 p1.0/com0/int1 4 5 test reset (note) 13 16 p0.4/int0 p0.5/int0 10 11 6 7 8 9 t_z 3 v dd p0.0/int0 v ss v ss v ss sw1 sw3 sw2 button button button t_x t_y v dd v dd r_z d_z to host p1.1/com1/int1 p1.2/com2/int1 p1.3/com3/int1 p1.4/com4/int1 p1.5/com5/int1 v dd d_x d_y r_xy v ss v dd d- d+ x i note: reset pin is connected to internal pull-up register after power on reset. if reset pin is low, s3c9654/c9658/p9658 goes to reset. v ss figure 1-9. usb mouse circuit diagram
product overview s3c9654/c9658/p9658 1- 10 notes
s3c9654/c9658/p9658 address spaces 2- 1 2 address spaces overview the s3c9654/c9658/p9658 microcontroller has two kinds of address space: ? program memory (rom) ? internal register file a 13-bit address bus supports both program memory. special instructions and related internal logic determine when the 13-bit bus carries addresses for program memory. a separate 8 -bit register bus carries addresses and data between the cpu and the internal register file. the s3c9654/c9658 has 4/8 kbytes of mask-programmable program memory on-chip . the s3c9654/c9658/p9658 microcontroller has 192 bytes general-purpose registers in its internal register file. forty- eight bytes in the register file are mapped for system and peripheral control functions.
address spaces s3c9654/c9658/p9658 2- 2 program memory (rom) normal operating mode (internal rom) the s3c9654/c9658/p9658 has 4 /8 kbytes of internal mask-programmable program memory. the first 2 bytes of the rom (0000h? 0001h) are an interrupt vector address. the program reset address in the rom is 0100h. 4.096 256 1000h 0100h 0 4 k byte internal program memory area interrupt vector 1 2 0002h 0001h program start 0000h 8.192 256 2000h 0100h 0 8 k byte internal program memory area interrupt vector 1 2 0002h 0001h program start 0000h s3c9654 s3c9658/p9658 figure 2- 1. s3c9654/c9658/p9658 program memory address space
s3c9654/c9658/p9658 address spaces 2- 3 register architecture the upper 6 4 bytes of the s3c9654/c9658/p9658 's internal register file are addressed as working registers, system cont r ol registe r s and periphe r al control registers. the lower 192 bytes of internal register file (00h? b fh) is called the general purpose register space . for many sam88rcri microcontrollers, the addressable area of the internal register file is further expanded by the additional of one or more register pages at general purpose register space (00h?bfh). this register file expansion is not implemented in the s3c9654/c9658/p9658 . ffh c0h ~ bfh 00h 192 bytes 64 bytes of common area d0h cfh e0h dfh working registers system control registers peripheral control registers general purpose register file and stack area figure 2- 2 . internal register file organization
address spaces s3c9654/c9658/p9658 2- 4 common working register area (c0h?cfh) the sam88rcr i register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. this16-byte address range is called common area. that is, locations in this area can be used as working registers by operations that address any location on any page in the register file. typically, these working registers serve as temporary buffers for data operations between different pages. however, because the s3c9654/c9658/p9658 uses only page 0, you can use the common area for any internal data operation. the register (r) addressing mode can be used to access this area registers are addressed either as a single 8-bit register or as a paired 16-bit register. in 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. the most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register. msb rn lsb rn + 1 n = even address figure 2- 3 . 16-bit register pairs + + programming tip ? addressing the common working register area as the following examples show, you should access working registers in the common area, locations c0h?cfh, using working register addressing mode only. example s: 1. ld 0c2h,40h ; invalid addressing mode! use working register addressing instead: ld r2,40h ; r2 (c2h) ? the value in location 40h 2. add 0c3h,#45h ; invalid addressing mode! use working register addressing instead: add r3,#45h ; r3 (c3h) ? r3 + 45h
s3c9654/c9658/p9658 address spaces 2- 5 system stack ks86-series microcontrollers use the system stack for subroutine calls and returns and to store data. the push and pop instructions are used to control system stack operations. the s3c9654/c9658/p9658 architecture supports stack operations in the internal register file. stack operations return addresses for procedure calls and interrupts and data are stored on the stack. the contents of the pc are saved to stack by a call instruction and restored by the ret instruction. when an interrupt occurs, the contents of the pc and the flags register are pushed to the stack. the iret instruction then pops these values back to their original locations. the stack address is always decremented before a push operation and incremented after a pop operation. the stack pointer (sp) always points to the stack frame stored on the top of the stack, as shown in figure 2-4 . stack contents after a call instruction stack contents after an interrupt top of stack flags pch pcl pcl pch top of stack low address high address figure 2- 4 . stack operations stack pointer (sp) register location d9h contains the 8-bit stack pointer (sp) that is used for system stack operations. after a reset, the sp value is undetermined. because only internal memory space is implemented in the ks86c6104/p6104 , the sp must be initialized to an 8-bit value in the range 00h? b fh. note in case a stack pointer is initialized to 00h, it is decrea s ed to ffh when stack operation starts. this means that a stack pointer access invalid stack area.
address spaces s3c9654/c9658/p9658 2- 6 + + programming tip ? standard stack operations using push and pop the following example shows you how to perform stack operations in the internal register file using push and pop instructions: ld sp,#0c0h ; sp ? c0h (normally, the sp is set to 0c0h by the ; initialization routine) ? ? ? push sym ; stack address 0bfh ? sym push ccon ; stack address 0beh ? ccon push 20h ; stack address 0bdh ? 20h push r3 ; stack address 0bch ? r3 ? ? ? pop r3 ; r3 ? stack address 0bch pop 20h ; 20h ? stack address 0bdh pop ccon ; ccon ? stack address 0beh pop sym ; sym ? stack address 0bfh
s3c9654/c9658/p9658 addressing modes 3- 1 3 addressing modes overview instructions that are stored in program memory are fetched for execution using the program counter. instructions indicate the operation to be performed and the data to be operated on. addressing mode is the method used to determine the location of the data operand. the operands specified in sam88rc r i instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. the sam88rcri instruction set supports six explicit addressing modes. not all of these addressing modes are available for each instruction. the addressing modes and their symbols are as follows: ? register (r) ? indirect register (ir) ? indexed (x) ? direct addr ess (da) ? relative address (ra) ? immediate (im)
addressing modes s3c9654/c9658/p9658 3- 2 register addressing mode (r) in register addressing mode, the operand is the content of a specified register (see figure 3- 1). working register addressing differs from register a ddressing because it uses a 16- byte working register s pace in the register file and a 4-bit register within that space (see figure 3- 2). dst value used in instruction execution opcode operand 8-bit register file address point to one rigister in register file one-operand instruction (example) sample instruction: dec cntr ; where cntr is the label of an 8-bit register address program memory register file figure 3- 1 . register addressing dst opcode 4-bit working register point to the woking register (1 of 16) two-operand instruction (example) sample instruction: add r1, r2 ; where r1 = c1h and r2 = c2h program memory register file src 4 lsbs operand cfh c0h . . . . figure 3- 2 . working register addressing
s3c9654/c9658/p9658 addressing modes 3- 3 indirect register addressing mode (ir) in indirect register (ir) addressing mode, the content of the specified register or register pair is the address of the operand. depending on the instruction used, the actual address may point to a register in the register file, to program memory (rom), or to an external memory space (see figures 3- 3 through 3- 6). you can use any 8-bit register to indirectly address another register. any 16-bit register pair can be used to indirectly address another memory location. 8-bit register file address one-operand instruction (example) dst address of operand used by instruction opcode address point to one rigister in register file sample instruction: rl @shift ; where shift is the label of an 8-bit register address program memory register file value used in instruction execution operand figure 3- 3 . indirect register addressing to register file
addressing modes s3c9654/c9658/p9658 3- 4 indirect register addressing mode ( c ontinued ) dst opcode pair points to rigister pair example instruction references program memory sample instructions: call @rr2 jp @rr2 program memory register file value used in instruction operand register program memory 16-bit address points to program memory figure 3- 4 . indirect register addressing to program memory
s3c9654/c9658/p9658 addressing modes 3- 5 indirect register addressing mode (c ontinued ) dst opcode operand 4-bit working register address point to the woking register (1 of 16) sample instruction: or r6, @r2 program memory register file src 4 lsbs value used in instruction operand cfh c0h . . . . figure 3- 5 . indirect working register addressing to register file
addressing modes s3c9654/c9658/p9658 3- 6 indirect register addressing mode (c oncluded ) dst opcode 4-bit working register address sample instructions: lcd r5,@rr6 ; program memory access lde r3,@rr14 ; external data memory access lde @rr4, r8 ; external data memory access program memory register file src value used in instruction operand example instruction references either program memory or data memory program memory or data memory next 3 bits point to working register pair (1 of 8) lsb selects register pair 16-bit address points to program memory or data memory cfh . . . . c0h figure 3- 6 . indirect working register addressing to program or data memory
s3c9654/c9658/p9658 addressing modes 3- 7 indexed addressing mode (x) indexed (x) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see figure 3- 7). you can use indexed addressing mode to access locations in the internal register file or in external memory. in short offset indexed addressing mode, the 8- bit displacement is treated as a signed integer in the range of ?128 to +127. this applies to external memory accesses only (see figure 3- 8). for register file addressing, an 8-b it base address provided by the instruction is added to an 8-bit offset contained in a working register. for external memory accesses, the base address is stored in the working register pair designated in the instruction. the 8-bit or 16-bit offset given in the instruction is then added to the base address (see figure 3- 9). the only instruction that supports indexed addressing mode for the internal register file is the load instruction (ld). the ldc and lde instructions support indexed addressing mode for internal program memory, external program memory, and for external data memory, when implemented. dst opcode two-operand instruction example point to one of the woking register (1 of 16) sample instruction: ld r0, #base[r1] ; where base is an 8-bit immediate value program memory register file 4 lsbs value used in instruction operand index base address ~ ~ ~ ~ + src figure 3- 7 . indexed addressing to register file
addressing modes s3c9654/c9658/p9658 3- 8 indexed addressing mode (c ontinued ) point to working register pair (1 of 8) lsb selects 16-bit address added to offset dst opcode program memory xs (offset) 4-bit working register address sample instructions: ldc r4, #04h[rr2] ; the values in the program address (rr2 + #04h) are loaded into register r4. lde r4,#04h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 3 bits register pair src 8-bits 16-bits + program memory or datamemory operand value used in instruction 16-bits register file figure 3- 8 . indexed addressing to program or data memory with short offset
s3c9654/c9658/p9658 addressing modes 3- 9 indexed addressing mode (c oncluded ) point to working register pair (1 of 8) lsb selects 16-bit address added to offset program memory 4-bit working register address sample instructions: ldc r4, #1000h[rr2] ; the values in the program address (rr2 + #1000h) are loaded into register r4. lde r4, #1000h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 3 bits register pair 8-bits 16-bits + program memory or datamemory operand value used in instruction 16-bits register file opcode xl h (offset) xl l (offset) dst src figure 3- 9 . indexed addressing to program or data memory with long offset
addressing modes s3c9654/c9658/p9658 3- 10 direct address mode (da) in direct address (da) mode, the instruction provides the operand's 16-bit memory address. jump (jp) and call (call) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the pc whenever a jp or call instruction is executed. the ldc and lde instructions can use direct address mode to specify the source or destination address for load operations to program memory (ldc) or to external data memory (lde), if implemented. sample instructions: ldc r5,1234h ; the values in the program address (1234h) are loaded into register r5. lde r5,1234h ; identical operation to ldc example, except that external program memory is accessed. dst/src opcode program memory "0" or "1" lower address byte lsb selects program memory or data memory: "0" = program memory "1" = data memory memory address used upper address byte program or data memory figure 3- 10 . direct addressing for load instructions
s3c9654/c9658/p9658 addressing modes 3- 11 direct address mode (c ontinued ) opcode program memory upper address byte program memory address used lower address byte sample instructions: jp c,job1 ; where job1 is a 16-bit immediate address call display ; where display is a 16-bit immediate address next opcode figure 3- 11 . direct addressing for call and jump instructions
addressing modes s3c9654/c9658/p9658 3- 12 relative address mode (ra) in relative address (ra) mode, a two's-complement signed displacement between ? 128 and + 127 is specified in the instruction. the displacement value is then added to the current pc value. the result is the address of the next instruction to be executed. before this addition occurs, the pc contains the address of the instruction immediately following the current instruction. the instructions that support ra addressing is jr. opcode program memory displacement program memory address used sample instructions: jr ult,$ + offset ; where offset is a value in the range + 127 to - 128 next opcode + signed displacement value current instruction current pc value figure 3- 12 . relative addressing immediate mode (im) in immediate (im) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. immediate addressing mode is useful for loading constant values into registers. (the operand value is in the instruction) opcode sample instruction: ld r0,#0aah program memory operand figure 3- 13 . immediate addressing
s3c9654/c9658/p9658 control registers 4- 1 4 control registers overview in this section, detailed descriptions of the s3c9654/c9658/p9658 control registers are presented in an easy-to- read format. these descriptions will help familiarize you with the mapped locations in the register file. you can also use them as a quick-reference source when writing application programs. system and peripheral registers are summarized in table 4- 1. figure 4- 1 illustrates the important features of the standard register description format. control register descriptions are arranged in alphabetical order according to register mnemonic. more information about control registers is presented in the context of the various peripheral hardware descriptions in part ii of this manual.
control registers s3c9654/c9658/p9658 4- 2 table 4- 1. sys tem and peripheral c ontrol registers register name mnemonic hex r/w general purpose register file & stack area ? 00-bfh r/w working register area ? c0h-cfh r/w timer 0 counter register t0cnt d0h r timer 0 data register t0data d1h r/w timer 0 control register t0con d2h r/w location d3h is not mapped. clock cont r ol register clkcon d4h r/w system flag register flags d5h r/w locations d6h?d 8 h are not mapped. stack pointer sp d9h r/w location s dah? dbh are not mapped. basic timer control register btcon dch r/w basic timer counter btcnt ddh r location deh is not mapped. system mode register sym dfh r/w port 0 data register p0 e0h r/w port 1 data register p1 e1h r/w port 2 data register p2 e2h r/w port 1 pull-down control pdcon e3h r/w comparator control mode register ccon e4h r/w comparison result register cdata e5h r port 0 low nibble control register p0conl e6h r/w port 0 high nibble control register p0conh e7h r/w port 1 high nibble control register p1conh e8h r/w port 1 low nibble control register p1conl e9h r/w port 0 interrupt control register p0int eah r/w port 0 interrupt pending register p0pnd ebh r/w port 1 interrupt control register p1int ech r/w port 1 interrupt pending register p1pnd edh r/w port 2 control/interrupt control and pending register p2conint eeh r/w sub oscillator control register subcon efh r/w
s3c9654/c9658/p9658 control registers 4- 3 table 4- 1. sys tem and peripheral c ontrol registers (continued) register name mnemonic hex r/w usb function address register faddr f0h r/w control endpoint status register ep0csr f1h r/w interrupt endpoint status register ep1csr f2h r/w control endpoint byte count register ep0bcnt f3h r control endpoint fifo register ep0fifo f4h w interrupt endpoint fifo register ep1fifo f5h w usb interrupt pending register usbpnd f6h r/w usb interrupt enable register usbint f7h r/w usb power management register pwrmgr f8h r/w locations f9h is not mapped locations fah is not mapped usb mode select register usbsel fbh r/w locations fch is not mapped sink current control register snkcon fdh r/w usb signal control xcon feh r/w usb reset register usbrst ffh r/w notes: 1 . reset = value notation 2. ?_? = not used. 3. ?x? = undetermind value .
control registers s3c9654/c9658/p9658 4- 4 flags - system flags register .7 .6 .5 bit identifier reset reset value read/write r = read-only w = write-only r/w = read/write ' - ' = not used bit number: msb = bit 7 lsb = bit 0 addressing mode or modes you can use to modify register values description of the effect of specific bit settings reset value notation: '-' = not used 'x' = undetermind value '0' = logic zero '1' = logic one bit number(s) that is/are appended to the register name for bit addressing d5h register address (hexadecimal) full register name register mnemonic name of individual bit or bit function .7 .6 .5 .4 .2 .3 .1 .0 x r/w x r/w x r/w x r/w 0 r/w x r/w 0 r/w x r/w carry flag (c) 0 operation dose not generate a carry or borrow condition 1 operation generates carry-out or borrow into high-order bit7 zero flag 0 operation result is a non-zero value 1 operation result is zero sign flag 0 operation generates positive number (msb = "0") 1 operation generates negative number (msb = "1") figure 4-1. register description format
s3c9654/c9658/p9658 control registers 4- 5 btc on ? basic timer co ntrol register dch bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 ? .4 watchdog timer en able bits 1 0 1 0 disable watchdog function any other value enable watchdog function .3 ? .2 basic timer input clock selection bits 0 0 f osc /4096 0 1 f osc /1024 1 0 f osc /128 1 1 non divided ( f osc ) .1 basic timer counter clear bit ( note ) 0 no effect 1 clear btcnt .0 basic timer divider clear bit ( note ) 0 no effect 1 clear both dividers note: when you write a "1" to btcon.0 (o r btcon.1), the basic timer counter (or basic timer divider) is cleared. the bit is then cleared automatically to "0".
control registers s3c9654/c9658/p9658 4- 6 ccon ? comparator mode register e4 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 comparator enable bit 0 disable comparator 1 enable comparator .6 conversion time 0 conversion time (6 192/fx) 1 conversion time (4 12/fx) .5 external reference voltage 0 internal reference voltage 1 external reference voltage .4 ? .0 reference voltage ( vref) selection v dd (n + 0.5)/24, n = 0 to 7 v dd (0.3125 + (n ? 7)/48), n = 8 to 23 v dd (0.6458 + (n ? 23)/24), n = 24 to 31
s3c9654/c9658/p9658 control registers 4- 7 clkcon ? system clock control register d4h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 ? ? 0 0 ? ? ? read/write r/w ? ? r/w r/w ? ? ? .7 oscillator irq wake-up function bit 0 enable irq for main system oscillator wake-up in power down mode 1 disable irq for main system oscillator wake-up in power down mode .6 and .5 not used for s3c9654/c9658/p9658 .4 and .3 cpu clock (system clock) selection bits 0 0 divide by 16 (f osc /16) 0 1 divide by 8 (f osc /8) 1 0 divide by 2 (f osc /2) 1 1 non-divided clock (f osc ) .2 ? .0 not used for s3c9654/c9658/p9658
control registers s3c9654/c9658/p9658 4- 8 ep0csr ? control endpoint status register f1 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 setup_end clear bit 0 no effect (when write) 1 clear setup_end (bit4) bit .6 out_pkt_rdy clear bit 0 no effect (when write) 1 clear out_pkt_rdy (bit0) bit .5 stall signal sending bit 0 no effect (when write) 1 send stall signal to host .4 setup transfer end bit 0 no effect (when write) 1 sie sets this bit when a control transfer ends before data_end (bit3) is set . 3 setup data end bit 0 no effect (when write) 1 mcu set this bit after loading or unloading the last packet data into the fifo . 2 stall signal receive bit 0 mcu clear this bit to end the stall condition 1 sie sets this bit if a control transaction is ended due to a protocol violation . 1 in packet ready bit 0 sie clear this bit once the packet has been successfully sent to the host 1 mcu sets this bit after writing a packet of data into endpoint0 fifo . 0 out packet ready bit 0 no effect (when write) 1 sie sets this bit once a valid token is written to the fifo
s3c9654/c9658/p9658 control registers 4- 9 ep1csr ? interrupt endpoint status register f2 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 data_toggle clear bit 0 no effect (when write) 1 clears the data toggle sequence bit .6 ? .3 maximum packet size bits 0 no effect (when write) 1 indicates the maximum packet size for interrupt endpoint . 2 fifo flush bit 0 no effect (when write) 1 fifo is flushed, and in_pkt_rdy cleared . 1 force stall bit 0 mcu clears this bit to end the stall condition 1 issues a stall handshake to usb . 0 in packet ready bit 0 sie clear this bit once the packet has been successfully sent to the host 1 mcu sets this bit after writing a packet of data into endpoint1 fifo
control registers s3c9654/c9658/p9658 4- 10 flags ? system flags register d5h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 ? ? ? ? read/write r/w r/w r/w r/w ? ? ? ? .7 carry flag (c) 0 operation does not generate a carry or borrow condition .6 zero flag (z) 0 operation result is a non-zero value 1 operation result is zero .5 sign flag (s) 0 operation generates a positive number (msb = "0") 1 operation generates a negative number (msb = "1") .4 overflow flag (v) 0 operation result is +127 or 3 ?128 1 operation result is 3 +127 or ?128 .3 ? .0 not used for s3c9654/c9658/p9658
s3c9654/c9658/p9658 control registers 4- 11 p0conh ? port 0 control register (high byte) (e7 h , r/w) bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7 ? .4 not used for s3c9654/c9658/p9658 .3 and .2 port 0.5 configuration control bits 0 0 schmitt trigger input, rising edge external interrupt. 0 1 schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 output mode, push-pull 1 1 not used .1 and .0 port 0.4 configuration control bits 0 0 schmitt trigger input, rising edge external interrupt. 0 1 schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 output mode, push-pull 1 1 not used
control registers s3c9654/c9658/p9658 4- 12 p0conl ? port 0 control register ( low byte) (e6 h , r/w) bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 0.3 configuration control bits 0 0 schmitt trigger input, rising edge external interrupt. 0 1 schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 output mode, push-pull 1 1 not used .5 and .4 port 0.2 configuration control bits 0 0 schmitt trigger input, rising edge external interrupt. 0 1 schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 output mode, push-pull 1 1 not used .3 and .2 port 0.1 configuration control bits 0 0 schmitt trigger input, rising edge external interrupt. 0 1 schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 output mode, push-pull 1 1 not used .1 and .0 port 0.0 configuration control bits 0 0 input, rising edge external interrupt. 0 1 input, falling edge external interrupt with pull-up resistor 1 0 output mode, n- ch open drain 1 1 not used
s3c9654/c9658/p9658 control registers 4- 13 p 0int ? port 0 interrupt control register (ea h , r/w) bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? 0 0 0 0 0 0 read/write ? ? r/w r/w r/w r/w r/w r/w .7 and .6 not used for s3c9654/c9658/p9658 .5 ? .0 p0.5-p0.0 interrupt enable bits 0 external interrupt disable 1 external interrupt enable p0 pnd ? port 0 interrupt pending register (eb h , r/w) bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? 0 0 0 0 0 0 read/write ? ? r/w r/w r/w r/w r/w r/w .7 and .6 not used for s3c9654/c9658/p9658 .5 ? .0 p0.5-p0.0 interrupt pending bit 0 no pending (when read) /clear pending bit (when write) 1 p ending (when read) /no effect (when write)
control registers s3c9654/c9658/p9658 4- 14 p1conh ? port 1 control register (high byte) ( e8h , r/w) bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7 ? .4 not used for s3c9654/c9658/p9658 .3 and .2 port 1.5 configuration control bits 0 0 schmitt trigger input, rising edge external interrupt. 0 1 schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 o utput mode, push-pull 1 1 comparator input, analog input, (external reference voltage input) .1 and .0 port 1.4 configuration control bits 0 0 schmitt trigger input, rising edge external interrupt. 0 1 schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 o utput mode, push-pull 1 1 comparator input, analog input
s3c9654/c9658/p9658 control registers 4- 15 p1conl ? port 1 control register (low byte) e9h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 1.3 configuration control bits 0 0 schmitt trigger input, rising edge external interrupt. 0 1 schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 output mode, push-pull 1 1 comparator input, analog input .5 and .4 port 1.2 configuration control bits 0 0 schmitt trigger input, rising edge external interrupt. 0 1 schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 output mode, push-pull 1 1 comparator input, analog input .3 and .2 port 1.1 configuration control bits 0 0 schmitt trigger input, rising edge external interrupt. 0 1 schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 output mode, push-pull 1 1 comparator input, analog input .1 and .0 port 1.0 configuration control bits 0 0 schmitt trigger input, rising edge external interrupt. 0 1 schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 output mode, push-pull 1 1 comparator input, analog input
control registers s3c9654/c9658/p9658 4- 16 p1 int ? port 1 interrupt control register ( ech , r/w) bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? 0 0 0 0 0 0 read/write ? ? r/w r/w r/w r/w r/w r/w .7 and .6 not used for s3c9654/c9658/p9658 .5 ? .0 p 1.0-p1.5 interrupt enable bit 0 external interrupt disable 1 external interrupt enable p 1 pnd ? port 1 interrupt pending register edh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? 0 0 0 0 0 0 read/write ? ? r/w r/w r/w r/w r/w r/w .7 and .6 not used for s3c9654/c9658/p9658 .5 ? .0 p 1 .7 interrupt pending bit 0 no pending (when read) /clear pending bit (when write) 1 p ending (when read) /no effect (when write)
s3c9654/c9658/p9658 control registers 4- 17 p2conint ? port 2 control/interrupt control and pending register ee h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 2.1 configuration control bits 0 0 shcmitt trigger input, falling edge external interrupt 0 1 shcmitt trigger input, falling edge external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .5 and .4 port 2.0 configuration control bits 0 0 shcmitt trigger input, falling edge external interrupt 0 1 shcmitt trigger input, falling edge external interrupt with pull-up 1 0 n-ch open drain output mode 1 1 n-ch open drain output mode with pull-up .3 and .2 p2.1-p2.0 interrupt enable bit 0 external interrupt disable 1 external interrupt enable .1 and .0 p2.1-p2.0 interrupt pending bit 0 no pending (when read)/clear pending bit (when write) 1 pending (when read)/no effect (when write)
control registers s3c9654/c9658/p9658 4- 18 pdcon ? port 1 pull-down resistor control (e3h, r/w) bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7 ? . 4 not used for s3c9654/c9658/p9658 .3 "1" = pull-down enable,"0" pull-down disable when p1 comparator input mode. .2 ? .0 select pull-down resistor value from 5 k w ?19 k w 2 k w /bit weight at v port = 2.5 v. "0 08" = 19 k w "0 0f" = 5 k w , when v port = 2.5 v pwrmgr ? usb power management register (f8h) bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 ? . 2 always logic zero .1 resume signal sending bit 0 resume signal is ended 1 while in suspend state, if the mcu wants to initiate a resume, it writes a 1 to this register for 10 ms (maximum of 15 ms), and clears this register. in suspend mode, if this bit is set to ?1?, usb generates resume signaling. .0 suspend status bit 0 cleared automatically when mcu writes a zero to resume signal sending bit or when function receives resume signal from the host while in suspend mode 1 this bit is set when suspend interrupt occur
s3c9654/c9658/p9658 control registers 4- 19 snkcon ? sink current control register (fdh, r/w) bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? ? 0 0 read/write ? ? ? ? ? ? r/w r/w .7 ? . 2 not used for s3c9654/c9658/p9658 .1 ? .0 select sink current of the port 0.0 n- ch open drain. "0x00" = 30 ma, "0x01" = 40 ma, "0x02" = 50 ma, :"0x03": = 60 ma when v port = 0.4 v
control registers s3c9654/c9658/p9658 4- 20 subcon ? sub_oscillator control (efh, r/w) bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? 0 ? ? 0 0 0 0 read/write ? r/w ? ? r/w r/w r/w r/w .7 not used for s3c9654/c9658/p9658 .6 sub_oscillator interrupt pending bit 0 no pending (when read)/clear pending (when write) 1 pending (when read)/no effect (when write) .5 ? .4 not used for s3c9654/c9658/p9658 .3 sub_oscillator interrupt enable bit 0 sub_oscillator disable, interrupt disable 1 sub_oscillator enable, interrupt enable .2 and .0 sub_oscillator counter input clock selection bits 0 0 0 f osc /2048 0 0 1 f osc /3072 0 1 0 f osc /4096 0 1 1 f osc /6144 1 0 0 f osc /8192 1 0 1 f osc /12288 1 1 0 f osc /16384 1 1 1 f osc /24576 note: f osc = 130 khz ( typ.) when v dd = 5.0 v, t a = 25 c.
s3c9654/c9658/p9658 control registers 4- 21 sym ? system mode register ( dfh , r/w) bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7 ? .4 not used for s3c9654/c9658/p9658 .3 global interrupt enable bit 0 g lobal interrupt processing disable 1 g lobal interrupt processing enable .2 and .0 page select bit 0 0 0 page 0 0 0 1 page 1 (not allowed in s3c9654/c9658/p9658) 0 1 0 page 2 (not allowed in s3c9654/c9658/p9658) 0 0 1 page 3 (not allowed in s3c9654/c9658/p9658)
control registers s3c9654/c9658/p9658 4- 22 t0con ? timer 0 control register d2h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 t0 counter input clock selection bits 0 0 f osc /4096 0 1 f osc /256 1 0 f osc / 8 1 1 not used for s3c9654/c9658/p9658 .5 and .4 t0 operating mode selection bits 0 0 interval timer mode ( the counter is automatically cleared when ever t0data value equals to t0cnt value ) 0 1 invalid selection 1 0 1 1 overflow mode (ovf interrupt can occur) .3 t0 counter clear bit (t0clr) 0 no effect 1 clear t0 counter (when write) .2 t0 overflow interrupt enable bit (t0ovf) 0 disable t0 overflow interrupt 1 enable t0 overflow interrupt .1 t0 match interrupt enable bit (t0int) 0 disable t0 match interrupt 1 enable t0 match interrupt .0 t0 interrupt pending bit (t0pnd) 0 no interrupt pending (when read)/ clear this pending bit (when write) 1 interrupt is pending(when read)/no effect(when write) note : when you write a "1" to t 0 con. 3, the timer 0 counter is cleared. the bit is then cleared automatically to "0".
s3c9654/c9658/p9658 control registers 4- 23 usbint ? usb interrupt enable register f7h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? 0 1 1 read/write ? ? ? ? ? r/w r/w r/w .7 ? . 3 not used for s3c9654/c9658/p9658 .2 suspend/resume interrupt enable bit 0 disable suspend and reseme interrupt (default) 1 enable suspend and reseme interrupt .1 endpoint1 interrupt pending bit 0 disable endpoint 1 interrupt 1 enable endpoint 1 interrupt (default) .0 endpoint0 interrupt pending bit 0 disable endpoint 0 interrupt 1 enable endpoint 0 interrupt (default)
control registers s3c9654/c9658/p9658 4- 24 usbpnd ? usb interrupt pending register f6h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7 ? . 4 not used for s3c9654/c9658/p9658 .3 resume interrupt pending bit 0 no effect (once read, this bit is cleared automatically) 1 this bit is set, if resume signaling is received while in suspend mode .2 suspend interrupt pending bit 0 no effect (once read, this bit is cleared automatically) 1 this bit is set, when suspend signaling is received .1 endpoint1 interrupt pending bit 0 no effect (once read, this bit is cleared automatically) 1 this bit is set, when endpoint1 needs to be serviced .0 endpoint0 interrupt pending bit 0 no effect (once read, this bit is cleared automatically) 1 this bit is set, while endpoint 0 needs to serviced. it is set under the following conditions: ? out_pkt_rdy is set ? in_pkt_rdy get cleared ? sent_stall gets set ? data_end gets cleared ? setup_end gets set
s3c9654/c9658/p9658 control registers 4- 25 usbrst ? usb reset reset register ffh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? ? ? 1 read/write ? ? ? ? ? ? ? r/w .7 ? . 1 not used for s3c9654/c9658/p9658 .0 usb reset signal receive bit 0 clear reset signal bit 1 this bit is set when host send usb reset signal usbsel ? port 2 mode select register fbh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? ? ? 0 read/write ? ? ? ? ? ? ? r/w .7 ? . 1 not used for s3c9654/c9658/p9658 .0 "0" = gpio port, ps/2 mode, "1" = usb port usb mode.
control registers s3c9654/c9658/p9658 4- 26 xcon ? usb signal control register (feh, r/w) bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? 0 0 0 0 0 0 read/write ? ? r/w r/w r/w r/w r/w r/w note: xcon register value advised by factory (the recommendable value is 1bh).
s3c9654/c9658/p9658 interrupt structure 5- 1 5 interrupt structure overview the sam88rcri interrupt structure has two basic components: a vector, and sources. the number of interrupt sources can be serviced through a interrupt vector which is assigned in rom address 0000h?0001h. sources vector s1 s2 s3 sn 0000h 0001h notes: 1. the sam88rcri interrupt has only one vector address (0000h-0001h). 2. the number of sn value is expandable. figure 5- 1 . s3c9 -series interrupt type interrupt processing control points interrupt processing can be controlled in two ways: globally, or by specific interrupt level and source. the system- level control points in the interrupt structure are therefore: ? global interrupt enable and disable (by ei and di instructions) ? interrupt source en able and disable settings in the corresponding peripheral control register(s) enable/disable interrupt instructions (ei, di) the system mode register, sym (dfh), is used to enable and disable interrupt processing. sym.3 is the enable and disable bit for global interrupt processing, which you can set by modifying sym.3 . an enable interrupt (ei) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing. al though you can manipulate sym.3 directly to enable and disable interrupts during normal operation, we recommend that you use the ei and di instructions for this purpose.
interrupt structure s3c9654/c9658/p9658 5- 2 interrupt pending function types when the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (iret) occurs. interrupt priority because there is not a interrupt priority register in sam87r i , the order of service is determined by a sequence of source which is executed in interrupt service routine. s r q interrupt pending register global interrupt control (ei, di instruction) vector interrupt cycle interrpt priority is determind by software polling method "ei" instruction execution reset source interrupts source interrupt enable figure 5- 2 . interrupt function diagram
s3c9654/c9658/p9658 interrupt structure 5- 3 interrupt source service sequence the interrupt request polling and servicing sequence is as follows: 1. a source generates an interrupt request by setting the interrupt request pending bit to "1". 2. the cpu generates an interrupt acknowledge signal. 3. the service routine starts and the source's pending flag is cleared to "0" by software. 4. interrupt priority must be determined by software polling method. interrupt service routines before an interrupt request can be serviced, the following conditions must be met: ? interrupt proce ssing must be enabled (ei ) ? interrupt must be enabled at the interrupt's source (peripheral control register) if all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. the cpu then initiates an interrupt machine cycle that completes the following processing sequence: 1. reset (clear to "0") the global interrupt enable bit in the sym register (di) to disable all subsequent interrupts. 2. save the program counter and status flags to stack. 3. branch to the interrupt vector to fetch the service routine's address. 4. pass control to the interrupt service routine. when the interrupt service routine is completed, an interrupt return instruction (iret) occurs. the iret restores the pc and status flags and sets sym.3 to "1"(ei), allowing the cpu to process the next interrupt request. generating interrupt vector addresses the interrupt vector area in the rom contains the address of the interrupt service routine. vectored interrupt processing follows this sequence: 1. push the program counter's low-byte value to stack. 2. push the program co unter's high-byte value to stack. 3. push the flags register values to stack. 4. fetch the service routine's high-byte address from the vector address 0000h. 5. fetch the service routine's low-byte address from the vector address 0001h. 6. branch to the service routine specified by the 16-bit vector address.
interrupt structure s3c9654/c9658/p9658 5- 4 s3c9654/c9658/p9658 interrupt structure the s3c9654/c9658/p9658 microcontroller has thirteen peripheral interrupt sources: ? timer 0 match interrupt ? timer 0 overflow interrupt ? suspend interrupt ? resume interrupt ? two endpoint interrupts for endpoint 0 and endpoint 1 ? three external interrupts for port 0 , p 0 .0?p 0 . 5 ? fou r external interrupts for port 1 , p 1 . 1 ?p 1 . 5 ? five external interrupts for port 2, p2.0?p2.1 (ps/2 mode only) ? internal rc osc interrupt. vector 0000h sym.3 (ei, di) t1con.1 to match interrupt t1con.2 to overflow interrupt suspend interrupt resume interrupt suspend/resume interrupt enable p0.0-p0.5 interrupt p1.0-p1.5 interrupt internal rc interrupt subcon.3 p0int.x p1int.x endpoint 0 interrupt endpoint 1 interrupt ps2 pad interrupt p2int.x enable_ep0 enable_ep1 subcon.6 p0pnd.0-6 p1pnd.0-5 p2pnd.3 ep0_pnd ep1_pnd t0con.0 suspend_ pnd resume_ pnd figure 5- 3 . s3c9654/c9658/p9658 interrupt structure
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 1 6 sam8 8rc r i instruction set overview the sam88rcri instruction set is designed to support the large register file. it includes a full complement of 8- bit arithmetic and logic operations. there are 41 instructions. no special i/o instructions are necessary because i/o control and data registers are mapped directly into the register file. flexible instructions for bit addressing, rotate, and shift operations complete the powerful data manipulation capabilities of the sam88rcri instruction set. register addressing to access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. paired registers can be used to construct 13-bit program memory or data memory addresses. for detailed information about register addressing, please refer to section 2, "address spaces". addressing modes there are six addressing modes: register (r), indirect register (ir), indexed (x), direct (da), relative (ra), and immediate (im). for detailed descriptions of these addressing modes, please refer to section 3, "addressing modes".
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 2 table 6- 1. instruction group summary mnemonic operands instruction load instructions clr dst clear ld dst,src load ldc dst,src load program memory lde dst,src load external data memory ldcd dst,src load program memory and decrement lded dst,src load external data memory and decrement ldci dst,src load program memory and increment ldei dst,src load external data memory and increment pop dst pop from stack push src push to stack arithmetic instructions adc dst,src add with carry add dst,src add cp dst,src compare dec dst decrement inc dst increment sbc dst,src subtract with carry sub dst,src subtract logic instructions and dst,src logical and com dst complement or dst,src logical or xor dst,src logical exclusive or
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 3 table 6- 1. instruction group summary (continued) mnemonic operands instruction program control instructions call dst call procedure iret interrupt return jp cc,dst jump on condition code jp dst jump unconditional jr cc,dst jump relative on condition code ret return bit manipulation instructions tcm dst,src test complement under mask tm dst,src test under mask rotate and shift instructions rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic cpu control instructions ccf complement carry flag di disable interrupts ei enable interrupts idle enter idle mode nop no operation rcf reset carry flag scf set carry flag stop enter stop mode
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 4 flags register (flags) the flags register contains eight bits that describe the current status of cpu operations. four of these bits, flags.4 ? flags.7, can be tested and used with conditional jump instructions; flags register can be set or reset by instructions as long as its outcome does not affect the flags, such as, load instruction. logical and arithmetic instructions such as, and, or, xor, add, and sub can affect the flags register. for example, the and instruction updates the zero, sign and overflow flags based on the outcome of the and instruction. if the and instruction uses the flags register as the destination, then simultaneously, two write will occur to the flags register producing an unpredictable result. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb system flags register (flags) d5h, r/w not mapped carry flag (c) zero flag (z) sign flag (s) overflow flag (v) figure 6- 1. system flags register (flags) flag descriptions overflow flag (flags.4, v) the v flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than ? 128. it is also cleared to "0" following logic operations. sign flag (flags.5, s) following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the msb of the result. a logic zero indicates a positive number and a logic one indicates a negative number. zero flag (flags.6, z) for arithmetic and logic operations, the z flag is set to "1" if the result of the operation is zero. for operations that test register bits, and for shift and rotate operations, the z flag is set to "1" if the result is logic zero. carry flag (flags.7, c) the c flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (msb). after rotate and shift operations, it contains the last value shifted out of the specified register. program instructions can set, clear, or complement the carry flag.
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 5 instruction set notation table 6- 2. flag notation conventions flag description c carry flag z zero flag s sign flag v overflow flag 0 cleared to logic zero 1 set to logic one * set or cleared according to operation ? value is unaffected x value is undefined table 6- 3. instruction set symbols symbol description dst destination operand src source operand @ indirect register address prefix pc program counter flags flags register (d5h) # immediate operand or register address prefix h hexadecimal number suffix d decimal number suffix b binary number suffix opc opcode
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 6 table 6- 4. instruction notation conventions notation description actual operand range cc condition code see list of condition codes in table 6- 6. r working register only rn (n = 0?15) rr working register pair rrp (p = 0, 2, 4, ..., 14) r register or working register reg or rn ( reg = 0?255, n = 0?15) rr register pair or working register pair reg or rrp ( reg = 0?254, even number only, where p = 0, 2, ..., 14) ir indirect working register only @ rn (n = 0?15) ir indirect register or indirect working register @ rn or @ reg ( reg = 0?255, n = 0?15) irr indirect working register pair only @ rrp (p = 0, 2, ..., 14) irr indirect register pair or indirect working register pair @ rrp or @ reg ( reg = 0?254, even only, where p = 0, 2, ..., 14) x indexed addressing mode # reg[ rn] ( reg = 0?255, n = 0?15) xs indexed (short offset) addressing mode # addr[ rrp] ( addr = range ?128 to +127, where p = 0, 2, ..., 14) xl indexed (long offset) addressing mode # addr [ rrp] ( addr = range 0?8191, where p = 0, 2, ..., 14) da direct addressing mode addr ( addr = range 0?8191) ra relative addressing mode addr ( addr = number in the range +127 to ?128 that is an offset relative to the address of the next instruction) im immediate addressing mode #data (data = 0?255)
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 7 table 6- 5. opcode quick reference opcode map lower nibble (hex) ? 0 1 2 3 4 5 6 7 u 0 dec r1 dec ir1 add r1,r2 add r1,ir2 add r2,r1 add ir2,r1 add r1,im p 1 rlc r1 rlc ir1 adc r1,r2 adc r1,ir2 adc r2,r1 adc ir2,r1 adc r1,im p 2 inc r1 inc ir1 sub r1,r2 sub r1,ir2 sub r2,r1 sub ir2,r1 sub r1,im e 3 jp irr1 sbc r1,r2 sbc r1,ir2 sbc r2,r1 sbc ir2,r1 sbc r1,im r 4 or r1,r2 or r1,ir2 or r2,r1 or ir2,r1 or r1,im 5 pop r1 pop ir1 and r1,r2 and r1,ir2 and r2,r1 and ir2,r1 and r1,im n 6 com r1 com ir1 tcm r1,r2 tcm r1,ir2 tcm r2,r1 tcm ir2,r1 tcm r1,im i 7 push r2 push ir2 tm r1,r2 tm r1,ir2 tm r2,r1 tm ir2,r1 tm r1,im b 8 ld r1, x, r2 b 9 rl r1 rl ir1 ld r2, x, r1 l a cp r1,r2 cp r1,ir2 cp r2,r1 cp ir2,r1 cp r1,im ldc r1, irr2, xl e b clr r1 clr ir1 xor r1,r2 xor r1,ir2 xor r2,r1 xor ir2,r1 xor r1,im ldc r2, irr2, xl c rrc r1 rrc ir1 ldc r1,irr2 ld r1, ir2 h d sra r1 sra ir1 ldc r2,irr1 ld ir1,im ld ir1, r2 e e rr r1 rr ir1 ldcd r1,irr2 ldci r1,irr2 ld r2,r1 ld r2,ir1 ld r1,im ldc r1, irr2, xs x f call irr1 ld ir2,r1 call da1 ldc r2, irr1, xs
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 8 table 6- 5. opcode quick reference (continued) opcode map lower nibble (hex) ? 8 9 a b c d e f u 0 ld r1,r2 ld r2,r1 jr cc,ra ld r1,im jp cc,da inc r1 p 1 p 2 e 3 r 4 5 n 6 idle i 7 stop b 8 di b 9 ei l a re t e b iret c rcf h d scf e e ccf x f ld r1,r2 ld r2,r1 jr cc,ra ld r1,im jp cc,da inc r1 nop
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 9 condition codes the opcode of a conditional jump always contains a 4-bit field called the condition code (cc). this specifies under which conditions it is to execute the jump. for example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. condition codes are listed in table 6- 6. the carry (c), zero (z), sign (s), and overflow (v) flags are used to control the operation of conditional jump instructions. table 6- 6. condition codes binary mnemonic description flags set 0000 f always false ? 1000 t always true ? 0111 (1) c carry c = 1 1111 (1) nc no carry c = 0 0110 (1) z zero z = 1 1110 (1) nz not zero z = 0 1101 pl plus s = 0 0101 mi minus s = 1 0100 ov overflow v = 1 1100 nov no overflow v = 0 0110 (1) eq equal z = 1 1110 (1) ne not equal z = 0 1001 ge greater than or equal (s xor v) = 0 0001 lt less than (s xor v) = 1 1010 gt greater than (z or (s xor v)) = 0 0010 le less than or equal (z or (s xor v)) = 1 1111 (1) uge unsigned greater than or equal c = 0 0111 (1) ult unsigned less than c = 1 1011 ugt unsigned greater than (c = 0 and z = 0) = 1 0011 ule unsigned less than or equal (c or z) = 1 notes: 1. i ndicate condition codes that are related to two different mnemonics but which test the same flag. for example, z and eq are both true if the zero flag (z) is set, but after an add instruction, z would probably be used; after a cp instruction, however, eq would probably be used. 2. for operations involving unsigned numbers, the special condition codes uge, ult, ugt, and ule must be used.
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 10 instruction descriptions this section contains detailed information and programming examples for each instruction in the sam88rcri instruction set. information is arranged in a consistent format for improved readability and for fast referencing. the following information is included in each instruction description: ? instruction name (mnemonic) ? full instruction name ? source/destination format of the instruction operand ? shorthand notation of the instruction's operation ? textual description of the instruction's effect ? specific flag settings affected by the instruction ? detailed description of the instruction's format, execution time, and addressing mode(s) ? programming ex ample(s) explaining how to use the instruction
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 11 adc ? add with carry adc dst,src operation: dst dst + src + c the source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's- complement addition is performed. in multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 r r 6 15 r ir opc dst src 3 6 16 r im examples: given: r1 = 10h, r2 = 03h, c flag = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: adc r1,r2 ? r1 = 14h, r2 = 03h adc r1,@r2 ? r1 = 1bh, r2 = 03h adc 01h,02h ? register 01h = 24h, register 02h = 03h adc 01h,@02h ? register 01 h = 2bh, register 02h = 03h adc 01h,#11h ? register 01h = 32h in the first example, destination register r1 contains the value 10h, the carry flag is set to "1", and the source working register r2 contains the value 03h. the statement "adc r1,r2" adds 03h and the carry flag value ("1") to the destination value 10h, leaving 14h in register r1.
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 12 add ? add add dst,src operation: dst dst + src the source operand is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's-complement addition is performed. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if a carry from the low-order nibble occurred. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 r r 6 05 r ir opc dst src 3 6 06 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: add r1,r2 ? r1 = 15h, r2 = 03h add r1,@r2 ? r1 = 1ch, r2 = 03h add 01h,02h ? register 01h = 24h, register 02h = 03h add 01h,@02h ? register 01h = 2bh, registe r 02h = 03h add 01h,#25h ? register 01h = 46h in the first example, destination working register r1 contains 12h and the source working register r2 contains 03h. the statement "add r1,r2" adds 03h to 12h, leaving the value 15h in register r1.
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 13 and ? logical and and dst,src operation: dst dst and src the source operand is logically anded with the destination operand. the result is stored in the destination. the and operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. the contents of the source are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 r r 6 55 r ir opc dst src 3 6 56 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: and r1,r2 ? r1 = 02h, r2 = 03h and r1,@r2 ? r1 = 02h, r2 = 03h and 01h,02h ? register 01h = 01h, register 02h = 03h and 01h,@02h ? register 01h = 00h, register 02h = 03h and 01h,#25h ? register 01h = 21h in the first example, destination working register r1 contains the value 12h and the source working register r2 contains 03h. the statement "and r1,r2" logically ands the source operand 03h with the destination operand value 12h, leaving the value 02h in register r1.
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 14 call ? call procedure call dst operation: sp sp ? 1 @sp pcl sp sp ?1 @sp pch pc dst the current contents of the program counter are pushed onto the top of the stack. the program counter value used is the address of the first instruction following the call instruction. the specified destination address is then loaded into the program counter and points to the first instruction of a procedure. at the end of the procedure the return instruction (ret) can be used to return to the original program flow. ret pops the top of the stack back into the program counter. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 3 14 f6 da opc dst 2 12 f4 irr examples: given: r0 = 15h, r1 = 21h, pc = 1a47h, and sp = 0b2h: call 1521h ? sp = 0b0h (memory locations 00h = 1ah, 01h = 4ah, where 4ah is the address that follows the instruction.) call @rr0 ? sp = 0b0h (00h = 1ah, 01h = 49h) in the first example, if the program counter value is 1a47h and the stack pointer contains the value 0b2h, the statement "call 1521h" pushes the current pc value onto the top of the stack. the stack pointer now points to memory location 00h. the pc is then loaded with the value 1521h, the address of the first instruction in the program sequence to be executed. if the contents of the program counter and stack pointer are the same as in the first example, the statement "call @rr0" produces the same result except that the 49h is stored in stack location 01h (because the two-byte instruction format was used). the pc is then loaded with the value 1521h, the address of the first instruction in the program sequence to be executed.
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 15 ccf ? complement carry flag ccf operation: c not c the carry flag (c) is complemented. if c = "1", the value of the carry flag is changed to logic zero; if c = "0", the value of the carry flag is changed to logic one. flags: c: complemented. no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 ef example: given: the carry flag = "0": ccf if the carry flag = "0", the ccf instruction complements it in the flags register (0d5h), changing its value from logic zero to logic one.
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 16 clr ? clear clr dst operation: dst "0" the destination location is cleared to "0". flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 b0 r 4 b1 ir examples: given: register 00h = 4fh, register 01h = 02h, and register 02h = 5eh: clr 00h ? register 00h = 00h clr @01h ? register 01h = 02h, register 02h = 00h in register (r) addressing mode, the statement "clr 00h" clears the destination register 00h value to 00h. in the second example, the statement "clr @01h" uses indirect register (ir) addressing mode to clear the 02h register value to 00h.
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 17 com ? complement com dst operation: dst not dst the contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 60 r 4 61 ir examples: given: r1 = 07h and register 07h = 0f1h: com r1 ? r1 = 0f8h com @r1 ? r1 = 07h, register 07h = 0eh in the first example, destination working register r1 contains the value 07h (00000111b). the statement "com r1" complements all the bits in r1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0f8h (11111000b). in the second example, indirect register (ir) addressing mode is used to complement the value of destination register 07h (11110001b), leaving the new value 0eh (00001110b).
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 18 cp ? compare cp dst,src operation: dst ? src the source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. the contents of both operands are unaffected by the comparison. flags: c: set if a "borrow" occurred ( src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 a2 r r 6 a3 r lr opc src dst 3 6 a4 r r 6 a5 r ir opc dst src 3 6 a6 r im examples: 1. given: r1 = 02h and r2 = 03h: cp r1,r2 ? set the c and s flags destination working register r1 contains the value 02h and source register r2 contains the value 03h. the statement "cp r1,r2" subtracts the r2 value (source/subtrahend) from the r1 value (destination/minuend). because a "borrow" occurs and the difference is negative, c and s are "1". 2. given: r1 = 05h and r2 = 0ah: cp r1,r2 jp uge,skip inc r1 skip ld r3,r1 in this example, destination working register r1 contains the value 05h which is less than the contents of the source working register r2 (0ah). the statement "cp r1,r2" generates c = "1" and the jp instruction does not jump to the skip location. after the statement "ld r3,r1" executes, the value 06h remains in working register r3.
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 19 dec ? decrement dec dst operation: dst dst ? 1 the contents of the destination operand are decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, dst value is ?128(80h) and result value is +127(7fh); cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 00 r 4 01 ir examples: given: r1 = 03h and register 03h = 10h: dec r1 ? r1 = 02h dec @r1 ? register 03h = 0fh in the first example, if working register r1 contains the value 03h, the statement "dec r1" decrements the hexadecimal value by one, leaving the value 02h. in the second example, the statement "dec @r1" decrements the value 10h contained in the destination register 03h by one, leaving the value 0fh.
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 20 di ? disable interrupts di operation: sym (2) 0 bit zero of the system mode register, sym.2, is cleared to "0", globally disabling all interrupt processing. interrupt requests will continue to set their respective interrupt pending bits, but the cpu will not service them while interrupt processing is disabled. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 8f example: given: sym = 04h: di if the value of the sym register is 04h, the s tatement "di" leaves the new value 00h in the register and clears sym.2 to "0", disabling interrupt processing.
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 21 ei ? enable interrupts ei operation: sym (2) 1 an ei instruction sets bit 2 of the system mode register, sym.2 to "1". this allows interrupts to be serviced as they occur. if an interrupt's pending bit was set while interrupt processing was disabled (by executing a di instruction), it will be serviced when you execute the ei instruction. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 9f example: given: sym = 00h: ei if the sym register contains the value 00h, that is, if interrupts are currently disabled, the statement "ei" sets the sym register to 04h, enabling all interrupts (sym.2 is the enable bit for global interrupt processing) .
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 22 idle ? idle operation idle operation: the idle instruction stops the cpu clock while allowing system clock oscillation to continue. idle mode can be released by an interrupt request (irq) or an external reset operation. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 6f ? ? example: the instruction idle stops the cpu clock but not the system clock.
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 23 inc ? increment inc dst operation: dst dst + 1 the contents of the destination operand are incremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is dst value is +127(7fh) and result is ?128(80h); cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst dst | opc 1 4 re r r = 0 to f opc dst 2 4 20 r 4 21 ir examples: given: r0 = 1bh, register 00h = 0ch, and register 1bh = 0fh: inc r0 ? r0 = 1ch inc 00h ? register 00h = 0dh inc @r0 ? r0 = 1bh, register 01h = 10h in the first exam ple, if destination working register r0 contains the value 1bh, the statement "inc r0" leaves the value 1ch in that same register. the next example shows the effect an inc instruction has on register 00h, assuming that it contains the value 0ch. in the third example, inc is used in indirect register (ir) addressing mode to increment the value of register 1bh from 0fh to 10h.
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 24 iret ? interrupt return iret iret operation: flags @sp sp sp + 1 pc @sp sp sp + 2 sy m(2) 1 this instruction is used at the end of an interrupt service routine. it restores the flag register and the program counter. it also re-enables global interrupts. flags: all flags are restored to their original settings (that is, the settings before the interrupt occurred). format: iret (normal) bytes cycles opcode (hex) opc 1 6 bf
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 25 jp ? jump jp cc,dst (conditional) jp dst (unconditional) operation: if cc is true, pc dst the conditional jump instruction tr ansfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the jp instruction is executed. the unconditional jp simply replaces the contents of the pc with the contents of the specified register pair. control then passes to the statement addressed by the pc. flags: no flags are affected. format: (1) (2) bytes cycles opcode (hex) addr mode dst cc | opc dst 3 8 (3) ccd da cc = 0 to f opc dst 2 8 30 irr notes: 1. the 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. in the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four bits. examples: given: the carry flag (c) = "1", register 00 = 01h, and register 01 = 20h: jp c,label_w ? label_w = 1000h, pc = 1000h jp @00h ? pc = 0120h the first example shows a conditional jp. assuming that the carry flag is set to "1", the state ment "jp c,label_w" replaces the contents of the pc with the value 1000h and transfers control to that location. had the carry flag not been set, control would then have passed to the statement immediately following the jp instruction. the second example shows an unconditional jp. the statement "jp @00" replaces the contents of the pc with the contents of the register pair 00h and 01h, leaving the value 0120h.
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 26 jr ? jump relative jr cc,dst operation: if cc is true, pc pc + dst if the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the jr instruction is executed (see list of condition codes). the range of the relative address is +127, ?128, and the original value of the program counter is taken to be the address of the first instruction byte following the jr statement. flags: no flags are affected. format: (1) bytes cycles opcode (hex) addr mode dst cc | opc dst 2 6 (2) ccb ra cc = 0 to f note : in the first byte of the two-byte instruction format, the condition code and the opcode are each four bits. example: given: the carry flag = "1" and label_x = 1ff7h: jr c,label_x ? pc = 1ff7h if the carry flag is set (that is, if the condition code is true), the statement "jr c,label_x" will pass control to the statement whose address is now in the pc. otherwise, the program instruction following the jr would be executed.
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 27 ld ? load ld dst,src operation: dst src the contents of the source are loaded into the destination. the source's contents are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src dst | opc src 2 4 rc r im 4 r8 r r src | opc dst 2 4 r9 r r r = 0 to f opc dst | src 2 4 c7 r lr 4 d7 ir r opc src dst 3 6 e4 r r 6 e5 r ir opc dst src 3 6 e6 r im 6 d6 ir im opc src dst 3 6 f5 ir r opc dst | src x 3 6 87 r x [r] opc src | dst x 3 6 97 x [r] r
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 28 ld ? load ld (continued) examples: given: r0 = 01h, r1 = 0ah, register 00h = 01h, register 01h = 20h, register 02h = 02h, loop = 30h, and register 3ah = 0ffh: ld r0,#10h ? r0 = 10h ld r0,01h ? r0 = 20h, register 01h = 20h ld 01h,r0 ? register 01h = 01h, r0 = 01h ld r1,@r0 ? r1 = 20h, r0 = 01h ld @r0,r1 ? r0 = 01h, r1 = 0ah, register 01h = 0ah ld 00h,01h ? register 00h = 20h, register 01h = 20h ld 02h,@00h ? register 02h = 20h, register 00h = 01h ld 00h,#0ah ? register 00h = 0ah ld @00h,#10h ? register 00h = 01h, register 01h = 10h ld @00h,02h ? register 00h = 01h, register 01h = 02, register 02h = 02h ld r0,#loop[r1] ? r0 = 0ffh, r1 = 0ah ld #loop[r0],r1 ? register 31h = 0ah, r0 = 01h, r1 = 0ah
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 29 ldc/lde ? load memory ldc/lde dst,src operation: dst src this instruction loads a byte from program or data memory into a working register or vice-versa. the source values are unaffected. ldc refers to program memory and lde to data memory. the assembler makes ' irr' or ' rr' values an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src 1. opc dst | src 2 10 c3 r irr 2. opc src | dst 2 10 d3 irr r 3. opc dst | src xs 3 12 e7 r xs [ rr] 4. opc src | dst xs 3 12 f7 xs [ rr] r 5. opc dst | src xl l xl h 4 14 a7 r xl [ rr] 6. opc src | dst xl l xl h 4 14 b7 xl [ rr] r 7. opc dst | 0000 da l da h 4 14 a7 r da 8. opc src | 0000 da l da h 4 14 b7 da r 9. opc dst | 0001 da l da h 4 14 a7 r da 10. opc src | 0001 da l da h 4 14 b7 da r notes: 1. the source ( src) or working register pair [ rr] for formats 5 and 6 cannot use register pair 0?1. 2. for form ats 3 and 4, the destination address 'xs [ rr]' and the source address 'xs [ rr]' are each one byte. 3. for formats 5 and 6, the destination address 'xl [ rr] and the source address 'xl [ rr]' are each two bytes. 4. the da and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory.
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 30 ldc/lde ? load memory ldc/lde (continued) examples: given: r0 = 11h, r1 = 34h, r2 = 01h, r3 = 04h, r4 = 00h, r5 = 60h; program memory locations 0061 = aah, 0103h = 4fh, 0104h = 1a, 0105h = 6dh, and 1104h = 88h. external data memory locations 0061h = bbh, 0103h = 5fh, 0104h = 2ah, 0105h = 7dh, and 1104h = 98h: ldc r0,@rr2 ; r0 contents of program memory location 0104h ; r0 = 1ah, r2 = 01h, r3 = 04h lde r0,@rr2 ; r0 contents of external data memory location 0104h ; r0 = 2ah, r2 = 01h, r3 = 04h ldc * @rr2,r0 ; 11h (contents of r0) is loaded into program memory ; location 0104h (rr2), ; working re gisters r0, r2, r3 ? no change lde @rr2,r0 ; 11h (contents of r0) is loaded into external data memory ; location 0104h (rr2), ; working registers r0, r2, r3 ? no change ldc r0,#01h[rr4] ; r0 contents of program memory location 0061h ; (01h + rr4), ; r0 = aah, r2 = 00h, r3 = 60h lde r0,#01h[rr4] ; r0 contents of external data memory location 0061h ; (01h + rr4), r0 = bbh, r4 = 00h, r5 = 60h ldc (note) #01h[rr4],r0 ; 11h (contents of r0) is loaded into pr ogram memory ; location 0061h (01h + 0060h) lde #01h[rr4],r0 ; 11h (contents of r0) is loaded into external data memory ; location 0061h (01h + 0060h) ldc r0,#1000h[rr2] ; r0 contents of program memory location 1104h ; (1000h + 0104h), r0 = 88h, r2 = 01h, r3 = 04h lde r0,#1000h[rr2] ; r0 contents of external data memory location 1104h ; (1000h + 0104h), r0 = 98h, r2 = 01h, r3 = 04h ldc r0,1104h ; r0 contents of program memory location 1104h, ; r0 = 88h lde r0,1104h ; r0 contents of external data memory location 1104h, ; r0 = 98h ldc (note) 1105h,r0 ; 11h (contents of r0) is loaded into program memory ; location 1105h, (1105h) 11h lde 1105h,r0 ; 11h (contents of r0) is loaded into external data memory ; location 1105h, (1105h) 11h note: these instructions are not supported by masked rom type devices.
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 31 ldcd/lded ? load memory and decrement ldcd/lded dst,src operation: dst src rr rr ? 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then decremented. the contents of the source are unaffected. ldcd references program memory and lded references external data memory. the assembler makes ? irr ? an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e2 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory location 1033h = 0cdh, and external data memory location 1033h = 0ddh: ldcd r8,@rr6 ; 0cdh (contents of program memory location 1033h) is ; loaded into r8 and rr6 is decremented by one ; r8 = 0cdh, r6 = 10h, r7 = 32h (rr6 ? rr6 - 1) lded r8,@rr6 ; 0ddh (contents of data memory loca tion 1033h) is ; loaded into r8 and rr6 is decremented by one ; (rr6 ? rr6 - 1) r8 = 0ddh, r6 = 10h, r7 = 32h
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 32 ldci/ldei ? load memory and increment ldci/ldei dst,src operation: dst src rr rr + 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then incremented automatically. the contents of the source are unaffected. ldci refers to program memory and ldei refers to external data memory. the assembler makes ' irr' even for program memory and odd for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e3 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory locations 1033h = 0cdh and 1034h = 0c5h; external data memory locations 1033h = 0ddh and 1034h = 0d5h: ldci r8,@rr6 ; 0cdh (contents of program memory location 1033h) is ; loaded into r8 and rr6 is incremented by one ; (rr6 rr6 + 1) r8 = 0cdh, r6 = 10h, r7 = 34h ldei r8,@rr6 ; 0ddh (contents of data m emory location 1033h) is ; loaded into r8 and rr6 is incremented by one ; (rr6 rr6 + 1) r8 = 0ddh, r6 = 10h, r7 = 34h
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 33 nop ? no operation nop operation: no action is performed when the cpu executes this instructio n. typically, one or more nops are executed in sequence in order to effect a timing delay of variable duration. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 ff example: when the instruction nop is encountered in a program, no operation occurs. instead, there is a delay in instruction execution time.
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 34 or ? logical or or dst,src operation: dst dst or src the source operand is logically ored with the destination operand and the result is stored in the destination. the contents of the source are unaffected. the or operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 r r 6 45 r ir opc dst src 3 6 46 r im examples: given: r0 = 15h, r1 = 2ah, r2 = 01h, register 00h = 08h, register 01h = 37h, and register 08h = 8ah: or r0,r1 ? r0 = 3fh, r1 = 2ah or r0,@r2 ? r0 = 37h, r2 = 01h, register 01h = 37h or 00h,01h ? register 00h = 3fh, register 01h = 37h or 01h,@00h ? register 00h = 08h, register 01h = 0bfh or 00h,#02h ? register 00h = 0ah in the first example, if working register r0 contains the value 15h and register r1 the value 2ah, the statement "or r0,r1" logical- ors the r0 and r1 register contents and stores the result (3fh) in destination register r0. the other examples show the use of the logical or instruction with the various addressing modes and formats.
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 35 pop ? pop from stack pop dst operation: dst @sp sp sp + 1 the contents of the location addressed by the stack pointer are loaded into the destination. the stack pointer is then incremented by one. flags: no flags affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 50 r 8 51 ir examples: given: register 00h = 01h, register 01h = 1bh, sp (0d9h) = 0bbh, and stack register 0bbh = 55h: pop 00h ? register 00h = 55h, sp = 0bch pop @00h ? register 00h = 01h, register 01h = 55h, sp = 0bch in the first example, general register 00h contains the value 01h. the statement "pop 00h" loads the contents of location 0bbh (55h) into destination register 00h and then increments the stack pointer by one. register 00h then contains the value 55h and the sp points to location 0bch.
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 36 push ? push to stack push src operation: sp sp ? 1 @sp src a push instruction decrements the stack pointer value and loads the contents of the source ( src) into the location addressed by the decremented stack pointer. the operation then adds the new value to the top of the stack. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc src 2 8 70 r 8 71 ir examples: given: register 40h = 4fh, register 4fh = 0aah, sp = 0c0h: push 40h ? register 40h = 4fh, stack register 0bfh = 4fh, sp = 0bfh push @40h ? register 40h = 4fh, register 4fh = 0aah, stack register 0bfh = 0aah, sp = 0bfh in the first example, if the stack pointer contains the value 0c0h, and general register 40h the value 4fh, the statement "push 40h" decrements the stack pointer from 0c0 to 0bfh. it then loads the contents of register 40h into location 0bfh. register 0bfh then contains the value 4fh and sp points to location 0bfh.
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 37 rcf ? reset carry flag rcf rcf operation: c 0 the carry flag is cleared to logic zero, regardless of its previous value. flags: c: cleared to "0". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 cf example: given: c = "1" or "0": the instruction rcf clears the carry flag (c) to logic zero.
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 38 ret ? return ret operation: pc @sp sp sp + 2 the ret inst ruction is normally used to return to the previously executing procedure at the end of a procedure entered by a call instruction. the contents of the location addressed by the stack pointer are popped into the program counter. the next statement that is executed is the one that is addressed by the new program counter value. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 8 af example: given: sp = 0bch, (sp) = 101ah, and pc = 1234: ret ? pc = 101ah, sp = 0beh the stat ement "ret" pops the contents of stack pointer location 0bch (10h) into the high byte of the program counter. the stack pointer then pops the value in location 0bdh (1ah) into the pc's low byte and the instruction at location 101ah is executed. the stack pointer now points to memory location 0beh.
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 39 rl ? rotate left rl dst operation: c dst (7) dst (0) dst (7) dst (n + 1) dst (n), n = 0?6 the contents of the destination operand are rotated left one bit position. the initial value of bit 7 is moved to the bit zero (lsb) position and also replaces the carry flag. c 7 0 flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 90 r 4 91 ir examples: given: register 00h = 0aah, register 01h = 02h and register 02h = 17h: rl 00h ? register 00h = 55h, c = "1" rl @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if general register 00h contains the value 0aah (10101010b), the statement "rl 00h" rotates the 0aah value left one bit position, leaving the new value 55h (01010101b) and setting the carry and overflow flags.
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 40 rlc ? rotate left through carry rlc dst operation: dst (0) c c dst (7) dst (n + 1) dst (n), n = 0?6 the contents of the destination operand with the carry flag are rotated left one bit position. the initial value of bit 7 replaces the carry flag (c); the initial value of the carry flag replaces bit zero. c 7 0 flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 10 r 4 11 ir examples: given: register 00h = 0aah, register 01h = 02h, and register 02h = 17h, c = "0": rlc 00h ? register 00h = 54h, c = "1" rlc @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if general register 00h has the value 0aah (10101010b), the statement "rlc 00h" rotates 0aah one bit position to the left. the initial value of bit 7 sets the carry flag and the initial value of the c flag replaces bit zero of register 00h, leaving the value 55h (01010101b). the msb of register 00h resets the carry flag to "1" and sets the overflow flag.
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 41 rr ? rotate right rr dst operation: c dst (0) dst (7) dst (0) dst (n) dst (n + 1), n = 0?6 the contents of the destination operand are rotated right one bit position. the initial value of bit zero (lsb) is moved to bit 7 (msb) and also replaces the carry flag (c). c 7 0 flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 e0 r 4 e1 ir examples: given: register 00h = 31h, register 01h = 02h, and register 02h = 17h: rr 00h ? register 00h = 98h, c = "1" rr @01h ? register 01h = 02h, register 02h = 8bh, c = "1" in the first example, if general register 00h contains the value 31h (00110001b), the statement "rr 00h" rotates this value one bit position to the right. the initial value of bit zero is moved to bit 7, leaving the new value 98h (10011000b) in the destination register. the initial bit zero also resets the c flag to "1" and the sign flag and overflow flag are also set to "1".
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 42 rrc ? rotate right through carry rrc dst operation: dst (7) c c dst (0) dst (n) dst (n + 1), n = 0?6 the contents of the destination operand and the carry flag are rotated right one bit position. the initial value of bit zero (lsb) replaces the carry flag; the initial value of the carry flag replaces bit 7 (msb). c 7 0 flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0" cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 c0 r 4 c1 ir examples: given: register 00h = 55h, register 01h = 02h, register 02h = 17h, and c = "0": rrc 00h ? register 00h = 2ah, c = "1" rrc @01h ? register 01h = 02h, register 02h = 0bh, c = "1" in the first example, if general register 00h contains the value 55h (01010101b), the statement "rrc 00h" rotates this value one bit position to the right. the initial value of bit zero ("1") replaces the carry flag and the initial value of the c f lag ("1") replaces bit 7. this leaves the new value 2ah (00101010b) in destination register 00h. the sign flag and overflow flag are both cleared to "0".
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 43 sbc ? subtract with carry sbc dst,src operation: dst dst ? src ? c the source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's-complement of the source operand to the destination operand. in multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. flags: c: set if a borrow occurred ( src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign f the result is the same as the sign of the source; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 r r 6 35 r ir opc dst src 3 6 36 r im examples: given: r1 = 10h, r2 = 03h, c = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: sbc r1,r2 ? r1 = 0ch, r2 = 03h sbc r1,@r2 ? r1 = 05h, r2 = 03h, register 03h = 0ah sbc 01h,02h ? register 01h = 1ch, register 02h = 03h sbc 01h,@02h ? register 01h = 15h,register 02h = 03h, register 03h = 0ah sbc 01h,#8ah ? register 01h = 95h; c, s, and v = "1" in the first example, if working register r1 contains the value 10h and register r2 the value 03h, the statement "sbc r1,r2" subtracts the source value (03h) and the c flag value ("1") from the destination (10h) and then stores the result (0ch) in register r1.
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 44 scf ? set carry flag scf operation: c 1 the carry flag (c) is set to logic one, regardless of its previous value. flags: c: set to "1". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 df example: the statement scf sets the carry flag to logic one.
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 45 sra ? shift right arithmetic sra dst operation: dst (7) dst (7) c dst (0) dst (n) dst (n + 1), n = 0?6 an arithmetic shift-right of one bit position is performed on the destination operand. bit zero (the lsb) replaces the carry flag. the value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6. c 7 6 0 flags: c: set if the bit shifted from the lsb position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 d0 r 4 d1 ir examples: given: register 00h = 9ah, register 02h = 03h, register 03h = 0bch, and c = "1": sra 00h ? register 00h = 0cd, c = "0" sra @02h ? register 02h = 03h, register 03h = 0deh, c = "0" in the first example, if general register 00h contains the value 9ah (10011010b), the statement "sra 00h" shifts the bit values in register 00h right one bit position. bit zero ("0") clears the c flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). this leaves the value 0cdh (11001101b) in destination register 00h.
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 46 stop ? stop operation stop operation: the stop instruction stops both the cpu clock and system clock and causes the microcontroller to enter stop mode. during stop mode, the contents of on-chip cpu registers, peripheral registers, and i/o port control and data registers are retained. stop mode can be released by an external reset operation or external interrupt input. for the reset operation, the reset pin must be held to low level until the required oscillation stabilization interval has elapsed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 7f ? ? example: the statement stop halts all microcontroller operations.
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 47 sub ? subtract sub dst,src operation: dst dst ? src the source operand is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's complement of the source operand to the destination operand. flags: c: set if a "borrow" occurred; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise indicating a "borrow". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 r r 6 25 r ir opc dst src 3 6 26 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: sub r1,r2 ? r1 = 0fh, r2 = 03h sub r1,@r2 ? r1 = 08h, r2 = 03h sub 01h,02h ? register 01h = 1eh, register 02 h = 03h sub 01h,@02h ? register 01h = 17h, register 02h = 03h sub 01h,#90h ? register 01h = 91h; c, s, and v = "1" sub 01h,#65h ? register 01h = 0bch; c and s = "1", v = "0" in the first example, if working register r1 contains the value 12h and if register r2 contains the value 03h, the statement "sub r1,r2" subtracts the source value (03h) from the destination value (12h) and stores the result (0fh) in destination register r1.
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 48 tcm ? test complement under mask tcm dst,src operation: (not dst) and src this instruction tests selected bits in the destination operand for a logic one value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). the tcm statement complements the destination operand, which is then anded with the source mask. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 r r 6 65 r ir opc dst src 3 6 66 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 12h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tcm r0,r1 ? r0 = 0c7h, r1 = 02h, z = "1" tcm r0,@r1 ? r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tcm 00h,01h ? register 00h = 2bh, register 01h = 02h, z = "1" tcm 00h,@01h ? register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "1" tcm 00h,#34 ? register 00h = 2bh, z = "0" in the first example, if working register r0 contains the value 0c7h (11000111b) and register r1 the value 02h (00000010b), the statement "tcm r0,r1" tests bit one in the destination register for a "1" value. because the mask value corresponds to the test bit, the z flag is set to logic one and can be tested to determine the result of the tcm operation.
s3c9654/c9658/p9658 s am8 8rc ri instruction set 6 - 49 tm ? test under mask tm dst,src operation: dst and src this instruction tests selected bits in the destination operand for a logic zero value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is anded with the destination operand. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 r r 6 75 r ir opc dst src 3 6 76 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tm r0,r1 ? r0 = 0c7h, r1 = 02h, z = "0" tm r0,@r1 ? r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tm 00h,01h ? register 00h = 2bh, register 01h = 02h, z = "0" tm 00h,@01h ? register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "0" tm 00h,#54h ? register 00h = 2bh, z = "1" in the first example, if working register r0 contains the value 0c7h (11000111b) and register r1 the value 02h (00000010b), the statement "tm r0,r1" tests bit one in the destination register for a "0" value. because the mask value does not match the test bit, the z flag is cleared to logic zero and can be tested to determine the result of the tm operation.
sam8 8 ri instruction set s3c9654/c9658/p9658 6 - 50 xor ? logical exclusive or xor dst,src operation: dst dst xor src the source operand is logically exclusive- ored with the destination operand and the result is stored in the destination. the exclusive-or operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 b2 r r 6 b3 r lr opc src dst 3 6 b4 r r 6 b5 r ir opc dst src 3 6 b6 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and reg ister 02h = 23h: xor r0,r1 ? r0 = 0c5h, r1 = 02h xor r0,@r1 ? r0 = 0e4h, r1 = 02h, register 02h = 23h xor 00h,01h ? register 00h = 29h, register 01h = 02h xor 00h,@01h ? register 00h = 08h, register 01h = 02h, register 02h = 23h xor 00h,#54h ? register 00h = 7fh in the first example, if working register r0 contains the value 0c7h and if register r1 contains the value 02h, the statement "xor r0,r1" logically exclusive- ors the r1 value with the r0 value and stores the result (0c5h) in the destination register r0.
s3c9654/c9658/p9658 clock circuit 7 - 1 7 clock circuit overview the s3c9654/c9658/p9658 has three oscillation circuit options, a crystal/ceramic oscillation and a rc oscillation and an external clock source. the crystal or ceramic oscillation source provides a maximum 6 mhz clock. the x in and x out pins connect the oscillation source to the on-chip clock circuit. external clock and rc oscillation and crystal/ceramic oscillator circuits are shown in figures 7- 1 , 7-2, and 7-3 . s3c9654/ s3c9658 s3p9658 x out x in figure 7-1. external oscillator x in x out r s3c9654/ s3c9658 s3p9658 figure 7-3. rc oscillator s3c9654/ s3c9658 s3p9658 x out x in figure 7-2. main oscillator circuit (crystal/ceramic oscillator)
clock circuit s3c96 54/c9658/p9658 7 - 2 main oscillator logic to increase processing speed and to reduce clock noise, non-divided logic is implemented for the main oscillator circuit. for this reason, very high resolution waveforms (square signal edges) must be generated in order for the cpu to efficiently process logic operations. clock status during power-down modes the two power-down modes, stop mode and idle mode, affect clock oscillation as follows: ? in stop mo de, the main oscillator "freezes," halting the cpu and peripherals. the contents of the register file and current system register values are retained. reset operation releases the stop mode , and starts the oscillator . ? in idle mode, the internal clock signal is gated off to the cpu, but not to interrupt control and the timer. the current cpu status is preserved, including stack pointer, program counter, and flags. data in the register file is retained. idle mode is released by a reset or by an interrupt (external or internally-generated). system clock control register (clkcon) the system clock control register, clkcon, is located in location d4h. it is read/write addressable and has the following functions: ? oscillator irq wake-up function enable/disable (clkcon.7) ? oscillator frequency divide-by value: non-divided, 2, 8, or 16 (clkcon.4 and clkcon.3) the clkcon register controls whether or not an external interrupt can be used to trigger a stop mode release (this is called the "irq wake-up" function). the irq wake-up enable bit is clkcon.7. after a reset , the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the f osc /16 (the slowest clock speed) is selected as the cpu clock. if necessary, you can then increase the cpu clock speed to f osc , f osc /2 or f osc /8.
s3c9654/c9658/p9658 clock circuit 7 - 3 .7 .6 .5 .4 .3 .2 .1 .0 lsb msb system clock control register (clkcon) d4h, r/w no effect divide-by selection bits for cpu clock frequency: 00 = fosc/16 01 = fosc/8 10 = fosc/2 11 = fosc(non-divided) oscillator irq wake-up enable bit: 0 = enable irq for main system oscillator wake-up function 1 = disable irq for main system oscillator wake-up function no effect figure 7-4. system clock control register (clkcon)
clock circuit s3c96 54/c9658/p9658 7 - 4 main osc noise filter oscillator wake-up oscillator stop clkcon.7 int pin clkcon.4-.3 1/2 1/8 1/16 m u x stop instruction cup clock figure 7-5. system clock circuit diagram
s3c9654/c9658/p9658 reset reset and power-down 8 - 1 8 reset reset and power-down system reset reset overview comparator glitch filter reset reference voltage generator voltage divider start up notes: 1. start up circuit: start up reference voltage generator circuit when device powered. 2. reference voltage generator: supply voltage independent reference voltage generator. (supply voltage must great then 2.5 v) 3. voltage divider: divide supply voltage by "n" (n: integer, 2). 4. comparator: compare reference voltage and divided voltage. 5. glitch filter: remove glitch and noise signal. figure 8-1. lvr (lvd) architecture
reset reset and power-down s3c9654/c9658/p9658 8 - 2 vc (compare voltage) reference voltage divide voltage v dd (supply voltage) normal operation reset operation by lvr notes: 1. lvr operation voltage range: 2.3 v-6.0 v 2. lvr detection voltage ran ge: 3.4 v 0.4 v 3. lvr current consumption: less then 10 ua (normally 5 ua) 4. lvr powered reset release time: more then 500 usec (lvr only, typical) 5. lvr simulation conditions (hspice simulation) temp: -40 - 80 c process veriation: worst to best conditions test voltage: 0.0 v-7.0 v powered slew rate: 5 v/1 usec- 5 v/100 msec figure 8-2. lvr characteristics the fol lowing sequence of events occur during a reset operation: ? all interrupts are disabled. ? the watchdog function (basic timer) is enabled. ? ports 0 and 1 are set to schmitt trigger input mode and all pull-up resistors are disabled. ? peripheral control and data registers are disabled and reset to their initial values. ? the program counter is loaded with the rom reset address, 0100h. ? when the programmed oscillation stabilization time interval has elapsed, the address stored in rom location 0100h (and 0101h) is fetched and executed. note to program the duration of the oscillation stabilization interval, you must make the appropriate settings to the basic timer control register, btcon, before entering stop mode. also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010b ' to the upper nibble of btcon.
s3c9654/c9658/p9658 reset reset and power-down 8 - 3 power-down modes stop mode stop mode is invoked by the instruction stop ( opcode 7fh). in stop mode, the operation of the cpu and all peripherals is halted. that is, the on-chip main oscillator stops and the supply current is reduced to less than 1 20 a. all system functions are halted when the clock "freezes," but data stored in the internal register file is retained. stop mode can be released in one of two ways: by a reset signal or by an external interrupt. using reset reset to release stop mode stop mode is released when the reset signal is released and returns to high level. all system and peripheral control registers are then reset to their default values and the contents of all data registers are retained. reset operation automatically selects a slow clock (1/16) because clkcon.3 and clkcon.4 are cleared to '00b'. after the oscillation stabilization interval has elapsed, the cpu executes the system initialization routine by fetching the 16-bit address stored in rom locations 0100h and 0101h. using an external interrupt to release stop mode only external interrupts with an rc-delay noise filter circuit can be used to release stop mode (clock-related external interrupts cannot be used). external interrupts in the ks86c6504/p6508 interrupt structure does not meet this criteria. note that when stop mode is released by an external interrupt, the current values in system and peripheral control registers are not changed. when you use an interrupt to release stop mode, the clkcon.3 and clkcon.4 register values remain unchanged, and the currently selected clock value is used. if you use an external interrupt for stop mode release, you can also program the duration of the oscillation stabilization interval. to do this, you must make the appropriate control and clock settings before entering stop mode. the external interrupt is serviced when the stop mode release occurs. following the iret from the service routine, the instruction immediately following the one that initiated stop mode is executed. note do not use the stop mode when external clock source is being used as the oscillation circuit option. idle mode idle mode is invoked by the instruction idle ( opcode 6fh). in idle mode, cpu operations are halted while select peripherals remain active. during idle mode, the internal clock signal is gated off to the cpu, but not to interrupt logic and timer/counters. port pins retain the mode (input or output) they had at the time idle mode was entered. there are two ways to release idle mode: 1. execute reset . all system and peripheral control registers are reset to their default values and the contents of all data registers are retained. the reset automatically selects a slow clock (1/16) because clkcon.3 and clkcon.4 are cleared to '00b'. if interrupts are masked, reset is the only way to release idle mode. 2. activate any enabled interrupt, causing idle mode to be released. when you use an interrupt to release idle mode, the clkcon.3 and clkcon.4 register values remain unchanged, and the currently selected clock value is used. the interrupt is then serviced. following the iret from the service routine, the instruction immediately following the one that initiated idle mode is executed. note only external interrupts that are not clock-related can be used to release stop mode. to release idle mode, however, any type of interrupt (that is, internal or external) can be used.
reset reset and power-down s3c9654/c9658/p9658 8 - 4 hardware reset reset values tables 8- 1 through 8- 3 list the values for cpu and system registers, peripheral control registers, and peripheral data registers following a reset operation in normal operating mode. the following notation is used in these tables to represent specific reset values: ? a "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. ? an 'x' means that the bit value is undefined following reset . ? a dash (' ?') means that the bit is either not used or not mapped. table 8- 1. register values a fter reset reset register name mnemonic address bit values after reset reset 7 6 5 4 3 2 1 0 g eneral purpose register file & stack area ? 00 ? 7 fh x x x x x x x x working register area ? c0h?cfh x x x x x x x x timer 0 counter register t0cnt d0h 0 0 0 0 0 0 0 0 timer 0 data register t0data d1h 1 1 1 1 1 1 1 1 timer 0 control register t0con d2h 0 0 0 0 0 0 0 0 location d3h is not mapped. clock control register clkcon d4h 0 0 0 0 0 0 0 0 system flag register flags d5h 0 0 0 0 ? ? ? ? locations d6h?d8h are not mapped. stack pointer sp d9h ? ? ? ? ? ? ? ? locations dah ?dbh are not mapped. basic timer control register btcon dch 0 0 0 0 0 0 0 0 basic timer counter register btcnt ddh ? ? ? ? ? ? ? ? location deh is not mapped. system mode register sym dfh ? ? ? ? 0 0 0 0 note : the timer 0 counter, t0cnt, the basic timer counter, btcnt, and comparison result, cdata, are read-only. all other registers are read/write addressable.
s3c9654/c9658/p9658 reset reset and power-down 8 - 5 table 8- 1. register values a fter reset reset (c ontinued) bank 0 register name mnemonic address bit values after reset reset 7 6 5 4 3 2 1 0 por t 0 data register p0 e0 h x x 0 0 0 0 0 0 port 1 data register p1 e1 h x x 0 0 0 0 0 0 port 2 data register p2 e2 h x x x x x x 0 0 port 1 pull-down control pdcon e3 h x x x x 0 0 0 0 comparator control mode register ccon e4 h 0 0 0 0 0 0 0 0 comparison result register cdata e5 h x x 0 0 0 0 0 0 port 0 low nibble control register p0conl e6 h 0 0 0 0 0 0 0 0 port 0 high bit control register p0conh e7 h x x x x 0 0 0 0 port 1 high bit control register p1conh e8h x x x x 0 0 0 0 port 1 low nibble control register p1conl e9h 0 0 0 0 0 0 0 0 port 0 interrupt control register p0int eah x x 0 0 0 0 0 0 port 0 interrupt pending register p0pnd ebh x x 0 0 0 0 0 0 port 1 interrupt control register p1int ech x x 0 0 0 0 0 0 port 1 interrupt pending register p1pnd edh x x 0 0 0 0 0 0 port 2 control/interrupt control and pending register p2conint eeh 0 0 0 0 0 0 0 0 sub oscillator control register subcon efh x 0 x x 0 0 0 0 usb function address register faddr f0h 0 0 0 0 0 0 0 0 control endpoint status register ep0csr f1h 0 0 0 0 0 0 0 0 interrupt endpoint status register ep1csr f2h 0 0 0 0 0 0 0 0 control endpoint byte count register ep0bcnt f3h 0 0 0 0 0 0 0 0 control endpoint fifo register ep0fifo f4h x x x x x x x x interrupt endpoint fifo register ep1fifo f5h x x x x x x x x usb interrupt pending register usbpnd f6h 0 0 0 0 0 0 0 0 usb interrupt enable register usbint f7h 0 0 0 0 0 0 0 0 usb power management register pwrmgr f8h 0 0 0 0 0 0 0 0 locations f9h ? fa h are not mapped. usb mode select register usbsel fbh x x x x x x x 0 locations fch is not mapped. sink current control register snkcon fdh x x x x x x 0 0 usb signal control xcon feh x x 0 0 0 0 0 0 usb reset register usbrst ffh x x x x x x x 0
reset reset and power-down s3c9654/c9658/p9658 8 - 6 notes
s3c9654/c9658/p9658 i/o ports 9 - 1 9 i/o ports overview the s3c9654/c9658/p9658 has two i/o ports ( port 0 , port 1, port 2 at ps/2 mode only ) , 14 pins total . you access these ports directly by writing or reading port data register addresses. for mouse applications, ports 1.0?1.5 are usually configured as mouse sensing input. port 0 is used for button data input. table 9- 1 . s3c9654/c9658/p9658 port configuration overview port function description programmability p 0 .0 bit-programmable i/o port for schmitt trigger input or n-ch open drain output (50 ma). pull-up resistor is assignable to input pin by software and is automatically disabled for output pin. port 0 can be individualy configured as external interrupt input. bit p0.1 ? p0.5 bit-programmable i/o port for schmitt trigger input or push-pull output. pull-up resistors are individually assignable to input pins by software and are automatically disabled for output pins. port 0 can be individualy configured as external interrupt inputs. bit p1.0 ? p1.5 bit-programmable i/o port for schmitt trigger input or push-pull output. pull-up resistors are individually assignable to input pins by software. port 1 can be configured as comparator input or external interrupt inputs. pull-down resistors are individually assignable. (in comparator input). bit p2.0/d- ? p2.1/d+ bit-programmable i/o port for schmitt trigger input or n-ch open drain output. pull-up resistors are individually assignable to input pins by software and are automatically disabled for output pins. port 2 can be individually configured as external interrupt pins. also it can be configured as an usb ports. bit
i/o ports s3c9654/c9658/p9658 9 - 2 port data registers table 9- 2 gives you an overview of the port data register names, locations, and addressing characteristics. data registers for ports 0 and 1 have the structure shown in figure 9- 1. table 9- 2 . port data register summary register name mnemonic hex r/w port 0 data register p0 e0h r/w port 1 data register p1 e1h r/w port 2 data register p2 e2h r/w p0.4 p1.4 p0.3 p1.3 i/o port ndata register (n = 0-2) .5 .4 .3 .2 .1 .0 msb lsb pn.1 p0.2 p1.2 p0.5 p1.5 pn.0 figure 9- 1 . port data register format
s3c9654/c9658/p9658 i/o ports 9 - 3 port 0, port 1 and port 2 ports 0 , 1 and 2 are bit-programmable, general-purpose, i/o ports. you can select schmitt trigger input mode with rising edge external interrupt or push-pull output mode. port1.0 to port1.5 can be configured as comparator input. you access ports 0, 1 and 2 directly by writing or reading the corresponding port data registers ? p0 (e0h) , p1 (e1h) and p2 (e2h). reset clears the port control registers p0conh, p0conl, p1conh, p1conl and p2conint, to ?00h?, configuring all port 0, port 1, port 2 pins as schmitt trigger inputs. port 0 control register p0conh, e7h, r/w .3 .2 .1 .0 msb lsb p0.5 p0.4 schmitt trigger input, rising edge external interrupt. schmitt trigger input, falling edge ecxternal interrupt with pull-up register. push-pull output mode. not used. 3, 1 0 0 0 1 1 0 1 1 2, 0 port mode selection figure 9-2. port 0 c ontrol registers (p0conh) port 0 control register p0conl, e6h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0.0 p0.1 p0.2 p0.3 p0conl schmitt trigger input, rising edge external interrupt. schmitt trigger input, falling edge ecxternal interrupt with pull-up register. push-pull output mode. (output mode, n-channel open drain: port 0.0 only) not used. port mode selection 0 0 0 1 1 0 1 1 7, 5, 3, 1 6, 4, 2, 0 figure 9- 3 . port 0 control registers (p0conl)
i/o ports s3c9654/c9658/p9658 9 - 4 port 1 control registers p1conh, e8h, r/w, p1conl, e9h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p1.4 p1.5 p1conh p1conl p1.1 p1.0 p1.3 p1.2 schmitt trigger input, rising edge external interrupt. schmitt trigger input, falling edge external interrupt with pull-up register. push-pull output mode. comparator input. port mode selection 0 0 0 1 1 0 1 1 7, 5, 3, 1 6, 4, 2, 0 figure 9-4. control registers (p1conh, p1conl) + + programming tip ? configuring s3c9654/c9658/p9658 port pins to specification this example shows how to configure ports 0? 1 to specification. the programming parameters are as follows: examples: 1. set port 0 push-pull output mode ld p0conl,#0aah ; p0.1?p0.3 ? push-pull output (p0.0 ? open-drain output) 2. set port 1.4?port 1.5 schmitt trigger input mode ld p1conh,#00h ; p1.4?p1.5 ? schmitt trigger input 3. set port 1.0?port 1.3 comparator input mode ld p1conl,#0ffh ; p1.0?p1.3 ? comparator input
s3c9654/c9658/p9658 i/o ports 9 - 5 port 2 control registers p2conint, eeh, r/w .3 .2 .1 .0 msb lsb p2.1, p2.0 interrupt enable bit p2.0 p2.1 p2conint: schmitt trigger input, rising edge external interrupt. schmitt trigger input, falling edge ecxternal interrupt. n-channel open drain output mode. n-channel open drain output mode with pull-up. port mode selection 0 0 0 1 1 0 1 1 7, 5 6, 4 p2.1, p2.0 interrupt enable bit .7 .6 .5 .4 figure 9-5. port control registers (p2conint)
i/o ports s3c9654/c9658/p9658 9 - 6 notes
s3c9654/c9658/p9658 basic timer and timer 0 10 - 1 10 basic timer and timer 0 module overview the s3c9654/c9658/p9658 has two default timers: an 8-bit basic timer and one 8-bit general-purpose timer/counter. the 8 -bit timer/counter is call ed timer 0. basic timer (bt) you can use the basic timer (bt) in two different ways: ? as a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. ? to signal the end of the required oscillation stabilization interval after a reset or a stop mode release. the functional components of the basic timer block are: ? clock frequency divider (f osc divided by 4096, 1024, or 128) with multiplexer ? 8-bit basic timer counter, btcnt (ddh, read-on ly) ? basic timer control register, btcon (dch, read/write) timer 0 timer 0 has t wo operating modes, one of which you select by the appropriate t0con setting: ? interval timer mode ? overflow mode timer 0 has the following functional components: ? clock frequency divider (f osc divided by 4096, 256, or 8) with multiplexer ? 8-bit counter (t0cnt), 8-bit comparator, and 8-bit reference data register (t0data) ? timer 0 overflow interrupt (t0ovf) and match interrupt (t0int) generation ? timer 0 control register, t0con
basic timer and timer 0 s3c9654/c9658/p9658 10 - 2 basic timer control register (btcon) the basic timer control register, btcon, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. a reset clears btcon to '00h'. this enables the watchdog function and selects a basic timer clock frequency of f osc /4096. to disable the watchdog function, you must write the signature code '1010b' to the basic timer register control bits btcon.7?btcon.4. the 8-bit basic timer counter, btcnt, can be cleared at any time during normal operation by writing a "1" to btcon.1. to clear the frequency dividers for both the basic timer input clock and the timer 0 clock, you write a "1" to btcon.0. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb basic timer control register (btcon) dch, r/w watchdog timer enable bits: 1010b = disable watchdog function other value = enable watchdog function basic timer counter clear bits: 0 = no effect 1 = clear btcnt basic timer input clock selection bits: 00 = fosc/4096 01 = fosc/1024 10 = fosc/128 11 = non divide divider clear bit for basic timer and timer 0: 0 = no effect 1 = clear both dividers figure 10- 1. basic timer control register (btcon)
s3c9654/c9658/p9658 basic timer and timer 0 10 - 3 basic timer function description watchdog timer function you can program the basic timer overflow signal to generate a reset by setting btcon.7?btcon.4 to any value other than '1010b' (the '1010b' value disables the watchdog function). a reset clears btcon to '00h', automatically enabling the watchdog timer function. a reset also selects the cpu clock (as determined by the current c lk con register setting) divided by 4096 as the bt clock. a reset whenever a basic timer counter overflow occurs. during normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. to do this, the btcnt value must be cleared (by writing a "1" to btcon.1) at regular intervals. if a system malfunction occurs due to circuit noise or some other error condition, the bt counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. in other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, btcnt) is always broken by a btcnt clear instruction. if a malfunction does occur, a reset is triggered automatically. oscillation stabilization interval timer function you can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt. in stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. the btcnt value then starts increasing at the rate of f osc /4096 (for reset), or at the rate of the preset clock source (for an external interrupt). when btcnt.4 is set , a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the cpu so that it can resume normal operation. in summary, the following events occur when stop mode is released: 1. during stop mode, a power-on reset or an external interrupt occurs to trigger the stop mode re lease and oscillation starts. 2. if a power-on reset occurred, the basic timer counter will increase at the rate of f osc /4096. if an external interrupt is used to release stop mode, the btcnt value increases at the rate of the preset clock source. 3. clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set . 4. when a btcnt.4 is set , normal cpu operation resumes. figure 10- 2 and 10- 3 show the oscillation stabilization time on reset and stop mode release , respectively.
basic timer and timer 0 s3c9654/c9658/p9658 10 - 4 oscillation stabilization time normal operating mode 0.8 v dd t wait = (4096x16)/f osc basic timer increment and cpu operations are idle mode 10000b 00000b reset release voltage note: duration of the oscillator stabilization wait time, t wait , when it is released by a power-on-reset is 4096 x 16/f osc . t rst rc (r is external resistor and c is on chip capacitor) v dd reset internal reset release oscillator (x out ) btcnt clock btcnt value oscillator stabilization time trst ~ rc ~ ~ ~ 0.8 v dd figure 10- 2. oscillation stabilization time on reset reset pin used note: see figure 14-3. for lvd reset
s3c9654/c9658/p9658 basic timer and timer 0 10 - 5 note: duration of the oscillator stabilzation wait time, twait, it is released by an interrupt is determined by the setting in basic timer control register, btcon. v dd oscillation stabilization time reset external interrupt oscillator (x out ) btcnt clock btcnt value t wait basic timer increment 10000b stop release signal 00000b normal operating mode normal operating mode stop mode stop mode release signal stop instruction execution btcon.3 btcon.2 0 0 1 1 0 1 0 1 t wait (4096 x 16)/fosc (1024 x 16)/fosc (128 x 16)/fosc invalid setting t wait (when f osc is 6 mhz) 10.92 ms 2.7 ms 0.341 ms figure 10- 3. oscillation stabilization time on stop mode release
basic timer and timer 0 s3c9654/c9658/p9658 10 - 6 timer 0 control register (t0con) t0con is located at address d2h, and is read/write addressable. a reset clears t0con to '00h'. this sets timer 0 to normal interval match mode , selects an input clock frequency of f osc /4096, and disables the timer 0 overflow interrupt and match interrupt. you can clear the timer 0 counter at any time during normal operation by writing a "1" to t0con.3. the timer 0 overflow interrupt can be enabled by writing a "1" to t0con.1. when a timer 0 overflow interrupt occurs and is serviced by the cpu, the pending condition must be cleared by software by writing a "0" to the timer 0 interrupt pending bit, t0con.0. to enable the timer 0 match interrupt, you must write t0con.1 to "1". to detect an interrupt pending condition, the application program polls t0con.0. when a "1" is detected, a timer 0 match/ capture interrupt is pending. when the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 0 interrupt pending bit, t0con.0. timer 0 interrupt pending bit: 0 = no interrupt pending 0 = clear pending bit (when write) 1 = interrupt is pending (when read) no effect (when write) .7 .6 .5 .4 .3 .2 .1 .0 lsb msb timer 0 control register (t0con) d2h, r/w timer 0 input clock selection bits: 00 = fosc/4096 01 = fosc/256 10 = fosc/8 11 = invalid selection timer 0 operating mode selection bits: 00 = interval match mode 01 = invalid selection 10 = invalid selection 11 = overflow mode timer 0 counter clear bit: 0 = no effect 1 = clear the timer 0 counter (when write) timer 0 match interrupt enable bit: 0 = disable match interrupt 1 = enable match interrupt timer 0 overflow interrupt enable bit: 0 = disable overflow interrupt 1 = enable overflow interrupt figure 10- 4. timer 0 control register (t0con)
s3c9654/c9658/p9658 basic timer and timer 0 10 - 7 timer 0 function description interval match mode in interval match mode , a match signal is generated when the counter value is identical to the value written to the t0 reference data register, t0data. the match signal generates a timer 0 match interrupt and then clears the counter. if for example, you write the value '10h' to t0data, the counter will increment until it reaches '10h' . at this point, the t0 match inte rr upt is generated, the counter value is reset and counting resumes. overflow mode in overflow mode , a overflow signal is generated regardless of the value written to the t0 reference data register when the counter value is overflowed . the overflow signal generates a timer 0 overflow interrupt and then t0 counter is clear ed . counter comparator clk t0int t0data buffer register r match data bus 8 t0data 8 when 8-bit counter is cleared, this buffer is open data bus t0pnd t0ovf figure 10- 5. simplified timer 0 function diagram: interval timer mode
basic timer and timer 0 s3c9654/c9658/p9658 10 - 8 8-bit up counter (btcnt, read-only) ovf bit 1 reset or stop reset data bus when btcnt.4 is set after releasing from reset or stop mode, cpu clock starts. bits 7, 6, 5, 4 write '1010xxxxb' to disable. basic timer control register timer 0 control register 8-bit counter (t0cnt, read-only) 8-bit comparator t0data buffer register r data bus t0data 8 data bus when 8-bit counter is cleared. this buffer is open 8 8 8 match/ overflow bits 5, 4 overflow bit 3 t0clr match signal bit 2 ovint bit 1 t0int bit 0 irq bits 7, 6 bits 3, 2 x in bit 0 f osc 1/128 1/4096 1/1024 1/8 1/256 1/4096 div r div r figure 10-6 . basic timer and timer 0 block diagram
s3c9654/c9658/p9658 universal serial b us 1 1- 1 11 universal serial bus overview universal serial bus (usb) is a communication architecture that supports data transfer between a host computer and a wide range of pc peripherals. usb is actually a cable bus in which the peripherals share its bandwidth through a host scheduled token based protocol. the usb module in s3c9654/c9658/p9658 is designed to serve at a low speed transfer rate (1.5 mbs) usb device as described in the universal serial bus specification revision 1.0. s3c9654/c9658/p9658 can be briefly describe as a microcontroller with sam 87rcri core with an on-chip usb peripheral as can be seen in figure 11-1. the s3c9654/c9658/p9658 comes equipped with serial interface engine (sie), which handles the communication protocol of the usb. the s3c9654/c9658/p9658 supports the following control logic: packet decoding/generation, crc generation/checking, nrzi encoding/decoding, sync detection, eop (end of packet) detection and bit stuffing. s3c9654/c9658/p9658 supports two types of data transfers; control and interrupt. two endpoints are used in this device; endpoint 0 and endpoint 1. please refer to the usb specification revision 1.0 for detail description of usb. sam88rcri core data bus transceiver voltage regulator sie (serial interface engine) endpoint 0 fifo endpoint 1 fifo d+ d- figure 11-1. usb peripheral interface
universal serial bus s3c9654/c9658/p9658 1 1- 2 serial bus interface engine (sie) the serial interface engine interfaces to the usb serial data and handles, deserialization/serialization of data, nrzi encoding/decoding, clock extraction, crc generation and checking, bit stuffing and other specifications pertaining to the usb protocol such as handling inter packet time out and pid decoding. control logic the usb control logic manages data movements between the cpu and the transceiver by manipulating the transceiver and the endpoint register. this includes both transmit and receive operations on the usb. the logic contains byte count buffers for transmit operations that load the active transmit endpoint's byte count and use this to determine the number of bytes to transfer. the same buffer is used for receive transactions to count the number of bytes received and transfer that number to the receive endpoint's byte count register at the end of the transaction. the control logic in s3c9654/c9658/p9658, when transmitting, manages parallel to serial conversion, packet generation, crc generation, nrzi encoding and bit stuffing. when receiving, the control logic in s3c9654/c9658/p9658 handles sync detection, packet decoding, eop (end of packet) detection, bit ( un)stuffing, nrzi decoding, crc checking and serial to parallel conversion bus protocol all bus transactions involve the transmission of packets. s3c9654/c9658/p9658 supports three packet types; token, data and handshake. each transaction starts when the host controller sends a token packet to the usb device. the token packets are generated by the usb host and decoded by the usb device. a token packet includes the type description, direction of the transaction, usb device address and the endpoint number. data and handshake packets are both decoded and generated by the usb device. in any transaction, the data is transferred from the host to a device or from a device to the host. the transaction source then sends a data packet or indicates that it has no data to transfer. the destination then responds with a handshake packet indicating whether the transfer was successful. data transfer types usb data transfer occurs between the host software and a specific endpoint on the usb device. an endpoint supports a specific type of data transfer. the s3c9654/c9658/p9658 supports two data transfer endpoints: control and interrupt. control transfer configures and assigns an address to the device when detected. control transfer also supports status transaction, returning status information from device to host. interrupt transfer refers to a small, spontaneous data transfer from usb device to host. endpoints communication flows between the host software and the endpoints on the usb device. each endpoint on a device has an identifier number. in addition to the endpoint number, each endpoint supports a specific transfer type. s3c9654/c9658/p9658 supports two endpoints: endpoint 0 supports control transfer, and endpoint 1 supports interrupt transfer.
s3c9654/c9658/p9658 universal serial b us 1 1- 3 structure of usb and ps/2 combinational port usb signal transceiver (with pull-up) ps/2 signal transceiver (with pull-up) dm dp voltage regulator (3.3 v generation) usb control ps/2 control (p2conint) pull-up enable usb enable [a] [b] [c] note: that block explain usb block can be enabled or disabled with pull-up by s/w. voltage regulator also disabled automatically when usb block was disabled. and ps/2 block can be controlled by software with pull-up. figure 11-2. block diagram of usb and ps/2 transceiver
universal serial bus s3c9654/c9658/p9658 1 1- 4 structure of voltage regulator enable reference voltage generator 3.3 v out current amplifier a b note: this blcok can give a explanation how it can be controlled automatically. when the 3.3 voltage regulator be enable by software, voltage regulator will operating to cover fluctuation of the line load, sometimes the line is not stabled and the driving ability will be dropped. as it operating in the normal stage without any peak, power will be supplied with 8 ma, and when the operating. current consumption go to peak, it was designed to cover by 50 ma. it means any kind of load problem will be compensated with above design. figure 11-3. block diagram of voltage regulator
s3c9654/c9658/p9658 universal serial b us 1 1- 5 structure of usb signal transmitter ctrl d- d+ bias clamp a b v33in control sinals enable dm tx/rx c d dm dp pull-up control r, 1.5 k w note: we didn't used the by-pass capacitor on the 3.3 v out, since the 3.3 v regulator and clamp circuit will give a solution through the feedback. usb block was designed to cover the line load, the typical value designed is 300 pf (max: 650 pf). the calmp block operating after it detect the voltage variation (actually the current fluctuation will be feedback into voltage variation, di/dt to dv/dt variation. bias control the slope. control signals means nrzi, eop, xcon, in/out. enable is for the tx, rx. internal pull-up resistor will be 1.5 k w dp tx/rx figure 11-4. block diagram of usb signal transceiver
universal serial bus s3c9654/c9658/p9658 1 1- 6 structure of ps/2 signal transmitter v dd dm_drvp dm_drvn dm ps/2 data pull-up enable v dd dp_drvp dp_drvn dp ps/2 clk pull-up enable note: it explain the ps/2 block. the pull-up resistor value will be 4.3 k w 20 % (vport = 0 v) this block can be controlled with pull-up resistor and it was designed with totally different from usb. 4.3 k w 4.3 k w figure 11-5. block diagram of ps/2 signal transmitter
s3c9654/c9658/p9658 universal serial b us 1 1- 7 usb function address register (faddr) this register holds the usb address assigned by the host computer. usbaddr is located at address f0h and is read/write addressable. bit7 not used bit6?0 faddr: mcu updates this register once it decodes a set_address command. mcu must write this register before it clears out_pkt_rdy (bit0) and sets data_end (bit3) in the ep0stu register. the function controller use this register's value to decode usb token packet address. at reset, if the device is not yet configured the value is reset to 0. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb usb function address register (faddr) f0h, r/w 7-bit programming device address. this register maintains the usb address assigned by the host. the function controller uses this register's value to decode usb token packet address. at reset when the device is not yet configured the value is reset to 0. not used figure 11-6. usb function address register (faddr)
universal serial bus s3c9654/c9658/p9658 1 1- 8 control endpoint status register (ep0csr) ep0csr register controls endpoint 0 (control endpoint), and also holds status bits for endpoint 0. ep0csr is located at f1h and is read/write addressable. bit7 clear_setup_end: mcu writes ?1? to this bit to clear setup_end bit (bit4). this bit is automatically cleared after writing "1" by usb block. bit6 clear_out_pkt_rdy: mcu writes ?1? to this bit to clear out_pkt_rdy bit (bit0). this bit is automatically cleared after writing "1" by usb block. bit5 send_stall: mcu writes ?1? to this bit to send stall signal to the host, at the same time it clears out_pkt_rdy (bit0), if it decodes an invalid token. usb issues a stall handshake to the current control transfer. this bit gets cleared once a stall handshake is issued to the current control transfer. bit4 setup_end: usb sets this bit, when a control transfer ends before data_end bit (bit3) is set. mcu clears this bit, by writing a ?1? to serviced_setup_end bit (bit7). when usb sets this bit, an interrupt is generated to mcu. when such condition occurs, usb flushes the fifo, and invalidates mcu?s access to fifo. bit3 data_end: mcu sets this bit: ? after loading the last packet of data into the fifo, and at the same time in_pkt_rdy bit is set. ? while it clears out_pkt_rdy bit after unloading the last packet of data. ? for a zero length data phase, when it clears out_pkt_rdy bit, and sets in_pkt_rdy bit. bit2 sent_stall: usb sets this bit, if a control transaction has ended due to a protocol violation. an interrupt is generated when this bit gets set. mcu clears this bit to end the stall condition. bit1 in_pkt_rdy: mcu sets this bit, after writing a packet of data into endpoint 0 fifo. usb clears this bit, once the packet has been successfully sent to the host. an interrupt is generated when usb clears this bit so that mcu can load the next packet. for a zero length data phase, mcu sets in_pkt_rdy bit and data_end bit at the same time. bit0 out_pkt_rdy: usb sets this bit, once a valid token is written to fifo. an interrupt is generated, when usb sets this bit. mcu clears this bit by writing "1? to serviced_out_pkt_rdy bit. notes: 1. in control transfer case, where there is no data phase, mcu after unloading the setup token, sets in_pkt_rdy, and data_end at the same time it clears out_pkt_rdy for the setup token. 2. when setup_end bit is set, out_pkt_rdy bit may also be set. this happens when the current transfer has ended, and a new control transfer is received befor e mcu can service the interrupt. in such case, mcu should first clear setup_end bit, and then start servicing the new control transfer.
s3c9654/c9658/p9658 universal serial b us 1 1- 9 .7 .6 .5 .4 .3 .2 .1 .0 lsb msb control endpoint status register (ep0csr) f1h, r/w clear_ setup_end clear_ out_pkt_rdy send_stall setup_end data_end sent_stall in_pkt_rdy out_pkt_rdy figure 11-7. control endpoint status register (ep0csr)
universal serial bus s3c9654/c9658/p9658 1 1- 10 interrupt endpoint status register (ep1csr) ep1csr is the control register for endpoint 1, interrupt endpoint. this register is located at address f2h and is read/write addressable. bit7 clr_data_toggle: mcu writes ?1? to this bit to clear the data toggle sequence bit. when the mcu writes a 1 to this register, the data toggle bit is initialized to data0. bit6?3 maxp: these bits indicate the maximum packet size for in endpoint, and needs to be updated by mcu before it sets in_pkt_rdy. once set, the contents are valid till mcu re-writes them. bit2 flush_fifo: when mcu writes ?1? to this register, the fifo is flushed, and in_pkt_rdy cleared. the mcu should wait for in_pkt_rdy to be cleared for the flush to take place. bit1 force_stall: mcu writes ?1? to this register to issue a stall handshake to usb. mcu clears this bit, to end the stall condition. bit0 in_pkt_rdy: mcu sets this bit, after writing a packet of data into endpoint 1 fifo. usb clears this bit, once the packet has been successfully sent to the host. an interrupt is generated when usb clears this bit, so mcu can load the next packet. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb control endpoint status register (ep1csr) f2h, r/w clear_data_toggle flush_fifo force_stall in_pkt_rdy maxp figure 11-8. interrupt endpoint status register (ep1csr) control endpoint byte count register (ep0bcnt) ep0bcnt register has the number of valid bytes in endpoint 0 fifo. it is located at address f3h read only addressable. once the mcu receives a out_pkt_rdy (bit0 of ep0csr) for endpoint 0, then it can read this register to find out the number of bytes to be read from endpoint 0 fifo.
s3c9654/c9658/p9658 universal serial b us 1 1- 11 control endpoint fifo register (ep0fifo) this register is bi-directional, 8 byte depth fifo used to transfer control endpoint data. ep0fifo is located at address f4h and is read/write addressable. initially, the direction of the fifo, is from the host to the mcu. after a setup token is received for a control transfer, that is, after mcu unload the setup token bytes, and clears out_pkt_rdy, the direction of fifo is changed automatically from mcu to the host. interrupt endpoint fifo register (ep1fifo) ep1fifo is an uni-direction 8-byte depth fifo used to transfer data from the mcu to the host. mcu writes data to this register, and when finished set in_pkt_rdy. this register is located at address f5h. usb interrupt pending register (usbpnd) usbpnd register has the interrupt bits for endpoints and power management. this register is cleared once read by mcu. while any one of the bits is set, an interrupt is generated. usbpnd is located at address f6h. bit7?4 not used bit3 resume_pnd: while in suspend mode, if resume signaling is received this bit gets set. bit2 suspend_pnd: this bit is set, when suspend signaling is received. bit1 endpt1_pnd: this bit is set, when en dpoint 1 needs to be serviced. bit0 endpt0_pnd: this bit is set, when endpoint 0 needs to be serviced. it is set under any one of the following conditions: ? out_pkt_rdy is set. ? in_pkt_rdy gets cleared. ? sent_stall gets set. ? data_end gets cleared. ? setup_end gets set. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb usb interrupt pending register (usbpnd) f6h, r/w suspend_pnd endpt1_pnd endpt0_pnd not used resume_pnd figure 11-9. usb interrupt pending register (usbpnd)
universal serial bus s3c9654/c9658/p9658 1 1- 12 usb interrupt enable register (usbint) usbint is located at address f7h and is read/write addressable. this register serves as an interrupt mask register. if the corresponding bit = 1 then the respective interrupt is enabled. by default, all interrupts except suspend interrupt is enabled. interrupt enables bits for suspend and resume is combined into a single bit (bit 2). bit7?3 not used bit2 enable_suspend_resume_int: 1 enable suspend and resume interrupt 0 disable suspend and resume interrupt (default) bit1 enable_endpt1_int: 1 enable endpoint 1 interrupt (default) 0 disable endpoint 1 interrupt bit0 enable_endpt0_int: 1 enable endpoint 0 interrupt (default) 0 disable endpoint 0 interrupt .7 .6 .5 .4 .3 .2 .1 .0 lsb msb usb interrupt enable register (usbint) f7h, r/w enable_endpt0_int not used enable_endpt1_int enable_suspend_resume_int figure 11-10. usb interrupt enable register (usbint)
s3c9654/c9658/p9658 universal serial b us 1 1- 13 usb power management register (pwrmgr) pwrmgr register interacts with the host?s power management system to execute system power events such as suspend or resume. this register is located at address f8h and is read/write addressable. bit7?2 reserved: the value read from this bit is zero. bit1 send_resume: while in suspend state, if the mcu wants to initiate resume, it writes ?1? to this register for 10ms (maximum of 15ms), and clears this register. in suspend mode if this bit reads ?1?, usb generates resume signaling. bit0 suspend_state: suspend state is set when the mcu sets suspend interrupt. this bit is cleared automatically when: ? mcu writes ?0? to send_resume bit to end the resume signaling (after send_resume is set for 10ms). ? mcu receives resumes signaling from the host while in suspend mode. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb usb power mangement register (pwrmgr) f8h, r/w suspend_state the value read form this bits is zero send_resume figure 11-11. usb power management register (pwrmgr)
universal serial bus s3c9654/c9658/p9658 1 1- 14 usb reset reset register (usbrst) usbrst register receives a reset signal from the host. this register is located at address ffh and is read/write addressable. bit7?1 not used bit0 usbrst: this bit is set when the host issues an usb reset signal. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb usb reset register (usbrst) ffh, r/w not used usbrst figure 11-12. usb reset reset register (usbrst)
s3c9654/c9658/p9658 comparator 12- 1 1 2 comparator overview p 1 .0 ? p 1 . 5 can be used as a analog input port for a comparator. the reference voltage for the 6 -channel comparator can be supplied either internally or externally at p 1.5 . when an internal reference voltage is used, six channels (p 1 .0?p 1.5 ) are used for analog inputs and the internal reference voltage is varied in 32 levels . if an external reference voltage is input at p 1.5 , the other three pins ( p 1.0?p1 . 4) in port x are used analog input. unused port x pins should be connected to v dd or v ss for current saving. when a conversion is completed, the result is saved in the comparison result register c data . the initial values of the c data are undefined and the comparator operation is disabled by a reset . ? analog c omparator ? internal reference voltage generator (5-bit resolution) ? external reference voltage source at p 1.5 ? comparator mode register (c con ) ? four multiplexed analog data input pins (cin0?cin5) ? 6?channel conversion data result register (cdata) ? 6?bit digital input port (alternatively, i/o port) ? internal reference voltage is varied in 32 levels with hysteresis. function description the comparator compares analog voltage input at cin0?cin5 with an external or internal reference voltage (v ref ) that is selected by ccon register. the result is written to the comparison result register cdata at address e5h. the comparison result is calculated as follows. if ?1? analog input voltage 3 v ref + 100 mv if ?0? analog input voltage v ref ? 100 mv to obtain a comparison result, the data must be read out from the cdata register after v ref is updated by changing the ccon value after a conversion time has elapsed.
comparator s3c9654/c9658/p9658 12- 2 comparator control register (ccon) the comparator control register ccon is an 8?bit register that is used to set the operation mode of the comparator. to initiate a comparison procedure, you write the reference voltage selection data in the comparator control register ccon and set the comparison start of enable bit, ccon.7. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb 6-bit comparator control register (ccon) reference voltage (v ref ) selection bits: v dd x (n + 0.5)/24, n = 0 to 7 v dd x (0.3125 + (n-7)/48), n = 8 to 23 v dd x (0.6458 + (n-23)/24), n = 24 to 31 example: n = 0 vref = 0.104 v (v dd = 5 v) n = 2 vref = 0.313 v n = 7 vref = 1.563 v n = 8 vref = 1.667 v . . . reference selection bits: 1 = cin5: external reference, cin0-4: analog input 0 = inrternal reference, cin0-5: analog input comparison time selection bit: 1 = comparison time (6 x 12 /f cpu ) 0 = comparison time (6 x 192 /f cpu ) comparison start control bit: 1 = start of enable the operation 0 = disable the operation figure 12- 1. comparison control register (ccon)
s3c9654/c9658/p9658 comparator 12- 3 5.00 4.50 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 2 4 6 8 10 12 14 16 18 20 24 26 28 30 step ref volatage internal reference voltage v dd = 5 v 22 figure 12-2. internal reference voltage ( hysteresis)
comparator s3c9654/c9658/p9658 12- 4 block diagram pdcon.[2:0] m u x p0.0/cin0 p0.1/cin1 p0.2/cin2 p0.3/cin3 p0.4/cin4 p0.5/cin5 + - scan signal comparison result register (cmpreg) m u x external vreference interval vreference 6 6 5-19 k w m u x 3 analog input mode p1conh p1conl 2 4 v dd 5 32 step i n t e r n a l b u s 6 4 4 8 8 ccon.[4:0] ccon.5 ccon.6 ccon.7 pdcon.3 6 figure 12-3 . comparator functional block diagram
s3c9654/c9658/p9658 sub rc oscillator 13- 1 1 3 sub rc oscillator overview the s3c9654/c9658/p9658 have a programmable sub rc oscillator. during idle or stop, programmable sub rc oscillator generated interrupt using sub rc oscillator control register (subcon). sub rc oscillator control register (subcon) .7 .6 .5 .4 .3 .2 .1 .0 lsb msb sub rc oscillator control register interrupt pending bit: 1 = no pending 0 = pending sub rc oscillator counter input clock selection bits: 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 f osc /2048 f osc /3072 f osc /4096 f osc /6144 f osc /8192 f osc /12288 f osc /16384 f osc /24576 sub rc oscillator enable bit: 1 = sub oscillator enable; interrupt enable 0 = sub oscillator disable; interrupt disable not used note: f osc = 130 khz typ. when v dd = 5.0 v, t a = 25 c figure 13-1. sub rc oscillator control register
sub rc oscillator s 3c9654/c9658/p9658 13- 2 notes
s3c9654/c9658/p9658 lvr (low voltage reset reset ) 14- 1 1 4 lvr (low voltage reset reset ) overview the s3c9654/c9658/p9658 have a lvr (low voltage reset) for power on reset and voltage reset. comparator glitch filter reset reference voltage generator voltage divider start up figure 14-1. lvr architecture ? low voltage reset generated reset signal. ? start up circuit: star t up reference voltage generator circuit when device powered. ? reference voltage generator: supply voltage indeoendent reference voltage generator. ? voltage divider: divide supply voltage by ?n? ? comparator: compare reference voltage and divided voltage. ? glitch filter: remove glitch and noise signal.
lvr (low voltage reset reset ) s3c9654/c9658/p96 58 14- 2 vc (compare voltage) reference voltage divide voltage v dd (supply voltage) normal operation reset operation by lvr notes: 1. lvr operation voltage range: 2.3 v-6.0 v 2. lvr detection voltage ran ge: 3.4 v 0.4 v 3. lvr current consumption: less then 10 ua (normally 5 ua) 4. lvr powered reset release time: more then 500 usec (lvr only, typical) 5. lvr simulation conditions (hspice simulation) temp: 0 c - 80 c process veriation: worst to best conditions test voltage: 0.0 v - 7.0 v powered slew rate: 5 v/1 usec- 5 v/100 msec figure 14-2. lvr characteristics
s3c9654/c9658/p9658 lvr (low voltage reset reset ) 14- 3 lvr and power on reset reset operations normal operating mode t wait = (4096x16)/f osc basic timer increment and cpu operations are idle mode 10000b 00000b notes: 1. t1 = 500 usc (at normal) 2. t2 = t1 + (4096 x 16)/f osc v dd lvd reset release internal reset release oscillator (x out ) btcnt clock btcnt value oscillator stabilization time t3 oscillation stabilization time t2 t1 lvd reset release time figure 14-3. lvr and power on reset reset operation
lvr (low voltage reset reset ) s3c9654/c9658/p96 58 14- 4 notes
s3c9654/c9658/p9658 electrical data 1 5- 1 1 5 electrical data overview in this section, the following s3c9654/c9658/p9658 electrical characteristics are presented in tables and graphs: ? absolute maximum ratings ? d.c. electrical characteristics ? i/o capacitance ? a.c. electrical characteristics ? oscillator characteristics ? operating voltage range ? oscillation stabilization time ? clock timing measurement points at x in ? data retention supply voltage in stop mode ? stop mode release timing when initiated by a reset ? stop mode release timing when initiated by an external interrupt ? characteristic curves ? comparator electrical characteristics
electrical data s3c9654/c9658/p9658 1 5- 2 table 15- 1 . absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i all ports ? 0.3 to v dd + 0.3 v output voltage v o all o utput ports ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 18 ma all i/o pins active ? 60 output current low i ol one i/o pin active (except p0.0) + 30 ma total pin current for ports 0, 1 , 2 (except p0.0) + 100 p0.0 + 50 operating temperature t a ? 0 to + 85 c storage temperature t stg ? ? 60 to + 150
s3c9654/c9658/p9658 electrical data 1 5- 3 table 15- 2 . d.c. electrical characteristics (t a = 0 c to + 85 c, v dd = 4. 0 v to 5.25 v) parameter symbol conditions min typ max unit input high voltage v ih 1 all input pin s except v ih 2, d+, d? 0.8 v dd ? v dd v v ih2 x in v dd ? 0.5 v dd input low voltage v il 1 all input pin s except v il2 , d+, d? ? ? 0.2 v dd v il2 x in ? ? 0.4 output high voltage v oh v dd = 4. 0 v ? 5.25 v i oh = ? 200 m a all output port s except d+, d? v dd ? 1.0 ? ? output low voltage v ol v dd = 4. 0 v ? 5.25 v i ol = 2 ma all output ports except d+, d?, p0.0 ? ? 0.4 output low current i ol v ol = 0.4 v 50 (4) ma input high leakage current i lih 1 v in = v dd all inputs except i lih 2 except d+, d?, x out ? ? 3 a i lih2 v in = v dd , x in ? ? 20 input low leakage current i lil 1 v in = 0 v all inputs except i lil 2 except d+, d?, x out ? ? ? 3 i lil2 v in = 0 v , x in ? ? ? 20 output high leakage current i loh v out = v dd all output pin s except d+, d? ? ? 3 output low leakage current i lol v out = 0 v all output pins except d+, d? x out , p0.0 ? ? ? 3 pull-up resistors r l1 v in = 0 v, v dd = 5.0 v, port 0, port 1 25 50 100 k w r l2 v in = 0 v , v dd = 5.0 v, port 2 ? 4.3 ? supply current i dd1 normal operation mode , v dd = 4. 0 v ? 5.25 v 6 mhz, cpu clock ? 6.5 15 ma i dd2 idle mode v dd = 4. 0 v ? 5.25 v 6 mhz, cpu clock ? 2 4 i dd3 stop mode, oscillator stop v dd = 5 v 10% ? 20 50 m a note s : 1. supply current does not include current drawn through internal pull-up resistors or external output curre nt load. 2. this parameter is guaranteed, but not tested (include d+, d?). 3. only in 4.0 v to 5.25 v, d+ and d? satisfy the usb spec 1.0. 4. p0.0 designed for direct led current sink, see the snkcon resistor and figure 1-9 (page 1-9).
electrical data s3c9654/c9658/p9658 1 5- 4 table 15- 3 . input/output capacitance (t a = 0 c to + 85 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out except x in, x out i/ o capacitance c io xi/xo capacitance c xi, c xo x in, x out ? 33 ? table 15- 4 . a.c. electrical characteristics (t a = 0 c to + 85 c, v dd = 4. 0 v to 5.25 v) parameter symbol conditions min typ max unit noise filter t nf1h , t nf1l p 1 (rc delay) 100 ? 200 ns 0.8 v dd 0.2 v dd t nf1l t nf1h 0.5 v dd t nf2 figure 15-1. nose filter timing measurement points
s3c9654/c9658/p9658 electrical data 1 5- 5 table 15-5. oscillator characteristics (t a = 0 c + 85 c) oscillator clock circuit test condition min typ max unit main crystal main ceramic (f osc ) x in x out oscillation frequency v dd = 4.0 v?5.25 v ? 6.0 ? mhz external clock x in x out oscillation frequency v dd = 4.0 v?5.25 v ? 6.0 ? mhz rc oscillator x in x out r oscillation frequency v dd = 5.0 v r = 22.6 k r = 8.8 k r = 3.2 k ? ? ? 1.0 2.0 4.0 ? ? ? mhz table 15- 6 . oscillation stabilization time (t a = 0 c + 85 c, v dd = 4. 0 v to 5.25 v) oscillator test condition min typ max unit main crystal v dd = 4. 0 v to 5.25 v , f osc > 6.0 mhz ? ? 10 ms main ceramic (oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range.) oscillator t wait stop mode release time by a reset ? 2 1 6 /f osc ? stabilization wait time t wait stop mode release time by an interrupt ? ? ? note: the oscillator stabilization wait time, t wait , when it is released by an interrupt, is determined by the setting in the basic timer control register, btcon.
electrical data s3c9654/c9658/p9658 1 5- 6 0.4 v t xl t xh x in 1/f osc v dd - 0.5 v figure 15-2. clock timing measurement points at x in table 15- 7 . data retention supply voltage in stop mode (t a = 0 c to + 70 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr stop mode 2.0 ? 6 v data retention supply current i dddr stop mode; v dddr = 2.0 v ? ? 5 a
s3c9654/c9658/p9658 electrical data 1 5- 7 data retention mode ~ ~ ~ v dddr execution of stop instrction v dd normal operating mode idle mode (basic timer active) ~ stop mode t wait 0.8 v dd 0.2 v dd external interrupt figure 15-3. stop mode release timing when initiated by an external interrupt table 15- 8 . comparator electrical characteristics (t a = 0 c to + 85 c, v dd = 4. 0 v to 5.25 v) parameter symbol conditions min typ max unit conversion time (1) t con ? ? 6 12 or 6 192 ? f cpu comparator input voltage v icn ? v ss ? v dd v comparator input impedance r cn ? 2 1000 ? m w comparator reference voltage v ref ? 1.8 ? v dd v comparator input current i cin v dd = 5 v ? 3 ? 3 m a reference input current i ref v dd = 5 v ? 3 ? 3 m a comparator block i com v dd = 5 .5 v ? 1 2 ma current (2) v dd = 4.5 v 0.5 1 ma v dd = 5 v (when power down mode) 100 500 n a notes: 1. conversion time is the time required from the moment a conversion operation starts until it ends. 2. i com is an operating current during conversion.
electrical data s3c9654/c9658/p9658 1 5- 8 table 15-9. low speed source electrical characteristics (usb) (t a = 0 c to + 85 c, internal voltage regulator output v 33out = 2.8 v to 3.6 v, typ 3.3 v) parameter symbol conditions min max unit transition time: rise time tr cl = 200 pf 75 ? ns cl = 650 pf ? 300 fall time tf cl = 200 pf 75 ? cl = 650 pf ? 300 rise/fall time matching trfm ( tr/ tf) cl = 50 pf 80 125 % output signal crossover voltage vcrs cl = 50 pf 1.3 2.0 v internal voltage regulator output voltage v 33out v dd = 4.0 ? 5.25 v 2.8 3.6 v r1 = 15 k w r2 = 1.5 k w cl = 200 pf - 650 pf dm: s/w on dp: s/w off d. u. t test point s/w v 33out r2 r1 c2 90 % measurement points 10 % 90 % 10 % tr tf d-/d+ figure 15-4. usb data signal rise and fall time dm dp v crs max: 2.0 v min: 1.3 v 3.3 v 0 v figure 15-5. usb output signal crossover point voltage
s3c9654/c9658/p9658 mechanical data 1 6- 1 16 mechanical data overview this section contains the following information about the device package: ? package dimensions in millimeters ? pad diagram note : dimensions are in millimeters. 26.80 max 26.40 0 .20 (1.77) 20-dip-300a 6.40 0 .20 #20 #1 0.46 0.10 1.52 0.10 #11 #10 0-15 0.25 + 0.10 - 0.05 7.62 2.54 0.51 min 3.30 0.30 3.25 0.20 5.08 max figure 16-1. 20-dip 300a package dimensions
mechanical data s3c9654/c9658/p9658 1 6- 2 28.85 (2.92) 6.48 #20 #1 1.63 #11 #10 0.38 7.62 2.54 0.89 3.43 0.56 3.51 4.06 9.25 20-dip-300a-sg figure 1 6- 2 . 20-dip-300a-sg package dimensions
s3c9654/c9658/p9658 mechanical data 1 6- 3 note : dimensions are in millimeters. 20-sop-300 7.80 0 .30 #11 #20 #1 #10 14.10 max 13.70 0 .20 (1.14) 0-8 0.20 + 0.10 - 0.05 7.62 5.40 0.20 0.60 0.20 0.05 min 1.70 0.10 2.00 max 0.40 0.10 max + 0.10 - 0.05 1.27 figure 16-3. 20-sop-300 package dimensions
mechanical data s3c9654/c9658/p9658 1 6- 4 23.50 (1.53) 6.48 #18 #1 #10 #9 0.38 7.62 10.03 1.63 0.56 2.54 0.89 3.18 3.51 4.06 18-dip-300a-sg figure 16-4. 18-dip-300a-sg package dimensions
s3c9654/c9658/p9658 mechanical data 1 6- 5 #1 #9 #10 #18 10.41 18.06 0.48 2.64 1.27bsc 18-sop-bd300-an 0-8 0.32 7.59 1.02 0.29 figure 16-5. 18-sop-bd300-an package dimensions
mechanical data s3c9654/c9658/p9658 1 6- 6 19.23 (0.53) 6.48 #16 #1 #9 #8 0.38 7.62 10.03 2.54 1.63 0.56 0.89 3.43 3.51 4.06 16-dip-300a-sg figure 16-6. 16-dip-300a-sg package dimensions
s3c9654/c9658/p9658 mechanical data 1 6- 7 #1 #8 #9 #16 10.50 10.56 2.65 1.27bsc 0.48 16-sop-bd300-sg 0-8 0.32 7.60 1.27 0.30 figure 16-7. 16-sop-bd300-sg package dimensions
mechanical data s3c9654/c9658/p9658 1 6- 8 notes
s3c9654/c9658/p9658 s3p9658 otp 17- 1 17 s3p9658 otp overview the s3p9658 single-chip cmos microcontroller is the otp (one time programmable) version of the s3p9658 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the s3p9658 is fully compatible with the s3p9658, both in function and in pin configuration. because of its simple programming requirements, the s3p9658 is ideal for use as an evaluation chip for the s3p9658. s3p9658 p0.3/int0 v dd p2.0/d-/int2 p2.1/d+/int2 reset/ reset reset x in x out test/ test p0.1/int0 p0.5/int0 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 p0.2/int0 v ss /v ss p0.0/int0 sclk / p1.0/com0/int 1 sdat / p1.1/com1/int 1 p1.2/com2/int1 p1.3/com3/int1 p1.4/com4/int1 p1.5/com5/int1 p0.4/int0 note: the bold is indicate an otp pin name. figure 17-1. s3p9658 pin assignments (20 pin)
ks86p6504/p6508 otp s3c9654/c9 658/p9658 17- 2 s3p9658 p0.3/int0 v dd / v dd p2.0/d-/int2 p2.1/d+/int2 reset / reset reset x in x out test/ test p0.1/int0 18 17 16 15 14 13 12 11 10 p0.2/int0 v ss /v ss p0.0/int0 sclk /p1.0/com0/int1 sdat /p1.1/com1/int1 p1.2/com2/int1 p1.3/com3/int1 p1.4/com4/int1 p1.5/com5/int1 1 2 3 4 5 6 7 8 9 note: the bold is indicate an otp pin name. figure 17-2. s3p9658 pin assignments (18 pin) s3p9658 v dd / v dd p2.0/d-/int2 p2.1/d+/int2 reset / reset reset x in x out test/ test p0.1/int0 16 15 14 13 12 11 10 9 v ss /v ss p0.0/int0 sclk /p1.0/com0/int1 sdat /p1.1/com1/int1 p1.2/com2/int1 p1.3/com3/int1 p1.4/com4/int1 p1.5/com5/int1 1 2 3 4 5 6 7 8 note: the bold is indicate an otp pin name. figure 17-3. s3p9658 pin assignments (16 pin)
s3c9654/c9658/p9658 s3p9658 otp 17- 3 table 17-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin number (20 dip) i/o function p1.0 sdat 5 i/o serial data pin (output when reading, input when writing) input and push-pull output port can be assigned p1.1 sclk 4 i/o serial clock pin (input only pin) reset reset 16 i 0 v : otp write and test mode 5 v : operating mode test v pp (test) 13 i chip initialization and eprom cell writing power supply pin (indicates otp mode entering) when writing 12.5 v is applied and when reading. v dd /v ss v dd /v ss 19/2 i logic power supply pin. table 17-2. comparison of s3p9658 and s3c9654/c9658 features characteristic s3p9658 s3c9654/c9658 program memory 8 k-byte eprom 4/8 k-byte mask rom operating voltage (v dd ) 4.0 v to 5.25 v 4.0 v to 5.25 v otp programming mode v dd = 5 v, v pp (test) = 12.5 v pin configuration 20/18/16 dip, 20/18/16 sop 20/18/16 dip, 20/18/16 sop, 16ssop eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp ( reset ) pin of the s3p9658, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 14-3 below. table 17-3. operating mode selection criteria v dd v pp ( reset reset ) reg/ mem mem address (a15-a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level.
ks86p6504/p6508 otp s3c9654/c9 658/p9658 17- 4 notes
s3c9654/c9658/p9658 development tools 18- 1 18 development tools overview samsung provides a powerf u l and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, for s3c7, s3c9, s3c8 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, a s sembler, and a program for setting options. shine samsung host interface for i n -circuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, hig hlighted, added, or removed compl etely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm86 the sasm86 is an relocatable assembler for samsung's s3c9 -series microcontrollers. the sasm86 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm86 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code(.obj file) by hex2rom, the value 'ff' is filled into the unused rom area upto the maximum rom size of the targe t device automatically.
development tools s3c9654/c9658/p9658 18- 2 target boards target boards are available for all s3c9 -series microcontrollers. all required target system cables and adapters are included with the device-specific target board. otp s one times programmable microcontrollers ( otps) are under development for s3c9654/c9658/p9658 microcontroller. bus smds2+ rs-232c pod probe adapter prom/otp writer unit ram break/display unit trace/timer unit sam8 base unit power supply unit ibm-pc at or compatible tb9654/8a target board eva chip target application system figure 18-1 . smds product configuration (smds2+)
s3c9654/c9658/p9658 development tools 18- 3 tb9654/8a target board the tb9654/8a target board is used for the s3c9654/c9658/p9658 microcontroller s . it is supported by the smds2+ development system. tb9654/8a sm1330a gnd v cc + idle + stop j101 20-pin socket 20 1 10 11 100-pin connector 25 1 reset to user_v cc off on u2 external triggers ch1 ch2 sw1 smds2 smds2+ 144 qfp s3e9600x eva chip 1 36 figure 18-2 . tb9654/8a target board configuration
development tools s3c9654/c9658/p9658 18- 4 table 18-1. power selection settings for tb9654/8a 'to user_vcc' settings operating mode comments to user_v cc off on target system smds2/smds2+ tb9654/8a v cc v ss v cc smds2 /smds2+ supplies v cc to the target board (evaluation chip) and the target system. to user_v cc off on target system smds2+ tb9654/8a external v cc v ss v cc smds2 /smds2+ supplies v cc only to the target board (evaluation chip). the target system must have a power supply of its own . smds2+ selection (sam8) in order to write data into program memory available in smds2+, the target board should be selected for smds2+ through a switch as follows. otherwise, the program memory writing function is not available. table 18-2 . the smds2+ tool selection setting 'sw1' setting operating mode smds2 smds2+ target board smds2+ r/w* r/w*
s3c9654/c9658/p9658 development tools 18- 5 table 18-3 . using single header pins as the input path for external trigger sources target board part comments external triggers ch1 ch2 connector from external trigger sources of the application system you can connect an external trigger source to one of the two external trigger channels (ch1 or ch2) for the smds2+ breakpoint and trace functions. 20-pin sop/dip socket j101 p0.3/int0 (note) v dd p2.0/d-/int2 p2.1/d+/int2 reset x in x out test p0.1/int0 p0.5/int0 (note) 20 19 18 17 16 15 14 13 12 11 (note) p0.2/int0 v ss p0.0/int0 p1.0/com0/int1 p1.1/com1/int1 p1.2/com2/int1 p1.3/com3/int1 p1.4/com4/int1 p1.5/com5/int1 (note) p0.4/int0 1 2 3 4 5 6 7 8 9 10 note: 16, 18, and 20 sop/dip. figure 18-3 . 20 -pin socket for tb9654/8a
development tools s3c9654/c9658/p9658 18- 6 target board target system part name: as20d order code: sm6304 20-pin sop/dip socket j101 1 10 20 11 1 20 10 11 figure 18-4 . tb9654/8a adapter cable for 20 - sop/di p package
s3c9654/c9658/p9658 appendix 19- 1 1 9 appendix samsung usb controller technical note usb reset signal application: ks86p/c6104, ks86p/c6504, ks86p/c6408. direction: from outside (from host or hub) to usb controller. effect: reset usb part. usb reset signal affect to only usb related r egisters. usb related registers are changed to reset value as below: usb function address register ? 00h ep0 csr register ? 00h ep0 byte count register ? 00h ep1 csr register ? 00h usb interrupt enable register ? 03h usb interrupt pending register ? 00h usb power management register ? 00h notice to mcu: when usb module receive usb reset signal from outside then set usbrst register. usbrst register ? 01h (this means usb controller have received usb res et signal) usb reset flag of usbrst register is sticky so during the reset signal this flag can not be cleared by mcu. after finishing the reset register this flag can be cleared by mcu. notes: 1. usb reset signal does not effect the mcu's register or state it only affect to usb part (usb module). 2. the effect of usb reset signal and hardware reset is same except for usbrst register. 3. if you power on the usb controller the usb reset flag is set so you should clear this flag in your initial rou tine.
appendix s3c9654/c9658/p9658 19- 2 stall condition application: ks86p/c610x4, ks86p/c6504, ks86p/c6408. condition: 1. in during the a data stage a command pipe sent more data or is requested to return more data than was indicated in the setup stage, it should return stall.(8.5.2.1) 2. in bulk transfer if the endpoint was halted, stall is returned to indicate that the host should not retry the transmission because there is an error on the function.(8.5.1) 3. when a request is received by a device that is not defined for the devi ce, is inappropriate for the current setting of the device, or has values that are note compatible with the request, then a request error exists. the device deals with the request error by returning a stall pid in response to the next data stage transaction or in the status stage of the message.(9.2.7) 4. if an unsupported or invalid request is made to a usb device, the device responds by returning stall in the data or status stage of the request. if the device detects the error in the setup stage, it is preferred that the device returns stall at the earlier of the data of status stage.(9.4) 5. control pipes have the unique ability to return a stall handshake due to function problems in control transfer. related flag: 1. ep0csr.2 (sent stall) this flag set by hardware when the usb module send stall packet to host. 2. ep0csr.5 (send stall) this flag set by mcu if the user want to send stall packet to host. this flag automatically cleared by hardware when send one stall packet to host. 3. ep1csr.1 (for ce stall) this flag set by mcu if the user want to send stall packet to host. if this flag is set by user then usb module continuously send stall packet to host until cleared by mcu. by setting the flag: 1. endpoint 0 (control endpoint) if there is problem and mcu want to send stall during control transfer then mcu should set send stall flag for one time send stall packet . you must notice after send one stall packet this flag cleared by hardware. (see example below) 2. endpoint 1 (interrupt endpoint) if mcu want to send stall packet during interrupt transfer then mcu should set this flag. if this flag is set the usb controller send stall packet continuously. if mcu clear this flag then usb controller stop send stall packet. the hardware does not clear this flag automatically so mcu should clear this flag after solve the stall condition.
s3c9654/c9658/p9658 appendix 19- 3 by hardware: in control transfer, if there is protocol violation then the hardware send stall packet to host automatically and set sent stall flag for noticing mcu. basica lly the blow case, the usb controller send stall packet by hardware. case 1: host send in packet without setup stage. case 2: host send out packet without setup stage. % if the usb controller send stall packet to host then the control transfer is finished. if host send in packet then the hardware treat this is protocol violation. (see example) example: control transfer: the host send in or out packet to function after receiving stall packet. setup stage in transaction in transaction a b d e in a point mcu set send stall flag then the b part is as below; in packet stall packet c host ? function function ? host b part in c point the hardware clear send stall flag and set sent flag. if the function send stall packet to host then the control transfer in finished without status stage so the function expect to receive setup stage. % sent flag does not affect to any state of usb controller. the role of this flag is just notice to mcu. clear this flag or not has no meaning to usb controller. in stall in stall in stall d part in d part the usb controller send stall packet because the control transfer is finished so sending in packet without setup stage is protocol violation. the hardware send stall packet and set sent stall flag continuously until receiving setup packet. setup packet data 0 packet ack packet host ? function host ? function function ? host e part after e part the stall condition is solved. % if you want to set send stall flag then you should set this flag before clearing out_pkt_rdy flag.
appendix s3c9654/c9658/p9658 19- 4 ep1csr usage and implementation. application: ks86p/c6104, ks86p/c6504, ks86p/c6408. direction: endpoint 1 only support in (function ? host) interrupt transfer. contents: bit 7 clear data toggle. bit 6 - bit 3 max packet bit 2 flush fifo bit 1 force stall bit 0 in_pkt_rdy usage: (1) clear data toggle. write "1" to this flag : initialize data toggle sequence. hardware clear this flag after initializing the toggle sequence. note: this flag was prepared for accident. usually not use. until now i use this flag only for test. the data toggle start data0 after reset. (2) max packet. this field use when the user want to limit the max packet. the reset value "1000" so the maximum packet size is 8 bytes. the mcu can not write more data then this value. this value does not define the sending data size, it only define the maximum size. if the mcu write only 3 bytes then the function send only three bytes. usb module have counter which count the number of written data to fifo. example 1) nop; assume internal counter is "0". ; and maxp field is "1000". ld fifo, data; internal counter become "1". ld fifo, data ; internal counter become "2". ld fifo, data ; internal counter become "3". set in_pkt_rdy ; ; after set in_pkt_rdy the mcu should not ; write data until it is cleared. this scheme can ; solve the dual access problem. ; internal counter is 3 so the function send 3 bytes ; to host when the f unction received in packet. example 2) nop; assume internal counter is "0". ; and maxp field is "0100". ld fifo, data; internal counter become "1". ld fifo, data; internal counter become "2". ld fifo, data; internal counter become "3". ld fifo, data; internal counter become "4". ld fifo, data; internal counter stay "4". ; this instruction does not work because the maxp ; field is 4. set in_pkt_rdy; ; internal counter is 4 so the function send 4 bytes ; to host when the function received in packet.
s3c9654/c9658/p9658 appendix 19- 5 (3) flush fifo. this field use when the user want to clear the contents of fifo. if the user write "1" to this flag than clear the whole and initialize the internal counter and generate interrupt signal to mcu. see the example. example) nop; assume internal counter is "0". ld fifo, data ; internal counter become "1". ld fifo, data ; internal counter become "2". ld fifo, data ; internal counter become "3". ld fifo, data ; internal counter become "4". set flush_fifo ; internal counter become "0". ; clear in_pkt_rdy if this bit was set. ; generate interrupt signal to mcu. ; and cleared by hardware. (4) force stall. if this flag is set than the function send stall packet when receive in packet. this flag should be clear by mcu. this is not cleared by hardware. see technical note 1.2. (5) in_pkt_rdy. after loading data to fifo than this flag should be set. see below examples. example) ld fifo, data; assume in_pkt_rdy is "0". ld fifo, data; finish the loading. ; if the function receive in packet then send nak because the value of in_pkt_rdy is "0". set in_pkt_rdy; ; if the function receive in packet then send data ; because the value in_pkt_rdy. ; the value of in_pkt_rdy stay "1". receive the ack from host; ; the value of in_pkt_rdy become to "0". this is ; done by hardware. ; and generate interrupt signal t mcu.
appendix s3c9654/c9658/p9658 19- 6 boundary condition problem. application: ks86p/c6104, ks86p/c6504, ks86p/c6408. direction: boundary condition arise fro m in (dev ? host) direction. condition : 1) happen in control transfer. 2) host want the data exactly the multiple of max packet number. ex) assume the max packet number is 8 and host want 2 bytes. problem: spec does not define exact protocol in this case. case 1, 1) host send setup transaction. 2) host send in packet and device reply 8 bytes. 3) host send in packet and device reply 8 bytes (16 bytes). 4) host send in packet and device reply 8 bytes (24 bytes). 5) host s end out packet for status stage. case 2, 1) host send setup transaction. 2) host send in packet and device reply 8 bytes. 3) host send in packet and device reply 8 bytes (16 bytes). 4) host send in packet and device reply 8 bytes (24 bytes). 5) host send in packet and device reply zero-length packet. 6) host send out packet for status stage. solution: samsung usb controller should reply both cases in one firmware. samsung usb controller can work with two cases like below. (1) usage : in_pkt_rdy, data_end flag. (2) mcu should set these two flag between 4) and 5) in above cases. example) 1. setup transaction. load data to fifo and set in_pkt_rdy.. 2. in-data1-ack, generate interrupt. load second data to fifo. and set in_pkt_rdy. (send 8 bytes, load 8 bytes). 3. in-data0-ack, generate interrupt. load third data to fifo. and set in_pkt_rdy. (send 16 bytes, load 8 bytes). 4. in-data1-ack, generate interrupt. (send 24 byt es). mcu should set in_pkt_rdy and data_end flag at the same time. 5. if host send in packet then device send zero-length packet. and do the status stage. if host send out packet then device send ack. note: if mcu does set in_pkt_rdy in 4 of example then device send stall when received another in packet.
s3c9654/c9658/p9658 appendix 19- 7 usb rst flag usage. application: ks86p/c6104, ks86p/c6504, ks86p/c6408. purpose: this flag made for just monitoring. issue: this flag use usb _rstn signal (this signal come from internal usb module.) as a synchronous set signal. when power on the internal state going to known value. since this transient value this flag set at starting. so mcu should clear this flag before starting the program. note: this flag is use just for monitor. basically the controller itself does not affect from usb reset signal. but some condition this might be needed for some reason. usage: usb reset a b c 1) usbrst flag set from the point 2.5us from a point. 2) this flag cannot clear by mcu between a point and c point. note: ld r0, usbrst ; if r0 is 01h then usb module receive reset ; signal now or before. means present state is ; in after a point. ld usbrst, #00h; ld r0, usbrst ; if r0 is 01h then present state is in b region. ; if r0 is 00h then present state is after c point. 3) this flag can be cleared by mcu after c point. 4) this flag can be writable before a and after c point. note: can write "1" or "0" if present state is not reset region.
appendix s3c9654/c9658/p9658 19- 8 suspend / resume supporting. application: ks86p/c6104, ks86p/c6504, ks86p/c6408. purpose: supporting usb suspend spec. implementation: usb module have a 3 ms counter for this purpose. this counter cleared when usb traffic happen (including keep alive signal) . so this is a idle counter. if there is no usb traffic during 3 ms then generate a suspend interrupt. if mcu receive this interrupt then do a suspend sequence. samsung usb controller have three mode, these are normal, idle, stop. in suspend mode samsung mcu usually using stop mode, in stop mode the oscillator is down, so there is no clock. samsung mcu use d+, d- signal as a clock source when suspend mode. so samsung can detect resume signal without clock and generate a resume interrupt. when mcu receive interrupt signal in stop mode, then the oscillator wake up and go interrupt service routine. usage1: wh en receive resume signal from upstream port. initialization routine; ld usbint, #0ffh; enable interrupt. int nop; here is interrupt service routine label. check interrupt vector; assume this interrupt is suspend. jp suspend; suspend nop; do suspend routine; stop; this means stop oscillator for saving power ; the whole chip action stop. this stop can be recovered from external interrupt (external resume, keystroke, mouse moving, etc.) source. that means if mcu receive interrupt then the oscillator automatically activating and jump to interrupt service routine. in resume case, d- line connected to the clock port of resume detect f/f, so any change from idle mode (idle to reset, idle to k-state) can be detected by this circuit. if this f/f detected action then generate a interrupt to mcu part and going to interrupt routine. int nop; if the mcu receive resume or external interrupt then the pc ; get this address. check interrupt v ector; assume this interrupt is resume. jp resume ; jump to resume interrupt service routine. resume nop; do wakeup process; jp main; jump to main loop;
s3c9654/c9658/p9658 appendix 19- 9 usage2: when usb controller drive resume signal to upstream port. assume suspend mode; receive mouse moving or keystroke; int nop; interrupt service routine. check interrupt source; assume the interrupt source is mouse ; moving or keystroke jp send_resume; jump to resume service routine. send_resume nop; ld pwrmgr, #02h ; start to send resume. ld r1, # some_value; spec says the length of resume signal should ; between 1 ms to 15 ms, so the programmer ; should select adequate value. loop3 nop; dec r1; cp r1, #00h; jp nz, loop3; ld pwrmgr, #00h; end of resume. jp main;
appendix s3c9654/c9658/p9658 19- 10 responding before reset signal. application: ks86p/c6504, ks86p/c6408, ks86p/c6308 problem: samsung usb controller respond to host before reset signal. solution: basically samsung usb cont roller respond to host before reset signal. this violation can be solved by heuristic method which considering transceiver characteristic. above samsung usb controller can support ps2/usb application. samsung usb controller share d+/ps_clk, d-/ps_data pins and can change the port mode. so, before usb reset signal we can use these pins as ps2 input (with pullup in d- pin) mode. and after receive the usb reset signal mcu can change these pins mode to normal usb d+, d-. mcu can read these pins using ps2 input mode. and usb reset signal length is at least 10 ms. mcu can figure it out whether reset or not. usage: initialization code; ld usbsel, #00h; set port mode as a ps2 mode. ld p2conint, #10h; <= ks86p/c6504 case ; set d+ as schmitt trigger input. ; set d- as schmitt trigger input with pull-up. ; this means usb connection established. loop1 ld r0, p2; read port data. cp r0, #00h; check port data. jp nz, loop1 ; if the port data is not zero then go to loop1. ; this loop wait until receive the reset signal. ld r1, #03h ; check three iteration for robustness. ; the length of usb signal is from 2.5 us to 10 ms, ; so 2,3,4 or 5 times checking is enough. loop2 ld r0, p2; cp r0, #00h; jp nz, loop1; if the se0 is too short then this signal is not usb reset signal, so return to loop1. dec r1; cp r1, #00h; jp nz, loop2; ld usbsel, #01h; change from ps2 mode to usb mode. do normal operation ; note: if mcu set transceiver as ps2 mode then the input signal does not go through to usb module, so usb module does not respond to host.
s3c9654/c9658/p9658 appendix 19- 11 internal hardware structure of samsung usb controller. application: ks86p/c6504, ks86p/c6408. ks86p/c6104 1. when the device receive setup transaction with data1 packet. answer) when the device receive setup transaction with data1 packet then the device send ack packet and does not generate interrupt signal. that means the device ignore this transaction since the data pid is not proper. 2. when the device receive setup transaction with data0 packet which have non-8 byte data length. answer) the device respond with ack and generate interrupt to mcu. if the device read ep0cnt register then the device can get the data number of this packet. 3. when the device receive setup transaction which have more then 8 bytes data packet. answer) the device keep first 8bytes data and response with ack packet. and the ep0cnt have the value 8. that means if the device rec eive more than 8 bytes then there is no way to distinguish this one from 8 bytes setup transaction. i upload this issue to usb-if web board and i received positive message. 4. device address scheme. answer) device address is generated by selecting two source. the below is the fragmentation of verilog file. verilog is a hardware description language so the hardware function is same with this statement. i synthesized the hardware using this program. when i designed this one i only think about fi rst set address command but now we must consider the second set address command. fortunately we can solve this issue using firmware. anyway you can figure it out what's going on internal hardware. assign fun_addr = ( device_configured) ? uc_fun_addr_reg: 7'h00; /* this means if the device_configured is 1 then the value of fun_addr is same to uc_fun_addr_reg. and if the device_configured is 0 then the value of fun_addr is zero. */ /* device_configured signal used for detecting the status stage of set address command. before status stage this value is 0 and after status stage this value going to 1. */
appendix s3c9654/c9658/p9658 19- 12 always @( posedge clk or negedge reset) begin if (reset) begin device_configured <= 1'b0; end else begin /* the below is the setting condition of the device_configured signal. after setting this value this signal remain 1 until receive reset signal. */ device_configured <= ( | ( uc_fun_addr_reg) & endpt0_data_end & endpt0_clr_data_end & ~endpt0_setup_end & ~endp t0_set_setup_end) | device_configured; /* set condition of this signal. 1. uc_fun_addr_reg have non-zero value. 2. endpt0_data_end should be 1. (this flag is csr0[3]). 3. endpt0_clr_data_end should be 1. (this means end of status stage.) 4. endpt0_setup_end should be 0. (this means not terminated by another setup transaction.) 5. endpt0_set_setup_end should be 1. (this signal is a setting signal of endpt0_setup_end.) */ end end always @ ( posedge clk or negedge reset) begin if ( ~reset) begin uc_fun_addr_reg <= 7'b00; end else begin /* the below statement means the firmware can change the uc_fun_addr_reg anytime. */ if ( uc_wrt & uc_dec_fun_addr) uc_fun_addr_reg <= uc_data[6:0] ; end end
s3c9654/c9658/p9658 appendix 19- 13 set address command supporting application: ks86p/c6104, ks86p/c6504, ks86p/c6408. purpose: supporting multiple set ad dress command and robustness. implementation: basically above usb controller does not support multiple set address command. but above usb controller can support multiple set address and robustness(missing status stage) using some heuristic method. the sequence of firmware is as below and the flowchart of this scheme is in next page. the below scheme perfectly supports missing status stage situation and multiple set address command using one method. scheme. 1. prepare variable prevaddr(8 bits), devaddr(8 bits) and initialize as below. prevaddr = 8'hff; devaddr = 8'h00; go to 2; 2. wait until receive interrupt. if (received interrupt == endpoint 0 interrupt) then go to 3 else go to 2. 3. if (received command == set address) then go to 4 else execute this command and go to 2. 4. write prevaddr to device address register; write 8'h48 to csr0; devaddr = received address; go to 5; 5. wait until interrupt. if (received interrupt == status stage) then write devaddr to device address register; prevaddr = devaddr; go to 2; else go to 6 ; 6. this state exists for missing status stage situation. if ( prevaddr == 8'hff) then write 8'h00 to device address register. revaddr = 8'h00; go to 2. else go to 2.
appendix s3c9654/c9658/p9658 19- 14 start initialize prevaddr = 8'hff; devaddr = 8'h00; idle set address command? execute command faddr = prevaddr; devaddr = in address; csr0 = 8'h48 status atage? if (prevaddr == 8'hff) {faddr = 9'h00; prevaddr = 8'h00;} faddr = devaddr; prevaddr = devaddr; no no yes yes figure 19-1. set address command supporting
s3c9654/c9658/p9658 appendix 19- 15 decoding tip of ep0 control register value application: ks86p/c6104, ks86p/c6504, ks86p/c6408. purpose: robust decoding scheme of endpoint control status register value. implementation: this part will cover robust way of implementing endpoint 0 csr value. the first one is a description which describe the flow of the implementation. the next one is a flowchart of description. the below description will help you to implement authentic method of endpoint 0 csr as a interrupt service routine. the below scheme assume you use event-driven scheme not polling scheme. if you use polling scheme then you may get another value of ep0csr. i will explain these issues briefly in last part. scheme example 1. idle state (busy waiting & if interrupt occurred then go to step 2). 2. read usbpnd register for checking interrupt source. if the interrupt source is not endpoint 0 then execute appropriate action and go to step 1. else go to 3. 3. check state variable which initialized to idle. if state is set_addr then begin if (csr0 == 00h) then begin ld faddr, devaddr. ld prevaddr, devaddr. go to step 1. end else begin if ( prevaddr == ffh) then begin ld faddr, 00h. ld prevaddr, 00h. go to step 4. end else go to step 4. end end /* this is for supporting multiple set address command. */ see ref, 1.9 else go to 4. 4. read ep0csr and store to csr0 variable. if csr0[4]( setup_end flag) is set then assign state = idle. initialize some variable for preparing next control transfer. assign csr0[4] = 0. go to step 5. else go to step 5.
appendix s3c9654/c9658/p9658 19- 16 5. if csr0[2]( sent_stall) is set then execute appropriate action. assign csr0[2] = 0. go to step 6. else go to step 6 6. if (csr0 == 8'h01h) then begin /*this means this interrupt is come from setup transaction or out transaction.*/ if (state == idle) then begin unload ep0fifo value and decode this command. go to step 7. end else begin if (state == out) then begin unload ep0fifo data and check the number of data byte. if the number of data byte is max_value then assign ep0csr = 8'h40. else ep0csr = 8'h48. go to step 1. else error!!! end end else go to 11. 7. if this is no data stage command then go to step 8. else go to step 9. 8. if this is set address command then begin ld faddr, prevaddr. ld devaddr, in_address. ld ep0csr, 48h. ld state, set_addr. go to step 1. end else begin execute this command. go to step 1. end 9. if this command is in control transfer then begin ld ep0csr, 40h. ld state, in. prepare variable for this transfer. go to 13(ep0fifo loading part). end else go to step 10.
s3c9654/c9658/p9658 appendix 19- 17 10. if this command is out control transfer then begin if (transfer is finished) ld ep0csr, 48h. else ld ep0csr, 40h. go to step 1. end else begin if this command is not supported by mcu then ld ep 0csr, 60h, go to step 1. end 11. if (csr0 == 8'h08) then do nothing and go to step 1. /*you can get this value after set 0ah to ep0csr and receive last in packet from host then the mcu send zero-length data packet and generate interrupt.*/ else go to step 12. 12. if (csr0 == 8'h00) then /*this means the interrupt occurred from status transaction.*/ if (state == in) then go to 13(ep0fifo loading part). else if (state == idle) then go to step 1. else error. else error. (other value is impossible) 13. /* variable definition. */ /* totdb : actual length of data. */ /* reqdb : requested data length. */ /* predb : present data count. */ /* nowcnt : present load count.*/ ld nowcnt, #00h. go to 14. 14. if (( predb == reqdb) || ( predb == totdb)) then begin ld state, idle. ld ep0csr, 0ah. go to step 1. end else go to 15. 15. ld ep0fifo, data. inc nowcnt. inc predb. if ( nowcnt == max_packet) then ld ep0csr, #02h. go to step1. else go to step 14.
appendix s3c9654/c9658/p9658 19- 18 flowchart diagram start ep0 int? no yes idle state==set_addr? ld csr0, ep0csr execute other routine ld faddr, devaddr ld prevaddr, devaddr csr0==00h? prevaddr==ffh? no a ld faddr, #00h ld prevaddr, #00h no yes no yes csr0[4]==1? no ld state, idle csr0[4] = 0 csr0[2]==1? no csr[2] = 0 csr0==01h? yes yes go to out_pkt_rdy implement part a csr0==08h? yes csr0==00h? state==in? yes go to ep0fifo loading part a state==idle? yes this state is impossible error! no no yes no no no figure 19-2. overall part
s3c9654/c9658/p9658 appendix 19- 19 state==idle? yes no data stage? ld ep0csr, 48h set address? no a ld faddr, prevaddr. ld devaddr, prevaddr ld ep0csr, 48h ld state, set_addr no yes in control trans? no out control trans? yes a unload ep0fifo decode data state==out? no finish? initialize prevaddr = 8'hff devaddr = 8'h00 execute command ld ep0csr, 48h no undefined state error! ld ep0csr, 40h no ld ep0csr, 40h ld state, in ld nowcnt, 00h prepare varaible go to ep0fifo loading part a finish? ld ep0csr, 48h unsupported command ld ep0csr, 60h ld ep0csr, 40h ld state, out yes yes no yes yes figure 19-3. out_pkt_rdy implement part
appendix s3c9654/c9658/p9658 19- 20 predb==reqdb? yes nowcnt==max?? a ld state, idle ld ep0csr, 0ah no predb==totdb? no ld ep0fifo, data inc nowcnt inc predb no yes yes ld ep0csr, 02h note: totdb: actual length of data reqdb: requested length of data predb: present value of data count nowcnt: present fifo load data count figure 19-4. ep0fifo loading part
s3c9654/c9658/p9658 appendix 19- 21 ep0csr flag definition 1. clr_setup_end. 1.1. write only flag. if you read this value then you will get always "0". 1.2. the mcu use this flag for clearing setup_end flag. the hardware will automatically clear this flag after clear setup_end flag. 1.3. this flag can not be a interrupt source. 2. clr_out_pkt_rdy. 2.1. write only flag. if you read this value then you will get always "0". 2.2. the mcu use this flag for clearing out_pkt_rdy flag. the hardware will automatically clear this flag after clearing out_pkt_rdy. 2.3. this flag can not be a interrupt source. 3. send_stall. 3.1. write only flag. the hardware will automatically clear after setting up send stall condition. 3.2. if you want to send stall to upstream then you should set this flag. after setting the fsm (for send stall in next transaction) this flag cleared by hardware. 3.3. actually this flag can not be a direct source of interrupt but can be a second source of interrupt. after sent stall packet the sie will set sent_stall flag and generate interrupt to mcu. 4. setup_end. 4.1. read only flag. this flag indicate the termination of control transfer. if the mcu set data_end flag and do a successful status stage then the control transfer is terminated by normally. in this case this flag will not be set. that means this flag will be set when the control transfer is terminated without data_end setting or terminated by new setup transaction or protocol violation(in this case, the sie will send stall and set sent_stall flag). you will get "1" value in above situation when interrupt occurred. 4.2. if you get "1" value when you get interrupt then you should clear this flag using clr_setup_end flag and should initialize state variable for next new control transfer. according to protocol, the next transaction should be a setup transaction. 4.3. this flag is source of interrupt. when this flag do a transaction from "0" to "1", the sie will generate a interrupt to mcu. 5. data_end. 5.1. read/write flag. but automatically cleared by hardware after sending status packet in status stage. 5.2. setting this flag means that mcu will only accepts status stage. so if the controller receive another transaction then the mcu will send stall packet (except for setup transaction). if the mcu receive new setup transaction then the hardware will clear this flag and set setup_end flag. 5.3. this can be a source of interrupt. when this flag do a transition from "1" to "0", the sie will generate a interrupt to mcu.
appendix s3c9654/c9658/p9658 19- 22 6. sent_stall. 6.1. read/clear flag. if mcu receive interrupt and get this value set then mcu should clear this flag through writing "0" to this flag. 6.2. if the sie sent stall to upstream then this flag will be set. there are two source which send stall to upstream, the one is set send_stall flag by mcu and the other case is by sie automatically when the host do a protocol violation. the below is the example of protocol violation which the sie send stall automatically. example) a. if the host send in or out token without setup transaction. b. if the host send in status transaction on in control transfer. c. if the host send out status transaction on out control transfer. d. if the host send out status transaction on non-data transfer. 6.3. this can be a source of interrupt. when this flag do a transition from "0" to "1", the sie will generate a interrupt to mcu. 7. in_pkt_rdy. 7.1. read/write flag. this value can be set by mcu but cleared by hardware after successful in transaction. 7.2. after loading the data to endpoint 0 fifo the mcu should set this flag. the mcu can not write data to endpoint 0 fifo during this flag is set. since set this flag means that data loading is finished. and if the controller receive in token then send these data to upstream. and if this value is "0" when received in token then the sie will send nak packet to upstream. if mcu set this flag without data loading then the sie will send zero-length data packet to upstream. if the mcu did not receive ack packet after sending loaded data then this value stay "1" and will retry in next in transaction. 7.3. this can be a source of interrupt. when this flag do a transition from "1" to "0", the sie will generate a interrupt to mcu. 8. out_pkt_rdy. 8.1. read only flag. this value can be set by sie but cleared by mcu through setting clr_out_pkt_rdy flag. 8.2. if the controller receive setup transaction in idle state and receive out transaction during data stage of out control transfer then the sie set this flag and generate interrupt to mcu. if the mcu get this value set then should download the data to local buffer. the mcu can not write data to endpoint 0 fifo if this value is set. so if mcu want to write data to endpoint 0 fifo then should clear this flag before loading. if the controller receive in or out transaction during this value set then the sie send nak to upstream. but if the mcu receive setup transaction then the sie set setup_end flag and set this flag and generate interrupt again. 8.3. this can be a source of interrupt. when this value do a transition from "0" to "1" the sie generate a interrupt to mcu.
s3c9654/c9658/p9658 appendix 19- 23 9. interrupt source. 9.1. data_end flag : "1" ? "0". 9.2. sent_stall : "0" ? "1". 9.3. in_pkt_rdy : "1" ? "0". 9.4 out_pkt_rdy : "0" ? "1". 10. possible value of ep0csr when you get interrupt and appropriate action. ?? the first two flag ( clr_setup_end, clr_out_pkt_rdy) are always "0" value when you read so i will explain just low 6 bits. ?? if the mcu did not clear sent_stall flag then this value remain "1" until cleared. so sent_stall can be set to any combination with below. 10.1. "000001" : set out_pkt_rdy. if you get this value then you should check your state variable. if the state is in out control transfer then this interrupt notice the receiving of out data transfer. so you should download the fifo data and clear this flag and do a appropriate action. if the state is in idle then this interrupt means that the controller receive new setup transaction so download the fifo data and should decode and do a appropriate action. 10.2. "000100" : set sent_stall. if the controller sent stall to upstream then this value be set by sie. this flag is for just monitoring. so just clearing this flag is enough action. 10.3. "001000" : set data_end flag. actually this flag does not a generate interrupt condition. when you set in_pkt_rdy and data_end flag at the same time and the controller receive in transaction and send data and receive ack packet then only in_pkt_rdy flag is cleared and generate interrupt. in this case you can get this value set but there is no meaning so just leave these alone is enough action. 10.4. "010000" : set setup_end. if the former control transfer is terminated by abnormally then this flag is set by hardware. so if mcu got this value then should clear this flag and initialize some variable and should prepare future control transfer. 10.5. "010001" : set setup_end and out_pkt_rdy. if the former transfer is terminated by new setup transaction then mcu can get this value. if the mcu get this value then should initialize variable and reset the status variable according to new command. 10.6. "000000" : nothing is set. this value can get in two case. if the former control transfer is terminated with data_end setting. the other case is happen in data stage of in control transfer. in in control transfer if you load data to endpoint 0 fifo and set in_pkt_rdy and the controller receive in token and send data and receive ack packet then the sie clear in_pkt_rdy and generate interrupt.
appendix s3c9654/c9658/p9658 19- 24 notes

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