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1 dual 3+1 pwm controller with current monitor for imvp-7/vr12? cpus ISL95839 the ISL95839 pulse width modu lation (pwm) controller ic provides a complete solution for imvp-7/vr12? compliant microprocessor and graphic proce ssor core power supplies. it provides the control and protecti on for two voltage regulators (vrs). the first vr, typical for v core , incorporates 2 integrated drivers and can operate in 3-, 2- or 1-phase configurations. the second vr, typical for graphics , incorporates 1 integrated driver. the two vrs share a serial control bus to communicate with the cpu and achieve lower cost and smalle r board area compared with the two-chip approach. both vrs utilize intersil?s robust ripple regulator r3 technology?. the r3 modulator has numerous advantages compared to traditional modulators, including faster transient response, variable switching freq uency during load transients, and improved light load efficiency due to its ability to automatically change switching frequency. the ISL95839 has several other key features. both outputs support either dcr current sensing with a single ntc thermistor for dcr temperature compensation, or more precise resistor current sensing if desired. both outputs come with remote voltage sense, programmable v boot voltage, i max, and switching frequency, adjustable overcurrent protection and separate power-good signals. features ? serial data bus ?dual outputs: - configurable 3-, 2- or 1-phase for the 1st output using two integrated gate drivers - 2nd output using an integrated gate driver ?r3? modulator - excellent transient response - high light load efficiency ? 0.5% system accuracy over-temperature ? supports multiple current sensing methods - lossless inductor dcr current sensing - precision resistor current sensing ? differential remote voltage sensing ?programmable v boot voltage at start-up ? resistor programmable i max , switching frequency for both outputs ? output current monitor (imon and imong) ? adaptive body diode conduction time reduction applications ? imvp-7/vr12 compliant computers figure 1. simplified application circ uit figure 2. load line regulation isl6208b driver ISL95839 vr2 vin vr1 vin vin vin 0.80 0.81 0.82 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.90 0.91 30 36 42 48 54 60 66 i out (a) v out (v) 0 6 12 18 24 v in = 19v v in = 12v v in = 8v may 9, 2013 fn8315.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved intersil (and design) and r3 technology? are trademarks ow ned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL95839 2 fn8315.0 may 9, 2013 table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 simplified application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 gate driver timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 multiphase r3? modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 diode emulation and period stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 start-up timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 voltage regulation and load line implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 differential voltage sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 phase current balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ccm switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 dynamic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 vr_hot#/alert# behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 fb2 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 adaptive body diode conduction time reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 supported data and configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 key component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 inductor dcr current-sensing network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 resistor current-sensing network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 programming resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 current balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 slew rate compensation circuit for vid tr ansition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 typical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
ISL95839 3 fn8315.0 may 9, 2013 ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL95839hrtz 95839 hrtz -10 to +100 40 ld 5x5 tqfn l40.5x5 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL95839 . for more information on msl please see techbrief tb363 . pin configuration ISL95839 (40 ld tqfn) top view pin descriptions pin # symbol description 2 imong output current monitor for vr2. 3 imon output current monitor for vr1. 4 ntcg the second thermistor input to vr_hot# circuit. use it to monitor vr2 temperature. 5, 6, 7 sclk, alert#, sda communication bus between the cpu and the vrs. 8 vr_hot# open drain thermal overload output indicator. can be considered part of communication bus with cpu. 9 fb2 there is a switch between the fb2 pin and the fb pin. the swit ch is on when vr1 is in 3-phase and 2-phase mode and is off in 1-phase mode. the components connecti ng to fb2 are used to adjust the compensation in 1-phase mode to achieve optimum performance for vr1. 10 ntc one of the thermistor inputs to vr_hot # circuit. use it to monitor vr1 temperature. 11 isen3 isen3 is the individual current sensing for vr1 phase 3. gnd pad (bottom) 40 39 38 37 36 35 34 33 32 31 29 30 27 28 25 26 23 24 21 22 11 12 13 14 15 16 17 18 19 20 2 1 4 3 6 5 8 7 10 9 ntcg sclk alert# sda vr_hot# fb2 ntc isen2 isen1 isump isumn rtn fb comp ugate2 lgate2 pwm3 lgate1 fbg compg pgoodg vr_on lgate1g pgood phase2 vdd boot2 imon phase1 ugate1 phase1g rtng isumng isen3 ugate1g imong isumpg boot1 boot1g vccp
ISL95839 4 fn8315.0 may 9, 2013 12 isen2 individual current sensing for vr1 phase 2. when isen2 and pwm3 are both pulled to 5v v dd , the controller will disable vr1 phases 3 and 2. 13 isen1 individual current sensing for vr1 phase 1. 14, 15 isump, isumn vr1 droop current sense input. 16 rtn vr1 remote voltage sensing return. 17 fb this pin is the inverting input of the error amplifier for vr1. 18 comp this pin is the output of the error amplifier for vr1. also, a resistor from this pin to gnd programs i max for vr1, and v boot for both vr1 and vr2. 19 pgood power-good open-drain output indicating when vr1 is ab le to supply regulated voltage. pull up externally with a 680 ? resistor to vccp or 1.9k ? to 3.3v. 20 boot1 connect an mlcc capacitor across the boot1 and the phase1 pins. the boot capacitor is charged through an internal boot diode connected from the vccp pin to the boot1 pin, each time the phase1 pin drops below vccp minus the voltage dropped across the internal boot diode. 21 ugate1 output of vr1 phase-1 hi gh-side mosfet gate driver. conn ect the ugate1 pin to the gate of the phase-1 high-side mosfet. 22 phase1 current return path for the vr1 phas e-1 high-side mosfet gate driver. connect th e phase1 pin to the node consisting of the high-side mosfet source, the low-side mosfet dr ain, and the output inductor of vr1 phase 1. 23 lgate1 output of vr1 phase-1 low-side mosfet gate driver. conn ect the lgate1 pin to the gate of vr1 phase-1 low-side mosfet. 24 pwm3 pwm output for vr1 phase 3. when pwm3 is pulled to 5v v dd , the controller will disable vr1 phase 3. 25 vdd 5v bias power. 26 vccp input voltage bias for the internal gate drivers. connect +5v to the vccp pin. decouple with at least 1f of an mlcc capa citor. 27 lgate2 output of vr1 phase-2 low-side mosfet gate driver. conn ect the lgate2 pin to the gate of vr1 phase-2 low-side mosfet. 28 phase2 current return path for vr1 phase-2 high-side mosfet gate driver. connect the phase2 pin to the node consisting of the high-side mosfet source, the low-side mosfet dr ain, and the output inductor of vr1 phase 2. 29 ugate2 output of vr1 phase-2 high-side mosfet gate driver. conn ect the ugate2 pin to the gate of vr1 phase-2 high-side mosfet. 30 boot2 connect an mlcc capacitor across the boot2 and the phase2 pins. the boot capacitor is charged through an internal boot diode connected from the vccp pin to the boot2 pin, each time the phase2 pin drops below vccp minus the voltage dropped across the internal boot diode. 31 boot1g connect an mlcc capacitor across the boot1g and the ph ase1g pins. the boot capacitor is charged through an internal boot diode connected from the vccp pin to the boot1g pin, ea ch time the phase1g pin drops below vccp minus the voltage dropped across the internal boot diode. 32 ugate1g output of vr2 phase-1 high-side mosf et gate driver. connect the ugate1g pin to the gate of vr2 phase-1 high-side mosfe t. 33 phase1g current return path for vr2 phase-1 high-side mosfet ga te driver. connect the phase1g pin to the node consisting of th e high-side mosfet source, the low-side mosfet dr ain, and the output inductor of vr2 phase 1. 34 lgate1g output of vr2 phase-1 low-side mosfet gate driver. conn ect the lgate1g pin to the gate of vr2 phase-1 low-side mosfet. 35 vr_on controller enable input. a high level logic signal on this pin enables the controller. 36 pgoodg power-good open-drain output indicating when vr2 is ab le to supply regulated voltage. pull-up externally with a 680 ? resistor to vccp or 1.9k ? to 3.3v. 37 compg this pin is the output of the error amplifier for vr2. also, a resistor from this pin to gnd programs i max for vr2 and t max for both vr1 and vr2. 38 fbg this pin is the inverting input of the error amplifier for vr2. 39 rtng vr2 remote voltage sensing return. 40, 1 isumng and isumpg vr2 droop current sense input. when isumng is pulled to 5v v dd , all the communication to vr2 is disabled. bottom pad gnd signal common of the ic. unless otherwise stated, signals are re ferenced to the gnd pin. in addition, it is the return path for all the low-side mosfet gate drivers. it should also be used as the thermal pad for heat removal. pin descriptions (continued) pin # symbol description
ISL95839 5 fn8315.0 may 9, 2013 block diagram rtn e/a fb idroop current sense isump isumn comp driver driver lgate1 phase1 ugate1 boot1 vccp ov fault pgood _ + _ + + + driver driver lgate2 phase2 ugate2 boot2 ibal fault oc fault pwm3 isen3 isen2 isen1 current balancing digital interface sda alert# sclk driver driver lgate1g phase1g ugate1g boot1g ov fault pgoodg oc fault mode1 dac1 mode2 dac2 temp monitor ntcg ntc vr_hot# t_monitor imax vboot tmax set (a/d) prog vr_on mode d/a a/d idroop idroopg vready rtng 6 e/a fbg idroopg current sense isumpg isumng compg vr2 modulator _ + _ + + + vr1 modulator fb2 circuit vdd gnd imon imong fb2
ISL95839 6 fn8315.0 may 9, 2013 simplified application circuit figure 3. typical ISL95839 application circuit using inductor dcr sensing ntcg gnd vccp +5v ISL95839 l2 l1 isen3 phase2 ugate2 rsum2 rsum1 rn cn ri l3 rsum3 boot2 v+5 vin lgate2 isen2 phase1 ugate1 boot1 lgate1 pwm3 isump isumn o c risen2 risen1 risen3 isen1 vsumn cisen3 cisen2 cisen1 cvsumn l4 gt vcore imong ugate1g rsum4 rng cng rig boot1g vin lgate1g imon isumpg isumng o c rimon vsumng cvsumng cpu vcore phase1g vdd rdroop vr_on pgood vsssense vccsense rntc o c fb vr_on comp rtn pgood ntc rdroopg vsssenseg vccsenseg rntcg o c fbg compg rtng sda sda alert# alert# sclk sclk pgoodg pgoodg vr_hot# vr_hot# rcompg rcomp vcc ugate lgate phase boot pwm fccm gnd isl6208 cimon rimong cimong fb2
ISL95839 7 fn8315.0 may 9, 2013 absolute maximum rating s thermal information supply voltage, vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v battery voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28v boot voltage (boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot-to-phase voltage (boot-phase) -0.3v to +7v(dc) . . . . . . . . . . . . . . . .-0.3v to +9v (<10ns) phase voltage (phase) . . . . . . . . . . . . . . . . -7v (<20ns pulse width, 10j) ugate voltage (ugate) . . . . . . . . . . . . . . . . . . . phase - 0.3v (dc) to boot . . . . . . . . . . . . . . . . . . . . phase - 5v (<20ns pulse width, 10j) to boot lgate voltage . . . . . . . . . . . . -2.5v (<20ns pulse width, 5j) to vdd+0.3v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (vdd +0.3v) open drain outputs, pgood, vr_hot#, alert#. . . . . . . . . . -0.3v to +7v esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 2kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd22-c101a) . . . . . . . . . . . . . . 1k latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 40 ld tqfn package (notes 4, 5) . . . . . . . 32 4 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c maximum junction temperature (plastic package) . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% battery voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75v to 25v ambient temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +100c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications operating conditions: v dd = 5v, t a = -10c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range, -10c to +100c parameter symbol test conditions min (note 6) typ max (note 6) units input power supply +5v supply current i vdd vr_on = 1v 6.4 8.0 ma vr_on = 0v 1 a power-on-reset thresholds v dd power-on-reset threshold vddpor r v dd rising 4.35 4.5 v vddpor f v dd falling 4.00 4.15 v vin power-on-reset threshold vinpor 4.40 4.75 v system and references system accuracy %error (v out ) no load; closed loop, active mode range, vid = 0.75v to 1.52v, -0.5 +0.5 % vid = 0.5v to 0.745v -6 +6 mv vid = 0.25v to 0.495v -10 +10 mv internal v boot 1.0945 1.100 1.1055 v maximum output voltage v out(max) vid = [11111111] 1.52 v minimum output voltage v out(min) vid = [00000001] 0.25 v channel frequency 300khz configuration f sw _300k 277 300 323 khz 350khz configuration f sw _350k 324 350 376 khz 400khz configuration f sw _400k 370 400 430 khz 450khz configuration f sw _450k 412 445 478 khz amplifiers current-sense amplifier input offset i fb = 0a -0.2 +0.2 mv error amp dc gain a v0 90 db error amp gain-bandwidth product gbw c l = 20pf 18 mhz
ISL95839 8 fn8315.0 may 9, 2013 isen imbalance voltage maximum of isens - minimum of isens 1 mv input bias current 20 na power-good and protection monitors pgood low voltage v ol i pgood = 4ma 0.15 0.4 v pgood leakage current i oh pgood = 3.3v 1 a pgood delay tpgd 2.6 ms alert# low 7 12 ? vr_hot# low 7 12 ? alert# leakage current 1 a vr_hot# leakage current 1 a current monitor imon and imong output current i imon isum- pin current = 40a 9.7 10 10.3 a isum- pin current = 20a 4.8 5 5.2 a isum- pin current = 4a 0.875 1 1.125 a i ccmax alert trip voltage v imonmax rising 1.2 v i ccmax alert reset voltage falling 1.14 v imon voltage clamp 1.8 v gate driver ugate pull-up resistance r ugpu 200ma source current 1.0 1.5 ? ugate source current i ugsrc ugate - phase = 2.5v 2.0 a ugate sink resistance r ugpd 250ma sink current 1.0 1.5 ? ugate sink current i ugsnk ugate - phase = 2.5v 2.0 a lgate pull-up resistance r lgpu 250ma source current 1.0 1.5 ? lgate source current i lgsrc lgate - vssp = 2.5v 2.0 a lgate sink resistance r lgpd 250ma sink current 0.5 0.9 ? lgate sink current i lgsnk lgate - vssp = 2.5v 4.0 a ugate to lgate deadtime t ugflgr ugate falling to lgate rising, no load 17 ns lgate to ugate deadtime t lgfugr lgate falling to ugate rising, no load 29 ns bootstrap switch on resistance r f 15 ? reverse leakage i r v r = 25v 0.2 a protection overvoltage threshold ov h vsen rising above setpoint for >1s 145 175 200 mv current imbalance threshold (vr1) one isen above another isen for >3.2ms 23 mv vr1 overcurrent threshold 3-phase - ps0 and 1-phase - all states 56 60 64 a 3-phase - ps1 37 40 43 a 3-phase - ps2 18 20 22 a 2-phase - ps0 56 60 64 a 2-phase - ps1 and ps2 27 30 33 a vr2 overcurrent threshold 1-phase - all states 56 60 64 a electrical specifications operating conditions: v dd = 5v, t a = -10c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range, -10c to +100c (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
ISL95839 9 fn8315.0 may 9, 2013 logic thresholds vr_on input low v il 0.3 v vr_on input high v ih 0.7 v pwm3 pwm output low v 0l sinking 5ma 1.0 v pwm output high v 0h sourcing 5ma 3.5 4.2 v pwm tri-state leakage pwm = 2.5v 1 a ntc and ntcg ntc source current ntc = 1.3v 58 60 62 a vr_hot# trip voltage (vr1 and vr2) falling 0.881 0.893 0.905 v vr_hot# reset voltage (vr1 and vr2) rising 0.924 0.936 0.948 v therm_alert trip voltage (vr1 and vr2) falling 0.920 0.932 0.944 v therm_alert reset voltage (vr1 and vr2) rising 0.962 0.974 0.986 v inputs vr_on leakage current i vr_on vr_on = 0v -1 0a vr_on = 1v 3.5 6 a sclk, sda leakage vr_on = 0v, sclk and sda = 0v and 1v -1 1 a vr_on = 1v, sclk and sda = 1v -2 1 a vr_on = 1v, sda = 0v -21 a vr_on = 1v, sclk= 0v -42 a slew rate (for vid change) fast slew rate 10 mv/s slow slew rate 2.5 mv/s note: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications operating conditions: v dd = 5v, t a = -10c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range, -10c to +100c (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
ISL95839 10 fn8315.0 may 9, 2013 gate driver timing diagram theory of operation multiphase r3? modulator the ISL95839 is a multiphase regulator implementing intel? imvp-7/vr12? protocol. it has two voltage regulators, vr1 and vr2, on one chip. vr1 can be programmed for 1-, 2- or 3-phase operation, and vr2 is 1-phase oper ation. the following description is based on vr1, but also applies to vr2 because they are based on the same architecture. the ISL95839 uses intersil patented r3? (robust ripple regulator?) modulator. the r3? modulator combines the best features of fixed frequency pwm and hysteretic pwm while eliminating many of their shortcomings. figure 4 conceptually shows the multiphase r3? modulato r circuit, and figure 5 shows the operation principles. inside the ic, the modulator uses the master clock circuit to generate the clocks for the slave circuits. the modulator discharges the ripple capacitor c rm with a current source equal to g m v o , where g m is a gain factor. c rm voltage v crm is a sawtooth waveform traversing between the vw and comp voltages. it resets to vw when it hits comp, and generates a one-shot master clock signal. a phase sequencer distributes the master clock signal to the slave circuits. if vr1 is in 3-phase mode, the master clock signal will be distributed to the three phases, and the clock1~3 signals will be 120 out-of-phase. if vr1 is in 2-phase mode, the master clock signal will be distributed to phases 1 and 2, and the clock1 and clock2 signals will be 180 out-of-phase. if vr1 is in 1-phase mode, the master clock signal will be distributed to phase 1 only and will be the clock1 signal. each slave circuit has its own ripple capacitor c rs , whose voltage mimics the inductor ripple current. a g m amplifier converts the inductor voltage into a current source to charge and discharge c rs . the slave circuit turns on its pwm pulse upon receiving the clock signal, and the current source charges c rs . when c rs voltage v crs hits vw, the slave circui t turns off the pwm pulse, and the current source discharges c rs . since the controller works with v crs , which are large-amplitude and noise-free synthesized signals, it achieves lower phase jitter than conventional hysteretic mode and fixed pwm mode controllers. unlike conventional hysteretic mode converters, the ISL95839 uses an error amplifier that allows the controller to maintain a 0.5% output voltage accuracy. pwm ugate lgate 1v 1v t ugflgr t rl t fu t ru t fl t lgfugr figure 4. r 3 ? modulator circuit crm gmvo master clock vw comp master clock phase sequencer clock1 clock2 r i l1 gm clock1 phase1 crs1 vw s q pwm1 l1 r i l2 gm clock2 phase2 crs2 vw s q pwm2 l2 co vo vcrm vcrs1 vcrs2 master clock circuit slave circuit 1 slave circuit 2 r i l3 gm clock3 phase3 crs3 vw s q pwm3 l3 vcrs3 slave circuit 3 clock3
ISL95839 11 fn8315.0 may 9, 2013 figure 6 shows the operation principles during load insertion response. the comp voltage ri ses during load insertion, generating the master clock sign al more quickly, so the pwm pulses turn on earlier, increasing the effective switching frequency, which allows for higher control loop bandwidth than conventional fixed frequency pw m controllers. the vw voltage rises as the comp voltage rises, making the pwm pulses wider. during load release response, th e comp voltage falls. it takes the master clock circuit longer to generate the next master clock signal so the pwm pulse is held off until needed. the vw voltage falls as the comp voltage falls, reducing the current pwm pulse width. this kind of behavior gives the controller excellent response speed. the fact that all the phases share the same vw window voltage also ensures excellent dynamic current balance among phases. diode emulation and period stretching ISL95839 can operate in diode em ulation (de) mode to improve light load efficiency. in de mode , the low-side mosfet conducts when the current is flowing from source to drain and doesn?t allow reverse current, emulating a diod e. as figure 7 shows, when lgate is on, the low-side mosfet carries current, creating negative voltage on the phase node due to the voltage drop across the on-resistance. the controller monitors the current through monitoring the phase node voltag e. it turns off lgate when the phase node voltage reaches zero to prevent the inductor current from reversing the direction and creating unnecessary power loss. if the load current is light enough, as figure 7 shows, the inductor current will reach and stay at ze ro before the next phase node pulse and the regulator is in discontinuous conduction mode (dcm). if the load current is heavy enough, the inductor current will never reach 0a, and the regulator is in ccm although the controller is in de mode. figure 8 shows the operation principle in diode emulation mode at light load. the load gets incremen tally lighter in the three cases from top to bottom. the pwm on-time is determined by the vw window size, therefore is the same, making the inductor current triangle the same in the three cases. the controller clamps the master ripple capacitor voltage v crm and the slave ripple capacitor voltage v crs in de mode to make it mimic the inductor current. it takes the v crm longer to hit comp, naturally stretching the switching period. the inductor current triangles move further apart from each other such that the in ductor current average value is equal to the load current. the reduced switching frequency helps increase light load efficiency. figure 5. r3 ? modulator operation principles in steady state comp vcrm master clock pwm1 vw clock1 pwm2 clock2 hysteretic window pwm3 vcrs3 clock3 vcrs2 vcrs1 vw figure 6. r3 ? modulator operation principles in load insertion response comp vcrm master clock pwm1 vcrs1 vw clock1 pwm2 vcrs2 clock2 pwm3 clock3 vcrs3 vw ugate phase il lgate figure 7. diode emulation
ISL95839 12 fn8315.0 may 9, 2013 start-up timing with the controller's v dd voltage above the por threshold, the start-up sequence begins when vr_on exceeds the logic high threshold. figure 9 shows the typical start-up timing of vr1 and vr2. the controller uses digital soft-start to ramp-up dac to the voltage programmed by the setvid command. pgood is asserted high and alert# is asserted low at the end of the ramp up. similar results occur if vr_on is tied to v dd , with the soft-start sequence starting 2.6ms after v dd crosses the por threshold. voltage regulation and load line implementation after the start sequence, the co ntroller regulates the output voltage to the value set by the vid information per table 1. the controller will control the no-load output voltage to an accuracy of 0.5% over the range of 0.25v to 1.52v. a differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die. il il vcrs il vcrs vcrs vw ccm/dcm boundary light dcm deep dcm vw vw figure 8. period stretching vdd vr_on dac 2.6ms 2.5mv/s vid slew rate vid command voltage pgood alert# ?... figure 9. vr1 soft-start waveforms table 1. vid table vid hex v o (v) 765 43210 0 0 0 0 0 0 0 0 0 0 0.00000 0 0 0 0 0 0 0 1 0 1 0.25000 0 0 0 0 0 0 1 0 0 2 0.25500 0 0 0 0 0 0 1 1 0 3 0.26000 0 0 0 0 0 1 0 0 0 4 0.26500 0 0 0 0 0 1 0 1 0 5 0.27000 0 0 0 0 0 1 1 0 0 6 0.27500 0 0 0 0 0 1 1 1 0 7 0.28000 0 0 0 0 1 0 0 0 0 8 0.28500 0 0 0 0 1 0 0 1 0 9 0.29000 0 0 0 0 1 0 1 0 0 a 0.29500 0 0 0 0 1 0 1 1 0 b 0.30000 0 0 0 0 1 1 0 0 0 c 0.30500 000 011010d0.31000 0 0 0 0 1 1 1 0 0 e 0.31500 0 0 0 0 1 1 1 1 0 f 0.32000 0 0 0 1 0 0 0 0 1 0 0.32500 0 0 0 1 0 0 0 1 1 1 0.33000 0 0 0 1 0 0 1 0 1 2 0.33500 0 0 0 1 0 0 1 1 1 3 0.34000 0 0 0 1 0 1 0 0 1 4 0.34500 0 0 0 1 0 1 0 1 1 5 0.35000 0 0 0 1 0 1 1 0 1 6 0.35500 0 0 0 1 0 1 1 1 1 7 0.36000 0 0 0 1 1 0 0 0 1 8 0.36500 000 11001190.37000 000 110101a0.37500 0 0 0 1 1 0 1 1 1 b 0.38000 0 0 0 1 1 1 0 0 1 c 0.38500 0 0 0 1 1 1 0 1 1 d 0.39000 0 0 0 1 1 1 1 0 1 e 0.39500 0 0 0 1 1 1 1 1 1 f 0.40000 0 0 1 0 0 0 0 0 2 0 0.40500 001 00001210.41000 0 0 1 0 0 0 1 0 2 2 0.41500 0 0 1 0 0 0 1 1 2 3 0.42000 0 0 1 0 0 1 0 0 2 4 0.42500 0 0 1 0 0 1 0 1 2 5 0.43000 0 0 1 0 0 1 1 0 2 6 0.43500
ISL95839 13 fn8315.0 may 9, 2013 0 0 1 0 0 1 1 1 2 7 0.44000 0 0 1 0 1 0 0 0 2 8 0.44500 0 0 1 0 1 0 0 1 2 9 0.45000 0 0 1 0 1 0 1 0 2 a 0.45500 0 0 1 0 1 0 1 1 2 b 0.46000 0 0 1 0 1 1 0 0 2 c 0.46500 0 0 1 0 1 1 0 1 2 d 0.47000 0 0 1 0 1 1 1 0 2 e 0.47500 0 0 1 0 1 1 1 1 2 f 0.48000 0 0 1 1 0 0 0 0 3 0 0.48500 0 0 1 1 0 0 0 1 3 1 0.49000 0 0 1 1 0 0 1 0 3 2 0.49500 0 0 1 1 0 0 1 1 3 3 0.50000 0 0 1 1 0 1 0 0 3 4 0.50500 001 10101350.51000 001 10110360.51500 0 0 1 1 0 1 1 1 3 7 0.52000 0 0 1 1 1 0 0 0 3 8 0.52500 0 0 1 1 1 0 0 1 3 9 0.53000 0 0 1 1 1 0 1 0 3 a 0.53500 0 0 1 1 1 0 1 1 3 b 0.54000 0 0 1 1 1 1 0 0 3 c 0.54500 0 0 1 1 1 1 0 1 3 d 0.55000 0 0 1 1 1 1 1 0 3 e 0.55500 0 0 1 1 1 1 1 1 3 f 0.56000 0 1 0 0 0 0 0 0 4 0 0.56500 010 00001410.57000 010 00010420.57500 0 1 0 0 0 0 1 1 4 3 0.58000 0 1 0 0 0 1 0 0 4 4 0.58500 0 1 0 0 0 1 0 1 4 5 0.59000 0 1 0 0 0 1 1 0 4 6 0.59500 0 1 0 0 0 1 1 1 4 7 0.60000 0 1 0 0 1 0 0 0 4 8 0.60500 010 01001490.61000 0 1 0 0 1 0 1 0 4 a 0.61500 0 1 0 0 1 0 1 1 4 b 0.62000 0 1 0 0 1 1 0 0 4 c 0.62500 0 1 0 0 1 1 0 1 4 d 0.63000 table 1. vid table (continued) vid hex v o (v) 765 43210 0 1 0 0 1 1 1 0 4 e 0.63500 0 1 0 0 1 1 1 1 4 f 0.64000 0 1 0 1 0 0 0 0 5 0 0.64500 0 1 0 1 0 0 0 1 5 1 0.65000 0 1 0 1 0 0 1 0 5 2 0.65500 0 1 0 1 0 0 1 1 5 3 0.66000 0 1 0 1 0 1 0 0 5 4 0.66500 0 1 0 1 0 1 0 1 5 5 0.67000 0 1 0 1 0 1 1 0 5 6 0.67500 0 1 0 1 0 1 1 1 5 7 0.68000 0 1 0 1 1 0 0 0 5 8 0.68500 0 1 0 1 1 0 0 1 5 9 0.69000 0 1 0 1 1 0 1 0 5 a 0.69500 0 1 0 1 1 0 1 1 5 b 0.70000 0 1 0 1 1 1 0 0 5 c 0.70500 010 111015d0.71000 0 1 0 1 1 1 1 0 5 e 0.71500 0 1 0 1 1 1 1 1 5 f 0.72000 0 1 1 0 0 0 0 0 6 0 0.72500 0 1 1 0 0 0 0 1 6 1 0.73000 0 1 1 0 0 0 1 0 6 2 0.73500 0 1 1 0 0 0 1 1 6 3 0.74000 0 1 1 0 0 1 0 0 6 4 0.74500 0 1 1 0 0 1 0 1 6 5 0.75000 0 1 1 0 0 1 1 0 6 6 0.75500 0 1 1 0 0 1 1 1 6 7 0.76000 0 1 1 0 1 0 0 0 6 8 0.76500 0 1 1 0 1 0 0 1 6 9 0.77000 0 1 1 0 1 0 1 0 6 a 0.77500 0 1 1 0 1 0 1 1 6 b 0.78000 0 1 1 0 1 1 0 0 6 c 0.78500 0 1 1 0 1 1 0 1 6 d 0.79000 0 1 1 0 1 1 1 0 6 e 0.79500 0 1 1 0 1 1 1 1 6 f 0.80000 0 1 1 1 0 0 0 0 7 0 0.80500 011 10001710.81000 0 1 1 1 0 0 1 0 7 2 0.81500 0 1 1 1 0 0 1 1 7 3 0.82000 0 1 1 1 0 1 0 0 7 4 0.82500 table 1. vid table (continued) vid hex v o (v) 765 43210
ISL95839 14 fn8315.0 may 9, 2013 0 1 1 1 0 1 0 1 7 5 0.83000 0 1 1 1 0 1 1 0 7 6 0.83500 0 1 1 1 0 1 1 1 7 7 0.84000 0 1 1 1 1 0 0 0 7 8 0.84500 0 1 1 1 1 0 0 1 7 9 0.85000 0 1 1 1 1 0 1 0 7 a 0.85500 0 1 1 1 1 0 1 1 7 b 0.86000 0 1 1 1 1 1 0 0 7 c 0.86500 0 1 1 1 1 1 0 1 7 d 0.87000 0 1 1 1 1 1 1 0 7 e 0.87500 0 1 1 1 1 1 1 1 7 f 0.88000 1 0 0 0 0 0 0 0 8 0 0.88500 1 0 0 0 0 0 0 1 8 1 0.89000 1 0 0 0 0 0 1 0 8 2 0.89500 1 0 0 0 0 0 1 1 8 3 0.90000 1 0 0 0 0 1 0 0 8 4 0.90500 100 00101850.91000 1 0 0 0 0 1 1 0 8 6 0.91500 1 0 0 0 0 1 1 1 8 7 0.92000 1 0 0 0 1 0 0 0 8 8 0.92500 1 0 0 0 1 0 0 1 8 9 0.93000 1 0 0 0 1 0 1 0 8 a 0.93500 1 0 0 0 1 0 1 1 8 b 0.94000 1 0 0 0 1 1 0 0 8 c 0.94500 1 0 0 0 1 1 0 1 8 d 0.95000 1 0 0 0 1 1 1 0 8 e 0.95500 1 0 0 0 1 1 1 1 8 f 0.96000 1 0 0 1 0 0 0 0 9 0 0.96500 1 0 0 1 0 0 0 1 9 1 0.97000 1 0 0 1 0 0 1 0 9 2 0.97500 1 0 0 1 0 0 1 1 9 3 0.98000 1 0 0 1 0 1 0 0 9 4 0.98500 1 0 0 1 0 1 0 1 9 5 0.99000 1 0 0 1 0 1 1 0 9 6 0.99500 1 0 0 1 0 1 1 1 9 7 1.00000 1 0 0 1 1 0 0 0 9 8 1.00500 100 11001991.01000 1 0 0 1 1 0 1 0 9 a 1.01500 1 0 0 1 1 0 1 1 9 b 1.02000 table 1. vid table (continued) vid hex v o (v) 765 43210 1 0 0 1 1 1 0 0 9 c 1.02500 1 0 0 1 1 1 0 1 9 d 1.03000 1 0 0 1 1 1 1 0 9 e 1.03500 1 0 0 1 1 1 1 1 9 f 1.04000 1 0 1 0 0 0 0 0 a 0 1.04500 1 0 1 0 0 0 0 1 a 1 1.05000 1 0 1 0 0 0 1 0 a 2 1.05500 1 0 1 0 0 0 1 1 a 3 1.06000 1 0 1 0 0 1 0 0 a 4 1.06500 1 0 1 0 0 1 0 1 a 5 1.07000 1 0 1 0 0 1 1 0 a 6 1.07500 1 0 1 0 0 1 1 1 a 7 1.08000 1 0 1 0 1 0 0 0 a 8 1.08500 1 0 1 0 1 0 0 1 a 9 1.09000 1 0 1 0 1 0 1 0 a a 1.09500 1 0 1 0 1 0 1 1 a b 1.10000 1 0 1 0 1 1 0 0 a c 1.10500 101 01101ad1.11000 1 0 1 0 1 1 1 0 a e 1.11500 1 0 1 0 1 1 1 1 a f 1.12000 1 0 1 1 0 0 0 0 b 0 1.12500 1 0 1 1 0 0 0 1 b 1 1.13000 1 0 1 1 0 0 1 0 b 2 1.13500 1 0 1 1 0 0 1 1 b 3 1.14000 1 0 1 1 0 1 0 0 b 4 1.14500 1 0 1 1 0 1 0 1 b 5 1.15000 1 0 1 1 0 1 1 0 b 6 1.15500 1 0 1 1 0 1 1 1 b 7 1.16000 1 0 1 1 1 0 0 0 b 8 1.16500 1 0 1 1 1 0 0 1 b 9 1.17000 1 0 1 1 1 0 1 0 b a 1.17500 1 0 1 1 1 0 1 1 b b 1.18000 1 0 1 1 1 1 0 0 b c 1.18500 1 0 1 1 1 1 0 1 b d 1.19000 1 0 1 1 1 1 1 0 b e 1.19500 1 0 1 1 1 1 1 1 b f 1.20000 1 1 0 0 0 0 0 0 c 0 1.20500 110 00001c11.21000 1 1 0 0 0 0 1 0 c 2 1.21500 table 1. vid table (continued) vid hex v o (v) 765 43210
ISL95839 15 fn8315.0 may 9, 2013 1 1 0 0 0 0 1 1 c 3 1.22000 1 1 0 0 0 1 0 0 c 4 1.22500 1 1 0 0 0 1 0 1 c 5 1.23000 1 1 0 0 0 1 1 0 c 6 1.23500 1 1 0 0 0 1 1 1 c 7 1.24000 1 1 0 0 1 0 0 0 c 8 1.24500 1 1 0 0 1 0 0 1 c 9 1.25000 1 1 0 0 1 0 1 0 c a 1.25500 1 1 0 0 1 0 1 1 c b 1.26000 1 1 0 0 1 1 0 0 c c 1.26500 1 1 0 0 1 1 0 1 c d 1.27000 1 1 0 0 1 1 1 0 c e 1.27500 1 1 0 0 1 1 1 1 c f 1.28000 1 1 0 1 0 0 0 0 d 0 1.28500 1 1 0 1 0 0 0 1 d 1 1.29000 1 1 0 1 0 0 1 0 d 2 1.29500 1 1 0 1 0 0 1 1 d 3 1.30000 1 1 0 1 0 1 0 0 d 4 1.30500 110 10101d51.31000 1 1 0 1 0 1 1 0 d 6 1.31500 1 1 0 1 0 1 1 1 d 7 1.32000 1 1 0 1 1 0 0 0 d 8 1.32500 1 1 0 1 1 0 0 1 d 9 1.33000 1 1 0 1 1 0 1 0 d a 1.33500 1 1 0 1 1 0 1 1 d b 1.34000 1 1 0 1 1 1 0 0 d c 1.34500 1 1 0 1 1 1 0 1 d d 1.35000 1 1 0 1 1 1 1 0 d e 1.35500 1 1 0 1 1 1 1 1 d f 1.36000 1 1 1 0 0 0 0 0 e 0 1.36500 1 1 1 0 0 0 0 1 e 1 1.37000 1 1 1 0 0 0 1 0 e 2 1.37500 1 1 1 0 0 0 1 1 e 3 1.38000 1 1 1 0 0 1 0 0 e 4 1.38500 1 1 1 0 0 1 0 1 e 5 1.39000 1 1 1 0 0 1 1 0 e 6 1.39500 1 1 1 0 0 1 1 1 e 7 1.40000 1 1 1 0 1 0 0 0 e 8 1.40500 111 01001e91.41000 table 1. vid table (continued) vid hex v o (v) 765 43210 1 1 1 0 1 0 1 0 e a 1.41500 1 1 1 0 1 0 1 1 e b 1.42000 1 1 1 0 1 1 0 0 e c 1.42500 1 1 1 0 1 1 0 1 e d 1.43000 1 1 1 0 1 1 1 0 e e 1.43500 1 1 1 0 1 1 1 1 e f 1.44000 1 1 1 1 0 0 0 0 f 0 1.44500 1 1 1 1 0 0 0 1 f 1 1.45000 1 1 1 1 0 0 1 0 f 2 1.45500 1 1 1 1 0 0 1 1 f 3 1.46000 1 1 1 1 0 1 0 0 f 4 1.46500 1 1 1 1 0 1 0 1 f 5 1.47000 1 1 1 1 0 1 1 0 f 6 1.47500 1 1 1 1 0 1 1 1 f 7 1.48000 1 1 1 1 1 0 0 0 f 8 1.48500 1 1 1 1 1 0 0 1 f 9 1.49000 1 1 1 1 1 0 1 0 f a 1.49500 1 1 1 1 1 0 1 1 f b 1.50000 1 1 1 1 1 1 0 0 f c 1.50500 111 11101fd1.51000 1 1 1 1 1 1 1 0 f e 1.51500 1 1 1 1 1 1 1 1 f f 1.52000 table 1. vid table (continued) vid hex v o (v) 765 43210 figure 10. differential sensing and load line implementation x 1 e/a dac vid rdroop idroop vdac vdroop fb comp vcc sense vss sense vids rtn vss internal to ic catch resistor catch resistor vr local vo
ISL95839 16 fn8315.0 may 9, 2013 as the load current increases from zero, the output voltage will droop from the vid table value by an amount proportional to the load current to achieve the load line. the controller can sense the inductor current through the intrin sic dc resistance (dcr) of the inductors (as shown in figure 3 on page 6) or through resistors in series with the inductors (as shown in figure 4 on page 10). in both methods, capacitor c n voltage represents the inductor total currents. a droop amplifier converts c n voltage into an internal current source with the gain set by resistor r i . the current source is used for load line implementation, current monitor and overcurrent protection. figure 10 shows the load line implementation. the controller drives a current source i droop out of the fb pin, described by equation 1. when using inductor dcr current sensing, a single ntc element is used to compensate the positive temperature coefficient of the copper winding thus sustaining the load line accuracy with reduced cost. i droop flows through resistor r droop and creates a voltage drop, as shown in equation 2. v droop is the droop voltage required to implement load line. changing r droop or scaling i droop can both change the load line slope. since i droop also sets the overcurrent protection level, it is recommended to first scale i droop based on ocp requirement, then select an appropriate r droop value to obtain the desired load line slope. current monitor the controller provides the curr ent monitor function. imon and imong pin reports the inductor current for bothe vrs respectively. the imon pin outputs a high-speed analog current source that is 1/4 of the droop current flowing ou t of the fb pin as equation 3: a resistor r imon is connected to the imon pin to convert the imon pin current to voltage. a capacitor should be paralleled with r imon to filter the voltage information. the imon pin voltage range is 0v to 1.2v. the controller monitors the imon pin voltage and consid ers that ISL95839 has reached i ccmax when imon pin voltage is 1.2v. imong pin has the same operation principle as imon pin. differential voltage sensing figure 10 also shows the differential voltage sensing scheme. vcc sense and vss sense are the remote voltage sensing signals from the processor die. a unity ga in differential amplifier senses the vss sense voltage and adds it to the dac output. the error amplifier regulates the invertin g and the non-inverting input voltages to be equal, as shown in equation 4: rewriting equation 4 and substi tution of equation 2 gives: equation 5 is the exact equati on required for load line implementation. the vcc sense and vss sense signals come from the processor die. the feedback will be open circuit in the absence of the processor. as figure 10 shows, it is recommended to add a ?catch? resistor to feed the vr local output voltage back to the compensator, and add another ?catch? resistor to connect the vr local output ground to the rtn pin. these resistors, typically 10 ? ~100 ? , will provide voltage feedback if the system is powered up without a processor installed. phase current balancing the controller monitors individual phase average current by monitoring the isen1, isen2, and isen3 voltages. figure 11 shows the recommended current balancing circuit. each phase node voltage is averaged by a low-pass filter consisting of r isen and c isen , and presented to the corresponding isen pin. r isen should be routed to inductor phas e-node pad in order to eliminate the effect of phase node parasitic pcb dcr. equations 6 thru 8 give the isen pin voltages: where r dcr1 , r dcr2 and r dcr3 are inductor dcr; r pcb1 , r pcb2 and r pcb3 are parasitic pcb dcr between the inductor output side pad and the output voltage rail; and i l1 , i l2 and i l3 are inductor average currents. the controller will adjust the ph ase pulse-width relative to the other phases to make v isen1 =v isen2 =v isen3 , thus to achieve i l1 =i l2 =i l3 , when there are r dcr1 =r dcr2 =r dcr3 and r pcb1 =r pcb2 =r pcb3 . using the same components for l1, l2 and l3 will provide a good match of r dcr1 , r dcr2 and r dcr3 . board layout will determine r pcb1 , r pcb2 and r pcb3 . it is recommended to have symmetrical layout for the power delivery path between each inductor and the output voltage rail, such that r pcb1 =r pcb2 =r pcb3 . i droop v cn r i ---------- - = (eq. 1) v droop r droop i droop = (eq. 2) i imon 0.25 i droop = (eq. 3) vcc sense v + droop v dac vss sense + = (eq. 4) vcc sense vss sense ? v dac r droop i droop ? = (eq. 5) figure 11. current balancing circuit internal to ic v o isen3 l3 risen cisen isen2 risen cisen isen1 risen cisen l2 l1 rdcr3 rdcr2 rdcr1 phase3 phase2 phase1 il3 il2 il1 rpcb3 rpcb2 rpcb1 v isen1 r dcr1 r pcb1 + () i l1 = (eq. 6) v isen2 r dcr2 r pcb2 + () i l2 = (eq. 7) v isen3 r dcr3 r pcb3 + () i l3 = (eq. 8)
ISL95839 17 fn8315.0 may 9, 2013 sometimes, it is difficult to implement symmetrical layout. for the circuit shown in figure 11, asymmetric layout causes different r pcb1 , r pcb2 and r pcb3 thus current imbalance. figure 12 shows a recommended differential-sensing current balancing circuit. the current sensing traces should be routed to the inductor pads so they only pick up the inductor dcr voltage. each isen pin sees the average voltage of three sources: its own phase inductor phase-node pad, and the other two phases inductor output side pads. equati ons 9 thru 11 give the isen pin voltages: the controller will make v isen1 = v isen2 = v isen3 , as shown in equations 12 and 13: rewriting equation 12 gives equation 14: and rewriting equation 13 gives equation 15: combining equations 14 and 15 gives: therefore: current balancing (i l1 =i l2 =i l3 ) will be achieved when there is r dcr1 =r dcr2 =r dcr3 . r pcb1 , r pcb2 and r pcb3 will not have any effect. since the slave ripple capacitor voltages mimic the inductor currents, r3? modulator can naturally achieve excellent current balancing during steady state and dynamic operations. figure 13 shows current balancing performance of the evaluation board with load transient of 12a/51a at different rep rates. the inductor currents follow the load current dynamic change with the output capacitors supplying the difference. the inductor currents can track the load current well at low rep rate, but cannot keep up when the rep rate gets into the hundred-khz range, where it?s out of the control loop bandwidth. the controller achieves excellent current balancing in all cases. figure 12. differential-sensing current balancing circuit internal to ic v o isen3 l3 risen cisen isen2 risen cisen isen1 risen cisen l2 l1 rdcr3 rdcr2 rdcr1 phase3 phase2 phase1 il3 il2 il1 rpcb3 rpcb2 rpcb1 risen risen risen risen risen risen v3p v3n v2p v2n v1p v1n v isen1 v 1p v 2n v 3n ++ = (eq. 9) v isen2 v 1n v 2p v 3n ++ = (eq. 10) v isen3 v 1n v 2n v 3p ++ = (eq. 11) v 1p v 2n v 3n ++ v 1n v 2p v 3n ++ = (eq. 12) v 1n v 2p v 3n ++ v 1n v 2n v 3p ++ = (eq. 13) v 1p v 1n ? v 2p v 2n ? = (eq. 14) v 2p v 2n ? v 3p v 3n ? = (eq. 15) v 1p v 1n ? v 2p v 2n ? v 3p v 3n ? == (eq. 16) r dcr1 i l1 r dcr2 i l2 r dcr3 i l3 == (eq. 17)
ISL95839 18 fn8315.0 may 9, 2013 ccm switching frequency the resistor from compg and gnd sets four different switching frequencies: 300khz, 350khz, 400khz and 450khz. please refer to table 8 on page 27 for details. to improve the efficiency at low vid, fixed on-time and period stretching will be implemented and ccm switching frequency will be proportional to the vid. the switching frequency will be stretched to 150khz when vid = 0.25v. the vid starting to period stretching will be 0.5v*f sw_set /300. for example, period stretching will start at vid = 0.5v with 300khz switching frequency setting, and period stre tching will start at vid = 0.75v with 450khz switching frequency setting. modes of operation vr1 can be configured for 3, 2 or 1-phase operation. table 2 shows vr1 configurations and operational modes, programmed by the pwm3 pin and the isen2 pin status, and the ps command. for 2-phase configuration, tie the pwm3 pin to 5v. in this configuration, phases 1 and 2 are active. for 1-phase configuration, tie the pwm3 pin an d the isen2 pin to 5v. in this configuration, only phase-1 is active. in 3-phase configuration, vr1 operates in 3-phase ccm in ps0. it enters 2-phase ccm mode in ps1 by dropping phase 3 and reducing the overcurrent and th e way-overcurrent protection levels to 2/3 of the initial values. it enters 1-phase de mode in ps2 and ps3 by dropping phase 2, phase 3 and reducing the overcurrent and the way-overcurrent protection levels to 1/3 of the initial values. in 2-phase configuration, vr1 operates in 2-phase ccm in ps0. it enters 1-phase ccm mode in ps1, and enters 1-phase de mode in ps2 and ps3 by dropping phase 2, and reducing the overcurrent and the way-overcurrent protection levels to 1/2 of the initial values. in 1-phase configuration, vr1 op erates in 1-phase ccm in ps0 and ps1, and enters 1-phase de mode in ps2 and ps3. figure 13. current balancing during dynamic operation. ch1: il1, ch2: i load , ch3: il2, ch4: il3 rep rate = 10khz rep rate = 25khz rep rate = 50khz rep rate = 100khz rep rate = 200khz table 2. vr1 modes of operation pwm3 isen2 config. ps mode ocp threshold (a) to external driver to power stage 3-phase cpu vr config. 0 3-phase ccm 60 1 2-phase ccm 40 21-phase de 20 3 tied to 5v 2-phase cpu vr config. 0 2-phase ccm 60 1 1-phase ccm 30 21-phase de 3 tied to 5v 1-phase cpu vr config. 0 1-phase ccm 60 1 21-phase de 3
ISL95839 19 fn8315.0 may 9, 2013 table 3 shows vr2 operational mo des, programmed by the ps command. vr2 operates in ccm in ps0 and ps1, and enters de mode in ps2 and ps3. vr2 can be disabled completely by tying isumng to 5v, and all communication to vr2 will be rejected. dynamic operation vr1 and vr2 behave the same during dynamic operation. the controller responds to vid change s by slewing to the new voltage at a slew rate indicated in the setvid command. there are three setvid slew rates, namely setvid_fast, setvid_slow and setvid_decay. setvid_fast command prompts the controller to enter ccm and to actively drive the output voltage to the new vid value at a minimum 10mv/s slew rate. setvid_slow command prompts th e controller to enter ccm and to actively drive the output voltage to the new vid value at a minimum 2.5mv/s slew rate. setvid_decay command prompts the controller to enter de mode. the output voltage will decay down to the new vid value at a slew rate determined by the load. if the voltage decay rate is too fast, the controller will limit the voltage slew rate at 10mv/s. alert# will be asserted low at the end of setvid_fast and setvid_slow vid transitions. figure 14 shows setvid decay pre-emptive behavior. the controller receives a setvid_d ecay command at t1. the vr enters de mode and the output voltage vo decays down slowly. at t2, before vo reaches the intended vid target of the setvid_decay command, the controller receives a setvid_fast (or setvid_slow) command to go to a voltage higher than the actual vo. the controller will turn around immediately and slew vo to the new target voltage at the slew rate specified by the setvid command. at t3, vo reaches the new target voltage and the controller asserts the alert# signal. the r3? modulator intrinsically has voltage feed-forward. the output voltage is insensitive to a fast slew rate input voltage change. vr_hot#/alert# behavior the controller drives 60a current source out of the ntc pin and the ntcg pin alternatively at approximately 36khz frequency with 50% duty cycle. the current source flows through the respective ntc resistor networks on the pins and creates voltages that are monitored by the controller through an a/d converter (adc) to generate the t zone value. table 4 shows the programming table for t zone . the user needs to scale the ntc and the ntcg network resistance such that it generates the ntc (and ntcg) pin voltage that corresponds to the left-most column. do not use any capacitor to filter the voltage. figure 15 shows how the ntc and the ntcg network should be designed to get correct vr_hot#/alert# behavior when the system temperature rise s and falls, manifested as the ntc and the ntcg pin voltage falls and rises. the series of events are: 1. the temperature rises so the ntc pin (or the ntcg pin) voltage drops. t zone value changes accordingly. 2. the temperature crosses the threshold where t zone register bit 6 changes from 0 to 1. 3. the controller changes status_1 register bit 1 from 0 to 1. table 3. vr2 modes of operation ps mode ocp threshold (a) 01-phase ccm 60 1 21-phase de 3 figure 14. setvid decay pre-emptive behavior vo setvid_decay setvid_fast/slow t_alert vid alert# t1 t2 t3 table 4. t zone table vntc (v) t max (%) t zone 0.84 >100 ffh 0.88 100 ffh 0.92 97 7fh 0.96 94 3fh 1.00 91 1fh 1.04 88 0fh 1.08 85 07h 1.12 82 03h 1.16 79 01h 1.2 76 01h >1.2 <76 00h 1 bit 6 =1 bit 7 =1 bit 5 =1 temp zone register 0001 1111 0011 1111 0 1 11 1111 1 111 1111 0 1 11 1111 0011 1111 0001 1111 status 1 register = ?001? = ?0 1 1? = ?0 0 1? temp zone 7 2 3 5 svid alert# vr_hot# 4 gerreg status1 8 6 9 10 11 1111 1111 0111 1111 0011 1111 0001 1111 12 13 15 gerreg status1 14 16 3% hysteris vr temperature figure 15. vr_hot#/alert# behavior
ISL95839 20 fn8315.0 may 9, 2013 4. the controller asserts alert#. 5. the cpu reads status_1 register value to know that the alert assertion is due to t zone register bit 6 flipping. 6. the controller clears alert#. 7. the temperature continues rising. 8. the temperature crosses the threshold where t zone register bit 7 changes from 0 to 1. 9. the controllers asserts vr_hot# signal. the cpu throttles back and the system temperature starts dropping eventually. 10. the temperature crosses the threshold where t zone register bit 6 changes from 1 to 0. this threshold is 1 adc step lower than the one when vr_hot# gets asserted, to provide 3% hysteresis. 11. the controllers de-asserts vr_hot# signal. 12. the temperature crosses the threshold where t zone register bit 5 changes from 1 to 0. this threshold is 1 adc step lower than the one when alert# gets asserted during the temperature rise to provide 3% hysteresis. 13. the controller changes status_1 register bit 1 from 1 to 0. 14. the controller asserts alert#. 15. the cpu reads status_1 register value to know that the alert assertion is due to t zone register bit 5 flipping. 16. the controller clears alert#. fb2 function figure 16 shows the fb2 function. a switch (called fb2 switch) turns on to short the fb and the fb 2 pins when the controller is in 2-phase mode. capacitors c3.1 and c3.2 are in parallel, serving as part of the compensator. when the controller enters 1-phase mode, the fb2 switch turns off, removing c3.2 and leaving only c3.1 in the compensator. the comp ensator gain will increase with the removal of c3.2. by properly sizing c3.1 and c3.2, the compensator can be optimal fo r both 3-, 2-phase mode and 1-phase mode. when the fb2 switch is off, c3.2 is disconnected from the fb pin. however, the controller still actively drives the fb2 pin voltage to follow the fb pin voltage such th at c3.2 voltage always follows c3.1 voltage. when the controller turns on the fb2 switch, c3.2 will be reconnected to the compensator smoothly. the fb2 function ensures excellent transient response in both 3-, 2-phase mode and 1-phase mode. if one decides not to use the fb2 function, simply populate c3.1 only. adaptive body diode conduction time reduction in dcm, the controller turns off the low-side mosfet when the inductor current approaches zero. during on-time of the low-side mosfet, phase voltage is negative and the amount is the mosfet r ds(on) voltage drop, which is proportional to the inductor current. a phase comp arator inside the controller monitors the phase voltage during on-time of the low-side mosfet and compares it with a threshold to determine the zero-crossing point of the inductor current. if the inductor current has not reached zero when the lo w-side mosfet turns off, it?ll flow through the low-side mosfet body diode, causing the phase node to have a larger voltage drop until it decays to zero. if the inductor current has crossed zero and reversed the direction when the low-side mosfet turns off, it?ll flow through the high-side mosfet body diode, causing the phase node to have a spike until it decays to zero. th e controller continues monitoring the phase voltage after turning off the low-side mosfet and adjusts the phase comparator th reshold voltage accordingly in iterative steps such that the low-side mosfet body diode conducts for approximately 40ns to minimize the body diode-related loss. protections vr1 and vr2 both provide overcurrent, current-balance and overvoltage fault protections. the controller also provides over-temperature protection. the fo llowing discussion is based on vr1 and also applies to vr2. the controller determines overcurrent protection (ocp) by comparing the average value of the droop current i droop with an internal current source threshold as table 2 shows. it declares ocp when i droop is above the threshold for 120s. for overcurrent conditions above 1.5x the ocp level, the pwm outputs will immediately shut off and pgood will go low to maximize protection. this protec tion is also referred to as way-overcurrent protection or fast-overcurrent protection, for short-circuit protection. the controller monitors the isen pin voltages to determine current-balance protection. if the difference of one isen pin voltage and the average isens pin voltage is greater than 9mv for at least 3.2ms, the controller will declare a fault and latch off. the controller takes the same actions for all of the above fault protections: de-assertion of both pgoods and turn-off of all the high-side and low-side power mosfets. any residual inductor current will decay through the mosfet body diodes. the controller will declare an over voltage fault and de-assert pgood if the output voltage exceeds the vid set value by +200mv. the controller will immediately declare an ov fault, de-assert pgood, and turn on the low-side powe r mosfets. the low-side power mosfets remain on until the output voltage is pulled down below the vid set value when all power mosfets are turned off. if the output voltage rises above the vid set value +200mv again, the protection process is repeated. this behavior provides the maximum amount of protection against shorted high-side power mosfets while preventing output ringing below ground. figure 16. fb2 function r1 e/a r3 c2 c1 vref r2 c3.2 c3.1 fb fb2 comp vsen r1 e/a r3 c2 c1 vref r2 c3.2 c3.1 fb fb2 comp vsen controller in 3- and 2-phase mode controller in 1-phase mode
ISL95839 21 fn8315.0 may 9, 2013 the overvoltage fault threshold is 1.7v when output voltage ramps up from 0v. and the overvoltage fault threshold is restored to vid set value + 200mv after the output voltage settles. all the above fault conditions can be reset by bringing vr_on low or by bringing v dd below the por threshold. when vr_on and v dd return to their high operating levels, a soft-start will occur. table 5 summarizes the fault protections. supported data and configuration registers the controller supports the fo llowing data and configuration registers. table 5. fault protection summary fault type fault duration before protection protection action fault reset overcurrent 120s pwm tri-state, pgood latched low vr_on toggle or v dd toggle phase current unbalance 3.2ms way-overcurrent (1.5xoc) immediately overvoltage +200mv pgood latched low. actively pulls the output voltage to below vid value, then tri-state. 1.7v overvoltage during output voltage ramp up from 0v table 6. supported data and configuration registers index register name description default value 00h vendor id uniquely identifies the vr vendor. assigned by intel. 12h 01h product id uniquely identifies the vr product. intersil assigns this number. 24h 02h product revision uniquely identifies the revision of the vr control ic. intersil assigns this data. 05h protocol id identifies what revision of svid protocol the controller supports. 01h 06h capability identifies the svid vr capabilities and which of the optional telemetry registers are supported. 81h 10h status_1 data register re ad after alert# signal. indicating if a vr rail has settled, has reached vrhot condition or has reached icc max. 00h 11h status_2 data register showing status_2 communication. 00h 12h temperature zone data register showing temperature zones that have been entered. 00h 1ch status_2_ lastread this register contains a copy of the status_2 data that was last read with the getreg (status_2) command. 00h 21h icc max data register containing the icc max the platform supports, set at start-up by resistors rprog1 and rprog2. the platform design engineer programs this value during the design process. binary format in amps, i.e., 100a = 64h refer to table 7 22h temp max not supported 24h sr-fast slew rate normal. the fastest slew rate the platform vr can sustain. binary format in mv/s. i.e., 0ah = 10mv/s. 0ah 25h sr-slow is 4x slower than normal. binary format in mv/s. i.e., 02h = 2.5mv/s 02h 26h v boot if programmed by the platform, the vr supports v boot voltage during start-up ramp. the vr will ramp to v boot and hold at v boot until it receives a new setvid command to move to a different voltage. 00h 30h vout max this register is programmed by the master and sets the maximum vid the vr will support. if a higher vid code is received, the vr will respond with ?not supported? acknowledge. fbh 31h vid setting data register containing currently programmed vid voltage. vid data format. 00h 32h power state register containing the current programmed power state. 00h 33h voltage offset sets offset in vid steps added to the vid setting for voltage margining. bit 7 is a sign bit, 0 = positive margin, 1 = negative margin. remaining 7 bits are # vid steps for the margin. 00h = no margin, 01h = +1 vid step 02h = +2 vid steps... 00h 34h multi vr config data register that configures multiple vrs behavior on the same svid bus. vr1: 00h vr2: 01h table 6. supported data and configuration registers (continued) index register name description default value
ISL95839 22 fn8315.0 may 9, 2013 key component selection inductor dcr current-sensing network figure 17 shows the inductor dcr current-sensing network for a 3-phase solution. an inductor current flows through the dcr and creates a voltage drop. each inductor has two resistors in r sum and r o connected to the pads to a ccurately sense the inductor current by sensing the dcr voltage drop. the r sum and r o resistors are connected in a summing network as shown, and feed the total current information to the ntc network (consisting of r ntcs , r ntc and r p ) and capacitor c n . r ntc is a negative temperature coefficient (ntc) thermistor, used to temperature-compensate the inductor dcr change. the inductor output side pads are electrically shorted in the schematic, but have some parasitic impedance in actual board layout, which is why one cannot simply short them together for the current-sensing summing network. it is recommended to use 1 ? ~10 ? r o to create quality signals. since r o value is much smaller than the rest of the current sensing circuit, the following analysis will ignore it for simplicity. the summed inductor current information is presented to the capacitor c n . equations 18 thru 22 describe the frequency-domain relationship between inductor total current i o (s) and c n voltage v cn (s): where n is the number of phases. transfer function a cs (s) always has unity gain at dc. the inductor dcr value increases as the wi nding temperature increases, giving higher reading of the inductor dc current. the ntc r ntc values decrease as its temperatur e decreases. proper selections of r sum , r ntcs , r p and r ntc parameters ensure that v cn represent the inductor total dc current over the temperature range of interest. there are many sets of parameters that can properly temperature-compensate the dcr change. since the ntc network and the r sum resistors form a voltage divider, v cn is always a fraction of the inductor dcr voltage. it is recommended to have a higher ratio of v cn to the inductor dcr voltage, so the droop circuit has a higher signal level to work with. a typical set of parameters that provide good temperature compensation are: r sum = 3.65k ? , r p =11k ? , r ntcs = 2.61k ? and r ntc = 10k ? (ert-j1vr103j). the ntc network parameters may need to be fine tuned on actual boards. one can apply full load dc current and record the output voltage reading immediately; then record the ou tput voltage reading again when the board has reached the thermal steady state. a good ntc network can limit the output voltag e drift to within 2mv. it is recommended to follow the intersil evaluation board layout and current-sensing network parameters to minimize engineering time. v cn (s) also needs to represent real-time i o (s) for the controller to achieve good transient response. transfer function a cs (s) has a pole w sns and a zero w l . one needs to match w l and w sns so a cs (s) is unity gain at all frequencies. by forcing w l equal to w sns and solving for the solution, equation 23 gives the cn value. for example, given n = 3, r sum = 3.65k ? , r p = 11k ? , r ntcs =2.61k ? , r ntc = 10k ? , dcr = 0.9m ? and l = 0.36h, equation 23 gives c n =0.397f. assuming the compensator design is correct, figure 18 shows the expected load transient response waveforms if c n is correctly selected. when the load current i core has a square change, the output voltage v core also has a square response. if c n value is too large or too small, v cn (s) will not accurately represent real-time i o (s) and will worsen the transient response. figure 19 shows the load transient response when c n is too small. v core will sag excessively upon load insertion and may create a system failure. figure 20 shows the transient response when c n is too large. v core is sluggish in drooping to its final value. there will be excessive overshoot if load insertion occurs during this time, which may potentially hurt the cpu reliability. cn rsum ro rntcs rntc rp dcr l dcr l rsum ro phase2 phase3 io dcr l phase1 ro rsum ri isum+ isum- vcn figure 17. dcr current-sensing network v cn s () r ntcnet r ntcnet r sum n -------------- - + ------------------------------------------ dcr n ------------- ?? ?? ?? ?? ?? i o s () a cs s () = (eq. 18) r ntcnet r ntcs r ntc + () r p r ntcs r ntc r p ++ ---------------------------------------------------- = (eq. 19) a cs s () 1 s l ------ - + 1 s sns ------------ - + ---------------------- - = (eq. 20) l dcr l ------------- = (eq. 21) sns 1 r ntcnet r sum n -------------- - r ntcnet r sum n -------------- - + ------------------------------------------ c n -------------------------------------------------------- = (eq. 22) c n l r ntcnet r sum n -------------- - r ntcnet r sum n -------------- - + ------------------------------------------ dcr -------------------------------------------------------------- - = (eq. 23)
ISL95839 23 fn8315.0 may 9, 2013 figure 21 shows the output voltage ring back problem during load transient response. the load current i o has a fast step change, but the inductor current i l cannot accurately follow. instead, i l responds in first order system fashion due to the nature of current loop. the esr and esl effect of the output capacitors makes the output voltage v o dip quickly upon load current change. however, the controller regulates v o according to the droop current i droop , which is a real-time representation of i l ; therefore it pulls v o back to the level dictated by i l , causing the ring back problem. this phenomenon is not observed when the output capacitor have very low esr and esl, such as all ceramic capacitors. figure 22 shows two optional circ uits for reduction of the ring back. c n is the capacitor used to match the inductor time constant. it usually takes the parallel of two (or more) capacitors to get the desired value. figure 22 shows that two capacitors c n.1 and c n.2 are in parallel. resistor r n is an optional co mponent to reduce the v o ring back. at steady state, c n.1 + c n.2 provides the desired c n capacitance. at the beginning of i o change, the effective capacitance is less because r n increases the impedance of the c n.1 branch. as figure 19 explains, v o tends to dip when c n is too small, and this effect will reduce the v o ring back. this effect is more pronounced when c n.1 is much larger than c n.2 . it is also more pronounced when r n is bigger. however, the presence of r n increases the ripple of the v n signal if c n.2 is too small. it is recommended to keep c n.2 greater than 2200pf. r n value usually is a few ohms. c n.1 , c n.2 and r n values should be determined through tuning th e load transient response waveforms on an actual board. r ip and c ip form an r-c branch in parallel with r i , providing a lower impedance path than r i at the beginning of i o change. r ip and c ip do not have any effect at steady state. through proper selection of r ip and c ip values, i droop can resemble i o rather than i l , and v o will not ring back. the recommended value for r ip is 100 ? . c ip should be determined through tuning the load transient response waveforms on an actual board. the recommended range for c ip is 100pf~2000pf. however, it should be noted that the r ip -c ip branch may distort the i droop waveform. instead of being triangular as the real inductor figure 18. desired load tr ansient response waveforms o i v o figure 19. load transient response when c n is too small o i v o figure 20. load transient response when c n is too large o i v o figure 21. output voltage ring back problem o i v o l i ring back figure 22. optional circuits for ring back reduction cn.2 rntcs rntc rp ri isum+ isum- rip cip optional vcn cn.1 rn optional
ISL95839 24 fn8315.0 may 9, 2013 current, i droop may have sharp spikes, which may adversely affect i droop average value detection and therefore may affect ocp accuracy. user discretion is advised. resistor current-sensing network figure 23 shows the resistor current-sensing network for a 2-phase solution. each inductor has a series current-sensing resistor r sen . r sum and r o are connected to the r sen pads to accurately capture the inductor current information. the r sum and r o resistors are connected to capacitor c n . r sum and c n form a filter for noise attenuation. equations 24 thru 26 give v cn (s) expression: transfer function a rsen (s) always has unity gain at dc. current-sensing resistor r sen value will not have significant variation over-temperature, so there is no need for the ntc network. the recommended values are r sum = 1k ? and c n = 5600pf. overcurrent protection refer to equation 1 on page 16 and figures 17, 21 and 23; resistor r i sets the droop current i droop . tables 2 and 3 show the internal ocp threshold. it is recommended to design i droop without using the r comp resistor. for example, the ocp threshold is 60a for 3-phase solution. we will design i droop to be 50a at full load, so the ocp trip level is 1.2x of the full load current. for inductor dcr sensing, equation 27 gives the dc relationship of v cn (s) and i o (s). substitution of equation 27 into equation 1 gives equation 28: therefore: substitution of equation 19 and application of the ocp condition in equation 29 gives equation 30: where i omax is the full load current, i droopmax is the corresponding droop current. for example, given n = 3, r sum = 3.65k ? , r p = 11k ? , r ntcs = 2.61k ? , r ntc = 10k ? , dcr = 0.9m ? , i omax = 94a and i droopmax = 50a, equation 30 gives r i = 467 ? . for resistor sensing, equation 31 gives the dc relationship of v cn (s) and i o (s). substitution of equation 31 in to equation 1 gives equation 32: therefore: substitution of equation 33 and application of the ocp condition in equation 29 gives equation 34: where i omax is the full load current, i droopmax is the corresponding droop current. for example, given n = 3, r sen =1m ? , i omax = 94a and i droopmax = 50a, equation 34 gives r i = 627 ? . load line slope refer to figure 10. for inductor dcr sensing, substitution of equation 28 into equation 2 gives the load line slope expression: figure 23. resistor current-sensing network cn rsum ro dcr l dcr l rsum ro phase2 phase3 io dcr l phase1 ro rsum ri isum+ isum- vcn rsen rsen rsen v cn s () r sen n ------------- i o s () a rsen s () = (eq. 24) a rsen s () 1 1 s rsen ----------------- + --------------------------- = (eq. 25) rsen 1 r sum n -------------- - c n ---------------------------- - = (eq. 26) v cn r ntcnet r ntcnet r sum n -------------- - + ------------------------------------------ dcr n ------------- ?? ?? ?? ?? ?? i o = (eq. 27) i droop 1 r i ----- r ntcnet r ntcnet r sum n -------------- - + ------------------------------------------ dcr n ------------- i o = (eq. 28) r i r ntcnet dcr i o nr ntcnet r sum n -------------- - + ?? ?? i droop --------------------------------------------------------------------------------- - = (eq. 29) r i r ntcs r ntc + () r p r ntcs r ntc r p ++ ---------------------------------------------------- dcr i omax n r ntcs r ntc + () r p r ntcs r ntc r p ++ ---------------------------------------------------- r sum n -------------- - + ?? ?? ?? i droopmax ---------------------------------------------------------------------------------------------------------------------------- - = (eq. 30) v cn r sen n ------------- i o = (eq. 31) i droop 1 r i ----- r sen n ------------- i o = (eq. 32) r i r sen i o ni droop --------------------------- = (eq. 33) r i r sen i omax ni droopmax -------------------------------------- = (eq. 34) ll v droop i o ------------------ - r droop r i ------------------- r ntcnet r ntcnet r sum n -------------- - + ------------------------------------------ dcr n ------------- == (eq. 35)
ISL95839 25 fn8315.0 may 9, 2013 for resistor sensing, substitution of equation 32 into equation 2 gives the load line slope expression : substitution of equation 29 and rewriting equation 35, or substitution of equation 33 and rewriting equation 36 give the same result in equation 37: one can use the full load condition to calculate r droop . for example, given i omax = 94a, i droopmax = 50a and ll = 1.9m ? , equation 37 gives r droop = 3.57k ? . it is recommended to start with the r droop value calculated by equation 37, and fine tune it on the actual board to get accurate load line slope. one should record the output volt age readings at no load and at full load for load line slope calculation. reading the output voltage at lighter load instead of full load will increase the measurement error. compensator figure 18 shows the desired load transient response waveforms. figure 24 shows the equivalent circuit of a voltage regulator (vr) with the droop function. a vr is equivalent to a voltage source (= vid) and output impedance z out (s). if z out (s) is equal to the load line slope ll, i.e., constant output impedance, in the entire frequency range, v o will have square response when i o has a square change. intersil provides a microsoft excel-based spreadsheet to help design the compensator and the current sensing network, so the vr achieves constant output impedance as a stable system. please go to http://www.intersil.com/en/support.html to request spreadsheet. a vr with active droop function is a dual-loop system consisting of a voltage loop and a droop loop wh ich is a current loop. however, neither loop alone is sufficient to describe the entire system. the spreadsheet shows two loop gain transfer functions, t1(s) and t2(s), that describe the entire system. figure 25 conceptually shows t1(s) measurement set-up and figure 26 conceptually shows t2(s) measurement set-up. the vr senses the inductor current, multiplies it by a gain of the load line slope, then adds it on top of the sensed output voltage and feeds it to the compensator. t(1) is measured after the summing node, and t2(s) is measured in the voltage loop before the summing node. the spreadsheet gives both t1(s) and t2(s) plots. however, only t2(s) can be actually measured on an ISL95839 regulator. t1(s) is the total loop gain of the voltage loop and the droop loop. it always has a higher crossover frequency than t2(s) and has more meaning of system stability. t2(s) is the voltage loop gain with closed droop loop. it has more meaning of output voltage response. design the compensator to get stable t1(s) and t2(s) with sufficient phase margin, and output impedance equal or smaller than the load line slope. ll v droop i o ------------------ - r sen r droop nr i --------------------------------------- == (eq. 36) r droop i o i droop ---------------- ll = (eq. 37) figure 24. voltage regulator equivalent circuit o i v o vid z out (s) = ll load vr figure 25. loop gain t1(s) measurement set-up q2 q1 l o i c out v o v in gate driver comp mod. load line slope ea vid channel b channel a excitation output isolation transformer 20 w loop gain = channel b channel a network analyzer figure 26. loop gain t2(s) measurement set-up q2 q1 l o i c out v o v in gate driver comp mod. load line slope ea vid channel b channel a excitation output isolation transformer 20 loop gain = channel b channel a network analyzer
ISL95839 26 fn8315.0 may 9, 2013 revision 9.1 attention: 1. "analysis toolpak" add-in is required. (to turn it on in ms excel 2003, go to tools--add-ins, and check "analysis toolpak"). 2. green cells require user input controller part number: phase number: 3 vin: 12 volts vo: 1 volts full load current: 94 amps estimated full-load efficiency: 85 % number of output bulk capacitors: 4 capacitance of each output bulk capacitor: 470 uf esr of each output bulk capacitor: 4.5 m : r1 3.572 k : r1 3.57 k : esl of each output bulk capacitor: 0.2 nh r2 270.237 k : r2 267 k : number of output ceramic capacitors: 28 r3 0.699 k : r3 0.499 k : capacitance of each output ceramic capacitor: 10 uf c1 497.168 pf c1 150 pf esr of each output ceramic capacitor: 3 m : c2 505.690 pf c2 470 pf esl of each output ceramic capacitor: 3 nh c3 31.478 pf c3 47 pf switching frequency: 300 khz rcomp 274 k : inductance per phase: 0.36 uh cpu socket resistance: 0.9 m : desired load-line slope: 1.9 m : do the following desired idroop current at full load: 50 ua t1 bandwidth: 118khz t2 bandwidth: 38khz for resistor (this sets the over-current protection level) t1 phase margin: 74.1 t2 phase margin: 85.9 sensing inductor dcr 0.9 m : <-- rsense place the 2nd compensator pole fp2 at: 1.5 rsum 3.65 k : <-- 0.001k 7xqh.&lwrjhwwkhghvluhgorrsjdlqedqgzlgwk rntc 10 k : <-- 1000k tune the compensator gain factor k & i: 1.3 rntcs 2.61 k : <-- 1000k 5hfrpphqghg.&ludqjhlva rp 11 k : <-- 1000k recommended value user selected value cn 0.397 uf cn 0.397 uf ri 467.239 : ri 467 : these rsum and cn values are used to "fool" the spreadsheet so it can calculate for resistor-sensing application they should not be used on the actual schematics comp pin voltage during reading of rcomp value (only on controllers with comp pin resistor reader function) note: comp pin voltage needs to reach or cross the threshold voltage at "time"=1ms. the above comp pin waveform passes operation parameters use user-selected value (y/n)? performance and stability x fs (switching frequency) changing the settings in red requires deep understanding of control loop design disable droop function (y/n)? compensator parameters current sensing network parameters compensation & current sensing network design for intersil multiphase r^3 regulators. recommended value user-selected value operation parameters ( ( ( ( ( ( ( ( * d l q g % ) u h t x h q f \ + ] loop gain, gain curve 7v 7v ( ( ( ( ( ( ( ( 0 d j q l w x g h p r k p ) u h t x h q f \ + ] output impedance z(f), gain curve ( ( ( ( ( ( ( ( 3 k d v h g h j u h h ) u h t x h q f \ + ] loop gain, phase curve 7v 7v ( ( ( ( ( ( ( ( 3 k d v h g h j u h h ) u h t x h q f \ + ] output impedance z(f), phase curve & 2 0 3 3 l q 9 r o w d j h 9 7 l p h p v voltage threshold comp pin voltage -------> copy to y i sl95836 r1 opamp r3 c2 c1 vref r2 c3 ? ? 1 ? ? ? ? 1 ? ? ? ? 1 ? ? ? ? 1 ? ? ? 2 1 2 1 2 1 2 1 2 1 2 1 ) ( p p z z i v f s f s s f s f s i k s a s s s s z z rcomp fb comp cn rsum ro r ntcs r ntc rp dcr l dcr l rsum ro phase2 phase3 vo dcr l phase1 ro rsum ri isum+ isum- n figure 27. screenshot of the compensator design spreadsheet ISL95839
ISL95839 27 fn8315.0 may 9, 2013 programming resistors there are two programming resistors: r comp and r compg . table 7 shows how to select r comp based on v boot and vr1 i ccmax register settings. vr1 can power to 0v v boot or an internally-set v boot based on r comp value. when the controller works with an actual cpu, select r comp such that vr1 powers up to v boot = 0v as required by the svid command. in the absence of a cpu, such as test ing of the vr al one, select r comp such that vr1 powers up to the internally-set v boot , which by default is 1.1v. determine the maximum current vr1 can support and set the vr1 i ccmax register value accordingly by selecting the appropriate r comp value. the cpu will read the vr1 i ccmax register value and ensure that the cpu core current doesn?t exceed the value specified by vr1 i ccmax . table 8 shows how to select r compg based on vr1 and vr2 ccm switching frequency and vr2 i ccmax register settings. there are four switching frequencies to choose from: 300khz, 350khz, 400khz, and 450khz. there are also three vr2 i ccmax values to choose. current balancing refer to figures 3 and 4. the controller achieves current balancing through matching the isen pin voltages. r isen and c isen form filters to remove the switching ripple of the phase node voltages. it is recommended to use rather long r isen c isen time constant such that the isen voltages have minimal ripple and represent the dc current flowing through the inductors. recommended values are r s = 10k ? and c s =0.22f. table 7. r comp programming table r comp (k ? ) v boot (v) vr1 i ccmax (a) min typ max 2.7 2.85 3.0 0 99 5.0 5.6 6.2 0 94 8.4 9.4 10.4 0 80 12.0 13.2 14.4 0 70 15.8 17.0 18.2 0 60 19.6 20.8 22.0 0 53 23.4 24.6 25.8 0 48 27.2 28.4 29.6 0 43 31.2 33.7 36.1 0 38 38.8 41.3 43.7 0 33 46.4 48.9 51.3 0 24 54.0 56.5 58.9 0 18 62.1 64.1 66.0 1.1 18 69.5 71.7 73.8 1.1 24 76.9 79.3 81.7 1.1 33 86.2 88.9 91.6 1.1 38 97.3 100.3 103.3 1.1 43 108.3 111.7 115.1 1.1 48 119.5 123.2 126.8 1.1 53 132.5 136.6 140.6 1.1 60 147.2 151.8 156.3 1.1 70 162.0 167.0 172.0 1.1 80 178.7 184.2 189.7 1.1 94 210.1 216.6 open 1.1 99 table 8. r compg programming table r compg (k ? ) switching frequency (khz) vr2 i ccmax (a) min typ max 12.0 13.2 14.4 450 33 15.8 17.0 18.2 450 24 19.6 20.8 22.0 450 18 23.4 24.6 25.8 400 18 27.2 28.4 29.6 400 24 31.2 33.7 36.1 400 33 86.2 88.9 91.6 350 33 97.3 100.3 103.3 350 24 108.3 111.7 115.1 350 18 119.5 123.2 126.8 300 18 132.5 136.6 140.6 300 24 147.2 151.8 156.3 300 33
ISL95839 28 fn8315.0 may 9, 2013 slew rate compensation circuit for vid transition during a large vid transition, the dac steps through the vids at a controlled slew rate. for example, the dac may change a tick (5mv) per 0.5s, controlling output voltage v core slew rate at 10mv/s. figure 28 shows the waveforms of vid transition. during vid transition, the output capacitor is being charged and discharged, causing c out x dv core /dt current on the inductor. the controller senses the inductor current increase during the up transition, as the i droop_vid waveform shows, and will droop the output voltage v core accordingly, making v core slew rate slow. similar behavior occurs during the down transition. to get the correct v core slew rate during vid transition, one can add the r vid -c vid branch, whose current i vid cancels i droop_vid . it?s recommended to choose the r, c values from the reference design as a starting point. then tweak the actual values on the board to get the best performance. during normal transient response, the fb pin voltage is held constant, therefore is virtual grou nd in small signal sense. the r vid - c vid network is between the virtual ground and the real ground, and hence has no effect on transient response. figure 28. slew rate compensation circuit for vid transition x 1 e/a dac vid rdroop idroop_vid vdac fb comp vcore vsssense vids rtn vss internal to ic rvid cvid vid vfb vcore ivid idroop_vid ivid optional
ISL95839 29 fn8315.0 may 9, 2013 0.01uf 97.6k -------- 0.1uf 649 3300pf ----- 649 11k fsw = 400khz ---- ------------------------------------------------------------------- - l1,l4 cpu side pull-up 2200pf 2k etqp4lr36afc(panasonic) bsc011n03ls-t(infineon) --------------------------------- 470uf 470uf dnp 10k 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 22uf 22uf 0.36uh 10 22uf 22uf 22uf 22uf 22uf 22uf 22uf 22uf 22uf 470uf 470uf 22uf 3.65k - r42,r43 - q2,q16 - q3,q17 ncp18wm474j03rb-t(murata) ert-j1vr103j-t(panasonic) bsc052n03ls-t(infineon) component - c24,c25 ------------------------------------------------------------------- - c39,c52,c301,c302,c113,c117 2tpw470m4r(sanyo) grm21br61c106ke15l(tdk) grm21br61c226ke15l(tdk) (kyocera,murata,taiyo,samsung) t520v277m2r5a(1_e4r5-6666(kemet) eeflx0d471r4(panasonic) (kyocera,murata,taiyo,samsung) mpch1040lr36(nec-tokin) 25sp56m(sanyo) --------------------------------- 22uf 22uf 10 470uf 22uf 22uf 22uf 22uf 22uf 470uf 22uf 22uf 22uf 22uf 22uf 680p dnp 11k ----> 330pf 130 ntc ntc -------- 43 0.22uf ---- 2.61k 2.61k ntc 470k 27.4k ------------------------------------------------------------------- - r20,r45 --------------------------------- ------------------------------------------------------------------- 54.9 330pf ---- optional 383 3300pf ---- 75 130 -------- dnp ---- ----- ---- optional ----- ------------------------------------------------------------------- - c40,c41,c47,c48,c53,c54 c59-c68,c114,c115,c118-c127 ------------------------------------------------------------------- - c310-c319 ----- ---- 680pf 27.4k 3.83k 133k 71.5k r4 = 71.5k vboot = 1.1v 2.1k 118 r2 = 28.7k iccmax_gt = 24a 2k 2200pf 0.01uf 0.22uf 10uf 3.65k 0.36uh ------------------------------------------------------------------- part number (manufacturer) 133k 1000pf 56pf 118 2.1k 56pf 0.01uf ------------------------------------------------------------------- ------------------------------------------------------------------- ------------------------------------------------------------------- ------------------------------------------------------------------- -------- ---- 3.83k ntc 470k controller side pull-up 97.6k 0.01uf iccmax = 24a 1000pf 383 28.7k place near l1 ----------> 0.1uf 10uf 10k place near l4 0.22uf vsumng vin vtt 1.91k +3.3v pgood +5v +3.3v pggodg 1.91k cpuvcore 10 cpuvccsense 499 ISL95839hrtz 1uf +5v vsumn vsump alert# sda 1uf vr_hot# sclk gtvcore 1uf 1 10uf vsumng vsumpg gtvcore 10uf 10uf vsump vsumn cpuvcore vsumpg 10uf 0 +5v 56uf 56uf 0 0.22uf cpuvsssense 10 gtvccsense gtvsssense 10 vr_on 10 imong imon r19 r183 out out in out in in in in in out in in in in in out in in in in in in in in in c52 c39 c117 c113 c302 c301 c24 c25 r12 r214 r213 out out out out c87 c8 r26 c30 c88 r2 r11 c6 c3 r7 r46 r10 r4 r112 r54 r49 u1 c130 r37 r202 r55 c11 r16 r31 r155 r24 c86 c99 l4 q3 l1 r80 q17 q16 r56 q2 r56 c30 r20 r17 r18 c81 r109 r30 r23 c93 r9 c51 r25 r1 r32 c14 ep ugate2 phase2 boot2 phase1 ugate1 lgate1 pwm3 vdd vccp lgate2 ntc fb2 vr_hot# alert# sda sclk ntcg imong isumpg imon r38 r5 c22 c68 c59 r42 c19 c20 c18 r36 r39 c94 c95 c90 c89 r43 c112 c110 c119 c121 c122 c129 c127 c125 c124 c123 c120 c118 c114 r127 c33 r63 c67 c63 c64 c53 c60 c54 c47 c48 c40 c41 r88 c311 c310 c313 c314 c315 c316 c317 c318 c319 c312 c27 r8 c13 c16 c12 r131 c115 r41 c97 pgoodg compg fbg rtng isumng isen3 phase1g ugate1g boot1g isen2 isen1 isump isumn fb rtn comp pgood boot1 vr_on lgate1g figure 29. ISL95839 1+1 reference design
ISL95839 30 fn8315.0 may 9, 2013 layout guidelines ISL95839 pin # symbol layout guidelines bottom pad gnd connect this ground pad to th e ground plane through low impedance path. recommend use of at least 5 vias to connec t to ground planes in pcb internal layers. 2 imong connect a resistor in parallel with a capacitor from imon and imong pins to ground resp ectively. place the resistors and capacitors as close as po ssible to the controller. 3imon 4 ntcg the ntc thermistor needs to be placed close to th e thermal source that is monitored to determine axg v core thermal throttling. recommend placing it at the hottest spot of the axg v core vr. 5, 6, 7 sclk, alert#, sda follow intel recommendation. 8 vr_hot# no special consideration. 9 fb2 place the compensator components in general proximity of the controller. 10 ntc the ntc thermistor needs to be placed close to th e thermal source that is monitored to determine cpu v core thermal throttling. recommend placing it at the hottest spot of the cpu v core vr. 11 isen3 each isen pin has a capacitor (cisen) decoupling it to vs umn, then through another capacitor (cvsumn) to gnd. place cise n capacitors as close as possible to the controller and keep the following loops small: 1. any isen pin to another isen pin 2. any isen pin to gnd the red traces in the following drawing show the loops that need to minimized. 12 isen2 13 isen1 14 isump place the current sensing circuit in general proximity of the controller. place capacitor cn very close to the controller. place the ntc thermistor next to vr1 phase-1 inductor (l 1) so it senses the inductor temperature correctly. each phase of the power stage sends a pair of vsump and vsum n signals to the controller. ru n these two signals traces in parallel fashion with decent width (>20mil). important: sense the inductor current by routing the sensing circuit to the inductor pads. route r63 and r71 to vr1 phase-1 side pad of inductor l1. route r88 to the output side pad of inductor l1. route r65 and r72 to vr1 phase-2 side pad of inductor l2. route r90 to the output side pad of induct or l2. if possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. if no via is allowed on the pad, consider routing the traces into the pads from th e inside of the inductor. the following drawings show the two preferred ways of routing current sensing traces. 15 isumn v o isen3 l3 risen isen2 isen1 l2 l1 risen risen phase1 phase2 phase3 ro ro ro gnd cisen cisen cisen cvsumn vsumn inductor current-sensing traces vias inductor current-sensing traces
ISL95839 31 fn8315.0 may 9, 2013 16 rtn place the rtn filter in close proximity of the controller for good decoupling. 17 fb place the compensator components in general proximity of the controller. 18 comp 19 pgood no special consideration. 20 boot1 use decent wide trace (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. 21 ugate1 run these two traces in parallel fa shion with decent width (>30mil). avoid any sensitive analog signal trace from cross ing over or getting close. recommend routing phase1 trace to vr 1 phase-1 high-side mosfet (q2 and q8) source pins instead of general copper. 22 phase1 23 lgate1 place the rtng filter in close proximity of the controller for good decoupling. 24 pwm3 no special consideration. 25 vdd a capacitor decouples it to gnd. place it in close proximity of the controller. 26 vccp a capacitor decouples it to gnd. place it in close proximity of the controller. 27 lgate2 use decent width (>30mil). avoid any sensitive anal og signal trace from crossing over or getting close. 28 phase2 run these two traces in parallel fashion with decent wi dth (>30mil). avoid any sensitive analog signal trace from cross ing over or getting close. recommend rout ing phase2 trace to vr1 phase-2 high-s ide mosfet (q4 and q10) source pins instead of general copper. 29 ugate2 30 boot2 use decent wide trace (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. 31 boot1g use decent wide trace (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. 32 ugate1g run these two traces in parallel fashion with decent width (>30mil). avoid an y sensitive analog signal trace from cros sing over or getting close. recommend routing phase1g trace to vr 2 phase-1 high-side mosfet sour ce pins instead of general copper 33 phase1g 34 lgate1g use decent width (>30mil). avoid any sensitive an alog signal trace from crossing over or getting close. 35 vr_on no special consideration. 36 pgoodg no special consideration. 37 compg place the compensator components in general proximity of the controller. 38 fbg 39 rtng place the rtng filter in close proximity of the controller for good decoupling. 40 isumng place the current sensing circuit in general proximity of the controller. place capacitor cn very close to the controller. place the ntc thermistor next to vr2 phase-1 inductor (l1) so it senses the inductor temperature correctly. see isumn and isump pins for layout guidelines of current-sensing trace routing. 1isumpg layout guidelines (continued) ISL95839 pin # symbol layout guidelines
ISL95839 32 fn8315.0 may 9, 2013 typical performance figure 30. vr1 soft-start, v in ? = ? 19v, i o ? = ? 5a, vid ? = ? 1.1v, ch1: vr_on, ch2: vr1 v o , ch3: pgood figure 31. vr2 soft-start, v in ? = ? 19v, i o ? = ? 5a, vid ? = ? 1.1v, ch1: vr_on, ch2: vr2 v o , ch3: pgoodg figure 32. 1 vr1 and vr2 soft-start, v in ? = ? 7v, i o_vr1 ? = ? 30a, i o_vr2 ? = ? 30a, vid ? = ? 1.1v, ch1: vr1 v o, ch2: vr2 v o, ch3: pgood, ch4: ? phase1g figure 33. 1 vr1 and vr2 soft-start, v in ? = ? 20v, i o_vr1 ? = ? 30a, i o_vr2 ? = ? 30a, vid ? = ? 1.1v, ch1: vr1 v o, ch2: vr2 v o, ch3: pgood, ch4: ? phase1g figure 34. vr1 shut down, v in ? = ? 12v, i o ? = ? 5a, vid ? = ? 1.1v, ch1: pgood, ch2: vr1 v o , ch3: vr_on, ch4: ? comp figure 35. vr2 shut down, v in ? = ? 12v, i o ? = ? 5a, vid ? = ? 1.1v, ch1: pgoodg, ch2: vr2 v o , ch3: vr_on, ch4: ? compg
ISL95839 33 fn8315.0 may 9, 2013 figure 36. vr1 pre-charged start up, v in ? = ? 19v, vid ? = ? 1.1v, v_pre-charge voltage = 0.5v, ch1: phase1, ch2: vr1 v o , ch3: vr_on, ch4: ? pgood figure 37. vr2 pre-charged start up, v in ? = ? 19v, vid ? = ? 1.1v, v_pre-charge voltage = 1.3v, ch1: phase1g, ch2: vr2 v o , ch3: vr_on, ch4: ? pgoodg figure 38. vr1 steady state, v in ? = ? 19v, i o ? = ? 94a, vid ? = ? 0.9v ch1: phase1, ch2: vr1 v o, ch3: phase2, ch4: ? phase3 figure 39. vr1 load release response, v in ? = ? 12v, vid ? = ? 0.9v, i o ? = ? 28a/94a, slew time= 150ns, ll ? = ? 1.9m ? , ch1: phase1, ch2: vr1 v o, ch3: phase2, ch4: phase3 figure 40. vr1 load insertion response, v in ? = ? 12v, vid ? = ? 0.9v, i o ? = ? 28a/94a, slew time= 150ns, ll ? = ? 1.9m ? , ch1: phase1, ch2: vr1 v o, ch3: phase2, ch4: phase typical performance (continued)
ISL95839 34 fn8315.0 may 9, 2013 figure 41. vr1 ps2 load transient response, v in ? = ? 19v, vid ? = ? 0.6v, i o ? = ? 1a/5a, slew time= 150ns, ll ? = ? 1.9m ? , ch1: phase1, ch2: vr1 v o figure 42. vr2 ps2 load transient response, v in ? = ? 19v, vid ? = ? 0.6v, i o ? = ? 1a/5a, slew time= 150ns, ll ? = ? 3.9m ? , ch1: phase1g, ch2: vr2 v o figure 43. vr1 setvid-fast response, i o ? = ? 5a, vid ? = ? 0.3v ? - ? 0.9v, ch1: phase1, ch2: vr1 v o , ch3: ? sda, ch4: alert# figure 44. vr2 setvid-fast response, i o ? = ? 5a, vid ? = ? 0.5v ? - ? 0.8v, ch1: phase1g, ch2: vr2 v o , ch3: ? sda, ch4: alert# figure 45. vr1 setvid-slow response, i o ? = ? 5a, vid ? = ? 0.3v ? - 0.9v, ch1: phase1, ch2: vr1 v o , ch3: ? sda, ch4: alert# figure 46. vr2 setvid-slow response, i o ? = ? 5a, vid ? = ? 0.4v ? - 0.9v, ch1: phase1g, ch2: vr2 v o , ch3: ? sda, ch4: alert# typical performance (continued)
ISL95839 35 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8315.0 may 9, 2013 for additional products, see www.intersil.com/en/products.html about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability figure 47. vr1 setvid decay pre_emptive behavior, se tvid-fast 0.8v after setvid decay 0v from 0.9v, i o ? = ? 4a, ch1: phase1, ch2: vr1 v o , ch3: sda, ch4: ? phase2 revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change may 9, 2013 fn8315.0 initial release. typical performance (continued)
ISL95839 36 fn8315.0 may 9, 2013 package outline drawing l40.5x5 40 lead thin quad flat no-lead plastic package rev 1, 9/10 typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.27mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: (40x 0.60) 0.00 min 0.05 max (4x) 0.15 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail ?x? c c 5 6 a b b 0.10 m a c c 0.10 // 5.00 5.00 3.50 5.00 0.40 4x 3.60 36x 0.40 3.50 0.20 40x 0.4 0 .1 0.750 0.050 0.2 ref (40x 0.20) (36x 0.40 b package outline jedec reference drawing: mo-220whhe-1 7. 6 4

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