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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . 2 0 w s t e r e o d i g i t a l c l a s s - d a u d i o p o w e r a m p l i f i e r w i t h e q , d r c a n d 2 . 1 m o d e a p a 3 1 6 9 t h e a p a 3 1 6 9 i s a d i g i t a l i n p u t , s t e r e o , h i g h e f f i c i e n c y , c l a s s - d a u d i o a m p l i f i e r a v a i l a b l e i n a t q f p 7 x 7 - 4 8 p p a c k a g e . t h e a p a 3 1 6 9 a c c e p t s t h e d i g i t a l s e r i a l a u d i o d a t a a n d u s i n g t h e d i g i t a l a u d i o p r o c e s s o r t o c o n v e r t t h e a u d i o d a t a b e c o m e s t h e s t e r e o c l a s s - d o u t p u t s p e a k e r a m p l i f i e r . t h i s p r o v i d e s t h e s e a m l e s s i n t e g r a t i o n b e t w e e n t h e c o d e c a n d t h e s p e a k e r a m p l i f i e r . t h e a p a 3 1 6 9 i s a s l a v e d e v i c e r e c e i v i n g c l o c k s f r o m e x - t e r n a l s o u r c e , a n d t h e c l a s s - d ? s p w m s w i t c h i n g f r e - q u e n c y i s 3 5 2 . 8 k h z f o r t h e s a m p l i n g r a t e 4 4 . 1 k h z o r 3 8 4 k h z f o r s a m p l i n g 4 8 k h z , d e p e n d o n t h e i n p u t s i g n a l ? s s a m p l i n g r a t e . o p e r a t i n g v o l t a g e : 8 . 0 v - 2 4 v f o r p v d d ? 3 . 0 v ~ 3 . 6 v f o r d v d d a n d a v d d h i g h e f f i c i e n c y c l a s s d o p e r a t i o n e l i m i n a t e t h e n e e d o f h e a t s i n k s d i g i t a l s e r i a l a u d i o i n p u t ( s t e r e o o u t p u t ) 2 . 1 m o d e ( 2 s e + 1 b t l ) 2 . 0 m o d e ( 2 b t l ) s i n g l e - f i l t e r p b t l m o d e s u p p o r t i 2 c a d d r e s s s e l e c t i o n p i n ( c h i p s e l e c t ) i 2 c c o n t r o l i n t e r f a c e s a m p l i n g r a t e s u p p o r t f r o m 3 2 k h z t o 1 9 2 k h z s e p a r a t e d v o l u m e c o n t r o l f r o m 2 4 d b t o m u t e s o f t m u t e ( 5 0 % d u t y c y c l e ) s e p a r a t e d y n a m i c r a n g e c o n t r o l f o r s a t e l l i t e a n d s u b c h a n n e l s 1 8 p r o g r a m m a b l e b i q u a d s f o r s p e a k e r e q a n d o t h e r a u d i o p r o c e s s i n g f e a t u r e s p r o g r a m m a b l e c o e f f i c i e n t s f o r d r c f i l t e r s d c b l o c k i n g f i l t e r s , d e - e m p h a s i s f i l t e r s s u p p o r t f o r 3 d e f f e c t s s h u t d o w n a n d m u t e f u n c t i o n t h e r m a l a n d o v e r - c u r r e n t p r o t e c t i o n s w i t h a u t o - r e c o v e r y s p a c e s a v i n g p a c k a g e t q f p 7 x 7 - 4 8 p l e a d f r e e a n d g r e e n d e v i c e s a v a i l a b l e ( r o h s c o m p l i a n t ) f e a t u r e s g e n e r a l d e s c r i p t i o n a p p l i c a t i o n s l c d t v i p o d d o c k s o u n d b a r s i m p l i f i e d a p p l i c a t i o n c i r c u i t apa 3169 out _ a out _ c out _ b out _ d digital audio source i 2 c control sda scl mclk lrclk sclk sdin control input loop filter a _ sel pll _ fltp pll _ fltm lc se pvdd lc se lc btl pvdd / reset _ n / pdn _ n free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 a p a 3 1 6 9 p i n c o n f i g u r a t i o n o r d e r i n g a n d m a r k i n g i n f o r m a t i o n n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . apa 3169 handling code temp erature range package code package code qca : tqfp 7 x 7 - 48 p operating ambient temperature range i : - 40 to 85 o c handling code tr : tape & reel assembly material g : halogen and lead free device apa 3169 qca : apa 3169 xxxxx xxxxx - date code assembly material bs _ a 4 avss 9 pbtl 8 pll _ fltm 10 pll _ fltp 11 vclab 5 tm 1 6 pvdd _ a 2 pvdd _ a 3 tm 2 7 vr _ ana 12 out _ a 1 33 bs _ d 28 dvss 35 pvdd _ d 32 vclcd 27 dvdd 34 pvdd _ d 36 out _ d 25 reset _ n 31 vreg 30 agnd 26 tp 3 29 dgnd apa 3169 a v d d 1 3 a _ s e l 1 4 m c l k 1 5 t p 1 1 6 t p 2 1 7 v r _ d i g 1 8 l r c l k 2 0 s c l k 2 1 s d i n 2 2 s d a 2 3 s c l 2 4 4 8 p g n d _ a b 4 7 p g n d _ a b 4 6 o u t _ b 4 5 p v d d _ b 4 4 p v d d _ b 4 3 b s _ b 4 2 b s _ c 4 1 p v d d _ c 4 0 p v d d _ c 3 9 o u t _ c 3 8 p g n d _ c d 3 7 p g n d _ c d p d n _ n 1 9 tqfp 7 x 7 - 48 p ( top view ) free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 a p a 3 1 6 9 symbol parameter rating unit v pvdd supply voltage (pvdd_x to pgnd_xx) - 0.3 to 26 v dvdd supply voltage (dvdd to dvss) - 0.3 to 6 v avdd supply voltage (avdd to avss) - 0.3 to 6 input voltage (mclk to avss) - 0. 5 to 6 input voltage (pdn , reset, lrclk, sclk, sdin, sda, scl to dvss) - 0. 5 to 6 input voltage input voltage (avss, dvss, agdn to pgnd_xx) - 0.3 to +0.3 v out_x out_x to pgnd_xx - 0.3 to +26 v bs_x bs_x to pgnd_xx - 0.3 to +31 v t j maximum junction temperature 150 o c t stg storage temperature range - 65 to +150 o c t sdr soldering temperature range, 10 seconds 260 o c p d power dissipation internally limited w a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. symbol parameter typical value unit q ja junction - to - ambient resistance in f ree a ir (note 2) tqfp7x7 - 4 8 p 25 c/w t h e r m a l c h a r a c t e r i s t i c s note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. the exposed pad of tqfp7x7-48p is soldered directly on the pcb. range symbol parameter min. max. unit v avdd , v dvdd analog/digital supply voltage (avdd,dvdd) 3 3.6 v pvdd full bridge stage supply voltage (pvdd_x) 8 24 v ih high l evel t hreshold v oltage pd n, mclk, lrclk, sclk, sdin, sda, scl, reset 2 5 v il lo w l evel t hreshold v oltage pd n, mclk, lrclk, sclk, sdin, sda, scl, reset 0 0.8 v t a ambient t emperature range - 40 85 t j junction temperature range - 40 125 o c r l (btl) speaker resistance 6 - w l o (btl) output low pass filter inductance 10 47 m h r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 a p a 3 1 6 9 e l e c t r i c a l c h a r a c t e r i s t i c s t a = 2 5 o c , v p v d d = 1 8 v , v a v d d = v d v d d = 3 . 3 v , r l = 8 w , b d m o d e , f s = 4 8 k h z ( u n l e s s o t h e r w i s e n o t e d ) APA3169 symbol parameter test condition s min. typ. max. unit pwm operating conditions 32 khz data rate 2% 256 44.1k/88.2k/176.4 khz data rate 2% 352.8 f s output sample rate 48k/96k/192 khz data rate 2% 384 khz pll input parameters a nd external filter components f mclk mclk frequency 2.8224 - 24.576 m hz mclk duty cycle 40 50 60 % tr/tf (mclk) rise/fall time for mclk - - 5 ns lrclk allowable drift before lrclk reset - - 4 mclks external pll filter capacitor c1 smd 0603 y5v - 47 - external pll filter capacitor c2 smd 0603 y5v - 4.7 - nf external pll filter resistor r - 470 - w dc characteristics v oh high level output voltage(a_sel and sda) i oh = - 4ma, dvdd=avdd=3v 2.4 - - v v ol low level output voltage(a_sel and sda) i o l =4ma, dvdd=avdd=3v - - 0.5 v i il low level input current v i v ih , d vdd =avdd =3.6v - - 75 m a normal mode ( no lc, no load) - 14 20 i dd 3.3v supply current (avdd + dvdd) reset ( no lc, no load ) - 14 20 normal mode ( no lc, no load) - 18 36 i pvdd full bridge stage supply current (pvdd_x) reset ( no lc, no load) - 0.5 1.6 ma drain to source resistance,ls t j =25 o c , includes metallization resistance - 180 - m w r ds(on) drain to source resistance ,hs t j =25 o c , includes metallization resistance - 180 - m w v uvp undervoltage protection limit pvdd falling - 6.8 - v v uvp,hyst undervoltage protection limit pvdd rising - 7.2 - v thermal protection threshold - 150 - t tp thermal protection threshold hysteresis - 30 - o c free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 5 a p a 3 1 6 9 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) APA3169 symbol parameter test condition s min. typ. max. unit dc characteristics (cont.) olpc overload protection counter f pwm =384khz - 0.63 - ms i oc overcurrent limit protection resistor - programmable, max. current - 4.5 - a i oct overcurrent response time - 150 - ns r out internal pull - down resistance at each out_x ccaopnanceitcoter dchwahrgeen. drivers are tristated to provide bootstrap - 3 - k w ac characteristics v p v dd =18 v 14.5 16 - v p v dd =12 v 6.5 7.2 - btl, thd+n= 1 % , f in =1khz,r l =8 w v p v dd =8 v 2.9 3.2 - v p v dd =18 v - 20 - v p v dd =12 v - 9 - btl, thd+n=10 % , f in =1khz,r l =8 w v p v dd =8 v - 4 - v p v dd =18 v - 30.5 - pbtl, thd+n= 1 % , f in =1khz ,r l = 4 w v p v dd =12 v - 13.7 - v p v dd =18 v - 37.1 - pbtl, thd+n= 1 0 % , f in =1khz,r l = 4 w v p v dd =12 v - 16.9 - v p v dd =18 v - 7.5 - se , thd+n= 1 % , f i n =1khz,r l = 4 w v p v dd =12 v - 3.4 - v p v dd =18 v - 9.5 - p o output power se , thd+n= 10 % , f in =1khz,r l = 4 w v p v dd =12 v - 4.3 - w v p v dd =18 v , po=1w - 0.06 - v p v dd =12 v , po=1w - 0.13 - thd+n total harmonic distortion pl u s noise f in =1khz,r l =8 w v p v dd =8 v , po=1w - 0.2 - % vn noise output voltage with a - weighting filter ( volume =0db) - 200 - m vms crosstalk chan nel separation p o =0.25w, r l =8 w , f in =1khz - - 72 - snr signal to noise ratio r l =8 w , po=16w, a - weighting filter ( volume =0db) - 95 - att mute mute attenuation f in =1 k hz , r l = 8 w , v o = 1v rms - - 70 - att shutdown shutdown attenuation f in =1 k hz , r l = 8 w , v o = 1v rms - - 110 - db t a = 2 5 o c , v p v d d = 1 8 v , v a v d d = v d v d d = 3 . 3 v , r l = 8 w , b d m o d e , f s = 4 8 k h z ( u n l e s s o t h e r w i s e n o t e d ) free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 6 a p a 3 1 6 9 s e r i a l a u d i o p o r t s s l a v e m o d e APA3169 symbol parameter test condition s min. typ. max. unit f sclk frequency, sclk 32xf s , 48xf s , 64xf s c l =30pf 1.024 - 12.288 mhz t setup1 setup time, lrclk to sclk rising edge 10 - - t hold1 hold time, lrclk to sclk rising edge 10 - - t setup 2 setup time, sdin to sclk rising edge 10 - - t hold hold time, sdin to sclk rising edge 10 - - ns lrclk frequency 32 48 192 khz lrclk duty cycle 40 50 60 sclk duty cycle 40 50 60 % sclk rising edges between lrclk riding edges 32 - 64 sclk ed ges t (edge) lrclk clock edge with respect to the falling edge of sclk - 1/4 - 1/4 sclk period tr/tf (sclk/lrclk) rise/fall time for sclk/lrclk - - 8 ns o v e r r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( u n l e s s o t h e r w i s e n o t e d ) lrclk ( input ) sdin t ( edge ) t h 1 t su 1 t su 2 t h 2 t r t f sclk ( input ) f i g u r e 1 . s l a v e m o d e s e r i a l d a t a i n t e r f a c e t i m i n g free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 7 a p a 3 1 6 9 i 2 c s e r i a l c o n t r o l p o r t o p e r a t i o n t i m i n g c h a r a c t e r i s t i c s f o r i 2 c i n t e r f a c e s i g n a l s o v e r r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( u n l e s s o t h e r w i s e n o t e d ) APA3169 symbol parameter test condition s min. typ. max. unit f scl frequency, scl no wait states - - 400 khz t w(h) pulse duration, scl high 0.6 - - t w(l) pulse duration, scl low 1.3 - - m s t r rise time, scl and sda - - 300 t f fall time, sc l and sda - - 300 t setup1 setup time, scl to sda 100 - - t hold1 hold time, scl to sda 0 - - ns t (buf) bus free time between stop and start condition 1.3 - - t setup2 setup time, scl to start condition 0.6 - - t hold2 hold time, start condition to scl 0.6 - - t setup3 setup time, scl to stop condition 0.6 - - m s c l load capacitance for each bus line - - 400 pf f i g u r e 2 . s c l a n d s d a t i m i n g f i g u r e 2 . s c l a n d s d a t i m i n g sda t h 2 t su 2 t ( buf ) t su 3 scl start condition stop condition sda t w ( h ) t w ( l ) t su 1 t h 1 t f t r scl free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 8 a p a 3 1 6 9 r e s e t t i m i n g c o n t r o l s i g n a l p a r a m e t e r s o v e r r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( u n l e s s o t h e r w i s e n o t e d ) . p l e a s e r e f e r t o ? r e c - o m m e n d e d u s e m o d e l ? s e c t i o n o n u s a g e o f a l l t e r m i n a l s . APA3169 symbol parameter test condition s min. typ. max. unit t p(rst) pulse duration, reset active. no load 100 - - m s t d(12c_ready) time to enable i 2 c - - 13.5 ms f i g u r e 4 . r e s e t t i m i n g reset t d ( i 2 c _ ready ) t w ( reset ) i 2 c active i 2 c active free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 9 a p a 3 1 6 9 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s , b t l c o n f i g u r a t i o n po = 2 . 5 w po = 1 w po = 0 . 5 w pv dd = 8 v r l = 8 w aux - 0025 aes - 17 ( 20 khz ) thd + n vs . frequency t h d + n ( % ) frequency ( hz ) 0 . 001 10 0 . 01 0 . 1 1 20 20 k 50 100 500 1 k 2 k 5 k 20 20 k 50 100 500 1 k 2 k 5 k po = 5 w po = 2 . 5 w po = 1 w pv dd = 12 v r l = 8 w aux - 0025 aes - 17 ( 20 khz ) thd + n vs . frequency t h d + n ( % ) frequency ( hz ) 0 . 001 10 0 . 01 0 . 1 1 20 20 k 50 100 500 1 k 2 k 5 k po = 5 w po = 2 . 5 w po = 1 w pv dd = 18 v r l = 8 w aux - 0025 aes - 17 ( 20 khz ) thd + n vs . frequency t h d + n ( % ) frequency ( hz ) 0 . 001 10 0 . 01 0 . 1 1 20 20 k 50 100 500 1 k 2 k 5 k po = 5 w po = 2 . 5 w po = 1 w pv dd = 24 v r l = 8 w aux - 0025 aes - 17 ( 20 khz ) thd + n vs . frequency t h d + n ( % ) frequency ( hz ) 0 . 001 10 0 . 01 0 . 1 1 0 . 001 10 0 . 01 0 . 1 1 10 m 50 100 m 1 2 5 10 thd + n vs . output power output power ( w ) t h d + n ( % ) pv dd = 8 v r l = 8 w duty = 97 . 7 % aux - 0025 aes - 17 ( 20 khz ) fin = 20 hz fin = 1 khz fin = 10 khz 0 . 001 10 0 . 01 0 . 1 1 10 m 50 100 m 1 2 5 10 thd + n vs . output power pv dd = 12 v r l = 8 w duty = 97 . 7 % aux - 0025 aes - 17 ( 20 khz ) output power ( w ) t h d + n ( % ) fin = 20 hz fin = 1 khz fin = 10 khz free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 0 a p a 3 1 6 9 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s , b t l c o n f i g u r a t i o n ( c o n t . ) 0 . 001 10 0 . 01 0 . 1 1 10 m 50 100 m 1 2 5 10 thd + n vs . output power output power ( w ) t h d + n ( % ) pv dd = 1 8 v r l = 8 w duty = 97 . 7 % aux - 0025 aes - 17 ( 20 khz ) fin = 20 hz fin = 1 khz fin = 10 khz 0 . 001 10 0 . 01 0 . 1 1 10 m 50 100 m 1 2 5 10 t thd + n vs . output power pv dd = 24 v r l = 8 w duty = 97 . 7 % aux - 0025 aes - 17 ( 20 khz ) output power ( w ) t h d + n ( % ) fin = 20 hz fin = 1 khz fin = 10 khz - 100 + 0 - 80 - 60 - 40 - 20 20 20 k 50 100 500 1 k 2 k 5 k crosstalk vs . frequency c r o s s t a l k ( d b ) frequency ( hz ) pv dd = 8 v p o = 1 w r l = 8 w aux - 0025 10 ~ 22 khz left to right right to left - 100 + 0 - 80 - 60 - 40 - 20 20 20 k 50 100 500 1 k 2 k 5 k crosstalk vs . frequency c r o s s t a l k ( d b ) frequency ( hz ) pv dd = 12 v p o = 1 w r l = 8 w aux - 0025 10 ~ 22 khz left to right right to left - 100 + 0 - 80 - 60 - 40 - 20 20 20 k 50 100 500 1 k 2 k 5 k crosstalk vs . frequency c r o s s t a l k ( d b ) frequency ( hz ) left to right right to left pv dd = 18 v p o = 1 w r l = 8 w aux - 0025 10 ~ 22 khz - 100 + 0 - 80 - 60 - 40 - 20 20 20 k 50 100 500 1 k 2 k 5 k crosstalk vs . frequency c r o s s t a l k ( d b ) frequency ( hz ) left to right right to left pv dd = 24 v p o = 1 w r l = 8 w aux - 0025 10 ~ 22 khz free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 1 a p a 3 1 6 9 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s , b t l c o n f i g u r a t i o n ( c o n t . ) output power vs . supply voltage 0 5 10 15 20 25 30 35 40 8 10 12 14 16 18 20 22 24 26 supply voltage ( v ) b t l o u t p u t p o w e r _ o u t a b ( w ) r l = 8 w duty = 97 . 7 % thd + n = 10 % thd + n = 1 % efficiency vs . output power 0 10 20 30 40 50 60 70 80 90 100 0 2 4 6 8 10 12 14 16 18 20 22 24 outab output power ( w ) e f f i c i e n c y ( % ) pvdd = 8 v pvdd = 12 v pvdd = 18 v r l = 8 w duty = 97 . 7 % pvdd = 24 v free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 2 a p a 3 1 6 9 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s , s e c o n f i g u r a t i o n output power vs . supply voltage 0 2 4 6 8 10 12 14 16 18 20 22 8 10 12 14 16 18 20 22 24 26 supply voltage ( v ) s e o u t p u t p o w e r _ o u t a ( w ) r l = 4 w duty = 97 . 7 % thd + n = 10 % thd + n = 1 % 0 . 001 10 0 . 01 0 . 1 1 20 20 k 50 100 500 1 k 2 k 5 k po = 2 . 5 w po = 1 w po = 0 . 5 w pv dd = 12 v r l = 4 w aux - 0025 aes - 17 ( 20 khz ) thd + n vs . frequency t h d + n ( % ) frequency ( hz ) 0 . 001 10 0 . 01 0 . 1 1 20 20 k 50 100 500 1 k 2 k 5 k po = 5 w po = 2 . 5 w po = 1 w pv dd = 18 v r l = 4 w aux - 0025 aes - 17 ( 20 khz ) thd + n vs . frequency t h d + n ( % ) frequency ( hz ) 0 . 001 10 0 . 01 0 . 1 1 20 20 k 50 100 500 1 k 2 k 5 k po = 5 w po = 2 . 5 w po = 1 w pv dd = 24 v r l = 4 w aux - 0025 aes - 17 ( 20 khz ) thd + n vs . frequency t h d + n ( % ) frequency ( hz ) 0 . 001 10 0 . 01 0 . 1 1 10 m 50 100 m 1 2 5 10 20 thd + n vs . output power fin = 1 khz r l = 4 w duty = 97 . 7 % aux - 0025 aes - 17 ( 20 khz ) output power ( w ) t h d + n ( % ) pvdd = 8 v pvdd = 12 v pvdd = 18 v pvdd = 24 v free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 3 a p a 3 1 6 9 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s , p b t l c o n f i g u r a t i o n 0 . 001 10 0 . 01 0 . 1 1 20 20 k 50 100 500 1 k 2 k 5 k po = 5 w po = 2 w po = 1 w pv dd = 8 v r l = 4 w aux - 0025 aes - 17 ( 20 khz ) thd + n vs . frequency t h d + n ( % ) frequency ( hz ) 0 . 001 10 0 . 01 1 1 20 20 k 50 100 500 1 k 2 k 5 k pv dd = 12 v r l = 4 w aux - 0025 aes - 17 ( 20 khz ) thd + n vs . frequency t h d + n ( % ) frequency ( hz ) po = 5 w po = 2 w po = 1 w 0 . 001 10 0 . 01 0 . 1 1 20 20 k 50 100 500 1 k 2 k 5 k pv dd = 18 v r l = 4 w aux - 0025 aes - 17 ( 20 khz ) thd + n vs . frequency t h d + n ( % ) frequency ( hz ) po = 5 w po = 2 w po = 1 w 0 . 001 10 0 . 01 0 . 1 1 20 20 k 50 100 500 1 k 2 k 5 k thd + n vs . frequency t h d + n ( % ) frequency ( hz ) pv dd = 24 v r l = 4 w aux - 0025 aes - 17 ( 20 khz ) po = 5 w po = 2 w po = 1 w 0 . 001 10 0 . 01 0 . 1 1 10 m 50 100 m 1 2 5 10 pvdd = 8 v r l = 4 w duty = 97 . 7 % aux - 0025 aes - 17 ( 20 khz ) thd + n vs . output power t h d + n ( % ) output power ( w ) fin = 20 hz fin = 1 khz fin = 10 khz 0 . 001 10 0 . 01 0 . 1 1 10 m 50 100 m 1 2 5 10 thd + n vs . output power output power ( w ) t h d + n ( % ) pvdd = 12 v r l = 4 w duty = 97 . 7 % aux - 0025 aes - 17 ( 20 khz ) fin = 20 hz fin = 1 khz fin = 10 khz free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 4 a p a 3 1 6 9 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s , p b t l c o n f i g u r a t i o n ( c o n t . ) output power vs . supply voltage 0 10 20 30 40 50 60 8 10 12 14 16 18 20 22 24 26 supply voltage ( v ) p b t l o u t p u t p o w e r _ o u t a b c d ( w ) 0 . 001 10 0 . 01 0 . 1 1 10 m 50 100 m 1 2 5 10 20 pvdd = 18 v r l = 4 w duty = 97 . 7 % aux - 0025 aes - 17 ( 20 khz ) thd + n vs . output power t h d + n ( % ) output power ( w ) fin = 20 hz fin = 1 khz fin = 10 khz 0 . 001 10 0 . 01 0 . 1 1 10 m 50 100 m 1 2 5 10 20 thd + n vs . output power output power ( w ) t h d + n ( % ) pvdd = 24 v r l = 4 w duty = 97 . 7 % aux - 0025 aes - 17 ( 20 khz ) fin = 20 hz fin = 1 khz fin = 10 khz free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 5 a p a 3 1 6 9 pin no. name i/o/p function 1 out_a o output,half - bridge a 2,3 pvdd_a p power supply input 4 bs_a p high - side bootstrap supply for half - bridge a 5 vclab p internal 3.3v reference voltage 6 tm1 i test mode input 7 tm2 i test mode input 8 pbtl i lo w means btl or se mode;high means pbtl mode 9 avss p analog 3.3v supply ground 10 pll_fltm o pll negative loop filter 11 pll_fltp o pll postive loop filter 12 vr_ana p analog regulator 13 avdd p 3.3v amalog power supply 14 a_sel i/o input: device add ress, output : fault 15 mclk i master clock input 16 tp1 i/o test mode probe 17 tp2 i/o test mode probe 18 vr_dig p digital regulator 19 pdn_n i power down,active low 20 lrclk i input serial audio data left/right clock 21 sclk i serial audio data cl ock. 22 sdin i serial audio data input 23 sda i/o i2c serial control data interface input/output 24 scl i i2c serial control clock input 25 reset_n i reset,active low 26 tp3 i/o test mode probe 27 dvdd p 3.3v digital power supply 28 dvss p digital g round 29 dgnd p digital ground for power stage 30 agnd p analog ground for power stage 31 vreg p not to be used for powering external circuitry 32 vclcd p internal 3.3v reference voltage 33 bs_d p high - side bootstrap supply for half - bridge d 34,35 pv dd_d p power supply input 36 out_d o output,half bridge d 37,38 pgnd_cd p power ground for half - bridge c and d 39 out_c o output,half - bridge c p i n d e s c r i p t i o n free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 6 a p a 3 1 6 9 p i n d e s c r i p t i o n pin no. name i/o/p function 40,41 pvdd_c p power supply input 42 bs_c p high - side bootstrap supply for half - bridge c 43 bs_b p high - side bootstrap supply for half - bridge b 44,45 pvdd_b p power supply input 46 out_b o output ,half bridge b 47,48 pg nd_ab p power ground for half - bridge a and b b l o c k d i a g r a m p w r _ s e q i i s t e s t o u t sdm output - map inter - polation i i c s e r i a l c o n t r o l i i s s e r i a l a u d i o p o r t s d i n s c l k l r c l k s d a s c l pcm to pwm p w m p r o c e s s o r m c l k r e g i s t e r p r e _ d i v p l l p d n t m 1 t m 2 r e s e t n dap r e g u l a t o r fifo fir l r l r l f e power stage a _ s e l c k g o u t a o u t b o u t c o u t d v a l i d e r r o r _ b o t w o u t a o u t b o u t c o u t d t p 1 t p 2 t p 3 f i g u r e 5 . b l o c k d i a g r a m free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 7 a p a 3 1 6 9 b l o c k d i a g r a m l r 1 b q 1 b q p r e _ s c a l e m i x e r 1 b q m i x e r 3 b q 2 b q m i x e r m i x e r 1 b q m i x e r 3 b q 2 0 x 5 1 m i x e r 2 b q 1 b q 1 b q c h 1 _ v o l c h 2 _ v o l c h 3 _ v o l c h 4 _ v o l master _ vol drc 1 mixer post _ scale l r s u b _ c h a n n e l d c _ b l o c k i n g d c _ b l o c k i n g d e _ e m p h a s i s d e _ e m p h a s i s 0 x 5 2 0 x 6 0 m i x 2 m i x 1 m i x 0 m i x 1 m i x 2 m i x 0 m i x 1 m i x 0 0 x 5 3 0 x 5 4 0 x 5 5 0 x 6 1 m i x 0 m i x 1 m i x 2 m i x 0 m i x 1 m i x 0 m i x 1 m i x 2 m i x 3 m i x 2 m i x 3 m i x 0 m i x 1 0 x 2 9 0 x 2 a 0 x 2 b ~ 2 d 0 x 5 8 ~ 5 9 0 x 3 0 0 x 3 1 0 x 3 2 ~ 3 4 b q 0 x 5 c ~ 5 d 0 x 5 a 0 x 5 b 0 x 5 e ~ 5 f 0 x 5 3 0 x 5 4 mixer mixer drc 1 f i g u r e 6 . d a p b l o c k d i a g r a m free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 8 a p a 3 1 6 9 t y p i c a l a p p l i c a t i o n c i r c u i t 2.0 channel 1 3 1 3 7 2 5 / reset avdd scl lrck sclk sdin 4700 p f apa 3169 sda 0 o 10 f 2200 pf 4700 pf jp 1 p b t l a v s s p l l _ f l t m p l l _ f l t p v r _ a n a p v d d _ a b s _ a v c l a b t m 1 t m 2 o u t _ a p v d d _ a a v d d a _ s e l m c l k t p 1 t p 2 s c l v r _ d i g / p d n _ n l r c l k s c l k s d i n s d a 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 d g n d d v s s d v d d t p 3 / r e s e t _ n p v d d _ d b s _ d v c l c d v r e g a g n d o u t _ d p v d d _ d p g n d _ a b p g n d _ a b o u t _ b p v d d _ b p v d d _ b p g n d _ c d b s _ b b s _ c p v d d _ c p v d d _ c o u t _ c p g n d _ c d 0 . 1 f 10 k o mclk a _ sel 18 . 2 k o 0 . 1 f 4 . 7 f 10 k o av dd / pdn dvdd 0 . 1 f 10 f 0 . 1 f 1 f 0 . 033 f pvdd 0 . 1 f 220 f 22 h 0 . 68 f 0 . 68 f 22 h 0 . 033 f 0 . 033 f 0 . 1 f 0 . 1 f pvdd 22 h 22 h 0 . 68 f 0 . 68 f pvdd 220 f 0 . 1 f 0 . 033 f 1 f 2 2 . 1 k o 10 k o 470 o 470 o 0 . 047 f 0 . 047 f avdd free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 9 a p a 3 1 6 9 t y p i c a l a p p l i c a t i o n c i r c u i t 2.1 channel 1 3 1 3 7 2 5 / reset avdd scl lrck sclk sdin 4700 p f apa 3169 sda 0 o 10 f 2200 pf 4700 pf jp 1 p b t l a v s s p l l _ f l t m p l l _ f l t p v r _ a n a p v d d _ a b s _ a v c l a b t m 1 t m 2 o u t _ a p v d d _ a a v d d a _ s e l m c l k t p 1 t p 2 s c l v r _ d i g / p d n _ n l r c l k s c l k s d i n s d a 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 d g n d d v s s d v d d t p 3 / r e s e t _ n p v d d _ d b s _ d v c l c d v r e g a g n d o u t _ d p v d d _ d p g n d _ a b p g n d _ a b o u t _ b p v d d _ b p v d d _ b p g n d _ c d b s _ b b s _ c p v d d _ c p v d d _ c o u t _ c p g n d _ c d 0 . 1 f 10 k o mclk a _ sel 18 . 2 k o 0 . 1 f 4 . 7 f 10 k o av dd / pdn dvdd 0 . 1 f 10 f 0 . 1 f 1 f 0 . 033 f pvdd 0 . 1 f 220 f 22 h 0 . 68 f 0 . 68 f 22 h 0 . 033 f 0 . 033 f 0 . 1 f 0 . 1 f pvdd 22 h 22 h 0 . 68 f 0 . 68 f pvdd 220 f 0 . 1 f 0 . 033 f 1 f 2 2 . 1 k o 10 k o 470 o 470 o 0 . 047 f 0 . 047 f avdd 220 f 220 f 10 k o 10 k o v dd 220 f 220 f 10 k o 10 k o v dd free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 0 a p a 3 1 6 9 t y p i c a l a p p l i c a t i o n c i r c u i t pbtl 1 3 1 3 7 2 5 / reset avdd scl lrck sclk sdin 4700 p f apa 3169 sda 0 o 10 f 2200 pf 4700 pf jp 1 p b t l a v s s p l l _ f l t m p l l _ f l t p v r _ a n a p v d d _ a b s _ a v c l a b t m 1 t m 2 o u t _ a p v d d _ a a v d d a _ s e l m c l k t p 1 t p 2 s c l v r _ d i g / p d n _ n l r c l k s c l k s d i n s d a 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 d g n d d v s s d v d d t p 3 / r e s e t _ n p v d d _ d b s _ d v c l c d v r e g a g n d o u t _ d p v d d _ d p g n d _ a b p g n d _ a b o u t _ b p v d d _ b p v d d _ b p g n d _ c d b s _ b b s _ c p v d d _ c p v d d _ c o u t _ c p g n d _ c d 0 . 1 f 10 k o mclk a _ sel 18 . 2 k o 0 . 1 f 4 . 7 f 10 k o av dd / pdn dvdd 0 . 1 f 10 f 0 . 1 f 1 f 0 . 033 f pvdd 0 . 1 f 220 f 22 h 0 . 68 f 0 . 033 f 0 . 033 f 0 . 1 f 0 . 1 f pvdd 22 h 0 . 68 f pvdd 220 f 0 . 1 f 0 . 033 f 1 f 2 2 . 1 k o 10 k o 470 o 470 o 0 . 047 f 0 . 047 f avdd free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 1 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n power supply to facilitate system design, the APA3169 needs only a 3.3-v supply in addition to the (typical) 18-v power-stage supply. an internal voltage regulator provides suitable voltage levels for the gate drive circuitry. additionally, all circuitry requir- ing a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors. in order to provide good electrical and acoustical characteristics, the pwm signal path for the output stage is designed as identical, independent half-bridges. for this reason, each half-bridge has separate bootstrap pins (bs_x), and power-stage supply pins (pvdd_x). the gate drive voltages (vclab and vclcd) are derived from the pvdd voltage. special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. in general, inductance between the power-supply pins and decoupling capacitors must be avoided. for a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (bs_x) to the power-stage output pin (out_x). when the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive regulator output pin (vcl_x) and the bootstrap pin. when the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. in an application with pwm switching frequencies in the range from 256 khz to 384 khz, it is recommended to use 33-nf 50-v x7r capacitors, size 0603 or 0805, for the bootstrap supply. these 33-nf capacitors ensure sufficient energy storage, even during minimal pwm duty cycles, to keep the high-side power stage fet (ldmos) fully turned on during the remaining part of the pwm cycle. special attention should be paid to the power-stage power supply; this includes component selection, pcb placement, and routing. as indicated, each half-bridge has independent power-stage supply pins (pvdd_x). for optimal electrical performance, emc compliance, and system reliability, it is important that each pvdd_x pin is decoupled with a 100-nf ceramic capacitor placed as close as possible to each supply pin. the APA3169 is fully protected against erroneous power-stage turnon due to parasitic gate charging. device protection system overcurrent (oc) protection with current limiting the device has independent, fast-reacting current detectors on all high-side and low-side power-stage fets. the detector outputs are closely monitored by two protection systems. the first protection system controls the power stage in order to prevent the output current further increasing, i.e., it performs a cycle-by-cycle current-limiting function, rather than prematurely shutting down during combinations of high-level music transients and extreme speaker load impedance drops. if the high-current condition situation persists, i.e., the power stage is being overloaded, a second protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (hi-z) state. the device returns to normal operation once the fault condition (i.e., a short circuit on the output) is removed. current limiting and overcurrent protection are not independent for half-bridges. that is, if the bridge-tied load between half-bridges a and b causes an overcurrent fault, half-bridges a, b, c, and d are shut down. pwm section overtemperature protection the APA3169 has over temperature-protection system. if the device junction temperature exceeds 150 o c (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (hi-z) state and /fault being asserted low. the APA3169 recovers automatically once the temperature drops approximately 30 o c free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 2 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) undervoltage protection (uvp) and power-on reset (por) the uvp and por circuits of the APA3169 fully protect the device in any power-up/down and brownout situation. while powering up, the por circuit resets the overload circuit and ensures that all circuits are fully operational when the pvdd and avdd supply voltages reach 7.6 v and 2.7 v, respectively. although pvdd and avdd are independently monitored, a supply voltage drop below the uvp threshold on avdd or either pvdd pin results in all half-bridge outputs immediately being set in the high-impedance (hi-z) state and /fault being asserted low. serial data interface serial data is input on sdin. the pwm outputs are derived from sdin. the APA3169 dap accepts serial data in 16-, 20-, or 24-bit left-justified, right-justified, and i2s serial data formats. pwm section the APA3169 dap device uses noise-shaping to achieve high power efficiency and high-performance digital audio reproduction. the dap uses a fourth-order noise shaper to increase dynamic range and snr in the audio band. the pwm section accepts pcm data from the dap and outputs two btl pwm audio output channels. the pwm section has individual channel dc blocking filters that can be enabled and disabled. the filter cutoff frequency is less than 1 hz. individual channel de-emphasis filters are included and can be enabled and disabled. finally, the pwm section has an adjustable maximum modulation limit of 93.8% to 98.4%. serial interface control and timing t h e i 2 s m o d e i s s e t b y w r i t i n g t o r e g i s t e r 0 x 0 4 . i 2 s timing i 2 s t i m i n g u s e s l r c l k t o d e f i n e w h e n t h e d a t a b e i n g t r a n s m i t t e d i s f o r t h e l e f t c h a n n e l a n d w h e n i t i s f o r t h e r i g h t c h a n n e l . l r c l k i s l o w f o r t h e l e f t c h a n n e l a n d h i g h f o r t h e r i g h t c h a n n e l . a b i t c l o c k r u n n i n g a t 3 2 , 4 8 , o r 6 4 x f s i s u s e d t o c l o c k i n t h e d a t a . t h e r e i s a d e l a y o f o n e b i t c l o c k f r o m t h e t i m e t h e l r c l k s i g n a l c h a n g e s s t a t e t o t h e f i r s t b i t o f d a t a o n t h e d a t a l i n e s . t h e d a t a i s w r i t t e n m s b f i r s t a n d i s v a l i d o n t h e r i s i n g e d g e o f b i t c l o c k . t h e d a p m a s k s u n u s e d t r a i l i n g d a t a b i t p o s i t i o n s . f i g u r e 7 . i 2 s 6 4 f s f o r m a t 23 22 9 8 5 4 1 0 19 18 5 4 1 0 15 14 1 0 23 22 9 8 5 4 1 0 19 18 5 4 1 0 15 14 1 0 32 clks 32 clks lrclk (note reversed phase) left channel right channel sclk sclk msb msb lsb lsb 24-bit mode 20-bit mode 16-bit mode 24-bit mode 20-bit mode 16-bit mode free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 3 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) f i g u r e 8 . i 2 s 4 8 f s f o r m a t 15 14 12 11 9 8 5 4 1 6 c l k s 16clks lrclk (note reversed phase) left channel right channel sclk sclk msb lsb lsb 16-bit mode 3 2 1 0 msb 16-bit mode 13 10 15 14 12 11 9 8 5 4 3 2 1 13 10 f i g u r e 9 . i 2 s 3 2 f s f o r m a t 23 22 17 16 9 8 5 4 19 18 13 12 5 4 15 14 9 8 2 4 c l k s 24 clks lrclk (note reversed phase) left channel right channel sclk sclk msb lsb lsb 24-bit mode 20-bit mode 16-bit mode 1 0 1 0 3 2 1 0 23 22 17 16 9 8 5 4 19 18 13 12 5 4 15 14 9 8 msb 24-bit mode 20-bit mode 16-bit mode 1 0 1 0 3 2 1 left-justified left-justified (lj) timing uses lrclk to define the data for the left channel and the right channel when the data being transmitted. for the left channel, the lrclk is high; for the right channel, the lrclk is low. a bit clock running at 32, 48, or 64 f s is used to clock in the data. the first bit of data appears on the data lines when lrclk toggles. the data is written msb first and is valid on the rising edge of the bit clock. the dap masks unused trailing data bit positions. f i g u r e 1 0 . l e f t - j u s t i f i e d 6 4 f s f o r m a t 23 22 9 8 5 4 1 0 19 18 5 4 1 0 15 14 1 0 23 22 9 8 5 4 1 0 19 18 5 4 1 0 15 14 1 0 32clks 32clks lrclk left channel right channel sclk sclk msb msb lsb lsb 24-bit mode 20-bit mode 16-bit mode 24-bit mode 20-bit mode 16-bit mode free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 4 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) f i g u r e 1 1 . l e f t - j u s t i f i e d 4 8 f s f o r m a t f i g u r e 1 2 . l e f t - j u s t i f i e d 3 2 f s f o r m a t 23 22 17 16 9 8 5 4 19 18 13 12 5 4 15 14 9 8 2 4 c l k s 24 clks lrclk left channel right channel sclk sclk msb lsb lsb 24-bit mode 20-bit mode 16-bit mode 1 0 1 0 3 2 1 0 23 22 17 16 9 8 5 4 19 18 13 12 5 4 15 14 9 8 msb 24-bit mode 20-bit mode 16-bit mode 1 0 1 0 3 2 1 15 14 12 11 9 8 5 4 1 6 c l k s 16clks lrclk left channel right channel sclk sclk msb lsb lsb 16-bit mode 3 2 1 0 msb 16-bit mode 13 10 15 14 12 11 9 8 5 4 3 2 1 13 10 0 right-justified right-justified (rj) timing uses lrclk to define the data for the left channel and the right channel when the data being transmitted. for the left channel, the lrclk is high; for the right channel, the lrclk low. a bit clock running at 32, 48, or 64 f s is used to clock in the data. after lrclk toggles, for 24bit data, the first bit of data appears on the data 8 bit-clock. in rj mode, the lsb of data is always clocked by the last bit clock before lrclk transitions. the data is written msb first and is valid on the rising edge of bit clock. the dap masks unused leading data bit positions. f i g u r e 1 3 . r i g h t - j u s t i f i e d 6 4 f s f o r m a t 23 22 19 18 15 14 1 0 19 18 15 14 1 0 15 14 1 0 32 clks 32 clks lrclk left channel right channel sclk sclk msb msb lsb lsb 24-bit mode 20-bit mode 16-bit mode 23 22 19 18 15 14 1 0 19 18 15 14 1 0 15 14 1 0 24-bit mode 20-bit mode 16-bit mode free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 5 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) f i g u r e 1 4 . r i g h t - j u s t i f i e d 4 8 f s f o r m a t f i g u r e 1 5 . r i g h t - j u s t i f i e d 3 2 f s f o r m a t 23 22 19 18 15 14 1 0 19 18 15 14 1 0 1 0 24 clks 24 clks lrclk left channel right channel sclk sclk msb msb ls b ls b 24-bit mode 20-bit mode 16-bit mode 24-bit mode 6 5 2 6 5 2 15 14 6 5 2 23 22 19 18 15 14 1 0 19 18 15 14 1 0 1 0 20-bit mode 16-bit mode 6 5 2 6 5 2 15 14 6 5 2 15 14 12 11 9 8 5 4 1 6 c l k s 16clks lrclk left channel right channel sclk sclk msb lsb lsb 16-bit mode 3 2 1 0 msb 16-bit mode 13 10 15 14 12 11 9 8 5 4 3 2 1 13 10 0 i 2 c serial control interface the APA3169 dap has a bidirectional i 2 c interface that compatible with the i 2 c (inter ic) bus protocol. besides, it provides both 100khz and 400khz data transfer rates to single and multiple bytes write and read operations. this is a slave only device, and it doesn?t support a multi-master bus environment or wait state insertion. the function of the control interface is to read device status and to program the registers of the device. the dap supports the standard-mode i 2 c bus operation (100khz maximum) and the fast i 2 c bus operation (400khz maximum). without i 2 c wait cycles, the dap performs i 2 c operations. general i 2 c operation the i 2 c bus uses sda (data) and scl (clock) to communicate between integrated circuits in a system. data is transferred on the bus serially one bit at a time. with the most significant bit (msb) transferred first, the address and data can be transferred in byte (8bit) format. in addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. the bus uses transitions on the sda when the clock is high to indicate start and stop conditions. a high-to-low transition on sda indicates a start, and a low-to-high transition indicates a stop. normal data bit transitions must occur within the low time of the clock. these conditions are shown in figure 10. the master generates the 7bit slave address and the read/write (r/w) bit to open communication with another device and then waits for an acknowledge condition. the APA3169 holds sda low during the acknowledge clock to indicate an acknowledgment. when this occurs, the master transmits the next byte of the sequence. each device is addressed by a unique 7bit slave address plus r/w bit (1 byte). all compatible devices share the same signals via a bidirectional bus using a wired-and connection. an external pull-up resistor must be used for the sda and scl signals to set the high level for the bus. free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 6 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) f i g u r e 1 6 . t y p i c a l i 2 c s e q u e n c e 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7-bit slave address r/ w a 8-bit register address (n) 8-bit register data for address (n) a a a 8-bit register data for address (n) sda scl start stop there is no limit on the number of bytes that can be transmitted between start and stop conditions. when the last word transfers, the master generates a stop condition to release the bus. a generic data transfer sequence is shown in figure 16. pin a_sel defines the i2c device address. an external 15k w pulldown on this pin gives a device address of 0x34 and a 15k w pullup gives a device address of 0x36. the 7-bit address is 0011 010 (0x34) or 0011 011 (0x36). the serial control interface supports single-byte and multiple-byte (r/w) operations for sub-addresses 0x00 to 0x1f. however, for the sub-addresses 0x20 to 0xff, the serial control interface supports only multiple-byte read/write operations (in multiples of 4 bytes). during multiple-byte read operations, the dap responds with data, a byte at a time, starting at the sub-address assigned, as long as the master device continues to respond with acknowledges. if a particular sub-address does not contain 32 bits, the unused bits are read as logic 0. during multiple-byte write operations, the dap compares the number of bytes transmitted to the number of bytes that are required for each specific sub-address. supplying a sub-address for each sub-address transaction is referred to as random i 2 c addressing. the APA3169 also supports sequential i 2 c addressing. for write transactions, if a sub-address is issued and followed by data for that sub-address and the 15 sub-addresses that follow, a sequential i 2 c write transaction has taken place, and the data for all 16 sub-addresses is successfully received by the APA3169. for i 2 c sequential write transactions, the sub- address then serves as the start address, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines how many sub-addresses are written. as was true for random addressing, sequential addressing requires that a complete set of data be transmitted. if only a partial set of data is written to the last sub- address, the data for the last sub-address is discarded. however, if all other data written is accepted, only the incomplete data is discarded. single-byte write as shown in figure 17, a single-byte data write transfer begins with the master device transmitting a start condition followed by the i2c device address and the read/write bit. the read/write bit determines the direction of the data transfer. for a write data transfer, the read/write bit will be a 0. after receiving the correct i2c device address and the read/write bit, the dap responds with an acknowledge bit. next, the master transmits the address byte or bytes corresponding to the APA3169 internal memory address being accessed. after receiving the address byte, the APA3169 again responds with an acknowledge bit. next, the master device transmits the data byte to be written to the memory address being accessed. after receiving the data byte, the APA3169 again responds with an acknowledge bit. finally, the master device transmits a stop condition to complete the single-byte data write transfer. single- and multiple-byte transfers free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 7 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) a6 a5 a4 a3 a2 a1 a0 ack r/w a6 a5 a4 a3 a2 a1 a0 ack a7 d6 d5 d4 d3 d2 d1 d0 ack d7 start condition stop condition i 2 c device address and read/ write bit sub-address data byte acknowledge acknowledge acknowledge f i g u r e 1 7 . s i n g l e - b y t e w r i t e t r a n s f e r multiple-byte write a multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the dap as shown in figure 18. after receiving each data byte, the APA3169 responds with an acknowledge bit. a6 a5 a1 a0 ack r/w a6 a2 a1 a0 ack a7 d0 ack d7 start condition stop condition i 2 c device address and read/ write bit sub-address first data byte acknowledge acknowledge acknowledge d0 ack acknowledge d7 acknowledge d0 ack d7 last data byte other data bytes f i g u r e 1 8 . m u l t i p l e - b y t e w r i t e t r a n s f e r single-byte read as shown in figure 19, a single-byte data read transfer begins with the master device transmitting a start condition followed by the i 2 c device address and the r/w bit. for the data read transfer, both a write followed by a read are actually done. initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. as a result, the r/w bit becomes a 0. after receiving the APA3169 address and the read/write bit, APA3169 responds with an acknowledge bit. besides, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the APA3169 address and the read/write bit again. this time the read/ write bit becomes a 1, indicating a read transfer. after receiving the address and the read/write bit, the APA3169 again responds with an acknowledge bit. and then, the APA3169 transmits the data byte from the memory address being read. after receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer. f i g u r e 1 9 . s i n g l e - b y t e r e a d t r a n s f e r a6 a5 a1 a0 ack r/w a6 a1 a0 ack a7 start condition stop condition i 2 c device address and read/ write bit sub-address acknowledge acknowledge a6 a5 a1 a0 r/w i 2 c device address and read/ write bit ack d6 d1 d0 ack d7 data byte acknowledge not acknowledge repeat start condition free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 8 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) multiple-byte read a multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the APA3169 to the master device as shown in figure 20. except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte. f i g u r e 2 0 . m u l t i p l e - b y t e r e a d t r a n s f e r a6 a0 ack r/w a6 a1 a0 ack a7 start condition i 2 c device address and read/ write bit sub- address acknowledge acknowledge a6 a0 r/w i 2 c device address and read/ write bit ack acknowledge repeat start condition d0 ack d7 stop condition first data byte acknowledge d0 ack not acknowledge d7 acknowledge d0 ack d7 last data byte other data bytes output mode and mux selection f i g u r e 2 1 . o u t p u t m o d e a n d m u x s e l e c t i o n ch 1 _ audio ch 2 _ audio pwm 1 pwm 2 pwm 3 pwm 4 2 . 0 btl bd reg setting 0 x 05 ( 2 ) = 0 ch 1 _ audio ch 3 _ audio pwm 1 pwm 2 pwm 3 pwm 4 2 . 1 se , btl - bd reg setting 0 x 05 ( 2 ) = 1 ch 2 _ audio free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 9 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) 2.1-mode support the APA3169 supports 2.0-mode and 2.1-mode operation.to enable 2.1 mode, register 0x05 bit d2 must be set to 1. p r o f e s s i o n a l - q u a l i t y d y n a m i c r a n g e c o m p r e s s i o n a u t o m a t i c a l l y a d - j u s t s v o l u m e t o f l a t t e n v o l u m e l e v e l . ? t h e d r c h a s a d j u s t a b l e t h r e s h o l d , o f f s e t , a n d c o m p r e s s i o n l e v e l s . f i g u r e 2 2 . d y n a m i c r a n g e c o n t r o l t input level (db) o u t p u t l e v e l ( d b ) k o 1:1 transfer function implemented transfer function biquad structure all biquads use a 2nd order iir filter structure as shown below. each biquad has 3 coefficients on the direct path (b0, b1, b2) and 2 coefficients on feedback path (a1 and a2) which is shown in the diagram. s z -1 z -1 z -1 z -1 magnitude trunction x(n) y(n) b 0 b 1 b 2 a 1 a 2 single-filter pbtl-mode support the APA3169 supports parallel btl (pbtl) mode with out_a/out_b (and out_c/out_d) connected before the lc filter. in order to put the part in pbtl configuration, drive pbtl (pin 8) high. this synchronizes the turnoff of half- bridges a and b (and similarly c/d) if an overcurrent condition is detected in either half-bridge. there is a pulldown resistor on the pbtl pin that configures the part in btl mode if the pin is left floating. pwm output multiplexers should be updated to set the device in pbtl mode. output mux register (0x25) should be written with a value of 0x01 10 32 45. dynamic range control (drc) the drc scheme has a single threshold, offset, and slope (all programmable). there is one ganged drc for the left/ right channels. the drc input/output diagram is shown in figure 22. f i g u r e 2 4 . b i q u a d f i l t e r free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 0 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) 26bit 3.23 number format all mixer gain coefficients are 26 bit coefficients and use a 3.23 number format. numbers formatted as 3.23 numbers means that there are 3 bits to the left of the decimal point and 23 bits to the right of the decimal point. this is shown in figure 18. f i g u r e 2 5 . 3 . 2 3 f o r m a t the decimal value of a 3.23 format number can be found by following the weighting and is shown in figure 25. if the msb is logic 0, the number is a positive number, and the weighting shown yields the correct number. if the msb is a logic 1, and then the number is a negative number. in this case, every bit must be inverted, a 1 added to the result, and then the weighting shown in figure 26 applied to obtain the magnitude of the negative number. f i g u r e 2 6 . c o n v e r s i o n w e i g h t i n g f a c r o e s 3 . 2 3 f o r m a t t o f l o a t i n g p o i n t gain coefficients, entered via the i 2 c bus, must be entered as 32 bit binary numbers. the format of the 32 bit number (4 byte or 8 digit hexadecimal number) is shown in figure 27. f i g u r e 2 7 . a l i g n m e n t o f 3 . 2 3 c o e f f i c i e n t i n 3 2 b i t i 2 c w o r d 2 -23 bit 2 0 bit 2 1 bit 2 -1 bit 2 -4 bit (1 or 0) x2 1 + (1 or 0) x2 0 + (1 or 0) x2 -1 + (1 or 0) x2 -4 + (1 or 0) x2 -23 s_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx 2 -23 bit 2 -5 bit 2 -1 bit 2 0 bit 2 1 bit sign bit u u u u u u s x x x x x x x x x x x x x x x x x x x x x x x x 0 fraction digit 6 fraction digit 5 fraction digit 4 fraction digit 2 fraction digit 3 fraction digit 1 integer digit 1 sign bit coefficient digit 8 coefficient digit 7 coefficient digit 6 coefficient digit 5 coefficient digit 4 coefficient digit 3 coefficient digit 2 coefficient digit 1 x free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 1 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) sample calculation for 3.23 format d b linear decimal hex (3.23 format) 0 1 8388608 00800000 5 1.7782794 14917288 00e39ea8 - 5 0.5623413 4717260 0047facc x l = 10 (x/20) d = 8388608 l h = dec2hex (d, 8) sample calculation for 9.17 format db linear decimal hex ( 9 . 17 format) 0 1 131072 00 02 0000 5 1.7782794 233082.6 00 0 3 8 e 7 a - 5 0.5623413 73707.2 00 011feb x l = 10 (x/20) d = 131072 l h = dec2hex (d, 8) recommended use model f i g u r e 2 8 . r e c o m m e n d e d c o m m a n d s e q u e n c e avdd/dvdd sd mclk lrclk sclk sdin i 2 s scl sda i 2 c rst pvdd/avcc trim dap config other config exit sd volume and mute commands clock errors and rate changes ok enter sd stable and valid clocks stable and valid clocks 3v t entersd t autodetect t por t por t exitsd t vdd-pvccl 10v 7.5v 10v 7.5v t rl-pvcch t pvccl-vddh t vddh-dl 3v reconfigure dap after shutdown reconfigure dap after shutdown normal operation shutdown power down t dl-vddh t rl-dv intialization t rh-i2c t dv-rh t pvcch-i2c t autodetect free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 2 a p a 3 1 6 9 recommended use model (cont.) f u n c t i o n d e s c r i p t i o n ( c o n t . ) f i g u r e 2 9 . p o w e r l o s s s e q u e n c e 3 v avdd / dvdd / pdn scl sda i 2 c / reset pvdd recommended command sequences the dap has two groups of commands. one set is for configuration and is intended for use only during initialization. the other set has built-in click and pop protection and may be used during normal operation while audio is streaming. the following supported command sequences illustrate how to initialize, operate, and shutdown the device. initialization sequence u s e t h e f o l l o w i n g s e q u e n c e t o p o w e r - u p a n d i n i t i a l i z e t h e d e v i c e : 1 . h o l d a l l d i g i t a l i n p u t s l o w a n d r a m p u p a v d d / d v d d t o a t l e a s t 3 v . 2 . i n i t i a l i z e d i g i t a l i n p u t s a n d p v d d s u p p l y a s f o l l o w s : ? d r i v e r e s e t = 0 , p d n = 1 , a n d o t h e r d i g i t a l i n p u t s t o t h e i r d e s i r e d s t a t e w h i l e e n s u r i n g t h a t a l l a r e n e v e r m o r e t h a n 2 . 5 v a b o v e a v d d / d v d d . d r i v e r e s e t = 1 . ? r a m p u p p v d d t o a t l e a s t 8 v . 3 . c o n f i g u r e t h e d a p v i a i 2 c . 4 . c o n f i g u r e r e m a i n i n g r e g i s t e r s . 5 . e x i t s h u t d o w n . normal operation the following are the only events supported during normal operation: (a) writes to master/channel volume registers (b) writes to soft mute register (c) enter and exit shutdown free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 3 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) shutdown sequence e n t e r : 1 . w r i t e 0 x 4 0 t o r e g i s t e r 0 x 0 5 . 2 . i f d e s i r e d , r e c o n f i g u r e b y r e t u r n i n g t o s t e p 4 o f i n i t i a l i z a t i o n s e q u e n c e . e x i t : 1 . w r i t e 0 x 0 0 t o r e g i s t e r 0 x 0 5 . 2 . p r o c e e d w i t h n o r m a l o p e r a t i o n . power-down sequence use the following sequence to power-down the device and its supplies: 1. if time permits, enter shutdown ; else, in case of sudden power loss, assert pdn=0. 2. assert reset=0. 3. drive digital inputs low and ramp down pvdd supply as follows: ? drive all digital inputs low after reset has been low. ? ramp down pvdd while ensuring that it remains above 8v until reset has been low. 4. ramp down avdd/dvdd while ensuring that it remains above 3v until pvdd is below 6v and that it is never more than 2.5v below the digital inputs. sub a ddress register name no. of bytes contents initialization values a u indicates unused bits. 0x00 clock control register 1 description shown in subsequent section 0x6c 0x01 device id register 1 description shown in subsequent section 0x 69 0x02 error status register 1 description shown in subsequent section 0x00 0x03 system control register 1 1 description shown in subsequent section 0x 80 0x04 serial data interface 1 description shown in subsequent section 0x05 0x05 1 description shown in sub sequent section 0x 4c 0x06 soft mute register 1 description shown in subsequent section 0x00 0x07 master volume 1 description shown in subsequent section 0xff (mute) 0x08 channel 1 vol 1 description shown in subsequent section 0x30 (0db) 0x09 channel 2 vol 1 description shown in subsequent section 0x30 (0db) 0x0a channel 3 vol 1 description shown in subsequent section 0x30 (0db) 0x0b - 0x0d reserved ( 1 ) 0x0e volume configuration register 1 description shown in subsequent section 0x91 0x0f 1 res erved(1) 0x10 modulation limit register 1 description shown in subsequent section 0x02 0x11 - 0x19 1 reserved(1) 0x1a start/stop period register 1 description shown in subsequent section 0x0f 0x1b - 0x1f 1 reserved(1) 0x20 input mux register 4 d escription shown in subsequent section 0x0089 7772 0x21 ch4 source select register 4 description shown in subsequent section 0x0000 4303 0x22 - 0x24 1 reserved(1) table 1. serial control interface register summary free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 4 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) sub a ddress register name no. of bytes contents initialization values 0x25 pwm output mux register 4 description shown in subsequent section 0x0102 1345 0x26 - 0x28 4 reserved(1) u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x29 ch1_bq[0] 20 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26 ], a1[25:0] 0x0000 0000 0x2a ch1_bq[1] 20 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x2b ch1_bq[2] 20 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x2c ch1_bq[3] 20 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:2 6], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x2d ch1_bq[4] 20 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x2e ch1_bq[5] 20 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x2f ch1_bq[6] 20 u[31:26], a2[25:0] 0 x0000 0000 table 1. serial control interface register summary (cont.) free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 5 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) sub a ddress register name no. of bytes contents initialization values u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x30 ch2_bq[0] 20 u[31:26], a2[25:0] 0x0 000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x31 ch2_bq[1] 20 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x32 ch2_bq[2] 20 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0 x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x33 ch2_bq[3] 20 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x34 ch2_bq[4] 20 u[31:26], a 2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x35 ch2_bq[5] 20 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x36 ch2_bq[6] 20 u[31:26], a2[25:0] 0x0000 0000 table 1. serial control interface register summary (cont.) free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 6 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) sub a ddress register name no. of bytes contents initialization values 0x37~ 0x3f reserved(1) 0x40 drc1 - t 4 t[31:0] (9.23 format) 0x007f ffff 0x41 drc1 - k 4 u[31:26], k[25:0] 0x0080 0000 0x42 drc1 - o 4 u[31:26], o[25:0] 0x0080 0000 0x43 drc2 - t 4 t[3 1:0] (9.23 format) 0x007f ffff 0x44 drc2 - k 4 u[31:26], k[25:0] 0x0080 0000 0x45 drc2 - o 4 u[31:26], o[25:0] 0x0080 0000 0x46 drc control 4 description shown in subsequent section 0x0000 0000 0x47 ? 0x4f reserved(1) 0x50 eq control 4 description show n in subsequent section 0x0000 0000 ch1_output_mixer2 0x0 707 0707 ch1_output_mixer1 0x0 707 0707 0x51 ch1 output mixer 12 ch1_output_mixer0 0x0 707 0707 ch2_output_mixer2 0x0 707 0707 ch2_output_mixer1 0x0 707 0707 0x52 ch2 output mixer 12 ch 2_output_mixer0 0x0 707 0707 ch1_input_mixer3 0x0 808 0808 ch1_input_mixer2 0x0 808 0808 ch1_input_mixer1 0x0 808 0808 0x53 ch1 input mixer 16 ch1_input_mixer0 0x0 808 0808 ch2_input_mixer3 0x0 808 0808 ch2_input_mixer2 0x0 808 0808 ch2_input_mixer1 0x0 808 0808 0x54 ch2 input mixer 16 ch2_input_mixer0 0x0 808 0808 ch3_input_mixer2 0x0 707 0707 ch3_input_mixer1 0x0 707 0707 0x55 ch3 input mixer 12 ch3_input_mixer0 0x0 707 0707 0x56 output post scale 4 9.17 format 0x0002 0000 0x57 in put pre scale 4 description shown in subsequent section 0x0080 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x58 ch1_bq[7] 20 u[31:26], a2[25:0] 0x0000 0000 table 1. serial control interface register summary (cont.) free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 7 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) sub a ddress register name no. of bytes contents initialization values u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x59 ch1_bq[8] 20 u[31:26], a2[25:0] 0x00 00 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x5a subchannel bq[0] 20 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0 x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x5b subchannel bq[1] 20 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b 2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x5c ch2_bq[7] 20 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x5d ch2_bq[8] 20 u[ 31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x5e pseudo_ch2_bq[0] 20 u[31:26], a2[25:0] 0x0000 0000 table 1. serial control interface register summary (cont.) free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 8 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) sub a ddress register name no. of bytes contents initialization values u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 0x5f pseudo_ch2_bq[1] 20 u[31:26], a2[25:0 ] 0x0000 0000 ch4_output_mixer1 0x0000 0000 0x60 ch4 output mixer 8 ch4_output_mixer0 0x0080 0000 ch4_input_mixer1 0x0040 0000 0x61 ch4 input mixer 8 ch4_input_mixer0 0x0040 0000 0x62 - 0xf0 reserved(1) table 1. serial control interface register summary (cont.) n o t e ( 1 ) : r e s e r v e d r e g i s t e r s h o u l d n o t b e a c c e s s e d a l l d a p c o e f f i c i e n t s a r e 3 . 2 3 f o r m a t u n l e s s s p e c i f i e d o t h e r w i s e . clock control register (0x00) the clocks and data rates are automatically determined by the APA3169. the clock control register contains the auto- detected clock status. bits d7-d5 reflect the sample rate. bits d4-d2 reflect the mclk frequency. d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 - - - - - f s =32khz sample rate 0 0 1 - - - - - f s = 88.2/96 khz sample rate 0 1 0 - - - - - f s = 176.4/192 khz sample rate 0 1 1 - - - - - f s =44.1/48khz sample rate ( 2 ) 1 0 0 - - - - - reserved (1) 1 0 1 - - - - - rese rved (1) 1 1 0 - - - - - reserved (1) 1 1 1 - - - - - reserved (1) - - - 0 0 0 - - mclk frequency=64 xf s ( 3 ) - - - 0 0 1 - - mclk frequency= 128xf s ( 3 ) - - - 0 1 0 - - mclk frequency= 192xf s ( 4 ) - - - 0 1 1 - - mclk frequency= 256xf s ( 2 ) - - - 1 0 0 - - mc lk frequency= 384xf s - - - 1 0 1 - - mclk frequency= 512xf s - - - 1 1 0 - - reserved ( 1 ) - - - 1 1 1 - - reserved ( 1 ) - - - - - - 0 - reserved (1) - - - - - - - 0 reserved (1) t a b l e 2 . c l o c k c o n t r o l r e g i s t e r ( 0 x 0 0 ) n o t e ( 1 ) : r e s e r v e d r e g i s t e r s s h o u l d n o t b e a c c e s s e d . n o t e ( 2 ) : d e f a u l t v a l u e s a r e i n b o l d n o t e ( 3 ) : o n l y a v a i l a b l e f o r 4 4 . 1 k h z a n d 4 8 k h z r a t e s . n o t e ( 4 ) : r a t e o n l y a v a i l a b l e f o r 3 2 / 4 4 . 1 / 4 8 k h z s a m p l e r a t e s . free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 9 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) device id register (0x01) the anpec id register contains the id code for the firmware revision. d7 d6 d5 d4 d3 d2 d1 d0 function 0 1 1 0 1 0 0 1 identification code t a b l e 3 . g e n e r a l s t a t u s r e g i s t e r ( 0 x 0 1 ) error status register (0x02) t h e e r r o r b i t s a r e s t i c k y a n d a r e n o t c l e a r e d b y t h e h a r d w a r e . t h i s m e a n s t h a t t h e s o f t w a r e m u s t c l e a r t h e r e g i s t e r ( w r i t e z e r o e s ) a n d t h e n r e a d t h e m t o d e t e r m i n e i f t h e y a r e p e r s i s t e n t e r r o r s . e r r o r d e f i n i t i o n s : m c l k e r r o r : m c l k f r e q u e n c y i s c h a n g i n g . t h e n u m b e r o f m c l k s p e r l r c l k i s c h a n g i n g . s c l k e r r o r : t h e n u m b e r o f s c l k s p e r l r c l k i s c h a n g i n g . l r c l k e r r o r : l r c l k f r e q u e n c y i s c h a n g i n g . t a b l e 4 . e r r o r s t a t u s r e g i s t e r ( 0 x 0 2 ) d7 d6 d5 d4 d3 d2 d1 d0 function 1 - - - - - - - mclk error - 1 - - - - - - pll auto clock error - - 1 - - - - - sclk error - - - 1 - - - - lrclk error - - - - 0 - - - reserved - - - - - 0 - - reserved - - - - - - 1 - over current, over temperature, over voltage or under voltage errors - - - - - - - 1 over temperature warning (sets around 1 50 o c ) 0 0 0 0 0 0 0 0 no errors n o t e : d e f a u l t v a l u e s a r e i n b o l d . system control register 1 (0x03) the system control register 1 has several functions: bit d7: if 0, the dc-blocking filter for each channel is disabled. if 1, the dc-blocking filter ( -3db cutoff < 1hz ) for each channel is enabled (default). bit d5: if 0, use soft unmute on recovery from clock error. this is a slow recovery. unmute takes same time as volume ramp defined in reg 0x0e. if 1, use hard unmute on recovery from clock error (default). this is a fast recovery, a single step volume ramp bits d1-d0: select de-emphasis. t a b l e 5 . s y s t e m c o n t r o l r e g i s t e r 1 ( 0 x 0 3 ) d7 d6 d5 d4 d3 d2 d1 d0 function 0 - - - - - - - pwm high - pass (dc blocking) dis enabled 1 - - - - - - - pwm high - pass (dc blocking) enabled - 0 0 0 0 0 - - reserved - - - - - - 0 0 no de - emphasis - - - - - - 0 1 de - emphasis for f s = 32 khz free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 0 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) d7 d6 d5 d4 d3 d2 d1 d0 function - - - - - - 1 0 de - emphasis for f s =44.1khz - - - - - - 1 1 de - emphasis for f s =4 8 khz n o t e : d e f a u l t v a l u e s a r e i n b o l d . serial data interface register (0x04) a s s h o w n i n t a b l e 6 , t h e a p a 3 1 6 9 s u p p o r t s 9 s e r i a l d a t a m o d e s . t h e d e f a u l t i s 2 4 b i t , i 2 s m o d e . table 6. serial data interface control register (0x04) format d7 d6 d5 d4 d3 d2 d1 d0 word length receive serial data interface format 0 0 0 0 - - - - reserved - - - - 0 0 0 0 16 right - justified - - - - 0 0 0 1 20 right - justified - - - - 0 0 1 0 24 right - justified - - - - 0 0 1 1 16 i 2 s - - - - 0 1 0 0 20 i 2 s - - - - 0 1 0 0 24 i 2 s - - - - 0 1 1 0 16 left - justified - - - - 0 1 1 20 left - justified 1 0 0 0 24 left - justified - - - - 1 0 0 1 reserved - - - - 1 0 1 0 reserved - - - - 1 0 1 1 reserved - - - - 1 1 0 0 reserved - - - - 1 1 0 1 reserv ed - - - - 1 1 1 0 reserved - - - - 1 1 1 1 reserved system control register 2 (0x05) when bit d6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs are shut down (hard mute). t a b l e 7 . s y s t e m c o n t r o l r e g i s t e r 2 ( 0 x 0 5 ) d7 d6 d5 d4 d3 d2 d1 d0 function 0 - - - - - - - reserved - 1 - - - - - - enter all channel shut down (hard mute) - 0 - - - - - - exit all channel shut down (normal operation) - - 0 0 1 - - - reserved - - - - - 0 - - 2.0 mode (2 btl) - - - - - 1 - - 2.1 mode (2 se + 1 btl) n o t e : d e f a u l t v a l u e s a r e i n b o l d . free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 1 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) soft mute register (0x06) writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute). d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 0 0 - - - reserved - - - - - 1 - - soft mute channel 3 - - - - - 0 - - soft un - mute channel 3 - - - - - - 1 - soft mute channel 2 - - - - - - 0 - soft un - mute channel 2 - - - - - - - 1 soft mute channel 1 - - - - - - - 0 soft un - mute channel 1 t a b l e 8 . s o f t m u t e r e g i s t e r ( 0 x 0 6 ) d7 d6 d5 d4 d3 d2 d1 d0 function - - - - - - 0 - a_sel configured as input - - - - - - 1 - a_sel configured as fault output - - - - - - - 0 reserved n o t e : d e f a u l t v a l u e s a r e i n b o l d . n o t e : d e f a u l t v a l u e s a r e i n b o l d . volume registers (0x07, 0x08, 0x09) s t e p s i z e i s 0 . 5 d b . m a s t e r v o l u m e - 0 x 0 7 ( d e f a u l t i s m u t e ) c h a n n e l - 1 v o l u m e - 0 x 0 8 ( d e f a u l t i s 0 d b ) c h a n n e l - 2 v o l u m e - 0 x 0 9 ( d e f a u l t i s 0 d b ) c h a n n e l - 3 v o l u m e - 0 x 0 a ( d e f a u l t i s 0 d b ) t a b l e 9 . v o l u m e r e g i s t e r s ( 0 x 0 7 , 0 x 0 8 , 0 x 0 9 ) d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 0 0 0 0 0 24db 0 0 1 1 0 0 0 0 0db 1 1 1 1 1 1 1 0 - 103db 1 1 1 1 1 1 1 1 mute (default for master volume) n o t e : d e f a u l t v a l u e s a r e i n b o l d . bits volume slew rate (used to control volume change and mute ramp rates). these bits control the d2-d0: number of steps in a volume ramp. volume steps occur at a rate that depends on the sample rate of the i 2 s data as follows. volume configuration register (0x0e) sample rate (khz) approximate ramp rate 8/16/32 125 m s/step 11.025/22.05/44.1 90.7 m s/step 12/24/48 83.3 m s/step free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 2 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) d7 d6 d5 d4 d3 d2 d1 d0 function 1 - - 1 0 - - - reserved 0 subchannel (ch4) volume = ch1 volume (default) 1 subchannel volume = register 0x.a 0 ch3 volume = ch2_volume (default) 1 ch3 volume = register 0x.a - - - - - 0 0 0 volume slew 512 steps (43ms volume ramp time at 48khz) - - - - - 0 0 1 volume slew 1024 steps (43ms volume ramp time at 48khz) - - - - - 0 1 0 volume slew 2048 steps (43ms volume ramp time at 48khz) - - - - - 0 1 1 volume slew 256 steps (43ms volume r amp time at 48khz) - - - - - 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 volume slew 0 step (disable) t a b l e 1 0 . v o l u m e c o n t r o l r e g i s t e r ( 0 x 0 e ) n o t e : d e f a u l t v a l u e s a r e i n b o l d . modulation limit register (0x10) t a b l e 1 1 . m o d u l a t i o n l i m i t r e g i s t e r ( 0 x 1 0 ) d7 d6 d5 d4 d3 d2 d1 d0 modulation limit 0 0 0 0 0 ? ? ? reserved - - - - - 0 0 0 reserved - - - - - 0 0 1 98.4% - - - - - 0 1 0 97.7% - - - - - 1 0 0 96.9% - - - - - 0 1 1 96.1% - - - - - 1 0 1 95.3% - - - - - 1 1 0 94.5% - - - - - 1 1 1 93.8% the modulation limit is the maximum duty cycle of the pwm output waveform. n o t e : d e f a u l t v a l u e s a r e i n b o l d . start/stop period register (0x1a) this register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down command or change in the pdn state. this helps reduce pops and clicks at start-up and shutdown. the times are only approximate and vary depending on device activity level and i 2 s clock stability. t a b l e 1 2 . s t a r t / s t o p p e r i o d r e g i s t e r ( 0 x 1 a ) d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 - - - - - reserved - - - 0 0 - - - no 50% duty cycle start/stop period - - - 0 1 0 0 0 16.5ms 50% duty cycle start/stop period free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 3 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) d7 d6 d5 d4 d3 d2 d1 d0 function - - - 0 1 0 0 1 23.9 ms 50% duty cycle start/stop period - - - 0 1 0 1 0 31.4 ms 50% duty cycle start/stop period - - - 0 1 0 1 1 40.4 ms 50% duty cycle start/stop period - - - 0 1 1 0 0 53.9 ms 50% duty cycle start/stop pe riod - - - 0 1 1 0 1 70.3 ms 50% duty cycle start/stop period - - - 0 1 1 1 0 94.2 ms 50% duty cycle start/stop period - - - 0 1 1 1 1 125.7 ms 50% duty cycle start/stop period - - - 1 0 0 0 0 164.6 ms 50% duty cycle start/stop period - - - 1 0 0 0 1 239. 4 ms 50% duty cycle start/stop period - - - 1 0 0 1 0 314.2 ms 50% duty cycle start/stop period - - - 1 0 0 1 1 403.9 ms 50% duty cycle start/stop period - - - 1 0 1 0 0 538.6 ms 50% duty cycle start/stop period - - - 1 0 1 0 1 703.4 ms 50% duty cycle start /stop period - - - 1 0 1 1 0 942.5 ms 50% duty cycle start/stop period - - - 1 0 1 1 1 1256.6 ms 50% duty cycle start/stop period - - - 1 1 0 0 0 1728.1 ms 50% duty cycle start/stop period - - - 1 1 0 0 1 2513.6 ms 50% duty cycle start/stop period - - - 1 1 0 1 0 3299.1 ms 50% duty cycle start/stop period - - - 1 1 0 1 1 4241.7 ms 50% duty cycle start/stop period - - - 1 1 1 0 0 5655.6 ms 50% duty cycle start/stop period - - - 1 1 1 0 1 7383.7 ms 50% duty cycle start/stop period - - - 1 1 1 1 0 9897.3 ms 50 % duty cycle start/stop period - - - 1 1 1 1 0 13196.4 ms 50% duty cycle start/stop period n o t e : d e f a u l t v a l u e s a r e i n b o l d . input multiplexer register (0x20) this register controls the routing of i 2 s audio to the internal channels. t a b l e 1 3 . i n p u t m u l t i p l e x e r r e g i s t e r ( 0 x 2 0 ) d 31 d 30 d 29 d 28 d 27 d 26 d 25 d 24 function 0 0 0 0 0 0 0 0 reserved d 23 d 22 d 21 d 20 d 19 d 18 d 17 d 16 function 1 - - - - - - - reserved - 0 0 0 - - - - sdin - l to channel 1 - 0 0 1 - - - - sdin - r to channel 1 - 0 1 0 - - - - reserved - 0 1 1 - - - - r eserved - 1 0 0 - - - - reserved - 1 0 1 - - - - reserved - 1 1 0 - - - - ground (0) to channel 1 free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 4 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) d 23 d 22 d 21 d 20 d 19 d 18 d 17 d 16 function - 1 1 1 - - - - reserved - - - - 1 - - - reserved - - - - - 0 0 0 sdin - l to channel 2 - - - - - 0 0 1 sdin - r to channel 2 - - - - - 0 1 0 reserved - - - - - 0 1 1 reserved - - - - - 1 0 0 reserved - - - - - 1 0 1 reserved - - - - - 1 1 0 ground (0) to channel 2 - - - - - 1 1 1 reserved d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 function 0 1 1 1 0 1 1 1 reserved d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 function 0 1 1 1 0 0 1 0 reserved n o t e : d e f a u l t v a l u e s a r e i n b o l d . channel 4 source select register (0x21) this register selects the channel 4 source. t a b l e 1 4 . s u b c h a n n e l c o n t r o l r e g i s t e r ( 0 x 2 1 ) d 31 d 30 d 29 d 28 d 27 d 26 d 25 d 24 function 0 0 0 0 0 0 0 0 reserved d 23 d 22 d 21 d 20 d 19 d 18 d 17 d 16 function 0 0 0 0 0 0 0 0 reserved d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 function 0 1 0 0 0 0 1 1 reserved d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 function 0 0 0 0 0 0 1 1 reserved n o t e : d e f a u l t v a l u e s a r e i n b o l d . pwm output mux register (0x25) this dap output mux selects which internal pwm channel is output to the external pins. any channel can be output to any external output pin. bits d21-d20: selects which pwm channel is output to out_a bits d17-d16: selects which pwm channel is output to out_b bits d13-d12: selects which pwm channel is output to out_c bits d09-d08: selects which pwm channel is output to out_d note that channels are enclosed so that channel 1=0x00, channel 2=0x01, channel 1=0x02, and channel 2=0x03. free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 5 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) t a b l e 1 5 . p w m o u t p u t m u x r e g i s t e r ( 0 x 2 5 ) d 31 d 30 d 29 d 28 d 27 d 26 d 25 d 24 function 0 0 0 0 0 0 0 0 reserved d 23 d 22 d 21 d 20 d 19 d 18 d 17 d 16 function 0 0 - - - - - - reserved - - 0 0 - - - - multiplex channel 1 to out_a - - 0 1 - - - - multiplex channel 2 to out_a - - 1 0 - - - - multiplex channel 1 to out_a - - 1 1 - - - - multiplex channel 2 to out_a - - - - 0 0 - - reserved - - - - - - 0 0 multiplex channel 1 to out_b - - - - - - 0 1 multiplex channel 2 to out_b - - - - - - 1 0 multiplex channel 1 to out_b - - - - - - 1 1 multiplex channel 2 to out_b d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 function 0 0 - - - - - - reserved - - 0 0 - - - - multiplex channel 1 to out_c - - 0 1 - - - - multiplex channel 2 to out_c - - 1 0 - - - - multiplex channel 1 to out_c - - 1 1 - - - - multiplex chan nel 2 to out_c - - - - 0 0 - - reserved - - - - - - 0 0 multiplex channel 1 to out_d - - - - - - 0 1 multiplex channel 2 to out_d - - - - - - 1 0 multiplex channel 1 to out_d - - - - - - 1 1 multiplex channel 2 to out_d d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 func tion 0 1 0 0 0 1 0 1 reserved n o t e : d e f a u l t v a l u e s a r e i n b o l d . d r c c o n t r o l ( 0 x 4 6 ) d 31 d 30 d 29 d 28 d 27 d 26 d 25 d 24 function 0 0 0 0 0 0 0 0 reserved d 23 d 22 d 21 d 20 d 19 d 18 d 17 d 16 function 0 0 0 0 0 0 0 0 reserved d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 function 0 0 0 0 0 0 0 0 reserved each drc can be enabled independently using the drc control register. the drcs are disabled by default. t a b l e 1 6 . d r c c o n t r o l r e g i s t e r free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 6 a p a 3 1 6 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 function 0 0 0 0 0 0 - - reserved - - - - - - 0 - drc2 turned off - - - - - - 1 - drc2 turned on - - - - - - - 0 drc1 turned off - - - - - - - 1 drc1 turned on n o t e : d e f a u l t v a l u e s a r e i n b o l d . e q c o n t r o l ( 0 x 5 0 ) d 31 d 30 d 29 d 28 d 27 d 26 d 25 d 24 function 0 0 0 0 0 0 0 0 reserved d 23 d 22 d 21 d 20 d 19 d 18 d 17 d 16 function 0 0 0 0 0 0 0 0 reserved d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 function 0 0 0 0 0 0 0 0 reserved d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 function 0 - - - - - - - eq on 1 - - - - - - - eq off - 0 0 0 0 0 0 0 reserved t a b l e 1 . e q c o n t r o l r e g i s t e r n o t e : d e f a u l t v a l u e s a r e i n b o l d . free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 7 a p a 3 1 6 9 a p p l i c a t i o n i n f o r m a t i o n l a n d p a t t e r n r e c o m m e n d a t i o n 0 . 28 mm via diameter = 0 . 3 mm x 16 ground plane for thermalpad 1 . 7 mm 5 . 5 mm exposed for thermal pad connected 5 . 0 m m 0 . 5 mm tqfp 7 x 7 - 48 land pattern recommendation free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 8 a p a 3 1 6 9 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) l a y o u t r e c o m m e n d a t i o n 1 3 1 3 7 2 5 / reset avdd scl lrck sclk sdin 4700 p f apa 3169 sda 0 o 10 f 2200 pf 4700 pf jp 1 p b t l a v s s p l l _ f l t m p l l _ f l t p v r _ a n a p v d d _ a b s _ a v c l a b t m 1 t m 2 o u t _ a p v d d _ a a v d d a _ s e l m c l k t p 1 t p 2 s c l v r _ d i g / p d n _ n l r c l k s c l k s d i n s d a 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 d g n d d v s s d v d d t p 3 / r e s e t _ n p v d d _ d b s _ d v c l c d v r e g a g n d o u t _ d p v d d _ d p g n d _ a b p g n d _ a b o u t _ b p v d d _ b p v d d _ b p g n d _ c d b s _ b b s _ c p v d d _ c p v d d _ c o u t _ c p g n d _ c d 0 . 1 f 10 k o mclk a _ sel 18 . 2 k o 0 . 1 f 4 . 7 f 10 k o av dd / pdn dvdd 0 . 1 f 10 f 0 . 1 f 1 f 0 . 033 f pvdd 0 . 1 f 220 f 22 h 0 . 68 f 0 . 68 f 22 h 0 . 033 f 0 . 033 f 0 . 1 f 0 . 1 f pvdd 22 h 22 h 0 . 68 f 0 . 68 f pvdd 220 f 0 . 1 f 0 . 033 f 1 f 2 2 . 1 k o 10 k o 470 o 470 o 0 . 047 f 0 . 047 f avdd avdd cap . & dvdd cap . should be close to the chip . thermal pad should be soldered on ground plane of the pcb . pvdd cap . and bootstrap cap . should be close to the chip . power stage block , please use high voltage - bearing component . output & vdd traces width = 4 0 mil , should be as short as they can , and symmetric . free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 9 a p a 3 1 6 9 p a c k a g e i n f o r m a t i o n t q f p 7 x 7 - 4 8 p 0 l 0 . 2 5 seating plane gauge plane l 0 . 006 0 o 7 o 0 o 7 o 0 . 50 bsc 0 . 020 bsc 0 . 45 0 . 75 0 . 018 0 . 030 s y m b o l min . max . 1 . 20 0 . 05 0 . 17 0 . 27 0 . 09 0 . 20 0 . 15 a a 1 b c d d 1 e e 1 e millimeters a 2 0 . 95 1 . 05 tqfp 7 x 7 - 48 p min . max . inches 0 . 047 0 . 002 0 . 037 0 . 041 0 . 007 0 . 011 0 . 004 0 . 008 d 2 e 2 3 . 00 0 . 118 3 . 00 5 . 50 5 . 50 0 . 177 0 . 118 0 . 177 8 . 80 9 . 20 0 . 346 0 . 362 6 . 90 7 . 10 0 . 272 0 . 280 8 . 80 6 . 90 7 . 10 9 . 20 0 . 346 0 . 272 0 . 362 0 . 280 note : 1 . followed from jedec ms - 026 abc . 2 . dimension " d 1 " and " e 1 " do not include mold protrusions . allowable protrusions is 0 . 25 mm per side . " d 1 " and " e 1 " are maximun plasticbody size dimensions including mold mismatch . d 1 d e 1 e e b d 2 e 2 exposed pad a 2 a 1 a c free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 5 0 a p a 3 1 6 9 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 16.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 16.0 ? 0.30 1.75 ? 0.10 7.5 ? 0.10 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tqfp7x7 - 48p 4.0 ? 0.10 12.0 ? 0.10 2.0 ? 0.10 1.5+0.10 - 0.00 1.5 min. 0.6+0.0 0 - 0.40 9.4 ? 0.20 9.4 ? 0.20 1.8 ? 0.20 (mm) c a r r i e r t a p e & r e e l d i m e n s i o n s d e v i c e s p e r u n i t package type unit quantity tqfp7x7 - 48p tape & reel 2500 h t1 a d a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 5 1 a p a 3 1 6 9 t a p i n g d i r e c t i o n i n f o r m a t i o n tqfp7x7-48p c l a s s i f i c a t i o n p r o f i l e user direction of feed free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 5 2 a p a 3 1 6 9 profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. c l a s s i f i c a t i o n r e f l o w p r o f i l e s table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c r e l i a b i l i t y t e s t p r o g r a m test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ t j =125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 5 3 a p a 3 1 6 9 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8 free datasheet http:///

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