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1 pf885-05 s1d13503 series dot matrix graphics lcd controller description this device is designed for products where low cost, low power consumption, and low component count are the major design considerations. this chip operates from 2.7 volts to 5.5 volts and up to 25 mhz to suit different power consumption, speed and cost requirements. the s1d13503 offers a flexible microprocessor interface and is pin compatible with the sed1352. the s1d13503 is capable of displaying a maximum of 16 levels of gray shade or 256 simultaneous colors. in gray shade modes, a 16 x 4 look-up table is provided to allow remapping of the 16 possible gray shades displayed on the lcd panel. in color modes, three 16 x 4 look-up tables are provided to allow remapping of the 4096 possible colors displayed on the lcd panel. the s1d13503 can interface to an mc68000 family microprocessor or an 8/16-bit mpu/bus with minimum external "glue" logic. this device can directly control up to 128k bytes of static ram with a 16-bit data path, or up to 64k bytes with an 8-bit data path. features technology low power cmos 2.7 to 5.5 volt operation s1d13503f00a is 100 pin qfp5-s2 surface mount package S1D13503F01A is 100 pin qfp15-std surface mount package s1d13503d00a is die form system maximum 25 mhz input clock (or pixel clock) 2-terminal crystal input for internal oscillator or direct connection to external clock source maximum 16 mhz, 16-bit mc68000 mpu interface 8-bit or 16-bit mpu/bus interface with memory accesses controlled by a ready (or wait#) signal option to use built-in index register or direct- mapping to access one of sixteen internal registers 8-bit or 16-bit sram data bus interface configurations display memory configurations: - 128k bytes using one 64k x 16 sram - 128k bytes using two 64k x 8 srams - 64k bytes using two 32k x 8 srams - 40k bytes using one 8k x 8 and one 32k x 8 sram - 32k bytes using one 32k x 8 sram - 16k bytes using two 8k x 8 srams - 8k bytes using one 8k x 8 sram display modes 1 bit-per-pixel, black-and-white display mode 2/4 bits-per-pixel, 4/16 level gray shade display modes 2/4/8 bits-per-pixel, 4/16/256 level color display modes one 16 x 4 look-up table provided for gray shade display modes three 16 x 4 look-up tables provided for color display modes maximum 16 shades of gray maximum 256 simultaneous colors from a possible 4096 colors split screen display mode (see aux[0a]) virtual display mode (see aux[0d]) note: 256 color display mode support requires a 16-bit display memory interface. display support example resolutions: - 1024 x 768 black-and-white - 640 x 480 with 4 colors/grays - 640 x 400 with 16 colors/grays - 320 x 240 with 256 colors passive monochrome lcd panels: - 4-bit single (4-bit data transfer) - 8-bit single (8-bit data transfer) - 8-bit dual (4-bit data transfer for each half panel) passive color lcd panels: - 4-bit single (4-bit data transfer) - 8-bit single (8-bit data transfer) - 8-bit dual (4-bit data transfer for each half panel) - 16-bit single (8-bit data transfer with external circuit) - 16-bit dual (8-bit data transfer with external circuit) power management two software power-save modes low power consumption panel power control switch (see aux[01] bit 4)
2 s1d13503 series typical system block diagrams the following figures show typical system implementations of the s1d13503. all of the following block diagrams are shown without sram or lcd display. refer to the interface specific application notes for complete details. 16-bit mc68000 mpu 16-bit 68000 series (example implementation only - actual may vary) decoder decoder a20 to a23 fc0 to fc1 a1 to a19 d0 to d15 dtack# uds# lds# as# r/w# memcs# iocs# ab1 to ab19 db0 to db15 ready ab0 bhe# ior# iow# a14 to a16 a10 to a19 mc68000 s1d13503
3 s1d13503 series mpu with ready (or wait#) signal decoder decoder mreq# mi# iorq# a0 to a15 d0 to d7 wait# wr# rd# reset# memcs# iocs# ab0 to ab15 db0 to db7 ready memw# memr# ior# iow# reset a10 to a15 z80 s1d13503 s2# s1# s0# a16 to a19 bhe# ad0 to ad15 memr# memw# ior# iow# ab16 to ab19 ab0 to ab15 bhe# memcs# iocs# db0 to db15 reset ready 8086 (maximum mode) 8288 s1d13503 clk s2# s1# s0# den dt/r ale clk ready reset# mrdc# amwc# iorc# aiowc# decoder a16 m/io# bhe# a0 to a16 stb transceiver d0 to d15 t oe 8284a clk rdy ready reset# 16-bit mode, example: i8086 (maximum mode) (example implementation only - actual may vary) 8-bit mode, example: z80 (example implementation only - actual may vary)
4 s1d13503 series decoder decoder refresh smemw# smemr# iochrdy sd0 to sd15 sa0 to sa19 aen iow# ior# sbhe# reset# iocs16# la17 to la23 memcs16# memcs# memw# memr# ready db0 to db15 ab0 to ab19 iocs# iow# ior# bhe# reset sa14 to sa16 sa10 to sa15 sa(1 or 4) through sa9 16-bit isa bus s1d13503 decoder decoder isa bus 8-bit mode (isa) (example implementation only - actual may vary) 16-bit mode (isa) (example implementation only - actual may vary) refresh smemw# smemr# iochrdy sd0 to sd7 sa0 to sa19 aen iow# ior# reset# 0ws# memcs# memw# memr# ready db0 to db7 ab0 to ab19 iocs# iow# ior# reset sa13 to sa16 sa10 to sa15 sa(1 or 4) through sa9 optional 8-bit isa bus s1d13503 decoder decoder decoder
5 s1d13503 series internal block diagram functional block descriptions bus signal translation according to configuration setting vd2, the bus signal translation block translates either mc68000 type mpu signals or mpu controlled by a ready type signals to internal bus interface signals. control registers the register block contains the 16 internal control and configuration registers. these registers can be accessed by either direct-mapping or using the built-in internal index register. sequence controller the sequence controller block generates horizontal and vertical display timings according to the configuration registers settings. lcd panel interface the lcd interface block performs frame rate modulation and output data pattern formatting for both passive monochrome and passive color lcd panels. look-up table the look-up table block contains three 16 x 4-bit wide palettes. in gray shade modes, the "green" palette can be configured for the re-mapping of 16 possible shades of gray. in color modes, all three palettes can be configured for the re-mapping of 4096 possible colors. see look-up table architecture for details. port decoder according to configuration settings vd1, vd12-vd4, iocs# and address lines ab9-1, the port decoder validates a given i/o cycle. memory decoder according to configuration settings vd15-vd13, memcs# and address lines ab19-17, the memory decoder validates a given memory cycle. data bus conversion according to configuration setting vd0, the data bus conversion block maps the external data bus, either 8- bit or 16-bit, into the internal odd and even data bus. bus signal translation sequence controller port decoder memory decoder look-up table lcd panel interface display data formatter data bus conversion address generator mpu/crt selector sram interface control registers timing generator power save oscillator ior#, iow#, iocs#, memcs#, memr#, memw#, bhe#, ab[19:0] ready vwe# voe# vd[15:0] va[15:0], vsc0#, vsc1# osc1 osc2 lcdenb ud[3:0], ld[3:0], lp, yd, xscl, wf (xscl2) db[15:0] internal block diagram
6 s1d13503 series address generator the address generator generates display refresh addresses to be used to access display memory. mpu / crt selector this block grants access to the display memory from either the mpu or the display refresh circuitry. display data formatter the display data formatter reads in the display data from the display memory and outputs the correct format for all supported gray shade and color selections. clock inputs / timing the timing block generates the internal master clock (mclk) according to gray-level/color selected and display memory interface. the master clock (mclk) can be; - mclk = input clock - mclk = 1/2 input clock - mclk = 1/4 input clock pixel clock = input clock (f osc ) sram interface this block generates the necessary signals to interface to the display memory (sram).
7 s1d13503 series pinout diagram s1d13503f00a pinout diagram note: package type: 100 pin surface mount qfp5-s2 ? pin 80 = wf in all display modes except format 1 for 8-bit single color panel. ? pin 80 = xscl2 in format 1 for 8-bit single color panel. index s1d13503f00a db7 v ss v dd db8 db9 db10 db11 db12 db13 db14 db15 ab0 ab1 ab2 ab3 ab4 ab5 ab6 ab7 ab8 ab9 ab10 ab11 ab12 ab13 ab14 ab15 ab16 ab17 ab18 wf/xscl2 * lp yd ld0 ld1 ld2 ld3 ud0 ud1 ud2 ud3 vcs1# vcs0# vwe# va15 va14 va13 va12 va11 vd15 vd14 vd13 vd12 vd11 vd10 vd9 vd8 v dd v ss vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0 va10 va9 va8 va7 va6 va5 va4 va3 va2 va1 va0 reset ab19 xscl lcdenb voe# iocs# iow# ior# memcs# memw# memr# ready bhe# osc1 osc2 db0 db1 db2 db3 db4 db5 db6 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
8 s1d13503 series S1D13503F01A pinout diagram note: package type: 100 pin surface mount qfp15-std ? pin 77 = wf in all display modes except format 1 for 8-bit single color panel. ? pin 77 = xscl2 in format 1 for 8-bit single color panel. index S1D13503F01A db8 db9 db10 db11 db12 db13 db14 db15 ab0 ab1 ab2 ab3 ab4 ab5 ab6 ab7 ab8 ab9 ab10 ab11 ab12 ab13 ab14 ab15 ab16 yd ld0 ld1 ld2 ld3 ud0 ud1 ud2 ud3 vcs1# vcs0# vwe# va15 va14 va13 va12 va11 vd15 vd14 vd13 vd12 vd11 vd10 vd9 vd8 v dd v ss vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0 va10 va9 va8 va7 va6 va5 va4 va3 va2 va1 va0 reset ab19 ab18 ab17 lp wf/xscl2 * xscl lcdenb voe# iocs# iow# ior# memcs# memw# memr# ready bhe# osc1 osc2 db0 db1 db2 db3 db4 db5 db6 db7 v ss v dd 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
9 s1d13503 series s1d13503d00a pad diagram ? pad 97 = wf in all display modes except format 1 for 8-bit single color panel. ? pad 97 = xscl2 in format 1 for 8-bit single color panel. 1 v ss v dd db8 db9 db10 db11 db12 db13 db14 db15 ab0 ab1 ab2 ab3 ab4 ab5 ab6 ab7 ab8 ab9 ab10 ab11 ab12 ab13 ab14 ab15 ab16 ab17 ab18 ab19 reset va0 va1 va2 va3 va4 va5 va6 va7 va8 va9 va10 vd0 vd1 vd2 vd3 vd4 vd5 vd6 vd7 dummy pad v ss v dd vd8 vd9 vd10 vd11 vd12 vd13 vd14 vd15 va11 va12 va13 va14 va15 vwe# vcs0# vcs1# ud3 ud2 ud1 ud0 ld3 ld2 ld1 ld0 yd lp wf/xscl2 * xscl lcdenb voe# iocs# iow# ior# memcs# memw# memr# ready bhe# osc1 osc2 db0 db1 db2 db3 db4 db5 db6 db7 dummy pad 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 128 s1d13503d00a chip size = 5.030 mm x 5.030 mm chip thickness = 0.400 mm pad size = 0.090 mm x 0.090 mm pad pitch = 0.126 mm (min.)
10 s1d13503 series pad coordinates pad no. pad name pad center coordinate pad no. pad name pad center coordinate xy xy 1v ss -2.165 -2.390 66 2.000 2.390 2 -2.000 -2.390 67 v dd 1.840 2.390 3v dd -1.840 -2.390 68 vd8 1.685 2.390 4 db8 -1.685 -2.390 69 vd9 1.535 2.390 5 db9 -1.535 -2.390 70 vd10 1.388 2.390 6 db10 -1.388 -2.390 71 vd11 1.246 2.390 7 db11 -1.246 -2.390 72 vd12 1.106 2.390 8 db12 -1.106 -2.390 73 vd13 0.969 2.390 9 db13 -0.969 -2.390 74 vd14 0.835 2.390 10 db14 -0.835 -2.390 75 vd15 0.703 2.390 11 db15 -0.703 -2.390 76 0.573 2.390 12 -0.573 -2.390 77 va 11 0.444 2.390 13 ab0 -0.444 -2.390 78 va 12 0.317 2.390 14 ab1 -0.317 -2.390 79 va 13 0.190 2.390 15 ab2 -0.190 -2.390 80 va 14 0.063 2.390 16 ab3 -0.063 -2.390 81 va 15 -0.063 2.390 17 ab4 0.063 -2.390 82 vwe# -0.190 2.390 18 ab5 0.190 -2.390 83 vcs0# -0.317 2.390 19 ab6 0.317 -2.390 84 vcs1# -0.444 2.390 20 ab7 0.444 -2.390 85 -0.573 2.390 21 0.573 -2.390 86 ud3 -0.703 2.390 22 ab8 0.703 -2.390 87 ud2 -0.835 2.390 23 ab9 0.835 -2.390 88 ud1 -0.969 2.390 24 ab10 0.969 -2.390 89 ud0 -1.106 2.390 25 ab11 1.106 -2.390 90 ld3 -1.246 2.390 26 ab12 1.246 -2.390 91 ld2 -1.388 2.390 27 ab13 1.388 -2.390 92 ld1 -1.535 2.390 28 ab14 1.535 -2.390 93 ld0 -1.685 2.390 29 ab15 1.685 -2.390 94 yd -1.840 2.390 30 ab16 1.840 -2.390 95 -2.000 2.390 31 2.000 -2.390 96 lp -2.340 2.390 32 ab17 2.165 -2.390 97 wf/xscl2 -2.390 2.165 33 ab18 2.390 -2.340 98 -2.390 2.000 34 2.390 -2.000 99 -2.390 1.840 35 2.390 -1.840 100 xscl -2.390 1.685 36 ab19 2.390 -1.685 101 lcdenb -2.390 1.535 37 reset 2.390 -1.535 102 voe# -2.390 1.388 38 va 0 2.390 -1.388 103 iocs# -2.390 1.246 39 va 1 2.390 -1.246 104 iow# -2.390 1.106 40 va 2 2.390 -1.106 105 -2.390 0.969 41 2.390 -0.969 106 ior# -2.390 0.835 42 va 3 2.390 -0.835 107 memcs# -2.390 0.703 43 va 4 2.390 -0.703 108 -2.390 0.573 44 2.390 -0.573 109 memw# -2.390 0.444 45 va 5 2.390 -0.444 110 memr# -2.390 0.317 46 va 6 2.390 -0.317 111 -2.390 0.190 47 2.390 -0.190 112 ready -2.390 0.063 48 va 7 2.390 -0.063 113 bhe# -2.390 -0.063 49 va 8 2.390 0.063 114 -2.390 -0.190 50 2.390 0.190 115 osc1 -2.390 -0.317 51 va 9 2.390 0.317 116 osc2 -2.390 -0.444 52 va10 2.390 0.444 117 -2.390 -0.573 53 2.390 0.573 118 db0 -2.390 -0.703 54 vd0 2.390 0.703 119 db1 -2.390 -0.835 55 vd1 2.390 0.835 120 -2.390 -0.969 56 2.390 0.969 121 db2 -2.390 -1.106 57 vd2 2.390 1.106 122 db3 -2.390 -1.246 58 vd3 2.390 1.246 123 db4 -2.390 -1.388 59 vd4 2.390 1.388 124 db5 -2.390 -1.535 60 vd5 2.390 1.535 125 db6 -2.390 -1.685 61 vd6 2.390 1.685 126 -2.390 -1.840 62 2.390 1.840 127 -2.390 -2.000 63 2.390 2.000 128 db7 -2.390 -2.165 64 vd7 2.390 2.165 129 dummy pad 2.390 2.390 65 v ss 2.165 2.390 130 dummy pad -2.390 -2.390 (unit: mm)
11 s1d13503 series pin description description key: i = input o = output i/o = bidirectional (input/output) p = power pin cox = cmos level output driver, x denotes driver type (see table output specifications on page 15) coxs = cmos level output driver with slew rate control for noise reduction, x denotes driver type (see table output specifications on page 15) tsx = tri-state cmos level output driver, x denotes driver type (see table output specifications on page 15) tsxd2 = tri-state cmos level output driver with pull down resistor (typical values of 100 k ? /200 k ? at 5 v/3.0 v respectively), x denotes driver type (see table output specifications on page 15) ttl = ttl level input ttls = ttl level input with hysteresis bus interface pin name type f00a pin no . f01a pin no . d00a pad no . driver descr iption db0 db15 i/o 94 100, 1, 4 11 91 98, 1 8 118 119, 121 125, 128, 4 11 ts2 these pins are connected to the system data bus. in 8-bit bus mode, db8 db15 must be tied to v dd . ab0 12 13 ttls in mc68000 mpu interface, this pin is connected to the upper data strobe (uds#) pin of mc68000. in other mpu/bus inter- faces, this pin is connected to the system address bus. ab1 ab19 i i 13 31 10 28 14 20, 22 30, 32 33, 36 ttl bhe# i 91 88 9 113 ttls in mc68000 mpu interface, this pin is connected to the lower data strobe (lds#) pin of mc68000. in other mpu/bus inter- faces, this pin is the byte high enable input for use with 16-bit system. in 8-bit bus mode tie the bhe# input to v dd . iocs# i 84 81 103 ttls active low input to select one of sixteen internal registers. iow# i 85 82 104 ttls in mc68000 mpu interface, this pin is connected to the r/w# pin of mc68000. this input pin defines whether the data trans- fer is a read (active high) or write (active low) cycle. in other mpu/bus interfaces, this is the active low input to write data into an internal register. ior# i 86 83 106 ttls in mc68000 mpu interface, this pin is connected to the as# pin of mc68000. this input pin indicates a valid address is available on the address bus. in other mpu/bus interfaces, this is the active low input to read data from an internal register. memcs# i 87 84 107 ttls active low input to indicate a memory cycle. memw# i i 88 85 109 ttls active low input to indicate a memory write cycle. this pin should be tied to v dd in an mc68000 mpu interface. memr # 89 86 110 ttls active low input to indicate a memory read cycle. this pin should be tied to v dd in an mc68000 mpu interface. ready o 90 87 112 ts3 for mc68000 mpu interface, this pin is connected to the dtack# pin of mc68000 and is driven low when the data transfer is complete. in other mpu/bus interfaces, this output is driven low to force the system to insert wait states when needed. ready is placed in a high impedance (hi-z) state after the transfer is completed. reset i 32 29 37 ttls active high input to force all signals to their inactive states. these pins are connected to the system address bus.
12 s1d13503 series display memory interface lcd interface pin name type f00a pin no. f01a pin no. d00a pad no. driver descr iption vd0 vd15 i/o 44 51, 54 61 41 48, 51 58 54 55, 57 61, 64, 68 75 ts1d2 these pins are connected to the display memory data bus. for 16-bit interface, vd0 vd7 are connected to the display memory data bus of even byte addresses and vd8 vd15 are connected to the display memory data bus of odd byte addresses. the output drivers of these pins are placed in a high impedance state when reset is high. on the falling edge of reset, the values of vd0 vd15 are latched into the chip to configure various hardware options(see table summary of power on/reset options on page 13). va 0 va 1 5 o 3 3 43, 62 66 30 40, 59 63 38 40, 42 43, 45 46, 48 49, 51 52, 77 81 co1 these pins are connected to the display memory address bus. vcs1# o 69 66 84 co1 active low chip-select output to the second or odd byte address sram. see display memory interface section for details. vcs0# o 68 65 83 co1 active low chip-select output to the first or even byte address sram. see display memory interface section for details. active low output used for writing data to the display memory. this pin is connected to the we# input of the srams. active low output to enable reading of data from the display memory. this pin is connected to the oe# input of the srams. vwe# o 67 64 82 co1 voe# o 83 80 102 co1 pin name fpdi-1 tm pin name #1 type f00a pin no. f01a pin no. d00a pad no. driver descr iption ud3 ud0 ld3 ld 0 ud3 ud0 ld3 ld 0 o 70 73, 74 77 67 70, 71 74 86 89, 90 93 co3s panel display data bus. the data format depends on the specific panel connected. for 4-bit single panels, ld3 ld0 are driven low (0 state). xscl fpshift o 81 78 100 co3 lp fpline o 79 76 96 co3 wf/ xscl2 mod fpshift2 o 80 77 97 co3 for format 1 of 8-bit single color panels this is the second shift clock. for all other modes, this is the lcd backplane bias signal. this output toggles once every frame, or as programmed in aux[05] bits 7 2. yd fpframe o 78 75 94 co3 vertical scanning start pulse. a logic 1 on this signal, sampled by the lcd module on the falling edge of lp, is used by the panel y driver (row driver) to indicate the start of the vertical frame. lcdenb o 82 79 101 co2 lcd enable signal output. it can be used externally to turn off the panel supply voltage and backlight. display data latch clock. the falling edge of this signal is used to latch a row of display data in the lcd x-drivers and to turn on the y driver (row driver). display data shift clock. data is shifted into the lcd x-drivers on the falling edge of this signal. power supply pin name type f00a pin no. f01a pin no. d00a pad no. driver descr iption v dd p 3, 53 50, 100 3, 67 p voltage supply .. v ss p 2, 52 49, 99 1, 65 p voltage ground. pin name type f00a pin no. f01a pin no. d00a pad no. driver descr iption osc1 i 9 2 92 115 ? this pin, along with osc2, is the 2-terminal crystal interface when using a 2-terminal crystal as the clock input. if an external oscillator is used as a clock source, then this pin is the clock input. osc2 o 93 93 116 ? this pin, along with osc1, is the 2-terminal crystal interface when using a 2-terminal crystal as the clock input. if an external oscillator is used as a clock source this pin should be left unconnected. #1: vesa flat panel display interface standard (fpdi-1tm) clock inputs
13 s1d13503 series summary of configuration options the s1d13503 requires some configuration information on power-up. this information is provided through the sram data lines vd[0...15]. the state of these pins are read on the falling edge of reset and used to configure the following options: summary of power on / reset options note : the s1d13503 has internal pull down resistors on these pins and therefore will be pulled down and read on a logic 0 after reset. if pull up resistors are required refer to table input specifications on page 16 for pull down resistor values. example: if an isa bus (no byte swap) with memory segment a and i/o location 300h are used, the corresponding settings of vd15-vd0 would be: i/o and memory addressing example where x = don't care; 1 = connected to pull-up resistor; 0 = no pull-up resistor pin name value on this pin at falling edge of reset is used to con gure: (1/0) 1 0 vd0 16-bit host bus interface 8-bit host bus interface vd1 use direct-mapping for i/o accesses use internal index register for i/o accesses vd2 mc68000 mpu interface mpu / bus interface with memory accesses controlled by a ready (wait#) signal vd3 swap of high and low data bytes in 16-bit bus inter-face no byte swap of high and low data bytes in 16-bit bus interface vd12 vd4 select i/o mapping address bits [9:1]. vd15 vd13 select memory mapping address bits [3:1] these nine bits are latched on power-up and are compared to the mpu address bits [9 1]. a valid i/o cycle combined with a valid address will enable the internal i/o decoder. therefore, both types of i/o mapping are limited to even address boundaries to determine either the absolute or indexed i/o address of the first register. note that a valid i/o cycle includes iocs# being toggled low. these three bits are latched on power-up and are compared to the mpu address bits [19 17]. a valid memory cycle combined with a valid address will enable the internal memory decoder. as only the three most significant bits of the address are compared, the maximum amount of memory supported is 128k bytes. note that a valid memory cycle includes memcs# being toggled low. when using 128k-byte memory it must be mapped at an even address such that all 128k bytes is available without a change in state on a17, as this would invalidate the internal compare logic. pin name 8-bit isa bus 16-bit isa bus index register direct mapping index register direct mapping vd0 0 vd1 0 1 0 1 vd2 0 vd3 0 011 0 0 0 0 0 0 vd12 vd4 11 0000 000 11 0000 xxx 11 0000 000 11 0000 xxx vd15 vd13 101 101 101 101
14 s1d13503 series d.c. characteristics absolute maximum ratings symbol parameter rating units v dd supply voltage -0.3 to +6.0 v v in input voltage -0.3 to v dd + 0.5 v v out output voltage -0.3 to v dd + 0.5 v t stg storage temperature -65 to 150 c t sol solder temperature/time 260 for 10 sec. max. at lead c recommended operating conditions symbol parameter condition min. typ. max. units v dd supply voltage v ss = 0v 2.7 3.0/3.3/5.0 5.5 v v in input voltage ss dd v v v i opr operating current f osc = 6mhz 256 colors 4.5/5.0/11 ma t opr operating temperature -40 25 85 c input specifications symbol parameter condition min. typ. max. units v il low level input voltage v dd = 4.5v 0.8 v v dd = 3.0v 0.4 v dd = 2.7v 0.3 v ih high level input voltage v dd = 5.5v 2.0 v v dd = 3.6v 1.3 v dd = 3.3v 1.2 v t+ positive-going threshold v dd = 5.0v 2.4 v v dd = 3.3v 1.4 v dd = 3.0v 1.3 v t- negative-going threshold v dd = 5.0v 0.6 v v dd = 3.3v 0.5 v dd = 3.0v 0.4 v h hysteresis voltage v dd = 5.0v 0.1 v v dd = 3.3v 0.1 v dd = 3.0v 0.1 i iz input leakage current -1 1 a c in input pin capacitance f = 1mhz v dd = 0v 12 pf r pd pull down resistance v dd = 5.0v v i = v dd 50 100 200 k ? v dd = 3.3v v i = v dd 90 180 360 v dd = 3.0v v i = v dd 100 200 400
15 s1d13503 series output specifications symbol parameter condition min. typ. max. units v (5.0v) low level output voltage type 1 - ts1d2, co1 type 2 - ts2 type 3 - ts3, co3, co3s v = min. i = 4ma i = 8ma i = 12ma 0.4 v v (3.3v) low level output voltage type 1 - ts1d2, co1 type 2 - ts2 type 3 - ts3, co3, co3s v = min. i = 2ma i = 4ma i = 6ma 0.3 v v (3.0v) low level output voltage type 1 - ts1d2, co1 type 2 - ts2 type 3 - ts3, co3, co3s v = min. i = 1.8ma i = 3.5ma i = 5ma 0.3 v v (5.0v) high level output voltage type 1 - ts1d2, co1 type 2 - ts2 type 3 - ts3, co3, co3s v = min. i = -4ma i = -8ma i = -12ma v-0.4 v v (3.3v) high level output voltage type 1 - ts1d2, co1 type 2 - ts2 type 3 - ts3, co3, co3s v = min. i = -2ma i = -4ma i = -6ma v-0.3 v v (3.0v) high level output voltage type 1 - ts1d2, co1 type 2 - ts2 type 3 - ts3, co3, co3s v = min. i = -1.8ma i = -3.5ma i = -5ma v-0.3 v i output leakage current - 1 1 a c output pin capacitance f = 1mhz v= 0v 12 pf c bidirectional pin capacitance f = 1mhz v ol dd ol ol ol ol dd ol ol ol ol dd ol ol ol oh dd oh oh oh dd oh dd oh oh oh dd oh dd oh oh oh dd oz out dd bi d dd = 0v 12 pf
16 s1d13503 series display memory interface sram configurations supported 8-bit mode 8-bit mode - 16k bytes sram (requires aux[01] bit 0 = 0) we# 8k x 8 cs# we# 8k x 8 cs# vd0-7 vwe# vcs0# vcs1# va0-12 s1d13503 we# 8k x 8 cs# n/c s1d13503 vd0-7 vwe# vcs0# vcs1# va0-12 8-bit mode - 8k bytes sram (requires aux[01] bit 0 = 0) 8-bit mode - 32k bytes sram (requires aux[01] bit 0 = 1) we# 32k x 8 cs# n/c vd0-7 vwe# vcs0# vcs1# va0-14 s1d13503
17 s1d13503 series we# 8k x 8 cs# cs# 8k x 8 we# s1d13503 vd0-7 vwe# vcs0# va0-12 vcs1# vd8-15 16-bit mode 16-bit mode - 16k bytes sram we# 32k x 8 cs# we# 32k x 8 cs# vd0-7 vwe# vcs0# vcs1# va0-14 s1d13503 8-bit mode - 64k bytes sram (requires aux[01] bit 0 = 1) we# 32k/8k x 8 cs# we# 8k/32k x 8 cs# s1d13503 vd0-7 vwe# vcs0# vcs1# va0-14 8-bit mode - 40k bytes sram [either (8k x 8 + 32k x 8) requiring aux[01] bit 0 = 0 or (32k x 8 + 8k x 8) requiring aux[01] bit 0 = 1]
18 s1d13503 series s1d13503 64k x 16 vwe# vcs0# vcs1# va0-15 vd0-7 vd8-15 we# lb# ub# a0-15 i/o 1-8 i/o 9-16 16-bit mode - 128k bytes sram we# 32k x 8 cs# cs# 32k x 8 we# s1d13503 vd0-7 vwe# vcs0# va0-14 vcs1# vd8-15 16-bit mode - 64k bytes sram
19 s1d13503 series unit: mm unit: mm mechanical data mechanical drawing qfp15-100-std mechanical drawing qfp5-100-s2 14 0.1 16 0.4 51 75 14 0.1 16 0.4 26 50 index 0.18 25 1 100 76 1.4 0.1 0.1 1.7 max 1 0.5 0.2 0 10 0.125 0.5 +0.1 0.05 +0.05 0.025 20 0.1 23.2 0.4 51 80 14 0.1 17.2 0.4 31 50 index 0.3 +0.1 0.05 30 1 100 81 2.7 0.1 0.35 3.5 max 1.6 0.8 0.2 0 10 0.15 0.05 0.65
s1d13503 series notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there i s no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2001, all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department europe & u.s.a. 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department asia 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110 epson electronic devices website http://www.epsondevice.com first issue november, 1997 h printed october, 2001 in japan c

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