cy2313anz 13 output, 3.3 v clock buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07144 rev. *c revised september 14, 2010 13 output, 3.3 v clock buffer features one input to 13 output buffer/driver supply voltage: 3.3 v supports up to three sdram dimms smbus serial interfac e for output control low skew outputs up to 100-mhz operation multiple v dd and v ss pins for noise reduction low emi outputs package: 28-pin small-outline integrated circuit (soic) functional description the cy2313anz is a 3.3 v clock buffer. while originally designed to distribute clocks in desktop pc applications - hence the signal names - it is a general purpose device suitable to a wide variety of clock buffering app lications. the part has thirteen outputs. in a pc application, twel ve of which can be used to drive up to three sdram dimms, and the remaining output can be used for external feedback to a pll. the device operates at 3.3 v and outputs can run up to 100 mhz. the cy2313anz also includes an smbus serial interface which can enable or disable each output clock. on power-up, all output clocks are enabled. logic block diagram serial interface buf_in sdata sclock sdram0 sdram1 sdram2 sdram3 sdram4 sdram5 sdram6 sdram7 decoding sdram8 sdram9 sdram10 sdram11 sdram12 [+] feedback
cy2313anz document number: 38-07144 rev. *c page 2 of 10 pin summary name pins description v dd 1, 5, 20, 24, 28 3.3 v digital voltage supply v ss 4, 8, 17, 21, 25 ground v ddiic 13 serial interface voltage supply v ssiic 16 ground for serial interface buf_in 9 input clock sdata 14 smbus data input/output, internal pull-up to v dd sclk 15 smbus clock input, internal pull-up to v dd sdram [0-12] 2, 3, 6, 7, 10, 11, 12, 18, 19, 22, 23, 26, 27 clock outputs 1 2 3 4 v dd sdram11 sdram10 v ss v dd sdram9 pin configuration 8 5 6 7 12 9 10 11 13 14 28 27 26 25 21 24 23 22 17 20 19 18 16 15 sdram8 v ss v dd sdram7 sdram6 v ss v ssiic sclk v dd sdram0 sdram1 v ss v dd sdram2 v ss buf_in sdram4 sdram5 sdram12 v ddiic sdata sdram3 figure 1. 28-pin soic (top view) [+] feedback
cy2313anz document number: 38-07144 rev. *c page 3 of 10 serial configuration map the serial bits will be read by the clock driver in the following order: byte 0 - bits 7, 6, 5, 4, 3, 2, 1, 0 byte 1 - bits 7, 6, 5, 4, 3, 2, 1, 0 . . . byte n - bits 7, 6, 5, 4, 3, 2, 1, 0 reserved and unused bits should be programmed to ?0? serial interface address for the cy2313anz is: a6 a5 a4 a3 a2 a1 a0 r/w 1101001? byte 0:sdram active/ inactive register (1 = enable, 0 = disabl e), default = enabled bit pin # description bit 7 11 sdram5 (active/inactive) bit 6 10 sdram4 (active/inactive) bit 5 ? reserved, drive to 0 bit 4 ? reserved, drive to 0 bit 3 7 sdram3 (active/inactive) bit 2 6 sdram2 (active/inactive) bit 1 3 sdram1 (active/inactive) bit 0 2 sdram0 (active/inactive) byte 1: sdram active/inactive register (1 = active, 0 = inact ive), default = active bit pin # description bit 7 27 sdram11 (active/inactive) bit 6 26 sdram10 (active/inactive) bit 5 23 sdram9 (active/inactive) bit 4 22 sdram8 (active/inactive) bit 3 ? reserved, drive to 0 bit 2 ? reserved, drive to 0 bit 1 19 sdram7 (active/inactive) bit 0 18 sdram6 (active/inactive) byte 2: sdram active/inactive register (1 = active, 0 = inact ive), default = active bit pin # description bit 7 ? reserved, drive to 0 bit 6 12 sdram12 (active/inactive) bit 5 ? reserved, drive to 0 bit 4 ? reserved, drive to 0 bit 3 ? reserved, drive to 0 bit 2 ? reserved, drive to 0 bit 1 ? reserved, drive to 0 bit 0 ? reserved, drive to 0 [+] feedback
cy2313anz document number: 38-07144 rev. *c page 4 of 10 maximum ratings exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. supply voltage to ground potenti al ...............?0.5 v to +7.0 v dc input voltage (except buf_in) ...... ?0.5 v to v dd + 0.5 v dc input voltage (buf_in) .......... .............. ...?0.5 v to +7.0 v storage temperature ................................ ?65 ? c to +150 ? c junction temperature................................................. 150 ? c static discharge voltage (per mil-std-883, method 3015) .. ............. ............ > 2000 v operating conditions [1] parameter description min max unit v dd supply voltage 3.135 3.465 v t a operating temperature (a mbient temperature) 0 70 ? c c l load capacitance ? 30 pf c in input capacitance ? 7 pf t pu power-up time for all v dd ?s to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms electrical characteristics over the operating range parameter description test conditions min max unit v il input low voltage [2] except serial interface pins ? 0.8 v v iliic input low voltage for serial interface pins only ? 0.7 v v ih input high voltage [2] 2.0 ? v i il input low current (buf_in input) v in = 0 v ?10 10 a i il input low current (except buf_in pin) v in = 0 v ? 100 a i ih input high current v in = v dd ?10 10 a v ol output low voltage [3] i ol = 25 ma ? 0.4 v v oh output high voltage [3] i oh = ?36 ma 2.4 ? v i dd supply current [3] unloaded outputs, 100 mhz ? 200 ma i dd supply current [3] loaded outputs, 100 mhz ? 290 ma i dd supply current [3] unloaded outputs, 66.67 mhz ? 150 ma i dd supply current [3] loaded outputs, 66.67 mhz ? 185 ma i dds supply current buf_in = v dd or v ss all other inputs at v dd ?500a notes 1. electrical parameters are guaranteed und er the operating conditions specified. 2. buf_in input has a threshold voltage of v dd /2. 3. parameter is guaranteed by design and charac terization. not 100% tested in production. [+] feedback
cy2313anz document number: 38-07144 rev. *c page 5 of 10 switching characteristics [4] over the operating range parameter name test conditions min typ max unit maximum operating frequency ? ? 100 mhz duty cycle [5, 6] = t 2 ?? t 1 measured at 1.5 v 45 50 55 % t 3 rising edge rate [5] measured between 0.4 v and 2.4 v 0.9 1.5 4.0 v/ns t 4 falling edge rate [5] measured between 2.4 v and 0.4 v 0.9 1.5 4.0 v/ns t 5 output to output skew [5] all outputs equally loaded ?250 ? 250 ps t 6 sdram buffer lh propagation delay [5] input edge greater than 1 v/ns 1.0 3.5 5.0 ns t 7 sdram buffer hl propagation delay [5] input edge greater than 1 v/ns 1.0 3.5 5.0 ns notes 4. all parameters specified with loaded outputs. 5. parameter is guaranteed by design and characteri zation. not 100 percent tested in production. 6. duty cycle of input clock is 50 pe rcent. rising and falling edge rate of th e input clock is gr eater than 1 v/ns. switching waveforms figure 2. duty cycle timing t 1 t 2 1.5 v 1.5 v 1.5 v figure 3. all outputs rise/fall time output 3.3 v t 3 0 v 0.4 v 2.4 v 2.4 v 0.4 v t 4 1.5 v t 5 output output 1.5 v figure 4. output-output skew [+] feedback
cy2313anz document number: 38-07144 rev. *c page 6 of 10 application information clock traces may require either series or parallel termi nation. an ibis model is available for simulation. surface mount, low-esr, ceramic capacitors should be used for filtering. typically, these capacitors have a value of 0.1 ? f. in some cases, smaller value capacitors may be required. the value of the series terminating resist or satisfies the following equation, where rtrace is the loaded characteristic impeda nce of the trace, rout is the output impeda nce of the buffer (typically 25 ? ), and rseries is the series terminating resistor. rseries > rtrace ? rout footprints must be laid out for optional emi-reducing capacito rs, which should be placed as close to the terminating resistor a s is physically possible. typical values of these capacitors range from 4.7 pf to 22 pf. a ferrite bead may be used to isolate the board v dd from the clock generator v dd island. ensure that the ferrite bead offers greater than 50 ? impedance at the clock frequency, under loaded dc conditions. refer to the application note layout and termination techniques for cypress clock generators for more details. if a ferrite bead is used, a 10 f to 22 f tantalum bypass ca pacitor should be placed close to the ferrite bead. this capacito r prevents power supply droop during current surges. switching waveforms (continued) figure 5. sdram buffer lh and hl propagation delay t 6 input output t 7 0.1 ? f v dd clk out c load outputs gnd test circuit [+] feedback
cy2313anz document number: 38-07144 rev. *c page 7 of 10 ordering code definitions ordering information ordering code package type operating range cy2313anzsc?1 28-pin soic commercial, 0 ? c to 70 ? c pb-free cy2313anzsxc?1 28-pin soic commercial, 0 ? c to 70 ? c cy2313anzsxc?1t 28-pin soic tape and reel commercial, 0 ? c to 70 ? c t = tape and reel, blank = tube fixed value temperature range: c = commercial package: xx = sx or s sx = soic, pb-free s = soic, not pb-free part identifier company code: cy = cypress semiconductor 2313anz cy xx c ? 1 (t) package diagram figure 6. 28-pin (300-mil) molded soic 51-85026 *e [+] feedback
cy2313anz document number: 38-07144 rev. *c page 8 of 10 acronyms document conventions units of measure acronym description dimm dual in-line memory module pc personal computer pll phase-locked loop sdram synchronous dynamic random access memory soic small-outline integrated circuit symbol unit of measure ? c degree celcius a micro amperes ma milli amperes ms milli seconds mhz mega hertz ns nano seconds ? ohms pf pico farad vvolts [+] feedback
cy2313anz document number: 38-07144 rev. *c page 9 of 10 document history page document title: cy2313anz 13 output, 3.3 v clock buffer document number: 38-07144 rev. ecn no. issue date orig. of change description of change ** 110253 11/18/01 dsg change from spec number: 38-00692 to 38-07144 *a 121831 12/14/02 rbi power up requirements a dded to operating conditions information *b 1244583 see ecn dpf added pb-free part numbers in the ordering information *c 3022355 09/14/2010 kvm changed title from ?13 output, 3.3 v sdram buffer for desktop pcs with three dimms? to ?13 output, 3.3 v clock buffer? clarified that the serial interface is smbus removed timing parameters and wa veforms that were not applicable added ordering code definitions updated package diagram added acronyms and document conventions minor edits and updated in new template [+] feedback
document number: 38-07144 rev. *c revised september 14, 2010 page 10 of 10 pentium is a registered trademark of intel corporation. all products and company names mentioned in this document may be the trademarks of their respective holders. cy2313anz ? cypress semiconductor corporation, 2001-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback
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