View UPD789012CT-XXX_7279027.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet mos integr a ted circuit m pd7890 1 1, 789012 8-bit single-chip microcontroller the information in this document is subject to change without notice. the m pd789011 and 789012 are products in the m pd789014 subseries of compact, general-purpose microcontrollers in the 78k/0s series. in addition to an 8-bit cpu, these products have substantial hardware such as on-chip i/o ports, timers, serial interface, and interrupt controls. the m pd78p9014, one-time prom product that can be written only once, and various development tools are also available. these users manuals contain detailed descriptions of the functions. be sure to read them before designing. m pd78p9014 subseries users manual : u11187e 78k/0s series users manual instructio n : u11047e features ? rom and ram capacity item program memory data memory (internal package product name (rom) high-speed ram) m pd789011 2 kbytes 128 bytes 28-pin plastic shrink dip (400 mil) m pd789012 4 kbytes 28-pin plastic sop (375 mil) ? minimum instruction execution time changeable to the high-speed (0.4 m s) and the low-speed (1.6 m s) ? i/o ports: 22 ? serial interface: 1 channel 3-wire serial i/o mode/uart mode selectable ? timers: 3 channels ? 8-bit timer/event counter: 2 channels ? watchdog timer: 1 channel ? power supply voltage : v d d = 1.8 to 5.5 v the mark shows major revised points. document no. u11095ej1v0ds00 (1st edition) date publishe d november 1997 n printed in japan 1996
m pd789011, 789012 2 application fields compact household appliances, remote controls, games, etc. ordering information part number package m pd789011ct- 28-pin plastic shrink dip (400 mil) m pd789011gt- 28-pin plastic sop (375 mil) m pd789012ct- 28-pin plastic shrink dip (400 mil) m pd789012gt- 28-pin plastic sop (375 mil) remark indicates the rom code suffix.
m pd789011, 789012 3 overview of the functions item m pd789011 m pd789012 on-chip memory rom 2 kbytes 4 kbytes high-speed ram 128 bytes general-purpose registers 8 bits 8 registers minimum instruction execution time 0.4 m s or 1.6 m s (at 5.0-mhz operation with main system clock) instruction set ? 16-bit calculations ? bit manipulation (set, reset, test) i/o ports cmos i/o : 22 serial interface 3-wire serial i/o mode/uart mode selectable : 1 channel timers ? 8-bit timer/event counter : 2 channels ? watchdog timer : 1 channel timer output 2 vector interrupt source maskable internal: 6, external: 3 non-maskable internal: 1 power supply voltage v dd = 1.8 to 5.5 v ambient operating temperature t a = C40 to +85 c package ? 28-pin plastic shrink dip (400 mil) ? 28-pin plastic sop (375 mil)
m pd789011, 789012 4 78k/0s series expansion the following shows the 78k/0s series products development. subseries names are shown inside frames. compact, general- purpose compact, general- purpose + a/d rc oscillation version the following lists the main functional differences between subseries products. function rom timers 8-bit 10-bit serial interface i/o minimum remark subseries name capacity 8-bit 16-bit watch wdt a/d a/d v dd m pd789026 4k to 16k 1ch 1ch 1ch 1ch (uart :1 ch) 34 1.8 v m pd789014 2k to 4k 2ch 22 m pd789134 2k to 8k 1ch 1ch 1ch 4ch 1ch (uart : 1ch) 20 1.8 v m pd789124 4ch m pd789114 4ch m pd789104 4ch lcd driving m pd789417 12k to 24k 3ch 1ch 1ch 1ch 7ch 1ch (uart : 1ch) 43 1.8 v m pd789407 7ch assp m pd789800 8k 2ch 1ch 2ch (usb : 1ch) 31 4.0 v m pd789810 6k 1 1.8 v on-chip eeprom tm products in mass production products under development m pd789026 m pd789014 m pd789417 m pd789407 m pd789800 m pd789810 m a 16-bit timer was added to the pd789014. on-chip uart, and low voltage operation (1.8 v) is possible. a/d converter of the pd789407 was enhanced. a/d converter was added to the pd789026, and timer was enhanced. for pc keyboards. on-chip usb functions. for ic cards. on-chip security circuit. 42/44-pin 28-pin 80-pin 80-pin 42/44-pin 5-pin y subseries products are compatible with i 2 c bus. 78k/0s series compact general-purpose m pd789134 m pd789124 m m a/d converter of the pd789124 was enhanced. rc oscillation version of pd789104 28/30-pin 28/30-pin m pd789114 m pd789104 m m a/d converter of the pd789104 was enhanced. a/d converter and mulitplier were added to the pd789104 28/30-pin 28/30-pin compact general-purpose + a/d driving lcd assp m m
m pd789011, 789012 5 contents 1. pin configuration (top view) ................................................................................................. ...... 6 2. block diagram................................................................................................................ ................ 7 3. pin function list ............................................................................................................ ................ 8 3.1 port pins ................................................................................................................... ................................... 8 3.2 non-port pins ............................................................................................................... ............................... 9 3.3 pin i/o circuit and recommended connecitons of unused pins ........................................................ 10 4. memory space ................................................................................................................. .............. 11 5. peripheral hardware functions ......................................................................................... 12 5.1 ports ....................................................................................................................... .................................... 12 5.2 clock generator ............................................................................................................. ........................... 12 5.3 timer ....................................................................................................................... ................................... 13 5.4 serial interface ............................................................................................................ .............................. 14 6. interrupt functions .......................................................................................................... ........ 15 7. standby functions ............................................................................................................ ......... 17 8. reset functions .............................................................................................................. ............. 17 9. overview of the instruction set ......................................................................................... 18 9.1 legend ...................................................................................................................... ................................. 18 9.2 operation list .............................................................................................................. .............................. 20 10. electrical specifications ................................................................................................... .... 25 11. package drawings ............................................................................................................ .......... 37 12. recommended soldering conditions.................................................................................. 39 appendix a. development tools................................................................................................. .40 appendix b. related documents ................................................................................................. 41
m pd789011, 789012 6 1. pin configuration (top view) ? 28-pin plastic shrink dip (400 mil) m pd789011ct- m pd789012ct- ? 28-pin plastic sop (375 mil) m pd789011gt- m pd789012gt- caution connect ic pin directly to v ss . asck : asynchronous serial clock sck0 : serial clock ic : internally connected si0 : serial input intp0 to intp2 : interrupt from peripherals so0 : serial output p00 to p07 : port0 ti0, ti1 : timer input p10 to p17 : port1 to0, to1 : timer output p20 to p22 : port2 txd : transmit data p30 to p32 : port3 v dd : power supply reset : reset v ss : ground rxd : receive data x1, x2 : crystal p31/intp1/ti1/to1 p32/intp2 ic reset x2 x1 v ss v dd p00 p01 p02 p03 p04 p05 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 p30/intp0/ti0/to0 p22/rxd/si0 p21/txd/so0 p20/asck/sck0 p17 p16 p15 p14 p13 p12 p11 p10 p07 p06
m pd789011, 789012 7 2. block diagram ti0/to0/p30/intp0 ti1/to1/p31/intp1 sck0/asck/p20 so0/txd/p21 si0/rxd/p22 intp0/p30 to intp2/p32 8-bit timer/ event counter0 8-bit timer/ event counter1 watchdog timer serial interface0 interrupt control 78k/0s cpu core rom ram port0 port1 port2 port3 system control v dd v ss ic p00 to p07 p10 to p17 p20 to p22 p30 to p32 reset x1 x2
m pd7890 1 1, 789012 8 3. pin function list 3.1 port pins pin name i/o function after reset alternate function p00 to p07 i/ o port 0 input 8-bit i/o port input/output specifiable bit-wise when used as an input port, on-chip pull-up resistor can be used by software. leds can be directly driven. p10 to p17 i/ o port 1 input 8-bit i/o port input/output specifiable bit-wise when used as an input port, on-chip pull-up resistor can be used by software. leds can be directly driven. p20 i/o port 2 input asck/sck0 3-bit i/o port p21 input/output specifiable bit-wise txd/so0 when used as an input port, on-chip pull-up resistor can be used p22 by software. rxd/si0 leds can be directly driven. p30 i/o port 3 input intp0/ti0/to0 3-bit i/o port p31 input/output specifiable bit-wise intp1/ti1/to1 when used as an input port, on-chip pull-up resistor can be used p32 by software. intp2 leds can be directly driven.
m pd789011, 789012 9 3.2 non-port pins pin name i/o function after reset alternate function intp0 note input external interrupt input whose valid edge can be specified (rising input p30/ti0/to0 intp1 note edge, falling edge, or both the rising and falling edges). p31/ti1/to1 intp2 note p32 si0 note input serial data input in the serial interface input p22/rxd so0 output serial data output in the serial interface input p21/txd sck0 note i/o serial clock i/o for the serial interface input p20/asck rxd note input serial data input for the asynchronous serial interface input p22/si0 txd output serial data output for the asynchronous serial interface input p21/so0 asck note input serial clock input for the asynchronous serial interface input p20/sck0 ti0 note input external count clock input to the 8-bit timer (tm0) input p30/intp0/to0 ti1 note external count clock input to the 8-bit timer (tm1) p31/intp1/to1 to0 output 8-bit timer output input p30/intp0/ti0 to1 p31/intp1/ti1 reset input system reset input input x1 input crystal connection for the main system clock oscillation x2 v dd positive power supply ic internally connected. connect directly to v ss . v ss ground potential note these pins are input through schmitt triggers (see type 5-d in figure 3-1 pin i/o circuit types ).
m pd789011, 789012 10 3.3 pin i/o circuit and recommended connections of unused pins table 3-1 shows the types of the i/o circuits of each pin and the connections for unused pins. see figure 3-1 for the structure of each type of i/o circuit. table 3-1. types of pin i/o circuits pin name i/o circuit type i/o recommended connection for unused pins p00-p07 5-a i/o connect to v dd or v ss via a resistor independently. p10-p17 p20/asck/sck0 5-d p21/txd/so0 5-a p22/rxd/si0 5-d p30/intp0/ti0/to0 connect to v ss via a resistor independently. p31/intp1/ti1/to1 p32/intp2 reset 2 ic connect directly to v ss . figure 3-1. summary of the pin i/o circuits schmitt-triggered input with hysteresis characteristics type 2 type 5-a type 5-d in v dd p-ch v dd p-ch n-ch in/out pullup enable data output disable input enable v dd p-ch v dd p-ch n-ch in/out pullup enable data output disable input enable
m pd789011, 789012 11 4. memory space figure 4-1 shows the m pd789011 and 789012 memory map. figure 4-1. memory map note internal rom capacity differs depending on the product (see the table below). product name internal rom bottom address nnnnh m pd789011 07ffh m pd789012 0fffh f f f e 0 f 0 f h h ffffh f f e e 8 7 0 f h h nnnn nnnn h + 1 h 0000h 0000h 0 0 0 0 8 7 0 f h h nnnnh 0 0 0 0 4 3 0 f h h 0 0 0 0 1 1 4 3 h h data memory space program memory space special function register 256 8 bits internal high-speed ram 128 8 bits use prohibited internal rom note program area callt table area program area vector table area
m pd789011, 789012 12 5. peripheral hardware functions 5.1 ports the m pd789011 and 789012 are provided with the ports shown below, which enable various types of control. table 5-1. port functions name pin name function port 0 p00 to p07 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. port 1 p10 to p17 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. port 2 p20 to p22 3-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. port 3 p30 to p32 3-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. 5.2 clock generator the main system clock generator is incorporated. also, the minimum instruction execution can be changed. ? 0.4 m s/1.6 m s (at 5.0-mhz operation with main system clock) figure 5-1. clock generator block diagram x1 stop x2 main system clock oscillator f x prescaler f x 2 2 prescaler clock to peripheral hardware cpu clock (f cpu ) standby control circuit wait control circuit selector
m pd789011, 789012 13 5.3 timer the m pd789011 and 789012 incorporate 3 channels of the timer. ? 8-bit timer/event counter : 2 channels ? watchdog timer : 1 channel table 5-2. operations of timer 8-bit timer/event counter watchdog timer operation mode interval timer 2 channels 1 channel external event counter 2 channels function timer output 2 outputs interrupt request 2 1 figure 5-2. 8-bit timer/event counter block diagram remark n = 0 or 1 figure 5-3. watchdog timer block diagram internal bus 8-bit compare register (crn0) match selector inttmn ton/p3n/intpn/tin clear 8-bit timer register (tmn) output control circuit internal bus f x f x /2 5 tin/p3n/intpn/ton prescaler f x 2 6 f x 2 8 f x 2 10 selector 7-bit counter control circuit f x 2 4 intwdt maskable interrupt request intwdt non-maskable interrupt request reset
m pd789011, 789012 14 5.4 serial interface 1 channel of serial interface is incorporated. serial interface channel 0 has the following two modes. ? 3-wire serial i/o mode : msb/lsb first switchable ? asynchronous serial interface (uart) mode : dedicated baud rate generator incorporated figure 5-4. serial interface channel 0 block diagram internal bus receive buffer register (rxb/sio0) direction control circuit direction control circuit transmit shift register (txs/sio0) receive shift register (rxs) transmit control circuit receive control circuit sck output control circuit baud rate generator r x d/si0/p22 t x d/so0/p21 asck/sck0/p20 intst intsr/intcsi0 f x /2 to f x /2 8
m pd789011, 789012 15 6. interrupt functions there are 10 interrupt functions of 2 different sources as follows. ? non-maskable : 1 ? maskable : 9 table 6-1. interrupt source list interrupt interrupt source internal/ vector basic priority note 1 table configuration type name trigger external address type note 2 non-maskable intwdt watchdog timer overflow internal 0004h (a) (when the watchdog timer mode 1 is selected) maskable 0 intwdt watchdog timer overflow (b) (when the interval timer mode is selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intsr completion of serial interface channel 0 internal 000ch (b) uart reception intcsi0 completion of serial interface channel 0 3-wire transfer 5 intst completion of serial interface channel 0 000eh uart transmission 6 inttm0 generation of matching signal of 8-bit timer/ 0010h event counter 0 7 inttm1 generation of matching signal of 8-bit timer/ 0012h event counter 1 notes 1. the priority is the priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest order and 7 the lowest. 2. basic configuration types (a) to (c) correspond to those in figure 6-1, respectively.
m pd789011, 789012 16 figure 6-1. basic configuration of interrupt functions (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt if : interrupt request flag ie : interrupt enable flag mk : interrupt mask flag internal bus interrupt request vector table address generation circuit standby release signal internal bus mk if interrupt request ie vector table address generation circuit standby release signal internal bus external interrupt mode register (intm0) mk if ie vector table address generation circuit standby release signal edge detection circuit interrupt request
m pd789011, 789012 17 7. standby functions there are the following two standby functions to reduce the system power consumption. ? halt mode : the cpu operation clock is stopped. the average current consumption can be reduced by intermittent operation in combination with the normal operation mode. ? stop mode: the main system clock oscillation is stopeed. all the operations performed on the main system clock is stopped, and power consumption becomes extremely small. figure 7-1. standby function 8. reset functions there are the following two reset methods. ? external reset input by reset pin ? internal reset by watchdog timer runaway time detection main system clock operation stop mode main system clock oscillatin is stopped halt mode clock supply to cpu is stopped, oscillation maintained ( ( ( ( stop instruction halt instruction interrupt request interrupt request
m pd789011, 789012 18 9. overview of the instruction set the instruction set of m pd789011 and 789012 is shown in the table below. 9.1 legend 9.1.1 operand identifiers and methods of use operands are described in operand column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more description methods, select one of them. alphabetic letters in capitals and symbols, #, !, $, and [ ] are keywords and must be described as they are. each symbol has the following meaning. ? # : immediate data specification ? $ : relative address specification ? ! : absolute address specification ? [ ] : indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $, and [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. table 9-1. operand identifiers and description methods identifier description method r x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) rp ax (rp0), bc (rp1), de (rp2), hl (rp3) sfr special-function register symbol saddr fe20h to ff1fh immediate data or labels saddrp fe20h to ff1fh immediate data or labels (even addresses only) addr16 0000h to ffffh immediate data or labels (only even addresses in a 16-bit data transfer instructions) addr5 0040h to 007fh immediate data or labels (even addresses only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label
m pd789011, 789012 19 9.1.2 description of operation column a : a register ; 8-bit accumulator x : x register b : b register c : c register d : d register e : e register h : h register l : l register ax : ax register pair; 16-bit accumulator bc : bc register pair de : de register pair hl : hl register pair pc : program counter sp : stack pointer psw : program status word cy : carry flag ac : auxiliary carry flag z : zero flag ie : interrupt request enable flag nmis : non-maskable interrupt servicing flag ( ) : memory contents indicated by the address or register contents in parentheses x h , x l : high 8 bits and low 8 bits of a 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) : inverted data addr16 : 16-bit immediate data or label jdisp8 : signed 8-bit data (displacement value) 9.1.3 description of flag operation column (blank) : unchanged 0 : clear to 0. 1 : set to 1. : set/cleared according to the result r : previously saved value is restored.
m pd789011, 789012 20 9.2 operation list mnemonic operand bytes clock operation flags zaccy mov r, #byte 3 6 r ? byte saddr, #byte 3 6 (saddr) ? byte sfr, #byte 3 6 sfr ? byte a, r note 1 24a ? r r, a note 1 24r ? a a, saddr 2 4 a ? (saddr) saddr, a 2 4 (saddr) ? a a, sfr 2 4 a ? sfr sfr, a 2 4 sfr ? a a, !addr16 3 8 a ? (addr16) !addr16, a 3 8 (addr16) ? a psw, #byte 3 6 psw ? byte a, psw 2 4 a ? psw psw, a 2 4 psw ? a a, [de] 1 6 a ? (de) [de], a 1 6 (de) ? a a, [hl] 1 6 a ? (hl) [hl], a 1 6 (hl) ? a a, [hl + byte] 2 6 a ? (hl + byte) [hl + byte], a 2 6 (hl + byte) ? a xch a, x 1 4 a ? x a, r note 2 26a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? (sfr) a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) a, [hl + byte] 2 8 a ? (hl + byte) movw rp, #word 3 6 rp ? word ax, saddrp 2 6 ax ? (saddrp) saddrp, ax 2 8 (saddrp) ? ax ax, rp note 3 1 4 ax ? rp rp, ax note 3 1 4 rp ? ax xchw ax, rp note 3 1 8 ax ? rp notes 1. except r = a 2. except r = a or x 3. only when rp = bc, de, or hl remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc).
m pd789011, 789012 21 mnemonic operand bytes clock operation flags zaccy add a, #byte 2 4 a, cy ? a + byte saddr, #byte 3 6 (saddr), cy ? (saddr) + byte a, r 2 4 a, cy ? a + r a, saddr 2 4 a, cy ? a + (saddr) a, !addr16 3 8 a, cy ? a + (addr16) a, [hl] 1 6 a, cy ? a + (hl) a, [hl + byte] 2 6 a, cy ? a + (hl + byte) addc a, #byte 2 4 a, cy ? a + byte + cy saddr, #byte 3 6 (saddr), cy ? (saddr) + byte + cy a, r 2 4 a, cy ? a + r + cy a, saddr 2 4 a, cy ? a + (saddr) + cy a, !addr16 3 8 a, cy ? a + (add16) + cy a, [hl] 1 6 a, cy ? a + (hl) + cy a, [hl + byte] 2 6 a, cy ? a + (hl + byte) + cy sub a, #byte 2 4 a, cy ? a C byte saddr, #byte 3 6 (saddr), cy ? (saddr) C byte a, r 2 4 a, cy ? a C r a, saddr 2 4 a, cy ? a C (saddr) a, !addr16 3 8 a, cy ? a C (addr16) a, [hl] 1 6 a, cy ? a C (hl) a, [hl + byte] 2 6 a, cy ? a C (hl + byte) subc a, #byte 2 4 a, cy ? a C byte C cy saddr, #byte 3 6 (saddr), cy ? (saddr) C byte C cy a, r 2 4 a, cy ? a C r C cy a, saddr 2 4 a, cy ? a C (saddr) C cy a, !addr16 3 8 a, cy ? a C (addr16) C cy a, [hl] 1 6 a, cy ? a C (hl) C cy a, [hl + byte] 2 6 a, cy ? a C (hl + byte) C cy and a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) a, [hl + byte] 2 6 a ? a (hl + byte) remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc).
m pd789011, 789012 22 mnemonic operand bytes clock operation flags zaccy or a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) a, [hl + byte] 2 6 a ? a (hl + byte) xor a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) a, [hl + byte] 2 6 a ? a (hl + byte) cmp a, #byte 2 4 a C byte saddr, #byte 3 6 (saddr) C byte a, r 2 4 a C r a, saddr 2 4 a C (saddr) a, !addr16 3 8 a C (addr16) a, [hl] 1 6 a C (hl) a, [hl + byte] 2 6 a C (hl + byte) addw ax, #word 3 6 ax, cy ? ax + word subw ax, #word 3 6 ax, cy ? ax C word cmpw ax, #word 3 6 ax C word inc r 2 4 r ? r + 1 saddr 2 4 (saddr) ? (saddr) + 1 dec r 2 4 r ? r C 1 saddr 2 4 (saddr) ? (saddr) C 1 incw rp 1 4 rp ? rp + 1 decw rp 1 4 rp ? rp C 1 ror a, 1 1 2 (cy, a 7 ? a 0 , a mC1 ? a m ) 1 rol a, 1 1 2 (cy, a 0 ? a 7 , a m+1 ? a m ) 1 rorc a, 1 1 2 (cy ? a 0 , a 7 ? cy, a mC1 ? a m ) 1 rolc a, 1 1 2 (cy ? a 7 , a 0 ? cy, a m+1 ? a m ) 1 remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc).
m pd789011, 789012 23 mnemonic operand bytes clock operation flags zaccy set1 saddr. bit 3 6 (saddr. bit) ? 1 sfr. bit 3 6 sfr. bit ? 1 a. bit 2 4 a. bit ? 1 psw. bit 3 6 psw. bit ? 1 [hl]. bit 2 10 (hl). bit ? 1 clr1 saddr. bit 3 6 (saddr. bit) ? 0 sfr. bit 3 6 sfr. bit ? 0 a. bit 2 4 a. bit ? 0 psw. bit 3 6 psw. bit ? 0 [hl]. bit 2 10 (hl). bit ? 0 set1 cy 1 2 cy ? 11 clr1 cy 1 2 cy ? 00 not1 cy 1 2 cy ? cy call !addr16 3 6 (spC1) ? (pc + 3) h , (sp C 2) ? (pc + 3) l , pc ? addr16, sp ? sp C 2 callt [addr5] 1 8 (spC1) ? (pc + 1) h , (sp C 2) ? (pc + 1) l , pc h ? (00000000, addr5 + 1), pc l ? (00000000, addr5), sp ? sp C 2 ret 1 6 pc h ? (sp + 1), pc l ? (sp), sp ? sp + 2 reti 1 8 pc h ? (sp + 1), pc l ? (sp), r r r psw ? (sp + 2), sp ? sp + 3, nmis ? 0 push psw 1 2 (sp C 1) ? psw, sp ? sp C 1 rp 1 4 (sp C 1) ? rp h , (sp C 2) ? rp l , sp ? sp C 2 pop psw 1 4 psw ? (sp), sp ? sp + 1 r r r rp 1 6 rp h ? (sp + 1), rp l ? (sp), sp ? sp + 2 movw sp, ax 2 8 sp ? ax ax, sp 2 6 ax ? sp br !addr16 3 6 pc ? addr16 $addr16 2 6 pc ? pc + 2 + jdisp8 ax 1 6 pc h ? a, pc l ? x remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc).
m pd789011, 789012 24 mnemonic operand bytes clock operation flags zaccy bc $saddr16 2 6 pc ? pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 pc ? pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 pc ? pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 pc ? pc + 2 + jdisp8 if z = 0 bt saddr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr. bit) = 1 sfr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr. bit = 1 a. bit, $addr16 3 8 pc ? pc + 3 + jdisp8 if a. bit = 1 psw. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if psw. bit = 1 bf saddr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr. bit) = 0 sfr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr. bit = 0 a. bit, $addr16 3 8 pc ? pc + 3 + jdisp8 if a. bit = 0 psw. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if psw. bit = 0 dbnz b, $addr16 2 6 b ? b C 1, then pc ? pc + 2 + jdisp8 if b 1 0 c, $addr16 2 6 c ? c C 1, then pc ? pc + 2 + jdisp8 if c 1 0 saddr, $addr16 3 8 (saddr) ? (saddr) C 1, then pc ? pc + 3 + jdisp8 if (saddr) 1 0 nop 1 2 no operation ei 3 6 ie ? 1 (enable interrupt) di 3 6 ie ? 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc).
m pd789011, 789012 25 10. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol test conditions rating unit supply voltages v dd C0.3 to + 7.0 v input voltage v i C0.3 to v dd + 0.3 v output voltage v o C0.3 to v dd + 0.3 v output current, high i oh note 1 pin peak value C10 ma r.m.s. C5 ma total of all pins peak value C30 ma r.m.s. C15 ma output current, low i ol note 1 pin peak value 30 ma r.m.s. 15 ma total of all pins peak value 160 ma r.m.s. 80 ma operating ambient temperature t a C40 to +85 c storage temperature t stg C65 to +150 c note the r.m.s. should be calculated as follows : [r.m.s.] = [peak value] duty caution product quality may suffer if the absolute maximum rating is exceeded for even single parameter or even momentarily. that is, the absolute maximum ratings are the rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. remark the characteristics of an alternate function pin and a port pin are the same unless specified otherwise. capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol test condition min. typ. max. unit input capacitance c in f = 1 mhz, unmeasured pins returned to 0 v 15 pf output capacitance c out 15 pf i/o capacitance c io 15 pf ?
m pd789011, 789012 26 main system clock oscillation circuit characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter test condition min. typ. max. unit ceramic oscillator frequency (fx) note 1 v dd = oscillating voltage 1.0 5.0 mhz resonator range oscillation stabilization after v dd reaches oscillator 4 ms time note 2 voltage range min. crystal oscillating frequency (fx) note 1 1.0 5.0 mhz resonator oscillation stabilization v dd = 4.5 to 5.5 v 10 ms time note 2 30 external x1 input frequency (fx) note 1 1.0 5.0 mhz clock x1 input high/low level width 100 500 ns (t xh , t xl ) notes 1. indicates only oscillation circuit characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. caution when using the main system clock oscillator, wiring the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. wiring should be as short as possible. wiring should not cross other signal lines. wiring should not be placed close to a varying higher current. the potential of the oscillator capacitor ground should be the same as v ss . do not ground wiring to a ground pattern in which a high current flows. do not fetch a signal from the oscillator. x1 x2 x1 x2 c1 c2 x1 x2 c1 c2
m pd789011, 789012 27 recommended oscillating circuit constants ceramic resonator (t a = C40 to +85 c) c1 c2 min. max. murata mfg. csb1000j note 1.00 100 100 1.9 5.5 rd = 1.0 k w co., ltd. csa2.00mg040 2.00 100 100 2.1 5.5 cst2.00mg040 C C product containing capacitor csa4.19mg 4.19 30 30 1.8 5.5 cst4.19mgw C C product containing capacitor csa5.00mg 5.00 30 30 2.2 5.5 cst5.00mgw C C product containing capacitor csa5.00mgu 30 30 2.0 5.5 cst5.00mgwu C C product containing capacitor note if the ceramic resonator is the csb1000j (1.0 mhz) by murata mfg. co., ltd., the limiting resistor (rd = 1.0 k w ) is needed (see the following figure). if another recommended oscillator is used, the limiting resistor is not needed. manufacturer product name frequency (mhz) recommended oscillation circuit constant (pf) oscillation voltage range (v dd ) remarks caution the oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee the accuracy of the oscillation frequency. if the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. for this, it is necessary to directly contact manufacturer of the resonator being used. x1 x2 csb1000j rd c2 c1
m pd789011, 789012 28 dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit output current, low i ol 1 pin 15 ma total of all of the pins 80 ma input voltage, high v ih1 p00 to p07, p10 to p17, v dd = 2.7 to 5.5 v 0.7 v dd v dd v p20 to p22, p30 to p32 0.9 v dd v dd v v ih2 intp0 to intp2, si0, rxd, v dd = 2.7 to 5.5 v 0.8 v dd v dd v asck, sck0, ti0, ti1, reset 0.9 v dd v dd v v ih3 x1, x2 v dd C 0.1 v dd v input voltage, low v il1 p00 to p07, p10 to p17, v dd = 2.7 to 5.5 v 0 0.3 v dd v p20 to p22, p30 to p32 0 0.1 v dd v v il2 intp0 to intp2, si0, r x d, v dd = 2.7 to 5.5 v 0 0.2 v dd v asck, sck0, ti0, ti1, reset 0 0.1 v dd v v il3 x1, x2 0 0.1 v output voltage, high v oh v dd = 4.5 to 5.5 v, i oh = C1 ma v dd C 1.0 v i oh = C100 m a v dd C 0.5 v output voltage, low v ol v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v i ol = 400 m a 0.5 v input leakage current, high i lih1 v in = v dd pins other than 3 m a x1 and x2 i lih2 x1, x2 20 m a input leakage current, low i lil1 v in = 0 v pins other than C3 m a x1 and x2 i lil2 x1, x2 C20 m a output leakage current, high i loh v out = v dd 3 m a output leakage current, low i lol v out = 0 v C3 m a remark the characteristics of an alternate function pin and a port pin are the same unless specified otherwise.
m pd789011, 789012 29 dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit software pull-up resistor r v in = 0 v 50 100 200 k w supply current note 1 i dd1 5.0 mhz v dd = 5.0 v 10% note 2 1.1 2.0 ma crystal oscillation operation v dd = 3.0 v 10% note 3 0.3 0.45 ma i dd2 5.0 mhz v dd = 5.0 v 10% note 2 0.6 0.85 ma crystal oscillation halt mode v dd = 3.0 v 10% note 3 0.2 0.35 ma i dd3 stop mode v dd = 5.0 v 10% 0.1 10 m a v dd = 3.0 v 0.05 5 m a 10% t a = 25 c 0.05 3 v dd = 2.0 v 10% 0.05 3 m a notes 1. this does not include the port current (containing the current flowing through the on-chip pull-up resistor). 2. when operating at high-speed mode (when the processor clock control register (pcc) is set to 00h) 3. when operating at low-speed mode (when pcc is set to 02h) remark the characteristics of an alternate function pin and a port pin are the same unless specified otherwise.
m pd789011, 789012 30 ac characteristics (1) basic operation (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit cycle time (min. t cy v dd = 2.7 to 5.5 v 0.4 8 m s instruction execution time) 1.6 8 m s ti0, ti1 inputs t tih ,v dd = 2.7 to 5.5 v 0.1 m s high/low level widths t til 1.8 m s ti0, ti1 input frequency f ti v dd = 2.7 to 5.5 v 0 4 mhz 0 275 khz interrupt request input t inth , intp0 to intp2 v dd = 2.7 to 5.5 v 10 m s high/low level widths t intl 20 m s reset t rsl v dd = 2.7 to 5.5 v 10 m s low level width 20 m s remark the shaded area indicates the operation guaranteed range of the m pd78p9014. 60 10 8.0 2.0 1.6 1.0 0.5 0.4 0.1 t cy vs v dd (main system clock) cycle time t cy ( s) m 1 1.82 2.73 4 4.5 5 5.5 6 supply voltage v dd (v) operation guaranteed range
m pd789011, 789012 31 (2) serial interface channel 0 (t a = C40 to +85 , v dd = 1.8 to 5.5 v) (i) 3-wire serial i/o mode (sck0 : internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy1 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck0 high/low level t kh1, v dd = 2.7 to 5.5 v t kcy1 /2 C 50 ns widths t kl1 t kcy1 /2 C 150 ns si0 setup time t sik1 v dd = 2.7 to 5.5 v 150 ns (on sck0 - ) 500 ns si0 hold time t ksi1 v dd = 2.7 to 5.5 v 400 ns (on sck0 - ) 600 ns sck0 ? so0 t kso1 r = 1k w ,v dd = 2.7 to 5.5 v 0 250 ns output delay time c = 100 pf note 0 1000 ns note r and c are the load resistance and load capacitance of the so0 output line. (ii) 3-wire serial i/o mode (sck0 : external clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy2 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck0 high/low level t kh2, v dd = 2.7 to 5.5 v 400 ns widths t kl2 1600 ns si0 setup time t sik2 v dd = 2.7 to 5.5 v 100 ns (on sck0 - ) 150 ns si0 hold time t ksi2 v dd = 2.7 to 5.5 v 400 ns (on sck0 - ) 600 ns sck0 ? so0 t kso2 r = 1k w ,v dd = 2.7 to 5.5 v 0 300 ns output delay time c = 100 pf note 0 1000 ns note r and c are the load resistance and load capacitance of the so0 output line. (iii) uart mode (dedicated baud rate generator output) parameter symbol test conditions min. typ. max. unit transfer rate v dd = 2.7 to 5.5 v 78125 bps 19531 bps
m pd789011, 789012 32 (iv) uart mode (external clock input) parameter symbol test conditions min. typ. max. unit asck cycle time t kcy3 v dd = 2.7 to 5.5 v 800 ns 3200 ns asck high and low level t kh3, v dd = 2.7 to 5.5 v 400 ns widths t kl3 1600 ns transfer rate v dd = 2.7 to 5.5 v 39063 bps 9766 bps asck rise and fall times t r , t f 1 m s
m pd789011, 789012 33 ac timing test points (except for x1 input) clock timing ti timing test points 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd x1 input v ih3 (min.) v il3 (max.) 1/f x t xl t xh ti0, ti1 t til0, t til1 t tih0, t tih1
m pd789011, 789012 34 serial transfer timing 3-wire serial i/o mode: uart mode (external clock input): output data t kcym t klm t khm t sikm t ksim input data t ksom sck0 si0 so0 asck t r t kcy3 t kl3 t kh3 t f
m pd789011, 789012 35 data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85 c) parameter symbol test conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v release signal set time t srel 00 m s oscillation stabilization wait time t wait release by reset 2 15 /f x ms release by interrupt request note ms note in combination with bits 0 to 2 (osts0 to osts2) of oscillation stabilization time select register (osts), selection of 2 12 /f x , 2 15 /f x , or 2 17 /f x is possible. remark f x : main system clock oscillation frequency data retention timing (stop mode release by reset) data retention timing (standby release signal: stop release by interrupt request signal) stop mode internal reset operation halt mode operating mode data retention mode stop instruction execution v dd reset v dddr t srel t wait stop mode data retention mode halt mode operating mode v dddr t srel t wait stop instruction execution standby release signal (interrupt request) v dd
m pd789011, 789012 36 interrupt request input timing reset input timing intp0 to intp2 t intl t inth reset t rsl
m pd789011, 789012 37 11. package drawings 28pin plastic shrink dip (400 mil) item millimeters inches notes 1) each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. n 0.17 0.007 a 28.46 max. 1.121 max. b 2.67 max. 0.106 max. f 0.9 min. 0.035 min. g 3.2?.3 0.126?.012 j 5.08 max. 0.200 max. k 10.16 (t.p.) 0.400 (t.p.) c 1.778 (t.p.) 0.070 (t.p.) d 0.50?.10 0.020 +0.004 ?.005 h 0.51 min. 0.020 min. i 4.31 max. 0.170 max. l 8.6 0.339 m 0.25 0.010 +0.004 ?.003 +0.10 ?.05 m r m i h g f dn c b k p28c-70-400a-1 r 0~15 0~15 2) ltem "k" to center of leads when formed parallel. 1 14 28 15 a j l
m pd789011, 789012 38 28 pin plastic sop (375 mil) item millimeters inches a b c e f g h i j 18.07 max. 1.27 (t.p.) 2.9 max. 2.50 10.3?.3 0.78 max. 0.12 1.6 7.2 m 0.1?.1 n 0.712 max. 0.031 max. 0.004?.004 0.115 max. 0.098 0.406 0.283 0.063 0.005 0.050 (t.p.) p28gm-50-375b-3 p3 3 +7 a g note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. d 0.40 0.016 +0.10 ?.05 k 0.15 0.006 +0.10 ?.05 l 0.8?.2 0.031 0.15 ? +7 ? 0.006 +0.009 ?.008 +0.004 ?.002 +0.004 ?.003 +0.012 ?.013 p detail of lead end 114 28 15 m f e c dm b l k h i j n
m pd789011, 789012 39 12. recommended soldering conditions the m pd789011 and 789012 should be soldered and mounted under the conditions recommended in the table below. for detail of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e). for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 12-1. soldering conditions for surface-mount devices m pd789011gt- : 28-pin plastic sop (375 mil) m pd789012gt- : 28-pin plastic sop (375 mil) recommended soldering method soldering conditions condition code infrared reflow package peak temperature: 235 c, duration: 30 seconds max. (at 210 c or above) number of times: two times max. vps package peak temperature: 215 c, duration: 40 seconds max. (at 200 c or above) number of times: two times max. wave soldering soldering bath temperature: 260 c max., duration: 10 seconds max., number of times: once preheating temperature: 120 c max.(package surface temperature) partial heating pin temperature: 300 c max., duration: 3 seconds max. (per device side) note the storage conditions are 25 c and 65% rh for the number of storage days after opening the seal of the dry pack. caution using more than one soldering method should be avoided. (except in the case of partial heating) table 12-2. soldering conditions for through-hole devices m pd789011ct- : 28-pin plastic shrink dip (400 mil) m pd789012ct- : 28-pin plastic shrink dip (400 mil) soldering method soldering conditions wave soldering (pin only) solder bath temperature: 260 c max., duration: 10 seconds max. partial heating pin temperature: 300 c max., duration: 3 seconds max.(per pin) caution wave soldering is only for the lead part in order that jet solder cannot contact with the chip directly. ir35-00-2 vp15-00-2 ws60-00-1
m pd789011, 789012 40 appendix a. development tools the following development tools are available for the development of systems that employ the m pd789011 and 789012. language processing software ra78k0s notes 1, 2, 3 78k/0s series common assembler package cc78k0s notes 1, 2, 3 78k/0s series common c compiler package df789014 notes 1, 2, 3 m pd789014 subseries common device file cc78k0s-l notes 1, 2, 3, 5 78k/0s series common c compiler library source file prom writing tools pg-1500 prom programmer pa-78p9014gt prom programmer adapter connected to pg-1500 pg-1500 controller pg-1500 control program debugging tools ie-78k0s-ns note 5 in-circuit emulator common to 78k/0s series ie-70000-98-if-b note 5 interface adapter when pc-9800 series (except for notebooks) is used as host machine of ie-78k0s-ns. ie-70000-98n-if note 5 interface adapter and cable when pc-9800 series notebook is used as host machine of ie- 78k0s-ns. ie-70000-pc-if-b note 5 interface adapter when ibm pc/at tm or its compatibles is used as host machine of ie- 78k0s-ns. ie-789014-ns-em1 note 5 emulation board for m pd789014 subseries np-28ct note 4 emulation probe for 28-pin plastic shrink dip np-28gt note 4 emulation probe for 28-pin plastic sop sm78k0s notes 1, 2, 3 system simulator common to 78k/0s series df789014 notes 1, 2, 3 device file in common with m pd7890914 subseries real-time os mx78k0s notes 1, 2 78k/0s series os notes 1. pc-9800 series (ms-dos tm + windows tm ) based 2. ibm pc/at and compatibles (pc dos tm /ibm dos tm /ms-dos + windows) based 3. hp9000 series 700 tm (hp-ux tm ) based, sparcstation tm (sunos tm ) based, news tm (news- os tm ) based 4. this is a product of naito densei machida seisakusho co., ltd. (044-822-3813). to purchase, contact naito densei machida seisakusho co., ltd. 5. under development remark ra78k0s, cc78k0s, and sm78k0s are used with df789014.
m pd789011, 789012 41 appendix b. related documents documents related to device document name document no. english japanese m pd78p9014 data sheet u10912e u10912j m pd789011, 789012 data sheet this document u11095j m pd789014 subseries users manual u11187e u11187j 78k/0s series users manual instruction u11047e u11047j 78k/0s series instruction summary sheet to be prepared 78k/0s series instruction set to be prepared development tool documents (users manual) document name document no. english japanese ra78k0s assembler package operation u11622e u11622j assembly language u11599e u11599j structured assembly language u11623e u11623j cc78k/0s c compiler operation u11816e u11816j language u11817e u11817j sm78k0s system simulator windows based reference u11489e u11489j sm78k series system simulator external components user-open u10092e u10092j interface specification pg-1500 u11940e u11940j documents related to embedded software (users manual) document name document no. english japanese 78k/0s series os mx78k0s to be prepared to be prepared other related documents document name document no. english japanese ic package manual c10943x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor devices c11531e c11531j nec semiconductor device reliability/quality control system c10983e c10983j guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e c11892j guide to quality assurance for semiconductor devices mei-1202 c11893j microcontroller related product guide third party c11416j caution the documents listed above are subject to change without notice. be sure to use the latest documents for designing, etc.
m pd789011, 789012 42 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m pd789011, 789012 43 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j97. 8
m pd789011, 789012 1 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 eeprom is a trademark of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation.

▲Up To Search▲

Price & Availability of UPD789012CT-XXX

	To Download UPD789012CT-XXX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .