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| 32 bit risc microcontroller tx03 series TMPM333FDFG/fyfg/fwfg
? 2010 toshiba corporation all rights reserved TMPM333FDFG/fyfg/fwfg ************************************************************************************************************************* arm, arm powered, amba, adk, arm9tdmi, tdmi, primecell, realview, thumb, cortex, coresight, arm9, arm926ej-s, embedded trace macrocell, etm, ahb, apb, and keil are registered trademarks or trademarks of arm limited in the eu and other countries. ************************************************************************************************************************* r introduction: notes on the description of sfr (special function register) under this specifica- tion an sfr (special function register) is a control register for periperal circuits (ip). the sfr addressses of ips are described in the chapter on memory map, and the details of sfr are given in the chapter of each ip. definition of sfr used in this specification is in accordance with the following rules. a. sfr table of each ip as an example ? ? ? ? 1.2.2 samcr(control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - mode after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol mode tdata after reset 0 0 0 1 0 0 0 0 bit bit symbol type function 31-10 ? r "0" can be read. 9-7 mode[2:0] r/w operation mode settings 000 : sample mode 0 001 : sample mode 1 010 : sample mode 2 011 : sample mode 3 the settings other than those above: reserved 6-0 tdata[6:0] w transmitted data note: the type is divided into three as shown below. r / w read write r read w write c. data descriptopn meanings of symbols used in the sfr description are as shown below. x:channel numbers/ports n,m:bit numbers d. register descriptoption registers are described as shown below. register name TMPM333FDFG/fyfg/fwfg revision history date revision comment 2010/6/1 1 first release 2010/10/6 2 contents revised table of contents introduction: notes on the description of sfr (special function register) under this specification TMPM333FDFG/fyfg/fwfg 1.1 features......................................................................................................................................1 1.2 block diagram........................................................................................................................... 3 1.3 pin layout (top view)............................................................................................................... 4 1.4 pin names and functions........................................................................................................... 5 1.4.1 sorted by pin........................................................................................................................................................................5 1.4.2 sorted by port.................................................................................................................................................................... 11 1.5 pin numbers and power supply pins...................................................................................... 16 2. processor core 2.1 information on the processor core........................................................................................... 17 2.2 configurable options............................................................................................................... 17 2.3 exceptions/ interruptions ......................................................................................................... 17 2.3.1 number of interrupt inputs................................................................................................................................................ 17 2.3.2 number of priority level interrupt bits............................................................................................................................ 18 2.3.3 systick.............................................................................................................................................................................. 18 2.3.4 sysresetreq................................................................................................................................................................ 18 2.3.5 lockup........................................................................................................................................................................... 18 2.3.6 auxiliary fault status register........................................................................................................................................... 18 2.4 events...................................................................................................................................... 19 2.5 power management................................................................................................................. 19 2.6 exclusive access...................................................................................................................... 19 3. debug interface 3.1 specification overview........................................................................................................... 21 3.2 swj-dp................................................................................................................................... 21 3.3 etm......................................................................................................................................... 21 3.4 pin functions........................................................................................................................... 22 3.5 peripheral functions in halt mode.......................................................................................... 23 3.6 reset vector break.................................................................................................................. 23 3.7 connection with a debug tool................................................................................................ 24 3.7.1 about connection with debug tool..................................................................................................................................... 24 3.7.2 important points of using debug interface pins used as general-purpose ports................................................................. 24 4. memory map i 4.1 memory map............................................................................................................................ 25 4.1.1 memory map of the TMPM333FDFG ............................................................................................................................... 26 4.1.2 memory map of tmpm333fyfg.................................................................................................................................... 27 4.1.3 memory map of tmpm333fwfg................................................................................................................................... 28 4.2 sfr area detail.........................................................................................................................29 5. reset 5.1 cold reset................................................................................................................................. 31 5.2 warm reset............................................................................................................................... 32 5.2.1 reset period....................................................................................................................................................................... 32 5.2.2 after reset.......................................................................................................................................................................... 32 6. clock/mode control 6.1 features....................................................................................................................................33 6.2 registers.................................................................................................................................. 34 6.2.1 register list.......................................................................................................................................................................34 6.2.2 cgsyscr (system control register)................................................................................................................................ 35 6.2.3 cgosccr (oscillation control register).......................................................................................................................... 36 6.2.4 cgstbycr (standby control register)............................................................................................................................ 37 6.2.5 cgpllsel (pll selection register)...............................................................................................................................38 6.2.6 cgcksel (system clock selection register).................................................................................................................... 39 6.3 clock control........................................................................................................................... 40 6.3.1 clock system block diagram............................................................................................................................................ 40 6.3.2 initial values after reset .................................................................................................................................................... 40 6.3.3 clock system diagram.......................................................................................................................................................41 6.3.4 clock multiplication circuit (pll)................................................................................................................................... 42 6.3.5 warm-up function.............................................................................................................................................................. 42 6.3.6 system clock..................................................................................................................................................................... 44 6.3.6.1 high speed clock 6.3.6.2 low speed clock 6.3.7 prescaler clock control..................................................................................................................................................... 44 6.3.8 system clock pin output function................................................................................................................................... 45 6.4 modes and mode transitions................................................................................................. 46 6.4.1 mode transitions............................................................................................................................................................... 46 6.5 operation mode....................................................................................................................... 47 6.5.1 normal mode................................................................................................................................................................ 47 6.5.2 slow mode...................................................................................................................................................................... 47 6.6 low power consumption modes............................................................................................ 48 6.6.1 idle mode........................................................................................................................................................................ 48 6.6.2 sleep mode......................................................................................................................................................................48 6.6.3 stop mode ........................................................................................................................................................................49 6.6.4 low power consumption mode setting............................................................................................................................ 49 6.6.5 operational status in each mode...................................................................................................................................... 50 6.6.6 releasing the low power consumption mode................................................................................................................. 51 6.6.7 warm-up............................................................................................................................................................................52 6.6.8 clock operations in mode transition............................................................................................................................... 53 6.6.8.1 transition of operation modes: normal stop normal 6.6.8.2 transition of operation modes: normal sleep normal 6.6.8.3 transition of operation modes: slow stop slow 6.6.8.4 transition of operation modes: slow sleep slow 7. exceptions 7.1 overview.................................................................................................................................. 55 7.1.1 exception types ................................................................................................................................................................ 55 7.1.2 handling flowchart........................................................................................................................................................... 56 ii 7.1.2.1 exception request and detection 7.1.2.2 exception handling and branch to the interrupt service routine (pre-emption) 7.1.2.3 executing an isr 7.1.2.4 exception exit 7.2 reset exceptions......................................................................................................................61 7.3 non-maskable interrupts (nmi).............................................................................................. 62 7.4 systick.................................................................................................................................... 62 7.5 interrupts..................................................................................................................................63 7.5.1 interrupt sources................................................................................................................................................................63 7.5.1.1 interrupt route 7.5.1.2 generation 7.5.1.3 transmission 7.5.1.4 precautions when using external interrupt pins 7.5.1.5 list of interrupt sources 7.5.1.6 active level 7.5.2 interrupt handling.............................................................................................................................................................. 67 7.5.2.1 flowchart 7.5.2.2 preparation 7.5.2.3 detection by clock generator 7.5.2.4 detection by cpu 7.5.2.5 cpu processing 7.5.2.6 interrupt service routine (isr) 7.6 exception/interrupt-related registers..................................................................................... 72 7.6.1 register list.......................................................................................................................................................................72 7.6.2 nvic registers ..................................................................................................................................................................73 7.6.2.1 systick control and status register 7.6.2.2 systick reload value register 7.6.2.3 systick current value register 7.6.2.4 systick calibration value register 7.6.2.5 interrupt set-enable register 1 7.6.2.6 interrupt set-enable register 2 7.6.2.7 interrupt clear-enable register 1 7.6.2.8 interrupt clear-enable register 2 7.6.2.9 interrupt set-pending register 1 7.6.2.10 interrupt set-pending register 2 7.6.2.11 interrupt clear-pending register 1 7.6.2.12 interrupt clear-pending register 2 7.6.2.13 interrupt priority register 7.6.2.14 vector table offset register 7.6.2.15 application interrupt and reset control register 7.6.2.16 system handler priority register 7.6.2.17 system handler control and state register 7.6.3 clock generator registers................................................................................................................................................... 91 7.6.3.1 cgimcga(cg interrupt mode control register a) 7.6.3.2 cgimcgb(cg interrupt mode control register b) 7.6.3.3 cgimcgc(cg interrupt mode control register c) 7.6.3.4 cgicrcg(cg interrupt request clear register) 7.6.3.5 cgnmiflg(nmi flag register) 7.6.3.6 cgrstflg (reset flag register) 8. input/output ports 8.1 port functions........................................................................................................................ 101 8.1.1 function lists .................................................................................................................................................................. 101 8.1.2 port registers outline...................................................................................................................................................... 104 8.1.3 port states in stop mode............................................................................................................................................... 105 8.1.4 precautions for mode transition between stop and sleep.........................................................................................105 8.2 port functions......................................................................................................................... 106 8.2.1 port a (pa0 to pa7)........................................................................................................................................................ 106 8.2.1.1 port a circuit type 8.2.1.2 port a register 8.2.1.3 padata (port a data register) 8.2.1.4 pacr (port a output control register) 8.2.1.5 pafr1 (port a function register 1) 8.2.1.6 papup (port a pull-up control register) 8.2.1.7 papdn (port a pull-down control register) 8.2.1.8 paie (port a input control register) 8.2.2 port b (pb0 to pb7) .........................................................................................................................................................111 8.2.2.1 port b circuit type iii 8.2.2.2 port b register 8.2.2.3 pbdata (port b data register) 8.2.2.4 pbcr (port b output control register) 8.2.2.5 pbfr1 (port b function register 1) 8.2.2.6 pbpup (port b pull-up control register) 8.2.2.7 pbie (port b input control register) 8.2.3 port c (pc0 to pc3) .........................................................................................................................................................115 8.2.3.1 port c circuit type 8.2.3.2 port c register 8.2.3.3 pcdata (port c data register) 8.2.3.4 pcpup (port c pull-up control register) 8.2.3.5 pcie (port c input control register) 8.2.4 port d (pd0 to pd7)........................................................................................................................................................ 118 8.2.4.1 port d circuit type 8.2.4.2 port d register 8.2.4.3 pddata (port d data register) 8.2.4.4 pdfr1 (port d function register 1) 8.2.4.5 pdpup (port d pull-up control register) 8.2.4.6 pdie (port d input control register) 8.2.5 port e (pe0 to pe6)......................................................................................................................................................... 121 8.2.5.1 port e circuit type 8.2.5.2 port e register 8.2.5.3 pedata (port e data register) 8.2.5.4 pecr (port e output control register) 8.2.5.5 pefr1(port e function register 1) 8.2.5.6 pefr2(port e function register 2) 8.2.5.7 peod (port e open drain control register) 8.2.5.8 pepup (port e pull-up control register) 8.2.5.9 peie (port e input control register) 8.2.6 port f (pf0 to pf7).......................................................................................................................................................... 126 8.2.6.1 port f circuit type 8.2.6.2 port f register 8.2.6.3 pfdata (port f data register) 8.2.6.4 pfcr (port f output control register) 8.2.6.5 pffr1(port f function register 1) 8.2.6.6 pffr2(port f function register 2) 8.2.6.7 pfod (port f open drain control register) 8.2.6.8 pfpup (port f pull-up control register) 8.2.6.9 pfie (port f input control register) 8.2.7 port g (pg0 to pg7)........................................................................................................................................................ 131 8.2.7.1 port g circuit type 8.2.7.2 port g register 8.2.7.3 pgdata (port g data register) 8.2.7.4 pgcr (port g output control register) 8.2.7.5 pgfr1(port g function register 1) 8.2.7.6 pgod (port g open drain control register) 8.2.7.7 pgpup (port g pull-up control register) 8.2.7.8 pgie (port g input control register) 8.2.8 port h (ph0 to ph7)........................................................................................................................................................ 136 8.2.8.1 port h circuit type 8.2.8.2 port h register 8.2.8.3 phdata (port h data register) 8.2.8.4 phcr (port h output control register) 8.2.8.5 phfr1(port h function register 1) 8.2.8.6 phpup (port h pull-up control register) 8.2.8.7 phie (port h input control register) 8.2.9 port i (pi0 to pi7)............................................................................................................................................................. 140 8.2.9.1 port i circuit type 8.2.9.2 port i register 8.2.9.3 pidata(port i data register) 8.2.9.4 picr (port i output control register) 8.2.9.5 pifr1(port i function register 1) 8.2.9.6 pipup (port i pull-up control register) 8.2.9.7 piie (port i input control register) 8.2.10 port j (pj0 to pj7).......................................................................................................................................................... 144 8.2.10.1 port j circuit type 8.2.10.2 port j register 8.2.10.3 pjdata (port j data register) 8.2.10.4 pjcr (port j output control register) 8.2.10.5 pjfr1(port j function register 1) 8.2.10.6 pjpup (port j pull-up control register) 8.2.10.7 pjie (port j input control register) 8.2.11 port k (pk0 to pk2)...................................................................................................................................................... 148 8.2.11.1 port k circuit type 8.2.11.2 port k register 8.2.11.3 pkdata(port k data register) iv 8.2.11.4 pkcr (port k output control register) 8.2.11.5 pkfr1(port k function register 1) 8.2.11.6 pkfr2(port k function register 2) 8.2.11.7 pkpup (port k pull-up control register) 8.2.11.8 pkie (port k input control register) 8.3 block diagrams of ports........................................................................................................153 8.3.1 port types........................................................................................................................................................................ 153 8.3.2 type t1............................................................................................................................................................................154 8.3.3 type t2............................................................................................................................................................................155 8.3.4 type t3............................................................................................................................................................................156 8.3.5 type t4............................................................................................................................................................................157 8.3.6 type5 t5..........................................................................................................................................................................158 8.3.7 type t6............................................................................................................................................................................159 8.3.8 type t7............................................................................................................................................................................160 8.3.9 type t8............................................................................................................................................................................161 8.3.10 type t9..........................................................................................................................................................................162 8.3.11 type t10........................................................................................................................................................................163 8.3.12 type t11........................................................................................................................................................................164 8.3.13 type t12........................................................................................................................................................................165 8.3.14 type t13........................................................................................................................................................................166 8.3.15 type t14........................................................................................................................................................................167 8.3.16 type t15........................................................................................................................................................................168 8.3.17 type t16........................................................................................................................................................................169 8.3.18 type t17........................................................................................................................................................................170 8.3.19 type t18........................................................................................................................................................................171 8.4 appendix (port setting list).................................................................................................. 172 8.4.1 port a setting................................................................................................................................................................... 172 8.4.2 port b setting...................................................................................................................................................................173 8.4.3 port c setting...................................................................................................................................................................174 8.4.4 port d setting................................................................................................................................................................... 174 8.4.5 port e setting................................................................................................................................................................... 175 8.4.6 port f setting................................................................................................................................................................... 176 8.4.7 port g setting................................................................................................................................................................... 177 8.4.8 port h setting................................................................................................................................................................... 178 8.4.9 port i setting.................................................................................................................................................................... 179 8.4.10 port j setting.................................................................................................................................................................. 180 8.4.11 port k setting................................................................................................................................................................. 181 9. 16-bit timer/event counters(tmrb) 9.1 outline................................................................................................................................... 183 9.2 differences in the specifications........................................................................................... 184 9.3 configuration......................................................................................................................... 185 9.4 registers................................................................................................................................ 186 9.4.1 register list according to channel.................................................................................................................................... 186 9.4.2 tbxen (enable register)................................................................................................................................................. 187 9.4.3 tbxrun(run register) ..................................................................................................................................................188 9.4.4 tbxcr(control register)................................................................................................................................................. 189 9.4.5 tbxmod(mode register) ................................................................................................................................................ 190 9.4.6 tbxffcr(flip-flop control register).............................................................................................................................. 191 9.4.7 tbxst(status register).................................................................................................................................................... 192 9.4.8 tbxim(interrupt mask register)...................................................................................................................................... 193 9.4.9 tbxuc(up counter capture register).............................................................................................................................. 193 9.4.10 tbxrg0(timer register 0)............................................................................................................................................ 194 9.4.11 tbxrg1(timer register 1)............................................................................................................................................ 194 9.4.12 tbxcp0(capture register 0).......................................................................................................................................... 195 9.4.13 tbxcp1(capture register 1).......................................................................................................................................... 195 9.5 description of operations for each circuit........................................................................... 196 9.5.1 prescaler...........................................................................................................................................................................196 9.5.2 up-counter (uc).............................................................................................................................................................. 200 9.5.3 timer registers (tbxrg0, tbxrg1).............................................................................................................................. 200 9.5.4 capture............................................................................................................................................................................. 201 9.5.5 capture registers (tbxcp0, tbxcp1)............................................................................................................................. 201 v 9.5.6 up-counter capture register (tbxuc)............................................................................................................................. 201 9.5.7 comparators (cp0, cp1)................................................................................................................................................. 201 9.5.8 timer flip-flop (tbxff0)............................................................................................................................................... 201 9.5.9 capture interrupt (intcapx0, intcapx1)................................................................................................................... 201 9.6 description of operations for each mode............................................................................. 202 9.6.1 16-bit interval timer mode............................................................................................................................................. 202 9.6.2 16-bit event counter mode............................................................................................................................................. 202 9.6.3 16-bit ppg (programmable pulse generation) output mode......................................................................................... 203 9.6.4 timer synchronous mode................................................................................................................................................. 205 9.7 applications using the capture function .............................................................................. 206 9.7.1 one-shot pulse output triggered by an external pulse...................................................................................................... 206 9.7.2 frequency measurement.................................................................................................................................................. 208 9.7.3 pulse width measurement................................................................................................................................................ 209 9.7.4 time difference measurement........................................................................................................................................ 210 10. serial channel (sio/uart) 10.1 overview............................................................................................................................. 211 10.2 difference in the specifications of sio modules ................................................................ 211 10.3 configuration....................................................................................................................... 212 10.4 registers description........................................................................................................... 213 10.4.1 registers list in each channel...................................................................................................................................... 213 10.4.2 scxen (enable register).............................................................................................................................................. 214 10.4.3 scxbuf (buffer register) ............................................................................................................................................ 215 10.4.4 scxcr (control register)............................................................................................................................................. 216 10.4.5 scxmod0 (mode control register 0) ..........................................................................................................................217 10.4.6 scxmod1 (mode control register 1) ..........................................................................................................................218 10.4.7 scxmod2 (mode control register 2) ..........................................................................................................................219 10.4.8 scxbrcr (baud rate generator control register), scxbradd (baud rate generator control register 2).......... 221 10.4.9 scxfcnf ( fifo configuration register) ................................................................................................................... 223 10.4.10 scxrfc (rx fifo configuration register) .............................................................................................................. 224 10.4.11 scxtfc (tx fifo configuration register) (note2)................................................................................................. 225 10.4.12 scxrst (rx fifo status register) ........................................................................................................................... 226 10.4.13 scxtst (tx fifo status register) ............................................................................................................................227 10.5 operation in each mode...................................................................................................... 228 10.6 data format......................................................................................................................... 229 10.6.1 data format list............................................................................................................................................................ 229 10.6.2 parity control................................................................................................................................................................. 230 10.6.2.1 transmission 10.6.2.2 receiving data 10.6.3 stop bit length........................................................................................................................................................... 230 10.7 clock control....................................................................................................................... 231 10.7.1 prescaler......................................................................................................................................................................... 231 10.7.2 serial clock generation circuit..................................................................................................................................... 235 10.7.2.1 baud rate generator 10.7.2.2 clock selection circuit 10.8 transmit/receive buffer and fifo..................................................................................... 239 10.8.1 configuration................................................................................................................................................................. 239 10.8.2 transmit/receive buffer................................................................................................................................................ 239 10.8.3 fifo............................................................................................................................................................................... 239 10.9 status flag........................................................................................................................... 240 10.10 error flag........................................................................................................................... 240 10.10.1 oerr flag................................................................................................................................................................... 240 10.10.2 perr flag................................................................................................................................................................... 241 10.10.3 ferr flag................................................................................................................................................................... 241 10.11 receive.............................................................................................................................. 242 10.11.1 receive counter........................................................................................................................................................... 242 10.11.2 receive control unit................................................................................................................................................... 242 10.11.2.1 i/o interface mode 10.11.2.2 uart mode 10.11.3 receive operation........................................................................................................................................................ 242 vi 10.11.3.1 receive buffer 10.11.3.2 receive fifo operation 10.11.3.3 i/o interface mode with sclk output 10.11.3.4 read received data 10.11.3.5 wake-up function 10.11.3.6 overrun error 10.12 transmission...................................................................................................................... 246 10.12.1 transmission counter..................................................................................................................................................246 10.12.2 transmission control...................................................................................................................................................246 10.12.2.1 i/o interface mode 10.12.2.2 uart mode 10.12.3 transmit operation......................................................................................................................................................246 10.12.3.1 operation of transmission buffer 10.12.3.2 transmit fifo operation 10.12.3.3 i/o interface mode/transmission by sclk output 10.12.3.4 under-run error 10.13 handshake function........................................................................................................... 250 10.14 interrupt/error generation timing.................................................................................... 251 10.14.1 rx interrupts............................................................................................................................................................... 251 10.14.1.1 single buffer / double buffer 10.14.1.2 fifo 10.14.2 tx interrupts................................................................................................................................................................ 252 10.14.2.1 single buffer / double buffer 10.14.2.2 fifo 10.14.3 error generation.......................................................................................................................................................... 253 10.14.3.1 uart mode 10.14.3.2 io interface mode 10.15 software reset................................................................................................................... 253 10.16 operation in each mode.................................................................................................... 254 10.16.1 mode 0 (i/o interface mode)....................................................................................................................................... 254 10.16.1.1 transmitting data 10.16.1.2 receive 10.16.1.3 transmit and receive (full-duplex) 10.16.2 mode 1 (7-bit uart mode)........................................................................................................................................265 10.16.3 mode 2 (8-bit uart mode)........................................................................................................................................265 10.16.4 mode 3 (9-bit uart mode)........................................................................................................................................266 10.16.4.1 wakeup function 10.16.4.2 protocol 11. serial bus interface (i2c/sio) 11.1 configuration....................................................................................................................... 270 11.2 register................................................................................................................................ 271 11.2.1 registers for each channel............................................................................................................................................. 271 11.3 i2c bus mode data format.................................................................................................272 11.4 control registers in the i2c bus mode............................................................................... 273 11.4.1 sbixcr0(control register 0) ......................................................................................................................................... 273 11.4.2 sbixcr1(control register 1)......................................................................................................................................... 274 11.4.3 sbixcr2(control register 2)......................................................................................................................................... 276 11.4.4 sbixsr (status register)............................................................................................................................................... 277 11.4.5 sbixbr0(serial bus interface baud rate register 0)....................................................................................................... 278 11.4.6 sbixdbr (serial bus interface data buffer register)..................................................................................................... 278 11.4.7 sbixi2car (i2cbus address register) .......................................................................................................................... 279 11.5 control in the i2c bus mode............................................................................................... 280 11.5.1 serial clock.................................................................................................................................................................... 280 11.5.1.1 clock source 11.5.1.2 clock synchronization 11.5.2 setting the acknowledgement mode.............................................................................................................................281 11.5.3 setting the number of bits per transfer........................................................................................................................281 11.5.4 slave addressing and address recognition mode........................................................................................................ 281 11.5.5 operating mode.............................................................................................................................................................. 281 11.5.6 configuring the sbi as a transmitter or a receiver......................................................................................................282 11.5.7 configuring the sbi as a master or a slave................................................................................................................... 282 11.5.8 generating start and stop conditions........................................................................................................................... 282 11.5.9 interrupt service request and release.......................................................................................................................... 283 vii 11.5.10 arbitration lost detection monitor............................................................................................................................. 283 11.5.11 slave address match detection monitor..................................................................................................................... 285 11.5.12 general-call detection monitor ................................................................................................................................... 285 11.5.13 last received bit monitor...........................................................................................................................................285 11.5.14 data buffer register (sbixdbr)................................................................................................................................285 11.5.15 baud rate register (sbixbr0)................................................................................................................................... 285 11.5.16 software reset.............................................................................................................................................................285 11.6 data transfer procedure in the i2c bus modei2c............................................................. 286 11.6.1 device initialization.......................................................................................................................................................286 11.6.2 generating the start condition and a slave address..................................................................................................... 286 11.6.2.1 master mode 11.6.2.2 slave mode 11.6.3 transferring a data word.............................................................................................................................................. 288 11.6.3.1 master mode ( 12.4.3 ad monitor function.................................................................................................................................................... 333 12.4.4 selecting the input channel........................................................................................................................................... 334 12.4.5 ad conversion details.................................................................................................................................................. 334 12.4.5.1 starting ad conversion 12.4.5.2 ad conversion 12.4.5.3 top-priority ad conversion during normal ad conversion 12.4.5.4 stopping repeat conversion mode 12.4.5.5 reactivating normal ad conversion 12.4.5.6 conversion completion 12.4.5.7 interrupt generation timings and ad conversion result storage register 13. watchdog timer(wdt) 13.1 configuration....................................................................................................................... 341 13.2 register................................................................................................................................ 342 13.2.1 wdmod(watchdog timer mode register) ................................................................................................................ 342 13.2.2 wdcr (watchdog timer control register)................................................................................................................. 343 13.3 operations............................................................................................................................ 344 13.3.1 basic operation.............................................................................................................................................................. 344 13.3.2 operation mode and status ............................................................................................................................................ 344 13.4 operation when malfunction (runaway) is detected............................................................ 345 13.4.1 intwdt interrupt generation....................................................................................................................................... 345 13.4.2 internal reset generation................................................................................................................................................. 346 13.5 control register.................................................................................................................... 347 13.5.1 watchdog timer mode register (wdmod)................................................................................................................ 347 13.5.2 watchdog timer control register(wdcr).................................................................................................................. 347 13.5.3 setting example.............................................................................................................................................................. 348 13.5.3.1 disabling control 13.5.3.2 enabling control 13.5.3.3 watchdog timer clearing control 13.5.3.4 detection time of watchdog timer 14. real time clock (rtc) 14.1 function............................................................................................................................... 349 14.2 block diagram..................................................................................................................... 349 14.3 detailed description register.............................................................................................. 350 14.3.1 register list................................................................................................................................................................... 350 14.3.2 control register............................................................................................................................................................. 350 14.3.3 detailed description of control register...................................................................................................................... 352 14.3.3.1 rtcsecr (second column register (for page0 only)) 14.3.3.2 rtcminr (minute column register (page0/1)) 14.3.3.3 rtchourr (hour column register(page0/1)) 14.3.3.4 rtcdayr (day of the week column register(page0/1)) 14.3.3.5 rtcdater (day column register (for page0/1 only)) 14.3.3.6 rtcmonthr (month column register (for page0 only)) 14.3.3.7 rtcmonthr (selection of 24-hour clock or 12-hour clock24(for page1 only)) 14.3.3.8 rtcyearr (year column register (for page0 only)) 14.3.3.9 rtcyearr (leap year register (for page1 only)) 14.3.3.10 rtcpager(page register(page0/1)) 14.3.3.11 rtcrestr (reset register (for page0/1)) 14.4 operational description....................................................................................................... 359 14.4.1 reading clock data......................................................................................................................................................... 359 14.4.2 writing clock data.......................................................................................................................................................... 359 14.4.3 entering the low power consumption mode............................................................................................................... 361 14.5 alarm function..................................................................................................................... 362 14.5.1 "low" pulse (when the alarm register corresponds with the clock)............................................................................. 362 14.5.2 1hz cycle "low" pulse1 hz........................................................................................................................................... 363 14.5.3 16hz cycle "low" pulse16 hz....................................................................................................................................... 363 ix 15. flash memory operation 15.1 flash memory......................................................................................................................365 15.1.1 features..........................................................................................................................................................................365 15.1.2 block diagram of the flash memory section............................................................................................................... 367 15.2 operation mode................................................................................................................... 368 15.2.1 reset operation.............................................................................................................................................................. 369 15.2.2 user boot mode (single chip mode) ............................................................................................................................. 370 15.2.2.1 (1-a) method 1: storing a programming routine in the flash memory 15.2.2.2 (1-b) method 2: transferring a programming routine from an external host 15.2.3 single boot mode.......................................................................................................................................................... 378 15.2.3.1 (2-a) using the program in the on-chip boot rom 15.2.4 configuration for single boot mode.............................................................................................................................381 15.2.5 memory map................................................................................................................................................................. 382 15.2.6 interface specification.................................................................................................................................................... 383 15.2.7 data transfer format.....................................................................................................................................................384 15.2.8 restrictions on internal memories................................................................................................................................. 384 15.2.9 transfer format for single boot mode commands....................................................................................................... 384 15.2.9.1 ram transfer 15.2.9.2 show flash memory sum 15.2.9.3 transfer format for the show product information 15.2.9.4 chip erase and protect bit erase 15.2.10 operation of boot program.......................................................................................................................................... 391 15.2.10.1 ram transfer command 15.2.10.2 show flash memory sum command 15.2.10.3 show product information command 15.2.10.4 chip and protection bit erase command 15.2.10.5 acknowledge responses 15.2.10.6 determination of a serial operation mode 15.2.10.7 password 15.2.10.8 calculation of the show flash memory sum command 15.2.10.9 checksum calculation 15.2.11 general boot program flowchart................................................................................................................................ 405 15.3 on-board programming of flash memory (rewrite/erase)................................................ 406 15.3.1 flash memory................................................................................................................................................................406 15.3.1.1 block configuration 15.3.1.2 basic operation 15.3.1.3 reset(hardware reset) 15.3.1.4 commands 15.3.1.5 flash control/ status register 15.3.1.6 list of command sequences 15.3.1.7 address bit configuration for bus write cycles 15.3.1.8 flowchart 16. rom protection 16.1 outline................................................................................................................................. 421 16.2 future................................................................................................................................... 421 16.2.1 write/ erase-protection function.................................................................................................................................... 421 16.2.2 security function............................................................................................................................................................421 16.3 register................................................................................................................................ 422 16.3.1 fcflcs (flash control register)................................................................................................................................... 423 16.3.2 fcsecbit(security bit register)................................................................................................................................... 424 16.4 writing and erasing .............................................................................................................. 425 16.4.1 protection bits................................................................................................................................................................ 425 16.4.2 security bit..................................................................................................................................................................... 425 17. electrical characteristics 17.1 absolute maximum ratings................................................................................................ 427 x 17.2 dc electrical characteristics (1/3)...................................................................................... 428 17.3 dc electrical characteristics (2/3)...................................................................................... 429 17.4 dc electrical characteristics (3/3)...................................................................................... 430 17.4.1 TMPM333FDFG/tmpm333fyfg.............................................................................................................................. 430 17.4.2 tmpm333fwfg........................................................................................................................................................... 430 17.5 10-bit adc electrical characteristics ................................................................................. 431 17.6 ac electrical characteristics............................................................................................... 432 17.6.1 ac measurement condition........................................................................................................................................... 432 17.6.2 serial channel (sio/uart).......................................................................................................................................... 432 17.6.2.1 i/o interface mode 17.6.3 serial bus interface(i2c/sio)....................................................................................................................................... 434 17.6.3.1 i2c mode 17.6.3.2 clock-synchronous 8-bit sio mode 17.6.4 event counter................................................................................................................................................................ 436 17.6.5 capture........................................................................................................................................................................... 436 17.6.6 external interrupt........................................................................................................................................................... 436 17.6.7 nmi................................................................................................................................................................................ 437 17.6.8 scout pin ac characteristic...................................................................................................................................... 437 17.6.9 debug communication.................................................................................................................................................. 438 17.6.9.1 swd interface 17.6.9.2 jtag interface 17.6.10 etm trace................................................................................................................................................................... 439 17.7 flash characteristics............................................................................................................ 439 17.7.1 rewriting....................................................................................................................................................................... 439 17.8 recommended oscillation circuit....................................................................................... 440 17.8.1 ceramic oscillator.......................................................................................................................................................... 440 17.8.2 crystal oscillator............................................................................................................................................................ 440 17.9 handling precaution............................................................................................................ 441 17.9.1 solderability................................................................................................................................................................... 441 17.9.2 power-on sequence........................................................................................................................................................ 441 18. port section equivalent circuit schematic 18.1 pa0, pb1 to 2, pe1 to 3, pe5 to 6, pf1 to 7, pg0 to 6, ph0 to 7, pi6 to 7, pj0 to 3, pj6 to 7 ................................................................................................................................................ 443 18.2 pa1...................................................................................................................................... 443 18.3 pa2 to 7, pb0, pb3 to 7, pe0, pe4, pf0, pg7, pi0 to 5, pj4 to 5, pk1 to 2..................... 444 18.4 pc0 to 3, pd4 to 7............................................................................................................... 444 18.5 pd0 to 3............................................................................................................................... 444 18.6 pk0...................................................................................................................................... 445 18.7 nmi, mode........................................................................................................................ 445 18.8 reset................................................................................................................................. 445 18.9 x1, x2.................................................................................................................................. 446 18.10 xt1, xt2 ........................................................................................................................... 446 18.11 vrefh, avss.................................................................................................................. 446 19. package dimensions xi xii TMPM333FDFG/fyfg/fwfg the TMPM333FDFG/fyfg/fwfg is a 32-bit risc microprocessor series with an arm cortex-m3 micro- processor core. product name rom (flash) ram package TMPM333FDFG 512 kbyte 32 kbyte lqfp100-p-1414-0.50h tmpm333fyfg 256 kbyte 16 kbyte tmpm333fwfg 128 kbyte 8 kbyte features of the TMPM333FDFG/fyfg/fwfg are as follows: 1.1 features 1. arm cortex-m3 microprocessor core a. improved code efficiency has been realized through the use of thumb -2 instruction. ? ? ? ? ? ? ? ? ? product name on chip flash rom on chip ram TMPM333FDFG 512 kbyte 32 kbyte tmpm333fyfg 256 kbyte 16 kbyte tmpm333fwfg 128 kbyte 8 kbyte 3. 16-bit timer (tmrb): 10 channels ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? TMPM333FDFG/fyfg/fwfg 1.1 features page 2 1.2 block diagram figure 1-1 TMPM333FDFG/fyfg/fwfgblock diagram TMPM333FDFG/fyfg/fwfg page 3 cortex-m3 cpu debug nvic i/f flash i/f ram i/f bootrom bus bridge ahb-bus-matrix d-code i-code system i/o-bus cg sio/uart (3ch) i2c/sio (3ch) port a~k tmrb (10ch) wdt rtc adc (12ch) 1.3 pin layout (top view) figure 1-2 shows the pin layout of TMPM333FDFG/fyfg/fwfg. figure 1-2 pin layout (lqfp100) TMPM333FDFG/fyfg/fwfg 1.3 pin layout (top view) page 4 1 5 10 15 20 25 80 85 90 95 100 50 45 40 35 30 75 70 65 60 55 TMPM333FDFG tmpm333fyfg tmpm333fwfg top view ain10/pd6 ain11/pd7 avss vrefh avdd3 int4/pg3 tb9out/pk2 tb7out/pj5 tb2in0/ph4 tb2in1/ph5 tb8out/pg7 test2 dvss dvdd3 sda2/so2/pg4 scl2/si2/pg5 sck2/pg6 test1 int5/pf7 txd0/pe0 rxd0/pe1 cts0/sclk0/pe2 txd1/pe4 rxd1/pe5 cts1/sclk1/pe6 pk0 pj1/int1 pi3/tb3out pb7 pf6/sck1 pf5/si1/scl1 pf4/so1/sda1 pb6 pi2/tb2out pb5 pi1/tb1out pj6/int6 pi0/tb0out pb4 ph3/tb1in1 pf2/sclk2/cts2 pf1/rxd2 pf0/txd2 ph2/tb1in0 ph1/tb0in1 ph0/tb0in0/boot pb3 pg2/sck0 pg1/si0/scl0 pg0/so0/sda0 rvss x1 dvss x2 dvdd3 pj0/int0 pa7 pa6/tracedata3 pa5/tracedata2 pa4/tracedata1 pa3/tracedata0 pa2/traceclk dvss dvdd3 pf3 pb2/trst pb1/tdi pj7/int7 test3 pa1/tck/swclk pa0/tms/swdio pb0/tdo/swv pi5/tb5out pi4/tb4out pk1/scout/alarm rvdd3 xt1 xt2 tb4in0/pi6 nmi mode reset tb4in1/pi7 tb3in0/ph6 tb3in1/ph7 int2/pj2 int3/pj3 tb6out/pj4 pe3 test4 ain0/pc0 ain1/pc1 ain2/pc2 ain3/pc3 tb5in0/ain4/pd0 tb5in1/ain5/pd1 tb6in0/ain6/pd2 tb6in1/ain7/pd3 ain8/pd4 ain9/pd5 1.4 pin names and functions table 1-1 and table 1-2 sort the input and output pins of the TMPM333FDFG/fyfg/fwfg by pin or port. each table includes alternate pin names and functions for multi-function pins. 1.4.1 sorted by pin table 1-1 pin names and functions sorted by pin (1/6) type pin no. pin name input/ output function function 1 pd6 ain10 i i input port analog input function 2 pd7 ain11 i i input port analog input ps 3 avss i ad converter: gnd pin (0v) (note) avss must be connected to gnd even if the a/d converter is not used. ps 4 vrefh i supplying the ad converter with a reference power supply. (note) vrefh must be connected to power supply even if a/d converter is not used. ps 5 avdd3 i supplying the ad converter with a power supply. (note) avdd must be connected to power supply even if a/d converter is not used. function 6 pg3 int4 i/o i i/o port external interrupt pin function 7 pk2 tb9out i/o o i/o port timer b output function 8 pj5 tb7out i/o o i/o port timer b output function 9 ph4 tb2in0 i/o i i/o port inputting the timer b capture trigger function 10 ph5 tb2in1 i/o i i/o port inputting the timer b capture trigger function 11 pg7 tb8out i/o o i/o port timer b output test 12 test2 ? test pin: (note) test pin must be left open. ps 13 dvss ? gnd pin ps 14 dvdd3 ? power supply pin function 15 pg4 sda2/so2 i/o i/o i/o port if the serial bus interface operates -in the i2c mode: data pin -in the sio mode: data pin function 16 pg5 scl2/si2 i/o i/o i/o port if the serial bus interface operates -in the i2c mode: clock pin -in the sio mode: data pin function 17 pg6 sck2 i/o i/o i/o port inputting and outputting a clock if the serial bus interface operates in the sio mode. test 18 test1 ? test pin: (note) test pin must be left open. TMPM333FDFG/fyfg/fwfg page 5 table 1-1 pin names and functions sorted by pin (2/6) type pin no. pin name input/ output function function 19 pf7 int5 i/o i i/o port external interrupt pin function 20 pe0 txd0 i/o o i/o port sending serial data function 21 pe1 rxd0 i/o i i/o port receiving serial data function 22 pe2 sclk0 cts0 i/o i/o i i/o port serial clock input/ output handshake input pin function 23 pe4 txd1 i/o o i/o port sending serial data function 24 pe5 rxd1 i/o i i/o port receiving serial data function 25 pe6 sclk1 cts1 i/o i/o i i/o port serial clock input/ output handshake input pin function 26 pg0 sda0/so0 i/o i/o i/o port -in the i2c mode: data pin -in the sio mode: data pin function 27 pg1 scl0/si0 i/o i/o i/o port -in the i2c mode: clock pin -in the sio mode: data pin function 28 pg2 sck0 i/o i/o i/o port inputting and outputting a clock if the serial bus interface operates in the sio mode. function 29 pb3 i/o i/o port function/ control 30 ph0 tb0in0 boot i/o i i i/o port inputting the timer b capture trigger setting a single boot mode: (note) this pin goes into single boot mode by sampling "low" at the rise of a reset signal. function 31 ph1 tb0in1 i/o i i/o port inputting the timer b capture trigger function 32 ph2 tb1in0 i/o i i/o port inputting the timer b capture trigger function 33 pf0 txd2 i/o o i/o port sending serial data function 34 pf1 rxd2 i/o i i/o port receiving serial data function 35 pf2 sclk2 cts2 i/o i/o i i/o port serial clock input/ output handshake input pin TMPM333FDFG/fyfg/fwfg 1.4 pin names and functions page 6 table 1-1 pin names and functions sorted by pin (3/6) type pin no. pin name input/ output function function 36 ph3 tb1in1 i/o i i/o port inputting the timer b capture trigger function 37 pb4 i/o i/o port function 38 pi0 tb0out i/o o i/o port timer b output function 39 pj6 int6 i/o i i/o port external interrupt pin function 40 pi1 tb1out i/o o i/o port timer b output function 41 pb5 i/o i/o port function 42 pi2 tb2out i/o o i/o port timer b output function 43 pb6 i/o i/o port function 44 pf4 sda1/so1 i/o i/o i/o port -in the i2c mode: data pin -in the sio mode: data pin function 45 pf5 scl1/si1 i/o i/o i/o port -in the i2c mode: clock pin -in the sio mode: data pin function 46 pf6 sck1 i/o i/o i/o port inputting and outputting a clock if the serial bus interface operates in the sio mode. function 47 pb7 i/o i/o port function 48 pi3 tb3out i/o o i/o port timer b output function 49 pj1 int1 i/o i i/o port external interrupt pin function 50 pk0 i/o i/o port (note) nch open drain port. function 51 pk1 scout alarm i/o o o i/o port system clock output alarm output function 52 pi4 tb4out i/o o i/o port timer b output function 53 pi5 tb5out i/o o i/o port timer b output function/ debug 54 pb0 tdo/swv i/o o i/o port debug pin function/ debug 55 pa0 tms/swdio i/o i/o i/o port debug pin TMPM333FDFG/fyfg/fwfg page 7 table 1-1 pin names and functions sorted by pin (4/6) type pin no. pin name input/ output function function/ debug 56 pa1 tck/swclk i/o i i/o port debug pin test 57 test3 ? test pin: (note) test pin must be left open. function 58 pj7 int7 i/o i i/o port external interrupt pin function/ debug 59 pb1 tdi i/o i i/o port debug pin function/ debug 60 pb2 trst i/o i i/o port debug pin function 61 pf3 i/o i/o port ps 62 dvdd3 ? power supply pin ps 63 dvss ? gnd pin function/ debug 64 pa2 traceclk i/o o i/o port debug pin function/ debug 65 pa3 tracedata0 i/o o i/o port debug pin function/ debug 66 pa4 tracedata1 i/o o i/o port debug pin function/ debug 67 pa5 tracedata2 i/o o i/o port debug pin function/ debug 68 pa6 tracedata3 i/o o i/o port debug pin function 69 pa7 i/o i/o port function 70 pj0 int0 i/o i i/o port external interrupt pin ps 71 dvdd3 ? power supply pin clock 72 x2 o connected to a high-speed oscillator. ps 73 dvss ? gnd pin clock 74 x1 i connected to a high-speed oscillator. ps 75 rvss ? gnd pin ps 76 rvdd3 ? power supply pin clock 77 xt1 i connected to a low-speed oscillator. clock 78 xt2 o connected to a low-speed oscillator. function 79 pi6 tb4in0 i/o i i/o port inputting the timer b capture trigger TMPM333FDFG/fyfg/fwfg 1.4 pin names and functions page 8 table 1-1 pin names and functions sorted by pin (5/6) type pin no. pin name input/ output function function 80 nmi i non-maskable interrupt (note) with a noise filter (about 30ns (typical value)) control 81 mode i mode pin: (note) mode pin must be connected to gnd. function 82 reset i reset input pin (note) with a pull-up and a noise filter (about 30ns (typical value)) function 83 pi7 tb4in1 i/o i i/o port inputting the timer b capture trigger function 84 ph6 tb3in0 i/o i i/o port inputting the timer b capture trigger function 85 ph7 tb3in1 i/o i i/o port inputting the timer b capture trigger function 86 pj2 int2 i/o i i/o port external interrupt pin function 87 pj3 int3 i/o i i/o port external interrupt pin function 88 pj4 tb6out i/o o i/o port timer b output function 89 pe3 i/o i/o port test 90 test4 ? test pin: (note) test pin must be left open. function 91 pc0 ain0 i i input port analog input function 92 pc1 ain1 i i input port analog input function 93 pc2 ain2 i i input port analog input function 94 pc3 ain3 i i input port analog input function 95 pd0 ain4 tb5in0 i i i input port analog input inputting the timer b capture trigger function 96 pd1 ain5 tb5in1 i i i input port analog input inputting the timer b capture trigger TMPM333FDFG/fyfg/fwfg page 9 table 1-1 pin names and functions sorted by pin (6/6) type pin no. pin name input/ output function function 97 pd2 ain6 tb6in0 i i i input port analog input inputting the timer b capture trigger function 98 pd3 ain7 tb6in1 i i i input port analog input inputting the timer b capture trigger function 99 pd4 ain8 i i input port analog input function 100 pd5 ain9 i i input port analog input TMPM333FDFG/fyfg/fwfg 1.4 pin names and functions page 10 1.4.2 sorted by port table 1-2 pin names and functions sorted by port (1/5) port type pin no. pin name input/ output function port a function/ debug 55 pa0 tms/swdio i/o i/o i/o port debug pin port a function/ debug 56 pa1 tck/swclk i/o i i/o port debug pin port a function/ debug 64 pa2 traceclk i/o o i/o port debug pin port a function/ debug 65 pa3 tracedata0 i/o o i/o port debug pin port a function/ debug 66 pa4 tracedata1 i/o o i/o port debug pin port a function/ debug 67 pa5 tracedata2 i/o o i/o port debug pin port a function/ debug 68 pa6 tracedata3 i/o o i/o port debug pin port a function 69 pa7 i/o i/o port port b function/ debug 54 pb0 tdo/swv i/o o i/o port debug pin port b function/ debug 59 pb1 tdi i/o i i/o port debug pin port b function/ debug 60 pb2 trst i/o i i/o port debug pin port b function 29 pb3 i/o i/o port port b function 37 pb4 i/o i/o port port b function 41 pb5 i/o i/o port port b function 43 pb6 i/o i/o port port b function 47 pb7 i/o i/o port port c function 91 pc0 ain0 i i input port analog input port c function 92 pc1 ain1 i i input port analog input port c function 93 pc2 ain2 i i input port analog input port c function 94 pc3 ain3 i i input port analog input port d function 95 pd0 ain4 tb5in0 i i i input port analog input inputting the timer b capture trigger TMPM333FDFG/fyfg/fwfg page 11 table 1-2 pin names and functions sorted by port (2/5) port type pin no. pin name input/ output function port d function 96 pd1 ain5 tb5in1 i i i input port analog input inputting the timer b capture trigger port d function 97 pd2 ain6 tb6in0 i i i input port analog input inputting the timer b capture trigger port d function 98 pd3 ain7 tb6in1 i i i input port analog input inputting the timer b capture trigger port d function 99 pd4 ain8 i i input port analog input port d function 100 pd5 ain9 i i input port analog input port d function 1 pd6 ain10 i i input port analog input port d function 2 pd7 ain11 i i input port analog input port e function 20 pe0 txd0 i/o o i/o port sending serial data port e function 21 pe1 rxd0 i/o i i/o port receiving serial data port e function 22 pe2 sclk0 cts0 i/o i/o i i/o port serial clock input/ output handshake input pin port e function 89 pe3 i/o i/o port port e function 23 pe4 txd1 i/o o i/o port sending serial data port e function 24 pe5 rxd1 i/o i i/o port receiving serial data port e function 25 pe6 sclk1 cts1 i/o i/o i i/o port serial clock input/ output handshake input pin port f function 33 pf0 txd2 i/o o i/o port sending serial data port f function 34 pf1 rxd2 i/o i i/o port receiving serial data port f function 35 pf2 sclk2 cts2 i/o i/o i i/o port serial clock input/ output handshake input pin port f function 61 pf3 i/o i/o port TMPM333FDFG/fyfg/fwfg 1.4 pin names and functions page 12 table 1-2 pin names and functions sorted by port (3/5) port type pin no. pin name input/ output function port f function 44 pf4 sda1/so1 i/o i/o i/o port -in the i2c mode: data pin -in the sio mode: data pin port f function 45 pf5 scl1/si1 i/o i/o i/o port -in the i2c mode: clock pin -in the sio mode: data pin port f function 46 pf6 sck1 i/o i/o i/o port inputting and outputting a clock if the serial bus interface operates in the sio mode. port f function 19 pf7 int5 i/o i i/o port external interrupt pin port g function 26 pg0 sda0/so0 i/o i/o i/o port -in the i2c mode: data pin -in the sio mode: data pin port g function 27 pg1 scl0/si0 i/o i/o i/o port -in the i2c mode: clock pin -in the sio mode: data pin port g function 28 pg2 sck0 i/o i/o i/o port inputting and outputting a clock if the serial bus interface operates in the sio mode. port g function 6 pg3 int4 i/o i i/o port external interrupt pin port g function 15 pg4 sda2/so2 i/o i/o i/o port if the serial bus interface operates -in the i2c mode: data pin -in the sio mode: data pin port g function 16 pg5 scl2/si2 i/o i/o i/o port if the serial bus interface operates -in the i2c mode: clock pin -in the sio mode: data pin port g function 17 pg6 sck2 i/o i/o i/o port inputting and outputting a clock if the serial bus interface operates in the sio mode. port g function 11 pg7 tb8out i/o o i/o port timer b output port h function/ control 30 ph0 tb0in0 boot i/o i i i/o port inputting the timer b capture trigger setting a single boot mode: this pin goes into single boot mode by sampling "low" at the rise of a reset signal. port h function 31 ph1 tb0in1 i/o i i/o port inputting the timer b capture trigger port h function 32 ph2 tb1in0 i/o i i/o port inputting the timer b capture trigger port h function 36 ph3 tb1in1 i/o i i/o port inputting the timer b capture trigger TMPM333FDFG/fyfg/fwfg page 13 table 1-2 pin names and functions sorted by port (4/5) port type pin no. pin name input/ output function port h function 9 ph4 tb2in0 i/o i i/o port inputting the timer b capture trigger port h function 10 ph5 tb2in1 i/o i i/o port inputting the timer b capture trigger port h function 84 ph6 tb3in0 i/o i i/o port inputting the timer b capture trigger port h function 85 ph7 tb3in1 i/o i i/o port inputting the timer b capture trigger port i function 38 pi0 tb0out i/o o i/o port timer b output port i function 40 pi1 tb1out i/o o i/o port timer b output port i function 42 pi2 tb2out i/o o i/o port timer b output port i function 48 pi3 tb3out i/o o i/o port timer b output port i function 52 pi4 tb4out i/o o i/o port timer b output port i function 53 pi5 tb5out i/o o i/o port timer b output port i function 79 pi6 tb4in0 i/o i i/o port inputting the timer b capture trigger port i function 83 pi7 tb4in1 i/o i i/o port inputting the timer b capture trigger port j function 70 pj0 int0 i/o i i/o port external interrupt pin port j function 49 pj1 int1 i/o i i/o port external interrupt pin port j function 86 pj2 int2 i/o i i/o port external interrupt pin port j function 87 pj3 int3 i/o i i/o port external interrupt pin port j function 88 pj4 tb6out i/o o i/o port timer b output port j function 8 pj5 tb7out i/o o i/o port timer b output port j function 39 pj6 int6 i/o i i/o port external interrupt pin port j function 58 pj7 int7 i/o i i/o port external interrupt pin port k function 50 pk0 i/o i/o port (note) nch open drain port. TMPM333FDFG/fyfg/fwfg 1.4 pin names and functions page 14 table 1-2 pin names and functions sorted by port (5/5) port type pin no. pin name input/ output function port k function 51 pk1 scout alarm i/o o o i/o port system clock output alarm output port k function 7 pk2 tb9out i/o o i/o port timer b output - function 82 reset i reset input pin (note) with a pull-up and a noise filter (about 30ns (typical value)) - function 80 nmi i non-maskable interrupt (note) with a noise filter (about 30ns (typical value)) - control 81 mode i mode pin: (note) mode pin must be connected to gnd. - clock 72 x2 o connected to a high-speed oscillator. - clock 74 x1 i connected to a high-speed oscillator. - clock 77 xt1 i connected to a low-speed oscillator. - clock 78 xt2 o connected to a low-speed oscillator. - test 12 test2 ? test pin: (note) test pin must be left open. - test 18 test1 ? test pin: (note) test pin must be left open. - test 57 test3 ? test pin: (note) test pin must be left open. - test 90 test4 ? test pin: (note) test pin must be left open. - ps 3 avss i ad converter: gnd pin (0v) (note) avss must be connected to gnd even if the a/d converter is not used. - ps 4 vrefh i supplying the ad converter with a reference power supply. (note) vrefh must be connected to power supply even if a/d converter is not used. - ps 5 avdd3 i supplying the ad converter with a power supply. (note) avdd must be connected to power supply even if a/d converter is not used. - ps 13 dvss ? gnd pin - ps 14 dvdd3 ? power supply pin - ps 62 dvdd3 ? power supply pin - ps 63 dvss ? gnd pin - ps 71 dvdd3 ? power supply pin - ps 73 dvss ? gnd pin - ps 75 rvss ? gnd pin - ps 76 rvdd3 ? power supply pin TMPM333FDFG/fyfg/fwfg page 15 1.5 pin numbers and power supply pins table 1-3 pin numbers and power supplies power supply voltage range pin no. pin name dvdd3 2.7 to 3.6v 14, 62,71 pa,pb,pe,pf,pg,ph,pi,pj,pk,x1,x2,xt1, xt2, reset, nmi,mode avdd3 5 pc,pd rvdd3 76 ? TMPM333FDFG/fyfg/fwfg 1.5 pin numbers and power supply pins page 16 2. processor core the tx03 series has a high-performance 32-bit processor core (the arm cortex-m3 processor core). for infor- mation on the operations of this processor core, please refer to the "cortex-m3 technical reference manual" issued by arm limited.this chapter describes the functions unique to the tx03 series that are not explained in that document. 2.1 information on the processor core the following table shows the revision of the processor core in the TMPM333FDFG/fyfg/fwfg. refer to the detailed information about the cpu core and architecture, refer to the arm manual "cortex-m series processors" in the following url: http://infocenter.arm.com/help/index.jsp product name core revision TMPM333FDFG tmpm333fyfg r1p1-00rel0 tmpm333fwfg r1p1-01rel0 2.2 configurable options the cortex-m3 core has optional blocks. the optional blocks of the revision r1p1 are etm and mpu. the following tables shows the configurable options in the TMPM333FDFG/fyfg/fwfg. configurable options implementation mpu not implementable etm implementable 2.3 exceptions/ interruptions exceptions and interruptions are described in the following section. 2.3.1 number of interrupt inputs the number of interrupt inputs can optionally be defined from 1 to 240 in the cortex-m3 core. TMPM333FDFG/fyfg/fwfg has 46 interrupt inputs. the number of interrupt inputs is reflected in 2.3.2 number of priority level interrupt bits the cortex-m3 core can optionally configure the number of priority level interrupt bits from 3 bits to 8 bits. TMPM333FDFG/fyfg/fwfg has three priority level interrupt bits. the number of priority level interrupt bits is used for assigning a priority level in the interrupt priority registers and system handler priority registers. 2.3.3 systick the cortex-m3 core has a systick timer which can generate systick exception. in the TMPM333FDFG/fyfg/fwfg, the clock that is input from x1 pin dividing by 32 is used as a count clock for the systic timer. systick calibration register can set a calibration value to measure 10ms. in this product, when 8mhz is input to x1 pin, calibration value is set to 0x9c4 which can measure 10ms. additionally, if this value is read as "0" both of 2.4 events the cortex-m3 core has event output signals and event input signals. an event output signal is output by sev instruction execution. if an event is input, the core returns from low-power consumption mode caused by wfe in- struction. TMPM333FDFG/fyfg/fwfg does not use event output signals and event input signals. please do not use sev instruction and wfe instruction. 2.5 power management the cortex-m3 core provides power management system which uses sleeping signals and sleepdeep signals. sleepdeep signals are output when TMPM333FDFG/fyfg/fwfg 2. processor core 2.6 exclusive access page 20 3. debug interface 3.1 specification overview TMPM333FDFG/fyfg/fwfg contains the serial wire jtag debug port (swj-dp) unit for interfacing with the debugging tools and the embedded trace macrocell(etm) unit for instruction trace output.trace data is output to the dedicated pins(tracedata[3:0], swv) for the debugging via the on-chip trace port interface unit (tpiu). for details about swj-dp, etm and tpiu, refer to "cortex-m3 technical reference manual" . 3.2 swj-dp swj-dp supports the serial wire debug port (swdck, swdio) and the jtag debug port (tdi, tdo, tms, tck, trst). 3.3 etm etm supports four data signal pins (tracedata[3:0]), one clock signal pin (traceclk) and trace output from swv. TMPM333FDFG/fyfg/fwfg page 21 3.4 pin functions the debug interface pins can also be used as general-purpose ports. the pa0 and pa1 pins are shared between the jtag debug port function and the serial wire debug port function. the pb0 pin is shared between the jtag debug port function and the swv trace output function. table 3-1 swj-dp,etm debug functions swj-dp pin name general- purpose port name jtag debug function sw debug function i / o explanation i / o explanation tms / swdio pa0 input jtag test mode selection i / o serial wire data input/output tck / swclk pa1 input jtag test check input serial wire clock tdo / swv pb0 output jtag test data output (output)(note) (serial wire viewer output) tdi pb1 input jtag test data input - - trst pb2 input jtag test reset - - traceclk pa2 output trace clock output tracedata0 pa3 output trace data output0 tracedata1 pa4 output trace data output1 tracedata2 pa5 output trace data output2 tracedata3 pa6 output trace data output3 note: when swv function is enabled. after reset, pa0, pa1, pb0, pb1 and pb2 pins are configured as debug port function pins. the functions of other debug interface pins need to be programmed as required. when using a low power consumption mode, take note of the following points. note 1: if pa0 and pb0 are configured as tms/swdio and tdo/swv, output continues to be enabled even in stop mode regardless of the setting of the cgstbycr table 3-2 debug interface pins and related port settings after reset port name (bit name) debug function value of related port settings after reset function (pxfr) input (pxie) output (pxcr) pull-up (pxpup) pull-down (pxpdn) pa0 tms/swdio 1 1 1 1 ? pa1 tck/swclk 1 1 0 ? 1 pb0 tdo/swv 1 0 1 0 ? pb1 tdi 1 1 0 1 ? pb2 trst 1 1 0 1 ? pa2 traceclk 0 0 0 0 ? pa3 tracedata0 0 0 0 0 ? pa4 tracedata1 0 0 0 0 ? pa5 tracedata2 0 0 0 0 ? pa6 tracedata3 0 0 0 0 ? ? : dont care 3.5 peripheral functions in halt mode when the cortex-m3 core enters in the halt mode, the watchdog-timer (wdt) automatically stops. other peripheral functions continue to operate. 3.6 reset vector break TMPM333FDFG/fyfg/fwfg is prohibited from transmission with debug tools while reset caused by reset pin is effective.when setting a stop by using reset vector, set the following procedure after reset; set break points from the debug tools, then set the application interrupt and the 3.7 connection with a debug tool 3.7.1 about connection with debug tool concerning a connection with debug tools, refer to manufactures recommendations. debug interface pins contain a pull-up resistor and a pull-down resistor.when debug interface pins are con- nected with external pull-up or pull-down, please pay attention to input level. 3.7.2 important points of using debug interface pins used as general-purpose ports TMPM333FDFG/fyfg/fwfg is prohibited from transmission with debug tools while reset caused by re- set pin is effective. therefor it cannot change to the debug mode. the pa0, pa1, pb0, pb1 and pb2 ports are the debug interface pins after reset however if these pins are changed to the general-purpose port immediately after reset, the control from the debug tools are not accepted under some circumstances.when changing the settings, please pay attention to the status of debug interface pins. table 3-3 table of using debug interface pins debug interface pins trst tdi tdo / swv tck / swclk tms / swdio trace data[3:0] trace clk jtag+sw (after reset) jtag+sw (without trst) jtag+trace sw sw+swv debugging function disabled : enabled : disabled (usable as general-purpose port) TMPM333FDFG/fyfg/fwfg 3. debug interface 3.7 connection with a debug tool page 24 4. memory map 4.1 memory map the memory maps for theTMPM333FDFG/fyfg/fwfg are based on the arm cortex-m3 processor core mem- ory map. the internal rom is mapped to the code of the cortex-m3 core memory, the internal ram is mapped to the sram region and the special function register (sfr) is mapped to the peripheral region respectively. the special function register (sfr) indicates i/o ports and control registers for the peripheral function. the sram and sfr regions are all included in the bit-band region. the cpu register region is the processor core's internal register region. for more information on each region, see the "cortex-m3 technical reference manual". note that access to regions indicated as "fault" causes a memory fault if memory faults are enabled or a hard fault if memory faults are disabled. do not access the vendor-specific region. TMPM333FDFG/fyfg/fwfg page 25 4.1.1 memory map of the TMPM333FDFG figure 4-1shows the memory map of the TMPM333FDFG. figure 4-1 memory map (TMPM333FDFG) TMPM333FDFG/fyfg/fwfg 4. memory map 4.1 memory map page 26 sfr internal ram (32k) internal rom (512k) [ b ) ) ) ) [ b [ b ) ) ) [ b [ b ) ) ) ) [ b vendor-specific cpu register region fault fault fault [ ' ) ) ) b ) ) ) ) [ ( b [ ( ) b ) ) ) ) [ ( b [ ) ) ) ) b ) ) ) ) 4.1.2 memory map of tmpm333fyfg figure 4-2 shows the memory map of the tmpm333fyfg. figure 4-2 memory map (tmpm333fyfg) note:in addition to 256kb flash area, the tmpm333fyfg provides 128-word data/ password area (1 page) for show product information command in the address range 0x0007_fe00 - 0x0007_ffff. see the chapter "flash memory operation" for details on the single boot mode. do not access to the range from 0x0004_0000 through the password area. TMPM333FDFG/fyfg/fwfg page 27 sfr internal ram (16k) internal rom (256k) [ b ) ) ) ) [ b [ b ) ) ) [ b [ b ) ) ) ) [ b vendor-specific cpu register region fault fault fault [ ' ) ) ) b ) ) ) ) [ ( b [ ( ) b ) ) ) ) [ ( b [ ) ) ) ) b ) ) ) ) 4.1.3 memory map of tmpm333fwfg figure 4-3 shows the memory map of the tmpm333fwfg. figure 4-3 memory map (tmpm333fwfg) TMPM333FDFG/fyfg/fwfg 4. memory map 4.1 memory map page 28 sfr internal ram (8k) internal rom (128k) [ b ) ) ) ) [ b [ b ) ) ) [ b [ b ) ) ) ) [ b vencor-specific cpu register region fault fault fault [ ' ) ) ) b ) ) ) ) [ ( b [ ( ) b ) ) ) ) [ ( b [ ) ) ) ) b ) ) ) ) 4.2 sfr area detail this section contains the list of addresses in the sfr area (0x4000_0000 through 0x4007_ffff) assigned to pe- ripheral function. access to the reserved areas in the table 4-1 is prohibited. as for the sfr area, reading the areas not described in the table 4-1 yields undefined value. writing these area is ignored. table 4-1 sfr area detail start address end address peripheral reserved 0x4000_0000 0x4000_02bf port(a to k) 0x4000_0190 0x4000_01d0 0x4000_0210 0x4000_0250 to to to to 0x4000_0193 0x4000_01d3 0x4000_0213 0x4000_0253 0x4001_0000 0x4001_027f tmrb(10ch) 0x4002_0000 0x4002_007f i2c/sio(3ch) 0x4002_0080 0x4002_013f sio/uart(3ch) 0x4003_0000 0x4003_007f adc(12ch) 0x4003_0024 to 0x4003_002f 0x4004_0000 0x4004_003f wdt 0x4004_0100 0x4004_013f rtc 0x4004_010d 0x4004_0200 0x4004_023f cg 0x4004_022c to 0x4004_023f 0x4004_0300 0x4004_033f reserved 0x4004_0400 0x4004_047f reserved 0x4004_0428 0x4004_0468 to to 0x4004_0433 0x4004_0473 0x4004_0500 0x4004_053f flash 0x4004_0504 0x4004_0524 to to 0x4004_0507 0x4004_052b 0x4004_0540 0x4004_05bf reserved 0x4004_0540 0x4004_0550 0x4004_0560 to to to 0x4004_0547 0x4004_0553 0x4004_0593 0x4004_0700 0x4004_073f reserved 0x4004_0700 to 0x4004_0707 TMPM333FDFG/fyfg/fwfg page 29 TMPM333FDFG/fyfg/fwfg 4. memory map 4.2 sfr area detail page 30 5. reset the TMPM333FDFG/fyfg/fwfg has three reset sources: an external reset pin ( reset), a watchdog timer (wdt) and the setting 5.2 warm reset 5.2.1 reset period as a precondition, ensure that the power supply voltage is within the operating range and the internal high- frequency oscillator is providing stable oscillation. to reset the TMPM333FDFG/fyfg/fwfg, assert the reset signal (active low) for a minimum duration of 12 system clocks. 5.2.2 after reset a warm reset initializes the majority of the cortex-m3 processor core's system control registers and internal function registers. the processor core's system debug components (fpb, dwt, itm) register, the clock generator's cgrstflg register and the fcsecbit register are initialized by a only cold reset. after reset, the pll multiplication circuit is inactive and must be enabled in the cgpllsel register if needed. when the reset exception handling is completed, the program branches to the reset interrupt service routine. note: the reset operation may alter the internal ram state. TMPM333FDFG/fyfg/fwfg 5. reset 5.2 warm reset page 32 6. clock/mode control 6.1 features the clock/mode control block enables to select clock gear, prescaler clock and warm-up of the pll clock multi- plication circuit and oscillator. there is also the low power consumption mode which can reduce power consumption by mode transitions. this chapter describes how to control clock operating modes and mode transitions. the clock/mode control block has the following functions: ? ? ? ? 6.2 registers 6.2.1 register list the following table shows the cg-related registers and addresses. base address = 0x4004_0200 register name address (base+) system control register cgsyscr 0x0000 oscillation control register cgosccr 0x0004 standby control register cgstbycr 0x0008 pll selection register cgpllsel 0x000c system clock selection register cgcksel 0x0010 TMPM333FDFG/fyfg/fwfg 6. clock/mode control 6.2 registers page 34 6.2.2 cgsyscr (system control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - scosel after reset 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 bit symbol - - - fpsel - prck after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - gear after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-18 ? r read as 0. 17-16 scosel[1:0] r/w scout out 00: fs 01: fsys/2 10: fsys 11: t0 enables to output the specified clock from scout pin. 15-13 ? r read as 0. 12 fpsel r/w fperiph 0: fgear 1: fc specifies the source clock to fperiph. 11 ? r read as 0. 10-8 prck[2:0] r/w prescaler clock 000: fperiph 001: fperiph/2 010: fperiph/4 011: fperiph/8 100: fperiph/16 101: fperiph/32 110: reserved 111: reserved specifies the prescaler clock to peripheral i/o. 7-3 ? r read as 0. 2-0 gear[2:0] r/w high-speed clock gear (fc) gear 000: fc 001: reserved 010: reserved 011: reserved 100: fc/2 101: fc/4 110: fc/8 111: reserved TMPM333FDFG/fyfg/fwfg page 35 6.2.3 cgosccr (oscillation control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - xten xen after reset 0 0 0 0 0 0 1 1 7 6 5 4 3 2 1 0 bit symbol - wupt wupsel pllon wuef wueon after reset 0 0 0 1 0 0 0 0 bit bit symbol type function 31-14 ? r read as 0. 13-12 ? r/w write "0". 11-10 ? r read as 0 9 xten r/w low-speed oscillator 0: stop 1:oscillation 8 xen r/w high-speed oscillator 0: stop 1:oscillation 7 ? r read as 0 6-4 wupt[2:0] r/w warm-up time x1 000: no warm-up 001: 2 10 / input freq. 010: 2 11 / input freq. 011: 2 12 / input freq. 100: 2 13 /input freq. 101: 2 14 / input freq. 110: 2 15 / input freq. 111: 2 16 / input freq. xt1 000:no warm-up 001: 2 6 / input freq. 010: 2 7 / input freq. 011: 2 8 / input freq. 100: 2 15 / input freq. 101: 2 16 / input freq. 110: 2 17 / input freq. 111: 2 18 / input freq. 3 wupsel r/w warm-up counter 0: x1 1: xt1 specifies the oscillator to warm-up. a clock generated by the specified oscillator is used for the warm-up timer count. 2 pllon r/w pll operation 0: stop 1: oscillation specifies operation of the pll. it stops after reset.setting the bit is required. 1 wuef r status of warm-up timer (wup) 0:warm-up completed 1: warm-up operation enables to monitor the status of the warm-up timer. 0 wueon w operation of warm-up timer 0: don't care 1: starting warm-up enables to start the warm-up timer. TMPM333FDFG/fyfg/fwfg 6. clock/mode control 6.2 registers page 36 6.2.4 cgstbycr (standby control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - drve after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - rxten rxen after reset 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 bit symbol - - - - - stby after reset 0 0 0 0 0 0 1 1 bit bit symbol type function 31-18 ? r read as 0. 17 ? r/w write "0". 16 drve r/w pin status in stop mode. 0: inactive 1:active 15-10 ? r read as 0 9 rxten r/w low-speed oscillator operation after releasing the stop mode. 0: stop 1:oscillation 8 rxen r/w high-speed oscillator operation after releasing the stop mode. 0: stop 1:oscillation 7-3 ? r read as 0. 2-0 stby[2:0] r/w low power consumption mode 000: reserved 001: stop 010: sleep 011: idle 100: reserved 101: reserved 110: reserved 111: reserved TMPM333FDFG/fyfg/fwfg page 37 6.2.5 cgpllsel (pll selection register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - pllsel after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-1 ? r read as 0. 0 pllsel r/w use of pll 0: disuse. x1 selected 1: use specifies use or disuse of the clock multiplied by the pll. "x1" is automatically set after reset. resetting is required when using the pll. TMPM333FDFG/fyfg/fwfg 6. clock/mode control 6.2 registers page 38 6.2.6 cgcksel (system clock selection register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - sysck sysckflg after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-2 ? r read as 0. 1 sysck r/w system clock 0: high-speed (fc) 1: low-speed (fs) enables to specify the system clock. setting cgosccr 6.3 clock control 6.3.1 clock system block diagram each clock is defined as follows: fosc : clock input from the x1 and x2 pins fs : clock input from the xt1 and xt2 (low-speed clock) fpll : clock quadrupled by pll fc : clock specified by cgpllsel 6.3.3 clock system diagram figure 6-1 shows the clock system diagram. figure 6-1 clock block diagram the input clocks to selector shown with an arrow are set as default after reset. TMPM333FDFG/fyfg/fwfg page 41 warming-up timer cgosccr 6.3.4 clock multiplication circuit (pll) this circuit outputs the fpll clock that is quadruple of the high-speed oscillator output clock (fosc.) as a result, the input frequency to oscillator can be low, and the internal clock be made high-speed. the pll is disabled after reset. to enable the pll, set "1" to the cgosccr the following are the examples of the warm-up function configuration. 6.3.6 system clock the TMPM333FDFG/fyfg/fwfg offers two selectable system clocks: low-speed or high-speed. the high- speed clock is dividable. note 1: switching of clock gear is executed when a value is written to the cgsyscr 6.3.8 system clock pin output function the tx03 enables to output the system clock from a pin. the pk1/scout pin can output the low speed clock fs, the system clock fsys and fsys/2, and the prescaler input clock for peripheral i/o t0. by setting the port k registers, the pkcr 6.4 modes and mode transitions 6.4.1 mode transitions the normal mode and the slow mode use the high-speed and low-speed clocks for the system clock respectively. the idle, sleep and stop modes can be used as the low power consumption mode that enables to reduce power consumption by halting processor core operation. when the low-speed clock is not used, the slow and sleep modes cannot be used. figure 6-2 shows a mode transition diagram. for a detail of sleep-on-exit, refer to "cortex-m3 technical reference manual." figure 6-2 mode transition diagram TMPM333FDFG/fyfg/fwfg 6. clock/mode control 6.4 modes and mode transitions page 46 5 h v h w k d v e h h q s h u i r p h g , q v w u x f w l r q / sleep on exit , q w h u u x s w 5 h v h w normal mode idle p r g h stop p r g h slow mode sleep mode , q v w u x f w l r q / sleep on exit , q w h u u x s w , q w h u u x s w , q v w u x f w l r q / sleep on exit , q v w u x f w l r q , q w h u u x s w , q w h u u x s w , q v w u x f w l r q / sleep on exit , q v w u x f w l r q / sleep on exit 6.5 operation mode two operation modes, normal and slow, are available. the features of each mode are described in the fol- lowing section. 6.5.1 normal mode this mode is to operate the cpu core and the peripheral hardware by using the high-speed clock. it is shifted to the normal mode after reset. the low-speed clock can also be used. 6.5.2 slow mode this mode is to operate the cpu core and the peripheral hardware by using the low-speed clock with high- speed clock stopped. the slow mode reduces power consumption compared to the normal mode. this mode allows only the following peripheral functions to operate: i/o ports, real-time clock (rtc). note 1: be sure to stop peripheral functions except for the cpu, rtc and i/o ports before switching to the slow mode. note 2: in the slow mode, be sure not to perform reset using the application interrupt and reset control register 6.6 low power consumption modes the tx03 has three low power consumption modes: idle, sleep and stop. to shift to the low power con- sumption mode, specify the mode in the system control register cgstbycr 6.6.3 stop mode all the internal circuits including the internal oscillator are brought to a stop in the stop mode. by releasing the stop mode, the device returns to the preceding mode of the stop mode and starts operation. the stop mode enables to select the pin status by setting the cgstbycr 6.6.5 operational status in each mode table 6-7 show the operational status in each mode. for i/o port, "" and "" indicate that input/output is enabled and disabled respectively. for other functions, "" and "" indicate that clock is supplied and is not supplied respectively. table 6-7 operational status in each mode block normal slow idle sleep stop processor core i/o port * (note 3) adc (note 1) on/off select- able for each module sio (note 1) sbi (note 1) tmrb (note 1) wdt (note 1) rtc cg pll high-speed oscilla- tor (fc) * (note 2) low-speed oscillator (fs) note 1: in the slow mode, the adc, sio, sbi, tmrb and wdt cannot be used and must be stopped. note 2: the high-speed oscillator does not stop automatically and must be stopped by setting the cgosccr 6.6.6 releasing the low power consumption mode the low power consumption mode can be released by an interrupt request, non-maskable interrupt (nmi) or reset. the release source that can be used is determined by the low power consumption mode selected. details are shown in table 6-8. table 6-8 release source in each mode low power consumption mode idle sleep stop release source interrupt int0 to 7 (note1) intrtc inttb0 to 9 intcap00 to 60, 01 to 61 intrx0 to 2, inttx0 to 2 intsbi0 to 2 intad/intadhp/intadm0, 1 nmi (intwdt) nmi ( nmi pin) reset ( reset pin) : : starts the interrupt handling after the mode is released. (the reset initializes the lsi) unavailable note 1: to release the low power consumption mode by using the level mode interrupt, keep the level until the interrupt handling is started. changing the level before then will prevent the interrupt handling from starting properly. note 2: for shifting to the low power consumption mode, set the cpu to prohibit all the interrupts other than the release source. if not, releasing may be executed by an unspecified interrupt. release by interrupt request to release the low power consumption mode by an interrupt, the cpu must be set in advance to detect the interrupt. in addition to the setting in the cpu, the clock generator must be set to detect the interrupt to be used to release the sleep and stop modes. release by non-maskable interrupt (nmi) there are two kinds of nmi sources: wdt interrupt (intwdt) and nmi pin. intwdt can only be used in the idle mode. the nmi pin can be used to release all the lower power consumption modes. release by reset any low power consumption mode can be released by reset from the reset pin. after that, the mode switches to the normal mode and all the registers are initialized as is the case with normal reset. note that returning to the stop mode by reset does not induce the automatic warm-up. keep the reset signal valid until the oscillator operation becomes stable. refer to "interrupts" for details. TMPM333FDFG/fyfg/fwfg page 51 6.6.7 warm-up mode transition may require the warm-up so that the internal oscillator provides stable oscillation. in the mode transition from stop to the normal/ slow or from sleep to normal, the warm-up counter is activated automatically. and then the system clock output is started after the elapse of configured warm-up time. it is necessary to select a oscillator to be used for warm-up in the cgosccr 6.6.8 clock operations in mode transition the clock operations in mode transition are described in chapter 6.6.8.1 to 6.6.8.4. 6.6.8.1 transition of operation modes: normal stop normal when returning to the normal mode from the stop mode, the warm-up is activated automatically. it is necessary to set the warm-up time before entering the stop mode. returning to the normal mode by reset does not induce the automatic warm-up. keep the reset signal asserted until the oscillator operation becomes stable. 6.6.8.2 transition of operation modes: normal sleep normal when returning to the normal mode from the sleep mode, the warm-up is activated automatically. it is necessary to set the warm-up time before entering the sleep mode. returning to the normal mode by reset does not induce the automatic warm-up. keep the reset signal asserted until the oscillator operation becomes stable. TMPM333FDFG/fyfg/fwfg page 53 fsys (system clock) sleep fosc normal normal mode warm-up system clock stops high-speed clock starts oscillating. warm-up starts. wfi instruction/ sleep on exit release event occurs. warm-up completes. system clock starts. oscillation continues. fs (low speed clock) fsys (system clock) stop fosc normal normal mode warm-up system clock stops high-speed clock starts oscillating. warm-up starts. wfi instruction/ sleep on exit release event occurs. warm-up completes. system clock starts 6.6.8.3 transition of operation modes: slow stop slow the warm-up is activated automatically. it is necessary to set the warm-up time before entering the stop mode. 6.6.8.4 transition of operation modes: slow sleep slow the low-speed clock continues oscillation in the sleep mode. there is no need to make a warm-up setting. TMPM333FDFG/fyfg/fwfg 6. clock/mode control 6.6 low power consumption modes page 54 fsys (system clock= fs) sleep fs slow slow mode system clock stops. wfi instruction / sleep on exit release event occurs. system clock starts. fsys (system clock=fs) stop fs slow slow mode warm-up system clock stops low-speed clock starts oscillating. warm-up starts. wfi insutruction/ sleep on exit release eventoccurs. warm-up completes. system clock starts. 7. exceptions this chapter describes features, types and handling of exceptions. exceptions have close relation to the cpu core. refer to "cortex-m3 technical reference manual" if needed. 7.1 overview an exception causes the cpu to stop the currently executing process and handle another process. there are two types of exceptions: those that are generated when some error condition occurs or when an instruction to generate an exception is executed; and those that are generated by hardware, such as an interrupt request signal from an external pin or peripheral function. all exceptions are handled by the nested vectored interrupt controller (nvic) in the cpu according to the re- spective priority levels. when an exception occurs, the cpu stores the current state to the stack and branches to the corresponding interrupt service routine (isr). upon completion of the isr, the information stored to the stack is automatically restored. 7.1.1 exception types the following types of exceptions exist in the cortex-m3. for detailed descriptions on each exception, refer to "cortex-m3 technical reference manual". ? ? ? ? ? ? ? ? ? ? ? 7.1.2 handling flowchart the following shows how an exception/interrupt is handled. in the following descriptions, indicates hardware handling. indicates software handling. each step is described later in this chapter. processing description see detection by cg/cpu the cg/cpu detects the exception request. section 7.1.2.1 handling by cpu the cpu handles the exception request. section 7.1.2.2 branch to isr the cpu branches to the corresponding interrupt service routine (isr). execution of isr necessary processing is executed. section 7.1.2.3 return from exception the cpu branches to another isr or returns to the previous program. section 7.1.2.4 7.1.2.1 exception request and detection (1) exception occurrence exception sources include instruction execution by the cpu, memory accesses, and interrupt requests from external interrupt pins or peripheral functions. an exception occurs when the cpu executes an instruction that causes an exception or when an error condition occurs during instruction execution. an exception also occurs by an instruction fetch from the execute never (xn) region or an access violation to the fault region. an interrupt request is generated from an external interrupt pin or peripheral function.for interrupts that are used for releasing a standby mode, relevant settings must be made in the clock generator.for details, refer to "7.5 interrupts". TMPM333FDFG/fyfg/fwfg 7. exceptions 7.1 overview page 56 (2) exception detection if multiple exceptions occur simultaneously, the cpu takes the exception with the highest priority. table 7-1 shows the priority of exceptions. "configurable" means that you can assign a priority level to that exception. memory management, bus fault and usage fault exceptions can be enabled or dis- abled. if a disabled exception occurs, it is handled as hard fault. table 7-1 exception types and priority no. exception type priority description 1 reset ?3 (highest) reset pin, wdt or sysretreq 2 non-maskable interrupt ?2 nmi pin or wdt 3 hard fault ?1 fault that cannot activate because a higher-priority fault is being handled or it is disabled 4 memory management configurable exception from the memory protection unit (mpu) (note 1) instruction fetch from the execute never (xn) region 5 bus fault configurable access violation to the hard fault region of the memory map 6 usage fault configurable undefined instruction execution or other faults related to instruction ex- ecution 7~10 reserved ? 11 svcall configurable system service call with svc instruction 12 debug monitor configurable debug monitor when the cpu is not faulting 13 reserved ? 14 pendsv configurable pendable system service request 15 systick configurable notification from system timer 16~ external interrupt configurable external interrupt pin or peripheral function (note 2) note 1: this product does not contain the mpu. note 2: external interrupts have different sources and numbers in each product. for details, see "7.5.1.5 list of interrupt sources". (3) priority setting priority levels the external interrupt priority is set to the interrupt priority register and other exceptions are set to the table 7-2 shows the priority group setting. the pre-emption priority and the sub priority in the table are the number in the case that old sp 7.1.2.3 executing an isr an isr performs necessary processing for the corresponding exception. isrs must be prepared by the user. an isr may need to include code for clearing the interrupt request so that the same interrupt will not occur again upon return to normal program execution. for details about interrupt handling, see "7.5 interrupts". if a higher priority exception occurs during isr execution for the current exception, the cpu abandons the currently executing isr and services the newly detected exception. 7.1.2.4 exception exit (1) execution after returning from an isr when returning from an isr, the cpu takes one of the following actions: ? ? ? (2) exception exit sequence when returning from an isr, the cpu performs the following operations: ? ? ? 7. exceptions 7.1 overview page 60 7.2 reset exceptions reset exceptions are generated from the following three sources. use the reset flag (cgrstflg) register of the clock generator to identify the source of a reset. ? ? ? note: do not reset with 7.3 non-maskable interrupts (nmi) non-maskable interrupts are generated from the following two sources. use the nmi flag (cgnmiflg) register of the clock generator to identify the source of a non-maskable interrupt. ? ? 7.4 systick systick provides interrupt features using the cpu's system timer. when you set a value in the systick reload value register and enable the systick features in the systick control and status register, the counter loads with the value set in the reload value register and begins counting down.when the counter reaches "0", a systick exception occurs.you may be pending exceptions and use a flag to know when the timer reaches "0". the systick calibration value register holds a reload value for counting 10 ms with the system timer. the count clock frequency varies with each product, and so the value set in the systick calibration value register also varies with each product. note: in this product, the system timer counts based on a clock obtained by dividing the clock input from the x1 pin by 32.the systick calibration value register is set to 0x9c4, which provides 10 ms timing when the clock input from x1 is 8 mhz. TMPM333FDFG/fyfg/fwfg 7. exceptions 7.3 non-maskable interrupts (nmi) page 62 7.5 interrupts this chapter describes routes, sources and required settings of interrupts. the cpu is notified of interrupt requests by the interrupt signal from each interrupt source. it sets priority on interrupts and handles an interrupt request with the highest priority. interrupt requests for clearing a standby mode are notified to the cpu via the clock generator. therefore, appropriate settings must be made in the clock generator. 7.5.1 interrupt sources 7.5.1.1 interrupt route figure 7-1 shows an interrupt request route. the interrupts issued by the peripheral function that is not used to release standby are directly input to the cpu (route1). the peripheral function interrupts used to release standby (route 2) and interrupts from the external interrupt pin (route 3) are input to the clock generator and are input to the cpu through the logic for releasing standby (route 4 and 5). if interrupts from the external interrupt pins are not used to release standby, they are directly input to the cpu, not through the logic for standby release (route 6). figure 7-1 interrupt route TMPM333FDFG/fyfg/fwfg page 63 peripheral function cpu exiting standby mode clock generator peripheral function interruptrequest external interrupt pin 7.5.1.2 generation an interrupt request is generated from an external pin or peripheral function assigned as an interrupt source or by setting the nvic's interrupt set-pending register. ? ? ? 7.5.1.3 transmission an interrupt signal from an external pin or peripheral function is directly sent to the cpu unless it is used to exit a standby mode. interrupt requests from interrupt sources that can be used for clearing a standby mode are transmitted to the cpu via the clock generator. for these interrupt sources, appropriate settings must be made in the clock generator in advance. external interrupt sources not used for exiting a standby mode can be used without setting the clock generator. 7.5.1.4 precautions when using external interrupt pins if you use external interrupts, be aware the followings not to generate unexpected interrupts. if input disabled (pxie 7.5.1.5 list of interrupt sources table 7-3 shows the list of interrupt sources. table 7-3 list of interrupt sources no. interrupt source active level (clearing standby) cg interrupt mode control register 0 int0 interrupt pin (pj0/70pin) selectable cgimcga 1 int1 interrupt pin (pj1/49pin) 2 int2 interrupt pin (pj2/86pin) 3 int3 interrupt pin (pj3/87pin) 4 int4 interrupt pin (pg3/6pin) cgimcgb 5 int5 interrupt pin (pf7/19pin) 6 intrx0 serial reception (channel.0) 7 inttx0 serial transmission (channel.0) 8 intrx1 serial reception (channel.1) 9 inttx1 serial transmission (channel.1) 10 intsbi0 serial bus interface 0 11 intsbi1 serial bus interface 1 12 reserved - 13 reserved - 14 reserved - 15 intadhp highest priority ad conversion complete interrupt 16 intadm0 ad conversion monitoring function interrupt 0 17 intadm1 ad conversion monitoring function interrupt 1 18 inttb0 16-bit tmrb match detection 0 19 inttb1 16-bit tmrb match detection 1 20 inttb2 16-bit tmrb match detection 2 21 inttb3 16-bit tmrb match detection 3 22 inttb4 16-bit tmrb match detection 4 23 inttb5 16-bit tmrb match detection 5 24 inttb6 16-bit tmrb match detection 6 25 intrtc real time clock falling edge cgimcgc 26 intcap00 16-bit tmrb input capture 00 27 intcap01 16-bit tmrb input capture 01 28 intcap10 16-bit tmrb input capture 10 29 intcap11 16-bit tmrb input capture 11 30 intcap50 16-bit tmrb input capture 50 31 intcap51 16-bit tmrb input capture 51 32 intcap60 16-bit tmrb input capture 60 33 intcap61 16-bit tmrb input capture 61 34 int6 interrupt pin (pj6/39pin) selectable cgimcgc 35 int7 interrupt pin (pj7/58pin) 36 intrx2 serial reception (channel.2) 37 inttx2 serial transmission (channel.2) 38 intsbi2 serial bus interface 2 39 reserved - TMPM333FDFG/fyfg/fwfg page 65 table 7-3 list of interrupt sources no. interrupt source active level (clearing standby) cg interrupt mode control register 40 inttb7 16-bit tmrb match detection 7 41 inttb8 16-bit tmrb match detection 8 42 inttb9 16-bit tmrb match detection 9 43 intcap20 16-bit tmrb input capture 20 44 intcap21 16-bit tmrb input capture 21 45 intcap30 16-bit tmrb input capture 30 46 intcap31 16-bit tmrb input capture 31 47 intcap40 16-bit tmrb input capture 40 48 intcap41 16-bit tmrb input capture 41 49 intad a/d conversion completion 7.5.1.6 active level the active level indicates which change in signal of an interrupt source triggers an interrupt. the cpu recognizes interrupt signals in "high" level as interrupt. interrupt signals directly sent from peripheral func- tions to the cpu are configured to output "high" to indicate an interrupt request. active level is set to the clock generator for interrupts which can be a trigger to release standby. interrupt requests from peripheral functions are set as rising-edge or falling-edge triggered. interrupt requests from interrupt pins can be set as level-sensitive ("high" or "low") or edge-triggered (rising or falling). if an interrupt source is used for clearing a standby mode, setting the relevant clock generator register is also required. enable the cgimcgx 7.5.2 interrupt handling 7.5.2.1 flowchart the following shows how an interrupt is handled. in the following descriptions, indicates hardware handling. indicates software handling. processing details see settings for detection set the relevant nvic registers for detecting interrupts. set the clock generator as well if each interrupt source is used to clear a standby mode. common setting nvic registers setting to clear standby mode clock generator "7.5.2.2 preparation" settings for sending interrupt signal execute an appropriate setting to send the interrupt signal depending on the in- terrupt type. setting for interrupt from external pin port setting for interrupt from peripheral function peripheral function (see the chapter of each peripheral function for details.) interrupt generation an interrupt request is generated. interrupt lines used for clearing a standby mode are connected to the cpu via the clock generator. "7.5.2.3 detection by clock generator" cpu detects interrupt the cpu detects the interrupt. "7.5.2.4 detection by cpu" if multiple interrupt requests occur simultaneously, the interrupt request with the highest priority is detected according to the priority order. cpu handles interrupt the cpu handles the interrupt. "7.5.2.5 cpu pro- cessing" the cpu pushes register contents to the stack before entering the isr. TMPM333FDFG/fyfg/fwfg page 67 cg detects interrupt (clearing standby mode) clearing standby mode not clearing standby mode processing details see isr execution program for the isr. clear the interrupt source if needed. "7.5.2.6 interrupt service routine (isr)" return to preceding program configure to return to the preceding program of the isr. 7.5.2.2 preparation when preparing for an interrupt, you need to pay attention to the order of configuration to avoid any unexpected interrupt on the way. initiating an interrupt or changing its configuration must be implemented in the following order basically. disable the interrupt by the cpu. configure from the farthest route from the cpu. then enable the interrupt by the cpu. to configure the clock generator, you must follow the order indicated here not to cause any unexpected interrupt. first, configure the precondition. secondly, clear the data related to the interrupt in the clock gen- erator and then enable the interrupt. the following sections are listed in the order of interrupt handling and describe how to configure them. 1. disabling interrupt by cpu 2. cpu registers setting 3. preconfiguration (1) (interrupt from external pin) 4. preconfiguration (2) (interrupt from peripheral function) 5. preconfiguration (3) (interrupt set-pending register) 6. configuring the clock generator 7. enabling interrupt by cpu (1) disabling interrupt by cpu to make the cpu for not accepting any interrupt, write "1" to the corresponding bit of the primask register. all interrupts and exceptions other than non-maskable interrupts and hard faults can be masked. use "msr" instruction to set this register. interrupt mask register primask "1" (interrupt disabled) note 1: primask register cannot be modified by the user access level. note 2: if a fault causes when "1" is set to the primask register, it is treated as a hard fault. (2) cpu registers setting you can assign a priority level by writing to each interrupt source is provided with eight bits for assigning a priority level from 0 to 255, but the number of bits actually used varies with each product.priority level 0 is the highest priority level.if multiple sources have the same priority, the smallest-numbered interrupt source has the highest priority. you can assign grouping priority by using the prigroup field in the application interrupt and reset control register. nvic register before enabling an interrupt, clear the corresponding interrupt request already held. this can avoid unexpected interrupt.to clear corresponding interrupt request, write a value corresponding to the in- terrupt to be used to the cgicrcg register.see "7.6.3.4 cgicrcg(cg interrupt request clear register)" for each value. interrupt requests from external pins can be used without setting the clock generator if they are not used for exiting a standby mode. however, an "high" pulse or "high"-level signal must be input so that the cpu can detect it as an interrupt request. also, be aware of the description of"7.5.1.4 precautions when using external interrupt pins". clock generator register cgimcgn 7.5.2.4 detection by cpu the cpu detects an interrupt request with the highest priority. 7.5.2.5 cpu processing on detecting an interrupt, the cpu pushes the contents of pc, psr, r0-r3, r12 and lr to the stack then enter the isr. 7.5.2.6 interrupt service routine (isr) an isr requires specific programming according to the application to be used. this section describes what is recommended at the service routine programming and how the source is cleared. (1) pushing during isr an isr normally pushes register contents to the stack and handles an interrupt as required. the cortex- m3 core automatically pushes the contents of pc, psr, r0-r3, r12 and lr to the stack. no extra programming is required for them. push the contents of other registers if needed. interrupt requests with higher priority and exceptions such as nmi are accepted even when an isr is being executed. we recommend you to push the contents of general-purpose registers that might be rewritten. (2) clearing an interrupt source if an interrupt source is used for clearing a standby mode, each interrupt request must be cleared with the cg interrupt request clear (cgicrcg) register. if an interrupt source is set as level-sensitive, an interrupt request continues to exist until it is cleared at its source. therefore, the interrupt source must be cleared. clearing the interrupt source automatically clears the interrupt request signal from the clock generator. if an interrupt is set as edge-sensitive, clear an interrupt request by setting the corresponding value in the cgicrcg register. when an active edge occurs again, a new interrupt request will be detected. TMPM333FDFG/fyfg/fwfg page 71 7.6 exception/interrupt-related registers the cpu's nvic registers and clock generator registers described in this chapter are shown below with their respective addresses. 7.6.1 register list nvic registers base address = 0xe000_e000 register name address systick control and status register 0x0010 systick reload value register 0x0014 systick current value register 0x0018 systick calibration value register 0x001c interrupt set-enable register 1 0x0100 interrupt set-enable register 2 0x0104 interrupt clear-enable register 1 0x0180 interrupt clear-enable register 2 0x0184 interrupt set-pending register 1 0x0200 interrupt set-pending register 2 0x0204 interrupt clear-pending register 1 0x0280 interrupt clear-pending register 2 0x0284 interrupt priority register 0x0400 ~ 0x0430 vector table offset register 0x0d08 application interrupt and reset control register 0x0d0c system handler priority register 0x0d18, 0x0d1c, 0x0d20 system handler control and state register 0x0d24 clock generator registers base address = 0x4004_0200 register name address cg interrupt request clear register cgicrcg 0x0014 nmi flag register cgnmiflg 0x0018 reset flag register cgrstflg 0x001c cg interrupt mode control register a cgimcga 0x0020 cg interrupt mode control register b cgimcgb 0x0024 cg interrupt mode control register c cgimcgc 0x0028 reserved - 0x002c reserved - 0x0030 reserved - 0x0034 reserved - 0x0038 reserved - 0x003c note: access to the "reserved" areas is prohibited. TMPM333FDFG/fyfg/fwfg 7. exceptions 7.6 exception/interrupt-related registers page 72 7.6.2 nvic registers 7.6.2.1 systick control and status register 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - countflag after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - clksource tickint enable after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-17 ? r read as 0. 16 countflag r/w 0: timer not counted to 0 1: timer counted to 0 returns "1" if timer counted to "0" since last time this was read. clears on read of any part of the systick control and status register. 15-3 ? r read as 0. 2 clksource r/w 0: external reference clock 1: cpu clock 1 tickint r/w 0: do not pend systick 1: pend systick 0 enable r/w 0: disable 1: enable if "1" is set, it reloads with the value of the reload value register and starts operation. TMPM333FDFG/fyfg/fwfg page 73 7.6.2.2 systick reload value register 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol reload after reset undefined 15 14 13 12 11 10 9 8 bit symbol reload after reset undefined 7 6 5 4 3 2 1 0 bit symbol reload after reset undefined bit bit symbol type function 31-24 ? r read as 0. 23-0 reload r/w reload value set the value to load into the systick current value register when the timer reaches "0". note: in this product, the system timer counts based on a clock obtained by dividing the clock input from the x1 pin by 32. TMPM333FDFG/fyfg/fwfg 7. exceptions 7.6 exception/interrupt-related registers page 74 7.6.2.3 systick current value register 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol current after reset undefined 15 14 13 12 11 10 9 8 bit symbol current after reset undefined 7 6 5 4 3 2 1 0 bit symbol current after reset undefined bit bit symbol type function 31-24 ? r read as 0. 23-0 current r/w [read] current systick timer value [write] clear writing to this register with any value clears it to 0. clearing this register also clears the 7.6.2.4 systick calibration value register 31 30 29 28 27 26 25 24 bit symbol noref skew - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol tenms after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol tenms after reset 0 0 0 0 1 0 0 1 7 6 5 4 3 2 1 0 bit symbol tenms after reset 1 1 0 0 0 1 0 0 bit bit symbol type function 31 noref r 0: reference clock provided 1: no reference clock 30 skew r 0: calibration value is 10 ms. 1: calibration value is not 10 ms. 29-24 ? r read as 0. 23-0 tenms r calibration value reload value to use for 10 ms timing (0x9c4). (note) note: in this product, the system timer counts based on a clock obtained by dividing the clock input from the x1 pin by 32.the systick calibration value register is set to a value that provides 10 ms timing when the cock input from x1 is 8 mhz. TMPM333FDFG/fyfg/fwfg 7. exceptions 7.6 exception/interrupt-related registers page 76 7.6.2.5 interrupt set-enable register 1 31 30 29 28 27 26 25 24 bit symbol setena (interrupt 31) setena (interrupt 30) setena (interrupt 29) setena (interrupt 28) setena (interrupt 27) setena (interrupt 26) setena (interrupt 25) setena (interrupt 24) after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol setena (interrupt 23 setena (interrupt 22) setena (interrupt 21) setena (interrupt 20) setena (interrupt 19) setena (interrupt 18) setena (interrupt 17) setena (interrupt 16) after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol setena (interrupt 15) - - - setena (interrupt 11) setena (interrupt 10) setena (interrupt 9) setena (interrupt 8) after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol setena (interrupt 7) setena (interrupt 6) setena (interrupt 5) setena (interrupt 4) setena (interrupt 3) setena (interrupt 2) setena (interrupt 1) setena (interrupt 0) after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-15 setena r/w interrupt number [31:15] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 14-12 - r/w write "0". 11-0 setena r/w interrupt number [11:0] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. note: for descriptions of interrupts and interrupt numbers, see section "7.5.1.5 list of interrupt sources". TMPM333FDFG/fyfg/fwfg page 77 7.6.2.6 interrupt set-enable register 2 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - setena (interrupt 49) setena (interrupt 48) after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol setena (interrupt 47) setena (interrupt 46) setena (interrupt 45) setena (interrupt 44) setena (interrupt 43) setena (interrupt 42) setena (interrupt 41) setena (interrupt 40) after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - setena (interrupt 38) setena (interrupt 37) setena (interrupt 36) setena (interrupt 35) setena (interrupt 34) setena (interrupt 33) setena (interrupt 32) after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-18 ? r read as 0. 17-8 setena r/w interrupt number [49:40] [write] 1: enable [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 7 ? r/w write "0". 6-0 setena r/w interrupt number [38:32] [write] 1: enable [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. note: for descriptions of interrupts and interrupt numbers, see section "7.5.1.5 list of interrupt sources". TMPM333FDFG/fyfg/fwfg 7. exceptions 7.6 exception/interrupt-related registers page 78 7.6.2.7 interrupt clear-enable register 1 31 30 29 28 27 26 25 24 bit symbol clrena (interrupt 31) clrena (interrupt 30) clrena (interrupt 29) clrena (interrupt 28) clrena (interrupt 27) clrena (interrupt 26) clrena (interrupt 25) clrena (interrupt 24) after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol clrena (interrupt 23) clrena (interrupt 22) clrena (interrupt 21) clrena (interrupt 20) clrena (interrupt 19) clrena (interrupt 18) clrena (interrupt 17) clrena (interrupt 16) after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol clrena (interrupt 15) - - - clrena (interrupt 11) clrena (interrupt 10) clrena (interrupt 9) clrena (interrupt 8) after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol clrena (interrupt 7) clrena (interrupt 6) clrena (interrupt 5) clrena (interrupt 4) clrena (interrupt 3) clrena (interrupt 2) clrena (interrupt 1) clrena (interrupt 0) after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-15 clrena r/w interrupt number [31:15] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 14-12 - r/w write "0". 11-0 clrena r/w interrupt number [11:0] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. note: for descriptions of interrupts and interrupt numbers, see section "7.5.1.5 list of interrupt sources". TMPM333FDFG/fyfg/fwfg page 79 7.6.2.8 interrupt clear-enable register 2 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - clrena (interrupt 49) clrena (interrupt 48) after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol clrena (interrupt 47) clrena (interrupt 46) clrena (interrupt 45) clrena (interrupt 44) clrena (interrupt 43) clrena (interrupt 42) clrena (interrupt 41) clrena (interrupt 40) after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - clrena (interrupt 38) clrena (interrupt 37) clrena (interrupt 36) clrena (interrupt 35) clrena (interrupt 34) clrena (interrupt 33) clrena (interrupt 32) after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-18 ? r read as 0. 17-8 clrena r/w interrupt number [49:40] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 7 - r/w write "0". 6-0 clrena r/w interrupt number [38:32] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. note: for descriptions of interrupts and interrupt numbers, see section "7.5.1.5 list of interrupt sources". TMPM333FDFG/fyfg/fwfg 7. exceptions 7.6 exception/interrupt-related registers page 80 7.6.2.9 interrupt set-pending register 1 31 30 29 28 27 26 25 24 bit symbol setpend (interrupt 31) setpend (interrupt 30) setpend (interrupt 29) setpend (interrupt 28) setpend (interrupt 27) setpend (interrupt 26) setpend (interrupt 25) setpend (interrupt 24) after reset undefined undefined undefined undefined undefined undefined undefined undefined 23 22 21 20 19 18 17 16 bit symbol setpend (interrupt 23) setpend (interrupt 22) setpend (interrupt 21) setpend (interrupt 20) setpend (interrupt 19) setpend (interrupt 18) setpend (interrupt 17) setpend (interrupt 16) after reset undefined undefined undefined undefined undefined undefined undefined undefined 15 14 13 12 11 10 9 8 bit symbol setpend (interrupt 15) - - - setpend (interrupt 11) setpend (interrupt 10) setpend (interrupt 9) setpend (interrupt 8) after reset undefined undefined undefined undefined undefined undefined undefined undefined 7 6 5 4 3 2 1 0 bit symbol setpend (interrupt 7) setpend (interrupt 6) setpend (interrupt 5) setpend (interrupt 4) setpend (interrupt 3) setpend (interrupt 2) setpend (interrupt 1) setpend (interrupt 0) after reset undefined undefined undefined undefined undefined undefined undefined undefined bit bit symbol type function 31-15 setpend r/w interrupt number [31:15] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt clear-pending register clears the bit in this register. 14-12 - r/w write "0". 11-0 setpend r/w interrupt number [11:0] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt clear-pending register clears the bit in this register. note: for descriptions of interrupts and interrupt numbers, see section "7.5.1.5 list of interrupt sources". TMPM333FDFG/fyfg/fwfg page 81 7.6.2.10 interrupt set-pending register 2 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - setpend (interrupt 49) setpend (interrupt 48) after reset 0 0 0 0 0 0 undefined undefined 15 14 13 12 11 10 9 8 bit symbol setpend (interrupt 47) setpend (interrupt 46) setpend (interrupt 45) setpend (interrupt 44) setpend (interrupt 43) setpend (interrupt 42) setpend (interrupt 41) setpend (interrupt 40) after reset undefined undefined undefined undefined undefined undefined undefined undefined 7 6 5 4 3 2 1 0 bit symbol - setpend (interrupt 38) setpend (interrupt 37) setpend (interrupt 36) setpend (interrupt 35) setpend (interrupt 34) setpend (interrupt 33) setpend (interrupt 32) after reset undefined undefined undefined undefined undefined undefined undefined undefined bit bit symbol type function 31-18 ? r read as 0. 17-8 setpend r/w interrupt number [49:40] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. clear and interrupt set-pending register bit by writing "1" to the corresponding bit in the interrupt clear-pending register. 7 - r/w write "0". 6-0 setpend r/w interrupt number [38:32] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. clear and interrupt set-pending register bit by writing "1" to the corresponding bit in the interrupt clear-pending register. note: for descriptions of interrupts and interrupt numbers, see section "7.5.1.5 list of interrupt sources". TMPM333FDFG/fyfg/fwfg 7. exceptions 7.6 exception/interrupt-related registers page 82 7.6.2.11 interrupt clear-pending register 1 31 30 29 28 27 26 25 24 bit symbol clrpend (interrupt 31) clrpend (interrupt 30) clrpend (interrupt 29) clrpend (interrupt 28) clrpend (interrupt 27) clrpend (interrupt 26) clrpend (interrupt 25) clrpend (interrupt 24) after reset undefined undefined undefined undefined undefined undefined undefined undefined 23 22 21 20 19 18 17 16 bit symbol clrpend (interrupt 23) clrpend (interrupt 22) clrpend (interrupt 21) clrpend (interrupt 20) clrpend (interrupt 19) clrpend (interrupt 18) clrpend (interrupt 17) clrpend (interrupt 16) after reset undefined undefined undefined undefined undefined undefined undefined undefined 15 14 13 12 11 10 9 8 bit symbol clrpend (interrupt 15) - - - clrpend (interrupt 11) clrpend (interrupt 10) clrpend (interrupt 9) clrpend (interrupt 8) after reset undefined undefined undefined undefined undefined undefined undefined undefined 7 6 5 4 3 2 1 0 bit symbol clrpend (interrupt 7) clrpend (interrupt 6) clrpend (interrupt 5) clrpend (interrupt 4) clrpend (interrupt 3) clrpend (interrupt 2) clrpend (interrupt 1) clrpend (interrupt 0) after reset undefined undefined undefined undefined undefined undefined undefined undefined bit bit symbol type function 31-15 clrpend r/w interrupt number [31:15] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the corresponding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. 14-12 - r/w write "0". 11-0 clrpend r/w interrupt number [11:0] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the corresponding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. note: for descriptions of interrupts and interrupt numbers, see section "7.5.1.5 list of interrupt sources". TMPM333FDFG/fyfg/fwfg page 83 7.6.2.12 interrupt clear-pending register 2 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - clrpend (interrupt 49) clrpend (interrupt 48) after reset 0 0 0 0 0 0 undefined undefined 15 14 13 12 11 10 9 8 bit symbol clrpend (interrupt 47) clrpend (interrupt 46) clrpend (interrupt 45) clrpend (interrupt 44) clrpend (interrupt 43) clrpend (interrupt 42) clrpend (interrupt 41) clrpend (interrupt 40) after reset undefined undefined undefined undefined undefined undefined undefined undefined 7 6 5 4 3 2 1 0 bit symbol - clrpend (interrupt 38) clrpend (interrupt 37) clrpend (interrupt 36) clrpend (interrupt 35) clrpend (interrupt 34) clrpend (interrupt 33) clrpend (interrupt 32) after reset undefined undefined undefined undefined undefined undefined undefined undefined bit bit symbol type function 31-18 ? r read as 0. 17-8 clrpend r/w interrupt number [49:40] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the corresponding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. 7 - r/w write "0". 6-0 clrpend r/w interrupt number [38:32] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the corresponding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. note: for descriptions of interrupts and interrupt numbers, see section "7.5.1.5 list of interrupt sources". TMPM333FDFG/fyfg/fwfg 7. exceptions 7.6 exception/interrupt-related registers page 84 7.6.2.13 interrupt priority register each interrupt is provided with eight bits of an interrupt priority register. the following shows the addresses of the interrupt priority registers corresponding to interrupt numbers. 31 24 23 16 15 8 7 0 0xe000_e400 pri_3 pri_2 pri_1 pri_0 0xe000_e404 pri_7 pri_6 pri_5 pri_4 0xe000_e408 pri_11 pri_10 pri_9 pri_8 0xe000_e40c pri_15 ? ? ? 0xe000_e410 pri_19 pri_18 pri_17 pri_16 0xe000_e414 pri_23 pri_22 pri_21 pri_20 0xe000_e418 pri_27 pri_26 pri_25 pri_24 0xe000_e41c pri_31 pri_30 pri_29 pri_28 0xe000_e420 pri_35 pri_34 pri_33 pri_32 0xe000_e424 ? pri_38 pri_37 pri_36 0xe000_e428 pri_43 pri_42 pri_41 pri_40 0xe000_e42c pri_47 pri_46 pri_45 pri_44 0xe000_e430 ? ? pri_49 pri_48 the number of bits to be used for assigning a priority varies with each product. this product uses three bits for assigning a priority. the following shows the fields of the interrupt priority registers for interrupt numbers 0 to 3. the interrupt priority registers for all other interrupt numbers have the identical fields. unused bits return "0" when read, and writing to unused bits has no effect. 31 30 29 28 27 26 25 24 bit symbol pri_3 - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol pri_2 - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol pri_1 - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pri_0 - - - - - after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-29 pri_3 r/w priority of interrupt number 3 28-24 ? r read as 0. 23-21 pri_2 r/w priority of interrupt number 2 20-16 ? r read as 0. 15-13 pri_1 r/w priority of interrupt number 1 12-8 ? r read as 0. 7-5 pri_0 r/w priority of interrupt number 0 4-0 ? r read as 0. TMPM333FDFG/fyfg/fwfg page 85 7.6.2.14 vector table offset register 31 30 29 28 27 26 25 24 bit symbol - - tblbase tbloff after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol tbloff after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol tbloff after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol tbloff - - - - - - - after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-30 ? r read as 0. 29 tblbase r/w table base the vector table is in: 0: code space 1: sram space 28-7 tbloff r/w offset value set the offset value from the top of the space specified in tblbase. the offset must be aligned based on the number of exceptions in the table.this means that the minimum alignment is 32 words that you can use for up to 16 interrupts.for more interrupts, you must adjust the alignment by rounding up to the next power of two. 6-0 ? r read as 0. TMPM333FDFG/fyfg/fwfg 7. exceptions 7.6 exception/interrupt-related registers page 86 7.6.2.15 application interrupt and reset control register 31 30 29 28 27 26 25 24 bit symbol vectkey/vectkeystat after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol vectkey/vectkeystat after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol endianess - - - - prigroup after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - sysreset req vectclr active vectreset after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-16 vectkey (write)/ vectkey- stat(read) r/w register key [write] writing to this register requires 0x5fa in the 7.6.2.16 system handler priority register each exception is provided with eight bits of a system handler priority register. the following shows the addresses of the system handler priority registers corresponding to each ex- ception. 31 24 23 16 15 8 7 0 0xe000_ed18 pri_7 pri_6 (usage fault) pri_5 (bus fault) pri_4 (memory management) 0xe000_ed1c pri_11 (svcall) pri_10 pri_9 pri_8 0xe000_ed20 pri_15 (systick) pri_14 (pendsv) pri_13 pri_12 (debug monitor) the number of bits to be used for assigning a priority varies with each product. this product uses three bits for assigning a priority. the following shows the fields of the system handler priority registers for memory management, bus fault and usage fault. unused bits return "0" when read, and writing to unused bits has no effect. 31 30 29 28 27 26 25 24 bit symbol pri_7 - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol pri_6 - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol pri_5 - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pri_4 - - - - - after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-29 pri_7 r/w reserved 28-24 ? r read as 0. 23-21 pri_6 r/w priority of usage fault 20-16 ? r read as 0. 15-13 pri_5 r/w priority of bus fault 12-8 ? r read as 0. 7-5 pri_4 r/w priority of memory management 4-0 ? r read as 0. TMPM333FDFG/fyfg/fwfg 7. exceptions 7.6 exception/interrupt-related registers page 88 7.6.2.17 system handler control and state register 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - usgfault ena busfault ena memfault ena after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol svcall pended busfault pended memfault pended usgfault pended systickact pendsvact - monitor act after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol svcallact - - - usgfault act - busfault act memfault act after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-19 ? r read as 0. 18 usgfault ena r/w usage fault 0: disabled 1: enable 17 busfaul tena r/w bus fault 0: disabled 1: enable 16 memfault ena r/w memory management 0: disabled 1: enable 15 svcall pended r/w svcall 0: not pended 1: pended 14 busfault pended r/w bus fault 0: not pended 1: pended 13 memfault pended r/w memory management 0: not pended 1: pended 12 usgfault pended r/w usage fault 0: not pended 1: pended 11 systickact r/w systick 0: inactive 1: active 10 pendsvact r/w pendsv 0: inactive 1: active 9 ? r read as 0. 8 monitoract r/w debug monitor 0: inactive 1: active 7 svcallact r/w svcall 0: inactive 1: active 6-4 ? r read as 0. TMPM333FDFG/fyfg/fwfg page 89 bit bit symbol type function 3 usgfault act r/w usage fault 0: inactive 1: active 2 ? r read as 0. 1 busfault act r/w bus fault 0: inactive 1: active 0 memfault act r/w memory management 0: inactive 1: active note: you must clear or set the active bits with extreme caution because clearing and setting these bits does not repair stack contents. TMPM333FDFG/fyfg/fwfg 7. exceptions 7.6 exception/interrupt-related registers page 90 7.6.3 clock generator registers 7.6.3.1 cgimcga(cg interrupt mode control register a) 31 30 29 28 27 26 25 24 bit symbol - emcg3 emst3 - int3en after reset 0 0 1 0 0 0 undefined 0 23 22 21 20 19 18 17 16 bit symbol - emcg2 emst2 - int2en after reset 0 0 1 0 0 0 undefined 0 15 14 13 12 11 10 9 8 bit symbol - emcg1 emst1 - int1en after reset 0 0 1 0 0 0 undefined 0 7 6 5 4 3 2 1 0 bit symbol - emcg0 emst0 - int0en after reset 0 0 1 0 0 0 undefined 0 bit bit symbol type function 31 ? r read as 0. 30-28 emcg3[2:0] r/w active level setting of int3 standby clear request. (101~111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edges 27-26 emst3[1:0] r active level of int3 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edges 25 ? r reads as undefined. 24 int3en r/w int3 clear input 0:disable 1: enable 23 ? r read as 0. 22-20 emcg2[2:0] r/w active level setting of int2 standby clear request. (101~111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edges 19-18 emst2[1:0] r active level of int2 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edges 17 ? r reads as undefined. 16 int2en r/w int2 clear input 0:disable 1: enable 15 ? r read as 0. TMPM333FDFG/fyfg/fwfg page 91 bit bit symbol type function 14-12 emcg1[2:0] r/w active level setting of int1 standby clear request. (101~111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edges 11-10 emst1[1:0] r active level of int1 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edges 9 ? r reads as undefined. 8 int1en r/w int1 clear input 0:disable 1: enable 7 ? r read as 0. 6-4 emcg0[2:0] r/w active level setting of int0 standby clear request. (101~111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edges 3-2 emst0[1:0] r active level of int0 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edges 1 ? r reads as undefined. 0 int0en r/w int0 clear input 0:disable 1: enable note 1: 7.6.3.2 cgimcgb(cg interrupt mode control register b) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 1 0 0 0 undefined 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 1 0 0 0 undefined 0 15 14 13 12 11 10 9 8 bit symbol - emcg5 emst5 - int5en after reset 0 0 1 0 0 0 undefined 0 7 6 5 4 3 2 1 0 bit symbol - emcg4 emst4 - int4en after reset 0 0 1 0 0 0 undefined 0 bit bit symbol type function 31 ? r read as 0. 30-28 ? r/w write any value. 27-26 ? r read as 0. 25 ? r reads as undefined. 24 ? r/w write "0". 23 ? r read as 0. 22-20 ? r/w write any value. 19-18 ? r read as 0. 17 ? r reads as undefined. 16 ? r/w write "0". 15 ? r read as 0. 14-12 emcg5[2:0] r/w active level setting of int5 standby clear request (101~111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edges 11-10 emst5[1:0] r active level of int5 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edges 9 ? r reads as undefined. 8 int5en r/w int5 clear input 0:disable 1: enable 7 ? r read as 0. 6-4 emcg4[2:0] r/w active level setting of int4 standby clear request (101~111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edges 3-2 emst4[1:0] r active level of int4 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edges 1 ? r reads as undefined. TMPM333FDFG/fyfg/fwfg page 93 bit bit symbol type function 0 int4en r/w int4 clear input 0:disable 1: enable note 1: 7.6.3.3 cgimcgc(cg interrupt mode control register c) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 1 0 0 0 undefined 0 23 22 21 20 19 18 17 16 bit symbol - emcga emsta - intaen after reset 0 0 1 0 0 0 undefined 0 15 14 13 12 11 10 9 8 bit symbol - emcg9 emst9 - int9en after reset 0 0 1 0 0 0 undefined 0 7 6 5 4 3 2 1 0 bit symbol - emcg8 emst8 - int8en after reset 0 0 1 0 0 0 undefined 0 bit bit symbol type function 31 ? r read as 0. 30-28 ? r/w write any value. 27-26 ? r read as 0. 25 ? r reads as undefined. 24 ? r/w write "0". 23 ? r read as 0. 22-20 emcga[2:0] r/w active level setting of int7 standby clear request. (101~111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edges 19-18 emsta[1:0] r active level of int7 standby clear request. 00: ? 01: rising edge 10: falling edge 11: both edges 17 ? r reads as undefined. 16 intaen r/w int7clear input 0:disable 1: enable 15 ? r read as 0. 14-12 emcg9[2:0] r/w active level setting of int6 standby clear request. (101~111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edges 11-10 emst9[1:0] r active level of int6 standby clear request. 00: ? 01: rising edge 10: falling edge 11: both edges 9 ? r reads as undefined. 8 int9en r/w int6 clear input 0:disable 1: enable 7 ? r read as 0. TMPM333FDFG/fyfg/fwfg page 95 bit bit symbol type function 6-4 emcg8[2:0] r/w active level setting of intrtc standby clear request. set it as shown below. 010: falling edge 3-2 emst8[1:0] r active level of intrtc standby clear request. 00: ? 01: rising edge 10: falling edge 11: both edges 1 ? r reads as undefined. 0 int8en r/w intrtc clear input 0:disable 1: enable note 1: 7.6.3.4 cgicrcg(cg interrupt request clear register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - icrcg after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-5 ? r read as 0. 4-0 icrcg[4:0] w clear interrupt requests. 0_0000: int0 0_0001: int1 0_0010: int2 0_0011: int3 0_0100: int4 0_0101: int5 0_0110: reserved 0_0111: reserved 0_1000: intrtc 0_1001: int6 0_1010: int7 0_1011 to 1_1111: setting prohibited. read as 0. TMPM333FDFG/fyfg/fwfg page 97 7.6.3.5 cgnmiflg(nmi flag register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - nmiflg1 nmiflg0 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-2 ? r read as 0. 1 nmiflg1 r nmi source generation flag 0: not applicable 1: generated from nmi pin 0 nmiflg0 r nmi source generation flag 0: not applicable 1: generated from wdt note: 7.6.3.6 cgrstflg (reset flag register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after pin reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after pin reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after pin reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - sysrstf - wdtrstf pinrstf ponrstf after pin reset 0 0 0 0 0 0 1 1 / 0 bit bit symbol type function 31-5 ? r read as 0. 4 sysrstf r/w debug reset flag(note1) 0: "0" is written 1: reset from sysresetreq 3 ? r/w write as 0. 2 wdtrstf r/w wdt reset flag 0: "0" is written 1: reset from wdt 1 pinrstf r/w reset pin flag 0: "0" is written 1: reset from reset pin 0 ponrstf r/w power-on flag 0: "0" is written 1: "1" is set to this bit in initial reset state right after power-on. note 1: this flag indicates a reset generated by the sysresetreq bit of the application interrupt and reset control register of the cpu's nvic. note 2: this register is not cleared automatically. write "0" to clear the register. TMPM333FDFG/fyfg/fwfg page 99 TMPM333FDFG/fyfg/fwfg 7. exceptions 7.6 exception/interrupt-related registers page 100 8. input/output ports 8.1 port functions 8.1.1 function lists TMPM333FDFG/fyfg/fwfg has 78 ports. besides the ports function, these ports can be used as i/o pins for peripheral functions. table 8-1, table 8-2 and table 8-3 show the port function table. table 8-1 port function list (port a-port c) port pin input/ output pull-up pull-down schmitt input noise filter program- mable open-drain function pin port a pa0 i/o pull-up ? ? tms/ swdio pa1 i/o pull-down ? ? ? tck/ swclk pa2 i/o pull-up ? ? ? traceclk pa3 i/o pull-up ? ? ? tracedata0 pa4 i/o pull-up ? ? ? tracedata1 pa5 i/o pull-up ? ? ? tracedata2 pa6 i/o pull-up ? ? ? tracedata3 pa7 i/o pull-up ? ? ? ? port b pb0 i/o pull-up ? ? ? tdo/ swv pb1 i/o pull-up ? ? ? tdi pb2 i/o pull-up ? ? trst pb3 i/o pull-up ? ? ? ? pb4 i/o pull-up ? ? ? ? pb5 i/o pull-up ? ? ? ? pb6 i/o pull-up ? ? ? ? pb7 i/o pull-up ? ? ? ? port c pc0 input pull-up ? ? ? ain0 pc1 input pull-up ? ? ? ain1 pc2 input pull-up ? ? ? ain2 pc3 input pull-up ? ? ? ain3 : exist - : not exist note:the noise elimination width of the noise filter is approximately 30 ns under typical conditions. TMPM333FDFG/fyfg/fwfg page 101 table 8-2 port function list (port d-port g) port pin input/out- put pull-up pull-down schmitt input noise filter program- mable open-drain function pin port d pd0 input pull-up ? ? ? ain4, tb5in0 pd1 input pull-up ? ? ? ain5, tb5in1 pd2 input pull-up ? ? ? ain6, tb6in0 pd3 input pull-up ? ? ? ain7, tb6in1 pd4 input pull-up ? ? ? ain8 pd5 input pull-up ? ? ? ain9 pd6 input pull-up ? ? ? ain10 pd7 input pull-up ? ? ? ain11 port e pe0 i/o pull-up ? ? txd0 pe1 i/o pull-up ? rxd0 pe2 i/o pull-up ? sclk0, cts0 pe3 i/o pull-up ? ? pe4 i/o pull-up ? ? txd1 pe5 i/o pull-up ? rxd1 pe6 i/o pull-up ? sclk1, cts1 port f pf0 i/o pull-up ? ? txd2 pf1 i/o pull-up ? rxd2 pf2 i/o pull-up ? sclk2, cts2 pf3 i/o pull-up ? ? pf4 i/o pull-up ? sda1/ so1 pf5 i/o pull-up ? scl1/ si1 pf6 i/o pull-up ? sck1 pf7 i/o pull-up int5 port g pg0 i/o pull-up ? sda0/ so0 pg1 i/o pull-up ? scl0/ si0 pg2 i/o pull-up ? sck0 pg3 i/o pull-up int4 pg4 i/o pull-up ? sda2/ so2 pg5 i/o pull-up ? scl2/ si2 pg6 i/o pull-up ? sck2 pg7 i/o pull-up ? ? tb8out : exist - : not exist note:the noise elimination width of the noise filter is approximately 30 ns under typical conditions. TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.1 port functions page 102 table 8-3 port function list (port h-port k) port pin input/out- put pull-up pull-down schmitt input noise filter program- mable open-drain function pin port h ph0 i/o pull-up ? ? tb0in0, boot ph1 i/o pull-up ? ? tb0in1 ph2 i/o pull-up ? ? tb1in0 ph3 i/o pull-up ? ? tb1in1 ph4 i/o pull-up ? ? tb2in0 ph5 i/o pull-up ? ? tb2in1 ph6 i/o pull-up ? ? tb3in0 ph7 i/o pull-up ? ? tb3in1 port i pi0 i/o pull-up ? ? ? tb0out pi1 i/o pull-up ? ? ? tb1out pi2 i/o pull-up ? ? ? tb2out pi3 i/o pull-up ? ? ? tb3out pi4 i/o pull-up ? ? ? tb4out pi5 i/o pull-up ? ? ? tb5out pi6 i/o pull-up ? ? tb4in0 pi7 i/o pull-up ? ? tb4in1 port j pj0 i/o pull-up ? int0 pj1 i/o pull-up ? int1 pj2 i/o pull-up ? int2 pj3 i/o pull-up ? int3 pj4 i/o pull-up ? ? ? tb6out pj5 i/o pull-up ? ? ? tb7out pj6 i/o pull-up ? int6 pj7 i/o pull-up ? int7 port k pk0 i/o ? ? (note1) ? pk1 i/o pull-up ? ? ? scout, alarm pk2 i/o pull-up ? ? ? tb9out : exist - : not exist note 1: n-ch open drain port. note 2: the noise elimination width of the noise filter is approximately 30 ns under typical conditions. TMPM333FDFG/fyfg/fwfg page 103 8.1.2 port registers outline the following registers need to be configured to use ports. ? ? ? ? ? ? ? 8. input/output ports 8.1 port functions page 104 8.1.3 port states in stop mode input and output in stop mode are enabled/disabled by the cgstbycr 8.2 port functions this chapter describes the port registers detail. this chapter describes only "circuit type" reading circuit configuration.for detailed circuit diagram, refer to "8.3 block diagrams of ports". 8.2.1 port a (pa0 to pa7) the port a is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose input/output function, the port a performs the debug interface and the debug trace output. pa0 and pa1 are assigned as the debug interface after reset. pa0 is initialized as the tms/swdio pin with input, output and pull-up enabled. pa1 is initialized as the tck/swclk pin with input and pull-down enabled. pins from pa2 to pa7 operate as general-purpose-ports, and input, output and pull-up are disabled. note 1: if pa0 is configured as the tms/swdio pin, output is enabled even in stop mode regardless of the cgstbycr 8.2.1.3 padata (port a data register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pa7-pa0 r/w port a data register. 8.2.1.4 pacr (port a output control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pa7c pa6c pa5c pa4c pa3c pa2c pa1c pa0c after reset 0 0 0 0 0 0 0 1 bit bit symbol type function 31-8 ? r read as 0. 7-0 pa7c-pa0c r/w output 0: disable 1: enable TMPM333FDFG/fyfg/fwfg page 107 8.2.1.5 pafr1 (port a function register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - pa6f1 pa5f1 pa4f1 pa3f1 pa2f1 pa1f1 pa0f1 after reset 0 0 0 0 0 0 1 1 bit bit symbol type function 31-7 ? r read as 0. 6 pa6f1 r/w 0: port 1: tracedata3 5 pa5f1 r/w 0: port 1: tracedata2 4 pa4f1 r/w 0: port 1: tracedata1 3 pa3f1 r/w 0: port 1: tracedata0 2 pa2f1 r/w 0: port 1: traceclk 1 pa1f1 r/w 0: port 1: tck/swclk 0 pa0f1 r/w 0: port 1: tms/swdio TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 108 8.2.1.6 papup (port a pull-up control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pa7up pa6up pa5up pa4up pa3up pa2up - pa0up after reset 0 0 0 0 0 0 0 1 bit bit symbol type function 31-8 ? r read as 0. 7-2 pa7up-pa2up r/w pull-up 0: disable 1: enable 1 ? r read as 0. 0 pa0up r/w pull-up 0:disable 1:enable 8.2.1.7 papdn (port a pull-down control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - pa1dn - after reset 0 0 0 0 0 0 1 0 bit bit symbol type function 31-2 ? r read as 0. 1 pa1dn r/w pull-down 0: disable 1: enable 0 ? r read as 0. TMPM333FDFG/fyfg/fwfg page 109 8.2.1.8 paie (port a input control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pa7ie pa6ie pa5ie pa4ie pa3ie pa2ie pa1ie pa0ie after reset 0 0 0 0 0 0 1 1 bit bit symbol type function 31-8 ? r read as 0. 7-0 pa7ie-pa0ie r/w input 0: disable 1: enable TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 110 8.2.2 port b (pb0 to pb7) the port b is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose input/output function, the port b performs the debug interface. reset configures pb0, pb1 and pb2 as debug interface.pb0 is initialized as the tdo/swv pin with output enabled. pb1 is initialized as the tdi pin with input and pull-up enabled. pb2 is initialized as the trst pin with input and pull-up enabled.pb3 to pb7 are initialized as general-purpose ports with input, output and pull-up disabled. note:if pb0 is configured as the tdo/swv pin, output is enabled even in stop mode regardless of the cgstbycr 8.2.2.3 pbdata (port b data register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pb7-pb0 r/w port b data register. 8.2.2.4 pbcr (port b output control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pb7c pb6c pb5c pb4c pb3c pb2c pb1c pb0c after reset 0 0 0 0 0 0 0 1 bit bit symbol type function 31-8 ? r read as 0. 7-0 pb7c-pb0c r/w output 0: disable 1: enable TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 112 8.2.2.5 pbfr1 (port b function register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - pb2f1 pb1f1 pb0f1 after reset 0 0 0 0 0 1 1 1 bit bit symbol type function 31-3 ? r read as 0. 2 pb2f1 r/w 0: port 1: trst 1 pb1f1 r/w 0: port 1: tdi 0 pb0f1 r/w 0: port 1: tdo/swv TMPM333FDFG/fyfg/fwfg page 113 8.2.2.6 pbpup (port b pull-up control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pb7up pb6up pb5up pb4up pb3up pb2up pb1up pb0up after reset 0 0 0 0 0 1 1 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pb7up-pb0up r/w pull-up 0: disable 1: enable 8.2.2.7 pbie (port b input control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pb7ie pb6ie pb5ie pb4ie pb3ie pb2ie pb1ie pb0ie after reset 0 0 0 0 0 1 1 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pb7ie-pb0ie r/w input 0: disable 1: enable TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 114 8.2.3 port c (pc0 to pc3) the port c is a 4-bit input port. besides the general-purpose input function, the port c functions as analog input pins of the ad converter. reset initializes all bits of the port c as general-purpose input ports with input and pull-up disabled. to use the port c as an analog input of the ad converter, disable input on pcie and disable pull-up on pcpup. note:unless you use all the bits of port c and port d as analog input pins, conversion accuracy may be reduced. be sure to verify that this causes no problem on your system. 8.2.3.1 port c circuit type 7 6 5 4 3 2 1 0 type ? ? ? ? t17 t17 t17 t17 8.2.3.2 port c register base address = 0x4000_0080 register name address (base+) port c data register pcdata 0x0000 port c pull-up control register pcpup 0x002c port c input control register pcie 0x0038 TMPM333FDFG/fyfg/fwfg page 115 8.2.3.3 pcdata (port c data register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - pc3 pc2 pc1 pc0 after reset 0 0 0 0 1 1 1 1 bit bit symbol type function 31-4 ? r read as 0. 3-0 pc3-pc0 r port c data register. 8.2.3.4 pcpup (port c pull-up control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - pc3up pc2up pc1up pc0up after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-4 ? r read as 0. 3-0 pc3up-pc0up r/w pull-up 0: disable 1: enable TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 116 8.2.3.5 pcie (port c input control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - pc3ie pc2ie pc1ie pc0ie after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-4 ? r read as 0. 3-0 pc3ie-pc0ie r/w input 0: disable 1: enable TMPM333FDFG/fyfg/fwfg page 117 8.2.4 port d (pd0 to pd7) the port d is an 8-bit input port. besides the general-purpose input function, the port d receives an analog input of the ad converter and a 16-bit timer input. reset initializes all bits of the port d as general-purpose input ports with input and pull-up disabled. set the pdfr1 and pdie when you use the port d as input pins of the 16-bit timer. to use the port d as an analog input of the ad converter, disable input on pdie and disable pull-up on pdpup. note:unless you use all the bits of port c and port d as analog input pins, conversion accuracy may be reduced. be sure to verify that this causes no problem on your system. 8.2.4.1 port d circuit type 7 6 5 4 3 2 1 0 type t17 t17 t17 t17 t18 t18 t18 t18 8.2.4.2 port d register base address = 0x4000_00c0 register name address (base+) port d data register pddata 0x0000 port d function register 1 pdfr1 0x0008 port d pull-up control register pdpup 0x002c port d input control register pdie 0x0038 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 118 8.2.4.3 pddata (port d data register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 after reset 1 1 1 1 1 1 1 1 bit bit symbol type function 31-8 ? r read as 0. 7-0 pd7-pd0 r port d data register. 8.2.4.4 pdfr1 (port d function register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - pd3f1 pd2f1 pd1f1 pd0f1 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-4 ? r read as 0. 3 pd3f1 r/w 0: port 1: tb6in1 2 pd2f1 r/w 0: port 1: tb6in0 1 pd1f1 r/w 0: port 1: tb5in1 0 pd0f1 r/w 0: port 1: tb5in0 TMPM333FDFG/fyfg/fwfg page 119 8.2.4.5 pdpup (port d pull-up control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pd7up pd6up pd5up pd4up pd3up pd2up pd1up pd0up after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pd7up-pd0up r/w pull-up 0: disable 1: enable 8.2.4.6 pdie (port d input control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pd7ie pd6ie pd5ie pd4ie pd3ie pd2ie pd1ie pd0ie after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pd7ie-pd0ie r/w input 0: disable 1: enable TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 120 8.2.5 port e (pe0 to pe6) the port e is a general-purpose, 7-bit input/output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose port function, the port e performs the serial interface function. reset initializes all bits of the port e as general-purpose ports with input, output and pull-up disabled. the port e has two types of function register. if you use the port e as a general-purpose port, set "0" to the corresponding bit of the two registers. if you use the port e as other than a general-purpose port, set "1" to the corresponding bit of the function register. do not set "1" to the both function registers at the same time. 8.2.5.1 port e circuit type 7 6 5 4 3 2 1 0 type ? t16 t4 t10 t4 t16 t4 t10 8.2.5.2 port e register base address = 0x4000_0100 register name address (base+) port e data register pedata 0x0000 port e output control register pecr 0x0004 port e function register 1 pefr1 0x0008 port e function register 2 pefr2 0x000c port e open drain control register peod 0x0028 port e pull-up control register pepup 0x002c port e input control register peie 0x0038 TMPM333FDFG/fyfg/fwfg page 121 8.2.5.3 pedata (port e data register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - pe6 pe5 pe4 pe3 pe2 pe1 pe0 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-7 ? r read as 0. 6-0 pe6-pe0 r/w port e data register 8.2.5.4 pecr (port e output control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - pe6c pe5c pe4c pe3c pe2c pe1c pe0c after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-7 ? r read as 0. 6-0 pe6c-pe0c r/w output 0: disable 1: enable TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 122 8.2.5.5 pefr1(port e function register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - pe6f1 pe5f1 pe4f1 pe3f1 pe2f1 pe1f1 pe0f1 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-7 ? r read as 0. 6 pe6f1 r/w 0: port 1: sclk1 5 pe5f1 r/w 0: port 1: rxd1 4 pe4f1 r/w 0: port 1: txd1 3 pe3f1 r/w 0: port 1: reserved 2 pe2f1 r/w 0: port 1: sclk0 1 pe1f1 r/w 0: port 1: rxd0 0 pe0f1 r/w 0: port 1: txd0 TMPM333FDFG/fyfg/fwfg page 123 8.2.5.6 pefr2(port e function register 2) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - pe6f2 - - - pe2f2 - - after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-7 ? r read as 0. 6 pe6f2 r/w 0: port 1: cts1 5-3 ? r read as 0. 2 pe2f2 r/w 0: port 1: cts0 1-0 ? r read as 0. 8.2.5.7 peod (port e open drain control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - pe6od pe5od pe4od pe3od pe2od pe1od pe0od after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-7 ? r read as 0. 6-0 pe6od- pe0od r/w 0: cmos 1: open-drain TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 124 8.2.5.8 pepup (port e pull-up control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - pe6up pe5up pe4up pe3up pe2up pe1up pe0up after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-7 ? r read as 0. 6-0 pe6up-pe0up r/w pull-up 0: disable 1: enable 8.2.5.9 peie (port e input control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - pe6ie pe5ie pe4ie pe3ie pe2ie pe1ie pe0ie after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-7 ? r read as 0. 6-0 pe6ie-pe0ie r/w input 0: disable 1: enable TMPM333FDFG/fyfg/fwfg page 125 8.2.6 port f (pf0 to pf7) the port f is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose port function, the port f performs the functions of the serial interface, the serial bus interface and the external interrupt input. reset initializes all bits of the port f as general-purpose ports with input, output and pull-up disabled. the port f has two types of function register. if you use the port f as a general-purpose port, set "0" to the corresponding bit of the two registers. if you use the port f as other than a general-purpose port, set "1" to the corresponding bit of the function register. do not set "1" to the both function registers at the same time. to use the external interrupt input for releasing stop mode, select this function in the pffr1 and enable input in the pfie register. these settings enable the interrupt input even if the cgstbycr 8.2.6.3 pfdata (port f data register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pf7-pf0 r/w port f data register 8.2.6.4 pfcr (port f output control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pf7c pf6c pf5c pf4c pf3c pf2c pf1c pf0c after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pf7c-pf0c r/w output 0: disable 1: enable TMPM333FDFG/fyfg/fwfg page 127 8.2.6.5 pffr1(port f function register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pf7f1 pf6f1 pf5f1 pf4f1 pf3f1 pf2f1 pf1f1 pf0f1 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7 pf7f1 r/w 0: port 1: int5 6 pf6f1 r/w 0: port 1: sck1 5 pf5f1 r/w 0: port 1: si1/scl1 4 pf4f1 r/w 0: port 1: so1/sda1 3 pf3f1 r/w 0: port 1: reserved 2 pf2f1 r/w 0: port 1: sclk2 1 pf1f1 r/w 0: port 1: rxd2 0 pf0f1 r/w 0: port 1: txd2 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 128 8.2.6.6 pffr2(port f function register 2) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - pf2f2 - - after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-3 ? r read as 0. 2 pf2f2 r/w 0: port 1: cts2 1-0 ? r read as 0. 8.2.6.7 pfod (port f open drain control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pf7od pf6od pf5od pf4od pf3od pf2od pf1od pf0od after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pf7od-pf0od r/w 0: cmos 1: open-drain TMPM333FDFG/fyfg/fwfg page 129 8.2.6.8 pfpup (port f pull-up control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pf7up pf6up pf5up pf4up pf3up pf2up pf1up pf0up after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pf7up-pf0up r/w pull-up 0: disable 1: enable 8.2.6.9 pfie (port f input control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pf7ie pf6ie pf5ie pf4ie pf3ie pf2ie pf1ie pf0ie after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pf7ie-pf0ie r/w input 0: disable 1: enable TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 130 8.2.7 port g (pg0 to pg7) the port g is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose port function, the port g performs the functions of the serial bus interface, the external interrupt input, and the 16-bit timer output. reset initializes all bits of the port g as general-purpose ports with input, output and pull-up disabled. to use the external interrupt input for releasing stop mode, select function in the pgfr register and enable input in the pgie register. these settings enable the interrupt input even if the cgstbycr 8.2.7.3 pgdata (port g data register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pg7-pg0 r/w port g data register. 8.2.7.4 pgcr (port g output control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pg7c pg6c pg5c pg4c pg3c pg2c pg1c pg0c after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pg7c-pg0c r/w output 0: disable 1: enable TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 132 8.2.7.5 pgfr1(port g function register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pg7f1 pg6f1 pg5f1 pg4f1 pg3f1 pg2f1 pg1f1 pg0f1 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7 pg7f1 r/w 0: port 1: tb8out 6 pg6f1 r/w 0: port 1: sck2 5 pg5f1 r/w 0: port 1: si2/scl2 4 pg4f1 r/w 0: port 1: so2/sda2 3 pg3f1 r/w 0: port 1: int4 2 pg2f1 r/w 0: port 1: sck0 1 pg1f1 r/w 0: port 1: si0/scl0 0 pg0f1 r/w 0: port 1: so0/sda0 TMPM333FDFG/fyfg/fwfg page 133 8.2.7.6 pgod (port g open drain control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pg7od pg6od pg5od pg4od pg3od pg2od pg1od pg0od after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pg7od- pg0od r/w 0: cmos 1: open-drain 8.2.7.7 pgpup (port g pull-up control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pg7up pg6up pg5up pg4up pg3up pg2up pg1up pg0up after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pg7up- pg0up r/w pull-up 0: disable 1: enable TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 134 8.2.7.8 pgie (port g input control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pg7ie pg6ie pg5ie pg4ie pg3ie pg2ie pg1ie pg0ie after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pg7ie-pg0ie r/w input 0: disable 1: enable TMPM333FDFG/fyfg/fwfg page 135 8.2.8 port h (ph0 to ph7) the port h is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose port function, the port h performs the functions of the 16-bit timer input and the operation mode setting. while a reset signal is in "low" state, the 8.2.8.1 port h circuit type 7 6 5 4 3 2 1 0 type t3 t3 t3 t3 t3 t3 t3 t5 8.2.8.2 port h register base address = 0x4000_01c0 register name address (base+) port h data register phdata 0x0000 port h output control register phcr 0x0004 port h function register 1 phfr1 0x0008 reserved - 0x0010 port h pull-up control register phpup 0x002c port h input control register phie 0x0038 note:access to the "reserved" areas is prohibited. TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 136 8.2.8.3 phdata (port h data register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 ph7-ph0 r/w port h data register. 8.2.8.4 phcr (port h output control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol ph7c ph6c ph5c ph4c ph3c ph2c ph1c ph0c after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 ph7c-ph0c r/w output 0: disable 1: enable TMPM333FDFG/fyfg/fwfg page 137 8.2.8.5 phfr1(port h function register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol ph7f1 ph6f1 ph5f1 ph4f1 ph3f1 ph2f1 ph1f1 ph0f1 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7 ph7f1 r/w 0: port 1: tb3in1 6 ph6f1 r/w 0: port 1: tb3in0 5 ph5f1 r/w 0: port 1: tb2in1 4 ph4f1 r/w 0: port 1: tb2in0 3 ph3f1 r/w 0: port 1: tb1in1 2 ph2f1 r/w 0: port 1: tb1in0 1 ph1f1 r/w 0: port 1: tb0in1 0 ph0f1 r/w 0: port 1: tb0in0 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 138 8.2.8.6 phpup (port h pull-up control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol ph7up ph6up ph5up ph4up ph3up ph2up ph1up ph0up after reset 0 0 0 0 0 0 0 1 bit bit symbol type function 31-8 ? r read as 0. 7-0 ph7up-ph0up r/w pull-up 0: disable 1: enable 8.2.8.7 phie (port h input control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol ph7ie ph6ie ph5ie ph4ie ph3ie ph2ie ph1ie ph0ie after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 ph7ie-ph0ie r/w input 0: disable 1: enable TMPM333FDFG/fyfg/fwfg page 139 8.2.9 port i (pi0 to pi7) the port i is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose port function, the port i performs the 16-bit timer input/output function. reset initializes all bits of the port i as general-purpose ports with input, output and pull-up disabled. 8.2.9.1 port i circuit type 7 6 5 4 3 2 1 0 type t3 t3 t9 t9 t9 t9 t9 t9 8.2.9.2 port i register base address = 0x4000_0200 register name address (base+) port i data register pidata 0x0000 port i output control register picr 0x0004 port i function register 1 pifr1 0x0008 reserve - 0x0010 port i pull-up control register pipup 0x002c port i input control register piie 0x0038 note:access to the "reserved" areas is prohibited. TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 140 8.2.9.3 pidata(port i data register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pi7 pi6 pi5 pi4 pi3 pi2 pi1 pi0 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pi7-pi0 r/w port i data register. 8.2.9.4 picr (port i output control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pi7c pi6c pi5c pi4c pi3c pi2c pi1c pi0c after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pi7c-pi0c r/w output 0: disable 1: enable TMPM333FDFG/fyfg/fwfg page 141 8.2.9.5 pifr1(port i function register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pi7f1 pi6f1 pi5f1 pi4f1 pi3f1 pi2f1 pi1f1 pi0f1 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7 pi7f1 r/w 0: port 1: tb4in1 6 pi6f1 r/w 0: port 1: tb4in0 5 pi5f1 r/w 0: port 1: tb5out 4 pi4f1 r/w 0: port 1: tb4out 3 pi3f1 r/w 0: port 1: tb3out 2 pi2f1 r/w 0: port 1: tb2out 1 pi1f1 r/w 0: port 1: tb1out 0 pi0f1 r/w 0: port 1: tb0out TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 142 8.2.9.6 pipup (port i pull-up control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pi7up pi6up pi5up pi4up pi3up pi2up pi1up pi0up after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pi7up-pi0up r/w pull-up 0: disable 1: enable 8.2.9.7 piie (port i input control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pi7ie pi6ie pi5ie pi4ie pi3ie pi2ie pi1ie pi0ie after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pi7ie-pi0ie r/w input 0: disable 1: enable TMPM333FDFG/fyfg/fwfg page 143 8.2.10 port j (pj0 to pj7) the port j is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose port function, the port j performs the functions of the 16-bit timer output and the external interrupt input. reset initializes all bits of the port j as to perform as the general-purpose ports with input, output and pull-up disabled. to use the external interrupt input for releasing stop mode, select this function in the pjfr1 register and enable input in the pjie register. these settings enable the interrupt input even if the cgstbycr 8.2.10.3 pjdata (port j data register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pj7-pj0 r/w port j data register. 8.2.10.4 pjcr (port j output control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pj7c pj6c pj5c pj4c pj3c pj2c pj1c pj0c after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pj7c-pj0c r/w output 0: disable 1: enable TMPM333FDFG/fyfg/fwfg page 145 8.2.10.5 pjfr1(port j function register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pj7f1 pj6f1 pj5f1 pj4f1 pj3f1 pj2f1 pj1f1 pj0f1 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7 pj7f1 r/w 0: port 1: int7 6 pj6f1 r/w 0: port 1: int6 5 pj5f1 r/w 0: port 1: tb7out 4 pj4f1 r/w 0: port 1: tb6out 3 pj3f1 r/w 0: port 1: int3 2 pj2f1 r/w 0: port 1: int2 1 pj1f1 r/w 0: port 1: int1 0 pj0f1 r/w 0: port 1: int0 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 146 8.2.10.6 pjpup (port j pull-up control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pj7up pj6up pj5up pj4up pj3up pj2up pj1up pj0up after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pj7up-pj0up r/w pull-up 0: disable 1: enable 8.2.10.7 pjie (port j input control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol pj7ie pj6ie pj5ie pj4ie pj3ie pj2ie pj1ie pj0ie after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 pj7ie-pj0ie r/w input 0: disable 1: enable TMPM333FDFG/fyfg/fwfg page 147 8.2.11 port k (pk0 to pk2) the port k is a general-purpose, 3-bit input/output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose port function, the port k performs the functions of the 16-bit timer output, the clock output and the alarm output. reset initializes all bits of the port k as general-purpose ports with input, output and pull-up disabled. note:pk0 is an n-ch open drain port. 8.2.11.1 port k circuit type 7 6 5 4 3 2 1 0 type ? ? ? ? ? t9 t15 t14 8.2.11.2 port k register base address = 0x4000_0280 register name address (base+) port k data register pkdata 0x0000 port k output control register pkcr 0x0004 port k function register 1 pkfr1 0x0008 port k function register 2 pkfr2 0x000c port k pull-up control register pkpup 0x002c port k input control register pkie 0x0038 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 148 8.2.11.3 pkdata(port k data register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - pk2 pk1 pk0 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-3 ? r read as 0. 2-0 pk2-pk0 r/w port k data register. 8.2.11.4 pkcr (port k output control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - pk2c pk1c pk0c after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-3 ? r read as 0. 2-0 pk2c-pk0c r/w output 0: disable 1: enable TMPM333FDFG/fyfg/fwfg page 149 8.2.11.5 pkfr1(port k function register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - pk2f1 pk1f1 pk0f1 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-3 ? r read as 0. 2 pk2f1 r/w 0: port 1: tb9out 1 pk1f1 r/w 0: port 1: scout 0 pk0f1 r/w 0: port 1: reserved TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 150 8.2.11.6 pkfr2(port k function register 2) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - pk1f2 - after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-2 ? r read as 0. 1 pk1f2 r/w 0: port 1: alarm 0 ? r read as 0. 8.2.11.7 pkpup (port k pull-up control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - pk2up pk1up - after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-3 ? r read as 0. 2-1 pk2up-pk1up r/w pull-up 0: disable 1: enable 0 ? r read as 0. TMPM333FDFG/fyfg/fwfg page 151 8.2.11.8 pkie (port k input control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - pk2ie pk1ie pk0ie after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-3 ? r read as 0. 2-0 pk2ie-pk0ie r/w input 0: disable 1: enable TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.2 port functions page 152 8.3 block diagrams of ports 8.3.1 port types the ports are classified as shown below. please refer to the following pages for the block diagrams of each port type. dot lines in the figure indicate the part of the equivalent circuit described in the "block diagrams of ports". table 8-5 function lists type gp port function 1 function 2 analog pull-up pull-down programma- ble open-drain note t1 i/o ? ? ? r ? ? t2 i/o input ? ? nor ? ? t3 i/o input ? ? r ? ? t4 i/o input ? ? r ? t5 i/o input ? ? nor ? ? boot input enabled during reset t6 i/o input ? ? ? nor ? t7 i/o input (int) ? ? r ? ? t8 i/o input (int) ? ? r ? t9 i/o output ? ? r ? ? t10 i/o output ? ? r ? t11 i/o output ? ? r ? ? function output triggered by enable signal t12 i/o i/o ? ? nor ? ? function output triggered by enable signal t13 i/o i/o ? ? r ? t14 i/o i/o ? ? ? ? ? nch open drain port t15 i/o output output ? r ? ? t16 i/o i/o input ? r ? t17 input ? ? r ? ? t18 input input ? r ? ? int: interrupt input ?: not exist : exist r: forced disable during reset. nor: unaffected by reset. TMPM333FDFG/fyfg/fwfg page 153 8.3.2 type t1 figure 8-1 port type t1 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.3 block diagrams of ports page 154 pxpup (pull-up control) pxcr (output controll) pxdata (output latch) pxie (input control) reset i/o port drive disable in stop mode (set by 8.3.3 type t2 figure 8-2 port type t2 TMPM333FDFG/fyfg/fwfg page 155 pxpup (pull-up control) pxcr (output control) pxdata (output latch) pxie (input control) reset i/o port port read pxfr1 (function control) 0 1 function input drive disable in stop mode set by 8.3.4 type t3 figure 8-3 port type t3 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.3 block diagrams of ports page 156 pxpup (pull-up control) pxcr (output control) pxdata (output latch) pxie (input control) reset i/o port port read pxfr1 (function control) 0 1 function input drive disable in stop mode (set by 8.3.5 type t4 figure 8-4 port type t4 TMPM333FDFG/fyfg/fwfg page 157 pxpup (pull-up control) pxcr (output control) pxdata (output latch) pxie (input control) reset i/o port port read pxfr1 (function control) 0 1 function input pxod (open drain control) drive disable in stop mode set by 8.3.6 type5 t5 figure 8-5 port type t5 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.3 block diagrams of ports page 158 pxpup (pull-up control) pxcr (output control) pxdata (output latch) pxie (input control) reset i/o port 3 r u w 5 h d g pxfr1 (function control) 0 1 function input b oo t drive disable in stop mode (set by 8.3.7 type t6 figure 8-6 port type t6 TMPM333FDFG/fyfg/fwfg page 159 pxpdn (pull-down control) pxcr (output control) pxdata (output latch) pxie (input control) reset i/o port port read pxfr1 (function control) 0 1 function input drive disable in stop mode (set by 8.3.8 type t7 figure 8-7 port type t7 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.3 block diagrams of ports page 160 pxpup (pull-up control) pxcr (output control) pxdata (output latch) pxie (input control) reset i/o port port read pxfr1 (function control) 0 1 interrupt input drive disable in stop mode (set by 8.3.9 type t8 figure 8-8 port type t8 TMPM333FDFG/fyfg/fwfg page 161 pxpup (pull-up control) pxcr (output control) pxdata (output latch) pxie (input control) reset i/o port port read pxfr1 (function control) 0 1 interrupt input pxod (open-drain control) drive disable in stop mode set by 8.3.10 type t9 figure 8-9 port type t9 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.3 block diagrams of ports page 162 pxpup (pull-up control) pxcr (output control) pxdata (output latch) pxie (input control) reset i/o port port read pxfr1 (function control) 0 1 function output 0 1 drive disable in stop mode (set by 8.3.11 type t10 figure 8-10 port type t10 TMPM333FDFG/fyfg/fwfg page 163 pxpup (pull-up control) pxcr (output control) pxdata (output latch) pxie (input control) reset i/o port port read pxfr1 (function control) 0 1 pxod (open-drain control) function output 0 1 drive disable in stop mode (set by 8.3.12 type t11 figure 8-11 port type t11 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.3 block diagrams of ports page 164 pxpup (pull-up control) pxcr (output control) pxdata (output latch) pxie (input control) reset i/o port port read pxfr1 (function control) 0 1 function output 0 1 function output enable 0 1 drive disable in stop mode (set by 8.3.13 type t12 figure 8-12 port type t12 TMPM333FDFG/fyfg/fwfg page 165 pxpup (pull-up control) pxcr (output control) pxdata (output latch) pxie (input control) reset i/o port port read pxfr1 (function control) 0 1 function output 0 1 function output enable 0 1 function input drive disable in stop mode (set by 8.3.14 type t13 figure 8-13 port type t13 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.3 block diagrams of ports page 166 pxpup (pull-up control) pxcr (output control) pxdata (output latch) pxie (input control) reset i/o port port read pxfr1 (function control) 0 1 pxod (open-drain control) function output 0 1 function input drive disable in stop mode (set by 8.3.15 type t14 figure 8-14 port type t14 TMPM333FDFG/fyfg/fwfg page 167 pxcr (output control) pxdata (output latch) pxie (input control) reset i/o port port read pxfr1 (function control) 0 1 function output 0 1 function input n-chanel open-drain drive disable in stop mode (set by 8.3.16 type t15 figure 8-15 port type t15 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.3 block diagrams of ports page 168 pxpup (pull-up control) pxcr (output control) pxfr1 (function control) pxie (input control) reset i/o port port read pxfr2 (function control) pxdata (output latch) function output2 0 1 function output1 0 1 drive disable in stop mode set by 8.3.17 type t16 figure 8-16 port type t16 TMPM333FDFG/fyfg/fwfg page 169 pxpup (pull-up control) pxcr (output control) pxdata (output latch) pxie (input control) reset i/o port port read pxfr1 (function control) 0 1 pxod (open-drain control) function output1 0 1 function input1 pxfr2 (function control) function input2 drive disable in stop mode set by 8.3.18 type t17 figure 8-17 port type t17 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.3 block diagrams of ports page 170 pxpup (pull-up control) pxie (input control) reset input port port read analog input drive disable in stop mode 6 h w e \ 8.3.19 type t18 figure 8-18 port typet18 TMPM333FDFG/fyfg/fwfg page 171 pxpup (pull-up control) pxie (input control) reset i/o port port read a nalog input pxfr1 (function control) function input drive disable in stop mode set by 8.4 appendix (port setting list) the following table shows the register setting for each function. initialization of the ports where the [ ? 8.4.1 port a setting table 8-6 port setting list (port a) pin port type function after reset pacr pafr1 papup papdn paie pa0 t12 input port 0 0 x 0 1 output port 1 0 x 0 0 tms(input)/ swdio(i/o) ? 1 1 1 0 1 pa1 t6 input port 0 0 0 x 1 output port 1 0 0 x 0 tck(input)/ swclk(input) ? 0 1 0 1 1 pa2 t9 input port 0 0 x 0 1 output port 1 0 x 0 0 traceclk(output) 1 1 x 0 0 pa3 t9 input port 0 0 x 0 1 output port 1 0 x 0 0 tracedata0(output) 1 1 x 0 0 pa4 t9 input port 0 0 x 0 1 output port 1 0 x 0 0 tracedata1(output) 1 1 x 0 0 pa5 t9 input port 0 0 x 0 1 output port 1 0 x 0 0 tracedata2(output) 1 1 x 0 0 pa6 t9 input port 0 0 x 0 1 output port 1 0 x 0 0 tracedata3(output) 1 1 x 0 0 pa7 t1 input port 0 0 x 0 1 output port 1 0 x 0 0 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.4 appendix (port setting list) page 172 8.4.2 port b setting table 8-7 port setting list (port b) pin port type function after re- set pbcr pbfr1 pbpup pbie pb0 t11 input port 0 0 x 1 output port 1 0 x 0 tdo(output)/ swv(output) 1 1 0 0 pb1 t2 input port 0 0 x 1 output port 1 0 x 0 tdi(input) 0 1 1 1 pb2 t2 input port 0 0 x 1 output port 1 0 x 0 trst(input) 0 1 1 1 pb3 t1 input port 0 0 x 1 output port 1 0 x 0 pb4 t1 input port 0 0 x 1 output port 1 0 x 0 pb5 t1 input port 0 0 x 1 output port 1 0 x 0 pb6 t1 input port 0 0 x 1 output port 1 0 x 0 pb7 t1 input port 0 0 x 1 output port 1 0 x 0 TMPM333FDFG/fyfg/fwfg page 173 8.4.3 port c setting table 8-8 port setting list (port c) pin port type function after re- set pcpup pcie pc0 t17 input port x 1 analog input 0 0 pc1 t17 input port x 1 analog input 0 0 pc2 t17 input port x 1 analog input 0 0 pc3 t17 input port x 1 analog input 0 0 8.4.4 port d setting table 8-9 port setting list (port d) pin port type function after re- set pdfr1 pdpup pdie pd0 t18 input port 0 x 1 tb5in0(input) 1 x 1 analog input x 0 0 pd1 t18 input port 0 x 1 tb5in1(input) 1 x 1 analog input x 0 0 pd2 t18 input port 0 x 1 tb6in0(input) 1 x 1 analog input x 0 0 pd3 t18 input port 0 x 1 tb6in1(input) 1 x 1 analog input x 0 0 pd4 t17 input port 0 x 1 analog input x 0 0 pd5 t17 input port 0 x 1 analog input x 0 0 pd6 t17 input port 0 x 1 analog input x 0 0 pd7 t17 input port 0 x 1 analog input x 0 0 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.4 appendix (port setting list) page 174 8.4.5 port e setting table 8-10 port setting list (port e) pin port type function after re- set pecr pefr1 pefr2 peod pepup peie pe0 t10 input port 0 0 0 x x 1 output port 1 0 0 x x 0 txd0(output) 1 1 0 x x 0 pe1 t4 input port 0 0 0 x x 1 output port 1 0 0 x x 0 rxd0(input) 0 1 0 x x 1 pe2 t16 input port 0 0 0 x x 1 output port 1 0 0 x x 0 sclk0(input) 0 1 0 x x 1 sclk0(output) 1 1 0 x x 0 cts0(input) 0 0 1 x x 1 pe3 t4 input port 0 0 0 x x 1 output port 1 0 0 x x 0 pe4 t10 input port 0 0 0 x x 1 output port 1 0 0 x x 0 txd1(output) 1 1 0 x x 0 pe5 t4 input port 0 0 0 x x 1 output port 1 0 0 x x 0 rxd1(input) 0 1 0 x x 1 pe6 t16 input port 0 0 0 x x 1 output port 1 0 0 x x 0 sclk1(input) 0 1 0 x x 1 sclk1(output) 1 1 0 x x 0 cts1(input) 0 0 1 x x 1 TMPM333FDFG/fyfg/fwfg page 175 8.4.6 port f setting table 8-11 port setting list (port f) pin port type function after re- set pfcr pffr1 pffr2 pfod pfpup pfie pf0 t10 input port 0 0 0 x x 1 output port 1 0 0 x x 0 txd2(output) 1 1 0 x x 0 pf1 t4 input port 0 0 0 x x 1 output port 1 0 0 x x 0 rxd2(input) 0 1 0 x x 1 pf2 t16 input port 0 0 0 x x 1 output port 1 0 0 x x 0 sclk2(input) 0 1 1 x x 1 sclk2(output) 1 1 0 x x 0 cts2(input) 0 0 0 x x 1 pf3 t4 input port 0 0 0 x x 1 output port 1 0 0 x x 0 pf4 t13 input port 0 0 0 x x 1 output port 1 0 0 x x 0 so1(output) 1 1 0 x x 0 sda1(input/output) 1 1 0 1 x 1 pf5 t13 input port 0 0 0 x x 1 output port 1 0 0 x x 0 si1(input) 0 1 0 x x 1 scl1(input/output) 1 1 0 1 x 1 pf6 t13 input port 0 0 0 x x 1 output port 1 0 0 x x 0 sck1(input) 0 1 0 x x 1 sck1(output) 1 1 0 x x 0 pf7 t8 input port 0 0 0 x x 1 output port 1 0 0 x x 0 int5(input) 0 1 0 x x 1 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.4 appendix (port setting list) page 176 8.4.7 port g setting table 8-12 port setting list (port g) pin port type function after re- set pgcr pgfr1 pgod pgpup pgie pg0 t13 input port 0 0 x x 1 output port 1 0 x x 0 so0(output) 1 1 x x 0 sda0(input/output) 1 1 1 x 1 pg1 t13 input port 0 0 x x 1 output port 1 0 x x 0 si0(input) 0 1 x x 1 scl0(input/output) 1 1 1 x 1 pg2 t13 input port 0 0 x x 1 output port 1 0 x x 0 sck0(input) 0 1 x x 1 sck0(output) 1 1 x x 0 pg3 t8 input port 0 0 x x 1 output port 1 0 x x 0 int4(input) 0 1 x x 1 pg4 t13 input port 0 0 x x 1 output port 1 0 x x 0 so2(output) 1 1 x x 0 sda2(input/output) 1 1 1 x 1 pg5 t13 input port 0 0 x x 1 output port 1 0 x x 0 si2(input) 0 1 x x 1 scl2(input/output) 1 1 1 x 1 pg6 t13 input port 0 0 x x 1 output port 1 0 x x 0 sck2(input) 0 1 x x 1 sck2(output) 1 1 x x 0 pg7 t10 input port 0 0 x x 1 output port 1 0 x x 0 tb8out(output) 1 1 x x 0 TMPM333FDFG/fyfg/fwfg page 177 8.4.8 port h setting table 8-13 port setting list (port h) pin port type function after re- set phcr phfr1 phpup phie ph0 t5 input port 0 0 x 1 output port 1 0 x 0 tb0in0(input) 0 1 x 1 ph1 t3 input port 0 0 x 1 output port 1 0 x 0 tb0in1(input) 0 1 x 1 ph2 t3 input port 0 0 x 1 output port 1 0 x 0 tb1in0(input) 0 1 x 1 ph3 t3 input port 0 0 x 1 output port 1 0 x 0 tb1in1(input) 0 1 x 1 ph4 t3 input port 0 0 x 1 output port 1 0 x 0 tb2in0(input) 0 1 x 1 ph5 t3 input port 0 0 x 1 output port 1 0 x 0 tb2in1(input) 0 1 x 1 ph6 t3 input port 0 0 x 1 output port 1 0 x 0 tb3in0(input) 0 1 x 1 ph7 t3 input port 0 0 x 1 output port 1 0 x 0 tb3in1(input) 0 1 x 1 note:the ph0 input and pull-up are enabled and act as boot input pin while a reset is in "low" state. TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.4 appendix (port setting list) page 178 8.4.9 port i setting table 8-14 port setting list (port i) pin port type function after re- set picr pifr1 pipup piie pi0 t9 input port 0 0 x 1 output port 1 0 x 0 tb0out(output) 1 1 x 0 pi1 t9 input port 0 0 x 1 output port 1 0 x 0 tb1out(output) 1 1 x 0 pi2 t9 input port 0 0 x 1 output port 1 0 x 0 tb2out(output) 1 1 x 0 pi3 t9 input port 0 0 x 1 output port 1 0 x 0 tb3out(output) 1 1 x 0 pi4 t9 input port 0 0 x 1 output port 1 0 x 0 tb4out(output) 1 1 x 0 pi5 t9 input port 0 0 x 1 output port 1 0 x 0 tb5out(output) 1 1 x 0 pi6 t3 input port 0 0 x 1 output port 1 0 x 0 tb4in0(input) 0 1 x 1 pi7 t3 input port 0 0 x 1 output port 1 0 x 0 tb4in1(input) 0 1 x 1 TMPM333FDFG/fyfg/fwfg page 179 8.4.10 port j setting table 8-15 port setting list (port j) pin port type function after re- set pjcr pjfr1 pjpup pjie pj0 t7 input port 0 0 x 1 output port 1 0 x 0 int0(input) 0 1 x 1 pj1 t7 input port 0 0 x 1 output port 1 0 x 0 int1(input) 0 1 x 1 pj2 t7 input port 0 0 x 1 output port 1 0 x 0 int2(input) 0 1 x 1 pj3 t7 input port 0 0 x 1 output port 1 0 x 0 int3(input) 0 1 x 1 pj4 t9 input port 0 0 x 1 output port 1 0 x 0 tb6out(output) 1 1 x 0 pj5 t9 input port 0 0 x 1 output port 1 0 x 0 tb7out(output) 1 1 x 0 pj6 t7 input port 0 0 x 1 output port 1 0 x 0 int6(input) 0 1 x 1 pj7 t7 input port 0 0 x 1 output port 1 0 x 0 int7(input) 0 1 x 1 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.4 appendix (port setting list) page 180 8.4.11 port k setting table 8-16 port setting list (port k) pin port type function after re- set pkcr pkfr1 pkfr2 pkpup pkie pk0 t14 input port 0 0 0 0 1 output port 1 0 0 0 0 pk1 t15 input port 0 0 0 x 1 output port 1 0 0 x 0 scout(output) 1 1 0 x 0 alarm(output) 1 0 1 x 0 pk2 t9 input port 0 0 0 x 1 output port 1 0 0 x 0 tb9out(output) 1 1 0 x 0 note:pk0 is an n-ch open drain port. TMPM333FDFG/fyfg/fwfg page 181 TMPM333FDFG/fyfg/fwfg 8. input/output ports 8.4 appendix (port setting list) page 182 9. 16-bit timer/event counters(tmrb) 9.1 outline tmrb operate in the following four operation modes: ? ? ? ? ? ? ? TMPM333FDFG/fyfg/fwfg page 183 9.2 differences in the specifications TMPM333FDFG/fyfg/fwfg contains 10-channel of tmrb. each channel functions independently and the channels operate in the same way except for the differences in their specification as shown in table 9-1. some of the channels can put the capture trigger and the synchronous start trigger on other channels. 1. the flip-flop output of tmrb 7 through tmrb 9 can be used as the capture trigger of other channels. ? ? ? ? ? table 9-1 differences in the specifications of tmrb modules specification external pins trigger function between timers interrupt channel external clock/ capture trigger input pins timer flip-flop output pin capture trigger synchronous start trigger channel capture interrupt tmrb interrupt signal port (pin number) signal port (pin number) tmrb0 tb0in0 tb0in1 ph0 (30) ph1 (31) tb0out pi0 (38) tb7out ? intcap00 intcap01 inttb0 tmrb1 tb1in0 tb1in1 ph2 (32) ph3 (36) tb1out pi1 (40) tb7out tmrb0 intcap10 intcap11 inttb1 tmrb2 tb2in0 tb2in1 ph4 (9) ph5 (10) tb2out pi2 (42) tb8out tmrb0 intcap20 intcap21 inttb2 tmrb3 tb3in0 tb3in1 ph6 (84) ph7 (85) tb3out pi3 (48) tb8out tmrb0 intcap30 intcap31 inttb3 tmrb4 tb4in0 tb4in1 pi6 (79) pi7 (83) tb4out pi4 (52) tb8out ? intcap40 intcap41 inttb4 tmrb5 tb5in0 tb5in1 pd0 (95) pd1 (96) tb5out pi5 (53) tb9out tmrb4 intcap50 intcap51 inttb5 tmrb6 tb6in0 tb6in1 pd2 (97) pd3 (98) tb6out pj4 (88) tb9out tmrb4 intcap60 intcap61 inttb6 tmrb7 ? ? tb7out pj5 (8) ? tmrb4 ? inttb7 tmrb8 ? ? tb8out pg7 (11) ? ? ? inttb8 tmrb9 ? ? tb9out pk2 (7) ? ? ? inttb9 TMPM333FDFG/fyfg/fwfg 9. 16-bit timer/event counters(tmrb) 9.2 differences in the specifications page 184 9.3 configuration each channel consists of a 16-bit up-counter, two 16-bit timer registers (double-buffered), two 16-bit capture reg- isters, two comparators, a capture input control, a timer flip-flop and its associated control circuit.timer operation modes and the timer flip-flop are controlled by a register. figure 9-1 tmrbx block diagram(x= 0 to 9) TMPM333FDFG/fyfg/fwfg page 185 2481632 t1 t4 t16 t1 t4 t16 tmrbx interrupt inttbx tbxin0 tbxin1 internal data bus run/ clear tbxmod 9.4 registers 9.4.1 register list according to channel the following table shows the register names and addresses of each channel. channel x base address channel0 0x4001_0000 channel1 0x4001_0040 channel2 0x4001_0080 channel3 0x4001_00c0 channel4 0x4001_0100 channel5 0x4001_0140 channel6 0x4001_0180 channel7 0x4001_01c0 channel8 0x4001_0200 channel9 0x4001_0240 register name(x=0 to 9) address(base+) enable register tbxen 0x0000 run register tbxrun 0x0004 control register tbxcr 0x0008 mode register tbxmod 0x000c flip-flop control register tbxffcr 0x0010 status register tbxst 0x0014 interrupt mask register tbxim 0x0018 up counter capture register tbxuc 0x001c timer register 0 tbxrg0 0x0020 timer register 1 tbxrg1 0x0024 capture register 0 tbxcp0 0x0028 capture register 1 tbxcp1 0x002c TMPM333FDFG/fyfg/fwfg 9. 16-bit timer/event counters(tmrb) 9.4 registers page 186 9.4.2 tbxen (enable register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol tben - - - - - - - after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7 tben r/w tmrbx operation 0: disabled 1: enabled specifies the tmrb operation. when the operation is disabled, no clock is supplied to the other registers in the tmrb module. this can reduce power consumption. (this disables reading from and writing to the other reg- isters except tbxen register.) to use the tmrb, enable the tmrb operation (set to "1") before programming each register in the tmrb module. if the tmrb operation is executed and then disabled, the settings will be maintained in each register. 6-0 ? r read as 0. TMPM333FDFG/fyfg/fwfg page 187 9.4.3 tbxrun(run register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - tbprun - tbrun after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-3 ? r read as 0. 2 tbprun r/w prescaler operation 0: stop & clear 1: count 1 ? r read as 0. 0 tbrun r/w count operation 0: stop & clear 1: count TMPM333FDFG/fyfg/fwfg 9. 16-bit timer/event counters(tmrb) 9.4 registers page 188 9.4.4 tbxcr(control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol tbwbf - tbsync - i2tb - - - after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7 tbwbf r/w double buffer 0: disabled 1: enabled 6 ? r/w write 0. 5 tbsync r/w synchronous mode switching 0: individual (unit of channel) 1: synchronous 4 ? r read as 0. 3 i2tb r/w operation at idle mode 0: stop 1:operation 2-0 ? r read as 0. TMPM333FDFG/fyfg/fwfg page 189 9.4.5 tbxmod(mode register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - tbcp tbcpm tbcle tbclk after reset 0 0 1 0 0 0 0 0 bit bit symbol type function 31-7 ? r read as 0. 6 ? r/w write 0. 5 tbcp w capture control by software 0: capture by software 1: dont care when "0" is written, the capture register 0 (tbxcp0) takes count value. read as 1. 4-3 tbcpm[1:0] r/w capture timing 00: disable capture timing 01: tbxin0 tbxin1 takes count values into capture register 0 (tbxcp0) upon rising of tbxin0 pin input. takes count values into capture register 1 (tbxcp1) upon rising of tbxin1 pin input. 10: tbxin0 tbxin0 takes count values into capture register 0 (tbxcp0) upon rising of tbxin0 pin input. takes count values into capture register 1 (tbxcp1) upon falling of tbxin0 pin input. 11: tbxout tbxout takes count values into capture register 0 (tbxcp0) upon rising of 16-bit timer match output (tbxout) and into capture register 1 (tbxcp1) upon falling of tbxout. (tmrb0 and tmrb1:tb7out, tmrb2 through tmrb4:tb8out, tmrb5 and tmrb6:tb9out). 2 tbcle r/w up-counter control 0: disables clearing of the up-counter. 1: enables clearing of the up-counter. clears and controls the up-counter. when "0" is written, it disables clearing of the up-counter. when "1" is written, it clears up counter when there is a match with timer regsiter1 (tbxrg1). 1-0 tbclk[1:0] r/w selects the tmrbx source clock. 00: tbxin0 pin input 01: t1 10: t4 11: t16 TMPM333FDFG/fyfg/fwfg 9. 16-bit timer/event counters(tmrb) 9.4 registers page 190 9.4.6 tbxffcr(flip-flop control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - tbc1t1 tbc0t1 tbe1t1 tbe0t1 tbff0c after reset 1 1 0 0 0 0 1 1 bit bit symbol type function 31-8 ? r read as 0. 7-6 ? r read as 1. 5 tbc1t1 r/w tbxff0 reverse trigger when the up-counter value is taken into the tbxcp1. 0: disable trigger 1: enable trigger by setting "1", the timer-flip-flop reverses when the up-counter value is taken into the capture register 1 (tbxcp1). 4 tbc0t1 r/w tbxff0 reverse trigger when the up-counter value is taken into the tbxcp0. 0: disable trigger 1: enable trigger by setting "1", the timer-flip-flop reverses when the up-counter value is taken into the capture register 0 (tbxcp0). 3 tbe1t1 r/w tbxff0 reverse trigger when the up-counter value is matched with tbxrg1. 0: disable trigger 1: enable trigger by setting "1", the timer-flip-flop reverses when the up-counter value is matched with the timer register 1 (tbxrg1). 2 tbe0t1 r/w tbxff0 reverse trigger when the up-counter value is matched with tbxrg0. 0: disable trigger 1: enable trigger by setting "1", the timer-flip-flop reverses when an up-counter value is matched with the timer register 0 (tbxrg0). 1-0 tbff0c[1:0] r/w tbxff0 control 00: invert reverses the value of tbxff0 (reverse by using software). 01: set sets tbxff0 to "1". 10: clear clears tbxff0 to "0". 11: don't care * this is always read as "11". TMPM333FDFG/fyfg/fwfg page 191 9.4.7 tbxst(status register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - inttbof inttb1 inttb0 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-3 ? r read as 0. 2 inttbof r overflow flag 0:no overflow occurs 1:overflow occurs when an up-counter is overflow, "1" is set. 1 inttb1 r match flag (tbxrg1) 0:no detection of a mach 1:detects a match with tbxrg1 when a match with the timer register 1 (tbxrg1) is detected,"1" is set. 0 inttb0 r match flag (tbxrg0) 0:no match is detected 1:detects a match with tbxrg0 when a match with the timer register 0 (tbxrg0) is detected, "1" is set. note 1: the factors only which is not masked by tbxim output interrupt request to the cpu.even if the mask setting is done, the flag is set. note 2: the flag is cleared by reading the tbxst register.to clear the flag, tbxst register should be read. TMPM333FDFG/fyfg/fwfg 9. 16-bit timer/event counters(tmrb) 9.4 registers page 192 9.4.8 tbxim(interrupt mask register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - tbimof tbim1 tbim0 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-3 ? r read as 0. 2 tbimof r/w overflow interrupt mask 0:disable 1:enable sets the up-counter overflow interrupt to disable or enable. 1 tbim1 r/w match interrupt mask (tbxrg1) 0:disable 1:enable sets the match interrupt mask with the timer register 1 (tbxrg1) to enable or disable. 0 tbim0 r/w match interrupt mask (tbxrg0) 0:disable 1:enable sets the match interrupt mask with the timer register 0 (tbxrg0) to enable or disable. 9.4.9 tbxuc(up counter capture register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol tbuc after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol tbuc after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-16 ? r read as 0. 15-0 tbuc[15:0] r captures a value by reading up-counter out. if tbxuc is read, current up-counter value can be captured. TMPM333FDFG/fyfg/fwfg page 193 9.4.10 tbxrg0(timer register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol tbrg0 after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol tbrg0 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-16 ? r read as 0. 15-0 tbrg0[15:0] r/w sets a value comparing to the up-counter. 9.4.11 tbxrg1(timer register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol tbrg1 after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol tbrg1 after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-16 ? r read as 0. 15-0 tbrg1[15:0] r/w sets a value comparing to the up-counter. TMPM333FDFG/fyfg/fwfg 9. 16-bit timer/event counters(tmrb) 9.4 registers page 194 9.4.12 tbxcp0(capture register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol tbcp0 after reset undefined undefined undefined undefined undefined undefined undefined undefined 7 6 5 4 3 2 1 0 bit symbol tbcp0 after reset undefined undefined undefined undefined undefined undefined undefined undefined bit bit symbol type function 31-16 ? r read as 0. 15-0 tbcp0[15:0] r a value captured from the up-counter is read. 9.4.13 tbxcp1(capture register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol tbcp1 after reset undefined undefined undefined undefined undefined undefined undefined undefined 7 6 5 4 3 2 1 0 bit symbol tbcp1 after reset undefined undefined undefined undefined undefined undefined undefined undefined bit bit symbol type function 31-16 ? r read as 0. 15-0 tbcp1[15:0] r a value captured from the up-counter is read. TMPM333FDFG/fyfg/fwfg page 195 9.5 description of operations for each circuit the channels operate in the same way, except for the differences in their specifications as shown in table 9-1 . 9.5.1 prescaler there is a 4-bit prescaler to generate the source clock for up-counter uc. the prescaler input clock t0 is fperiph/1, fperiph/2, fperiph/4, fperiph/8, fperiph/16 or fperiph/32 selected by cgsyscr table 9-2 prescaler output clock resolutions(fc = 40mhz) select peripheral clock cgsyscr table 9-3 prescaler output clock resolutions(fc = 32mhz) select peripheral clock cgsyscr table 9-3 prescaler output clock resolutions(fc = 32mhz) select peripheral clock cgsyscr 9.5.2 up-counter (uc) uc is a 16-bit binary counter. ? ? ? ? 9.5.3 timer registers (tbxrg0, tbxrg1) tbxrg0 and tbxrg1 are registers for setting values to compare with up-counter values and two registers are built into each channel. if the comparator detects a match between a value set in this timer register and that in a uc up-counter, it outputs the match detection signal. tbxrg0 and tbxrg1 are consisted of the double-buffered configuration which are paired with register buf- fers. the double buffering is disabled in the initial state. controlling double buffering disable or enable is specified by tbxcr 9.5.4 capture this is a circuit that controls the timing of latching values from the uc up-counter into the tbxcp0 and tbxcp1 capture registers. the timing with which to latch data is specified by tbxmod 9.6 description of operations for each mode 9.6.1 16-bit interval timer mode in the case of generating constant period interrupt, set the interval time to the timer register (tbxrg1) to generate the inttbx interrupt. 7 6 5 4 3 2 1 0 tbxen 1 x x x x x x x enables tmrbx operation. tbxrun x x x x x 0 x 0 stops count operation. interrupt set-enable register * * * * * * * * permits inttbx interrupt by setting corresponding bit to "1". tbxffcr x x 0 0 0 0 1 1 disable to tbxff0 reverse trigger tbxmod x 0 1 0 0 1 * * changes to prescaler output clock as input clock. specifies capture function to disable. (** = 01, 10, 11) tbxrg1 * * * * * * * * specifies a time interval. (16 bits) * * * * * * * * tbxrun * * * * * 1 x 1 starts tmrbx. note:x; dont care ?; no change 9.6.2 16-bit event counter mode it is possible to make it the event counter by using an input clock as an external clock (tbxin0 pin input). the up-counter counts up on the rising edge of tbxin0 pin input. it is possible to read the count value by capturing value using software and reading the captured value. 7 6 5 4 3 2 1 0 tbxen 1 x x x x x x x enables tmrbx operation. tbxrun x x x x x 0 x 0 stops count operation. pxie[m] 1 allocates corresponding port totbxin0. pxfr1[m] 1 tbxffcr x x 0 0 0 0 1 1 disables to tbxff0 reverse trigger tbxmod x 0 1 0 0 0 0 0 changes totbxin0 as an input clock tbxrun * * * * * 1 x 1 starts tmrbx. tbxmod x 0 0 0 0 0 0 0 software capture is done. note 1: m: corresponding bit of port note 2: x; dont care ?; no change TMPM333FDFG/fyfg/fwfg 9. 16-bit timer/event counters(tmrb) 9.6 description of operations for each mode page 202 9.6.3 16-bit ppg (programmable pulse generation) output mode square waves with any frequency and any duty (programmable square waves) can be output. the output pulse can be either low-active or high-active. programmable square waves can be output from the tbxout pin by triggering the timer flip-flop (tbxff) to reverse when the set value of the up-counter (uc) matches the set values of the timer registers (tbxrg0 and tbxrg1). note that the set values of tbxrg0 and tbxrg1 must satisfy the following requirement: (set value of tbxrg0) < (set value of tbxrg1) figure 9-2 example of output of programmable pulse generation (ppg) in this mode, by enabling the double buffering of tbxrg0, the value of register buffer 0 is shifted into tbxrg0 when the set value of the up-counter matches the set value of tbxrg1. this facilitates handling of small duties. figure 9-3 register buffer operation TMPM333FDFG/fyfg/fwfg page 203 q 2 q 1 match with tbxrg1 tbxrg0 (compare value) q 3 q 2 register buffer trigger to shift to tbxrg1 write tbxrg0 up-counter= q 1 up-counter= q 2 match with tbxrg0 tbxout pin match with tbxrg0 (inttbx interrupt) match with tbxrg1 (inttbx interrupt) the block diagram of this mode is shown below. figure 9-4 block diagram of 16-bit ppg mode each register in the 16-bit ppg output mode must be programmed as listed below. 7 6 5 4 3 2 1 0 tbxen 1 x x x x x x x enables tmrbx operation. tbxrun x x x x x 0 x 0 stops count operation. tbxcr 0 0 ? x ? x x x disables double buffering. tbxrg0 specifies a duty. (16 bits) tbxrg1 specifies a cycle. (16 bits) tbxcr 1 0 x 0 0 0 0 0 enables the tbxrg0 double buffering. (changes the duty/cycle when the inttbx interrupt is gener- ated) tbxffcr x x 0 0 1 1 1 0 specifies to trigger tbxff0 to reverse when a match with tbxrg0 or tbxrg1 is detected,and sets the initial value of tbxff0 to "0." tbxmod x 0 1 0 0 1 designates the prescaler output clock as the input clock,and disables the capture function. ( = 01, 10, 11) pxcr[m] 1 allocates corresponding port to tbxout. pxfr1[m] 1 tbxrun 1 x 1 starts tmrbx. note 1: m: corresponding bit of port note 2: x; dont care ?; no change TMPM333FDFG/fyfg/fwfg 9. 16-bit timer/event counters(tmrb) 9.6 description of operations for each mode page 204 selector internal data bus tbxcr 9.6.4 timer synchronous mode this mode enables the timers to start synchronously. if the mode is used with ppg output, the output can be applied to drive a motor. tmrb is consisted of two pairs of 4-channel tmrb. if one channel starts, remaining 3 channels can be start synchronously. in the TMPM333FDFG/fyfg/fwfg, the following combinations allow to use. start trigger channel (master channel) synchronous operation channel (slave channel) tmrb0 tmrb1, tmrb2, tmrb3 tmrb4 tmrb5, tmrb6, tmrb7 use of the timer synchronous mode is specified in tbxcr 9.7 applications using the capture function the capture function can be used to develop many applications, including those described below: 1. one-shot pulse output triggered by an external pulse 2. frequency measurement 3. pulse width measurement 4. time difference measurement 9.7.1 one-shot pulse output triggered by an external pulse one-shot pulse output triggered by an external pulse is carried out as follows: the 16-bit up-counter is made to count up by putting it in a free-running state using the prescaler output clock. an external pulse is input through the tbxin0 pin. a trigger is generated at the rising of the external pulse by using the capture function and the value of the up-counter is taken into the capture registers (tbxcp0). the cpu must be programmed so that an interrupt intcapx0 is generated at the rising of an external trigger pulse. this interrupt is used to set the timer registers (tbxrg0) to the sum of the tbxcp0 value (c) and the delay time (d), (c + d), and set the timer registers (tbxrg1) to the sum of the tbxrg0 values and the pulse width (p) of one-shot pulse, (c + d + p).[tbxrg1 change must be completed before the next match.] in addition, the timer flip-flop control registers(tbxffcr the followings show the settings in the case that 2 ms width one-shot pulse is output after 3ms by triggering tbxin0 input at the rising edge. ( t1 is selected for counting.) changes source clock to t1. fetches a count value into the tbxcp0 at the rising edge of tbxin0. 7 6 5 4 3 2 1 0 [main processing] capture setting by tbxin0 pxie[m] 1 allocates corresponding port to tbxin0. pxfr1[m] 1 tbxen 1 x x x x x x x enables tmrbx operation. tbxrun x x x x x 0 x 0 stops count operation. tbxmod x 0 1 0 1 0 0 1 changes source clock to t1. fetches a count value into the tbxcp0 at the rising edge of tbxin0. tbxffcr x x 0 0 0 0 1 0 clears tbxff0 reverse trigger and disables. pxcr[m] 1 allocates corresponding port totbxout. pxfr1[m] 1 interrupt set-enable register permits to generate interrupts specified by intcapx0 interrupt corresponding bit by setting to "1". tbxrun 1 x 1 starts the tmrbx module. [processing of intcapx0 interrupt service routine] pulse output setting tbxrg0 sets count value. (tbxcap0 + 3ms/t1) tbxrg1 sets count value.(tbxcap0 + (3+2)ms/t1) tbxffcr x x ? ? 1 1 ? ? reverses tbxff0 if tbxrg0 consistent with tbxrg1. tbxim x x x x x 1 0 1 masks except tbxrg1 correspondence interrupt. interrupt set-enable register permits to generate interrupt specified by inttbx interrupt cor- responding bit setting to "1". [processing of inttbx interrupt service routine] output disable tbxffcr x x ? ? 0 0 ? ? clears tbxff0 reverse trigger setting. interrupt enable clear register prohibits interrupts specified by inttbx interrupt correspond- ing bit by setting to "1". note 1: m: corresponding bit of port note 2: x; dont care ?; no change if a delay is not required, tbxff0 is reversed when data is taken into tbxcp0, and tbxrg1 is set to the sum of the tbxcp0 value (c) and the one-shot pulse width (p), (c + p), by generating the intcapx0 interrupt. (tbxrg1 change must be completed before the next match.) tbxff0 is enabled to reverse when uc matches with tbxrg1, and is disabled by generating the inttbx interrupt. figure 9-6 one-shot pulse output triggered by an external pulse (without delay) TMPM333FDFG/fyfg/fwfg page 207 count clock (prescaler output clock) timer output tbxout pin tbxin0 input (external trigger pulse) match with tbxrg1 c (p) c + p enable reverse inttbx generation enable reverse when data is taken into tbxcp0. taking data into the capture register tbxcp0. taking data into the capture register tbxcp1. disable reverse when data is taken into tbxcp1. pulse width intcapx0 generation 9.7.2 frequency measurement the frequency of an external clock can be measured by using the capture function. to measure frequency, another 16-bit timer is used in combination with the 16-bit event counter mode. as an example, we explain with tmrb3 and tmrb8. tb8out of the 16-bit timer tmrb8 is used to specify the measurement time. tmrb3 count clock selects tb3in0 input and performs count operation by using external clock input. if tb3mod 9.7.3 pulse width measurement by using the capture function, the "high" level width of an external pulse can be measured. specifically, by putting it in a free-running state using the prescaler output clock, an external pulse is input through the tbxin0 pin and the up-counter (uc) is made to count up. a trigger is generated at each rising and falling edge of the external pulse by using the capture function and the value of the up-counter is taken into the capture registers (tbxcp0, tbxcp1). the cpu must be programmed so that intcapx1 is generated at the falling edge of an external pulse input through the tbxin0 pin. the "high" level pulse width can be calculated by multiplying the difference between tbxcp0 and tbxcp1 by the clock cycle of an internal clock. for example, if the difference between tbxcp0 and tbxcp1 is 100 and the cycle of the prescaler output clock is 0.5 s , the pulse width is 100 0.5 s = 50 s. caution must be exercised when measuring pulse widths exceeding the uc maximum count time which is dependant upon the source clock used. the measurement of such pulse widths must be made using software. the "low" level width of an external pulse can also be measured. in such cases, the difference between c2 generated the first time and c1 generated the second time is initially obtained by performing the second stage of intcapx0 interrupt processing as shown in "figure 9-8 pulse width measurement" and this difference is mul- tiplied by the cycle of the prescaler output clock to obtain the "low" level width. figure 9-8 pulse width measurement TMPM333FDFG/fyfg/fwfg page 209 prescaler output clock taking data into tbxcp1 tbxin0 pin input (external pulse) taking data into tbxcp0 c1 c1 c1 c2 c2 c2 intcapx1 intcapx0 9.7.4 time difference measurement the time difference of two events can be measured by the capture function. the up-counter (uc) is made to count up by putting it in a free-running state using the prescaler output clock. the value of uc is taken into the capture register (tbxcp0) at the rising edge of the tbxin0 pin input pulse. the cpu must be programmed to generate intcapx0 interrupt at this time. the value of uc is taken into the capture register (tbxcp1) at the rising edge of the tbxin1 pin input pulse. the cpu must be programmed to generate intcapx1 interrupt at this time. the time difference can be calculated by multiplying the difference between tbxcp1 and tbxcp0 by the clock cycle of an internal clock. figure 9-9 time difference measurement TMPM333FDFG/fyfg/fwfg 9. 16-bit timer/event counters(tmrb) 9.7 applications using the capture function page 210 prescaler output clock taking data into tbxcp1 tbxin0 pin input tbxin1 pin input taking data into tbxcp0 c1 c2 intcapx0 intcapx1 time difference 10. serial channel (sio/uart) 10.1 overview this device has two mode for the serial channel, one is the synchronous communication mode (i/o interface mode), and the other is the asynchronous communication mode (uart mode). their features are given in the following. ? ? ? ? 10.2 difference in the specifications of sio modules TMPM333FDFG/fyfg/fwfg has three sio channels. each channel functions independently. the used pins and interrupt in each channel are collected in the following. table 10-1 difference in the specifications of sio modules channel 0 channel 1 channel 2 pin name txd pe0(20pin) pe4(23pin) pf0(33pin) rxd pe1(21pin) pe5(24pin) pf1(34pin) cts/slck pe2(22pin) pe6(25pin) pf2(35pin) interrupt receive interrupt intrx0 intrx1 intrx2 transmit interrupt inttx0 inttx1 inttx2 TMPM333FDFG/fyfg/fwfg page 211 10.3 configuration figure 10-1 shows sio block diagram. figure 10-1 sio block diagram TMPM333FDFG/fyfg/fwfg 10. serial channel (sio/uart) 10.3 configuration page 212 t0 f sys t t1 t t4 t t16 t t64 t t1 scxbrcr 10.4 registers description 10.4.1 registers list in each channel the each channel registers and addresses are shown here. channel x base address channel0 0x4002_0080 channel1 0x4002_00c0 channel2 0x4002_0100 register name (x=0 to 2) address (base+) enable register scxen 0x0000 buffer register scxbuf 0x0004 control register scxcr 0x0008 mode control register 0 scxmod0 0x000c baud rate generator control register scxbrcr 0x0010 baud rate generator control register 2 scxbradd 0x0014 mode control register 1 scxmod1 0x0018 mode control register 2 scxmod2 0x001c rx fifo configuration register scxrfc 0x0020 tx fifo configuration register scxtfc 0x0024 rx fifo status register scxrst 0x0028 tx fifo status register scxtst 0x002c fifo configuration register scxfcnf 0x0030 note:do not modify any control register when data is being transmitted or received. TMPM333FDFG/fyfg/fwfg page 213 10.4.2 scxen (enable register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - sioe after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-1 ? r read as 0. 0 sioe r/w sio operation 0: disabled 1: enabled specified the sio operation. to use the sio, set 10.4.3 scxbuf (buffer register) scxbuf works as a transmit buffer or fifo for write operation and as a receive buffer or fifo for read operation. 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol tb / rb after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7-0 tb[7:0] / rb [7:0] r/w [write] tb : transmit buffer / fifo [read] rb : receive buffer / fifo TMPM333FDFG/fyfg/fwfg page 215 10.4.4 scxcr (control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol rb8 even pe oerr perr ferr sclks ioc after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7 rb8 r receive data bit 8 (for uart) 9th bit of the received data in the 9 bits uart mode. 6 even r/w parity (for uart) 0: odd 1: even selects even or odd parity. "0" : odd parity, "1" : even parity. the parity bit may be used only in the 7- or 8-bit uart mode. 5 pe r/w add parity (for uart) 0: disabled 1: enabled controls enabling/ disabling parity. the parity bit may be used only in the 7- or 8-bit uart mode. 4 oerr r overrun error flag (note) 0: normal operation 1: error 3 perr r parity / underrun error flag (note) 0: normal operation 1: error 2 ferr r framing error flag (note) 0: normal operation 1: error 1 sclks r/w selecting input clock edge (for i/o interface) 0: rising edges 1: falling edges selects input clock edge for data transmission and reception. set to "0" in the clock output mode. 0 ioc r/w selecting clock (for i/o interface) 0: baud rate generator 1: sclk pin input note: any error flag (oerr, perr, ferr) is cleared to "0" when read. TMPM333FDFG/fyfg/fwfg 10. serial channel (sio/uart) 10.4 registers description page 216 10.4.5 scxmod0 (mode control register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol tb8 ctse rxe wu sm sc after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7 tb8 r/w transmit data bit 8 (for uart) writes the 9th bit of transmit data in the 9 bits uart mode. 6 ctse r/w handshake function control (for uart) 0: cts disabled 1: cts enabled controls handshake function. setting "1" enables handshake function using cts pin. 5 rxe r/w receive control (note) 0: disabled 1: enabled 4 wu r/w wake-up function (for uart) 0: disabled 1: enabled this function is available only at 9-bit uart mode. in other mode, this function has no meaning. in it is enabled, interrupt only when rb9 = "1" at 9-bit uart mode. 3-2 sm[1:0] r/w specifies transfer mode. 00: i/o interface mode 01: 7-bit length uart mode 10: 8-bit length uart mode 11: 9-bit length uart mode 1-0 sc[1:0] r/w serial transfer clock (for uart) 00: timer tb9out 01: baud rate generator 10: internal clock fsys 11: external clock (sclk input) (as for the i/o interface mode, the serial transfer clock can be set in the control register (scxcr). note 1: with 10.4.6 scxmod1 (mode control register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol i2sc fdpx txe sint - after reset 0 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7 i2sc r/w idle 0: stop 1: operate specifies the idle mode operation. 6-5 fdpx[1:0] r/w transfer mode setting 00: transfer prohibited 01: half duplex (recieve) 10: half duplex (trasmitt) 11: full duplex configures the transfer mode in the i/o interface mode. also configures the fifo if it is enabled. in the uart mode, it is used only to specify the fifo configuration. 4 txe r/w transmit control (note) 0 :disabled 1: enabled this bit enables transmission and is valid for all the transfer modes. 3-1 sint[2:0] r/w interval time of continuous transmission (for i/o interface) 000: none 001: 1sclk 010: 2sclk 011: 4sclk 100: 8sclk 101: 16sclk 110: 32sclk 111: 64sclk this parameter is valid only for the i/o interface mode when sclk pin output is selected. in other modes, this function has no meaning. specifies the interval time of continuous transmission when double buffering or fifo is enabled in the i/o interface mode. 0 ? r/w write a "0". note 1: specify the all mode first and then enable the 10.4.7 scxmod2 (mode control register 2) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol tbemp rbfll txrun sblen drchg wbuf swrst after reset 1 0 0 0 0 0 0 0 bit bit symbol type function 31-8 ? r read as 0. 7 tbemp r transmit buffer empty flag. 0: full 1: empty if double buffering is disabled, this flag is insignificant. this flag shows that the transmit double buffers are empty. when data in the transmit double buffers is moved to the transmit shift register and the double buffers are empty, this bit is set to "1". writing data again to the double buffers sets this bit to "0". 6 rbfll r receive buffer full flag. 0: empty 1: full this is a flag to show that the receive double buffers are full. when a receive operation is completed and received data is moved from the receive shift register to the receive double buffers, this bit changes to "1" while reading this bit changes it to "0". if double buffering is disabled, this flag is insignificant. 5 txrun r in transmission flag 0: stop 1: operate this is a status flag to show that data transmission is in progress. |