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general description the max9386/max9387/max9388 are fully differential, high-speed, low-jitter ecl/pecl multiplexers (muxes) with output buffer(s). the devices are designed for clock-and-data distribution applications, and feature extremely low propagation delays (318ps, typ) and out- put-to-output skews (3.9ps, typ). the max9386 is a 5:1 mux with a single output buffer. the max9387 is a 5:1 mux with dual output buffers, and is intended for use in redundant systems. the max9388 is a 4:1 mux with a single output buffer, and is pin compatible with the mc100ep57. three single-ended select inputs, sel0, sel1, and sel2, control the mux function on the max9386/ max9387. the max9388 has two select inputs, sel0 and sel1. the mux select inputs are compatible with ecl/pecl logic, and are internally referenced to the on-chip output v bb , nominally v cc - 1.425v. the select inputs accept signals between v cc and v ee . internal pulldowns to v ee ensure a low-default condition if the select inputs are left open. the differential inputs d_, d_ can be configured to accept a single-ended signal when the unused comple- mentary input is connected to the on-chip reference output v bb . all the differential inputs have internal bias and clamping circuits that ensure low-default output states when the inputs are left open. the max9386/max9387/max9388 operate with a wide supply range | v cc - v ee | of 2.375v to 5.5v. the max9386/max9388 are offered in 20-pin tssop and qsop packages. the max9387 is offered in 24-pin tssop and qsop packages. applications high-speed telecom and datacom applications central office backplane clock distribution dslam/dlc features 318ps (typ) propagation delay >2.7ghz toggle frequency 0.3ps(rms) random jitter <14ps (max) at +25? output-to-output skew (max9387) -2.375v to -5.5v supplies for differential lvecl/ecl +2.375v to +5.5v supplies for differential lvpecl/pecl outputs low for open inputs dual output buffers (max9387) pin compatible with mc100ep57 (max9388eup) >2kv esd protection (human body model) max9386/max9387/max9388 differential 5:1 or 4:1 ecl/pecl multiplexers with single/dual output buffers ________________________________________________________________ maxim integrated products 1 19-2617; rev 1; 12/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range pin- package selection max9386 eup -40 c to +85 c 20 tssop 5:1 mux with 1 output buffer max9386eep* -40 c to +85 c 20 qsop 5:1 mux with 1 output buffer 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 v cc sel2 sel1 sel0 d1 d1 do do top view q q v cc v bb1 d3 d3 d2 d2 12 11 9 10 v bb2 v ee d4 d4 max9386 tssop/qsop pin configurations pin configurations continued at end of data sheet. ordering information continued at end of data sheet. * future productcontact factory for availability.
max9386/max9387/max9388 differential 5:1 or 4:1 ecl/pecl multiplexers with single/dual output buffers 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc - v ee ...............................................................-0.3v to +6.0v inputs (d_, d_ , sel_) to v ee ......................-0.3v to (v cc + 0.3v) d_ to d_ ..............................................................................?.0v continuous output current .................................................50ma surge output current........................................................100ma v bb_ sink/source current ...............................................?00? continuous power dissipation (t a = +70?) 20-lead tssop (derate 11.0mw/? above +70?) ....880mw ja in still air ...........................................................+91?/w jc ...........................................................................+20?/w 24-lead tssop (derate 12.2mw/? above +70?) ....976mw ja in still air ...........................................................+82?/w jc ...........................................................................+15?/w 20-lead qsop (derate 9.1mw/? above +70?) .......727mw ja in still air .........................................................+110?/w jc ...........................................................................+34?/w 24-lead qsop (derate 9.5mw/? above +70?) .......762mw ja in still air .........................................................+105?/w jc ...........................................................................+34?/w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? esd protection human body model ( d_ , d_, q_, q_ , sel_, v bb_ ) ............. 2kv lead temperature (soldering, 10s) .................................+300? dc electrical characteristics (v cc - v ee = 2.375v to 5.5v, outputs loaded with 50 ? 1% to v cc - 2v. typical values are at v cc - v ee = 3.3v, v ihd = v cc - 1v, v ild = v cc - 1.5v, unless otherwise noted.) (notes 1?) -40 c +25 c +85 c parameter symbol conditions min typ max min typ max min typ max units input (d_, d_ , sel_) single-ended input high voltage v ih v bb connected to the unused input (figure 1) v cc - 1.225 v cc - 0.880 v cc - 1.225 v cc - 0.880 v cc - 1.225 v cc - 0.880 v single-ended input low voltage v il v bb connected to the unused input (figure 1) v cc - 1.945 v cc - 1.625 v cc - 1.945 v cc - 1.625 v cc - 1.945 v cc - 1.625 v differential input high voltage v ihd figure 1 v ee + 1.2 v cc v ee + 1.2 v cc v ee + 1.2 v cc v differential input low voltage v ild figure 1 v ee v cc - 0.095 v ee v cc - 0.095 v ee v cc - 0.095 v v cc - v ee < 3.0v 0.095 v cc - v ee 0.095 v cc - v ee 0.095 v cc - v ee differential input voltage v i h d - v i ld figure 1 v cc - v ee 3.0v 0.095 3.000 0.095 3.000 0.095 3.000 v input current i in v ih , v il , v ihd , v ild -100 +100 -100 +100 -100 +100 a
max9386/max9387/max9388 differential 5:1 or 4:1 ecl/pecl multiplexers with single/dual output buffers _______________________________________________________________________________________ 3 ac electrical characteristics (v cc - v ee = 2.375v to 5.5v, outputs loaded with 50 ? 1% to v cc - 2v, v ihd - v ild = 0.15v to 1v, f in 2.5ghz input duty cycle = 50%, input transition time = 125ps (20% to 80%). typical values are at v cc - v ee = 3.3v, v ihd = v cc - 1v, v ild = v cc - 1.5v, f in = 622mhz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.) (note 7) -40 c +25 c +85 c parameter symbol conditions min typ max min typ max min typ max units differential input-to-output delay t plhd , t phld figure 2 222 309 377 238 318 395 254 333 431 ps sel_-to-output delay t plh2 , t phl2 figure 4, input transition time = 500ps (20% to 80%) (note 8) 1.64 1.4 1.6 ns output-to- output skew t skoo max9387 only, figure 5 (note 9) 3.9 26 3.9 14 8.0 26 ps input-to-output skew t skio figure 6 (note 10) 7.3 53 7.7 50 8.3 50 ps p ar t- to- p ar t s kew t skpp (note 11) 111 130 133 ps dc electrical characteristics (continued) (v cc - v ee = 2.375v to 5.5v, outputs loaded with 50 ? 1% to v cc - 2v. typical values are at v cc - v ee = 3.3v, v ihd = v cc - 1v, v ild = v cc - 1.5v, unless otherwise noted.) (notes 1 4) -40 c +25 c +85 c parameter symbol conditions min typ max min typ max min typ max units output (q_, q_ ) single-ended output high voltage v oh figure 2 v cc - 1.145 v cc - 0.895 v cc - 1.145 v cc - 0.895 v cc - 1.145 v cc - 0.895 v single-ended output low voltage v ol figure 2 v cc - 1.945 v cc - 1.695 v cc - 1.945 v cc - 1.695 v cc - 1.945 v cc - 1.695 v differential output voltage v oh - v ol figure 2 650 830 650 840 650 840 mv reference output (v bb _ ) reference voltage output v bb1 , v bb2 i bb1 + i bb2 = 0.5ma (note 5) v cc - 1.525 v cc - 1.425 v cc - 1.325 v cc - 1.525 v cc - 1.425 v cc - 1.325 v cc - 1.525 v cc - 1.425 v cc - 1.325 v power supply max9386 34 50 36 50 38 50 max9387 40 60 42 60 45 60 supply current (note 6) i ee max9388 31 47 33 47 35 47 ma
max9386/max9387/max9388 differential 5:1 or 4:1 ecl/pecl multiplexers with single/dual output buffers 4 _______________________________________________________________________________________ note 1: measurements are made with the device in thermal equilibrium. note 2: current into an i/o pin is defined as positive. current out of an i/o pin is defined as negative. note 3: dc parameters production tested at t a = +25 c and guaranteed by design over the full operating temperature range. note 4: single-ended data input operation using v bb_ is limited to (v cc - v ee ) 3.0v. note 5: use v bb_ only for inputs that are on the same device as the v bb_ reference. note 6: all pins open except v cc and v ee . note 7: guaranteed by design and characterization. limits are set at 6 sigma. note 8: measured from the 50% point of the input signal with the 50% point equal to v bb , to the 50% point of the output signal. note 9: measured between outputs of the same part at the signal crossing points for a same-edge transition. note 10: measured between input-to-output paths of the same part at the signal crossing points for a same-edge transition of the differential input signal. note 11: measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. note 12: device jitter added to the differential input signal. ac electrical characteristics (continued) v cc - v ee = 2.375v to 5.5v, outputs loaded with 50 ? 1% to v cc - 2v, v ihd - v ild = 0.15v to 1v, f in 2.5ghz input duty cycle = 50%, input transition time = 125ps (20% to 80%). typical values are at v cc - v ee = 3.3v, v ihd = v cc - 1v, v ild = v cc - 1.5v, f in = 622mhz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.) (note 7) -40 c +25 c +85 c parameter symbol conditions min typ max min typ max min typ max units f in = 156m h z 0.3 1.15 0.3 1.15 0.3 1.15 f in = 622m h z 0.3 1.15 0.3 1.15 0.3 1.15 added random jitter (note 12) t rj clock pattern f in = 2.5gh z 0.3 1.15 0.3 1.15 0.3 1.15 ps(rms) f in = 156m b p s 3395 3395 3395 added deterministic jitter (note 12) t dj prbs 2 23 - 1 f in = 622m b p s 2161 2161 2161 ps p-p switching frequency f max v oh - v ol 300mv, figure 2 2.7 2.7 2.7 ghz select toggle frequency f sel 100 100 100 mhz output rise and fall time (20% to 80%) t r , t f figure 2 67 105 138 74 117 155 81 128 165 ps
max9386/max9387/max9388 differential 5:1 or 4:1 ecl/pecl multiplexers with single/dual output buffers _______________________________________________________________________________________ 5 typical operating characteristics (v cc - v ee = 3.3v, v ihd = v cc - 1v, v ild = v cc - 1.5v, outputs loaded with 50 ? 1% to v cc - 2v, f in = 1.5ghz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.) supply current (i ee ) vs. temperature max9386 toc01 temperature ( c) supply current (ma) 60 35 -15 10 25 30 35 40 45 50 55 60 20 -40 85 output amplitude (v oh - v ol ) vs. frequency max9386 toc02 frequency (mhz) output voltage (mv) 2400 2000 1600 1200 800 400 200 400 600 800 1000 0 0 2800 output rise/fall vs. temperature max9386 toc03 temperature ( c) rise/fall time (ps) 60 35 10 -15 100 110 120 130 140 150 90 -40 85 fall rise differential propagation delay vs. input high voltage max9386 toc04 input high voltage (v) propagation delay (ps) 2.7 2.4 2.1 1.8 1.5 280 290 300 310 320 330 340 350 360 370 270 1.2 3.0 t plhd t phld differential propagation delay vs. temperature max9386 toc05 temperature ( c) transition time (ps) 60 35 10 -15 290 300 310 320 330 340 350 280 -40 85 t plhd t phld
max9386/max9387/max9388 differential 5:1 or 4:1 ecl/pecl multiplexers with single/dual output buffers 6 _______________________________________________________________________________________ pin max9386 max9388 name function 1 2 d0 noninverting differential input 0. internal 250k ? to v cc and 150k ? to v ee . 23 d0 inverting differential input 0. internal 150k ? to v cc and 150k ? to v ee . 3 4 d1 noninverting differential input 1. internal 250k ? to v cc and 150k ? to v ee . 45 d1 inverting differential input 1. internal 150k ? to v cc and 150k ? to v ee . 5 6 d2 noninverting differential input 2. internal 250k ? to v cc and 150k ? to v ee . 67 d2 inverting differential input 2. internal 150k ? to v cc and 150k ? to v ee . 7 8 d3 noninverting differential input 3. internal 250k ? to v cc and 150k ? to v ee . 89 d3 inverting differential input 3. internal 150k ? to v cc and 150k ? to v ee . 9 d4 noninverting differential input 4. internal 250k ? to v cc and 150k ? to v ee . 10 d4 inverting differential input 4. internal 150k ? to v cc and 150k ? to v ee . 11 10, 11 v ee negative supply 12 12 v bb2 reference output voltage 2. connect to the inverting or noninverting data input to provide a reference for single-ended operation. when used, bypass v bb2 to v cc with a 0.01f ceramic capacitor. otherwise leave open. 13 13 v bb1 reference output voltage 1. connect to the inverting or noninverting data input to provide a reference for single-ended operation. when used, bypass v bb1 to v cc with a 0.01f ceramic capacitor. otherwise leave open. 14, 20 1, 14 17, 20 v cc positive supply. bypass each v cc to v ee with 0.1f and 0.01f ceramic capacitors. place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 15 15 q inverting output. typically terminate with 50 ? resistor to v cc - 2v. 16 16 q noninverting output. typically terminate with 50 ? resistor to v cc - 2v. 17 18 sel0 select logic input 0. internal 120k ? pulldown to v ee . 18 19 sel1 select logic input 1. internal 120k ? pulldown to v ee . 19 sel2 select logic input 2. internal 120k ? pulldown to v ee . max9386/max9388 pin description
max9386/max9387/max9388 differential 5:1 or 4:1 ecl/pecl multiplexers with single/dual output buffers _______________________________________________________________________________________ 7 pin max9387 name function 1, 18, 24 v cc positive supply. bypass each v cc to v ee with 0.1f and 0.01f ceramic capacitors. place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 2 d0 noninverting differential input 0. internal 250k ? to v cc and 150k ? to v ee . 3 d0 inverting differential input 0. internal 150k ? to v cc and 150k ? to v ee . 4 d1 noninverting differential input 1. internal 250k ? to v cc and 150k ? to v ee . 5 d1 inverting differential input 1. internal 150k ? to v cc and 150k ? to v ee . 6 d2 noninverting differential input 2. internal 250k ? to v cc and 150k ? to v ee . 7 d2 inverting differential input 2. internal 150k ? to v cc and 150k ? to v ee . 8 d3 noninverting differential input 3. internal 250k ? to v cc and 150k ? to v ee . 9 d3 inverting differential input 3. internal 150k ? to v cc and 150k ? to v ee . 10 d4 noninverting differential input 4. internal 250k ? to v cc and 150k ? to v ee . 11 d4 inverting differential input 4. internal 150k ? to v cc and 150k ? to v ee . 12, 13 v ee negative supply 14 v bb2 reference output voltage 2. connect to the inverting or noninverting data input to provide a reference for single-ended operation. when used, bypass v bb2 to v cc with a 0.01f ceramic capacitor. otherwise leave open. 15 v bb1 reference output voltage 1. connect to the inverting or noninverting data input to provide a reference for single-ended operation. when used, bypass v bb1 to v cc with a 0.01f ceramic capacitor. otherwise leave open. 16 q1 inverting output 1. typically terminate with 50 ? resistor to v cc - 2v. 17 q1 noninverting output 1. typically terminate with 50 ? resistor to v cc - 2v. 19 q0 inverting output 0. typically terminate with 50 ? resistor to v cc - 2v. 20 q0 noninverting output 0. typically terminate with 50 ? resistor to v cc - 2v. 21 sel0 select logic input 0. internal 120k ? pulldown to v ee . 22 sel1 select logic input 1. internal 120k ? pulldown to v ee . 23 sel2 select logic input 2. internal 120k ? pulldown to v ee . max9387 pin description
max9386/max9387/max9388 differential 5:1 or 4:1 ecl/pecl multiplexers with single/dual output buffers 8 _______________________________________________________________________________________ figure 1. input definitions differential input voltage definition v cc v ee v cc v ih v il v bb v ee v ihd - v ild v ihd (max) v ild (max) v ihd (min) v ild (min) v ihd - v ild single-ended input voltage definition figure 2. differential input-to-output propagation delay timing diagram v oh v ol v ihd - v ild v oh - v ol v oh - v ol v oh - v ol v ihd t plhd t r t f t phld v ild 20% 80% differential output waveform 0v (differential) 20% 80% d_ d_ q_ q_ q_ - q_ figure 3. single-ended input-to-output propagation delay timing diagram v oh - v ol t plh1 t phl1 v oh v ol v ih v bb v bb v il d_ when d_ = v bb q_ q_ d_ when d_ = v bb or
max9386/max9387/max9388 differential 5:1 or 4:1 ecl/pecl multiplexers with single/dual output buffers _______________________________________________________________________________________ 9 figure 4. select input (sel0)-to-output (q_, q_ ) delay timing diagram v oh - v ol t plh2 t phl2 v oh v ol v ih v ihd v bb v il v ild v ihd - v ild q_ d_, d1 q_ d_, d1 sel_ = v il or open selo figure 5. output-to-output skew (t skoo ) definition (max9387 only) t skoo t skoo q0 q0 q1 q1 figure 6. input-to-output skew (t skio) definition d1 or d2 or d3 d0 d0 d1 or d2 or d3 q0 q0 q0 q0 t skio = | t plhd * - t plhd ** | or | t phld * - t phld ** | t plhd *t phld * t plhd ** t phld ** t plhd *: measured between d0, d0 input, and output. t plhd **: measured between any other input and output.
max9386/max9387/max9388 detailed description the max9386/max9387/max9388 are fully differential, high-speed, and low-jitter ecl/pecl muxes with output buffer(s). the devices are designed for clock-and-data distribution applications, and feature extremely low propagation delays (318ps, typ) and output-to-output skews (3.9ps, typ). the max9386 is a 5:1 mux with a single output buffer. the max9387 is a 5:1 mux with dual output buffers, and is intended for use in redun- dant systems. the max9388 is a 4:1 mux with a single output buffer, and is pin compatible with the mc100ep57. three single-ended select inputs, sel0, sel1, and sel2, control the mux function on the max9386/ max9387. the max9388 has two select inputs, sel0 and sel1 ( see tables 1 and 2). the mux select inputs are compatible with ecl/pecl logic, and are internally referenced to the on-chip output v bb, nominally v cc - 1.425v. the select inputs accept signals between v cc and v ee . internal 120k ? pulldowns to v ee ensure a low default condition if the select inputs are left open, selecting the d0, d0 input. the differential inputs d, d can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference voltage v bb. the reference output voltages, v bb1 and v bb2, provide the reference voltage for single-ended opera- tion for each mux. a single-ended input of at least v bb _ 100mv or a di fferential input of at least 100mv switches the outputs to the v oh and v ol levels specified in the dc electrical characteristics. the maximum magnitude of the differential input from d to d is 3.0v. this limit also applies to the difference between a single-ended input and any reference voltage input. specifications for the high and low voltages of a differ- ential input (v ihd and v ild ) and the differential input voltage (v ihd - v ild ) apply simultaneously. single-ended operation the recommended supply voltage for single-ended operation is 3.0v to 5.5v. the differential inputs (d, d ) can be configured to accept single-ended inputs when operating at supply voltages greater than 2.725v. in single-ended mode operation, the unused complemen- tary input needs to be connected to the on-chip refer- ence voltage, v bb , as a reference. for example, the differential d, d input is converted to a noninverting, single-ended input by connecting v bb to d and con- necting the single-ended input to d. similarly, an invert- ing input is obtained by connecting v bb to d and connecting the single-ended input to d . with a differen- tial input configured as single ended (using v bb ), the single-ended input can be driven to v cc or v ee or with a single-ended lvpecl/lvecl signal. in single-ended mode operation, a user must ensure that the supply voltage (v cc - v ee ) is greater than 2.725v. this is because the input high minimum level must be at (v ee + 1.2v) or higher for proper operation. the reference voltage, v bb , must be at least (v ee + 1.2v) for the same reason because it becomes the high- level input when a single-ended input swings below it. the minimum v bb output for the max9386/max9387/ max9388 is (v cc - 1.38v). substituting the minimum v bb output for (v bb = v ee + 1.2v) results in a minimum supply (v cc - v ee ) of 2.725v. rounding up to standard supplies gives the recommended single-ended operat- ing supply ranges (v cc - v ee ) of 3.0v to 5.5v. when using the v bb reference output, bypass it with a 0.01f ceramic capacitor to v cc . if not used, leave it open. the v bb reference can source or sink a total of 0.5ma (shared between v bb1 and v bb2 ), which is suffi- cient to drive five inputs. differential 5:1 or 4:1 ecl/pecl multiplexers with single/dual output buffers 10 ______________________________________________________________________________________ table 1. mux select input truth table for max9386/max9387 sel2 sel1 sel0 data output l or open l or open l or open d0* l or open l or open hd1 l or open h l or open d2 l or open hh d3 hxx d4 * default output when sel0, sel1, and sel2 are left open. sel1 sel0 data output l or open l or open d0* l or open h d1 h l or open d2 hhd3 * default output when sel0 and sel1 are left open. table 2. mux select input truth table for max9388
applications information output termination terminate the outputs through 50 ? to v cc - 2v or use equivalent thevenin terminations. terminate each q and q output with identical termination on each for min- imal distortion. when a single-ended signal is taken from the differential output, terminate both q and q . ensure that output currents do not exceed the current limits as specified in the absolute maximum ratings table. under all operating conditions, the device s total thermal limits should be observed. supply bypassing bypass v cc to v ee with high-frequency surface-mount ceramic 0.1f and 0.01f capacitors. for pecl, bypass each v cc to v ee . for ecl, bypass each v ee to v cc . place the capacitors as close to the device as possible with the 0.01f capacitor closest to the device pins. use multiple vias when connecting the bypass capaci- tors to ground. when using the v bb1 or v bb2 reference outputs, bypass each one with a 0.01f ceramic capacitor to v cc . if the v bb1 or v bb2 reference outputs are not used, they can be left open. traces circuit board trace layout is very important to maintain the signal integrity of high-speed differential signals. maintaining integrity is accomplished in part by reduc- ing signal reflections and skew, and increasing com- mon-mode noise immunity. signal reflections are caused by discontinuities in the 50 ? characteristic impedance of the traces. avoid dis- continuities by maintaining the distance between differ- ential traces, not using sharp corners or using vias. maintaining distance between the traces also increases common-mode noise immunity. reducing signal skew is accomplished by matching the electrical length of the differential traces. chip information transistor count: 583 process: bipolar max9386/max9387/max9388 differential 5:1 or 4:1 ecl/pecl multiplexers with single/dual output buffers ______________________________________________________________________________________ 11 v bb1 v bb2 v cc v ee v cc v ee mux 150k ? 150k ? 120k ? 150k ? 250k ? d0 d0 d1 d1 d2 d2 d3 d3 d4** sel0 sel1 sel2** d4** q0 (q*) q0 (q*) max9386 (*) does not have q1 and q1 outputs, and max9388 (**) does not have d4, d4, and sel2 inputs. q1* q1* d_ d_ max9386 max9387 max9388 v ee functional block diagram ordering information (continued) part temp range pin- package selection max9387 eug -40 c to +85 c 24 tssop 5:1 mux with 2 output buffers m ax 9387e e g * -40 c to +85 c 24 qsop 5:1 mux with 2 output buffers max9388 eup -40 c to +85 c 20 tssop 4:1 mux with 1 output buffer max9388eep* -40 c to +85 c 20 qsop 4:1 mux with 1 output buffer * future productcontact factory for availability.
max9386/max9387/max9388 differential 5:1 or 4:1 ecl/pecl multiplexers with single/dual output buffers 12 ______________________________________________________________________________________ top view 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 v cc sel1 sel0 v cc d1 d1 do v cc do q q v cc v bb1 d3 d3 d2 d2 12 11 9 10 v bb2 v ee v ee max9388 1 2 3 4 5 6 7 8 v cc sel2 sel1 sel0 d1 d1 do do v cc q0 q0 v cc v bb1 d3 d3 d2 d2 9 10 v bb2 v ee d4 d4 max9387 tssop/qsop tssop/qsop q1 q1 14 13 11 12 v ee 24 23 22 21 20 19 18 17 16 15 pin configurations (continued)
max9386/max9387/max9388 differential 5:1 or 4:1 ecl/pecl multiplexers with single/dual output buffers ______________________________________________________________________________________ 13 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) tssop4.40mm.eps
max9386/max9387/max9388 differential 5:1 or 4:1 ecl/pecl multiplexers with single/dual output buffers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qsop.eps

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