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? semiconductor components industries, llc, 2011 april, 2011 ? rev. 0 1 publication order number: ncp1093/d ncp1093, ncp1094 integrated ieee 802.3af poe-pd interface controller description the ncp1093 and ncp1094 are members of on semiconductor?s high power hipo power over ethernet powered device (poe ? pd) product family and integrate an ieee 802.3at poe ? pd interface controller. both variants incorporate the required functions such as detection, classification, under voltage lockout, inrush and operational current limit. a power good and nclass_at signal have been added to guarantee proper enabling/disabling of the dc ? dc controller for both type ? i and type ? ii operation. in addition, the ncp1093 offers a programmable under ? voltage while the ncp1094 provides an auxiliary pin for applications supporting auxiliary supplies. the ncp1093 and ncp1094 are fabricated in a robust high voltage process and integrate a rugged vertical n ? channel dmos suitable for the most demanding environments and capable of withstanding harsh environments such as hot swap and cable esd events. the ncp1093 and ncp1094 complement on semiconductor?s assp portfolio in industrial devices and can be combined with stepper motor drivers, can bus drivers and other high ? voltage interfacing devices to offer complete solutions to the industrial and security market. features ? fully supports ieee 802.3af/at specifications ? programmable classification current ? support two event classification ? signature ? adjustable under voltage lock out (ncp1094 only) ? open ? drain power good indicator ? 130 ma inrush current limit ? 500 ma operational current limit ? pass switch disabling input for rear auxiliary supply operation (ncp1094 only) ? over ? temperature protection ? industrial temperature range ? 40 c to 85 c with full operation up to 125 c junction temperature ? 0.6 hot ? swap pass ? switch ? vertical n ? channel dmos pass ? switch offers the robustness of discrete mosfets http://onsemi.com pin configuration (top view) rtn pgood * vportp class det inrush 1 vportn1 dfn10 mn suffix case 485c device package shipping ? ordering information ncp1093mng dfn10 (pb ? free) 120 units / tube ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. * ncp1093 = uvlo ncp1094 = aux ncp10 93mn alyw ncp109xmn = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package (note: microdot may be in either location) pin configuration nclass_at vportn2 ncp10 94mn alyw ncp1093mnrg dfn10 (pb ? free) 3000 / tape & reel ncp1094mng dfn10 (pb ? free) 120 units / tube ncp1094mnrg dfn10 (pb ? free) 3000 / tape & reel
ncp1093, ncp1094 http://onsemi.com 2 figure 1. ncp1093/94 functional block diagram internal supply & voltage reference inrush current limit classification detection vportn vportp class inrush thermal shutdown hot swap switch control & current limit blocks uvlo external uvlo rtn vport monitor det pgood power good indicator ncp1093 only ncp1094 only ieee interface shutdown (aux supply priority) aux selection nclass_at dual event indicator classification operational current limit
ncp1093, ncp1094 http://onsemi.com 3 simplified application diagrams figure 2. typical application circuit using the ncp1093 with external uvlo setting figure 3. typical application circuit using the ncp1094 ncp1093 data pairs cline spare pairs rclass rinrush rdet rj ? 45 db1 db2 z_line rtn vportn class inrush uvlo vportp det to dc ? dc converter cpd pgood ncp1094 data pairs cline spare pairs rclass rinrush rj ? 45 db1 db2 z_line rtn vportn class inrush aux vportp det to dc ? dc converter cpd pgood rdet nclass_at ruvlo1 ruvlo2 vaux (+) nclass_at vaux ( ? )
ncp1093, ncp1094 http://onsemi.com 4 table 1. pin description name pin no. type description ncp1093 ncp1094 inrush 1 1 output current limit programming pin. connect a resistor between inrush and vportn. class 2 2 output classification current programming pin. connect a resistor between class and vportn. det 3 3 output, open drain detection pin. connect a 24.9 k resistor between det and vportp for a valid pd detection signature. vportn1 4 4 ground negative input power. connected to the source of the internal pass ? switch vportn2 5 5 ground negative input power. connected to the source of the internal pass ? switch rtn 6 6 ground dc ? dc controller power return. connected to the drain of the internal pass ? switch pgood 7 7 output, open drain open drain power good indicator. pin is in hz mode when the power good signal is active. uvlo 8 ? input undervoltage lockout input. voltage with respect to vportn. connect a resist- or ? divider from vportp to uvlo to vportnx to set an external uvlo threshold. aux ? 8 input auxiliary pin. when this pin is pulled up, the pass switch is disabled and allows a supply transition from pse to the rear auxiliary supply connected between vportp and rtn. nclass_at 9 9 output active low enable signal used to verify high power operation vportp 10 10 input positive input power. voltage with respect to vportn. table 2. absolute maximum ratings symbol parameter min max units conditions vportp input power supply ? 0.3 72 v voltage with respect to vportn rtn analog ground supply 2 ? 0.3 72 v pass ? switch in off ? state (voltage with respect to vportn) class analog output ? 0.3 72 v voltage with respect to vportn inrush analog output ? 0.3 3.6 v voltage with respect to vportn aux analog input ? 0.3 72 v voltage with respect to vportn uvlo analog input ? 0.3 3.6 v voltage with respect to vportn pgood analog output ? 0.3 72 v voltage with respect to rtn ta ambient temperature ? 40 85 c tj junction temperature ? 125 c tj ? tsd junction temperature (note 1) ? 175 c thermal shutdown condition t stg storage temperature ? 55 150 c t ja thermal resistance, junction to air (note 2) 50 c/w dfn ? 10 esd ? hbm human body model 2 kv per eia ? jesd22 ? a114 standard esd ? cdm charged device model 500 v per esd ? stm5.3.1 standard esd ? mm machine model 200 v per eia ? jesd22 ? a115 ? a standard lu latch ? up 100 ma per jedec standard jesd78 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. tj ? tsd allowed during error conditions only. it is assumed that this maximum temperature condition does not occur more than 1 hour cumulative during the useful life for reliability reasons. 2. low ja is obtained with 2s2p test board (2 signal ? 2 plane). high ja is obtained with double sideboard with minimum pad area and natural convection. refer to jedec jesd51 for details. the exposed pad must be connected to the vportn ground pin.
ncp1093, ncp1094 http://onsemi.com 5 recommended operating conditions operating conditions define the limits for functional operation and parametric characteristics of the device. note that the functionality of the device outside the operating conditions described in this section is not warranted. operating outside the recommended operating conditions for extended periods of time may affect device reliability. table 3. operating conditions (all values are with respect to vportn unless otherwise noted.) symbol parameter min typ max units conditions input supply vport input supply voltage 0 ? 57 v vport = vportp ? vportn signature detection offset_det1 i (vportp) + i (rtn) ? 2 5 a vportp = rtn = 1.9 v rdet = 24.9 k sleep_det1 i (vportp) + i (rtn) ? 15 21 a vportp = rtn = 9.8 v rdet = 24.9 k offset_det2 i (vportp) + i (rtn) + i (det) 73 77 81 a vportp = rtn = 1.9 v rdet = 24.9 k sleep_det2 i (vportp) + i (rtn) + i (det) 390 400 412 a vportp = rtn = 9.8 v rdet = 24.9 k classification vcl_on classification current turn ? on lower threshold 9.8 11.3 13 v vportp rising vcl_off classification current turn ? off upper threshold 21 ? 24 v vportp rising vclass_reg classification buffer output voltage ? 9.8 ? v 13 v < vportp < 21 v icl_bias i(vportp) quiescent current during classification ? 600 ? a i(class) excluded 13 v < vportp < 21 v iclass0 class 0: rclass 4420 (note 3) 0 ? 4 ma 13 v < vportp < 21 v iclass1 class 1: rclass 953 (note 3) 9 ? 12 ma 13 v < vportp < 21 v iclass2 class 2: rclass 549 (note 3) 17 ? 20 ma 13 v < vportp < 21 v iclass3 class 3: rclass 357 (note 3) 26 ? 30 ma 13 v < vportp < 21 v iclass4 class 4: rclass 255 (note 3) 36 ? 44 ma 13 v < vportp < 21 v v_mark mark event voltage range 5.4 9.7 v vportp falling i_mark i (vportp) + i (rdet) during mark event range 0.5 ? 2 ma 5.4 v vportp 9.7 v dr_mark input signature during mark event (note 4) ? ? 12 k vreset classification reset range 4.3 4.9 5.4 v vportp falling nclass_at 2 event classification indicator inclass i (nclass_at) sinking current ? ? 5 ma nclass_low nclass_at voltage output low ? 0.2 0.5 v i (nclass_at) = 2 ma uvlo ? internal setting ? ncp1093/94 vuvlo_on default turn on voltage ? 37 40 v vportp rising vuvlo_off default turn off voltage 29.6 31 ? v vportp falling vhyst_int uvlo internal hysteresis ? 6 ? v uvlo_filter uvlo on / off filter time ? 100 ? s for information only 3. a tolerance of 1% on the rclass resistor is included in the min/max values. 4. measured with the 2 point measurement defined in the ieee 802.3af standard with 5.4 v and 9.7 v the extreme values for v2 & v 1.
ncp1093, ncp1094 http://onsemi.com 6 table 3. operating conditions (all values are with respect to vportn unless otherwise noted.) symbol conditions units max typ min parameter uvlo ? external setting ? ncp1093 only vuvlo_pr uvlo external programming range 25 ? 50 v vportp rising vuvlo_on2 external uvlo turn on voltage 1.14 1.2 1.26 v vhyst_off2 external uvlo turn off voltage 0.95 1 1.05 v uvlo_ipd uvlo internal pull down current ? 2.5 ? a auxiliary supply setting ? ncp1094 only aux_h aux input high level voltage 3.1 ? v aux_l aux input low level voltage ? ? 0.6 v aux_pd aux internal pull down resistor 100 ? ? k for information only pass ? switch and current limiting ron pass ? switch rds ? on ? 0.6 1 measured with i(rtn) = 200 ma i_inrush inrush current with rinrush = 169 k 75 120 170 ma measured at rtn ? vportn = 3 v i_ilim operating current limit with rinrush = 169 k 610 680 800 ma current limit threshold power good indicator vds_pgood_on rtn ? vportn threshold voltage required for power good status 0.8 1 1.2 v rtn ? vportn falling vds_pgood_off rtn ? vportn latchoff threshold voltage 9 10 11 v rtn ? vportn rising pgood_filter pgood filter time 100 s rising and falling / for information only ipgood i (pgood) sinking current ? ? 5 ma vpgood_low pgood voltage output low ? 0.2 0.5 v i (pgood) = 2 ma voltage with respect to rtn current consumption ivportp i (vportp) internal current consumption ? 600 900 a vportp = 48 v thermal shutdown tsd thermal shutdown threshold 150 ? ? c tj tj = junction temperature thyst thermal hysteresis ? 15 ? c tj tj = junction temperature thermal ratings ta ambient temperature ? 40 ? 85 c tj junction temperature ? ? 125 c 3. a tolerance of 1% on the rclass resistor is included in the min/max values. 4. measured with the 2 point measurement defined in the ieee 802.3af standard with 5.4 v and 9.7 v the extreme values for v2 & v 1.
ncp1093, ncp1094 http://onsemi.com 7 description of operation powered device interface the integrated pd interface supports the ieee 802.3af defined operating modes: detection signature, current source classification, undervoltage lockout, inrush and operating current limits. the following sections give an overview of these previous processes. detection during the detection phase, the incremental equivalent resistance seen by the pse through the cable must be in the ieee 802.3af standard specification range (23.70 k to 26.30 k ) for a pse voltage from 2.7 v to 10.1 v. in order to compensate for the non ? linear effect of the diode bridge and satisfy the specification at low pse voltage, the ncp1093/94 present a suitable impedance in parallel with the 24.9 k rdet external resistor. for some types of diodes (especially schottky diodes), it may be necessary to adjust this external resistor. the rdet resistor has to be inserted between vportp and det pins. during the detection phase, the det pin is pulled to ground and goes in high impedance mode (open ? drain) once the device exit this mode, reducing thus the current consumption on the cable. classification once the pse device has detected the pd device, the classification process begins. in classification, the pd regulates a constant current source that is set by the external resistor rclass value on the class pin. figure 4 shows the schematic overview of the classification block. the current source is defined as: iclass 9.8 v rclass figure 4. classification block diagram class vportp 1.2 v en class_enable vportp vportn 9.8 v the ncp1093/94 is able to detect a dual event classification generated by a type 2 pse, and flag it using its nclass_at open drain indicator. power mode when the classification hand ? shake is completed, the pse and pd devices move into the operating mode. under voltage lock out (uvlo) the ncp1093/94 incorporate a fixed under voltage lock out (uvlo) circuit which monitors the input voltage and determines when to turn on the pass switch and charge the dc ? dc converter input capacitor before the power up of the application. the ncp1093 offers a fixed or adjustable vuvlo_on threshold depending if the uvlo pin is used or not. in figure 5, the uvlo pin is strapped to ground and the vuvlo_on threshold is defined by the internal level. figure 5. default internal uvlo configuration (ncp1093 only) uvlo vportp vportn1,2 vport to define the uvlo threshold externally, the ulvo pin must be connected to the center of an external resistor divider between vportp and vportn as shown in figure 6. in order to guarantee the detection signature, the equivalent input resistor made of the ruvlo1, ruvlo2 and rdet should be equal to 24.9 k . uvlo vportn1,2 vport ruvlo2 ruvlo1 vportp ncp1093 det rdet figure 6. default internal uvlo configuration (ncp1093 only) for a vuvlo_on desired turn ? on voltage threshold, ruvlo1 and ruvlo2 can be calculated using the following equations: ruvlo 24.9 k rdet rdet 24.9 k ruvlo1 ruvlo2 ruvlo with ruvlo2 1.2 vuvlo_on ruvlo and with: vuvlo_on: desired turn ? on voltage threshold
ncp1093, ncp1094 http://onsemi.com 8 example for a targeted uvlo_on of 35 v: let?s start with a rdet of 30.1 k . this gives a ruvlo of 144 k made with a ruvlo2 of 4.99 k and a ruvlo1 of 140 k (closest values from e96 series). note that there is a pull down current of 2.5 a typ on the uvlo. assuming the previous example, this pull down current will create a (non critical) systematic offset of 350 mv on the uvlon_on level of 35 v. the external uvlo hysteresis on the ncp1093 is about 15 percent typical. inrush and operational current limitations both inrush and operational current limit are defined by an external rinrush resistor connected between inrush and vportn. the low inrush current limit allows smooth charge of large dc ? dc converter input capacitor by limiting the power dissipation over the internal pass switch. in power mode, the operational current limit protects the pass switch and the pd application against excessive transient current and failure on the dc ? dc converter output. once the input supply reached the vulvo_on level, the charge of cpd capacitor starts with a current limitation set to to the inrush level. when this capacitor is fully charged, the current limit switches without any spikes from the inrush current to the operational current level and the power good indicator on pgood pin is turned on. the capacitor is considered to be fully char ged once the following conditions are satisfied: 1. the drain ? source voltage of the pass switch has decreased below the vds_pgood_on level (typical 1v) 2. the gate ? source voltage of the pass switch is sufficiently high (above 2 v typical) which means the current in the pass switch has decreased below the current limit. this mechanism is depicted in the following figure 7. operational current limit vportnx pass switch inrush current limit rtn 0 1 vdda1 vdda1 1 v / 10 v 2 v delay & detector pgood pgood_on vdda1 rtn pgood_on sense resistor vds_pgood comparator vgs_pgood comparator figure 7. inrush and operational current limitation selection mechanism 100 s the operational current limit and the power good indicator stays active as long as r tn voltage stays below the vds_pgood_off threshold (10 v typical) and the input supply stay above the vulvo_off level. therefore, fast and large voltage step lower than 10 v are tolerated on the input without interruption of the converter controller. higher input transient will not affect the behavior if rtn does not exceed 10 v for more than 100 s. such input voltage steps may be introduced by a pse which is switched to a higher power supply. in case rtn is still above 10 v after this delay, the power good is turned off and the pass switch current limit falls back to the inrush level. pgood indicator the ncp1093/94 integrate a power good indicator circuitry indicating the end of the dc ? dc converter input capacitor charge, and the enabling of the operational current limit. this indicator is implemented on the pgood pin which goes in open drain state when active and which is pulled to ground during turn off. a possible usage of this pgood pin is illustrated in figure 8. during the inrush phase, the converter controller is forced in standby mode due to the pgood pin forcing low the under voltage lock out pin of the controller. once the cpd capacitor is fully charged, pgood goes in open drain state, allowing the start up sequence of the converter controller.
ncp1093, ncp1094 http://onsemi.com 9 ncp109x rclass rinrush rtn vportn class inrush vportp det cpd pgood dc ? dc converter controller vss vdd ovlo uvlo gate rdet figure 8. power good implementation ncp103x nclass_at dual event classification indicator the nclass at active low open drain output pin should be used to notify to the microprocessor of the powered device that the pse did a one or two event hardware classification. if a 2 event hardware classification has been done and once the pd application is supplied by the hipo dc/dc, the nclass_at will be pulled low to rtn (ground connection of the dc/dc controller converter). otherwise, nclass_at will be in high impedance mode. the following scheme illustrates how the nclass_at pin may be configured with the processor of the powered device. an optocoupler is here used to guarantee to the full isolation between the cable and the application. ncp 1094 cl ine rclass rinrush z_line rtn vportn nclass _at class inrush aux vportp det cpd pgood dc ? dc converter controller vss vdd ovlo uvlo gate powered application vbias type 2pse vsup vneg to vaux rdet figure 9. nclass at indicator / possible implementation with the powered device as soon as the application is powered by the dc/dc and after its initialization, the microprocessor will check if the pd interface detected a 2 event hardware classification by reading its digital input ( in1 in this example). if this in1 pin is low, the application knows that the type 2 pse, and therefore it can consume power till the level specified by the ieee802.3at standard. otherwise the application will have to perform a layer 2 classification with the pse. hereafter are described several scenarios for which hipo will not enable its nclass_at pin during the powered mode: ? the pse skipped the classification phase ? the pse did a 1 event hardware classification (it can be a type 1 pse or a type 2 pse with layer 2 only) ? the pse did a 2 event hardware classification but it didn?t well control the input voltage in the mark voltage (it crossed the reset range for example).
ncp1093, ncp1094 http://onsemi.com 10 auxiliary supply to support application connected to non ? poe enabled networks and minimize the bill of materials, the ncp1093 supports drawing power from an external supply and allows simplified designs with poe or auxiliary supply priorities. in most of the cases, the auxiliary supply is connected between vportp and rtn with a serial diode between vportp and vaux, as shown in figure 10. ncp1094 data pairs cline spare pairs rclass rinrush rj ? 45 db1 db2 z_line rtn vportn class inrush aux vportp det to dc ? dc converter cpd pgood rdet vaux (+) vaux ( ? ) figure 10. auxiliary supply dominant pd interface the ncp1094 offers an aux input pin which turns off the pass switch when pulled high. this feature is useful for pd applications where the auxiliary supply has to be dominant over the poe supply. when the auxiliary supply is inserted on a poe powered application, the pass switch disconnection will move the current path from the pse to the rear auxiliary supply. since the current delivered by the pse will goes below the dc mps level (specified in ieee 802.3 af/at standard), the pse will disconnect the poe ? pd and the application will remain supplied by the auxiliary supply. the transition will happens without any power conversion interruption since the pgood indicator stays active (high impedance state). next figure 11 depicts an other pd application where the poe supply is dominant over the vaux supply. a diode d1 has been added in order to not corrupt the pd detection signature when the dc ? dc converter is supplied by vaux. ncp1094 data pairs cline spare pairs rclass rinrush rj ? 45 db1 db2 z_line rtn vportn class inrush aux vportp det to dc ? dc converter cpd pgood rdet vaux (+) vaux ( ? ) d1 figure 11. poe supply dominant pd interface
ncp1093, ncp1094 http://onsemi.com 11 thermal shutdown the ncp1093/94 include a thermal shutdown which protect the device in case of high junction temperature. once the thermal shutdown (tsd) threshold is exceeded, the classification block, the pass switch and the pgood indicator are disabled. the ncp109x returns automatically to normal operation once the die temperature has fallen below the tsd low limit. company or product inquiries for more information about on semiconductor?s power over ethernet products visit our web site at http://www.onsemi.com .
ncp1093, ncp1094 http://onsemi.com 12 package dimensions dfn10, 3x3, 0.5p case 485c ? 01 issue b 10x seating plane l d e 0.15 c a a1 e d2 e2 b 15 10 6 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. terminal b may have mold compound material along side edge. mold flashing may not exceed 30 microns onto bottom surface of terminal b. 6. details a and b show optional views for end of terminal lead at edge of package. ??? ??? ??? ??? b a 0.15 c top view side view bottom view pin 1 reference 0.10 c 0.08 c (a3) c 10x 10x 0.10 c 0.05 c a b note 3 k 10x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 2.40 2.60 e 3.00 bsc e2 1.70 1.90 e 0.50 bsc l 0.35 0.45 l1 0.00 0.03 detail a k 0.19 typ 2x 2x l1 detail a bottom view (optional) *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.1746 2.6016 1.8508 0.5000 pitch 0.5651 10x 3.3048 0.3008 10x dimensions: millimeters on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ncp1093/d all brand names and product names appearing in this document are registered trademarks or trademarks of their respective holder s. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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