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1/24 ? semiconductor msm66585/586/587/p587/q587 ? semiconductor msm66585/586/587/p587/q587 built-in 16 bit pwm and 8 bit a/d converter, high-speed high-preformance 16 bit microcontroller preliminary general description msm66585/586/587 are high-performance cmos 16-bit microcontrollers that integrate a 16- bit cpu, rom, ram, 8-bit a/d converter, serial port, timers, and pwm. they also allow rom and ram to be expanded externally. the msm66p587 is of otp (one-time prom) version and the msm66q587 is of flash eeprom version. features ? powerful instruction set instruction set superior in orthogonal matrics 8/16-bit arithmetic instructions multiply/divide instructions bit manipulation instructions bit logical operation instructions rom table reference instructions ? abandant addressing modes register addressing page addressing pointer register indirect addressing stack addressing immediate addressing ? minimum instruction cycle 100 ns at 20 mhz (4.5v-5.5v) 200 ns at 10 mhz (2.7v-5.5v) ? program memory (rom) internal: 64 kb (m66587/m66p587/m66q587), 48 kb (m66585/586) external: 1 mb, ea pin active ? data memory (ram) internal: 2 kb external: 1022 kb ? i/o ports analog input-only port: 4 lines (test pins for m66585) input/output port: maximum 80 lines (40 lines with programmable pull-up) ? timers free-running counter: 16-bit 1 realtime output: 16-bit 2 general autoreload timer: 8-bit 1 ? 16-bit pwm input clock divider: 1 divider ? 8-bit serial port synchronous with brg: 1 port e2e1033 -27-y6 this version: jan. 1998 previous version: nov. 1996
2/24 ? semiconductor msm66585/586/587/p587/q587 ? a/d converter 8-bit resolution: 4 channels ? interrupts non-maskable: 1 interrupt maskable: 9 internal, 4 external (12 vectors) 3-level priority ? rom window function ? standby modes halt mode stop mode ? package 100-pin tqfp (tqfp100-p-1414-0.50-k) (product name : msm66585ts-k) (product name : msm66586ts-k) (product name : msm66587ts-k) (product name : msm66p587ts-k) (product name : msm66q587ts-k)
3/24 ? semiconductor msm66585/586/587/p587/q587 block diagram ssp lrb psw pc alu alu control acc system control instruction decoder rom 64 kb memory control pointing r local r. ram 2 kb ea ale/p5_5 psen /p5_4 rd /p7_1 wr /p7_0 wait/p7_2 ad0/p0_0 ad7/p0_7 a8/p1_0 a15/p1_7 a16/p9_0 a19/p9_3 control registers cpu core 16-bit rto/pwm timer serial port pwm a to d converter event timer interrupt peripheral port control *1 dsr tsr csr *2 res osc1 osc0 p12 p10 p9 p8 p7 p6 p5 p4 p2 p1 p0 bus port control p2_4/rt08 p2_5/rto9 p6_2/rxd1 p6_3/txd1 p6_4/rxc1 p6_5/txc1 p7_4/pwm0 v ref agnd ai0 ai3 p4_0/etmck p6_0/into p6_1/int1 p12_2/int2 p12_3/int3 nmi p7_3/clkout *1. 48kb for m66585 and m66586. *2. m66585 has no internal a/d converter.
4/24 ? semiconductor msm66585/586/587/p587/q587 pin configuration (top view) 75 1 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 ale/p5_5 p5_4 psen /p5_4 wr /p7_0 rd /p7_1 wait/p7_2 clkout/p7_3 pwm0/p7_4 p7_5 p7_6 p7_7 gnd osc1 osc0 v dd ea nmi res p8_7 p8_6 p8_5 p8_4 p8_3 p8_2 p8_1 p8_0 p9_7 p2_0 p2_1 p2_2 p2_3 p2_4/rt08 p2_5/rt09 p2_6 p2_7 p10_0 p10_1 p10_2 p10_3 p10_4 p10_5 p10_6 p10_7 v dd gnd p6_0/int0 p6_1/int1 p6_2/rxd1 p6_3/txd1 p6_4/rxc1 p6_5/txc1 12_0 74 p9_4 73 p9_3/a19 72 p9_2/a18 71 p9_1/a17 70 p9_0/a16 69 gnd 68 v dd 67 p1_7/a15 66 p1_6/a14 65 p1_5/a13 64 p1_4/a12 63 p1_3/a11 62 p1_2/a10 61 p1_1/a9 60 p1_0/a8 59 p0_7/ad7 58 p0_6/ad6 57 p0_5/ad5 56 p0_4/ad4 55 p0_3/ad3 54 p0_2/ad2 53 p0_1/ad1 52 p0_0/ad0 51 2 p12_1 3 int2/p12_2 4 int3/p12_3 5 p12_4 6 p12_5 7 p12_6 8 p12_7 9 v dd 10 *(v dd ) v ref 11 (gnd) agnd 12 (test0) ai0 13 (test1) ai1 14 (test2) ai2 15 (test3) ai3 16 gnd 17 v dd 18 etmck/p4_0 19 p4_1 20 p4_2 21 p4_3 22 p4_4 23 p4_5 24 p4_6 25 p4_7 p9_6
p9_5 * for msm66585, pin name is in parentheses ( ).
5/24 ? semiconductor msm66585/586/587/p587/q587 pin descriptions symbol type description p0_0-p0_7/ ad0-ad7 i/o p1_0-p1_7/ a8-a15 i/o p2_0-p2_3 p2_4-p2_5/ rt08-rt09 p2_6-p2_7 i/o p4_0/etmck p4_1-p4_7 i/o p5_4/psen p5_5/ale i/o port 0 is 8 input/output pins. input or output can be specified for each bit with the port 0 mode register (p0io). pull-up resistors can be specified for each bit with the port 0 pull-up register (p0pup). these pins also function as time-multiplexed address outputs and data input/output pins (ad0-ad7) when accessing memory that has been expanded externally (program or data memory). after reset (by res signal input, brk instruction execution, or op code trap), p0 will be high-impedance inputs. port 1 is 8 input/output pins. input or output can be specified for each bit with the port 1 mode register (p1io). pull-up resistors can be specified for each bit with the port 1 pull-up register (p1pup). p1_0-p1_7 also have a secondary function as input/output pins for internal operation. their secondary function can be set for each bit with the port 1 secondary function control register (p1sf). the input/output settings by p1io will be ignored for pins that have been set to the secondary function by p1sf. these pins function as output pins for address a8-a15 when accessing program memory or data memory that has been expanded externally. when the ea pin is low, a8-a15 will be output regardless of p1sf settings. after reset (by res signal input, brk instruction execution, or op code trap), p1 will be high-impedance inputs. p2_4 and p2_5 also have a secondary function as input/output pins for internal operation. their secondary function can be set for each bit with the port 2 secondary function control register (p2sf). the input/output settings of p2io will be ignored for pins that have been set to the secondary function by p2sf. these pins output a previously set level when the value of timer registers 8 and 9 match a selected counter value. after reset (by res signal input, brk instruction execution, or op code trap), p2 will be high-impedance inputs. port 4 is 8 input/output pins. input or output can be specified for each bit with the port 4 mode register (p4io). pull-up resistors can be specified for each bit with the port 4 pull-up register (p4pup). p4_0 also has a secondary function as an input pin for internal operation. its secondary function can be set for the bit with the port 4 secondary function control register (p4sf). the input/output settings by p4io will be ignored for pins that have been set to the secondary function by p4sf. this is the external clock input pin for the counter of a general 8-bit timer. after reset (by res signal input, brk instruction execution, or op code trap), p4 will be high-impedance inputs. port 5 is 2 input/output pins. input or output can be specified for each bit with the port 5 mode register (p5io). p5_4 and p5_5 also have a secondary function as output pins for internal operation. their secondary function can be set for each bit with the port 5 secondary function control register (p5sf). the input/output settings of p5io will be ignored for pins that have been set to the secondary function by p5sf. psen (p5_4): this pin outputs the strobe signal for read operations when external program memory is accessed. operation will automatically switch to the secondary function when the ea pin is low. this pin will be pulled up when both the ea pin and reset pin are low. ale (p5_5): this pin outputs the strobe for externally latching the lower 8 address bits output from p0 when external memory is accessed. operation will automatically switch to the secondary function when the ea pin is low. this pin will be pulled up when both the ea pin and reset pin are low. after reset (by res signal input, brk instruction execution, or op code trap), p5 will be high-impedance inputs.
6/24 ? semiconductor msm66585/586/587/p587/q587 pin descriptions (continued) symbol type description p6_0/int0 p6_1/int1 p6_2/rxd1 p6_3/txd1 p6_4/rxc1 p6_5/txc1 port 6 is 6 input/output pins. input or output can be specified for each bit with the port 6 mode register (p6io). p6_0-p6_5 also have a secondary function as input/output pins for internal operation. their secondary function can be set for each bit with the port 6 secondary function control register (p6sf). the input/output settings of p6io will be ignored for pins that have been set to the secondary function by p6sf. int0 (p5_0), int1 (p6_1): these pins input external interrupts 0 and 1. rxd1 (p6_2): this pin inputs receive data to the serial port 1 receive circuit. txd1 (p6_3): this pin outputs transmit data to the serial port 1 transmit circuit. rxc1 (p6_4): this pin outputs the shift clock when the serial port 1 receive circuit is in master mode. it inputs the shift clock when the receive circuit is in slave mode. txc1 (p6_4): this pin outputs the shift clock when the serial port 1 transmit circuit is in master mode. it inputs the shift clock when the transmit circuit is in slave mode. after reset (by res signal input, brk instruction execution, or op code trap), p6 will be high-impedance inputs. i/o p7_0/ wr p7_1/ rd p7_2/wait p7_3/clkout p7_4/pwm0 p7_5-p7_7 port 7 is 8 input/output pins. input or output can be specified for each bit with the port 7 mode register (p7io). p7_0-p7_4 also have a secondary function as input/output pins for internal operation. their secondary function can be set for each bit with the port 7 secondary function control register (p7sf). the input/output settings of p7io will be ignored for pins that have been set to the secondary function by p7sf. wr (p7_0): this pin outputs the strobe signal for write operations when external data memory is accessed. rd (p7_1): this pin outputs the strobe signal for read operations when external data memory is accessed. wait (p7_2): this pin inputs a wait to the internal cpu when external data memory with a slow access time is accessed. cpu is driven to "wait" state during wait pin high. clkout (p7_3): this pin outputs the clock pulses set by the peripheral control register (prphf). pwm0 (p7_4): this pin outputs pwm0. after reset (by res signal input, brk instruction execution, or op code trap), p7 will be high-impedance inputs. when p7_0 and p7_1 are used as their secondary functions ( wr , rd ), they need to be connected externally to pull-up resistors. i/o p8_0-p8_7 i/o port 8 is 8 input/output pins. input or output can be specified for each bit with the port 8 mode register (p8io). after reset (by res signal input, brk instruction execution, or op code trap), p8 will be high-impedance inputs.
7/24 ? semiconductor msm66585/586/587/p587/q587 pin descriptions (continued) symbol type description p9_0p9_3/ a16-a19 p9_4-p9_7 i/o p10_0-p10_7 port 10 is 8 input/output pins. input or output can be specified for each bit with the port 10 mode register (p10io). pull-up resistors can be specified for each bit with the port 10 pull-up register (p10pup). after reset (by res signal input, brk instruction execution, or op code trap), p10 will be high-impedance inputs. i/o p12_0-p12_1 p12_2-p12_3/ int2-int3 p12_4-p12_7 i/o port 9 is 8 input/output pins. input or output can be specified for each bit with the port 9 mode register (p9io). pull-up resistors can be specified for each bit with the port 9 pull-up register (p9pup). p9_0-p9_3 also have a secondary function as output pins for internal operation. their secondary function can be set for each bit with the port 9 secondary function control register (p9sf). the input/output settings of p9io will be ignored for pins that have been set to the secondary function by p9sf. a16-a19 (p9_0-p9_3): these pins function as output pins for address a16-a19 when accessing program memory or data memory that has been expanded externally. note that program memory address a16-a19 will be output even when accessing data memory that has been expanded externally. when the ea pin is low and program memory that has been expanded externally is accessed, a16-a19 will be output regardless of p9sf settings. after reset (by res signal input, brk instruction execution, or op code trap), p9 will be high-impedance inputs. port 12 is 8 input/output pins. input or output can be specified for each bit with the port 12 mode register (p12io). p12_2 and p12_3 also have a secondary function as input pins for internal operation. their secondary function can be set for each bit with the port 12 secondary function control register (p12sf). the input/output settings of p12io will be ignored for pins that have been set to the secondary function by p12sf. int2 (p12_2), int3 (p12_3): these pins input external interrupts 2 and 3. after reset (by res signal input, brk instruction execution, or op code trap), p12 will be high-impedance inputs. ai0-ai3 these are analog input pins for the a/d converter (test pins for msm66585). i v ref this is the reference voltage pin for the a/d converter (v dd for msm66585). i agnd this is the ground input pin for the a/d converter (gnd for msm66585). i osc0 this pins connect to a crystal oscillator, ceramic oscillator, or capacitors for base clock oscillation. when the base clock is to be supplied externally, it should be input on the osc0 pin with the osc1 pin left open. i nmi this input pin requests a non-maskable interrupt. i res this is an active-low reset input pin. i ea i v dd these are voltage pins. all v dd pins (9, 17, 37, 67, 93) should be connected to the supply voltage (for msm66585 connect pins 9, 10, 17, 37, 67, 93). i gnd these are ground pins. all gnd pins (16, 40, 68, 94) should be connected to ground (for msm66585 connect pins 11, 16, 40, 68, 94). i when this pin is high, program addresses 0h-ffffh will access internal program memory and program addresses 10000h-fffffh will access external program memory. to access external program memory, p1, p5, and p9 must be set with their secondary function control registers. when this pin is low, all program addresses will access external program memory. osc1 o
8/24 ? semiconductor msm66585/586/587/p587/q587 memory map program area 17ffh 1800h ffffh 0fffh 1000h 0069h 006ah 0049h 004ah 0000h vector table area 74 bytes vcal table area 32 bytes acal area 2 kb acal area 2 kb 17ffh 1800h ffffh 0fffh 1000h 0000h external rom area segment 0 segment 1 to 15 internal rom area vector table area 8 bytes 0071h 0072h * for m66585 and m66586 addresses 0c000h to 0ffffh of segment 0 are external rom area.
9/24 ? semiconductor msm66585/586/587/p587/q587 data area 0000h 00ffh 0100h 01ffh 0200h 02ffh 0300h 09ffh 0a00h 0fffh 1000h external memory area sfr area expanded sfr area segment 0 segment 1-15 internal ram area local register setting area rom window setting area external memory area common area 1fffh 3fffh 7fffh 03ffh bcb common range 0 1 2 3 0-03ffh 0-1fffh 0-3fffh 0-7fffh sfr area expanded sfr area fix area usp dp x2 x1 usp x1 usp dp x2 x1 usp dp x2 x1 pointing register sets scb=0 scb=1 scb=7 expanded sfr area sba area 64 bytes fixed page area the sba area that can be accessed using sb, rb, jbs, and jbr instruction. 01ffh 0200h 0208h 0210h 0238h 0240h 02c0h 0300h 0000h 0fffh 1000h ffffh 7fffh 8000h ffffh rom window setting area fix area
10/24 ? semiconductor msm66585/586/587/p587/q587 area for setting local registers er0 r0 r1 er1 r2 r3 er2 r4 r5 er3 r6 r7 er0 r0 r1 0200h 0208h 0a00h r6 r7 lrbl= 00h lrbl= 01h lrbl= ffh er3 area for setting local registers: specify 8-byte block with 8-bits of lrbl 0000h 0100h 0200h 0300h 0a00h fix area expanded sfr area sfr area internal ram area external ram area fffffh
11/24 ? semiconductor msm66585/586/587/p587/q587 absolute maximum ratings digital power supply voltage symbol units conditions parameter rating input voltage output voltage analog power supply voltage analog reference voltage analog input voltage power dissipation storage temperature v dd v i v o av dd v ref v ai pd t stg gnd=agnd=0v ta=25c ta=70c per package per output C0.3 to +7.0 C0.3 to v dd +0.3 C0.3 to v dd +0.3 C0.3 to v dd +0.3 C0.3 to av dd +0.3 C0.3 to v ref C50 to +150 v v v v v v mw mw c 8 650 note: power and ground connections must be made to all external v dd and gnd pins. allowable output current "h" output pin (1 pin) symbol units pin parameter min. "h" output pin (total) "l" output pin (1 pin) "l" output pin (total) i oh s i oh i ol s i ol ma all output pins total of all output pins all output pins total of p0, p1, p5 and p7 total of p2, p9 and p10 total of p4 and p8 total of all output pins total of p6 and p12 typ. max. C2 C40 5 50 100 (v dd =2.7 to 5.5v, ta=C30 to +70c) recommended operating conditions symbol units conditions parameter range analog reference voltage analog input voltage memory hold voltage operating frequency temperature range fan-out v ref v ai v ddh f osc ta n ttl loads p0, p5_4, p5_5, p7_0, p7_1 p1, p2, p4, p6, p7_2-p7_7, p8-p10, p12 av dd C0.3 to av dd agnd to v ref 2.0 to 5.5 2 to 20 C30 to +70 2 1 v v v mhz c f osc =0hz v dd =5v10% v dd v f osc 20mhz 4.5 to 5.5 digital power supply voltage mos loads 20 f osc 10mhz 2.7 to 5.5 v dd =2.7 to 5.5v 2 to 10 mhz
12/24 ? semiconductor msm66585/586/587/p587/q587 electrical characteristics dc characteristics (v dd =5v 10%) input high voltage symbol units conditions parameter min input low voltage input low voltage output high voltage v ih v il v oh v (ta=C30 to +70c) input high voltage 0.44v dd typ max 1 2, 4, 5, 6, 7 1 2, 4, 5, 6, 7 1, 4 v dd +0.3 0.80v dd v dd +0.3 C0.3 0.16v dd C0.3 0.2v dd v dd C0.4 output high voltage 2 v dd C0.4 i o =C400 m a i o =C200 m a output low voltage v ol 1, 4 0.4 output low voltage 2 0.8 i o =3.2ma i o =1.6ma input leakage current input current input current i ih /i il 3, 6 5 7 v i =v dd /0v 1/C1 1/C250 15/C15 m a output leakage current 1, 2, 4 10 i lo v o =v dd /0v m a input capacitance output capacitance 5 7 c i c o f=1mhz, ta=25c pf 4 10 a/d conversion operating a/d conversion stopped ma m a i ref analog reference power supply current 0.2 10 1 100 v dd =2v, ta=25c* * m a i dds supply current (stop mode) supply current (halt mode) supply current i ddh i dd f osc =20mhz, no load ma pull-up resistor r pull v i =0v 50 k w 25 70 25 100 i o =C2.0 ma i o =C2.0 ma v dd C0.6 v dd C0.6 i o =5.0ma i o =5.0ma 0.4 0.8 10 45 2 1. applies to p0. 2. applies to p1, p2, p4, p6, p7_2-p7_7, p8-p10, p12. 3. applies to ain. 4. applies to p5_4, p5_5, p7_0, p7_1. 5. applies to res . 6. applies to ea , nmi. 7. applies to osc0. * for input ports, v dd or 0 v. for other cases, unloaded.
13/24 ? semiconductor msm66585/586/587/p587/q587 dc characteristics (2.7v v dd 5.5v) input high voltage symbol units conditions parameter min input low voltage input low voltage output high voltage v ih v il v oh v (ta=C30 to +70c) input high voltage 0.44v dd typ max 1 2, 4, 5, 6, 7 1 2, 4, 5, 6, 7 1, 4 v dd +0.3 0.80v dd v dd +0.3 C0.3 0.16v dd C0.3 0.2v dd v dd C0.4 output high voltage 2 v dd C0.4 i o =C400 m a i o =C200 m a output low voltage v ol 1, 4 0.5 output low voltage 2 0.5 i o =3.2ma i o =1.6ma input leakage current input current input current i ih /i il 3, 6 5 7 v i =v dd /0v 1/C1 1/C250 15/C15 m a output leakage current 1, 2, 4 10 i lo v o =v dd /0v m a input capacitance output capacitance 5 7 c i c o f=1mhz, ta=25c pf 4 10 a/d conversion operating a/d conversion stopped ma m a i ref analog reference power supply current 0.2 10 1 100 v dd =2v, ta=25c* * m a i dds supply current (stop mode) supply current (halt mode) supply current i ddh i dd f osc =10mhz, no load ma pull-up resistor r pull v i =0v,v dd =5v10% 50 k w 515 30 50 25 100 i o =C2.0 ma i o =C2.0 ma i o =5.0ma i o =5.0ma v dd C0.6 v dd C0.8 0.9 1.2 v i =0v, v dd =3v10% 100 v dd =5.5v v dd =3.3v v dd =5.5v v dd =3.3v v dd =5v10% v dd =3v10% 3 10 v dd =5v10% v dd =3v10% 13 25 40 200 2 5 1. applies to p0. 2. applies to p1, p2, p4, p6, p7_2-p7_7, p8-p10, p12. 3. applies to ain. 4. applies to p5_4, p5_5, p7_0, p7_1. 5. applies to res . 6. applies to ea , nmi. 7. applies to osc0. * for input ports, v dd or 0 v. for other cases, unloaded.
14/24 ? semiconductor msm66585/586/587/p587/q587 ac characteristics (v dd =5v 10%) ? external program memory control ale pulse width symbol units conditions parameter min psen pulse width psen pulse delay time low address setup time low address hold time high address setup time t fw t als ns (ta=C30 to +70c) clock (osc) pulse width 25 c l =50pf 2t f w C2 2t f w C5 t f w C3 2t f w C3 t f w C3 4t f w C3 high address hold time 0 instruction setup time 15 instruction hold time 0 max t f w +3 2t f w +3 t f w +3 4t f w +3 t f w +3 t f w C3 t aw t pw t pad t alh t is t ahs t aph t ih clk ale t f w t f w psen t aw t pad t pw ad 0-ad7 pc 0-7 inst 0-7 t als t alh t is t ih a 8-a19 pc 8-19 t ahs t aph
15/24 ? semiconductor msm66585/586/587/p587/q587 ? external data memory control ale pulse width symbol units conditions parameter min rd pulse width wr pulse width rd pulse delay time wr pulse delay time low address setup time t f w t rad ns (ta=C30 to +70c) clock (osc) pulse width 25 c l =50pf 2t f w C2 2t f w C5 2t f w C5 t f w C3 t f w C3 2t f w C3 low address hold time t f w C3 high address setup time 3t f w C3 high address hold time t f w C3 max t f w +3 t f w +3 2t f w +3 t f w +3 3t f w +3 t f w +3 t aw t rw t ww t wad t ahs t als t alh t ahh memory data setup time 15 memory data hold time 0 data delay time t alh C0 data hold time t f w C3 t f w C3 t alh +5 t f w +3 t dd t ms t mh t dh clk ale t f w t f w t aw rd t rad t rw ad 0-ad7 rap 0-7 din 0-7 t als t alh t ms t mh a 8-a19 rap 8-19 t ahs t ahh wr t wad t ww ad 0-ad7 rap 0-7 dout 0-7 t als t alh t dh a 8-a19 rap 8-19 t ahs t ahh t dd
16/24 ? semiconductor msm66585/586/587/p587/q587 ? serial port contorl master mode serial clock cycle time symbol units conditions parameter min. output data setup time output data hold time input data setup time input data hold time t f w t srmxs ns (ta=C30 to +70c) clock (osc) pulse width 25 c l =50pf 8t f w 4t f w C5 3t f w C10 20 0 typ. t sckc t stmxs t stmxh t srmxh max. t sckc sdout (txd) t stmxh sdin (rxd) t srmxs sck t stmxs t srmxh valid valid
17/24 ? semiconductor msm66585/586/587/p587/q587 ac timing mesurement point slave mode serial clock cycle time symbol units conditions parameter min. output data setup time output data hold time input data setup time input data hold time t f w t srmxs ns (ta=C30 to +70c) clock (osc) pulse width 25 c l =50pf 8t f w 2t f w C15 4t f w C10 20 0 typ. t sckc t stmxs t stmxh t srmxh max. t sckc sdout (txd) t stmxh sdin (rxd) t srmxs sck t stmxs t srmxh valid valid v dd 0v 0.8v dd 0.8v dd 0.2v dd 0.2v dd
18/24 ? semiconductor msm66585/586/587/p587/q587 ac characteristics (2.7v v dd 5.5v) ? external program memory control ale pulse width symbol units conditions parameter min psen pulse width psen pulse delay time low address setup time low address hold time high address setup time t f w t als ns (ta= C30 to +70c) clock (osc) pulse width 50 c l =50pf 2t f w C4 2t f w C10 t f w C6 2t f w C6 t f w C6 4t f w C6 high address hold time 0 instruction setup time instruction hold time 0 max t f w +6 2t f w +6 t f w +6 4t f w +6 t f w +6 t f w C6 t aw t pw t pad t alh t is t ahs t aph t ih 30 clk ale t f w t f w psen t aw t pad t pw ad 0-ad7 pc 0-7 inst 0-7 t als t alh t is t ih a 8-a19 pc 8-19 t ahs t aph
19/24 ? semiconductor msm66585/586/587/p587/q587 ? external data memory control ale pulse width symbol units conditions parameter min rd pulse width wr pulse width rd pulse delay time wr pulse delay time low address setup time t f w t rad ns (ta= C30 to +70c) clock (osc) pulse width 50 c l =50pf 2t f w C4 2t f w C10 2t f w C10 t f w C6 t f w C6 2t f w C6 low address hold time t f w C6 high address setup time 3t f w C6 high address hold time t f w C6 max t f w +6 t f w +6 2t f w +6 t f w +6 3t f w +6 t f w +6 t aw t rw t ww t wad t ahs t als t alh t ahh memory data setup time memory data hold time 0 data delay time t alh C0 data hold time t f w C6 t f w C6 t alh +10 t f w +6 t dd t ms t mh t dh 30 clk ale t f w t f w t aw rd t rad t rw ad 0-ad7 rap 0-7 din 0-7 t als t alh t ms t mh a 8-a19 rap 8-19 t ahs t ahh wr t wad t ww ad 0-ad7 rap 0-7 dout 0-7 t als t alh t dh a 8-a19 rap 8-19 t ahs t ahh t dd
20/24 ? semiconductor msm66585/586/587/p587/q587 ? serial port control master mode serial clock cycle time symbol units conditions parameter min. output data setup time output data hold time input data setup time input data hold time t f w t srmxs ns (ta=C30 to +70c) clock (osc) pulse width 50 c l =50pf 8t f w 4t f w C10 3t f w C20 30 0 typ. t sckc t stmxs t stmxh t srmxh max. t sckc sdout (txd) t stmxh sdin (rxd) t srmxs sck t stmxs t srmxh valid valid
21/24 ? semiconductor msm66585/586/587/p587/q587 slave mode ac timing mesurement point serial clock cycle time symbol units conditions parameter min. output data setup time output data hold time input data setup time input data hold time t f w t srmxs ns (ta= C30 to +70c) clock (osc) pulse width 50 c l =50pf 8t f w 2t f w C30 4t f w C20 30 10 typ. t sckc t stmxs t stmxh t srmxh max. t sckc sdout (txd) t stmxh sdin (rxd) t srmxs sck t stmxs t srmxh valid valid v dd 0v 0.8v dd 0.8v dd 0.2v dd 0.2v dd
22/24 ? semiconductor msm66585/586/587/p587/q587 a/d converter characteristics recommended circuit linearity error symbol units conditions item min differential linearity error zero scale error full scale error conversion time e l e fs lsb (ta=C30 to +70c, v dd =v ref =5v10%, agnd=gnd=0v, f osc =20mhz) resolution refer to the recommended circuit analog input source impedance r i 5k w t conv =19.2 m sec typ max 8 m s/ch bit 6.4 19.2 n e d e zs t conv by adtm set data 2 1 +2 C2 a/d converter characteristics linearity error symbol units conditions item min differential linearity error zero scale error full scale error conversion time e l e fs lsb (ta=C30 to +70c, v dd =v ref =3v10%, agnd=gnd=0v, f osc =10mhz) resolution refer to the recommended circuit analog input source impedance r i 5k w t conv =38.4 m sec typ max 8 m s/ch bit 38.4 n e d e zs t conv adtm=00b (384clk selection) 1 0.5 +1 C1 reference voltage C + analog voltage c i 0.1 m f 47 m f + v ref ai0~ ai3 agnd gnd v dd 0.1 m f 47 m f + +5v 0v r i (analog input source impedance) 5k w c l = 0.1 m f r i 0.1 m f
23/24 ? semiconductor msm66585/586/587/p587/q587 definition of terms ? resolution resolution is the minimum input analog value that can be resolved. with 8 bits, 2 8 =256 so resolution can be to (v ref -agnd) ? 256. ? linearity error linearity error is the difference between actual conversion characteristics and ideal conversion characteristics of an 8-bit a/d converter (so this does not include quantization error). ideal conversion characteristics would be to divide the voltage between v ref and agnd into 256 equal steps. ? differential linearity error differential linearity error indicates slope of conversion characteristics. the change in analog input voltage value that would change the digital output by one bit is ideally 1 lsb = (v ref -agnd) ? 256, so differential linearity error is the difference between this ideal bit size and the actual bit size anywhere in the conversion range. ? zero scale error zero scale error is the difference between actual conversion characteristics and ideal conversion characteristics at the point where digital output switches from 00h to 01h. ? full scale error full scale error is the difference between actual conversion characteristics and ideal conversion characteristics at the point where digital output switches from feh to ffh.
24/24 ? semiconductor msm66585/586/587/p587/q587 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). tqfp100-p-1414-0.50-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.55 typ. mirror finish

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