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rev. pra 8/99 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a preliminary technical data ad73560 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 preliminary technical data six-input channel analog front end features afe performance six 16-bit a/d converters programmable input sample rate simultaneous sampling 76 db snr 64 ks/s maximum sample rate C 83 db crosstalk low group delay (25 ms typ per adc channel) programmable input gain single supply operation on-chip reference dsp performance 19ns instruction cycle time @3.3 v, 52 mips sustained performance single-cycle instruction execution single-cycle context switch 3-bus architecture allows dual operand fetches in every instruction cycle multifunction instructions power-down mode featuring low cmos standby power dissipation with 400 cycle recovery from power-down condition low power dissipation in idle mode flash memory 64kbytes writable in pages of 128 bytes fast page write cycle of 5ms (typical) functional block diagram general description the ad73560 is a six-input channel analog front-end processor for general purpose applications including in- dustrial power metering or multichannel analog inputs. it features six 16-bit a/d conversion channels each of which provide 76 db signal-to-noise ratio over a dc to 4khz signal bandwidth. each channel also features a program- mable input gain amplifier (pga) with gain settings in eight stages from 0 db to 38 db. the ad73560 is particularly suitable for industrial power metering as each channel samples synchronously, ensuring that there is no (phase) delay between the conversions. the ad73560 also features low group delay conversions on all channels. an on-chip reference voltage of 2.5v is included. the sampling rate of the device is programmable with four separate settings offering 64 khz, 32 khz, 16 khz and 8 khz sampling rates (from a master clock of 16.384 mhz) while the serial port (sport2) allows easy expansion of the number of input channels by cascading extra afe external to the ad73560. the ad73560s dsp engine combines the adsp-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal dma port, a byte dma port, a programmable timer, flag i/o, extensive interrupt capabilities and on-chip program and data memory. the ad73560-80 integrates 80k bytes of on-chip memory configured as 16k words (24-bit) of program ram and 16 k (16-bit) of data ram. the ad73560-40 integrates 40k bytes of on-chip memory configured as 8k words (24-bit) of program ram and 8k (16-bit) of data ram. power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. the ad73560 is available in a 119-ball pbga package. serial ports sport 1 sport 0 byte dma controller external data bus external address bus full memory mode memory pr ogrammable i/ o an d flags 16k pm (optional 8k) timer adsp-2100 base architecture shifter mac alu arithmetic units power-down control program sequencer dag 2 dag 1 data address generators program memory address data memory address program memory data data memory data 16k dm (optional 8k) flash byte memory 64 kbytes serial port sport 2 ref adc3 analog front end section adc1 adc2 adc4 adc5 adc6
rev. pra C2C ad73560Cspecifications preliminary technical data (avdd = +3v 10%; dvdd = +3v 10%; dgnd = agnd = 0 v, f mclk = 16.384 mhz, f sclk = 8.192 mhz, f s = 8 khz; t a = t min to t max , unless otherwise noted.) ad73560a parameter min typ max units test conditions/comments reference refcap absolute voltage, v refcap 1.125 1.25 1.375 v refcap tc 50 ppm/c 0.1 f capacitor required from refcap to agnd2 refout typical output impedance 130 v absolute voltage, v refout 1.125 1.25 1.375 v unloaded minimum load resistance 1 k v maximum load capacitance 100 pf adc specifications maximum input range at vin 2, 3 1.578 v p-p 5ven = 0, measured differentially C2.85 dbm nominal reference level at vin 1.0954 v p-p 5ven = 0, measured differentially (0 dbm0) C6.02 dbm absolute gain pga = 0 db C0.8 +0.8 db 1.0 khz pga = 38 db C0.8 +0.8 db 1.0 khz gain tracking error 0.1 db 1.0 khz, +3 dbm0 to C50 dbm0 signal to (noise + distortion) pga = 0 db 73 77 db 0 hz to f s /2; f s = 8 khz pga = 38 db 62 db 0 hz to 4 khz; f s = 64 khz total harmonic distortion pga = 0 db C83 C76 db pga = 38 db C70 db intermodulation distortion C76 db pga = 0 db idle channel noise C70 db pga = 0 db crosstalk adc-to-adc C83 db adc1 input signal level: 1.0 khz adc2 input at idle dc offset C30 +10 +45 mv pga = 0 db power supply rejection C55 db input signal level at avdd and dvdd pins 1.0 khz, 100 mv p-p sine wave group delay 4, 5 25 s 64 khz output sample rate 50 s 32 khz output sample rate 95 s 16 khz output sample rate 190 s 8 khz output sample rate input resistance at vin 2, 4 25 k v 6 dmclk = 16.384 mhz frequency response (adc) 7 typical output frequency (normalized to f s ) 0 0 db 0.03125 C0.1 db 0.0625 C0.25 db 0.125 C0.6 db 0.1875 C1.4 db 0.25 C2.8 db 0.3125 C4.5 db 0.375 C7.0 db 0.4375 C9.5 db > 0.5 < C12.5 db
rev. pra C3C ad73560 preliminary technical data ad73560a parameter min typ max units test conditions/comments logic inputs v inh , input high voltage v dd C 0.8 v dd v v inl , input low voltage 0 0.8 v i ih , input current 10 a c in , input capacitance 10 pf logic output v oh , output high voltage v dd C 0.4 v dd v |iout| - 100 a v ol , output low voltage 0 0.4 v |iout| - 100 a three-state leakage current C10 +10 a power supplies avdd1, avdd2 2.7 3.3 v dvdd 2.7 3.3 v i dd 8 see table i notes 1 operating temperature range is as follows: C40c to +85c. therefore, t min = C40c and t max = +85c. 2 test conditions: input pga set for 0 db gain (unless otherwise noted). 3 at input to sigma-delta modulator of adc. 4 guaranteed by design. 5 overall group delay will be affected by the sample rate and the external digital filtering. 6 the adcs input impedance is inversely proportional to dmclk and is approximated by: (4 x 10 11 )/dmclk. 7 frequency response of adc measured with input at audio reference level (the input level that produces an output level of C10 db m0), with 38 db preamplifier bypassed and input gain of 0 db. 8 test conditions: no load on digital inputs, analog inputs ac coupled to ground. specifications subject to change without notice. table i. afe section current summary (avdd = dvdd = +3.3 v) total analog digital current mclk conditions current current (max) se on comments adcs only on 12 10 26.5 1 yes refout disabled refcap only on 0.75 0.04 1.0 0 n o refout disabled refcap and refout only on 3.3 0.04 4.5 0 n o all sections off 0.01 1.2 1.5 0 yes mclk active levels equal to 0 v and dvdd all sections off 0.01 0.03 0.1 0 n o digital inputs static and equal to 0v or dvdd the above values are in ma and are typical values unless otherwise noted. mclk = 16.384 mhz; sclk = 16.384 mhz.
rev. pra C4C ad73560Cspecifications preliminary technical data parameter test conditions min typ max unit dsp section v ih hi-level input voltage 1, 2 @ v dd = max 2.0 v v ih hi-level clkin voltage @ v dd = max 2.2 v v il lo-level input voltage 1, 3 @ v dd = min 0.8 v v oh hi-level output voltage 1, 4, 5 @ v dd = min i oh = C0.5 ma 2.4 v @ v dd = min i oh = C100 a 6 v dd C0.3 v v ol lo-level output voltage 1, 4, 5 @ v dd = min i ol = 2 ma 0.4 v i ih hi-level input current 3 @ v dd = max v in = v dd max 10 a i il lo-level input current 3 @ v dd = max v in = 0 v 10 a i ozh three-state leakage current 7 @ v dd = max v in = v dd max 8 10 a i ozl three-state leakage current 7 @ v dd = max v in = 0 v 8 10 a i dd supply current (idle) 9 @ v dd = 3.3 t ck = 19 ns 10 10 ma t ck = 25 ns 10 8ma t ck = 30 ns 10 7ma i dd supply current (dynamic) 11 @ v dd = 3.3 t amb = +25c t ck = 19 ns 10 51 ma t ck = 25 ns 10 41 ma t ck = 30 ns 10 34 ma c i input pin capacitance 3, 6, 12 @ v in = 2.5 v f in = 1.0 mhz t amb = +25c 8 pf c o output pin capacitance 6, 7, 12, 13 @ v in = 2.5 v f in = 1.0 mhz t amb = +25c 8 pf notes 1 bidirectional pins: d0Cd23, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, a1Ca13, pf0Cpf7. 2 input only pins: reset, br, dr0, dr1, pwd. 3 input only pins: clkin, reset, br, dr0, dr1, pwd. 4 output pins: bg, pms, dms, bms, ioms, cms, rd, wr, pwdack, a0, dt0, dt1, clkout, fl2C0, bgh. 5 although specified for ttl outputs, all ad73560 outputs are cmos-compatible and will drive to v dd and gnd, assuming no dc loads. 6 guaranteed but not tested. 7 three-statable pins: a0Ca13, d0Cd23, pms, dms, bms, ioms, cms, rd, wr, dt0, dt1, sclk0, sclk1, tfs0, tfs1, rfs0, rfs1, pf0Cpf7. 8 0 v on br. 9 idle refers to ad73560 state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 10 v in = 0 v and 3 v. for typical figures for supply currents, refer to power dissipation section. 11 i dd measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 12 applies to pbga package type. 13 output pin capacitance is the capacitive load for any three-stated output pin. specifications subject to change without notice. (avdd = dvdd = +3.0v to 3.6v; dgnd = agnd = 0 v, f mclk = 16.384 mhz, f samp = 64 khz; t a = t min to t max , unless otherwise noted)
rev. pra preliminary technical data ad73560 C5C preliminary technical data timing characteristics - afe section 1 limit at parameter t a = C40 8 8 8 8 8 c to +85 8 8 8 8 8 c units description clock signals see figure 1 t 1 61 ns min amclk period t 2 24.4 ns min amclk width high t 3 24.4 ns min amclk width low serial port see figures 3 and 4 t 4 t 1 ns min sclk period (sclk=amclk) t 5 0.4 x t 1 ns min sclk width high t 6 0.4 x t 1 ns min sclk width low t 7 20 ns min sdi/sdifs setup before sclk low t 8 0 ns min sdi/sdifs hold after sclk low t 9 10 ns max sdofs delay from sclk high t 10 10 ns min sdofs hold after sclk high t 11 10 ns min sdo hold after sclk high t 12 10 ns max sdo delay from sclk high t 13 30 ns max sclk delay from amclk (avdd = +3 v 6 6 6 6 6 10%; dvdd = +3 v 6 6 6 6 6 10%; agnd = dgnd = 0v; t a = t mln to t max , unless otherwise noted) notes 1 for details of the dsp section timing, please refer to the adsp-2185l data sheet and the adsp-2100 family users manual, third edition . specifications subject to change without notice. absolute maximum ratings* (t a = +25c unless otherwise noted) avdd, dvdd to gnd . . . . . . . . . . . C0.3 v to +4.6 v agnd to dgnd . . . . . . . . . . . . . . . . . C0.3 v to +0.3 v digital i/o voltage to dgnd. C0.3 v to dvdd + 0.3 v analog i/o voltage to agnd C0.3 v to avdd + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . C20c to +85c storage temperature range . . . . . . . . C40c to +125c maximum junction temperature . . . . . . . . . . . . +150c pbga, q ja thermal impedance . . . . . . . . . . . . . . 25c/w caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad73560 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functional- ity. warning! esd sensitive device reflow soldering maximum temperature . . . . . . . . . . . . . . . . . . +225c time at maximum temperature . . . . . . . . . . . . 15 sec *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide temperature package package model range description options ad73560bb-80 C20c to +85c 119-ball plastic grid array b-119 ad73560bb-40 C20c to +85c 119-ball plastic grid array b-119
rev. pra ad73560 C6C preliminary technical data a b c d e f g h j k l m n p r t u a b c d e f g h j k l m n p r t u 1234567 1234567 pbga ball configurations pbga ball pbga ball pbga ball pbga ball number name number name number name number name a1 irqe /pf4 e3 rfs0 j5 d22 n7 d13 a2 dms e4 a3/iad2 j6 d21 p1 ebr a3 vdd(int) e5 a2/iad1 j7 d20 p2 d0/iad13 a4 clkin e6 a1/iad0 k1 elout p3 dvdd a5 a11/iad10 e7 a0 k2 elin p4 dgnd a6 a7/iad6 f1 dr0 k3 eint p5 areset a7 a4/iad3 f2 sclk0 k4 d19 p6 sclk2 b1 irql0 /pf5 f3 dt1 k5 d18 p7 mclk b2 pms f4 pwdack k6 d17 r1 sdo b3 wr f5 bgh k7 d16 r2 sdofs b4 xtal f6 pf0[mode a] l1 bg r3 sdifs b5 a12/iad11 f7 pf1[mode b] l2 d3/ iack r4 sdi b6 a8/iad7 g1 tfs1 l3 d5/ial r5 se b7 a5/iad4 g2 rfs1 l4 d8 r6 refcap c1 irql1 /pf6 g3 dr1 l5 d9 r7 refout c2 ioms g4 gnd l6 d12 t1 vinn2 c3 rd g5 pwd l7 d15 t2 vinp2 c4 vdd(ext) g6 vdd(ext) m1 ebg t3 vinn1 c5 a13/iad12 g7 pf2[mode c] m2 d2/iad15 t4 vinp1 c6 a9/iad8 h1 sclk1 m3 d4/ is t5 vinn3 c7 gnd h2 ereset m4 d7/ iwr t6 vinp3 d1 irq2 /pf7 h3 reset m5 vdd(ext) t7 vinn4 d2 cms h4 pf3 m6 d11 u1 agnd d3 bms h5 fl0 m7 d14 u2 avdd d4 clkout h6 fl1 n1 br u3 vinp6 d5 gnd h7 fl2 n2 d1/iad14 u4 vinn6 d6 a10/iad9 j1 ems n3 vdd(int) u5 vinp5 d7 a6/iad5 j2 ee n4 d6/ ird u6 vinn5 e1 dt0 j3 eclk n5 gnd u7 vinp4 e2 tfs0 j4 d23 n6 d10
rev. pra preliminary technical data ad73560 C7C preliminary technical data pin function description mnemonic function vinp1 analog input to the positive terminal of input channel 1. vinn1 analog input to the negative terminal of input channel 1. vinp2 analog input to the positive terminal of input channel 2. vinn2 analog input to the negative terminal of input channel 2. vinp3 analog input to the positive terminal of input channel 3. vinn3 analog input to the negative terminal of input channel 3. vinp4 analog input to the positive terminal of input channel 4. vinn4 analog input to the negative terminal of input channel 4. vinp5 analog input to the positive terminal of input channel 5. vinn5 analog input to the negative terminal of input channel 5. vinp6 analog input to the positive terminal of input channel 6. vinn6 analog input to the negative terminal of input channel 6. refout buffered reference output, which has a nominal value of 1.25 v. this pin can be overdriven by an external reference if required. refcap a bypass capacitor to agnd2 of 0.1 f is required for the on-chip reference. the capacitor should be fixed to this pin. avdd analog power supply connection. agnd analog ground/substrate connection. dgnd digital ground/substrate connection. dvdd digital power supply connection. areset active low reset signal. this input resets the entire chip, resetting the control registers and clearing the digital circuitry. sclk2 output serial clock whose rate determines the serial transfer rate to/from the afe0. it is used to clock data or control information to and from the serial port (sport2). the frequency of sclk is equal to the frequency of the master clock (mclk) divided by an integer numberthis integer number being the product of the external master clock rate divider and the serial clock rate divider. mclk master clock input. mclk is driven from an external clock signal. sdo serial data output of the ad73560. both data and control information may be output on this pin and are clocked on the positive edge of sclk. sdo is in three-state when no information is being transmitted and when se is low. sdofs framing signal output for sdo serial transfers. the frame sync is one bit wide and it is active one sclk period before the first bit (msb) of each output word. sdofs is referenced to the positive edge of sclk. sdofs is in three-state when se is low. sdifs framing signal input for sdi serial transfers. the frame sync is one bit wide and it is valid one sclk period before the first bit (msb) of each input word. sdifs is sampled on the negative edge of sclk and is ignored when se is low. sdi serial data input of the ad73560. both data and control information may be input on this pin and are clocked on the negative edge of sclk. sdi is ignored when se is low. se sport enable. asynchronous input enable pin for the sport. when se is set low by the dsp, the output pins of the sport are three-stated and the input pins are ignored. sclk is also disabled internally in order to decrease power dissipation. when se is brought high, the control and data registers of the sport are at their original values (before se was brought low); however, the timing counters and other internal registers are at their reset values. reset (input) processor reset input br (input) bus request input bg (output) bus grant output bgh (output) bus grant hung output dms (output) data memory select output pms (output) program memory select output ioms (outp ut) memory select output bms (output) byte memory select output cms (output) combined memory select output rd (output) memory read enable output wr (output) memory write enable output irq2/ (input) edge- or level-sensitive interrupt pf7 (input/output) request. 1 programmable i/o pin
rev. pra ad73560 C8C preliminary technical data pin function description mnemonic function irql0/ (input) level-sensitive interrupt requests 1 pf6 (input/output) programmable i/o pin irql1/ (input) level-sensitive interrupt requests 1 pf5 (input/output) programmable i/o pin irqe/ (input) edge-sensitive interrupt requests 1 pf4 (input/output) programmable i/o pin mode d/ (input) mode select inputchecked only during reset pf3 (input/output) programmable i/o pin during normal operation mode c/ (input) mode select inputchecked only during reset pf2 (input/output) programmable i/o pin during normal operation mode b/ (input) mode select inputchecked only during reset pf1 (input/output) programmable i/o pin during normal operation mode a/ (input) mode select inputchecked only during reset pf0 (input/output) programmable i/o pin during normal operation clkin, xtal (inputs) clock or quartz crystal input clkout (output) processor clock output sport0 (inputs/outputs) serial port i/o pins sport1 (inputs/outputs) serial port i/o pins irq1:0 (inputs) edge- or level-sensitive interrupts, fi (input) flag in 2 fo (output) flag out 2 pwd (input) power-down control input pwdack (output) power-down control output fl0, fl1, fl2 (outputs) output flags vdd and gnd power and ground ez-iceport (i nputs/outputs) for emulation use ereset ems ee eclk elout elin eint ebr ebg notes 1 interrupt/flag pins retain both functions concurrently. if imask is set to enable the corresponding interrupts, then the dsp wi ll vector to the appropriate inter- rupt vector address when the pin is asserted, either by external de4vices, or set as a programmable flag. 2 sport configuration determined by the dsp system control register. software configurable.
rev. pra preliminary technical data ad73560 C9C preliminary technical data architecture overview the ad73560 instruction set provides flexible data moves and multifunction (one or two data moves with a computaion) instructions. every instructions can be ex- ecuted in a single processor cycle. the ad73560 assem- bly language uses an algebraic syntax for ease of coding and readability. a comprehensive set of development tools supports program development. serial ports sport 1 sport 0 byte dma controller external data bus external address bus full memory mode memory pr og ra mm ab le i/o and flags 16k p m (optional 8k) timer adsp-2100 base architecture shifter mac alu arithmetic units power-down control program sequencer dag 2 dag 1 data address generators program memory address data memory address program memory data data memory data 16k d m (optional 8k) flash byte memory 64 kbytes serial port sport 2 ref adc3 analog front end section adc1 adc2 adc4 adc5 adc6 figure 1. functional block diagram figure 1 is an overall block diagram of the ad73560. the processor section contains three independent compu- tational units: the alu, the multiplier/accumulator (mac) and the shifter. the computational units process 16 bit data directly and have provisions to support multiprecision computations. the alu performs a stan- dard set of arithmetic and logic operations; division primitives are also supported. the mac performs single- cycle multiply, multiply/add and multiply/subtract opera- tions with 40 bits of accumulation. the shifter performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations. the internal result (r) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. the sequencer supports condi- tional jumps, subroutine calls and returns in a single cycle. with internal loop counters and loop stacks, the ad73560 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. two data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and program memory). each dag maintains and updates four address pointers. whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possible modify registers. a length value may be associated with each pointer to imple- ment automatic modulo addressing for circular buffers. the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (pmd and dmd) share a single external data bus. byte memory space and i/o memory space also share the external buses. an interface to low cost byte-wide memory is provided by the byte dma port (bdma port). the bdma port is bi- directional and can directly address up to four megabytes of external ram or rom for off-chip storage of program overlays or data tables. the ad73560 can respond to eleven interrupts. there can be up to six external interrupts (one edge-sensitive, two level-sensitive and three configurable) and seven in- ternal interrupts generated by the timer, the serial ports (sports), the byte dma port and the power-down cir- cuitry. there is also a master reset signal. the two serial ports provide a complete synchronous serial inter- face with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. each port can generate an internal programmable serial clock or accept an external serial clock. the ad73560 provides up to 13 general-purpose flag pins. the data input and output pins on sport1 can be alternatively configured as an input flag and an output flag. in addition, there are eight flags that are program- mable as inputs or outputs and three flags that are always outputs. a programmable interval timer generates periodic inter- rupts. a 16-bit count register (tcount) is decremented every n processor cycle, where n is a scaling value stored in an 8-bit register (tscale). when the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod). analog front end the analog front end of the ad73560 is configured as a separate block that is normally connected to either sport0 or sport1 of the dsp section. as it is not hardwired to either sport the user has total flexibility in how they wish to allocate system resources to support the afe. it is also possible to further expand the number of analog input channels connected to the sport by cascading single ad73360 devices external to the ad73560. the afe is configured as six input channels. it comprises six independent encoder channels each featuring signal conditioning, programmable gain amplifier, sigma-delta a/d convertor and decimator sections. each of these sections is described in further detail below.all channels share a common internal reference whose nominal value is 1.25v. figure 2 shows a block diagram of the afe sec- tion of the ad73560. it shows six input channels along with a common reference. communication to all channels is handled by the sport2 block which interfaces to either sport0 or sport1 of the dsp section.
rev. pra ad73560 C10C preliminary technical data functional dsecription - afe encoder channel each encoder channel consists of a signal conditioner, a switched capacitor pga and a sigma-delta analog-to- digital converter (adc). an on-board digital filter, which forms part of the sigma-delta adc, also performs critical system-level filtering. due to the high level of oversampling, the input antialias requirements are reduced such that a simple single pole rc stage is sufficient to give adequate attenuation in the band of interest. signal conditioner each analog channel has an independent signal condition- ing block. this allows the analog input to be configured by the user depending on whether differential or single- ended mode is used. programmable gain amplifier each encoder sections analog front end comprises a switched capacitor pga that also forms part of the sigma- delta modulator. the sc sampling frequency is dmclk/ 8. the pga, whose programmable gain settings are shown in table ii, may be used to increase the signal level applied to the adc from low output sources such as microphones, and can be used to avoid placing external amplifiers in the circuit. the input signal level to the sigma-delta modulator should not exceed the maximum input voltage permitted. the pga gain is set by bits igs0, igs1 and igs2 in control registers d, e and f. table ii. pga settings for the encoder channel ixgs2 ixgs1 ixgs0 gain (db) 000 0 001 6 010 12 011 18 100 20 101 26 110 32 111 38 adc each channel has its own adc consisting of an analog sigma-delta modulator and a digital antialiasing decima- tion filter. the sigma-delta modulator noise-shapes the signal and produces 1- bit samples at a dmclk/8 rate. this bitstream, representing the analog input signal, is input to the antialiasing decimation filter. the decimation filter reduces the sample rate and increases the resolution. vinn1 vinp1 analog s - d modulator sdi sdifs sclk2 refcap refout se areset sdofs sdo amclk vinn2 vinp2 vinn3 vinp3 vinn4 vinp4 vinn5 vinp5 vinn6 vinp6 ad73360 signal conditioning 0/38db pga decimator serial i/o port analog s - d modulator signal conditioning 0/38db pga decimator analog s - d modulator signal conditioning 0/38db pga decimator analog s - d modulator signal conditioning 0/38db pga decimator analog s - d modulator signal conditioning 0/38db pga decimator analog s - d modulator signal conditioning 0/38db pga decimator reference figure 2. function block diagram of analog front end
rev. pra preliminary technical data ad73560 C11C preliminary technical data analog sigma-delta modulator the ad73560 input channels employ a sigma-delta conver- sion technique, which provides a high resolution 16-bit out- put with system filtering being implemented on-chip. sigma-delta converters employ a technique known as oversampling, where the sampling rate is many times the highest frequency of interest. in the case of the ad73560, the initial sampling rate of the sigma-delta modulator is dmclk/8. the main effect of oversampling is that the quantization noise is spread over a very wide bandwidth, up to f s /2 = dmclk/16 (figure 3a). this means that the noise in the band of interest is much reduced. another complementary feature of sigma-delta converters is the use of a technique called noise-shaping. this technique has the effect of pushing the noise from the band of interest to an out-of-band position (figure 3b). the combination of these techniques, followed by the application of a digital filter, reduces the noise in band sufficiently to ensure good dynamic performance from the part (figure 3c). band of interest f s /2 dmclk/16 f s /2 dmclk/16 f s /2 dmclk/16 digital filter noise-shaping band of interest band of interest a. b. c. figure 3. sigma-delta noise reduction figure 4 shows the various stages of filtering that are em- ployed in a typical ad73560 application. in figure 4a we see the transfer function of the external analog antialias filter. even though it is a single rc pole, its cutoff fre- quency is sufficiently far away from the initial sampling frequency (dmclk/8) that it takes care of any signals that could be aliased by the sampling frequency. this also shows the major difference between the initial oversampling rate and the bandwidth of interest. in figure 4b, the signal and noise-shaping responses of the sigma- delta modulator are shown. the signal response provides further rejection of any high frequency signals while the noise-shaping will push the inherent quantization noise to an out-of-band position. the detail of figure 4c shows the response of the digital decimation filter (sinc-cubed response) with nulls every multiple of dm clk/256, which is the decimation filter update rate. the final detail in figure 4d shows the application of a final antialias filter in the dsp engine. this has the advantage of being imple- mented according to the users requirements and avail- able mips. the filtering in figures 4a through 4c is implemented in the ad73 560. f b = 4khz f sinit = dmclk/8 a. analog antialias filter transfer function f b = 4khz f sinit = dmclk/8 noise transfer function signal transfer function b. analog sigma-delta modulator transfer function f b = 4khz f sinter = dmclk/256 c. digital decimator transfer function f b = 4khz f sinter = dmclk/256 f sfinal = 8khz d. final filter lpf (hpf) transfer function figure 4. dc frequency responses decimation filter the digital filter used in the ad73560 carries out two important f unctions. firstly, it removes the out-of-band quantization noise, which is shaped by the analog modula- tor and secondly, it decimates the high frequency bitstream to a lower rate 15-bit word.
rev. pra ad73560 C12C preliminary technical data the antialiasing decimation filter is a sinc-cubed digital filter that reduces the sampling rate from dmclk/8 to dmclk/256, and increases the resolution from a single bit to 15 bits. its z transform is given as: [(1Cz C32 )/(1Cz C 1 )] 3 . this ensures a minimal group delay of 25 s. adc coding the adc coding scheme is in twos complement format (see figure 8). the output words are formed by the decimation filter, which grows the word length from the single-bit output of the sigma-delta modulator to a 15-bit word, which is the final output of the adc block. in 16-bit data mode this value is left shifted with the lsb being set to 0. for input values equal to or greater than positive full scale, however, the output word is set at 0x7fff, which has the lsb set to 1. in mixed control/data mode, the resolution is fixed at 15 bits, with the msb of the 16-bit transfer being used as a flag bit to indicate either control or data in the frame. v ref + (v ref 3 0.32875) v ref v ref - (v ref 3 0.32875) 10...00 00...00 01...11 adc code differential analog input v inn v inp v ref + (v ref 3 0.6575) v ref - (v ref 3 0.6575) 10...00 00...00 01...11 adc code single-ended analog input v inp v inn figure 5. adc transfer function voltage reference the ad73560 reference, refcap, is a bandgap refer- ence that provides a low noise, temperature-compensated reference to the adc. a buffered version of the reference is also made available on the refout pin and can be used to bias other external analog circuitry. the reference has a nominal value of 1.25 v. the reference output (refout) can be enabled for bias- ing external circuitry by setting the ru bit (crc:6) of crc. afe serial port (sport2) the afe section communicate with dsp via the bi-direc- tional synchronous serial port (sport2) which interfaces to either sport0 or sport1 of the dsp section. sport2 is used to transmit and receive digital data and control information. additional external afes can be cascaded to the internal afe (up to a limit of 7) to provide additional input channels if required. in both transmit and receive modes, data is transferred at the serial clock (sclk2) rate with the msb being trans- ferred first. communication between the afe section and dsp section must always be initiated by the ade section (afe is in master mode, dsp is in slave mode). this ensures that there is no collision between input data and output samples. sport2 overview sport2 is a flexible, full-duplex, synchronous serial port whose protocol has been designed to allow addition afes (up to a limit of 7 external devices) to be connected in cas- cade to the dsp section. it has a very flexible architecture that can be configured by programming two of the internal control registers in each afe block. sport2 has three dis- tinct modes of operation: control mode, data mode and mixed control/data mode. note: as each afe has its own sport section, the register settings in each must be programmed. the regis- ters which control sport and sample rate operation (cra and crb) must be programmed with the same val- ues, otherwise incorrect operation may occur. in control mode (cra:0 = 0), the devices internal con- figuration can be programmed by writing to the eight internal control registers. in this mode, control informa- tion can be written to or read from the afe. in data mode (cra:0 = 1), any information that is sent to the afe is ignored, while the encoder section (adc) data is read from the device. in this mode, only adc data is read from the device. mixed mode (cra:0 = 1 and cra:1 = 1) allows the user to send control information and receive either control information or adc data. this is achieved by using the msb of the 16-bit frame as a flag bit. mixed mode reduces the resolution to 15 bits with the msb be- ing used to indicate whether the information in the 16-bit frame is control information or adc data. sport2 features a single 16-bit serial register that is used for both input and output data transfers. as the input and output data must share the same register there are some precautions that must be observed. the primary precaution is that no information must be written to sport2 without reference to an output sample event, which is when the serial register will be overwritten with the latest adc sample word. once sport2 starts to output the latest adc word, it is safe for the dsp to write new control words to the afe. in certain configurations, data can be written to the device to coincide with the out- put sample being shifted out of the serial registersee section on interfacing devices. the serial clock rate (crb:2C3) defines how many 16-bit words can be written to a device before the next output sample event will hap- pen. the sport2 block diagram, shown in figure 9, details the blocks associated with afe including the eight control registers (aCh), external amclk to internal dmclk divider and serial clock divider. the divider rates are controlled by the setting of control register b. the afe features a master clock divider that allows users the flex- ibility of dividing externally available high frequency dsp clocks to generate a lower frequency master clock inter- nally in the afe which may be more suitable for either
rev. pra preliminary technical data ad73560 C13C preliminary technical data serial transfer or sampling rate requirements. the master clock divider has five divider options (1 default condi- tion, 2, 3, 4, 5) that are set by loading the master clock divider field in register b with the appropriate code (see table vi). once the internal device master clock (dmclk) has been set using the master clock divider, the sample rate and serial clock settings are derived from dmclk. mclk divider amclk (external) se areset sdifs sdi serial port (sport) serial register sclk2 control register b control register c control register d control register e control register a 3 8 8 8 8 8 8 2 dmclk (internal) sdofs sdo control register f control register g control register h sclk divider figure 6. sport block diagram sport2 can work at four different serial clock (sclk) rates: chosen from dmclk, dmclk/2, dmclk/4 or dmclk/8, where dmclk is the internal or device mas- ter clock resulting from the external or pin master clock being divided by the master clock divider. care should be taken when selecting master clock, serial clock and sample rate divider settings to ensure that there is suffi- cient time to read all the data from the afe before the next sample interval. sport register maps there are eight control registers for the afe, each eight bits wide. table v shows the control register map for the afe. the first two control registers, cra and crb, are reserved for controlling sport2. they hold settings for parameters such as bit rate, internal master clock rate and device count. if multiple afes are cas- caded, registers cra and crb on each device must be programmed with the same setting to ensure correct op- eration. the other six registers; crc through crh are used to hold control settings for the reference, power control, adc channel and pga sections of the device. it is not necessary that the contents of crc through crh on each afe are similar. control registers are written to on the negative edge of sclk2. master clock divider the afe features a programmable master clock divider that allows the user to reduce an externally available mas- ter clock, at pin mclk, by one of the ratios 1, 2, 3, 4 or 5 to produce an internal master clock signal (dmclk) that is used to calculate the sampling and serial clock rates. the master clock divider is programmable by set- ting crb:4-6. table iii shows the division ratio corre- sponding to the various bit settings. the default divider ratio is divide-by-one. table iii. dmclk (internal) rate divider settings mcd2 mcd1 mcd0 dmclk rate 0 0 0 amclk 0 0 1 amclk/2 0 1 0 amclk/3 0 1 1 amclk/4 1 0 0 amclk/5 1 0 1 amclk 1 1 0 amclk 1 1 1 amclk serial clock rate divider the afe features a programmable serial clock divider that allows users to match the serial clock (sclk2) rate of the data to that of the dsp. the maximum sclk2 rate available is dmclk and the other available rates are: dmclk/2, dmclk/4 and dmclk/8. the slowest rate (d mclk/8) is the default sclk2 rate. the serial clock divider is programmable by setting bits crb:2C3. table iv shows the serial clock rate corresponding to the various bit set- tings. table iv. sclk rate divider settings scd1 scd0 sclk2 rate 0 0 dmclk/8 0 1 dmclk/4 1 0 dmclk/2 1 1 dmclk decimation rate divider the afe features a programmable decimation rate divider that allows users flexibility in matching the afes adc sample rates to the needs of the dsp software. the maximum sample rate available is dmclk/256 and the other avail- able rates are: dmclk/512, dmclk/1024 and dmclk/2048. the slowest rate (dmclk/2048) is the default sample rate. the sample rate divider is program- mable by setting bits crb:0-1. table v shows the sample rate corresponding to the various bit settings. table v. decimation rate divider settings dr1 dr0 sclk2 rate 0 0 dmclk/2048 0 1 dmclk/1024 1 0 dmclk/512 1 1 dmclk/256
rev. pra ad73560 C14C preliminary technical data table vii. control word description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 c/ d r/ w device addresss register address register data table vi. control register map address (binary) name description type width reset setting (hex) 000 cra control register a r / w 8 0x00 001 crb control register b r/ w 8 0x00 010 crc control register c r/ w 8 0x00 011 crd control register d r/ w 8 0x00 100 cre control register e r/ w 8 0x00 101 crf control register f r/ w 8 0x00 110 crg control register g r/ w 8 0x00 111 crh control register h r/ w 8 0x00 control frame description bit 15 control/ data when set high, it signifies a control word in program or mixed program/data modes. when set low, it signifies an invalid control word in program mode. bit 14 read/ write when set low, it tells the device that the data field is to be written to the register se- lected by the register field setting provided the address field is zero. when set high, it tells the device that the selected register is to be written to the data field in the serial register and that the new control word is to be output from the device via the serial output. bits 13C11 device address this 3-bit field holds the address information. only when this field is zero is a device selected. if the address is not zero, it is decremented and the control word is passed out of the device via the serial output. bits 10C8 register address this 3-bit field is used to select one of the eight control registers on the ad73560. bits 7C0 register data this 8-bit field holds the data that is to be written to or read from the selected register provided the address field is zero. table viii. control register a description 7 654321 0 reset dc2 dc1 dc0 slb C mm data/ pgm bit name description 0 data/ pgm operating mode (0 = program; 1 = data mode) 1 m m mixed mode (0 = off; 1 = enabled) 2 reserved must be programmed to zero (0) 3 s l b sport loop-back mode (0 = off; 1 = enabled) 4 dc0 device count (bit 0) 5 dc1 device count (bit 1) 6 dc2 device count (bit 2) 7 reset software reset (0 = off; 1 = initiates reset) control register a
rev. pra preliminary technical data ad73560 C15C preliminary technical data table ix. control register b description 76543210 cee mcd2 mcd1 mcd0 scd1 scd0 dr1 dr0 bit name description 0 dr0 decimation rate (bit 0) 1 dr1 decimation rate (bit 1) 2 scd0 serial clock divider (bit 0) 3 scd1 serial clock divider (bit 1) 4 mcd0 master clock divider (bit 0) 5 mcd1 master clock divider (bit 1) 6 mcd2 master clock divider (bit 2) 7 c e e control echo enable (0 = off; 1 = enabled) table x. control register c description 76543210 CrupurefCCCCgpu bit name description 0 g p u global power-up device (0 = power down; 1 = power up) 1 reserved must be programmed to zero (0) 2 reserved must be programmed to zero (0) 3 reserved must be programmed to zero (0) 4 reserved must be programmed to zero (0) 5 puref ref power (0 = power down; 1 = power up) 6 r u refout use (0 = disable refout; 1 = enable refout) 7 reserved must be programmed to zero (0) table xi. control register d description 76543210 pui2 i2gs2 i2gs1 i2gs0 pui1 i1gs2 i1gs1 i1gs0 bit name description 0 i1gs0 adc1:input gain select (bit 0) 1 i1gs1 adc1:input gain select (bit 1) 2 i1gs2 adc1:input gain select (bit 2) 3 pui1 power control (adc1); 1 = on, 0 = off 4 i2gs0 adc2:input gain select (bit 0) 5 i2gs1 adc2:input gain select (bit 1) 6 i2gs2 adc2:input gain select (bit 2) 7 pui2 power control (adc2); 1 = on, 0 = off control register b control register c control register d
rev. pra ad73560 C16C preliminary technical data table xiii. control register e description 76543210 pui4 i4gs2 i4gs1 i4gs0 pui3 i3gs2 i3gs1 i3gs0 bit name description 0 i3gs0 adc3:input gain select (bit 0) 1 i3gs1 adc3:input gain select (bit 1) 2 i3gs2 adc3:input gain select (bit 2) 3 pui3 power control (adc3); 1 = on, 0 = off 4 i4gs0 adc4:input gain select (bit 0) 5 i4gs1 adc4:input gain select (bit 1) 6 i4gs2 adc4:input gain select (bit 2) 7 pui4 power control (adc4); 1 = on, 0 = off table xiv. control register f description 76543210 pui6 i6gs2 i6gs1 i6gs0 pui5 i5gs2 i5gs1 i5gs0 bit name description 0 i5gs0 adc5:input gain select (bit 0) 1 i5gs1 adc5:input gain select (bit 1) 2 i5gs2 adc5:input gain select (bit 2) 3 pui5 power control (adc5); 1 = on, 0 = off 4 i6gs0 adc6:input gain select (bit 0) 5 i6gs1 adc6:input gain select (bit 1) 6 i6gs2 adc6:input gain select (bit 2) 7 pui6 power control (adc6); 1 = on, 0 = off table xv. control register g description 76543210 seen rmod ch6 ch5 ch4 ch3 ch2 ch1 bit name description 0 ch1 channel 1 select 1 ch2 channel 2 select 2 ch3 channel 3 select 3 ch4 channel 4 select 4 ch5 channel 5 select 5 ch6 channel 6 select 6 rmod reset analog modulator 7 seen enable single-ended input mode control register e control register f control register g
rev. pra preliminary technical data ad73560 C17C preliminary technical data table xvi. control register h description 76543210 inv tme ch6 ch5 ch4 ch3 ch2 ch1 bit name description 0 ch1 channel 1 select 1 ch2 channel 2 select 2 ch3 channel 3 select 3 ch4 channel 4 select 4 ch5 channel 5 select 5 ch6 channel 6 select 6 t m e test mode enable 7 inv enable invert channel mode control register h operation resetting the afe the areset pin resets all the control registers. all the afe registers are reset to zero indicating that the default sclk2 rate (dmclk/8) and sample rate (dmclk/ 2048) are at a minimum. as well as resetting the control registers of the afe using the areset pin, the device can be reset using the reset bit (cra:7) in control register a. both hardware and software resets require four dmclk cycles. on reset, data/ pgm (cra:0) is set to 0 (default condition) thus enabling control mode. the reset conditions ensure that the device must be pro- grammed to the correct settings after power-up or reset. following a reset, the sdofs will be asserted approxi- mately 2070 master (amclk) cycles after areset goes high. the data that is output following the reset and dur- ing control mode is random and contains no valid infor- mation until either data or mixed mode is set. power management the individual functional blocks of the afe can be en- abled separately by programming the power control regis- ter crc (the power management functions of the dsp section are seperate and will be referred to later). it allows certain sections to be powered down if not required, which adds to the devices flexibility in that the user need not incur the penalty of having to provide power for a certain section if it is not necessary to their design. the power control registers provide individual control settings for the major functional blocks on each analog front end unit and also a global override that allows all sections to be pow- ered up/down by setting/clearing the bit. using this method the user could, for example, individually enable a certain section, such as the reference (crc:5), and disable all others. the global power-up (crc:0) can be used to enable all sections but if power-down is required using the global control, the reference will still be enabled; in this case, because its individual bit is set. refer to table x for details of the settings of crc. crdCcrf can be used to control the power status of individual channels allowing multiple channels to be powered down if required. operating modes there are three operating modes available on the afe. they are control (program), data and mixed control/ data. the device configurationregister settingscan be changed only in program and mixed program/data modes. in all modes, transfers of information to or from the device occur in 16-bit packets, therefore the dsp engines sport will be programmed for 16-bit transfers. control mode in control mode, cra:0 = 0, the user writes to the con- trol registers to set up the device for desired operation sport2 operation, cascade length, power management, input/output gain, etc. in this mode, the 16-bit informa- tion packet sent to the device by the dsp is interpreted as a control word whose format is shown in table vii. in this mode, the user must address the device to be pro- grammed using the address field of the control word. this field is read by the device and if it is zero (000 bin), the device recognizes the word as being addressed to it. if the address field is not zero, it is then decremented and the control word is passed out of the deviceeither to the next device in a cascade or back to the dsp. this 3-bit address format allows the user to uniquely address any one of up to eight devices in a cascade. if the afe is used in a stand-alone configuration connected to the dsp, the de- vice address corresponds to 0. following reset, when the se pin is enabled, the afe responds by raising the sdofs pin to indicate that an output sample event has occurred. control words can be written to the device to coincide with the data being sent out of sport2, as shown in f igure 12 (directly coupled), or they can lag the output words by a time interval that should not exceed the sample interval (indirectly
rev. pra ad73560 C18C preliminary technical data coupled). refer to the digital interface section for more information. after reset, output frame sync pulses will occur at a slower default sample rate, which is dmclk/ 2048, until control register b is programmed, after which the sdofs will be pulsed at the selected rate. while the afe is in control mode, the data output by the device is random and should not be interpreted as adc data. data mode once the device has been configured by programming the correct settings to the various control registers, the device may exit program mode and enter data mode. this is done by programming the data/ pgm (cra:0) bit to a 1 and mm (cra:1) to 0. once the device is in data mode, the input data is ignored. when the device is in normal data mode (i.e., mixed mode disabled), it must receive a hardware reset to reprogram any of the control register settings. mixed program/data mode this mode allows the user to send control words to the device while receiving adc words. this permits adaptive control of the device whereby control of the input gains can be affected by reprogramming the control registers. the standard data frame remains 16 bits, but now the msb is used as a flag bit to indicate that the remaining 15 bits of the frame represents control information. mixed mode is enabled by setting the mm bit (cra:1) to 1 and the data/ pgm bit (cra:0) to 1. in the case where con- trol setting changes will be required during normal opera- tion, this mode allows the ability to load control information with the slight inconvenience of formatting the data. note that the output samples from the adc will also have the msb set to zero to indicate it is a data word. interfacing the afe section sport (sport2) can be interfaces to either sport0 or sport1 of the dsp section.. both serial input and output data use an accompanying frame synchronization signal which is active high one clock cycle before the start of the 16-bit word or during the last bit of the previous word if transmission is continuous. the serial clock (sclk) is an output from the afe and is used to define the serial transfer rate to the dsps tx and rx ports. two primary configurations can be used: the first is shown in figure 7 where the dsps tx data, tx frame sync, rx data and rx frame sync are connected to the ad73560s sdi, sdifs, sdo and sdofs respectively. this configuration, referred to as indirectly coupled or nonframe sync loop-back, has the effect of decoupling the transmission of input data from the receipt of output data. when programming the dsp serial port for this configu- ration, it is necessary to set the rx frame sync as an input to the dsp and the tx frame sync as an output generated by the dsp. this configuration is most useful when oper- ating in mixed mode, as the dsp has the ability to decide how many words can be sent to the afe(s). this means that full control can be implemented over the device con- figuration in a given s ample interval. the second configu- ration (shown in figure 8) has the dsps tx data and rx data connected to the afes sdi and sdo, respectively, while the dsps tx and rx frame syncs are connected to the ad73560s sdifs and sdofs. in this configura- tion, referred to as directly coupled or frame sync loop- back, the frame sync signals are connected together and the input data to the afe is forced to be synchronous with the output data from the afe. the dsp must be pro- grammed so that both the tx and rx frame syncs are in- puts as the afes sdofs will be input to both. this configuration guarantees that input and output events oc- cur simulta neously and is the simplest configuration for operation in normal d ata mode. note that when pro- gramming the dsp in this configuration it is advisable to preload the tx register with the first control word to be sent before the afe is taken out of reset. this ensures that this word will be transmitted to coincide with the first output word from the device(s). tfs(0/1) dt(0/1) sclk(0/1) dr(0/1) rfs(0/1) dsp section afe section sdifs sdi sclk sdo sdofs figure 7. indirectly coupled or nonframe sync loop-back configuration tfs(0/1) dt(0/1) sclk(0/1) dr(0/1) rfs(0/1) dsp section afe section sdifs sdi sclk sdo sdofs figure 8. directly coupled or frame sync loop- back configuration cascade operation the ad73560 has been designed to support cascading of external afes from either sport0 or sport1. the sport2 interface protocol has been designed so that device addressing is built into the packet of information sent to the device. this allows the cascade to be formed with no extra hardware overhead for control signals or addressing. a cascade can be formed in either of the two modes previously discussed.
rev. pra preliminary technical data ad73560 C19C preliminary technical data there may be some restrictions in cascade operation due to the number of devices configured in the cascade and the serial clock rate chosen. the formula below gives an indi- cation of whether the combination of sample rate, serial clock and number of devices can be successfully cascaded. this assumes a directly coupled frame sync arrangement as shown in figure 8 and does not take any interrupt la- tency into account. 1 f s 3 6 [(( devicecount - 1) 16 ) + 17] sclk when using the indirectly coupled frame sync configura- tion in cascaded operation it is necessary to be aware of the restrictions in sending control word data to all devices in the cascade. the user should ensure that there is suffi- cient time for all the control words to be sent between reading the last adc sample and the start of the next sample period. in cascade mode, each device must know the number of devices in the cascade to be able to output data at the cor- rect time. control register a contains a 3-bit field (dc0C 2) that is programmed by the dsp during the programming phase. the default condition is that the field contains 000b, which is equivalent to a single device in cascade (see table xvii). however, for cascade operation this field must contain a binary value that is one less than the number of devices in the cascade. with a number of ad73560s in cascade each device takes a turn to send an adc result to the dsp. for example, in a cascade of two devices the data will be output as device 2-channel 1, device 1-channel 1, device 2-channel 2, device 1- channel 2 etc. when the first device in the cascade has transmitted its channel data there is an additional sclk period during which the last device asserts its sdofs as it begins its transmission of the next channel. this will not cause a problem for most dsps as they count clock edges after a frame sync and hence the extra bit will be ignored. when multiple devices are connected in cascade there are also restrictions concerning which adc channels can be powered up. in all cases the cascaded devices must all have the same channels powered up (i.e., for a cascade of two devices requiring channels 1 and 2 on device 1 and channel 5 on device 2, channels 1, 2 and 5 must be pow- ered up on both devices to ensure correct operation). table xvii. device count settings dc2 dc1 dc0 cascade length 00 01 00 12 01 03 01 14 10 05 10 16 11 07 11 18 functional description - dsp the ad73560 instruction set provides flexible data moves and multifunction (one or two data moves with a compu- tation) instructions. every instruction can be executed in a single processor cycle. the ad73560 assembly language uses an algebraic syntax for ease of coding and readabil- ity. a comprehensive set of development tools supports program development. serial ports sport 1 sport 0 byte dma controller external data bus external address bus full memory mode memory pr ogra mm ab le i/ o an d flags 16k pm (optional 8k) timer adsp-2100 base architecture shifter mac alu arithmetic units power-down control program sequencer dag 2 dag 1 data address generators program memory address data memory address program memory data data memory data 16k dm (optional 8k) by t 6 serial port sport 2 ref adc3 analog front end section adc1 adc2 adc4 adc5 adc6 figure 9. functional block diagram figure 9 is an overall block diagram of the ad73560. the processor contains three independent computational units: the alu, the multiplier/accumulator (mac) and the shifter. the computational units process 16-bit data directly and have provisions to support multiprecision computations. the alu performs a standard set of arith- metic and logic operations; division primitives are also supported. the mac performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. the shifter performs logical and arith- metic shifts, normalization, denormalization and derive exponent operations. the shifter can be used to efficiently implement numeric format control including multiword and block floating- point representations. the internal result (r) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. the sequencer supports condi- tional jumps, subroutine calls and returns in a single cycle. with internal loop counters and loop stacks, the ad73560 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops.
rev. pra ad73560 C20C preliminary technical data two data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and program memory). each dag maintains and updates four address pointers. whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possible modify registers. a length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. efficient data transfer is achieved with the use of five in- ternal buses: ? program memory address (pma) bus ? program memory data (pmd) bus ? data memory address (dma) bus ? data memory data (dmd) bus ? result (r) bus the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (pmd and dmd) share a single external data bus. byte memory space and i/o memory space also share the external buses. program memory can store both instructions and data, permitting the ad73560 to fetch two operands in a single cycle, one from program memory and one from data memory. the ad73560 can fetch an operand from pro- gram memory and the next instruction in the same cycle. in lieu of the address and data bus for external memory connection, the ad73560 may be configured for 16-bit internal dma port (idma port) connection to external systems. the idma port is made up of 16 data/address pins and five control pins. the idma port provides trans- parent, direct access to the dsps on-chip program and data ram. an interface to low cost byte-wide memory is provided by the byte dma port (bdma port). the bdma port is bidirectional and can directly address up to four mega- bytes of external ram or rom for off-chip storage of program overlays or data tables. the byte memory and i/o memory space interface sup- ports slow memories and i/o memory-mapped peripherals with programmable wait state generation. external devices can gain control of external buses with bus request/grant signals (br, bgh, and bg). one execution mode (go mode) allows the ad73560 to continue running from on- chip memory. normal execution mode requires the pro- cessor to halt while buses are granted. the ad73560 can respond to eleven interrupts. there can be up to six external interrupts (one edge-sensitive, two level-sensitive and three configurable) and seven internal interrupts generated by the timer, the serial ports (sports), the byte dma port and the power-down cir- cuitry. there is also a master reset signal. the two serial ports provide a complete synchronous serial inter- face with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. each port can generate an internal programmable serial clock or accept an external serial clock. the ad73560 provides up to 13 general-purpose flag pins. the data input and output pins on sport1 can be alternatively configured as an input flag and an output flag. in addition, there are eight flags that are program- mable as inputs or outputs and three flags that are always outputs. a programmable interval timer generates periodic inter- rupts. a 16-bit count register (tcount) is decremented every n processor cycle, where n is a scaling value stored in an 8-bit register (tscale). when the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod). serial ports the ad73560 incorporates two complete synchronous serial ports (sport0 and sport1) for serial communi- cations and multiprocessor communication. here is a brief list of the capabilities of the ad73560 sports. for additional information on serial ports, refer to the adsp-2100 family users manual , third edition. ? sports are bidirectional and have a separate, double- buffered transmit and receive section. ? sports can use an external serial clock or generate their own serial clock internally. ? sports have independent framing for the receive and transmit sections. sections run in a frameless mode or with frame synchronization signals internally or externally generated. frame sync signals are active high or inverted, with either of two pulsewidths and timings. ? sports support serial data word lengths from 3 to 16 bits and provide optional a-law and -law companding according to ccitt recommendation g.711. ? sport receive and transmit sections can generate unique interrupts on completing a data word transfer. ? sports can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. an interrupt is generated after a data buffer transfer. ? sport0 has a multichannel interface to selectively receive and transmit a 24- or 32-word, time-division mul- tiplexed, serial bitstream. ? sport1 can be configured to have two external inter- rupts (irq0 and irq1) and the flag in and flag out signals. the internally generated serial clock may still be used in this configuration. dsp section pin descriptions the ad73560 will be available in a 119 ball pbga pack- age. in order to maintain maximum functionality and reduce package size and pin count, some serial port, pro- grammable flag, interrupt and external bus pins have dual, multiplexed f unctionality. the external bus pins are configured during reset only, while serial port pins are software configurable during program execution. flag and interrupt functionality is retained concurrently on multiplexed pins. in cases where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics. see pin de- scriptions on page 10.
rev. pra preliminary technical data ad73560 C21C preliminary technical data memory interface pins the ad73560 processor can be used in one of two modes, full memory mode, which allows bdma operation with full external overlay memory and i/o capability, or host mode, which allows idma operation with limited exter- nal addressing capabilities. the operating mode is deter- mined by the state of the mode c pin during reset and cannot be changed while the processor is running. see tables for full memory mode pins and host mode pins for descriptions. full memory mode pins (mode c = 0) pin # of input/ name(s) pins output function a13:0 14 o address output pins for pro- gram, data, byte and i/o spaces d23:0 24 i/o data i/o pins for program, data, byte and i/o spaces (8 msbs are also used as byte memory addresses) host mode pins (mode c = 1) pin # of input/ name(s) pins output function iad15:0 16 i/o idma port address/data bus a0 1 o address pin for external i/o, program, data or byte access d23:8 16 i/o data i/o pins for program, data byte and i/o spaces iwr 1 i idma write enable ird 1 i idma read enable ial 1 i idma address latch pin is 1 i idma select iack 1 o idma port acknowledge configur-able in mode d; open source in host mode, external peripheral addresses can be decoded using the a0, cms , pms , dms and ioms signals terminating unused pin the following table shows the recommendations for ter- minating unused pins. pin terminations i/o hi-z* pin 3-state reset caused unused name (z) state by configuration xtal i i float clkout o o float a13:1 or o (z) hi-z br , ebr float iad12:0 i/o (z) hi-z is float a0 o (z) hi-z br , ebr float d23:8 i/o (z) hi-z br , ebr float d7 or i/o (z) hi-z br , ebr float iwr i i high (inactive) d6 or i/o (z) hi-z br , ebr float ird ii br , ebr high (inactive) d5 or i/o (z) hi-z float ial i i low (inactive) d4 or i/o (z) hi-z br , ebr float is i i high (inactive) d3 or i/o (z) hi-z br , ebr float iack float d2:0 or i/o (z) hi-z br , ebr float iad15:13 i/o (z) hi-z is float pms o (z) o br, ebr float dms o (z) o br , ebr float bms o (z) o br , ebr float ioms o (z) o br , ebr float cms o (z) o br , ebr float rd o (z) o br , ebr float wr o (z) o br , ebr float br i i high (inactive) bg o (z) o ee float bgh o o float irq2 /pf7 i/o (z) i input = high (inac- tive) or program as out- put, set to 1, let float irql1 /pf6 i/o (z) i input = high (inac- tive) or program as out- put, set to 1, let float irql0 /pf5 i/o (z) i input = high (inac- tive) or program as out- put, set to 1, let float irqe /pf4 i/o (z) i input = high (inac- tive) or program as out- put, set to 1, let float sclk0 i/o i input = high or low, output = float rfs0 i/o i high or low dr0 i i high or low
rev. pra ad73560 C22C preliminary technical data pin terminations i/o hi-z* pin 3-state reset caused unused name (z) state by configuration tfs0 i/o o high or low dt0 o o float sclk1 i/o i input = high or low, output = float rfs1/ rq0 i/o i high or low dr1/ fl1 i i high or low tfs1/ rq1 i/o o high or low dt1/fo o o float ee i i ebr ii ebg oo ereset ii ems oo eint ii eclk i i elin i i elout o o notes * *hi-z = high impedance. 1. if the clkout pin is not used, turn it off. 2. if the interrupt/programmable flag pins are not used, there are two options: option 1: when these pins are configured as inputs at reset and function as interrupts and input flag pins, pull the pins high (inactive). option 2: program the unused pins as outputs, set them to 1, and let them float. 3. all bidirectional pins have three-stated outputs. when the pins is configured as an output, the output is hi-z (high impedance) when inactive. 4. clkin, reset, and pf3:0 are not included in the table because these pins must be used. interrupts the interrupt controller allows the processor to respond to the eleven possible interrupts and reset with mini- mum overhead. the ad73560 provides four dedicated external interrupt input pins, irq2 , irql0 , irql1 and irqe . in addi- tion, sport1 may be reconfigured for irq0 , irq1 , flag_in and flag_out, for a total of six external interrupts. the ad73560 also supports internal interrupts from the timer, the byte dma port, the two serial ports, software and the power-down control circuit. the inter- rupt levels are internally prioritized and individually maskable (except power down and reset). the irq2 , irq0 and irq1 input pins can be programmed to be either level- or edge-sensitive. irql0 and irql1 are level- sensitive and irqe is edge sensitive. the priorities and vector addresses of all interrupts are shown in table xix. table xix. interrupt priority and interrupt vector addresses interrupt vector source of interrupt address (hex) reset (or power-up with pucr = 1) 0000 ( highest priority ) power-down (nonmaskable) 002c irq2 0004 irql1 0008 irql0 000c sport0 transmit 0010 sport0 receive 0014 irqe 0018 bdma interrupt 001c sport1 transmit or irq1 0020 sport1 receive or irq0 0024 timer 0028 ( lowest priority ) interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. interrupts can be masked or unmasked with the imask register. individual interrupt requests are logically anded with the bits in imask; the highest priority un- masked int errupt is then selected. the power-down in- terrupt is nonmaskable. the ad73560 masks all interrupts for one instruction cycle following the execution of an instruction that modi- fies the imask register. this does not affect serial port auto-buffering or dma transfers. the interrupt control register, icntl, controls interrupt nesting and defines the irq0 , irq1 and irq2 external interrupts to be either edge- or level-sensitive. the irqe pin is an external edge-sensitive interrupt and can be forced and cleared. the irql0 and irql1 pins are ex- ternal level-sensitive interrupts. the ifc register is a write-only register used to force and clear interrupts. on-chip stacks preserve the processor status and are automatic ally maintained during interrupt handling. the stacks are twelve levels deep to allow inter- rupt, loop and subroutine nesting. the following instruc- tions allow global enable or disable servicing of the interrupts (including power down), regardless of the state of imask. disabling the interrupts does not affect serial port autobuffering or dma. ena ints; dis ints; when the processor is reset, interrupt servicing is enabled. low power operation the ad73560 has three low power modes that signifi- cantly reduce the power dissipation when the device oper- ates under standby conditions. these modes are: ? power-down ? idle ? slow idle the clkout pin may also be disabled to reduce exter- nal power dissipation.
rev. pra preliminary technical data ad73560 C23C preliminary technical data power-down the ad73560 processor has a low power feature that lets the processor enter a very low power dormant state through hardware or software control. here is a brief list of power-down features. refer to the adsp-2100 family users manual , third edition, system interface chapter, for detailed information about the power-d own feature. ? quick recovery from power-down. the processor begins executing instructions in as few as 400 clkin cycles. ? support for an externally generated ttl or cmos processor clock. the external clock can continue run- ning during power-down without affecting the 400 clkin cycle recovery. ? support for crystal operation includes disabling the oscillator to save power (the processor automatically waits 4096 clkin cycles for the crystal oscillator to start and stabilize), and letting the oscillator run to allow 400 clkin cycle start up. ? power-down is initiated by either the power-down pin ( pwd ) or the software power-down force bit interrupt support allows an unlimited number of instructions to be executed before optionally powering down. the power-down interrupt also can be used as a non- maskable, edge-sensitive interrupt. ? context clear/save control allows the processor to con- tinue where it left off or start with a clean context when leaving the power-down state. ? the reset pin also can be used to terminate power- down. ? power-down acknowledge pin indicates when the pro- cessor has entered power-down. idle when the ad73560 is in the idle mode, the processor waits indefinitely in a low power state until an interrupt occurs. when an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the idle instruction. in i dle mode idma, bdma and autobuffer cycle steals still occur. slow idle the idle instruction on the ad73560 slows the processors internal clock signal, further reducing power consump- tion. the reduced clock frequency, a programmable frac- tion of the normal clock rate, is specified by a selectable divisor given in the idle instruction. the format of the instruction is idle (n); where n = 16, 32, 64 or 128. this instruction keeps the processor fully functional, but operating at the slower clock rate. while it is in this state, the processors other internal clock signals, such as sclk, clkout and timer clock, are reduced by the same ratio. the default form of the instruction, when no clock divisor is given, is the standard idle instruction. when the idle (n) instruction is used, it effectively slows down the processors internal clock and thus its response time to incoming interrupts. the one-cycle response time of the standard idle state is increased by n , the clock divi- sor. when an enabled interrupt is received, the ad73560 will remain in the idle state for up to a maximum of n processor cycles ( n = 16, 32, 64 or 128) before resuming normal operation. when the idle (n) instruction is used in systems that have an externally generated serial clock (sclk), the serial clock rate may be faster than the processors reduced in- ternal clock rate. under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). system interface figure 10 shows a typical basic system configuration with the a d73560, two serial devices, a byte-wide eprom, and optional external program and data overlay memories (mode selectable). programmable wait state generation allows the processor to connect easily to slow peripheral devices. the ad73560 also provides four external inter- rupts and two serial ports or six external interrupts and one serial port. host memory mode allows access to the full external data bus, but limits addressing to a single address bit (a0) additional system peripherals can be added in this mode through the use of external hardware to generate and latch address signals. clock signals the ad73560 can be clocked by either a crystal or a ttl-compatible clock signal. the clkin input cannot be halted, changed during op- eration or operated below the specified frequency during normal operation. the only exception is while the proces- sor is in the power-d own state. for additional informa- tion, refer to chapter 9, adsp-2100 family users manual, third edition, for detailed information on this power-down feature. if an external clock is used, it should be a ttl-compat- ible signal running at half the instruction rate. the signal is connected to the processors clkin input. when an external clock is used, the xtal input must be left un- connected.
rev. pra ad73560 C24C preliminary technical data sclk1 rfs1 or irq0 tfs1 or irq1 dt1 or fo dr1 or fi sport1 sclk0 rfs0 tfs0 dt0 dr0 sport0 a0-a21 data cs byte memory i/o space (peripherals) cs data addr data addr 2048 locations overlay memory two 8k pm segments two 8k dm segments a 13-0 d 23-8 a 10-0 d 15-8 d 23-16 a 13-0 14 24 fl0-2 pf3 clkin xtal addr13-0 data23-0 bms iom s pms dms cms br bg bgh pwd pwdack ad73422 system interface or m controller 16 1 16 fl0-2 pf3 clkin xtal a0 data23-8 bms iom s ad73422 irq2 /pf7 irqe /pf4 irql0 /pf5 irql1 /pf6 mode c/pf2 mode b/pf1 mode a/pf0 host memory mode irq2 /pf7 irqe /pf4 irql0 /pf5 irql1 /pf6 mode c/pf2 mode b/pf1 mode a/pf0 full memory mode wr rd wr rd 1/2x clock or crystal afe* section or serial device afe* section or serial device d 23-0 1/2x clock or crystal sclk1 rfs1 or irq0 tfs1 or irq1 dt1 or fo dr1 or fi sport1 sclk0 rfs0 tfs0 dt0 dr0 sport0 afe* section or serial device afe* section or serial device pms dms cms br bg bgh pwd pwdack idma port ird /d6 iw r /d7 is /d4 ial/d5 iack /d3 iad15-0 *afe section can be connected to either sport0 or sport1 figure 10. ad73560 basic system configuration the ad73560 uses an input clock with a frequency equal to half the instruction rate; a 26.00 mhz input clock yields a 19 ns processor cycle (which is equivalent to 52 mhz). normally, instructions are executed in a single processor cycle. all device timing is relative to the inter- nal instruction clock rate, which is indicated by the clkout signal when enabled. because the ad73560 includes an on-chip oscillator cir- cuit, an external crystal may be used. the crystal should be connected across the clkin and xtal pins, with two capacitors con nected as shown in figure 11. capacitor values are dependent on crystal type and should be speci- fied by the crystal manufacturer. a parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. a clock output (clkout) signal is generated by the processor at the processors cycle rate. this can be en- abled and disabled by the clk0dis bit in the sport0 autobuffer control register. clkin clkout xtal dsp figure 11. external crystal connections reset the reset signal initiates a master reset of the ad73560. the reset signal must be asserted during the power-up sequence to assure proper initialization. reset during initial power-up must be held long enough to allow the internal clock to stabilize. if reset is activated any time after power-up, the clock continues to run and does not require stabilization time. the power-up sequence is defined as the total time re- quired for the crystal oscillator circuit to stabilize after a valid v dd is applied to the processor, and for the internal phase-locked loop (pll) to lock onto the specific crystal frequency. a minimum of 2000 clkin cycles ensures that the pll has locked, but does not include the crystal oscillator start-up time. during this power-up sequence the reset signal should be held low. on any subsequent resets, the reset signal must meet the minimum pulsewidth specification, t rsp . the reset input contains some hysteresis; however, if an rc circuit is used to generate the reset signal, an external schmidt trigger is recommended. the master reset sets all internal stack pointers to the empty stack condition, masks all interrupts and clears the mstat register. when reset is released, if there is no pending bus request and the chip is configured for boot- ing, the boot-loading sequence is performed. the first instruction is fetched from on-chip program memory loca tion 0x0000 once boot loading completes. modes of operation table xx summarizes the ad73560 memory modes. setting memory mode memory mode selection for the ad73560 is made during chip reset through the use of the mode c pin. this pin is multiplexed with the dsps pf2 pin, so care must be taken in how the mode selection is made. the two meth- ods for selecting the value of mode c are active and pas- sive. passive configuration involves the use a pull-up or pull- down resistor connected to the mode c pin. to minimize
rev. pra preliminary technical data ad73560 C25C preliminary technical data power consumption, or if the pf2 pin is to be used as an output in the dsp application, a weak pull-up or pull- down, on the order of 100 ky, can be used. this value should be sufficient to pull the pin to the desired level and still allow the pin to operate as a programmable flag output without undue strain on the processors output driver. for minimum power consump- tion during power-down, reconfigure pf2 to be an input, as the pull-up or pull-down will hold the pin in a known state, and will not switch. active configuration involves the use of a three-statable external driver connected to the mode c pin. a drivers output enable should be connected to the dsps reset signal such that it only drives the pf2 pin when reset is active (low). when reset is deasserted, the driver should three-state, thus allowing full use of the pf2 pin as either an input or output. to minimize power consump- tion during power-down, configure the programmable flag as an output when connected to a three-stated buffer. this ensures that the pin will be held at a constant level and not oscillate should the three-state drivers level hover around the logic switching point. memory architecture the ad73560 provides a variety of memory and periph- eral interface options. the key functional groups are pro- gram memory, data memory, byte memory, and i/o. refer to the following figures and tables for pm and dm memory allocations in the ad73560. program memory program memory (full memory mode) is a 24-bit-wide space for storing both instruction opcodes and data. the ad73560-80 has 16k words of program memory ram on chip (the ad73560-40 has 8k words of program memory ram on chip), and the capability of accessing up to two 8k external memory overlay spaces using the exter- nal data bus . program memory (host mode) allows access to all inter- nal memory. external overlay access is limited by a single external address line (a0). external program execution is not available in host mode due to a restricted data bus that is 16-bits wide only. table xxi. pmovlay bits pmovlay memory a13 a12:0 0, internal not applicable not applicable 1 external 0 13 lsbs of ad dress overlay 1 between 0x2000 and 0x3fff 2 external 1 13 lsbs of ad dress overlay 2 between 0x2000 and 0x3fff table xxi. modes of operations 1 mode c 2 mode b 3 mode a 4 booting method 0 0 0 bdma feature is used to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. chip is configured in full memory mode. 5 0 1 0 no automatic boot operations occur. program execution starts at external memory location 0. chip is configured in full memory mode. bdma can still be used, but the processor does not automatically use or wait for these operations. 1 0 0 bdma feature is used to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. chip is configured in host mode. (requires additional hardware.) 1 0 1 idma feature is used to load any internal memory as desired. program execu- tion is held off until internal program memory location 0 is written to. chip is configured in host mode. 5 notes 1 all mode pins are recognized while reset is active (low). 2 when mode c = 0, full memory enabled. when mode c = 1, host memory mode enabled. 3 when mode b = 0, auto booting enabled. when mode b = 1, no auto booting. 4 when mode a = 0, bdma enabled. when mode a = 1, idma enabled. 5 considered as standard operating settings. using these configurations allows for easier design and better memory management.
rev. pra ad73560 C26C preliminary technical data accessible when pmovlay = 2 accessible when pmovlay = 1 always accessible at address 0 x 0000 - 0 x 1fff accessible when pmovlay = 0 3 pm (mode b = 0) internal memory external memory 0 x2000- 0x3fff 0 x2000- 0x3fff 2 0 x2000- 0x3fff 2 8k internal pmovlay = 0 3 8k external program memory mode b = 1 address 0 x 3fff 0 x 2000 0 x 1fff 0 x 0000 8k internal pmovlay = 0 3 or 8k external pmovlay = 1 or 2 0 x 3fff 0 x 2000 0 x 1fff 8k internal 0 x 0000 program memory mode b = 0 address accessible when pmovlay = 0 internal memory external memory 0 x2000- 0x3fff 0 x0000- 0x1fff 2 pm (mode b = 1) 1 reserved 1 when m ode b = 1, pm ovlay must be set to 0 2 see table iii for pmovlay bits 3 not accessible on ad73422-40 accessible when pmovlay = 0 3 reserved figure 12. program memory map data memory data memory (full memory mode) is a 16-bit-wide space used for the storage of data variables and for memory- mapped control registers. the ad73560-80 has 16k words on data memory ram on chip (the ad73560-40 has 8k words on data memory ram on chip), consisting of 16,352 user-accessible locations in the case of the ad73560-80 ( 8,160 user-accessible locations in the case of the ad73560-40) and 32 memory-mapped registers. support also exists for up to two 8k external memory overlay spaces through the external data bus. all internal accesses complete in one cycle. accesses to external memory are timed using the wait states specified by the dwait register. accessible when dmovlay = 2 accessible when dmovlay = 1 always accessible at address 0 x 2000 - 0 x 3fff accessible when dmovlay = 0 internal memory external memory 0 x 0000- 0 x 1fff 0 x 0000- 0 x 1fff 0 x 0000- 0 x 1fff data memory 32 memory mapped registers 0 x 3fff 0 x 2000 0 x 1fff internal 8160 words 0 x 0000 data memory address 8k internal dmovlay = 0 or external 8k dmovlay = 1, 2 0 x 3fe0 0 x 3fdf figure 13. data memory map data memory (host mode) allows ac cess to all inte rnal memory. external overlay access is limited by a single external address line (a0). the dmovlay bits are de- fined in table xxii. table xxii. dmovlay bits dmovlay memory a13 a12:0 0, internal not applicable not applicable 1 external 0 13 lsbs of ad- dress overlay 1 between 0x2000 and 0x3fff 2 external 1 13 lsbs of ad- dress overlay 2 between 0x2000 and 0x3fff i/o space (full memory mode) the ad73560 supports an additional external memory space called i/o space. this space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface asic data reg- isters. i/o space supports 2048 locations of 16-bit wide data. the lower eleven bits of the external address bus are used; the upper three bits are undefined. two instructions were added to the core adsp-2100 family instruction set to read from and write to i/o memory space. the i/o space also has four dedicated 3-bit wait state registers, iowait0-3, that specify up to seven wait states to be automatically generated for each of four regions. the wait states act on address ranges as shown in table xxiii. table xxiii. wait states address range wait state register 0x000C0x1ff iowait0 0x200C0x3ff iowait1 0x400C0x5ff iowait2 0x600C0x7ff iowait3 composite memory select ( cms ) the ad73560 has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. the cms signal is generated to have the same timing as each of the individual memory select signals ( pms , dms , bms , ioms ) but can combine their functionality. each bit in the cmssel register, when set, causes the cms signal to be asserted when the selected memory select is asserted. for example, to use a 32k word memory to act as both program and data memory, set the pms and dms bits in the cmssel register and use the cms pin to drive the chip select of the memory; use either dms or pms as the additional address bit. the cms pin functions like the other memory select signals, with the same timing and bus request logic. a 1 in the enable bit causes the assertion of the cms signal at
rev. pra preliminary technical data ad73560 C27C preliminary technical data the same time as the selected memory select signal. all enable bits default to 1 at reset, except the bms bit. boot memory select ( bms ) disable the ad73560 also lets you boot the processor from one external memory space while using a different external memory space for bdma transfers during normal opera- tion. you can use the cms to select the first external memory space for bdma transfers and bms to select the second external memory space for booting. the bms signal can be disabled by setting bit 3 of the system con- trol register to 1. the system control register is illus- trated in figure 14. system control register pwait program memory wait states 0000010000000111 1514131211109876543210 dm (0 3 3fff) bms enable 0 = enabled 1 = disabled sport0 enable 1 = enabled 0 = disabled sport1 enable 1 = enabled 0 = disabled sport1 configure 1 = serial port 0 = fi, fo, irq0 , irq1 , sclk figure 14. system control register byte memory the byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. byte memory is accessed using the bdma feature. the bdma control register is shown in figure 15. the byte memory space consists of 256 pages, each of which is 16k x 8. the byte memory space on the ad73560 supports read and write operations as well as four different data formats. the byte memory uses data bits 15:8 for data. the byte memory uses data bits 23:16 and address bits 13:0 to cre- ate a 22-bit address. this allows up to a 4 meg 8 (32 megabit) rom or ram to be used without glue logic. all byte memory accesses are timed by the bmwait register. byte memory dma (bdma, full memory mode) the byte memory dma controller allows loading and storing of program instructions and data using the byte memory space. the bdma circuit is able to access the byte memory space while the processor is operating nor- mally, and steals only one dsp cycle per 8-, 16- or 24-bit word transferred. bdma control bm page btype bcr 0 = run during bdma 1 = halt during bdma 0000000000001000 1514131211109876543210 dm (0 3 3fe3) bdir 0 = load from bm 1 = store to bm figure 15. bdma control register the bdma circuit supports four different data formats that are selected by the btype register field. the appro- priate number of 8-bit accesses are done from the byte memory space to build the word size selected. table xxiv shows the data formats supported by the bdma circuit. table xxiv. data formats internal btype memory space word size alignment 00 program memory 24 full word 01 data memory 16 full word 10 data memory 8 msbs 11 data memory 8 lsbs unused bits in the 8-bit data memory formats are filled with 0s. the biad register field is used to specify the starting address for the on-chip memory involved with the transfer. the 14-bit bead register specifies the starting address for the external byte memory space. the 8-bit bmpage register specifies the starting page for the ex- ternal byte memory space. the bdir register field selects the direction of the transfer. finally the 14-bit bwcount register specifies the number of dsp words to transfer and initiates the bdma circuit transfers. bdma accesses can cross page boundaries during sequen- tial addressing. a bdma interrupt is generated on the completion of the number of transfers specified by the bwcount register. the bwcount register is updated after each transfer so it can be used to check the status of the transfers. when it reaches zero, the transfers have finished and a bdma interrupt is generated. the bmpage and bead registers must not be accessed by the dsp during bdma opera- tions. the source or destination of a bdma transfer will always be on-chip program or data memory. when the bwcount register is written with a nonzero value, the bdma circuit starts executing byte memory accesses with wait states set by bmwait. these accesses continue until the count reaches zero. when enough ac- cesses have occurred to create a destination word, it is transferred to or from on-chip memory. the transfer takes one dsp cycle. dsp accesses to external memory have priority over bdma byte memory accesses. the bdma context reset bit (bcr) controls whether or not the processor is held off while the bdma accesses are occurring. setting the bcr bit to 0 allows the processor to continue operations. setting the bcr bit to 1 causes the processor to stop execution while the bdma accesses are occurring, to clear the context of the processor and start execution at address 0 when the bdma accesses have completed. the bdma overlay bits specify the ovlay memory blocks to be accessed for internal memory. internal memory dma port (idma port; host memory mode) the idma port provides an efficient means of communi- cation between a host system and the ad73560. the port is used to access the on-chip program memory and data memory of the dsp with only one dsp cycle per word
rev. pra ad73560 C28C preliminary technical data overhead. the idma port cannot be used, however, to write to the dsps memory-mapped control registers. a typical idma transfer process is described as follows: 1. host starts idma transfer. 2. host checks iack control line to see if the dsp is busy. 3. host uses is and ial control lines to latch either the dma starting address (idmaa) or the pm/dm ovlay selection into the dsps idma control regis- ters. if iad[15] = 1, the value of iad[7:0] represent the idma overlay: iad[14:8] must be set to 0. if iad[15] = 0, the value of iad[13:0] represent the starting address of internal memory to be accessed and iad[14] reflects pm or dm for access. 4. host uses is and ird (or iwr ) to read (or write) dsp internal memory (pm or dm). 5. host checks iack line to see if the dsp has completed the previous idma operation. 6. host ends idma transfer. the idma port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. the idma port is completely asynchronous and can be written to while the ad73560 is operating at full speed. the dsp memory address is latched and then automati- cally incremented after each idma transaction. an exter- nal device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. this increases throughput as the address does not have to be sent for each memory access. idma port access occurs in two phases. the first is the idma add ress latch cycle. when the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. the address specifies an on-chip memory location; the destination type specifies whether it is a dm or pm access. the falling edge of the address latch signal latches this value into the idmaa register. once the address is stored, data can either be read from or written to the ad73560s on-chip memory. asserting the select line ( is ) and the appropriate read or write line ( ird and iwr respectively) signals the ad73560 that a particu- lar transaction is required. in either case, there is a one- processor-cycle delay for synchronization. the memory access consumes one additional processor cycle. once an access has occurred, the latched address is auto- matically incremented and another access can occur. through the idmaa register, the dsp can also specify the starting address and data format for dma operation. asserting the idma port select ( is ) and address latch enable (ial) directs the ad73560 to write the address onto the iad0C14 bus into the idma control register. if iad[15] is set to 0, idma latches the address. if iad[15] is set to 1, idma latches ovlay memory. the idma ovlay and address are stored in s eparate memory-mapped registers. the idmaa register, shown below, is memory mapped at address dm (0x3fe0). note that the latched address (idmaa) cannot be read back by the host. the idma ovlay register is memory mapped at address dm (0x3fe7). see figure 16 for more information on idma and dma memory maps. idma control (u = undefined at reset) dm(0 3 3fe0) idmaa address idmad destination memory type: 0 = pm 1 = dm uuuuuuuuuuuuuuu 15141312111098 76543210 figure 16. idma control/ovlay registers bootstrap loading (booting) the ad73560 has two mechanisms to allow automatic loading of the internal program memory after reset. the method for booting after reset is controlled by the mode a, b and c configuration bits. when the mode pins specify bdma booting, the ad73560 initiates a bdma boot sequence when reset is released. the bdma interface is set up during reset to the follow- ing defaults when bdma booting is specified: the bdir, bmpage, biad and bead registers are set to 0, the btype register is set to 0 to specify program memory 24-bit words, and the bwcount register is set to 32. this causes 32 words of on-chip program memory to be loaded from byte memory. these 32 words are used to set up the bdma to load in the remaining program code. the bcr bit is also set to 1, which causes program ex- ecution to be held off until all 32 words are loaded into on-chip program memory. execution then begins at ad- dress 0. the adsp-2100 family development software (revision 5.02 and later) fully supports the bdma booting feature and can generate byte memory space compatible boot code. the idle instruction can also be used to allow the pro- cessor to hold off execution while booting continues through the bdma interface. for bdma accesses while in host mode, the addresses to boot memory must be constructed externally to the ad73560. the only memory address bit provided by the processor is a0. idma port booting the ad73560 can also boot programs through its internal dma port. if mode c = 1, mode b = 0 and mode a = 1, the ad73560 boots from the idma port. idma fea- ture can load as much on-chip memory as desired. pro- gram execution is held off until on-chip program memory location 0 is written to. bus request and bus grant (full memory mode) the ad73560 can relinquish control of the data and ad- dress buses to an external device. when the external de- vice requires access to memory, it asserts the bus request (br) signal. if the ad73560 is not performing an external
rev. pra preliminary technical data ad73560 C29C preliminary technical data memory access, it responds to the active br input in the following processor cycle by: ? three-stating the data and address buses and the pms , dms , bms , cms , ioms , rd , wr output drivers, ? asserting the bus grant ( bg ) signal, and ? halting program execution. if go mode is enabled, the ad73560 will not halt pro- gram execution until it encounters an instruction that requires an external memory access. if the ad73560 is performing an external memory access when the external device asserts the br signal, it will not three-state the memory interfaces or assert the bg signal until the processor cycle after the access completes. the instruction does not need to be completed when the bus is granted. if a single instruction requires two external memory accesses, the bus will be granted between the two accesses. when the br signal is released, the processor releases the bg signal, reenables the output drivers and continues program execution from the point at which it stopped. the bus request feature operates at all times, including when the processor is booting and when reset is active. the bgh pin is asserted when the ad73560 is ready to execute an instruction, but is stopped because the external bus is already granted to another device. the other device can release the bus by deasserting bus request. once the bus is released, the ad73560 deasserts bg and bgh and executes the external memory access. flag i/o pins the ad73560 has eight general purpose programmable input/output flag pins. they are controlled by two memory mapped registers. the pftype register deter- mines the direction, 1 = output and 0 = input. the pfdata register is used to read and write the values on the pins. data being read from a pin configured as an input is synchronized to the ad73560s clock. bits that are pro- grammed as outputs will read the value being output. the pf pins default to input during reset. in addition to the programmable flags, the ad73560 has five fixed-mode flags, flag_in, flag_out, fl0, fl1 and fl2. fl0-fl2 are dedicated output flags. flag_in and flag_out are available as an alternate configuration of sport1. note: pins pf0, pf1, pf2 and pf3 are also used for device configuration during reset. instruction set description the ad73560 assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. the assembly language, which takes full ad- vantage of the processors unique architecture, offers the following benefits: ? the algebraic syntax eliminates the need to remember cryptic assembler mnemonics. for example, a typical arithmetic add instruction, such as ar = ax0 + ay0, resembles a simple equation. ? every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. ? the syntax is a superset adsp-2100 family assembly language and is completely source and object code compat- ible with other family members. programs may need to be relocated to utilize on-chip memory and conform to the ad73560s interrupt vector and reset vector map. ? sixteen condition codes are available. for conditional jump, call, return or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. ? multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle. designing an ez-ice-compatible system the ad73560 has on-chip emulation support and an ice- port, a special set of pins that interface to the ez-ice. these features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connec- tion from the target system to the ez-ice. target systems must have a 14-pin connector to accept the ez-ices in- circuit probe, a 14-pin plug. see the adsp-2100 family ez-tools data sheet for complete information on ice products. issuing the chip reset command during emulation causes the dsp to perform a full chip reset, including a reset of its memory mode. therefore, it is vital that the mode pins are set correctly prior to issuing a chip reset command from the emulator user interface. if you are using a passive method of maintaining mode information (as discussed in setting memory modes) then it does not matter that the mode information is latched by an emulator reset. how- ever, if you are using the reset pin as a method of set- ting the value of the mode pins, then you have to take into consideration the effects of an emulator reset. one method of ensuring that the values located on the mode pins are those desired is to construct a circuit like the one shown in figure 17. this circuit forces the value located on the mode a pin to logic high; regardless if it latched via the reset or ereset pin. reset ereset 1k w ad73560 mode a /pfo programmable i/o figure 17. mode a pin/ez-ice circuit
rev. pra ad73560 C30C preliminary technical data the ice-port interface consists of the following ad73560 pins: ebr ebg ereset ems eint eclk elin elout ee these ad73560 pins must be connected only to the ez- ice connector in the target system. these pins have no function except during emulation, and do not require pull-up or pull-down resistors. the traces for these signals between the ad73560 and the connector must be kept as short as possible, no longer than three inches. the following pins are also used by the ez-ice: br bg reset gnd the ez-ice uses the ee (emulator enable) signal to take control of the ad73560 in the target system. this causes the processor to use its ereset, ebr and ebg pins instead of the reset, br and bg pins. the bg output is three-stated. these signals do not need to be jumper- isolated in your system. the ez-ice connects to your target system via a ribbon cable and a 14-pin female plug. the ribbon cable is 10 inches in length with one end fixed to the ez-ice. the female plug is plugged onto the 14-pin connector (a pin strip header) on the target board. target board connector for ez-ice probe the ez-ice connector (a standard pin strip header) is shown in figure 18. you must add this connector to your target board design if you intend to use the ez-ice. be sure to allow enough room in your system to fit the ez- ice probe onto the 14-pin connector. 3 12 34 56 78 9 10 11 12 13 14 gnd key (no pin) reset br bg top view ebg ebr elout ee eint elin eclk ems ereset figure 18. target board connector for ez-ice the 14-pin, 2-row pin strip header is keyed at the pin 7 locationyou must remove pin 7 from the header. the pins must be 0.025 inch square and at least 0.20 inch in length. pin spacing should be 0.1 x 0.1 inches. the pin strip header must have at least 0.15 inch clearance on all sides to accept the ez-ice probe plug. pin strip headers are available from vendors such as 3m, mckenzie and samtec. target memory interface for your target system to be compatible with the ez-ice emulator, it must comply with the memory interface guidelines listed below. pm, dm, bm, iom and cm design your program memory (pm), data memory (dm), byte memory (bm), i/o memory (iom) and composite memory (cm) external interfaces to comply with worst case device timing requirements and switching characteristics as specified in the dsps data sheet. the performance of the ez-ice may approach published worst case specifica- tion for some memory access timing requirements and switching characteristics. note: if your target does not meet the worst case chip specification for memory access parameters, you may not be able to emulate your circuitry at the desired clkin frequency. depending on the severity of the specification violation, you may have trouble manufacturing your sys- tem as dsp components statistically vary in switching characteristic and timing requirements within published limits. restriction: all memory strobe signals on the ad73560 ( rd , wr , pms , dms , bms , cms and ioms ) used in your target system must have 10 k w pull-up resistors con- nected when the ez-ice is being used. the pull-up resis- tors are necessary because there are no internal pull-ups to guarantee their state during prolonged three-state condi- tions resulting from typical ez-ice debugging sessions. these resistors may be removed at your option when the ez-ice is not being used. target system interface signals when the ez-ice board is installed, the performance on some system signals changes. design your system to be compatible with the following system interface signal changes introduced by the ez-ice board: ? ez-ice emulation introduces an 8 ns propagation delay between your target circuitry and the dsp on the re- set signal. ? ez-ice emulation introduces an 8 ns propagation delay between your target circuitry and the dsp on the br signal. ? ez-ice emulation ignores reset and br when single- stepping. ? ez-ice emulation ignores reset and br when in emulator space (dsp halted). ? ez-ice emulation ignores the state of target br in certain modes. as a result, the target system may take control of the dsps external memory bus only if bus grant ( bg ) is asserted by the ez-ice boards dsp.
rev. pra preliminary technical data ad73560 C31C preliminary technical data flash memory description the ad73560 features a 64k x 8 cmos page mode eeprom which can be written with a 3.0-volt-only power supply. internal erase/program is transparent to the user. featuring high performance page write, the ad73560s flash memory provides a typical byte-write time of 39 sec. the entire memory, i.e., 64k bytes, can be written page by page in as little as 2.5 seconds, when using inter- face features such as toggle bit or data polling to indi- cate the completion of a write cycle. to protect against inadvertent write, the ad73560 has on-chip hardware and software data protection schemes. the ad73560s flash memory has a guaranteed page- write endurance of 10 4 or 10 3 cycles. data retention is rated at greater than 100 years. the ad73560 is suited for applications that require convenient and economical updating of program, configuration, or data memory. flash memory connection the flash memory section of the ad73560 is configured on the byte-wide dma bus (bdma) of the dsp section as shown in figure 19. hence if boot operation is re- quired from the ad73560s internal flash memory, the boot mode selection pins mode a, mode b and mode c should be set to zero (0). data [0-7] ce byte memory -flash 64 kbytes d 15 d 17 a 13 bms ad73560 wr rd d 8 a 0 d 16 address [0-13] address [14-15] db 7 db 0 a 13 a 0 a 15 a 14 oe we ds p section figure 19. flash interface to dsp section device operation the ad73560s page mode eeprom offers in-circuit electrical write capability. the ad73560 does not require separate erase and program operations. the internally timed write cycle executes both erase and program trans- parently to the user. the ad73560 has industry standard optional software data protection, which is recommended to be always enabled. read the read operation of the ad73560 is controlled by bms and rd , both have to be low for the dsp section to obtain data from the flash section. bms is used for device selec- tion. when bms is high, the flash memory is deselected and only standby power is consumed. rd is the output control and is used to gate data from the flash output pins. the data bus is in high impedance state when either bms or rd is high. refer to the read cycle timing diagram (figure 21) for further details. write the write operation consists of three steps. the first step is the optional three byte load sequence for software data protection. this is an optional first step in the write op- eration, but highly recommended to ensure proper data integrity. step 2 is the byte-load cycle to a page buffer of the flash. step 3 is an internally controlled write cycle for writing the data loaded in the page buffer into the memory array for nonvolatile storage. during the byte-load cycle, the addresses are latched by the falling edge of either bms or wr , whichever occurs last. the data is latched by the rising edge of either bms or wr , whichever occurs first. the internal write cycle is initiated by a timer after the rising edge of wr or bms , whichever occurs first. the write cycle, once initiated, will continue to comple- tion, typically within 5 ms. see figures 22 and 23 for wr and bms controlled page write cycle timing diagrams. the write operation has three functional cycles: the op- tional software data protection load sequence, the page x-decoder 512 kbit eeprom cell array y-decoder & page latches i/o buffers & data latches address buffer & latches control block data bus (db 0-7 ) address bus (a 0-15 ) ce oe we figure 20. flash memory organisation
rev. pra ad73560 C32C preliminary technical data load cycle and the internal write cycle. the software data protection consists of a specific three byte load sequence that will leave the ad73560 protected at the end of the page write. the page load cycle consists of loading 1 to 128 bytes of data into the page buffer. the internal write cycle consists of the t blco timeout and the write timer operation. during the write operation, the only valid reads are data polling and toggle bit. the page-write opera- tion allows the loading of up to 128 bytes of data into the page buffer of the ad73560 flash before the initiation of the internal write cycle. during the internal write cycle, all the data in the page buffer is written simultaneously into the memory array. hence, the page-write feature of ad73560 allows the entire memory to be written in as little as 2.5 seconds. during the internal write cycle, the host is free to perform additional tasks, such as to fetch data from other locations in the system to set up the write to the next page. in each page-write operation, all the bytes that are loaded into the page buffer must have the same page address, i.e., a7 through a15. any byte not loaded with user data will be written to ff. see figures 22 and 23 for the page-write cycle timing diagrams. if after the initial byte-load cycle, the host loads a second byte into the page buffer within a byte-load cycle time (t blc ) of 100 s, the ad73560 will stay in the page load cycle. additional bytes are then loaded consecutively. the page load cycle will be terminated if no additional byte is loaded into the page buffer within 200 s (t blco ) from the last byte-load cycle, i.e., no subsequent wr or bms high- to-low transition after the last rising edge of wr or bms . data in the page buffer can be changed by a subsequent byte-load cycle. the page load period can continue indefi- nitely, as long as the host continues to load the device within the byte-load cycle time of 100 s. the page to be loaded is determined by the page address of the last byte loaded. write operation status detection the ad73560 provides two software means to detect the completion of a write cycle, in order to optimize the sys- tem write cycle time. the software detection includes two status bits: data polling (dq7) and toggle bit (dq6). the end of write detection mode is enabled after the rising we or ce whichever occurs first, which initiates the in- ternal write cycle. the actual completion of the nonvola- tile write is asynchronous with the system; therefore, either a data polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq7 or dq6. in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. data polling (dq7) when the ad73560 is in the internal write cycle, any attempt to read dq7 of the last byte loaded during the byte-load cycle will receive the complement of the true data. once the write cycle is completed, dq7 will show true data. the device is then ready for the next operation. see figure 24 for data polling timing diagram. toggle bit (dq6) during the internal write cycle, any consecutive attempts to read dq6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. when the write cycle is com- pleted, the toggling will stop. the device is then ready for the next operation. see figure 25 for toggle bit timing diagram. the initial read of the toggle bit will be a 1. data protection the ad73560 provides both hardware and software fea- tures to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a wr or bms pulse of less than 5 ns will not initiate a write cycle. vdd power up/down detection: the write operation is inhibited when vdd is less than 2.5v. write inhibit mode: forcing rd low, bms high, or wr high will inhibit the write operation. this prevents inad- vertent writes during power-up or power-down. software data protection (sdp) the ad73560 flash-memory provides the jedec ap- proved optional software data protection scheme for all data alteration operations, i.e., write and chip erase. with this scheme, any write operation requires the inclusion of a series of three byte-load operations to precede the data loading operation. the three byte-load sequence is used to initiate the write cycle, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. the ad73560 is shipped with the software data protection disabled. the software pro- tection scheme can be enabled by applying a three-byte sequence to the device, during a page-load cycle (figures 22 and 23). the device will then be automatically set into the data protect mode. any subsequent write operation will require the preceding three-byte sequence. see fig- ures 22 and 23 for the timing diagrams. to set the device into the unprotected mode, a six-byte sequence is re- quired. see figure 26 for the timing diagram. if a write is attempted while sdp is enabled the device will be in a non-accessible state for ~ 300 s. it is recommended that software data protection always be enabled. the ad73560 software data protection is a global com- mand, protecting (or unprotecting) all pages in the entire memory array once enabled (or disabled). therefore us- ing sdp for a single page write will enable sdp for the entire array. single pages by themselves cannot be sdp enabled or disabled. single power supply reprogrammable nonvolatile memories may be uninten- tionally altered. sst strongly recommends that software data protection (sdp) always be enabled. the ad73560 should be programmed using the sdp command se- quence. it is recommended that the sdp disable com- mand sequence not be issued to the device prior to writing.
rev. pra preliminary technical data ad73560 C33C preliminary technical data software chip-erase the ad73560 provides a flash-erase operation, which allows the user to simultaneously clear the entire flash- memory array to the 1 state. this is useful when the entire flash memory must be quickly erased. the software flash-erase operation is initiated by using a specific six byte-load sequence. after the load sequence, the device enters into an internally timed cycle similar to the write cycle. during the erase operation, the only valid read is toggle bit. see figure 27 for timing diagram. figure 21. read cycle timing figure 22. wr controlled page mode write cycle timing address a 15-0 ce (bms) we (wr) oe (rd) db 7-0 high-z v ih t clz t olz data valid t oh t ce t oe t rc t aa t ohz t chz data valid address a 15-0 ce (bms) we (wr) oe (rd) db 7-0 5555 2aaa 5555 three byte sequence for enabling sdp t as t ah t cs t oes t ch t oeh t blc t wp aa a0 55 sw0 sw1 sw2 byte 0 byte 1 byte 127 t ds t dh data valid t wc t blco
rev. pra ad73560 C34C preliminary technical data ce (bms) we (wr) oe (rd) 5555 5555 2aaa address a 15-0 db 7-0 aa 55 a0 sw0 sw1 sw2 t oes t cs byte 0 t ds t dh t ch t oeh t blc byte 1 byte 127 data valid t wc t blco three byte sequence for enabling sdp t as tah t cp figure 23. bms controlled page mode write cycle timing ce (bms) we (wr) oe (rd) db 7-0 address a 15-0 t oeh t ce t oe t oes dd# t wc + t blco d# d figure 24. data/polling timing
rev. pra preliminary technical data ad73560 C35C preliminary technical data address a 15-0 ce (bms) we (wr) oe (rd) db7-0 t ce t oeh t oe t wc + t blco two read cycles with same outputs t oes figure 25. toggle bit timing address a 15-0 ce (bms) we (wr) oe (rd) db 7-0 six-byte sequence for disabling software data protection 5555 2aaa 5555 5555 2aaa 5555 t wc aa 55 80 aa 55 20 t wp t blc sw0 sw1 sw2 sw3 sw4 sw5 tblco figure 26. software data protection disable timing
rev. pra ad73560 C36C preliminary technical data address a 15-0 ce (bms) we (wr) oe (rd) db 7-0 sw0 sw1 sw2 sw3 sw4 sw5 t blc t wp six-byte code for software chip erase 5555 2aaa 5555 5555 2aaa 5555 aa 55 80 aa 55 10 t sce t blco figure 27. software flash-memory erase timing analog front end (afe) interfacing the afe section of the ad73560 features 6 input chan- nels each with 16-bit linear resolution. connectivity to the afe section from the dsp is uncommitted thus allowing the user the flexibility of connecting in the mode or con- figuration of their choice. this section will detail several configurations - with no extra afe channels configured and with an extra afe section configured (using an exter- nal ad73360 afe). dsp sport to afe interfacing the sclk, sdo, sdofs, sdi and sdifs must be connected to the sclk, dr, rfs, dt and tfs pins of the dsp respectively. the se pin may be controlled from a parallel output pin or flag pin such as fl0C2 or, where sport power-down is not required, it can be perma- nently strapped high using a suitable pull-up resistor. the areset pin may be connected to the system hardware reset structure or it may also be controlled using a dedi- cated control line. in the event of tying it to the global system reset, it is necessary to operate the device in mixed mode, which allows a software reset, otherwise there is no convenient way of resetting the device. tfs dt sclk dr rfs dsp section afe section sdifs sdi sclk sdo sdofs fl0 fl1 areset se figure 24. ad73560 afe to dsp connection cascade operation where it is required to configure extra analog input chan- nels to the existing six channels on the ad73560 it is possible to cascade up to 42 more channels (using external ad73360 afes) by using the scheme described in fig- ure 26. it is necessary however to ensure that the timing of the se and reset signals is synchronized at each device in the cascade. a simple d type flip-flop is sufficiend to sync each signal to the master clock mclk as shown in 25.
rev. pra preliminary technical data ad73560 C37C preliminary technical data 1/2 74hc74 clk dq dsp control to se mclk se signal synchronized to mclk 1/2 74hc74 clk dq dsp control to areset mclk areset signal synchronized to mclk figure 25 se and reset sync circuit for cascaded operation there may be some restrictions in cascade operation due to the number of devices configured in the cascade and the serial clock rate chosen. the formula below gives an indi- cation of whether the combination of sample rate, serial clock and number of devices can be successfully cascaded. this assumes a directly coupled frame sync arrangement as shown in figure 24 and does not take any interrupt latency into account. 1 f s 3 6 [(( devicecount - 1) 16 ) + 17] sclk when using the indirectly coupled frame sync configura- tion in cascaded operation it is necessary to be aware of the restrictions in sending control word data to all devices in the cascade. the user should ensure that there is suffi- cient time for all the control words to be sent between reading the last adc sample and the start of the next sample period. connection of a cascade of devices to a dsp, as shown in figure 26, is no more complicated than connecting a single device. instead of connecting the sdo and sdofs to the dsps rx port, these are now daisy-chained to the sdi and sdifs of the next device in the cascade. the sdo and sdofs of the final device in the cascade are connected to the dsps rx port to complete the cascade. se and reset on all devices are fed from the signals that were synchronized with the mclk using the circuit of figure . the sclk from only one device need be con- nected to the dsps sclk input(s) as all devices will be running at the same sclk frequency and phase. tfs dt dr rfs afe sdifs sdi sclk sdo sdofs sclk device 1 mclk se reset additional ad73360 afe 74hc74 q0 q1 d1 d0 fl0 fl1 dsp section clk sdifs sdi sclk sdo sdofs device 2 mclk se reset figure 26. connection of an ad73360 cascaded to the ad73560 interfacing to the ades analog inputs the ad73560 features six signal conditioning inputs. each signal conditioning block allows the ad73560 to be used with either a single-ended or differential signal. the applied signal can also be inverted internally by the ad73560 if required. the analog input signal to the ad73560 can be dc-coupled, provided that the dc bias level of the input signal is the same as the internal refer- ence level (refout). figure 27 shows the recom- mended differential input circuit for the ad73560. the circuit of figure 27 implements first-order low-pass filters vin to input bias circuitry vinpx vinnx refout refcap voltage reference 0.047 m f 100 v 100 v cin cin 10k v 10k v 0.047 m f 0.1 m f figure 27. example circuit for differential input (dc coupling) with a 3 db point at 34 khz; these are the only filters that must be imple mented external to the ad73560 to pre- vent aliasing of the sampled signal. since the adc uses a highly oversampled approach that transfers the bulk of the antialiasing filtering into the digital domain, the off-chip antialiasing filter need only be of a low order. it is recom- mended that for optimum performance the capacitors used for the antialiasing filter be of high quality dielectric (npo).
rev. pra ad73560 C38C preliminary technical data the ad73560s on-chip 38 db preamplifier can be en- abled when there is not enough gain in the input circuit for a particular channel; the preamplifier is configured by bits ixgs0C2 of crd to crf. the total gain must be configured to ensure that a full-scale input signal pro- duces a signal level at the input to the sigma-delta modu- lator of the adc that does not exceed the maximum input range. the dc biasing of the analog input signal is accomplished with an on-chip voltage reference. if the input signal is not biased at the int ernal reference level (via refout), then it must be ac- coupled with external coupling capacitors. cin should be 0.1 f or larger. the dc biasing of the input can then be accomplished using resistors to refout as in figure 28. vin to input bias circuitry vinpx vinnx refout refcap voltage reference 0.047 m f 100 v 100 v cin cin 10k v 10k v 0.047 m f 0.1 m f figure 28. example circuit for differential input (ac coupling) figures 29 and 20 detail ac- and dc-coupled input circuits for single-ended operation respectively. vin vinpx vinnx refout refcap voltage reference 100 v cin 10k v 0.047 m f 0.1 m f figure 29. example circuit for single-ended input (ac coupling) vin vinpx vinnx refout refcap voltage reference 100 v 0.047 m f 0.1 m f figure 30. example circuit for differential input (dc coupling) digital interface as there are a number of variations of sample rate and clock speeds that can be used with the ad73560 in a par- ticular application, it is important to select the best com- bination to achieve the desired performance. high speed serial clocks will read the data from the ad73560 in a shorter time, giving more time for processing by at the expense of injecting some digital noise into the circuit. digital noise can also be reduced by connecting resistors (typ <50 y) in series with the digital input and output lines. the noise can be minimized by good grounding and layout. typically the best performance is achieved by se- lecting the slowest sample rate and sclk frequency for the required application as this will produce the least amount of digital noise. figure 31 shows combinations of sample rate and sclk frequency which will allow data to be read from all six channels in one sample period. these figures correspond to setting dmclk = mclk. vin to input bias circuitry vinpx vinnx refout refcap voltage reference 0.047 m f 100 v 100 v cin cin 10k v 10k v 0.047 m f 0.1 m f figure 31. sclk and sample rates
rev. pra preliminary technical data ad73560 C39C preliminary technical data outline dimensions dimensions shown in inches and (mm). a b c d e f g h j k l m n p r t u 7 6 5 4 3 2 1 0.050 (1.27) bsc 0.800 (20.32) bsc 0.300 (7.62) bsc 0.050 (1.27) bsc 0.126 (3.19) ref 0.033 (0.84) ref bottom view a1 top view 0.874 (22.20) 0.858 (21.80) 0.559 (14.20) 0.543 (13.80) 0.089 (2.27) 0.073 (1.85) detail a seating plane 0.037 (0.95) 0.033 (0.85) 0.028 (0.70) 0.020 (0.50) detail a 0.035 (0.90) 0.024 (0.60) ball diameter 0.022 (0.56) ref 119 ball plastic ball grid array (pbga) b-119

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