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YGV638 vc2 video controller 2 YGV638 catalog catalog no. lsi-4gv638a21 2011.03 overview YGV638 (hereinafter called ?vc2?) is a pattern graphic controller with an on-chip vram and the ample drawing performance enables high -resolution animated guis on wvga display panels. vc2?s multiple video ports allow direct hand ling of video signals from various sources: dvd players, car navigation system s, rear view cameras, etc. in addition, vc2 is capable of superimposing characters, lines, and even graphic icons or menu screens (hereinafter called ?s prite?) onto these videos. with conventional graphic controllers, compli cated display control programs need to be developed. with vc2, sprites can be used to simplify the programs as all the controls of a sprite is available in its 12-byte attribute: position, s caling factor, transparency , color gradation, etc. vc2 integrates image de-compression engine (yamaha proprietary algorithm) to dynamically decompress the sprite data stored in its external memory (flash rom etc.) achieving substantial memory capacity savings. vc2, with the features above, allows display systems for in-vehicle av equipments, audio equipments with display to be built with low-cost components.
features YGV638 4gv638a21 2 features display function video output monitor supported: tft liquid crystal display (digital rgb connection) or compatible display equipments digital rgb666, digital rgb666+frc, digital rgb888 supports ntsc, pal, qvga, wqvga, vga, wvga, and svga supports interlace and progressive scans supports display timings in 1 dot and in 1 line resolution equalizing pulse insertion for composite sync signals dot clock polarity selection sync signal polarity selection gamma correction function (look-up table based) on-chip lcd timing controller display plane functions up to 341 planes (up to 128 planes per scan line) and one external video plane a layer displays either sprites, lines or texts alpha-blending between layers alpha-blending between layer and external video picture attribute controls by layers (contrasts, brightness) layer function sprite displaying up to 341 sprites per screen and up to 128 sprites per scan line specified by horizontal and vertical coordinates sizes from 8 dot 8 dot to 1024 dot 1024 dot. horizontal and vertical scaling independently selectable (in 8-dot unit) 2, 16, 64, or 256 palette colors from 16m colors, or 64k colors with 16-bit rgb, 256k colors with 18-bit rgb, and 16m colors, life-like picture quality with 24-bit rgb scaling function anti-aliasing of the outline profile on-chip palettes with 1024 colors (combinations of 2 color palettes, 16 color palettes, 64 color palettes, and 256 color palettes up to 1024 colors in total)
features YGV638 4gv638a21 3 text displaying up to 1948 characters per screen and up to 128 characters per scan line independent font selections for each character strings supports proportional font supports half-width font scaling function supports 4-bit/pixel anti-aliasing font font size: 1 dot 1 dot to 64 dot 64 dot in increments of 1-dot independently in horizontal and vertical direction line line drawn directly from specifications of start/end point coordinates up to 510 lines per screen 32768-color (rgb555) specification or palette index (10 bits) specification line width: from 1 dot to 16 dots (in one dot increments) anti-aliasing drawing function video signal inputs analog video input compatible with composite video, s video, component video, and rgb signal inputs on-chip three 10bit-adcs compatible with ntsc and pal signal formats on-chip video decoder supports interlace and progressive scans (rgb) compatible with composite sync signal inputs (rgb) digital video input compatible with rgb666, 16bit ycrcb, and 8bit ycrcb (itu-r bt.656) compatible with interlace and progressive scans compatible with composite sync signal inputs video image processing scaling (the input images scaled to fit the display resolution, not a zooming function) mirror flipping (through vertical axis) external sync mode (or free-running mode: switchable)
features YGV638 4gv638a21 4 video decoder on-chip high-quality y/c separation circuit (2d adaptive comb filter) digital agc circuit image color controls contrast brightness color hue chroma saturation color killer function other features cpu interface serial or 8-bit parallel connection indirect accesses to internal register s and tables through single access port flexible asynchronous bus interface macro command function pattern memory interface bus width of 32 bits, or 16 bits up to 512 mbits (64 mb) memory supports mask-rom, nor-type flash-memory, sram, or compatible timing memories supports page mode accesses access timings in multiples of the system clock cycle device specifications lead-free 208-pin lqfp package (YGV638-vz) supply voltages: 3.3v and 1.8v cpu interface power supply 3.3v operating temperature range from -40 to +85
pin attributes YGV638 4gv638a21 5 pin attributes pin name num. i/o function attribute drive cpu interface (22) d7-0 8 i/o cpu data bus tolerant 4ma ps2-0 3 i cpu port selection tolerant cs_n 1 i chip select (dua l-purpose pin) tolerant rd_n 1 i read strobe (dual-purpose pin) tolerant wr_n 1 i write strobe (dual-purpose pin) tolerant wait_n 1 ot cpu bus wait (dual-purpose pin) tolerant 4ma ready_n 1 ot cpu bus ready tolerant 4ma int_n 1 od interrupt tolerant 4ma ser_n 1 i cpu interface selection scs_n 1 i serial interface chip se lect (dual-purpose pin) tolerant sdin 1 i serial interface data i nput (dual-purpose pin) tolerant sclk 1 i serial interface clocked into (dual-purpose pin) tolerant sdout 1 ot serial interface data out put (dual-purpose pin) tolerant 4ma pattern memory interface (60) md31-0 32 i/o pattern memory data bus 4ma ma25-1 25 ot pattern memo ry address bus 4ma moe_n 1 ot pattern memo ry output enable 4ma mwe_n 1 ot pattern memory write pulse 4ma rahz_n 1 i pattern memory high-im pedance switching pin tolerant video input (58) acin1 1 i analog composite video input analog acin2 1 i analog composite video input analog arin 1 i analog video r input analog agin 1 i analog video g input analog abin 1 i analog video b input analog atestin 1 i test input analog vref0 1 o adc reference analog vrefp 1 o plus reference voltage for adc analog vrefn 1 o minus reference voltage for adc analog adckin 1 i analog video clock input tolerant arckin 1 i analog video clock input tolerant avsin_n 1 i analog video vertical sync signal input tolerant ahsin_n 1 i analog video horizontal sync signal input tolerant dri7-2 6 i digital video r input (dual-purpose pin) tolerant dgi7-2 6 i digital video g input (dual-purpose pin) tolerant dbi7-2 6 i digital video b input (dual-purpose pin) tolerant din7-0 8 i digital video 8bit ycrcb input (dual-purpose pin) tolerant yin7-0 8 i digital video y input (dual-purpose pin) tolerant cin7-0 8 i digital video cr/cb input (dual-purpose pin) tolerant dvsin_n 1 i digital video vertical sync signal input tolerant dhsin_n 1 i digital video horizontal sync signal input tolerant dgckin 1 i digital video clock input tolerant
pin attributes YGV638 4gv638a21 6 monitor interface (34) dro7-0 8 o digital video: r output 4ma dgo7-0 8 o digital vi deo: g output 4ma dbo7-0 8 o digital video: b output 4ma vsync_n 1 ot vertical sync signal ou tput (dual-purpose pin) tolerant 4ma hcsync_n 1 ot horizontal sync signal or composite sync signal output (dual-purpose pin) tolerant 4ma blank_n 1 ot display timi ng output (dual-purpose pin) tolerant 4ma starth 1 ot horizontal star t signal output tolerant 4ma loadh 1 ot horizontal load signal output tolerant 4ma clkv 1 ot vertical clock output (dual-purpose pin) tolerant 4ma startv 1 ot vertical start signal ou tput (dual-purpose pin) tolerant 4ma pol 1 ot polarity reverse output (dual-purpose pin) tolerant 4ma outenv 1 ot output enable signal for a gate driver output tolerant 4ma dotclk 1 o dot clock output 4ma clock & reset (8) xin 1 i reference clock input xout 1 o crystal connection dtckin 1 i dot clock input tolerant pllctl3-0 4 i pll control reset_n 1 i$ reset tolerant for device (56) xtest2-0 3 i test pin vdd33 17 digital i/o power supply vss 19 digital i/o vss pllvdd 1 power supply for system clock generation pll pllvss 1 vss for system clock generation pll apllvdd 1 power supply for analog rgb clock generation pll apllvss 1 vss for analog rgb clock generation pll avdd33 1 power supply for analog front end avdd18 2 power supply for analog front end avss 2 vss for analog front end vdd18 4 power supply for digital core vss18 4 vss for digital core others (1) nc 1 no connection pin total number of pins: 239 pin - 31 dual-purpose pin = 208 pins [description of i/o] i: input i$: input with schmitt trigger i/o: input and output o: output ot: 3-state output od: open-drain output [description of attribute] tolerant: an attribute of an input pin buffer and a bidirectional pin buffer, or the output pin buffer. during high impedance states, current will not flow into power supply pins from a pin when some voltage higher than the i/o supply voltage is applied to the pin, if the pin is ?tolerant.? analog: attribute which indicates an analog pi n. these pins are operated from avdd33 power supply.
pin attributes YGV638 4gv638a21 7 sharing pins on vc2, - the cpu interface pins change functions depending on which cpu interface, parallel or serial, is used. - the digital video input pins change functions depending on the digital video input format used. - the monitor interface pins change functions when the integrated lcd timing controller is used. i) sharing of cpu interface pins the vc2 supports the 8-bit parall el interface or serial interface. the correspondence between cpu interface and the shared pin is as follows. pin name parallel interface (ser_n=h) serial interface (ser_n=l) d7-0 d7-0 not used (fixed to ?h? or ?l?) ps2-0 ps2-0 not used (fixed to ?h? or ?l?) cs_n cs_n scs_n rd_n rd_n sdin wr_n wr_n sclk wait_n wait_n sdout ready_n ready_n not used (n.c.) int_n int_n int_n ii) sharing of digital video input pins vc2 supports the digital video input of rgb666, 16bit ycrcb, and 8bit ycrcb format. the correspondence between the format of digital video and the pins are as follows. pin name rgb666 (dvif=2?b00) 8bit ycrcb (dvif=2?b01) 16bit ycrcb (dvif=2?b10) dri2 dri2 not used cin0 dri3 dri3 not used cin1 dri4 dri4 not used cin2 dri5 dri5 not used cin3 dri6 dri6 not used cin4 dri7 dri7 not used cin5 dgi2 dgi2 not used cin6 dgi3 dgi3 not used cin7 dgi4 dgi4 not used not used dgi5 dgi5 not used not used dgi6 dgi6 din0 yin0 dgi7 dgi7 din1 yin1 dbi2 dbi2 din2 yin2 dbi3 dbi3 din3 yin3 dbi4 dbi4 din4 yin4 dbi5 dbi5 din5 yin5 dbi6 dbi6 din6 yin6 dbi7 dbi7 din7 yin7 dgckin dgckin dgckin dgckin dvsin_n dvsin_n not used dvsin_n dhsin_n dhsin_n not used dhsin_n pull up the ?not used? pins to ?h? or ?l? outside the device.
pin attributes YGV638 4gv638a21 8 iii) sharing of monitor interface pins vc2 has an on-chip lcd timing controller. the function of the following pins depends on whether or not the timing controller is used, as shown below: pin name timing controller not used (tcone=0) timing controller used (tcone=1) dro7-0 dro7-0 dro7-0 dgo7-0 dgo7-0 dgo7-0 dbo7-0 dbo7-0 dbo7-0 dotclk dotclk dotclk hcsync_n hcsync_n clkv vsync_n vsync_n pol blank_n blank_n startv loadh not used loadh starth not used starth outenv not used outenv pin assignments pllvdd pllvss dtckin adckin xin xout xtest1 xtest0 xtest2 pllctl3 pllctl2 pllctl1 pllctl0 reset_n cs_n wr_n rd_n ps2 ps1 ps0 avdd33 avdd18 avss d0 d1 d2 d3 d4 d5 d6 d7 wait_n ready_n int_n arckin avsin_n ahsin_n acin1 acin2 arin vrefp vrefn vref0 agin 2 53 208 52 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 1 50 51 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 104 103 102 101 100 99 98 97 105 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 138 137 136 135 134 133 132 131 130 139 128 127 126 125 124 123 122 121 120 129 118 117 116 115 114 113 112 111 110 119 108 107 106 109 207 206 205 204 203 202 201 200 198 197 196 195 194 193 192 191 190 199 188 187 186 185 184 183 182 181 180 189 178 177 176 175 174 173 172 171 170 179 168 167 166 165 164 163 162 161 160 169 158 157 159 vss vss vss vss vss vss vdd33 vdd33 vdd33 vdd33 vdd18 vss18 vdd33 vss vss vss vss vdd33 vdd33 vdd33 vdd18 vss18 avdd18 avss vdd33 vdd33 vdd33 vdd33 vss vss vss vss vss18 vdd18 vdd33 vss vdd18 vss18 vss vss vss vdd33 vdd33 vdd33 vdd33 abin atestin dgckin dvsin_n dhsin_n dri2 dri3 dri4 dri5 dri6 dri7 dgi2 dgi3 dgi4 dgi5 dgi6 dgi7 dbi2 dbi3 dbi4 dbi5 dbi6 dbi7 md31 md23 md30 md29 md28 md27 md26 md25 md24 md22 md21 md20 md19 md18 md17 md16 md15 md14 md13 md12 md11 md10 md9 md8 md7 md6 md5 md4 md3 md2 md1 md0 ma25 ma24 ma23 ma22 ma21 ma20 ma19 ma18 ma17 ma16 ma15 ma14 ma13 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 vss mwe_n moe_n ser_n outenv starth loadh blank_n hcsync_n vsync_n dotclk dbo7 apllvss apllvdd rahz_n dbo6 dbo5 dbo4 dbo3 dbo2 dbo1 dbo0 dgo7 dgo6 dgo5 dgo4 dgo3 dgo2 dgo1 dgo0 dro7 dro6 dro5 dro4 dro3 dro2 dro1 dro0 nc <208pin lqfp top view>
pin attributes YGV638 4gv638a21 9 pin names # pin name # pin name # pin name # pin name 1 pllvdd 53 abin 105 ma1 157 md1 2 dtckin 54 atestin 106 ma2 158 md8 3 adckin 55 avss 107 vss 159 md0 4 vss 56 avdd18 108 ma3 160 vss 5 xin 57 avdd33 109 ma4 161 rahz_n 6 xout 58 vss 110 ma5 162 apllvdd 7 vdd33 59 dgckin 111 ma6 163 nc 8 xtest0 60 dvsin_n 112 vdd33 164 apllvss 9 xtest1 61 dhsin_n 113 ma7 165 vss 10 xtest2 62 dri2 114 ma8 166 dro0 11 pllctl3 63 dri3 115 ma9 167 dro1 12 pllctl2 64 dri4 116 ma10 168 dro2 13 pllctl1 65 vdd33 117 vss 169 vdd33 14 pllctl0 66 dri5 118 ma11 170 dro3 15 reset_n 67 dri6 119 ma12 171 dro4 16 vss 68 dri7 120 ma13 172 dro5 17 cs_n 69 dgi2 121 ma14 173 dro6 18 wr_n 70 vss 122 vdd33 174 vss 19 rd_n 71 dgi3 123 ma15 175 dro7 20 vdd33 72 dgi4 124 ma16 176 dgo0 21 ps2 73 dgi5 125 ma17 177 dgo1 22 ps1 74 dgi6 126 ma18 178 dgo2 23 ps0 75 dgi7 127 vss 179 vdd33 24 vss18 76 vdd33 128 ma19 180 dgo3 25 d0 77 dbi2 129 vdd18 181 vdd18 26 vdd18 78 dbi3 130 ma20 182 dgo4 27 d1 79 vdd18 131 vss18 183 vss18 28 vdd33 80 dbi4 132 ma21 184 dgo5 29 d2 81 vss18 133 ma22 185 dgo6 30 d3 82 dbi5 134 vdd33 186 vss 31 vss 83 dbi6 135 ma23 187 dgo7 32 d4 84 vss 136 ma24 188 dbo0 33 d5 85 dbi7 137 ma25 189 dbo1 34 d6 86 md31 138 mwe_n 190 dbo2 35 d7 87 md23 139 moe_n 191 vdd33 36 vdd33 88 md30 140 vss 192 dbo3 37 wait_n 89 vdd33 141 md15 193 dbo4 38 ready_n 90 md22 142 md7 194 dbo5 39 int_n 91 md29 143 md14 195 dbo6 40 arckin 92 md21 144 vdd33 196 dbo7 41 avsin_n 93 md28 145 md6 197 vss 42 ahsin_n 94 md20 146 md13 198 dotclk 43 vss 95 vss 147 md5 199 vsync_n 44 avdd18 96 md27 148 md12 200 hcsync_n 45 avss 97 md19 149 vss 201 blank_n 46 acin1 98 md26 150 md4 202 vdd33 47 acin2 99 md18 151 md11 203 loadh 48 arin 100 md25 152 md3 204 starth 49 vrefp 101 vdd33 153 md10 205 outenv 50 vrefn 102 md17 154 md2 206 ser_n 51 vref0 103 md24 155 vdd33 207 vss 52 agin 104 md16 156 md9 208 pllvss
block diagram YGV638 4gv638a21 10 block diagram sprite rendering processor sprite & line plane generator pixel data controller monitor i/f dro7-0 dgo7-0 dbo7-0 hcsync_n vs ync_n blank_n dotclk clkv starth startv loadh pol outenv crtc general table color palette registers pattern memory interface clock generator cpu interface clo ck xin xout dtckin pllctl3-0 pattern memory i/f md31-0 ma25-1 moe_n mwe_n rahz_n cpu i/f d7-0 ps2-0 cs_n rd_n wr_n wa i t _ n ready_n int_n sdin sdout scs_n sclk ser_n f line buffer to al l blocks video input analog acin1 acin2 arin agin abin avsin_n ahsin_n vrefp vrefn vref0 adckin arckin digital dri7-2 dgi7-2 dbi7-2 dvsin_n dhsin_n dgckin analog front end video decoder input video signal controller to all blocks pattern data decoder line rendering processor analog video controller
block diagram YGV638 4gv638a21 11 typical applications vc2 stand-alone system typical display contents: dashboard instruments or vehicle information and alarms vc2 lcd pattern memory (flash rom) cpu osd system for video camera images typical display contents: dashboard instruments or vehicle information and alarms, blind spot monitor, night view cvbs vc2 lcd pattern memory (flash rom) cpu camera module
block diagram YGV638 4gv638a21 12 av + video camera images typical display contents: dashboard instruments and vehicle information, blind spot monitor, hmi (air-conditioner, audio), dvd, tv, aux cvbs vc2 lcd pattern memory (flash rom) cpu dvd module t v module camera module cvbs cvbs cvbs video camera add-ons for car navigation systems typical display contents: dashboard instruments and vehicles information, blind spot monitor, hmi (air-conditioner, audio), car navigation system, video cvbs vc2 lcd pattern memory (flash rom) cpu camera module digital rgb navigation module analog rgb or
electrical characteristics YGV638 4gv638a21 13 electrical characteristics absolute maximum ratings items symbol ratings unit note power supply voltage (vdd33 pin) v dd33 -0.5 to +4.6 v 1 power supply voltage (vdd18 pin) v dd18 -0.5 to +2.5 v 1 analog power supply voltage (avdd33 pin) v avd33 -0.5 to +4.6 v 1 analog power supply voltage (avdd18 pin) v avd18 -0.5 to +2.5 v 1 pll power supply voltage (pllvdd, apllvdd pin) v plvd -0.5 to +2.5 v 1 input pin voltage (tolerant pin) v i -0.5 to vdd33+4.6 ( 5.5 max) v 1 input pin voltage (analog pin) v i -0.5 to avdd+0.5 ( 4.6 max) v 1 input pin voltage (other pin) v i -0.5 to vdd33+0.5 ( 4.6 max) v 1 output pin voltage (tolerant pins including i/o pins) v o -0.5 to vdd33+4.6 ( 5.5 max) v 1 output pin voltage (analog pins including i/o pins) v o -0.5 to avdd+0.5 ( 4.6 max) v 1 output pin voltage (other pins including i/o pins) v o -0.5 to vdd33+0.5 ( 4.6 max) v 1 input pin current i i -20 to +20 ma output pin current i o -20 to +20 ma storage temperature t stg -50 to +125 note 1) voltage relative to v ss =0v. recommended operating condition items symbol min. typ. max. unit note power supply voltage (vdd33 pin) v dd33 3.0 3.3 3.6 v 1 power supply voltage (vdd18 pin) v dd18 1.65 1.8 1.95 v 1 analog power supply voltage (avdd33 pin) v avd33 3.0 3.3 3.6 v 1 analog power supply voltage (avdd18 pin) v avd18 1.65 1.8 1.95 v 1 pll power supply voltage (pllvdd, apllvdd pin) v plvd v apvd 1.65 1.8 1.95 v 1 operating ambient temperature t op -40 85 2 note 1) voltage relative to v ss =0v. note 2) the ambient temperature of 85 is the value measured u nder the following conditions: four-layer board with over 300% copper trace coverage current consumption items conditions symbol min. typ. max. unit note total power consumption p d 766 mw 1 current consumption by supply voltage vdd18 (including pllvdd, apllvdd) i vd18 192 ma 1, 2 vdd33 i vdd33 40 ma 1 avdd33 i avd33 20 ma 1 avdd18 c l =20pf v il =gnd v ih =v dd33 i avd18 90 ma 1 note 1) current consumption value an d power consumption value are the va lues under the recommended operating condition. note 2) pllvdd and apllvdd are internally connected to vdd18.
electrical characteristics YGV638 4gv638a21 14 dc characteristics items symbol min. typ. max. unit note low level input voltage (xin pin) v il -0.3 0.3v dd33 v 1 low level input voltage (except xin pin) v il -0.3 0.8 v 1 high level input voltage (xin pin) v ih 0.7v dd33 v dd33 +0.3 v 1 high level input voltage (reset_n pin) v ih 2.2 5.5 v 1, 2 high level input voltage (tolerant pin other than reset_n) v ih 2.0 5.5 v 1, 2 high level input voltage (except the above) v ih 2.0 v dd33 +0.3 v 1 note 1) voltage relative to v ss =0v. note 2) 5.5v can be applied to the tolerant pin when the supply voltage is within the range of the recommended operating voltage; however, up to 3.6v when the power is not applied. items conditions symbol min. typ. max. unit note i ol =100 av ol 0 0.2 v 1 low level output voltage (except xout pin) i ol =2ma v ol 0 0.4 v 1 i oh = -100 av oh v dd33 -0.2 v dd33 v 1 high level output voltage (except xout pin) i oh = -2ma v oh 2.4 v dd33 v 1 input leak current i li -10 +10 a output leak current i lo -25 +25 a note 1) voltage relative to v ss =0v. items symbol min. typ. max. unit note analog video input voltage (acin1, acin2 pins) v acin 1.25 1.4 vp-p 1 analog video input voltage (arin, agin, abin pins) v arin 0.7 1.4 vp-p 1 note 1) the above maximum value is for the setting of ?r#021h: adc*gain=2?b00.? items symbol min. typ. max. unit note input pin capacitance c i 10 pf output pin capacitance c o 10 pf input-output pin capacitance c io 10 pf
electrical characteristics YGV638 4gv638a21 15 ac characteristics ac characteristic is a value under the following conditions unless otherwise noted. input signal measurement condition: input voltages 0v / v dd33 input transition time (tr,tf) 1ns (provide for the transition time between 10% and 90% of the input voltage.) input measurement reference voltage 0.5v dd33 t f t r 0.9v dd33 0.1v dd33 0.5v dd33 0.9v dd33 0.1v dd33 0.5v dd33 gnd v dd33 gnd v dd33 measurement reference voltage measurement reference voltage input signal input signal output signal measurement condition output measurement reference voltage 0.5v dd33 (in neither 3-state output pin nor input output pins, even when it changed to high impedance, an output wave changes; therefore, i/o cell specifies the transition to high impedance to the timing, being as a disable state.) hi-z hi-z 0.5v dd33 0.5v dd33 gnd v dd33 measurement measurement output si g nal 3-state output signal gnd v dd33 measurement point gnd v dd33 measurement point 3-state output signal
electrical characteristics YGV638 4gv638a21 16 output load capacitance 20pf 20pf output pin clock input no. items symbol min. typ. max. unit note xin, dtckin, dgckin: clock frequency f ck 6 40 mhz 1 1 xin, dtckin, dgckin: clock cycle time t cck 25 166 ns 2 xin, dtckin, dgckin: clock high level pulse width t whck 7.5 ns 3 xin, dtckin, dgckin: clock low level pulse width t wlck 7.5 ns adckin: clock frequency f ad 20 28 mhz 4 adckin: clock cycle time t cad 35.7 50 ns 5 adckin: clock high level pulse width t whad 14.29 ns 6 adckin: clock low level pulse width t wlad 14.29 ns arckin: clock frequency f ar 6 40 mhz 7 arckin: clock cycle time t car 25 166 ns 8 arckin: clock high level pulse width t whar 10 ns 9 arckin: clock low level pulse width t wlar 10 ns syclk: clock frequency f sy 63 84 mhz 2 10 syclk: clock cycle time t csy 11.90 15.88 ns 2 dclk: clock frequency f dt 6 40 mhz 2 11 dclk: clock cycle time t cdt 25 166 ns 2 note 1) the maximum of the oscillation frequency between xin-xout is 30 mhz. note 2) syclk, dclk is the internal clock. xin dtckin dgckin t cck t whck t wlck v ih 0.5vdd33 v i l v il v ih 0.5vdd33
electrical characteristics YGV638 4gv638a21 17 adckin t cad t whad t wlad v ih 0.5vdd33 v i l v il v ih 0.5vdd33 arckin t car t whar t wlar v ih 0.5vdd33 v i l v il v ih 0.5vdd33 power supply and reset input no. items symbol min. typ. max. unit note 1 reset_n: input time t wres 10 s1 2 cpu access stand-by time after reset_n negation t waw 1 to 6.7 ms 2 3 reset_n: setup time t sres 0 ns 3 4 power-on time difference t vskwr 1 s 4 5 power-off time difference t vskwf 1 s 5 6 power rise time t vrise 200 ms note 1) the time from a point where a power supply power ed up last vdd33 reaches at 3.0v, and vdd18 reaches at 1.7v, and the input clock to the xin pin becomes stable. note 2) it is necessary to wait to access for 40000 t_ xin time (cycle of the clock inputted into xin pin) after reset_n negation as pll lock-up time. note 3) the specified value of vdd which is raised up the earliest. note 4) it is preferable to turn on vdd33, vdd18, avdd33, avdd18, pllvdd, and apllvdd at the same time. if 1 second or more time-difference occurs among their power-on, it may affect the lsi?s reliability. note 5) it is preferable to turn off vdd33, vdd18, avdd33, avdd18, pl lvdd, and apllvdd at the same time. if 1 second or more time-difference occurs among their power-off, it may affect the lsi?s reliability.
electrical characteristics YGV638 4gv638a21 18 vdd33 av d d 3 3 vdd18 av d d 1 8 pllvdd apllvdd reset_n cs_n xin vdd33 av d d 3 3 vdd18 av d d 1 8 pllvdd apllvdd 3.0v 3.0v 1.65v t vskwr t vrise t vrise 3.0v t waw t wres t sr es t wres t waw t vskwf 1.7v t wres 1.7v t vskwf cpu interface i) parallel interface no. items symbol min. typ. max. unit note 1 ps2-0: setup time tsa 4 1 2 ps2-0: hold time tha 0 1 3 cs_n: setup time tscs 0 2 4 cs_n: hold time t hcs 0 2 5 d7-0: output data turn on time t ond 0 6 d7-0: output data turn off time t offd 30 7 d7-0: output data valid delay time t dd 0 8 d7-0: output data hold time t hd 0 9 wait_n, ready_n: turn on time t onwait 0 10 wait_n: valid delay time t dwait 25 11 wait_n, ready_n: turn off time t offwait 30 12 d7-0: input data setup time t sd t csy +15 13 d7-0: input data hold time t hd 0 14 wr_n: hold time t hwr 0 15 ready_n: hold time t hready 0 30 16 command pulse active time t acmd 2 t csy 3 17 command pulse inhibit time t icmd 4 t csy 3 18 command cycle time t ccmd 6 t csy ns 3 note 1) specified values for wr_n and rd_n signals; however, in cs_n control, there are specified values for cs_n. note 2) conditions that prove to be wr_n and rd_n controls . if these specified values ar e not met, these are for cs_n control. note 3) ?command pulse? means a low ac tive pulse obtained by performing or op eration between cs_n signal and each of wr_n and rd_n signals.
electrical characteristics YGV638 4gv638a21 19 cpu read cycle ps2-0 cs_n rd_n d7-0 wait_n ready_n t hr eady t sa t hc s t ha t scs t offd t onwait t dd t offwait t dwai t t hd hi-z hi-z hi-z hi-z t onwait t dd t offwait hi-z hi-z t ond cpu write cycle ps2-0 cs_n wr_n d7-0 wait_n ready_n t sa t hc s t ha t sd t scs t hd t offwait t on wait h i -z hi-z t onwait t offwait t dwait h i -z hi-z t hready t hwr t hwr access cycle cs_n wr_n rd_n t ac md t icmd t ccmd t acmd t icmd t cc m d t acmd t icmd t ccmd t acmd t icmd t ccmd
electrical characteristics YGV638 4gv638a21 20 ii) serial interface no. items symbol min. typ. max. unit note 200 1 sclk clock cycle time t wsclk 4 t cxin 1, 2 100 2 sclk clock high level pulse width t whsclk 2 t cxin 1, 2 100 3 sclk clock low level pulse width t wlsclk 2 t cxin 1, 2 4 scs_n: setup time t sscs 25 5 scs_n: hold time t hscs 25 6 sdin: setup time t ssdi 25 7 sdin: hold time t hsdi 25 8 sdout: output data delay time t dsdo 65 3 9 sdout: turn off time t offfsdo 20 10 scs_n: pulse inhibit time t iscs 400 ns note 1) alternative value during vc2 initialization. note 2) tc xin is the period of a clock that is fed to xin pin. note 3) during vc2 initialization, the maximum of t dsdo becomes 17 ns plus 3 ti mes the xin input cycle. scs_n sclk sdin sdout hi-z t wsclk t sscs t wlsclk t whsclk t ssd i t hsd i t hscs t dsdo t offsdo t dsdo scs_n sclk t iscs
electrical characteristics YGV638 4gv638a21 21 pattern memory interface no. items symbol min. typ. max. unit note 1 ma25-1: output delay time t dma 14 1 2 moe_n: output delay time t doe 2 14 1 3 mwe_n: output delay time t dwe 2 14 1 4 md31-0: input setup time t smd 4 1 5 md31-0: input hold time t hmd 0 1 6 md31-0: output delay time t dmd 24 1 7 ma25-1: output hold time from moe_n t hmar 0 8 md31-0: input hold time from moe_n and ma25-1 t hmdi 0 9 ma25-1: output hold time from mwe_n t hmaw 0 10 md31-0: output hold time from mwe_n t hmdo 1 11 md31-0: turn off time from mwe_n t offmdo 1 10 12 output turn off / on time from rahz_n t on/offra 25 ns note 1) specified value for an internal clock (syclk) memory access cycle (random read cycle) syclk ma25-1 moe_n mwe_n md31-0 t dma t smd t hmd t dwd t doe t dma t doe t hmar t hmdi note) after the read access, values of ma[25:0] and moe_ n are held until the next ac cess to the pattern memory. memory access cycle (write cycle) syclk ma25-1 moe_n mwe_n md31-0 t dma t dmd t doe t dwe t dma t dwe t dmaw t offmdo t hmd o note) after the write access, values of ma25?1 and moe_n are held until the next ac cess to the pattern memory.
electrical characteristics YGV638 4gv638a21 22 rahz_n ma25-1, md31-0 moe_n,mwe_n rahz_n t on/offra t on/offra the ac characteristics of an external memory conn ecting to vc2 must meet the following conditions. (the following conditions are the values converted fro m the ac characteristics of the vc2 pattern memory; they do not guarantee the following specifications directly. in addition, the item names below are those mainly for an externally-connected memory.) ?f?, ?r?, and ?p? in the below are as follows. f = (r#008h: fltim[1:0] + 1) number of floating clocks r = (r#009h: rdm[3:0] + 1) nu mber of random access clocks p = (r#009h: pag[2:0] + 1) number of page mode access clocks no. items symbol conditions 13 address access time t acc it should be (f + r) * t csy ? t dma (max) ? t smd (min) or less 14 output enable time t oe it should be r * t csy ? t doe (max) ? t smd (min) or less 15 page mode access time t pacc it should be p * t csy ? t dma (max) ? t smd (min) or less 16 data turn on time t do it should be 0[ns] or over 17 data turn off time t df it should be f * t csy - t doe (max) + t dwe (min) or less 18 data setup time t ds it should be r * t csy - t dmd (max) + t dwe (min) or less syclk ma25-(n+1) ma(n)-1 moe_n mwe_n md31-0 t acc t df t pacc t hmar t hmd i t oe t hmod t ds t dma (max) t smd (min) t dma (max) r f t doe (max) t dw e (max) t dma (max) t dma (max) t hmdi t smd (min) p t do syclk ma25-(n+1) ma(n)-1 moe_n mwe_n md31-0 t hmdo t ds t dma (max) r f t dw e (max) t dwe (max) t dma (max) t dmd (max) t doe (max) note) after accesses, values of ma25?1 and moe_n are held until the next access to the pattern memory.
electrical characteristics YGV638 4gv638a21 23 video signal interface no. items symbol min. typ. max. unit note 1 dotclk: delay time t ddotc 26 2 vsync_n, hcsync_n, blank_n, dro7-0, dgo7-0, dbo7-0, loadh, starth, outenv: hold time t hdisp 0 3 vsync_n, hcsync_n, blank_n, dro7-0, dgo7-0, dbo7-0, loadh, starth, outenv: delay time t ddisp 10 4 dvsin_n, dhsin_n, dri7-2, dgi7-2, dbi7-2: setup time t sdi 4 5 dvsin_n, dhsin_n, dri7-2, dgi7-2, dbi7-2: hold time t hdi 1 6 avsin_n, ahsin_n: setup time t sdi 3 7 avsin_n, ahsin_n: hold time t hdi 1 ns dgckin or dtckin or xin dotclk outputs t ddotc t ddisp t hdisp t ddotc note) the above figure shows the st ate that dotclk is not reversed. inputs t sdi t hdi dgckin arckin
package information YGV638 4gv638a21 24 package information
YGV638 4gv638a21 25 precautions and inst ructions for safety warning prohibited do not use the device under stresses beyond those listed in absolute maximum ratings. such stresses may become causes of breakdown, damages, or deterioration, causing explosion or ignition, and this may lead to fire or personal injury. prohibited do not mount the device reversely or improperly and also do not connect a supply voltage in wrong polarity. otherwise, this may cause current and/or power-consumption to exceed the absolute maximum ratings, causing personal injury due to explosion or ignition as well as causing breakdown, damages, or deterioration. and, do not use the device again that has been improperly mounted and powered once. prohibited do not short between pins. in particular, when different power supply pins, such as between high-voltage and low-voltage pins, are shorted, smoke, fire, or explosion may take place. instructions as to devices capable of generating sound from its speaker outputs, please design with safety of your products and system in mind, such as the consequences of unusual speaker output due to a malfunction or failure. a speaker dissipates heat in a voice-coil by air flow accompanying vibration of a diaphragm. when a dc signal (several hz or less) is input due to device failure, heat dissipation characteristics degrade rapidly, thereby leading to voice-coil burnout, smoking or ignition of the speaker even if it is used within the rated input value. caution prohibited do not use yamaha products in close proximity to burning materials, combustible substances, or inflammable materials, in order to prevent the spread of the fire caused by yamaha products, and to prevent the smoke or fire of yamaha products due to peripheral components. instructions generally, semiconductor products may malfunction and break down due to aging, degradation, etc. it is the responsibility of the designer to take actions such as safety design of products and the entire system and also fail-safe design according to applications, so as not to cause property damage and/or bodily injury due to malfunction and/or failure of semiconductor products. instructions the built-in dsp may output the maximum amplitude waveform suddenly due to malfunction from disturbances etc. and this may cause damage to headphones, external amplifiers, and human body (the ear). please pay attention to safety measures for device malfunction and failure both in product and system design. instructions as semiconductor devices are not nonflammable, overcurrent or failure may cause smoke or fire. therefore, products should be designed with safety in mind such as using overcurrent protection circuits to control the amount of current during operation and to shut off on failure. instructions products should be designed with fail safe in mind in case of malfunction of the built-in protection circuits. note that the built-in protection circuits such as overcurrent protection circuit and high-temperature protection circuit do not always protect the internal circuits. in some cases, depending on usage or situations, such protection circuit may not work properly or the device itself may break down before the protection circuit kicks in. instructions use a robust power supply. the use of an unrobust power supply may lead to malfunctions of the protection circuit, causing device breakdown, personal injury due to explosion, or smoke or fire. instructions product's housing should be designed with the considerations of short-circuiting between pins of the mounted device due to foreign conductive substances (such as metal pins etc.). moreover, the housing should be designed with spatter prevention etc. due to explosion or burning. otherwise, the spattered substance may cause bodily injury. instructions the device may be heated to a high temperature due to internal heat generation during operation. therefore, please take care not to touch an operating device directly. v02

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