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hd66702 (lcd-ii/e20) (dot matrix liquid crystal display controller/driver) description the hd66702 lcd-ii/e20 dot-matrix liquid crystal display controller and driver lsi displays alphanu- merics, japanese kana characters, and symbols. it can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. since all the functions required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver. a single lcd-ii/e20 can display up to two 20- character lines. however, with the addition of hd44100 drivers, a maximum of up to two 40- character lines can be displayed. the low 3-v power supply of the lcd-ii/e20 under development is suitable for any portable battery- driven product requiring low power dissipation. features ? 7 and 5 10 dot matrix possible 80 8-bit display ram (80 characters max.) 7,200-bit character generator rom 160 character fonts (5 7 dot) 32 character fonts (5 10 dot) 64 8-bit character generator ram 8 character fonts (5 7 dot) 4 character fonts (5 10 dot) 16-common 100-segment liquid crystal display driver programmable duty cycles 1/8 for one line of 5 7 dots with cursor 1/11 for one line of 5 10 dots with cursor 1/16 for two lines of 5 7 dots with cursor maximum display characters one line 1/8 duty cycle, 20-char. 1-line (no exten- sion), 28-char. 1-line (extended with one hd44100r), 80-char. 1-line (max. exten- sion with eight hd44100s). 1/11 duty cycle, 20-char. 1-line (no extension), 28-char. 1-line (extended with one hd44100r), 80- char. 1-line (max. extension with eight hd44100rs) two lines 1/16 duty cycle, 20-char. 2-line (no exten- sion), 28-char. 2-line (extended with one hd44100r), 40-char. 2-line (max. exten- sion with eight hd44100rs) wide range of instruction functions display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift choice of power supply (v cc ): 4.5 to 5.5 v (standard), 2.7 to 5.5 v (low voltage) automatic reset circuit that initializes the controller/driver after power on (standard ver- sion only) independent lcd drive voltage driven off of the logic power supply (v cc ): 3.0 to 8.3 v
ordering information type no. package operating voltage rom font hcd66702ra00l chip 2.7 to 5.5 v standard japanese hd66702ra00f 144-pin plastic qfp (fp-144a) 4.5 to 5.5 v font hd66702ra00fl 144-pin plastic qfp (fp-144a) 2.7 to 5.5 v hd66702ra01f 144-pin plastic qfp (fp-144a) 4.5 to 5.5 v japanese font for comunication system hd66702ra02f 144-pin plastic qfp (fp-144a) 4.5 to 5.5 v european font hcd66702rbxxl chip 2.7 to 5.5 v custom font HD66702RBXXF 144-pin plastic qfp (fp-144a) 4.5 to 5.5 v HD66702RBXXFl 144-pin plastic qfp (fp-144a) 2.7 to 5.5 v note: xx: rom code no. hd66702 269
lcd-ii family comparison item lcd-ii (hd44780u) lcd-ii/e20 (hd66702) power supply voltage 2.7 to 5.5 v 5 v 10% (standard) 2.7 to 5.5 v (low voltage) liquid crystal drive 1/4 bias 3.0 to 11 v 3.0 to 8.3 v voltage v lcd 1/5 bias 3.0 to 11 v 3.0 to 8.3 v maximum display 16 digits 40 digits digits per chip (8 digits 2 lines) (20 digits 2 lines) display duty cycle 1/8, 1/11, and 1/16 1/8, 1/11, and 1/16 cgrom 9,600 bits 7,200 bits (208 character fonts (160 character fonts for for 5 8 dot and 5 7 dot and 32 character fonts 32 character fonts for for 5 10 dot) 5 10 dot) cgram 64 bytes 64 bytes ddram 80 bytes 80 bytes segment signals 40 100 common signals 16 16 liquid crystal drive waveform a b ladder resistor for lcd external external power supply clock source external resistor external resistor or external or external clock clock r f oscillation frequency 270 khz 30% 320 khz 30% (frame frequency) (59 to 110 hz for 1/8 and (69 to 128 hz for 1/8 and 1/16 duty cycles; 43 to 80 hz 1/16 duty cycles; 50 to 93 hz for 1/11 duty cycle) for 1/11 duty cycle) r f resistance 91 k w 2% (5 v) 68 k w 2% (5 v) 75 k 2% (3 v) 56 k w 2% (3 v) instructions fully compatible within the lcd-ii family cpu bus timing 1 mhz 1 mhz package fp-80b, tfp-80, and 80-pin 144-pin bare chip (no package) bare chip (no package) and fp-144a 270 hd66702
lcd-ii/e20 block diagram hd66702 271 display data ram (dd ram) 80 8 bits character generator rom (cg rom) 7,200 bits character generator ram (cg ram) 64 bytes instruction register (ir) timing generator common signal driver 16-bit shift register segment signal driver 100-bit latch circuit 100-bit shift register parallel/serial converter and attribute circuit lcd drive voltage selector address counter mpu inter- face input/ output buffer busy flag ext data register (dr) cursor and blink controller cpg cl 1 cl 2 m d rs r/w db to db 4 7 e instruction decoder osc 1 osc 2 com to com 1 16 seg to seg 1 100 8 8 8 7 100 5 5 100 7 8 7 8 7 16 test v cc gnd v 1 v 2 v 3 v 4 v 5 db to db 0 3 reset circuit acl 8
lcd-ii/e20 pad arrangement 272 hd66702 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg com com com com com com seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg gnd osc osc v v v v v v v cl cl m d ext test gnd rs r/w e db db db db db db db db com com com com com com com com com com seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg 1 cc cc 1 2 3 4 5 1 2 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 * note: * : test pins to be grounded : power supply pins : power supply pins (ground) : input pins : output pins : input/output pins minimum pad pitch = 130 m hd66702 type code 2 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 16 15 14 13 12 11 (top view)
hd66702 273 hcd66702 pad location coordinates pad pad no. name x (m) y (m) 1 seg 34 ?475 2350 2 seg 33 ?475 2205 3 seg 32 ?475 2065 4 seg 31 ?475 1925 5 seg 30 ?475 1790 6 seg 29 ?475 1655 7 seg 28 ?475 1525 8 seg 27 ?475 1395 9 seg 26 ?475 1265 10 seg 25 ?475 1135 11 seg 24 ?475 1005 12 seg 23 ?475 875 13 seg 22 ?475 745 14 seg 21 ?475 615 15 seg 20 ?475 485 16 seg 19 ?475 355 17 seg 18 ?475 225 18 seg 17 ?475 95 19 seg 16 ?475 ?5 20 seg 15 ?475 ?65 21 seg 14 ?475 ?95 22 seg 13 ?475 ?25 23 seg 12 ?475 ?55 24 seg 11 ?475 ?85 25 seg 10 ?475 ?15 26 seg 9 ?475 ?45 27 seg 8 ?475 ?075 28 seg 7 ?475 ?205 29 seg 6 ?475 ?335 30 seg 5 ?475 ?465 pad pad no. name x (m) y (m) 31 seg 4 ?475 ?600 32 seg 3 ?475 ?735 33 seg 2 ?475 ?870 34 seg 1 ?475 ?010 35 gnd ?475 ?180 36 osc 2 ?475 ?325 37 osc 1 ?445 ?475 38 v cc ?305 ?475 39 v cc ?165 ?475 40 v 1 ?025 ?475 41 v 2 ?875 ?475 42 v 3 ?745 ?475 43 v 4 ?595 ?475 44 v 5 ?465 ?475 45 cl 1 ?335 ?475 46 cl 2 ?185 ?475 47 m ?055 ?475 48 d ?05 ?475 49 ext ?75 ?475 50 test ?25 ?475 51 gnd ?95 ?475 52 rs ?45 ?475 53 r/ w ?95 ?475 54 e ?5 ?475 55 db 0 85 ?475 56 db 1 235 ?475 57 db 2 365 ?475 58 db 3 515 ?475 59 db 4 645 ?475 60 db 5 795 ?475
274 hd66702 pad pad no. name x (m) y (m) 61 db 6 925 ?475 62 db 7 1075 ?475 63 com 1 1205 ?475 64 com 2 1335 ?475 65 com 3 1465 ?475 66 com 4 1595 ?475 67 com 5 1725 ?475 68 com 6 1855 ?475 69 com 7 1990 ?475 70 com 8 2125 ?475 71 com 9 2265 ?475 72 com 10 2410 ?475 73 com 11 2475 ?290 74 com 12 2475 ?145 75 com 13 2475 ?005 76 com 14 2475 ?865 77 com 15 2475 ?730 78 com 16 2475 ?595 79 seg 100 2475 ?465 80 seg 99 2475 ?335 81 seg 98 2475 ?205 82 seg 97 2475 ?075 83 seg 96 2475 ?45 84 seg 95 2475 ?15 85 seg 94 2475 ?85 86 seg 93 2475 ?55 87 seg 92 2475 ?25 88 seg 91 2475 ?95 89 seg 90 2475 ?65 90 seg 89 2475 ?5 pad pad no. name x (m) y (m) 91 seg 88 2475 95 92 seg 87 2475 225 93 seg 86 2475 355 94 seg 85 2475 485 95 seg 84 2475 615 96 seg 83 2475 745 97 seg 82 2475 875 98 seg 81 2475 1005 99 seg 80 2475 1135 100 seg 79 2475 1265 101 seg 78 2475 1395 102 seg 77 2475 1525 103 seg 76 2475 1655 104 seg 75 2475 1790 105 seg 74 2475 1925 106 seg 73 2475 2065 107 seg 72 2475 2205 108 seg 71 2475 2350 109 seg 70 2320 2475 110 seg 69 2175 2475 111 seg 68 2035 2475 112 seg 67 1895 2475 113 seg 66 1760 2475 114 seg 65 1625 2475 115 seg 64 1495 2475 116 seg 63 1365 2475 117 seg 62 1235 2475 118 seg 61 1105 2475 119 seg 60 975 2475 120 seg 59 845 2475
hd66702 275 pad pad no. name x (m) y (m) 121 seg 58 715 2475 122 seg 57 585 2475 123 seg 56 455 2475 124 seg 55 325 2475 125 seg 54 195 2475 126 seg 53 65 2475 127 seg 52 ?5 2475 128 seg 51 ?95 2475 129 seg 50 ?25 2475 130 seg 49 ?55 2475 131 seg 48 ?85 2475 132 seg 47 ?15 2475 pad pad no. name x (m) y (m) 133 seg 46 ?45 2475 134 seg 45 ?75 2475 135 seg 44 ?105 2475 136 seg 43 ?235 2475 137 seg 42 ?365 2475 138 seg 41 ?495 2475 139 seg 40 ?625 2475 140 seg 39 ?760 2475 141 seg 38 ?895 2475 142 seg 37 ?035 2475 143 seg 36 ?175 2475 144 seg 35 ?320 2475 notes: 1. coordinates originate from the chip center. 2. the above are preliminary specifications, and may be subject to change.
hd66702 pin arrangement 276 hd66702 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg com com com com com com seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg gnd osc osc v v v v v v v cl cl m d ext test gnd rs r/w e db db db db db db db db com com com com com com com com com com seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg 1 cc cc 1 2 3 4 5 1 2 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 * note: * : test pins to be grounded : power supply pins : power supply pins (ground) : input pins : output pins : input/output pins 2 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 16 15 14 13 12 11 fp-144a (top view)
pin functions table 1 pin functional description device signal i/o interfaced with function rs i mpu selects registers 0: instruction register (for write) busy flag: address counter (for read) 1: data register (for write and read) r/ w i mpu selects read or write 0: write 1: read e i mpu starts data read/write db 4 to db 7 i/o mpu four high order bidirectional tristate data bus pins. used for data transfer between the mpu and the lcd-ii/e20. db 7 can be used as a busy flag. db 0 to db 3 i/o mpu four low order bidirectional tristate data bus pins. used for data transfer between the mpu and the lcd-ii/e20. these pins are not used during 4-bit operation. cl 1 o hd44100 clock to latch serial data d sent to the hd44100h driver cl 2 o hd44100 clock to shift serial data d m o hd44100 switch signal for converting the liquid crystal drive waveform to ac d o hd44100 character pattern data corresponding to each segment signal com 1 to com 16 o lcd common signals that are not used are changed to non- selection waveforms. com 9 to com 16 are non- selection waveforms at 1/8 duty factor and com 12 to com 16 are non-selection waveforms at 1/11 duty factor. seg 1 to seg 100 o lcd segment signals v 1 to v 5 power supply power supply for lcd drive v cc , gnd power supply v cc : +5 v or +3 v, gnd: 0 v test i test pin, which must be grounded ext i 0: enables extension driver control signals cl 1 , cl 2 , m, and d to be output from its corresponding pins. 1: drives cl 1 , cl 2 , m, and d as tristate, lowering power dissipation. osc 1 , osc 2 pins for connecting the registers of the internal clock oscillation. when the pin input is an external clock, it must be input to osc 1 . hd66702 277
278 hd66702 function description registers the hd66702 has two 8-bit registers, an instruc- tion register (ir) and a data register (dr). the ir stores instruction codes, such as display clear and cursor shift, and address information for display data ram (dd ram) and character generator ram (cg ram). the ir can only be written from the mpu. the dr temporarily stores data to be written into dd ram or cg ram. data written into the dr from the mpu is automatically written into dd ram or cg ram by an internal operation. the dr is also used for data storage when reading data from dd ram or cg ram. when address information is written into the ir, data is read and then stored into the dr from dd ram or cg ram by an internal operation. data transfer between the mpu is then completed when the mpu reads the dr. after the read, data in dd ram or cg ram at the next address is sent to the dr for the next read from the mpu. by the register selector (rs) signal, these two registers can be selected (table 2). busy flag (bf) when the busy flag is 1, the hd66702 is in the internal operation mode, and the next instruction will not be accepted. when rs = 0 and r/w = 1 (table 2), the busy flag is output to db 7 . the next instruction must be written after ensuring that the busy flag is 0. address counter (ac) the address counter (ac) assigns addresses to both dd ram and cg ram. when an address of an instruction is written into the ir, the address information is sent from the ir to the ac. selection of either dd ram or cg ram is also determined concurrently by the instruction. after writing into (reading from) dd ram or cg ram, the ac is automatically incremented by 1 (decremented by 1). the ac contents are then output to db 0 to db 6 when rs = 0 and r/ w = 1 (table 2). table 2 register selection rs r/ w operation 0 0 ir write as an internal operation (display clear, etc.) 0 1 read busy flag (db 7 ) and address counter (db 0 to db 6 ) 1 0 dr write as an internal operation (dr to dd ram or cg ram) 1 1 dr read as an internal operation (dd ram or cg ram to dr)
hd66702 279 display data ram (dd ram) display data ram (dd ram) stores display data represented in 8-bit character codes. its extended capacity is 80 8 bits, or 80 characters. the area in display data ram (dd ram) that is not used for display can be used as general data ram. see figure 1 for the relationships between dd ram addresses and positions on the liquid crystal display. the dd ram address (a dd ) is set in the address counter (ac) as hexadecimal. 1-line display (n = 0) (figure 2) case 1: when there are fewer than 80 dis- play characters, the display begins at the head position. for example, if using only the hd66702, 20 characters are displayed. see figure 3. when the display shift operation is per- formed, the dd ram address shifts. see figure 3. case 2: for a 28-character display, the hd66702 can be extended using one hd44100 and displayed. see figure 4. when the display shift operation is per- formed, the dd ram address shifts. see figure 4. case 3: the relationship between the display position and dd ram address when the number of display digits is increased through the use of two or more hd44100s can be considered as an extension of case #2. since the increase can be eight digits per additional hd44100, up to 80 digits can be displayed by externally connecting eight hd44100s. see figure 5. figure 1 dd ram address figure 2 1-line display ac6 ac5 ac4 ac3 ac2 ac1 ac0 1001110 ac (hexadecimal) example: dd ram address 4e high order bits low order bits 00 01 02 03 04 4e 4f dd ram address (hexadecimal) display position (digit) 123 45 7980 . . . . . . . . . . . . . . . . . .
figure 3 1-line by 20-character display example figure 4 1-line by 28-character display example figure 5 1-line by 80-character display example 280 hd66702 dd ram address display position 12345 678910111213141516 17 18 19 20 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 for shift left 10 11 12 13 14 for shift right 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 4f dd ram address display position 1 28 23456789101112131415161718192021222324252627 00 1b 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a lcd-ii/e20 display hd44100 display 01 02 03 04 05 06 07 08 for shift left for shift right 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 4f 1c dd ram address display position 1 28 23456789101112131415161718192021222324252627 00 1b 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a lcd-ii/e20 display 1st hd44100 display 80 77 78 79 4f 4c 4d 4e ........ 8th hd44100 display
hd66702 281 2-line display (n = 1) (figure 6) case 1: when the number of display char- acters is less than 40 2 lines, the two lines are displayed from the head. note that the first line end address and the second line start address are not consecutive. for example, when just the hd66702 is used, 20 characters 2 lines are displayed. see figure 7. when display shift operation is performed, the dd ram address shifts. see figure 7. figure 6 2-line display figure 7 2-line by 20-character display example 00 01 02 03 04 26 27 dd ram address (hexadecimal) display position 123 45 3940 . . . . . . . . . . . . . . . . . . 40 41 42 43 44 66 67 . . . . . . . . . . . . . . . . . . dd ram address display position 12345 678910111213141516 17 18 19 20 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 for shift left for shift right 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 14 54 27 67
282 hd66702 case 2: for a 28-character 2-line display, the hd66702 can be extended using one hd44100. see figure 8. when display shift operation is performed, the dd ram address shifts. see figure 8. case 3: the relationship between the display position and dd ram address when the number of display digits is increased by using two or more hd44100s, can be con- sidered as an extension of case #2. see figure 9. since the increase can be 8 digits 2 lines for each additional hd44100, up to 40 digits 2 lines can be displayed by externally con- necting three hd44100s. figure 8 2-line by 28-character display example figure 9 2-line by 40-character display example dd ram address display position 1 28 23456789101112131415161718192021222324252627 00 1b 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a for shift left 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 27 40 5b 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a lcd-ii/e20 display hd44100 display 02 01 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a for shift right 5b 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a 67 1b 1c 5c dd ram address display position 40 5b 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a lcd-ii/e20 display 1st hd44100 display 67 64 65 66 ........ 3rd hd44100 display 1 28 23456789101112131415161718192021222324252627 40 37 38 39 ........ 00 1b 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 27 24 25 26
hd66702 283 character generator rom (cg rom) the character generator rom generates 5 7 dot or 5 10 dot character patterns from 8-bit char- acter codes (table 5). it can generate 160 5 7 dot character patterns and 32 5 10 dot character patterns. user-defined character patterns are also available by mask-programmed rom. character generator ram (cg ram) in the character generator ram, the user can rewrite character patterns by program. for 5 7 dots, eight character patterns can be written, and for 5 10 dots, four character patterns can be written. write the character codes at the addresses shown as the left column of table 5 to show the character patterns stored in cg ram. see table 6 for the relationship between cg ram addresses and data and display patterns. areas that are not used for display can be used as general data ram. modifying character patterns character pattern development procedure the following operations correspond to the numbers listed in figure 10: 1. determine the correspondence between char- acter codes and character patterns. 2. create a listing indicating the correspondence between eprom addresses and data. 3. program the character patterns into the eprom. 4. send the eprom to hitachi. 5. computer processing on the eprom is per- formed at hitachi to create a character pattern listing, which is sent to the user. 6. if there are no problems within the character pattern listing, a trial lsi is created at hitachi and samples are sent to the user for evaluation. when it is confirmed by the user that the character patterns are correctly written, mass production of the lsi proceeds at hitachi.
figure 10 character pattern development procedure 284 hd66702 determine character patterns create eprom address data listing write eprom eprom ? hitachi computer processing create character pattern listing evaluate character patterns ok? art work sample evaluation ok? masking trial sample no yes no yes m/t 1 3 2 4 5 6 note: for a description of the numbers used in this figure, refer to the preceding page. user hitachi mass production start
hd66702 285 programming character patterns this section explains the correspondence be- tween addresses and data used to program character patterns in eprom. the lcd-ii/e20 character generator rom can generate 160 5 7 dot character patterns and 32 5 10 dot character patterns for a total of 192 different character patterns. ? 7 dot character pattern eprom address data and character pattern data correspond with each other to form a 5 7 dot character pattern (table 3). table 3 example of correspondence between eprom address data and character pattern (5 7 dots) notes: 1. eprom addresses a 10 to a 3 correspond to a character code. 2. eprom addresses a 2 to a 0 specify a line position of the character pattern. 3. eprom data o 4 to o 0 correspond to character pattern data. 4. a lit display position (black) corresponds to a 1. 5. line 8 (cursor position) of the character pattern must be blanked with 0s. 6. eprom data o 5 to o 7 are not used. a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 data o 4 o 3 o 2 o 1 o 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 1 0 0 1 0 eprom address character code line position fill line 8 (cursor position) with 0s 0 0 0 0 0 1 1 1 1 0 1 0 0 0 1 1 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 1 lsb
286 hd66702 ? 10 dot character pattern eprom address data and character pattern data correspond with each other to form a 5 10 dot character pattern (table 4). handling unused character patterns 1. eprom data outside the character pattern area: ignored by the character generator rom for display operation so 0 or 1 is arbitrary. 2. eprom data in cg ram area: ignored by the character generator rom for display oper- ation so 0 or 1 is arbitrary. 3. eprom data used when the user does not use any hd66702 character pattern: according to the user application, handled in one of the two ways listed as follows. a. when unused character patterns are not programmed: if an unused character code is written into dd ram, all its dots are lit. by not programing a character pattern, all of its bits become lit. (this is due to the eprom being filled with 1s after it is erased.) b. when unused character patterns are programmed as 0s: nothing is displayed even if unused character codes are written into dd ram. (this is equivalent to a space.) table 4 example of correspondence between eprom address data and character pattern (5 10 dots) notes: 1. eprom addresses a 10 to a 3 correspond to a character code. set a 8 and a 9 of character pattern lines 9, 10, and 11 to 0s. 2. eprom addresses a 2 to a 0 specify a line position of the character pattern. 3. eprom data o 4 to o 0 correspond to character pattern data. 4. a lit display position (black) corresponds to a 1. 5. blank out line 11 (cursor position) of the character pattern with 0s. 6. eprom data o 5 to o 7 are not used. a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 data o 4 o 3 o 2 o 1 o 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 0 0 0 1 eprom address character code line position fill line 11 (cursor position) with 0s lsb 1 0 1 1 1 0 1 1 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 1 1 1
table 5 correspondence between character codes and character patterns (rom code: a00) note: the user can specify any pattern for character-generator ram. hd66702 287 xxxx0000 xxxx0001 xxxx0010 xxxx0011 xxxx0100 xxxx0101 xxxx0110 xxxx0111 xxxx1000 xxxx1001 xxxx1010 xxxx1011 xxxx1100 xxxx1101 xxxx1110 xxxx1111 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 upper 4 bits lower 4 bits cg ram (1) (2) (3) (4) (5) (6) (7) (8) (1) (2) (3) (4) (5) (6) (7) (8)
table 5 correspondence between character codes and character patterns (rom code: a01) 288 hd66702 xxxx0000 xxxx0001 xxxx0010 xxxx0011 xxxx0100 xxxx0101 xxxx0110 xxxx0111 xxxx1000 xxxx1001 xxxx1010 xxxx1011 xxxx1100 xxxx1101 xxxx1110 xxxx1111 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 upper 4 bits lower 4 bits cg ram (1) (2) (3) (4) (5) (6) (7) (8) (1) (2) (3) (4) (5) (6) (7) (8)
table 5 correspondence between character codes and character patterns (rom code: a02) hd66702 289 xxxx0000 xxxx0001 xxxx0010 xxxx0011 xxxx0100 xxxx0101 xxxx0110 xxxx0111 xxxx1000 xxxx1001 xxxx1010 xxxx1011 xxxx1100 xxxx1101 xxxx1110 xxxx1111 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 upper 4 bits lower 4 bits cg ram (1) (2) (3) (4) (5) (6) (7) (8) (1) (2) (3) (4) (5) (6) (7) (8)
table 6 relationship between cg ram addresses, character codes (dd ram) and character patterns (cg ram data) for 5 7 dot character patterns notes: 1. character code bits 0 to 2 correspond to cg ram address bits 3 to 5 (3 bits: 8 types). 2. cg ram address bits 0 to 2 designate the character pattern line position. the 8th line is the cursor position and its display is formed by a logical or with the cursor. maintain the 8th line data, corresponding to the cursor display position, at 0 as the cursor display. if the 8th line data is 1, 1 bits will light up the 8th line regardless of the cursor presence. 3. character pattern row positions correspond to cg ram data bits 0 to 4 (bit 4 being at the left ). since cg ram data bits 5 to 7 are not used for display, they can be used for general data ram. 4. as shown tables 5 and 6, cg ram character patterns are selected when character code bits 4 to 7 are all 0. however, since character code bit 3 has no effect, the r display example above can be selected by either character code 00h or 08h. 5. 1 for cg ram data corresponds to display selection and 0 to non-selection. * indicates no effect. 290 hd66702 character codes (dd ram data) cg ram address character patterns (cg ram data) 7 6 5 4 3 2 1 0 0 0 0 0 * 0 0 0 0 0 0 0 * 0 0 1 0 0 0 0 * 1 1 1 5 4 3 2 1 0 0 0 0 0 0 1 1 1 1 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * * * * * * * * * * * * * * * * * high low high low high low character pattern cursor position 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 1 1 0 1 0 0 0
table 6 relationship between cg ram addresses, character codes (dd ram) and character patterns (cg ram data) (cont) for 5 10 dot character patterns notes: 1. character code bits 1 and 2 correspond to cg ram address bits 4 and 5 (2 bits: 4 types). 2. cg ram address bits 0 to 3 designate the character pattern line position. the 11th line is the cursor position and its display is formed by a logical or with the cursor. maintain the 11th line data corresponding to the cursor display positon at 0 as the cursor display. if the 11th line data is 1, 1 bits will light up the 11th line regardless of the cursor presence. since lines 12 to 16 are not used for display, they can be used for general data ram. 3. character pattern row positions are the same as 5 7 dot character pattern positions. 4. cg ram character patterns are selected when character code bits 4 to 7 are all 0. however, since character code bits 0 and 3 have no effect, the p display example above can be selected by character codes 00h, 01h, 08h, and 09h. 5. 1 for cg ram data corresponds to display selection and 0 to non-selection. * indicates no effect. hd66702 291 character codes (dd ram data) cg ram address character patterns (cg ram data) 7 6 5 4 3 2 1 0 0 0 0 0 * 0 0 0 0 0 0 1 1 5 4 3 2 1 0 0 0 1 1 7 6 5 4 3 2 1 0 * * * * * * * * * * * * * * * * * * * * * * * * high low high low high low character pattern cursor position 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 * * * * * ** 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 * * * * * * * * * * * * * * * *
292 hd66702 timing generation circuit the timing generation circuit generates timing signals for the operation of internal circuits such as dd ram, cg rom and cg ram. ram read timing for display and internal operation timing by mpu access are generated separately to avoid interfering with each other. therefore, when writing data to dd ram, for example, there will be no undesirable interferences, such as flickering, in areas other than the display area. this circuit also generates timing signals for the operation of the externally connected hd44100 driver. liquid crystal display driver circuit the liquid crystal display driver circuit consists of 16 common signal drivers and 100 segment signal drivers. when the character font and number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output non-selection waveforms. the segment signal driver has essentially the same configuration as the hd44100 driver. character pattern data is sent serially through a 100-bit shift register and latched when all needed data has arrived. the latched data then enables the driver to generate drive waveform outputs. the serial data can be sent to externally cascaded hd44100s used for displaying extended digit numbers. sending serial data always starts at the display data character pattern corresponding to the last address of the display data ram (dd ram). since serial data is latched when the display data character pattern corresponding to the starting address enters the internal shift register, the hd66702 drives from the head display. the rest of the display, corresponding to latter addresses, are added with each additional hd44100. cursor/blink control circuit the cursor/blink control circuit generates the cursor or character blinking. the cursor or the blinking will appear with the digit located at the display data ram (dd ram) address set in the address counter (ac). for example (figure 11), when the address counter is 08h, the cursor position is displayed at dd ram address 08h. figure 11 cursor/blink display example ac6 0 ac5 0 ac4 0 ac3 1 ac2 0 ac1 0 ac0 0 1 00 2 01 3 02 4 03 5 04 6 05 7 06 8 07 9 08 10 09 11 0a 1 00 40 2 01 41 3 02 42 4 03 43 5 04 44 6 05 45 7 06 46 8 07 47 9 08 48 10 09 49 11 0a 4a ac cursor position cursor position display position dd ram address (hexadecimal) display position dd ram address (hexadecimal) for a 1-line display for a 2-line display note: the cursor or blinking appears when the address counter (ac) selects the character generator ram (cg ram). however, the cursor and blinking become meaningless. the cursor or blinking is displayed in the meaningless position when the ac is a cg ram address.
hd66702 293 interfacing to the mpu the hd66702 can send data in either two 4-bit operations or one 8-bit operation, thus allowing interfacing with 4- or 8-bit mpus. for 4-bit interface data, only four bus lines (db 4 to db 7 ) are used for transfer. bus lines db 0 to db 3 are disabled. the data transfer between the hd66702 and the mpu is completed after the 4- bit data has been transferred twice. as for the order of data transfer, the four high order bits (for 8-bit operation, db 4 to db 7 ) are transferred before the four low order bits (for 8-bit operation, db 0 to db 3 ). the busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. two more 4-bit operations then transfer the busy flag and address counter data. for 8-bit interface data, all eight bus lines (db 0 to db 7 ) are used. figure 12 4-bit transfer example rs r/w e ir ir ir ir bf ac ac ac db db db db 7 6 5 4 instruction register (ir) write busy flag (bf) and address counter (ac) read data register (dr) read 7 6 5 4 ir ir ir ir 3 2 1 0 6 5 4 ac ac ac ac 3 2 1 0 dr dr dr dr 7 6 5 4 dr dr dr dr 3 2 1 0
294 hd66702 reset function initializing by internal reset circuit an internal reset circuit automatically initializes the hd66702 when the power is turned on. the following instructions are executed during the initialization. the busy flag (bf) is kept in the busy state until the initialization ends (bf = 1). the busy state lasts for 10 ms after v cc rises to 4.5 v. 1. display clear 2. function set: dl = 1; 8-bit interface data n = 0; 1-line display f = 0; 5 7 dot character font 3. display on/off control: d = 0; display off c = 0; cursor off b = 0; blinking off 4. entry mode set: i/d = 1; increment by 1 s = 0; no shift note: if the electrical characteristics conditions listed under the table power supply conditions using internal reset circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the hd66702. for such a case, initial- ization must be performed by the mpu as explained in the section, initializing by instruction. instructions outline only the instruction register (ir) and the data register (dr) of the hd66702 can be controlled by the mpu. before starting the internal operation of the hd66702, control information is temporarily stored into these registers to allow interfacing with various mpus, which operate at different speeds, or various peripheral control devices. the internal operation of the hd66702 is determined by signals sent from the mpu. these signals, which include register selection (rs), read/write (r/ w ), and the data bus (db 0 to db 7 ), make up the hd66702 instructions (table 7). there are four categories of instructions that: designate hd66702 functions, such as display format, data length, etc. set internal ram addresses perform data transfer with internal ram perform miscellaneous functions normally, instructions that perform data transfer with internal ram are used the most. however, auto-incrementation by 1 (or auto-decrementation by 1) of internal hd66702 ram addresses after each data write can lighten the program load of the mpu. since the display shift instruction (table 12) can perform concurrently with display data write, the user can minimize system development time with maximum programming efficiency. when an instruction is being executed for internal operation, no instruction other than the busy flag/address read instruction can be executed. because the busy flag is set to 1 while an instruc- tion is being executed, check it to make sure it is 0 before sending another instruction from the mpu. note: be sure the hd66702 is not in the busy state (bf = 0) before sending an instruction from the mpu to the hd66702. if an instruction is sent without checking the busy flag, the time between the first instruc- tion and next instruction will take much longer than the instruction time itself. refer to table 7 for the list of each instruc-tion execution time.
table 7 instructions code execution time (max) (when f cp or instruction rs r/ w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 description f osc is 320 khz) clear 0000000001 clears entire display and 1.28 ms display sets dd ram address 0 in address counter. return 000000001 sets dd ram address 0 in 1.28 ms home address counter. also returns display from being shifted to original position. dd ram contents remain unchanged. entry 00000001i/ds sets cursor move direction 31 s mode set and specifies display shift. these operations are performed during data write and read. display 0000001dcb sets entire display (d) 31 s on/off on/off, cursor on/off (c), control and blinking of cursor position character (b). cursor or 000001s/cr/l moves cursor and shifts 31 s display display without changing shift dd ram contents. function 00001dlnf sets interface data length 31 s set (dl), number of display lines (l), and character font (f). set cg 0001a cg a cg a cg a cg a cg a cg sets cg ram address. 31 s ram cg ram data is sent and address received after this setting. set dd 001a dd a dd a dd a dd a dd a dd a dd sets dd ram address. 31 s ram dd ram data is sent and address received after this setting. read busy 0 1 bf ac ac ac ac ac ac ac reads busy flag (bf) 0 s flag & indicating internal operation address is being performed and reads address counter contents. hd66702 295
table 7 instructions (cont) code execution time (max) (when f cp or instruction rs r/ w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 description f osc is 320 khz) write data 1 0 write data writes data into dd ram 31 s to cg or or cg ram. t add = 4.7 s * dd ram read data 1 1 read data reads data from dd ram 31 s from cg or or cg ram. t add = 4.7 s * dd ram i/d = 1: increment dd ram: display data execution time i/d = 0: decrement ram changes when s = 1: accompanies display shift cg ram: character frequency changes s/c = 1: display shift generator ram example: s/c = 0: cursor move a cg : cg ram address when f cp or f osc r/l = 1: shift to the right a dd : dd ram address is 270 khz, r/l = 0: shift to the left (corresponds to dl = 1: 8 bits, dl = 0: 4 bits cursor address) 31 s 320 = 37 s n = 1: 2 lines, n = 0: 1 line ac: address counter 270 f = 1: 5 10 dots, f = 0: 5 7 dots used for both dd and bf = 1: internally operating cg ram addresses bf = 0: instructions acceptable note: ? indicates no effect. * after execution of the cg ram/dd ram data write or read instruction, the ram address counter is incremented or decremented by 1. the ram address counter is updated after the busy flag turns off. in figure 13, t add is the time elapsed after the busy flag turns off until the address counter is updated. figure 13 address counter update 296 hd66702 busy state busy signal (db pin) address counter (db to db pins) 7 06 t add a a + 1 note: t depends on the operation frequency t = 1.5/(f or f ) seconds add add cp osc
hd66702 297 instruction description clear display clear display writes space code 20h (character pattern for character code 20h must be a blank pattern) into all dd ram addresses. it then sets dd ram address 0 into the address counter, and returns the display to its original status if it was shifted. in other words, the display disappears and the cursor or blinking goes to the left edge of the display (in the first line if 2 lines are displayed). it also sets i/d to 1 (increment mode) in entry mode. s of entry mode does not change. return home return home sets dd ram address 0 into the address counter, and returns the display to its original status if it was shifted. the dd ram contents do not change. the cursor or blinking go to the left edge of the display (in the first line if 2 lines are displayed). entry mode set i/d: increments (i/d = 1) or decrements (i/d = 0) the dd ram address by 1 when a character code is written into or read from dd ram. the cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1. the same applies to writing and reading of cg ram. s: shifts the entire display either to the right (i/d = 0) or to the left (i/d = 1) when s is 1. the display does not shift if s is 0. if s is 1, it will seem as if the cursor does not move but the display does. the display does not shift when reading from dd ram. also, writing into or reading out from cg ram does not shift the display. display on/off control d: the display is on when d is 1 and off when d is 0. when off, the display data remains in dd ram, but can be displayed instantly by setting d to 1. c: the cursor is displayed when c is 1 and not displayed when c is 0. even if the cursor disappears, the function of i/d or other specifications will not change during display data write. the cursor is displayed using 5 dots in the 8th line for 5 7 dot character font selection and in the 11th line for the 5 10 dot character font selection (figure 16). b: the character indicated by the cursor blinks when b is 1 (figure 16). the blinking is displayed as switching between all blank dots and displayed characters at a speed of 320-ms intervals when f cp or f osc is 320 khz. the cursor and blinking can be set to display simultaneously. (the blinking frequency changes according to f osc or the reciprocal of f cp . for example, when f cp is 270 khz, 320 320/270 = 379.2 ms.) cursor or display shift cursor or display shift shifts the cursor position or display to the right or left without writing or reading display data (table 8). this function is used to correct or search the display. in a 2-line display, the cursor moves to the second line when it passes the 40th digit of the first line. note that the first and second line displays will shift at the same time. when the displayed data is shifted repeatedly each line moves only horizontally. the second line display does not shift into the first line position. the address counter (ac) contents will not change if the only action performed is a display shift. function set dl: sets the interface data length. data is sent or received in 8-bit lengths (db 7 to db 0 ) when dl is 1, and in 4-bit lengths (db 7 to db 4 ) when dl is 0. when 4-bit length is selected, data must be sent or received twice.
298 hd66702 n: sets the number of display lines. f: sets the character font. note: perform the function at the head of the program before executing any instructions (except for the read busy flag and address instruction). from this point, the function set instruction cannot be executed unless the interface data length is changed. set cg ram address set cg ram address sets the cg ram address binary aaaaaa into the address counter. data is then written to or read from the mpu for cg ram. figure 14 figure 15 rs 0 r/w 0 db 0 db 0 db 0 db 0 db 0 code db 0 db 1 db 70 * note: don? care. * code rs 0 r/w 0 db 0 db 0 db 0 db 0 db 0 code db 1 db i/d db s 70 rs 0 r/w 0 db 0 db 0 db 0 db 0 db 1 code db d db c db b 70 rs 0 r/w 0 db 0 db 0 db 0 db 0 db 0 db 0 db 0 db 1 70 654321 654321 654321 654321 return home clear display entry mode set display on/off control rs 0 r/w 0 db 0 db 0 db 0 db 1 db s/c code db r/l db db 70 rs 0 r/w 0 db 0 db 0 db 1 db dl db n code db f db 70 * note: don? care. * * rs 0 r/w 0 db 0 db 1 db a db a db a code db a db a 70 db a highest order bit lowest order bit db * 654321 654321 654321 cursor or display shift function set set cg ram address * note: don? care. *
hd66702 299 set dd ram address set dd ram address sets the dd ram address binary aaaaaaa into the address counter. data is then written to or read from the mpu for dd ram. however, when n is 0 (1-line display), aaaaaaa can be 00h to 4fh. when n is 1 (2-line display), aaaaaaa can be 00h to 27h for the first line, and 40h to 67h for the second line. read busy flag and address read busy flag and address reads the busy flag (bf) indicating that the system is now internally operating on a previously received instruction. if bf is 1, the internal operation is in progress. the next instruction will not be accepted until bf is reset to 0. check the bf status before the next write operation. at the same time, the value of the address counter in binary aaaaaaa is read out. this address counter is used by both cg and dd ram addresses, and its value is determined by the previous instruction. the address contents are the same as for instructions set cg ram address and set dd ram address. table 8 shift function s/c r/l 0 0 shifts the cursor position to the left. (ac is decremented by one.) 0 1 shifts the cursor position to the right. (ac is incremented by one.) 1 0 shifts the entire display to the left. the cursor follows the display shift. 1 1 shifts the entire display to the right. the cursor follows the display shift. table 9 function set no. of display character duty n f lines font factor remarks 001 5 7 dots 1/8 011 5 10 dots 1/11 1 * 25 7 dots 1/16 cannot display two lines for 5 10 dot character font. note: * indicates don? care.
figure 16 cursor and blinking figure 17 300 hd66702 cursor 5 7 dot character font 5 10 dot character font alternating display blink display example cursor display example rs 0 r/w 0 db 1 db a db a db a db a code db a db a db a 70 highest order bit lowest order bit rs 0 r/w 1 db bf db a db a db a db a code db a db a db a 70 highest order bit lowest order bit 654321 654321 set dd ram address read busy flag and address
hd66702 301 write data to cg or dd ram write data to cg or dd ram writes 8-bit binary data dddddddd to cg or dd ram. to write into cg or dd ram is determined by the previous specification of the cg ram or dd ram address setting. after a write, the address is automatically incremented or decremented by 1 according to the entry mode. the entry mode also determines the display shift. read data from cg or dd ram read data from cg or dd ram reads 8-bit binary data dddddddd from cg or dd ram. the previous designation determines whether cg or dd ram is to be read. before entering this read instruction, either cg ram or dd ram address set instruction must be executed. if not executed, the first read data will be invalid. when serially executing read instructions, the next address data is normally read from the second read. the address set instructions need not be executed just before this read instruction when shifting the cursor by the cursor shift instruction (when reading out dd ram). the operation of the cursor shift instruction is the same as the set dd ram address instruction. after a read, the entry mode automatically increas- es or decreases the address by 1. however, display shift is not executed regardless of the entry mode. note: the address counter (ac) is automatically incremented or decremented by 1 after the write instructions to cg ram or dd ram are executed. the ram data selected by the ac cannot be read out at this time even if read instructions are executed. therefore, to correctly read data, execute either the address set instruction or cursor shift instruction (only with dd ram), then just before reading the desired data, execute the read instruction from the second time the read instruction is sent. figure 18 rs 1 r/w 1 db d db d db d db d db d code db d db d db d 70 higher order bits lower order bits rs 1 r/w 0 db d db d db d db d db d code db d db d db d 70 higher order bits lower order bits 654321 654321 read data from cg or dd ram write data to cg or dd ram
figure 19 8-bit mpu interface figure 20 hd6805 interface figure 21 hd6301 interface 302 hd66702 vma ? a a r/w d to d 15 0 7 0 e rs r/w db to db 7 0 com to com seg to seg 16 100 8 hd6800 hd66702 lcd 1 16 1 100 a to a c c c 7 0 1 2 7 0 16 100 hd6805 hd66702 8 0 db to db e rs r/w lcd com to com seg to seg 1 16 1 100 8 16 100 lcd p p p 34 35 36 p to p 17 10 rs r/w e db to db 7 0 hd66702 hd6301 com to com seg to seg 1 16 1 100
hd66702 303 interfacing the hd66702 interface to mpus interfacing to an 8-bit mpu through a pia see figure 23 for an example of using a pia or i/o port (for a single-chip microcomputer) as an interface device. the input and output of the device is ttl compatible. in this example, pb 0 to pb 7 are connected to the data bus db 0 to db 7 , and pa 0 to pa 2 are connected to e, r/ w , and rs, respectively. pay careful attention to the timing relationship between e and the other signals when reading or writing data using a pia for the interface. figure 22 example of busy flag check timing sequence figure 23 example of interface to hd68b00 using pia (hd68b21) rs r/w e internal operation db 7 functioning data busy busy not busy data instruction write busy flag check busy flag check busy flag check instruction write 8 8 16 100 a a a a a r/w db to db vma ?2 15 14 13 1 0 7 0 cs cs cs rs rs r/w e d to d 2 1 0 1 0 07 pa pa pa pb to pb 2 1 0 7 0 rs r/w e db to db 7 0 com to com seg to seg lcd hd68b00 (8-bit cpu) hd68b21 (pia) hd66702 1 16 1 100
304 hd66702 interfacing to a 4-bit mpu the hd66702 can be connected to the i/o port of a 4-bit mpu. if the i/o port has enough bits, 8-bit data can be transferred. otherwise, one data transfer must be made in two operations for 4-bit data. in this case, the timing sequence becomes somewhat complex. (see figure 24.) see figure 25 for an interface example to the hmcs43c. note that two cycles are needed for the busy flag check as well as for the data transfer. the 4-bit operation is selected by the program. figure 24 example of 4-bit data transfer timing sequence figure 25 example of interface to hmcs43c rs r/w e internal operation db 7 ir ir busy ac not busy ac d d instruction write busy flag check busy flag check instruction write note: ir , ir are the 7th and 3rd bits of the instruction. ac is the 3rd bit of the address counter. * functioning 73 3 3 73 73 3 d d d r to r 15 14 13 13 10 rs r/w e db to db 47 com to com seg to seg 4 100 16 lcd hmcs43c (hitachi 4-bit single-chip microcontroller) hd66702 1 16 1 100
hd66702 305 interface to liquid crystal display character font and number of lines: the hd66702 can perform two types of displays, 5 7 dot and 5 10 dot character fonts, each with a cursor. up to two lines are displayed for 5 7 dots and one line for 5 10 dots. therefore, a total of three types of common signals are available (table 10). the number of lines and font types can be selected by the program. (see table 7, instructions.) connection to hd66702 and liquid crystal display: see figure 26 for the connection examples. table 10 common signals number of lines character font number of common signals duty factor 15 7 dots + cursor 8 1/8 15 10 dots + cursor 11 1/11 25 7 dots + cursor 16 1/16 figure 26 liquid crystal display and hd66702 connections com com seg seg com com seg seg hd66702 example of a 5 7 dot, 20-character 1-line display (1/4 bias, 1/8 duty cycle) example of a 5 10 dot, 20-character 1-line display (1/4 bias, 1/8 duty cycle) hd66702 1 8 1 100 1 11 1 100
306 hd66702 since five segment signal lines can display one digit, one hd66702 can display up to 20 digits for a 1-line display and 40 digits for a 2-line display. the examples in figure 26 have unused common signal pins, which always output non-selection waveforms. when the liquid crystal display panel has unused extra scanning lines, connect the extra scanning lines to these common signal pins to avoid any undesirable effects due to crosstalk during the floating state (figure 28). figure 27 liquid crystal display and hd66702 connections (cont) figure 28 using com 9 to avoid crosstalk on unneeded scanning line com com seg seg hd66702 com com example of a 5 7 dot, 20-character 2-line display (1/5 bias, 1/16 duty cycle) 1 8 1 100 9 16 com com seg seg hd66702 com 5 7 dot, 20-character 1-line display (1/4 bias, 1/8 duty cycle) 1 8 1 100 9
hd66702 307 connection of changed matrix layout: in the preceding examples, the number of lines cor- respond to the scanning lines. however, the following display examples (figure 29) are made possible by altering the matrix layout of the liquid crystal display panel. in either case, the only change is the layout. the display characteristics and the number of liquid crystal display characters depend on the number of common signals or on duty factor. note that the display data ram (dd ram) addresses for 10 characters 2 lines and for 40 characters 1 line are the same as in figure 27. figure 29 changed matrix layout displays com com seg seg com com hd66702 5 7 dot, 40-character 1-line display (1/5 bias, 1/16 duty cycle) seg seg com com seg seg 5 7 dot, 10-character 2-line display (1/4 bias, 1/8 duty cycle) 1 8 1 100 9 16 1 50 1 8 51 100
308 hd66702 power supply for liquid crystal display drive various voltage levels must be applied to pins v 1 to v 5 of the hd66702 to obtain the liquid crystal display drive waveforms. the voltages must be changed according to the duty factor (table 11). v lcd is the peak value for the liquid crystal display drive waveforms, and resistance dividing provides voltages v 1 to v 5 (figure 30). table 11 duty factor and power supply for liquid crystal display drive duty factor 1/8, 1/11 1/16 bias power supply 1/4 1/5 v 1 v cc ?/4 v lcd v cc ?/5 v lcd v 2 v cc ?/2 v lcd v cc ?/5 v lcd v 3 v cc ?/2 v lcd v cc ?/5 v lcd v 4 v cc ?/4 v lcd v cc ?/5 v lcd v 5 v cc ? lcd v cc ? lcd figure 30 drive voltage supply example v v v v cc 1 4 5 v v 2 3 v v v v v v cc 1 2 3 4 5 r r r r vr ? v v (+5 v) cc ? v v (+5 v) cc r r r r r vr v lcd v lcd 1/4 bias (1/8, 1/11 duty cycle) 1/5 bias (1/16, duty cycle)
hd66702 309 relationship between oscillation frequency and liquid crystal display frame frequency the liquid crystal display frame frequencies of figure 31 apply only when the oscillation fre- quency is 320 khz (one clock pulse of 3.125 s). figure 31 frame frequency 1 2 3 4 8 1 2 1 2 3 4 11 1 2 1 2 3 4 16 1 2 400 clocks 400 clocks 200 clocks 1 frame 1 frame 1 frame 1/8 duty cycle 1/11 duty cycle 1/16 duty cycle v v v (v ) v v cc 1 2 3 4 5 v v v (v ) v v cc 1 2 3 4 5 v v v v v v cc 1 2 3 4 5 com1 com1 com1 1 frame = 3.125 ? 400 8 = 10000 ? = 10 ms frame frequency = = 100 hz 1 10 ms 1 frame = 3.125 s 400 11 = 13750 s = 13.75 ms frame frequency = = 72.7 hz 1 13.75 ms 1 frame = 3.125 s 200 16 = 10000 s = 10 ms frame frequency = = 100 hz 1 10 ms
310 hd66702 connection with hd44100 driver by externally connecting an hd44100 liquid crystal display driver to the hd66702, the number of display digits can be increased. the hd44100 is used as a segment signal driver when connected to the hd66702. the hd44100 can be directly connected to the hd66702 since it supplies cl 1 , cl 2 , m, and d signals and power for the liquid crystal display drive (figure 32). caution: the connection of voltage supply pins v 1 through v 6 for the liquid crystal display drive is somewhat complicated. the ext pin must be fixed low if the hd44100 is to be connected to the hd66702. up to eight hd44100 units can be connected for a 1-line display (duty factor 1/8 or 1/11) and up to three units for a 2-line display (duty factor 1/16). the ram size limits the hd66702 to a maximum of 80 character display digits. the connection method for both 1-line and 2-line displays or for 5 7 and 5 10 dot character fonts can remain the same (figure 32). figure 32 example of connecting hd44100hs to hd66702 v v v v v v v gnd v m cl cl 6 5 4 3 2 1 ee cc 2 1 com ?om (com ?om ) seg ?eg d ext cl cl m v gnd v v v 1 2 cc 2 3 5 16 (8) 100 40 40 40 dot-matrix liquid crystal display panel dl fcs shl shl 1 1 2 dl fcs shl shl 1 1 2 dl fcs shl shl 1 1 2 dl dr 2 1 dl dr 2 1 dr 2 dr 2 y y 40 y y 40 y y 40 hd44100 hd44100 hd44100 v v v v v v v gnd v m cl cl 6 5 4 3 2 1 ee cc 2 1 v v v v v v v gnd v m cl cl 6 5 4 3 2 1 ee cc 2 1 hd66702 11 1 1 1 16 8 1 100 dl dr 2 1 dr 2
hd66702 311 instruction and display correspondence 8-bit operation, 20-digit 1-line display with internal reset refer to table 12 for an example of an 8-bit 1- line display in 8-bit operation. the hd66702 functions must be set by the function set instruction prior to the display. since the display data ram can store data for 80 characters, as explained before, the ram can be used for displays such as for advertising when combined with the display shift operation. since the display shift operation changes only the display position with dd ram contents un- changed, the first display data entered into dd ram can be output when the return home operation is performed. 4-bit operation, 20-digit 1-line display with internal reset the program must set all functions prior to the 4-bit operation (table 13). when the power is turned on, 8-bit operation is automatically selected and the first write is performed as an 8- bit operation. since db 0 to db 3 are not connected, a rewrite is then required. however, since one operation is completed in two accesses for 4-bit operation, a rewrite is needed to set the functions (see table 13). thus, db 4 to db 7 of the function set instruction is written twice. 8-bit operation, 20-digit 2-line display for a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. thus, if there are only 20 characters in the first line, the dd ram address must be again set after the 20th character is completed. (see table 14.) note that the display shift operation is per- formed for the first and second lines. in the example of table 14, the display shift is per- formed when the cursor is on the second line. however, if the shift operation is performed when the cursor is on the first line, both the first and second lines move together. if the shift is repeated, the display of the second line will not move to the first line. the same display will only shift within its own line for the number of times the shift is repeated. note: when using the internal reset, the electrical characteristics in the power supply con- ditions using internal reset circuit table must be satisfied. if not, the lcd-ii/e20 must be initialized by instructions. (because the internal reset does not function correctly when v cc is 3 v, it must always be ini- tialized by software.) see the section, initializing by instruction.
table 12 8-bit operation, 20-digit 1-line display example with internal reset step instruction no. rs r/ w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 display operation 1 power supply on (the hd66702 is initialized by initialized. no display. the internal reset circuit) 2 function set sets to 8-bit operation and 00001100 ** selects 1-line display and character font. (number of display lines and character fonts cannot be changed after step #2.) 3 display on/off control turns on display and cursor. 0000001110 entire display is in space mode because of initialization. 4 entry mode set sets mode to increment the 0000000110 address by one and to shift the cursor to the right at the time of write to the dd/cg ram. display is not shifted. 5 write data to cg ram/dd ram writes h. dd ram has 1001001000 already been selected by initialization when the power was turned on. the cursor is incremented by one and shifted to the right. 6 write data to cg ram/dd ram writes i. 1001001001 7 8 write data to cg ram/dd ram writes i. 1001001001 9 entry mode set sets mode to shift display at 0000000111 the time of write. 10 write data to cg ram/dd ram writes a space. 1000100000 312 hd66702 _ _ h_ hi_ hitachi_ hitachi_ itachi _
table 12 8-bit operation, 20-digit 1-line display example with internal reset (cont) step instruction no. rs r/ w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 display operation 11 write data to cg ram/dd ram writes m. 1001001101 12 13 write data to cg ram/dd ram writes o. 1001001111 14 cursor or display shift shifts only the cursor position 00000100 ** to the left. 15 cursor or display shift shifts only the cursor position 00000100 ** to the left. 16 write data to cg ram/dd ram writes c over k. 1001000011 the display moves to the left. 17 cursor or display shift shifts the display and cursor 00000111 ** position to the right. 18 cursor or display shift shifts the display and cursor 00000101 ** position to the right. 19 write data to cg ram/dd ram writes m. 1001001101 20 21 return home returns both display and cursor 0000000010 to the original position (address 0). hd66702 313 tachi m_ microko_ microko _ microko _ icroco _ microco _ microco_ icrocom_ hitachi _
table 13 4-bit operation, 20-digit 1-line display example with internal reset step instruction no. rs r/ w db 7 db 6 db 5 db 4 display operation 1 power supply on (the hd66702 is initialized by initialized. no display. the internal reset circuit) 2 function set sets to 4-bit operation. 000010 in this case, operation is handled as 8 bits by initializa- tion, and only this instruction completes with one write. 3 function set sets 4-bit operation and selects 000010 1-line display and 5 7 dot 0000 ** character font. 4-bit operation starts from this step and resetting is necessary. (number of display lines and character fonts cannot be changed after step #3.) 4 display on/off control turns on display and cursor. 000000 entire display is in space mode 001110 because of initialization. 5 entry mode set sets mode to increment the 000000 address by one and to shift the 000110 cursor to the right at the time of write to the dd/cg ram. display is not shifted. 6 write data to cg ram/dd ram writes h. 100100 the cursor is incremented by 101000 one and shifts to the right. note: the control is the same as for 8-bit operation beyond step #6. 314 hd66702 _ _ h_
table 14 8-bit operation, 20-digit 2-line display example with internal reset step instruction no. rs r/ w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 display operation 1 power supply on (the hd66702 is initialized by initialized. no display. the internal reset circuit) 2 function set sets to 8-bit operation and 00001110 ** selects 2-line display and 5 7 dot character font. 3 display on/off control turns on display and cursor. 0000001110 all display is in space mode because of initialization. 4 entry mode set sets mode to increment the 0000000110 address by one and to shift the cursor to the right at the time of write to the dd/cg ram. display is not shifted. 5 write data to cg ram/dd ram writes h. dd ram has 1001001000 already been selected by initialization when the power was turned on. the cursor is incremented by one and shifted to the right. 6 7 write data to cg ram/dd ram writes i. 1001001001 8 set dd ram address sets ram address so that the 0011000000 cursor is positioned at the head of the second line. hd66702 315 _ _ h_ hitachi_ hitachi _
table 14 8-bit operation, 20-digit 2-line display example with internal reset (cont) step instruction no. rs r/ w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 display operation 9 write data to cg ram/dd ram writes m. 1001001101 10 11 write data to cg ram/dd ram writes o. 1001001111 12 entry mode set sets mode to shift display at 0000000111 the time of write. 13 write data to cg ram/dd ram writes m. display is shifted to 1001001101 the right. the first and second lines both shift at the same time. 14 15 return home returns both display and cursor 0000000010 to the original position (address 0). 316 hd66702 hitachi m_ hitachi microco_ hitachi microco_ itachi icrocom_ hitachi microcom _
hd66702 317 initializing by instruction if the power supply conditions for correctly oper- ating the internal reset circuit are not met, initialization by instructions becomes necessary. refer to figures 33 and 34 for the procedures on 8- bit and 4-bit initializations, respectively. figure 33 8-bit interface power on wait for more than 15 ms after v rises to 4.5 v wait for more than 4.1 ms wait for more than 100 ? rs 0 r/w 0 db 0 db 0 db 1 db 1 db db db db 76543210 * * * * rs 0 r/w 0 db 0 db 0 db 1 db 1 db db db db 76543210 * * * * rs 0 r/w 0 db 0 db 0 db 1 db 1 db db db db 76543210 * * * * rs 0 r/w 0 db 0 db 0 db 1 db 1 db n db f db db 76543210 * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 i/d 0 1 s initialization ends bf cannot be checked before this instruction. function set (interface is 8 bits long.) bf cannot be checked before this instruction. function set (interface is 8 bits long.) bf cannot be checked before this instruction. function set (interface is 8 bits long.) bf can be checked after the following instructions. when bf is not checked, the waiting time between instructions is longer than the execution instuction time. (see table 7.) function set (interface is 8 bits long. specify the number of display lines and character font.) the number of display lines and character font cannot be changed after this point. display off display clear entry mode set wait for more than 40 ms after v rises to 2.7 v cc cc
figure 34 4-bit interface 318 hd66702 initialization ends wait for more than 15 ms after v rises to 4.5 v wait for more than 40 ms after v rises to 2.7 v cc cc bf cannot be checked before this instruction. function set (interface is 8 bits long.) bf cannot be checked before this instruction. function set (interface is 8 bits long.) bf cannot be checked before this instruction. function set (interface is 8 bits long.) db 0 db 0 db 1 db 1 7654 rs 0 r/w 0 wait for more than 4.1 ms db 0 db 0 db 1 db 1 7654 rs 0 r/w 0 wait for more than 100 ? db 0 db 0 db 1 db 1 7654 rs 0 r/w 0 db 0 db 0 db 1 db 0 7654 rs 0 r/w 0 0 n 0 1 0 0 0 0 0 f 0 0 0 0 0 1 1 0 0 0 0 0 i/d 0 0 0 0 1 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * bf can be checked after the following instructions. when bf is not checked, the waiting time between instructions is longer than the execution instuction time. (see table 7.) function set (set interface to be 4 bits long.) interface is 8 bits in length. display off display clear entry mode set function set (interface is 4 bits long. specify the number of display lines and character font.) the number of display lines and character font cannot be changed after this point. power on
[low voltage version] absolute maximum ratings* item symbol unit value notes power supply voltage (1) v cc v ?.3 to +7.0 1 power supply voltage (2) v cc ? 5 v ?.3 to +8.5 2 input voltage v t v ?.3 to v cc +0.3 1 operating temperature t opr ? ?0 to +75 3 storage temperature t stg ? ?5 to +125 4 note: * if the lsi is used above these absolute maximum ratings, it may become permanently damaged. using the lsi within the following electrical characteristic limits is strongly recommended for normal operation. if these electrical characteristic conditions are also exceeded, the lsi will malfunction and cause poor reliability. hd66702 319
dc characteristics (v cc = 2.7 to 5.5 v, t a = ?0 to +75? *3 ) item symbol min typ max unit test condition notes * input high voltage (1) v ih1 0.7v cc ? cc v 6, 17 (except osc 1 ) input low voltage (1) v il1 ?.3 0.55 v 6, 17 (except osc 1 ) input high voltage (2) v ih2 0.7v cc ? cc v15 (osc 1 ) input low voltage (2) v il2 0.2v cc v15 (osc 1 ) output high voltage (1) v oh1 0.75v cc vi oh = 0.1 ma 7 (d 0 ? 7 ) output low voltage (1) v ol1 0.2v cc vi ol = 0.1 ma 7 (d 0 ? 7 ) output high voltage (2) v oh2 0.8v cc vi oh = 0.04 ma 8 (except d 0 ? 7 ) output low voltage (2) v ol2 0.2v cc vi ol = 0.04 ma 8 (except d 0 ? 7 ) driver on resistance r com 20 k id = 0.05 ma (com) 13 (com) driver on resistance r seg 30 k id = 0.05 ma (seg) 13 (seg) input leakage current i li ? 1 a v in = 0 to v cc 9 pull-up mos current ?p 10 50 120 a v cc = 3 v (rs, r/ w , d 0 ? 7 ) power supply current i cc 0.15 0.30 ma r f oscillation, 10, 14 external clock v cc = 3v, f osc = 270 khz lcd voltage v lcd1 3.0 8.3 v v cc ? 5 , 1/5 bias 16 v lcd2 3.0 8.3 v v cc ? 5 , 1/4 bias 16 note: * refer to the electrical characteristics notes section following these tables. 320 hd66702
ac characteristics (v cc = 2.7 to 5.5 v, t a = ?0 to +75? *3 ) clock characteristics item symbol min typ max unit test condition notes * external external clock frequency f cp 125 270 410 khz 11 clock external clock duty duty 45 50 55 % operation external clock rise time t rcp 0.2 s external clock fall time t fcp 0.2 s r f clock oscillation frequency f osc 240 320 390 khz r f = 56 k 12 oscillation v cc = 3 v note: * refer to the electrical characteristics notes section following these tables. bus timing characteristics write operation item symbol min typ max unit test condition enable cycle time t cyce 1000 ns figure 35 enable pulse width (high level) pw eh 450 enable rise/fall time t er , t ef 25 address set-up time (rs, r/ w to e) t as 40 address hold time t ah 20 data set-up time t dsw 195 data hold time t h 10 read operation item symbol min typ max unit test condition enable cycle time t cyce 1000 ns figure 36 enable pulse width (high level) pw eh 450 enable rise/fall time t er , t ef 25 address set-up time (rs, r/ w to e) t as 40 address hold time t ah 20 data delay time t ddr 350 data hold time t dhr 10 hd66702 321
interface timing characteristics with external driver item symbol min typ max unit test condition clock pulse width high level t cwh 800 ns figure 37 low level t cwl 800 clock set-up time t csu 500 data set-up time t su 300 data hold time t dh 300 m delay time t dm ?000 1000 clock rise/fall time t ct 200 power supply conditions using internal reset circuit item symbol min typ max unit test condition power supply rise time t rcc 0.1 10 ms figure 38 power supply off time t off 1 [standard voltage version] absolute maximum ratings* item symbol unit value notes power supply voltage (1) v cc v ?.3 to +7.0 1 power supply voltage (2) v cc ? 5 v ?.3 to +8.5 2 input voltage v t v ?.3 to v cc +0.3 1 operating temperature t opr ? ?0 to +75 3 storage temperature t stg ? ?5 to +125 4 note: * if the lsi is used above these absolute maximum ratings, it may become permanently damaged. using the lsi within the following electrical characteristic limits is strongly recommended for normal operation. if these electrical characteristic conditions are also exceeded, the lsi will malfunction and cause poor reliability. refer to the electrical characteristics notes section following these tables. 322 hd66702
dc characteristics (v cc = 5 v 10%, t a = ?0 to +75? *3 ) item symbol min typ max unit test condition notes * input high voltage (1) v ih1 2.2 v cc v 6, 17 (except osc 1 ) input low voltage (1) v il1 ?.3 0.6 v 6, 17 (except osc 1 ) input high voltage (2) v ih2 v cc ?.0 v cc v15 (osc 1 ) input low voltage (2) v il2 1.0 v 15 (osc 1 ) output high voltage (1) v oh1 2.4 v i oh = 0.205 ma 7 (d 0 ? 7 ) output low voltage (1) v ol1 0.4 v i ol = 1.6 ma 7 (d 0 ? 7 ) output high voltage (2) v oh2 0.9 v cc vi oh = 0.04 ma 8 (except d 0 ? 7 ) output low voltage (2) v ol2 0.1 v cc vi ol = 0.04 ma 8 (except d 0 ? 7 ) driver on resistance r com 20 k id = 0.05 ma (com) 13 (com) driver on resistance r seg 30 k id = 0.05 ma (seg) 13 (seg) input leakage current i li ? 1 a v in = 0 to v cc 9 pull-up mos current ? p 50 125 250 a v cc = 5 v (rs, r/ w , d 0 ? 7 ) power supply current i cc 0.35 0.60 ma r f oscillation, 10, 14 external clock v cc = 5 v, f osc = 270 khz lcd voltage v lcd1 3.0 8.3 v v cc ? 5 , 1/5 bias 16 v lcd2 3.0 8.3 v v cc ? 5 , 1/4 bias 16 note: * refer to the electrical characteristics notes section following these tables. hd66702 323
ac characteristics (v cc = 5 v 10%, t a = ?0 to +75? *3 ) clock characteristics item symbol min typ max unit test condition notes * external external clock frequency f cp 125 270 410 khz 11 clock external clock duty duty 45 50 55 % 11 operation external clock rise time t rcp 0.2 s 11 external clock fall time t fcp 0.2 s 11 r f clock oscillation frequency f osc 220 320 420 khz r f = 68 k 12 oscillation v cc = 5 v note: * refer to the electrical characteristics notes section following these tables. bus timing characteristics write operation item symbol min typ max unit test condition enable cycle time t cyce 1000 ns figure 35 enable pulse width (high level) pw eh 450 enable rise/fall time t er , t ef 25 address set-up time (rs, r/ w to e) t as 40 address hold time t ah 10 data set-up time t dsw 195 data hold time t h 10 read operation item symbol min typ max unit test condition enable cycle time t cyce 1000 ns figure 36 enable pulse width (high level) pw eh 450 enable rise/fall time t er , t ef 25 address set-up time (rs, r/ w to e) t as 40 address hold time t ah 10 data delay time t ddr 320 data hold time t dhr 20 324 hd66702
interface timing characteristics with external driver item symbol min typ max unit test condition clock pulse width high level t cwh 800 ns figure 37 low level t cwl 800 clock set-up time t csu 500 data set-up time t su 300 data hold time t dh 300 m delay time t dm ?000 1000 clock rise/fall time t ct 100 power supply conditions using internal reset circuit item symbol min typ max unit test condition power supply rise time t rcc 0.1 10 ms figure 38 power supply off time t off 1 hd66702 325
electrical characteristics notes 1. all voltage values are referred to gnd = 0 v. 2. v cc 3 v 1 3 v 2 3 v 3 3 v 4 3 v 5 must be maintained. 3. for die products, specified up to 75?. 4. for die products, specified by the die shipment specification. 5. the following four circuits are i/o pin configurations except for liquid crystal display output. 326 hd66702 v cc pmos nmos v cc v cc pmos nmos (pull up mos) pmos v cc pmos nmos v cc nmos nmos v cc pmos nmos (output circuit) (tristate) output enable data (pull-up mos) i/o pin pins: db ?b (mos with pull-up) 07 input pin pin: e (mos without pull-up) pins: rs, r/w (mos with pull-up) output pin pins: cl , cl , m, d 12 v cc (input circuit) pmos pmos input enable
6. applies to input pins and i/o pins, excluding the osc 1 pin. 7. applies to i/o pins. 8. applies to output pins. 9. current flowing through pull?p moss, excluding output drive moss. 10. input/output current is excluded. when input is at an intermediate level with cmos, the excessive current flows through the input circuit to the power supply. to avoid this from happening, the input level must be fixed high or low. 11. applies only to external clock operation. 12. applies only to the internal oscillator operation using oscillation resistor r f . hd66702 327 oscillator osc osc 0.7 v 0.5 v 0.3 v cc cc cc th tl t rcp t fcp duty = 100% th th + tl open 1 2 osc osc r f r : r : f f 56 k 2% (when v = 3 v) 68 k 2% (when v = 5 v) w w 500 400 300 200 100 50 100 150 (68) r (k ) f w f (khz) osc v = 5 v cc typ. 500 400 300 200 100 50 100 150 (56) r (k ) f w f (khz) osc v = 3 v cc typ. 1 2 since the oscillation frequency varies depending on the osc and osc pin capacitance, the wiring length to these pins should be minimized. 1 2 cc cc max. min. max. min.
13. r com is the resistance between the power supply pins (v cc , v 1 , v 4 , v 5 ) and each common signal pin (com 1 to com 16 ). r seg is the resistance between the power supply pins (v cc , v 2 , v 3 , v 5 ) and each segment signal pin (seg 1 to seg 100 ). 14. the following graphs show the relationship between operation frequency and current consumption. 15. applies to the osc 1 pin. 16. each com and seg output voltage is within 0.15 v of the lcd voltage (v cc , v 1 , v 2 , v 3 , v 4 , v 5 ) when there is no load. 17. the test pin should be fixed to gnd and the ext pin should be fixed to v cc or gnd. 328 hd66702 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 100 200 300 400 500 v = 5 v cc 0 100 200 300 400 500 v = 3 v cc f or f (khz) f or f (khz) osc osc cp cp i (ma) cc i (ma) cc max. typ. max. typ.
load circuits data bus db 0 to db 7 external driver control signal: cl1, cl2, d, m hd66702 329 for v = 5 v cc test point 90 pf 11 k w v = 5 v cc 2.4 k w 1s2074 diodes h for v = 3 v cc test point 50 pf test point 30 pf
timing characteristics figure 35 write operation figure 36 read operation 330 hd66702 rs r/w e db to db 07 v v ih1 il1 v v ih1 il1 t as t ah v il1 v il1 t ah pw eh t ef v v ih1 il1 v v ih1 il1 t er t dsw h t v v ih1 il1 v v ih1 il1 t cyce v il1 valid data rs r/w e db to db 07 v v ih1 il1 v v ih1 il1 t as t ah v ih1 v ih1 t ah pw eh t ef v v ih1 il1 v v ih1 il1 t ddr dhr t t er v il1 v v oh1 ol1 v v oh1 ol1 valid data t cyce
figure 37 interface timing with external driver figure 38 internal power supply reset hd66702 331 cl cl d m v oh2 v oh2 v ol2 t ct t cwh t cwh t csu v oh2 t csu t cwl t ct t dh t su v ol2 t dm v v oh2 ol2 1 2 v ol2 v cc 0.2 v 2.7 v/4.5 v * 2 0.2 v 0.2 v t rcc t off * 1 0.1 ms t 10 ms rcc t 1 ms 3 off notes: 1. 2. 3. t compensates for the power oscillation period caused by momentary power supply oscillations. specified at 4.5 v for 5-v operation, and at 2.7 v for 3-v operation. when the above condition cannot be satisfied, the internal reset circuit will not operate normally. in this case, the lsi must be initialized by software. (refer to the initializing by instruction section.) off

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