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1997 preliminary data sheet mos integrated circuit m pd70f3008 v854 tm 32-/16-bit single-chip microcontroller document no. u12756ej1v0ds00 (1st edition) date published august 1997 n printed in japan the m pd70f3008 has a flash memory instead of the internal mask rom of the m pd703008. because this device can be programmed by users while mounted on a board, it is ideally suited for applications involving the evaluation of systems in the development stage, small-scale production of many different products, and rapid development and time-to-market of new products. functions are described in detail in the following users manuals. be sure to read these manuals during system design. v854 users manual hardware : u11969e v850 family tm users manual architecture : u10243e features ? compatible with m pd703008 ? can be replaced with mask rom version m pd703008 for mass production of application set ? internal flash memory: 128 kbytes ordering information part number package m pd70f3008gj-33-8eu 144-pin plastic lqfp (fine pitch) (20 20 mm) the information in this document is subject to change without notice.
m pd70f3008 2 pin configuration (top view) notes 1. leave open when external clock is connected to the x1 pin. 2. connect to v ss via a resistor (r vpp ) during normal operation mode. 3. connect directly to v ss in normal operation mode. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 p87/ani15 p86/ani14 p85/ani13 p84/ani12 p83/ani11 p82/ani10 p81/ani9 p80/ani8 p77/ani7 p76/ani6 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 v dd v ss p17 p16/ti20/intp20 p15/to20 p14/ti1/intp14 p13/intp13 p12/intp12 p11/intp11 p10/intp10 p07/ti0/intp05 p06/tclr0/intp04 p05/intp03 p04/intp02 p03/intp01 p02/intp00 p01/to01 p00/to00 v dd v ss bv dd clkout wait p96/hldrq p95/hldak p94/astb p93/dstb/rd p92/r/w/wrh p91/uben p90/lben/wrl p67/a23 p66/a22 p65/a21 p64/a20 p63/a19 p62/a18 p61/a17 p60/a16 bv ss p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 bv dd bv ss v pp note 2 v dd mode0 mode1 mode2 note 3 p140 p141 p142 p143 p144 p145 p146 p147 p100/pwm0 p101/pwm1 p102/pwm2 p103/pwm3 v ss v dd p130/rtp0 p131/rtp1 p132/rtp2 p133/rtp3 p134/rtp4 p135/rtp5 p136/rtp6 p137/rtp7 p20/nmi p21/intp30 p22/adtrg p23/intp50 p24/intp51 p25/intp52 p26/intp53 v dd bv ss cv dd cv ss cksel pllsel x2 note 1 x1 reset p127/clo p126 p125/sck3 p124/si3 p123/so3 p122/sck2 p121/si2 p120/so2 p36 p35/sck1 p34/si1 p33/so1 p32/sck0 p31/si0/rxd p30/so0/txd v ss v dd p110/to21 p111/ti21/intp21 p112/to22 p113/ti22/intp22 p114/to23 p115/ti23/intp23 p116/to24 p117/ti24/intp24 av ref av ss av dd 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
m pd70f3008 3 p40 to p47 : port4 p50 to p57 : port5 p60 to p63 : port6 p70 to p77 : port7 p80 to p87 : port8 p90 to p96 : port9 p100 to p103 : port10 p110 to p117 : port11 p120 to p127 : port12 p130 to p137 : port13 p140 to p147 : port14 pllsel : pll select pwm0 to pwm3 : pulse width modulation rd : read reset : reset rtp0 to rtp7 : real-time port r/w : read/write status rxd : receive data sck0 to sck3 : serial clock si0 to si3 : serial input so0 to so3 : serial output tclr0 : timer clear ti0, ti1, : timer input ti20 to ti24 to00, to01, : timer output to20 to to24 txd : transmit data uben : upper byte enable v dd : power supply v pp : programming power supply v ss : ground wait : wait wrh : write strobe high level data wrl : write strobe low level data x1, x2 : crystal pin identification a16 to a23 : address bus ad0 to ad15 : address/data bus adtrg : ad trigger input ani0 to ani15 : analog input astb : address strobe av dd : analog v dd av ref : analog reference voltage av ss : analog v ss bv dd : power supply for bus interface bv ss : ground for bus interface cksel : clock select clkout : clock output clo : clock output (divided) cv dd : power supply for clock generator cv ss : ground for clock generator dstb : data strobe hldak : hold acknowledge hldrq : hold request intp00 to : interrupt request from peripherals intp05, intp10 to intp14, intp20 to intp24, intp30, intp50 to intp53 lben : lower byte enable mode0 to : mode mode2 nmi : non-maskable interrupt request p00 to p07 : port0 p10 to p17 : port1 p20 to p26 : port2 p30 to p36 : port3
m pd70f3008 4 internal block diagram nmi to00, to01 to20 to to24 rtp0 to rtp7 tclr0 ti0, ti1 ti20 to ti24 intp00 to intp05 intp10 to intp14 intp20 to intp24 intp30 intp50 to intp53 intc csi0/uart rtp pwm0 to pwm3 pwm rpu flash memory 128 kb ram 4 kb cpu pc 32-bit barrel shifter system register general register 32 bits x 32 alu multiplier 16 x 16 ? 32 port p140 to p147 p130 to p137 p120 to p127 p110 to p117 p100 to p103 p90 to p96 p80 to p87 p70 to p77 p60 to p67 p50 to p57 p40 to p47 p30 to p36 p21 to p26 p20 p10 to p17 p00 to p07 cg bcu instruction queue astb dstb r/w uben lben wait a16 to a23 ad0 to ad15 hldrq hldak rd wrl wrh v dd v ss bv dd bv ss cv dd cv ss v pp clkout x1 x2 cksel clo pllsel mode0 to mode2 reset brg0 so0/txd si0/rxd sck0 csi1 brg1 so1 si1 sck1 csi2 brg2 so2 si2 sck2 csi3 brg3 so3 si3 sck3 a/d converter adtrg ani0 to ani15 av ref av ss av dd
m pd70f3008 5 contents 1. differences between m pd703008 and m pd70f3008 6 2. pin functions 7 2.1 port pins 7 2.2 non-port pins 9 2.3 i/o circuit of pins and recommended connections of unused pins 12 3. flash memory programming 15 3.1 selecting communication mode 15 3.2 flash memory programming function 16 3.3 connecting dedicated flash programmer 16 4. electrical specifications 17 4.1 normal operating mode 17 4.2 flash memory programming mode 37 5. package drawing 39 6. recommended soldering conditions 40
m pd70f3008 6 1. differences between m pd703008 and m pd70f3008 part number m pd703008 m pd70f3008 parameter internal rom mask rom flash memory flash memory programming pin none provided (v pp ) flash memory programming mode none provided (v pp = 7.5 v, mode0 to mode2 = high-level) electrical specifications current consumption, etc. differ. (refer to each product data sheet.) others nose immunity and noise radiation are different because products differ in circuit size and mask layout. cautions 1. there are differences in noise immunity and noise radiation between the prom version and mask rom version. when pre-producing an application set with the prom version and then mass-producing it with the mask rom version, be sure to conduct sufficient evalua- tions for the set using consumer samples (not engineering samples) of the mask rom version. 2. when replacing a flash memory version with a mask rom version, be sure to write the same code into the internal roms reserved area.
m pd70f3008 7 2. pin functions 2.1 port pins (1/2) pin name i/o function alternate function p00 i/o port 0. to00 p01 8-bit i/o port. to01 p02 input/output can be specified in 1-bit units. intp00 p03 intp01 p04 intp02 p05 intp03 p06 tclr0/intp04 p07 ti0/intp05 p10 i/o port 1. intp10 p11 8-bit i/o port. intp11 p12 input/output can be specified in 1-bit units. intp12 p13 intp13 p14 ti1/intp14 p15 to20 p16 ti20/intp20 p17 C p20 input port 2. nmi p21 i/o p20 is an input-only port. intp30 p22 ? p20 functions as an nmi input after a valid edge is input. adtrg p23 ? bit 0 of p2 register indicates the nmi input status. intp50 p24 p21 to p26 are a 6-bit i/o port. intp51 p25 ? input/output can be specified in 1-bit units. intp52 p26 intp53 p30 i/o port 3. so0/txd p31 7-bit i/o port. si0/rxd p32 input/output can be specified in 1-bit units. sck0 p33 so1 p34 si1 p35 sck1 p36 C p40 to p47 i/o port 4. ad0 to ad7 8-bit i/o port. input/output can be specified in 1-bit units. p50 to p57 i/o port 5. ad8 to ad15 8-bit i/o port. input/output can be specified in 1-bit units.
m pd70f3008 8 (2/2) pin name i/o function alternate function p60 to p67 i/o port 6. a16 to a23 8-bit i/o port. input/output can be specified in 1-bit units. p70 to p77 input port 7. ani0 to ani7 8-bit input-only port. p80 to p87 input port 8. ani8 to ani15 8-bit input-only port. p90 i/o port 9. lben/wrl p91 7-bit i/o port. uben p92 input/output can be specified in 1-bit units. r/w/wrh p93 dstb/rd p94 astb p95 hldak p96 hldrq p100 to p103 i/o port 10. pwm0 to pmw3 4-bit i/o port. input/output can be specified in 1-bit units. p110 i/o port 11. to21 p111 8-bit i/o port. ti21/intp21 p112 input/output can be specified in 1-bit units. to22 p113 ti22/intp22 p114 to23 p115 ti23/intp23 p116 to24 p117 ti24/intp24 p120 i/o port 12. so2 p121 8-bit i/o port. si2 p122 input/output can be specified in 1-bit units. sck2 p123 so3 p124 si3 p125 sck3 p126 C p127 clo p130 to p137 i/o port 13. rtp0 to rtp7 8-bit i/o port. input/output can be specified in 1-bit units. p140 to p147 i/o port 14. C 8-bit i/o port. input/output can be specified in 1-bit units.
m pd70f3008 9 2.2 non-port pins (1/3) pin name i/o function alternate function to00 output pulse signal output from timers 0 and 2. p00 to01 p01 to20 p15 to21 p110 to22 p112 to23 p114 to24 p116 tclr0 input external clear signal input to timer 0. p06/intp04 ti0 input external count clock input to timers 0, 1, and 2. p07/intp05 ti1 p14/intp14 ti20 p16/intp20 ti21 p111/intp21 ti22 p113/intp22 ti23 p115/intp23 ti24 p117/intp24 intp00 to intp03 input external capture trigger input to timer 0. p02 to p05 also used to input external maskable interrupt request. intp04 input external maskable interrupt request input. p06/tclr0 intp05 p07/ti0 intp10 to intp13 input external capture trigger input to timer 1. p10 to p13 also used to input external maskable interrupt request. intp14 input external maskable interrupt request input. p14/ti1 intp20 input external maskable interrupt request input. p16/ti20 intp21 p111/ti21 intp22 p113/ti22 intp23 p115/ti23 intp24 p117/ti24 intp30 input external capture trigger input to timer 3. p21 also used to input external maskable interrupt request. intp50 to intp53 input external maskable interrupt request input. p23 to p26 nmi input non-maskable interrupt request input. p20 ad0 to ad7 i/o 16-bit multiplexed address/data bus when external memory is used. p40 to p47 ad8 to ad15 p50 to p57 a16 to a23 output higher address bus when external memory is used. p60 to p67 lben output lower byte enable signal output of external data bus. p90/wrl uben higher byte enable signal output of external data bus. p91 r/w external read/write status output. p92/wrh dstb external data strobe signal output. p93/rd astb external address strobe signal output. p94
m pd70f3008 10 (2/3) pin name i/o function alternate function hldak output bus hold acknowledge output. p95 hldrq input bus hold request input. p96 so0 input serial transmit data output from csi0 to csi3 (3-wire). p30/txd so1 p33 so2 p120 so3 p123 si0 input serial receive data input to csi0 to csi3 (3-wire). p31/rxd si1 p34 si2 p121 si3 p124 sck0 i/o serial clock i/o from/to csi0 to csi3 (3-wire). p32 sck1 p35 sck2 p122 sck3 p125 txd output serial transmit data output from uart. p30/so0 rxd input serial receive data input to uart. p31/si0 pwm0 to pwm3 output pulse signal output from pwm. p100 to p103 wrl output lower byte of external data bus write strobe signal output. p90/lben wrh higher byte of external data bus write strobe signal output. p92/r/w rd output external data bus read strobe signal output. p93/dstb ani0 to ani7 input analog input to a/d converter. p70 to p77 ani8 to ani15 p80 to p87 rtp0 to rtp7 output real time output port. p130 to p137 clo output system clock output (with frequency division function). p127 cksel input input to specify clock generator operation mode. C pllsel input input to specify the number of pll multiplication. C clkout output system clock output. C wait input control signal input inserting wait state to bus cycle. C mode0 to mode2 input specifies operation mode. C reset input system reset input. C x1 input system clock oscillator connecting pins. supply external clock to x1. C x2 C C
m pd70f3008 11 (3/3) pin name i/o function alternate function adtrg input a/d converter external trigger input. p22 av ref input reference voltage input for a/d converter. C av dd C positive power supply for a/d converter. C av ss C ground for a/d converter. C bv dd C positive power supply for bus interface. C bv ss C ground for bus interface. C cv dd C positive power supply for clock generator. C cv ss C ground for clock generator. C v dd C positive power supply. C v ss C ground. C v pp C high-voltage pin for program write/verify. C
m pd70f3008 12 2.3 i/o circuit of pins and recommended connections of unused pins table 2-1 shows the i/o circuit type for each pin and the recommended connections for all unused pins. figure 2-1 shows partially simplified pin i/o circuits. when connecting a pin to v dd or v ss via a resistor, use of a resistor of 1 to 10 k w is recommended. table 2-1. i/o circuit type of each pin and recommended connections of unused pins (1/2) pin i/o circuit type recommended connections p00/to00, p01/to01 5 individually connect to v dd or v ss via resistor. p02/intp00 to p05/intp03, 5-k p06/tclr0/intp04, p07/ti0/intp05 p10/intp10 to p13/intp13, p14/ti1/intp14, p16/ti20/intp20 p15/to20, p17 5 p20/nmi 2 connect directly to v ss . p21/intp30, p22/adtrg, 5-k individually connect to v dd or v ss via resistor. p23/intp50 to p26/intp53 p30/txd/so0 5 p31/rxd/si0, p32/sck0, p34/si1 5-k p33/so1, p35/sck1 13-g p36 5 p40/ad0 to p47/ad7 5 note individually connect to bv dd or bv ss via resistor. p50/ad8 to p57/ad15 p60/a16 to p67/a23 p70/ani0 to p77/ani7 9 connect directly to v ss . p80/ani8 to p87/ani15 p90/lben/wrl, p91/uben, 5 note individually connect to bv dd or bv ss via resistor. p92/r/w/wrh, p93/dstb/rd, p94/astb, p95/hldak, p96/hldrq p100/pwm0 to p103/pwm3 5 individually connect to v dd or v ss via resistor. p110/to21, p112/to22, p114/to23, p116/to24 p111/ti21/intp21, p113/ti22/intp22, 5-k p115/ti23/intp23, p117/ti24/intp24 p120/so2 5 p121/si2, p122/sck2 5-k p123/so3 5 p124/si3, p125/sck3 5-k p126, p127/clo 5 p130/rtp0 to p137/rtp7 p140 to p147 remark open input is possible for i/o circuit types 5, 5-k. and 13-g pins.
m pd70f3008 13 table 2-1. i/o circuit type of each pin and recommended connections of unused pins (2/2) pin i/o circuit type recommended connections wait 1 note connect directly to bv dd . clkout 3 note open. mode0 to mode2 2 individually connect to v dd or v ss via resistor. reset C av ref , av ss , cv ss C connect directly to v ss . av dd , cv dd C connect directly to v dd . pllsel 1 connect directly to v dd or v ss . cksel 1 v pp C individually connect to v ss via resistor (r vpp ). note read v dd as bv dd when referring to the i/o circuit diagram.
m pd70f3008 14 figure 2-1. pin i/o circuits type 1 type 2 type 3 p-ch n-ch in v dd in schmitt trigger input with hysteresis characteristics p-ch n-ch v dd out type 5 type 5-k p-ch n-ch v dd in/out data output disable input enable p-ch n-ch v dd in/out data output disable input enable in comparator + v ref (threshold voltage) p-ch n-ch input enable type 9 type 13-g n-ch in/out data output disable input enable
m pd70f3008 15 3. flash memory programming there are the following two methods for writing a program to the flash memory. (1) on-board programming write a program to the flash memory using a dedicated flash programmer after the m pd70f3008 has been mounted on the target board. also mount a connector, etc. on the target board to communicate with the dedicated flash programmer. (2) off-board programming write a program using a dedicated adapter before the m pd70f3008 has been mounted on the target board. 3.1 selecting communication mode to write the flash memory, use a dedicated flash programmer and serial communication. select a serial communication mode from those listed in table 3-1 in the format shown in figure 3-1. each communication mode is selected by the number of v pp pulses shown in table 3-1. table 3-1. communication modes communication mode pins used number of v pp pulses csi0 sck0 (serial clock input) 0 so0 (serial data output) si0 (serial data input) csi2 sck2 (serial clock input) 2 so2 (serial data output) si2 (serial data input) uart txd (serial data output) 8 rxd (serial data input) figure 3-1. communication mode selecting format 7.5 v v dd v ss v dd v ss v pp reset
m pd70f3008 16 3.2 flash memory programming function the flash memory is written by transmitting or receiving commands and data in a selected communication mode. the major functions of flush memory programming are listed in table 3-2. table 3-2. major functions of flash memory programming function description batch erasure erases all contents of memory. block erasure erases contents of memory in 4 kbytes. batch blank check checks erased status of entire memory. data write writes flash memory based on write start address and number of data to be written (in bytes). batch verify compares all contents of memory with input data. 3.3 connecting dedicated flash programmer the dedicated flash programmer and m pd70f3008 are connected differently depending on the selected communication mode. figures 3-2 and 3-3 show the connections in the respective communication modes. figure 3-2. connection of dedicated flash programmer in uart mode figure 3-3. connection of dedicated flash programmer in csi mode clk v pp v dd v ss reset txd rxd clk v pp v dd v ss reset txd rxd dedicated flash programmer pd70f3008 m clk v pp v dd v ss reset sck so si dedicated flash programmer pd70f3008 m clk v pp v dd v ss reset sckn son sin remark n = 0, 2
m pd70f3008 17 4. electrical specifications 4.1 normal operating mode absolute maximum ratings (t a = 25 c) parameter symbol condition ratings unit supply voltage v dd v dd pin C0.5 to +4.6 v av dd av dd pin C0.5 to +4.6 v bv dd bv dd pin C0.5 to +4.6 v cv dd cv dd pin C0.5 to +4.6 v v ss v ss pin C0.5 to +0.5 v av ss av ss pin C0.5 to +0.5 v bv ss bv ss pin C0.5 to +0.5 v cv ss cv ss pin C0.5 to +0.5 v input voltage v i1 except for x1 pin, v dd = 2.7 to 3.6 v C0.5 to v dd + 0.5 v v i2 v pp pin in flash memory programming mode C0.5 to +10.0 v clock input voltage v k x1 pin, v dd = 2.7 to 3.6 v C0.5 to v dd + 1.0 v output current, low i ol 1 pin 4.0 ma total of all pins 100 ma output current, high i oh 1 pin C4.0 ma total of all pins C100 ma output voltage v o v dd = 2.7 to 3.6 v C0.5 to v dd + 0.5 v operating ambient temperature t a C40 to +85 c storage temperature t stg C65 to +150 c cautions 1. do not directly connect the output (or i/o) pins of two or more ic products, and do not directly connect them to v dd , v cc , or gnd pin. open-drain pins and open-collector pins may be directly connected to one another however. moreover, an external circuit that is designed to prevent contention of output can be connected to pins that go into a high-impedance state. 2. should the absolute maximum rating of even one of the above parameters be exceeded even momentarily, the quality of the program may be degraded. the absolute maximum ratings are, therefore, the values exceeding which the product may be physically damaged. use the product so that these values are never exceeded. the normal operating ranges of ratings and conditions in which the quality of the product is guaranteed are specified in the following dc characteristics and ac characteristics.
m pd70f3008 18 capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol condition min. typ. max. unit input capacitance c i fc = 1 mhz 15 pf i/o capacitance c io unmeasured pins returned to 0 v. 15 pf output capacitance c o 15 pf operating conditions operation mode internal operating clock frequency ( f ) operating ambient temperature (t a ) supply voltage (v dd ) direct mode 0 to 33 mhz C40 to +85 c 2.7 to 3.6 v pll mode free-running oscillation frequency to 33 mhz C40 to +85 c 2.7 to 3.6 v
m pd70f3008 19 dc characteristics note 1 (t a = C40 to +85 c, v dd = cv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = cv ss = 0 v) parameter symbol condition min. typ. max. unit input voltage, high v ih 0.7v dd v dd + 0.3 v input voltage, low v il C0.3 0.2v dd v clock input voltage, high v kh x1 0.8v dd v dd + 0.3 v clock input voltage, low v kl x1 C0.3 0.15v dd v schmitt trigger input threshold voltage v t + note 2 , rising note 3 v v t C note 2 , falling note 3 v schmitt trigger input hysteresis width v t + C v t C note 2 note 3 v output voltage, high v oh i oh = C2.5 ma 0.8v dd v output voltage, low v ol i ol = 2.5 ma 0.15v dd v input leakage current, high i lih v i = v dd 5 m a input leakage current, low i lil v i = 0 v C5 m a output leakage current, high i loh v o = v dd 5 m a output leakage current, low i lol v o = 0 v C5 m a supply current operating i dd note 3 note 3 ma in halt mode note 3 note 3 ma in idle mode note 3 note 3 m a in stop mode note 3 note 3 m a notes 1. for the following pins, the parameter v dd in the above table should be read and referred to as bv dd (on condition of 2.0 v bv dd v dd ). p40/ad0 to p47/ad7, p50/ad8 to p57/ad15, p60/a16 to p67/a23. p90/lbe/wrl, p91/ube, p92/ r/w/wrh, p93/dstb/rd, p94/astb, p95/hldak, p96/hldrq, clkout, wait 2. p02/intp00 to p05/intp03, p06/tclr0/intp04, p07/ti0/intp05, p10/intp10, p11/intp11, p12/ intp12, p13/intp13, p14/ti1/intp14, p16/ti20/intp20, p111/ti21/intp21, p113/ti22/intp22, p115/ti23/intp23, p117/ti24/intp24, p21/intp30, p22/adtrg, p23/intp50, p24/intp51, p25/ intp52, p26/intp53, p31/rxd/si0, p32/sck0, p33/so1, p34/si1, p35/sck1, p121/si2, p122/ sck2, p124/si3, p125/sck3, mode0 to mode2, reset, p20/nmi 3. under evaluation remarks 1. typ. value is a value for your reference at t a = 25 c and v dd = 3.0 v. 2. f : internal operating clock frequency
m pd70f3008 20 data retention characteristics (t a = C40 to +85 c) parameter symbol condition min. typ. max. unit data hold voltage v dddr stop mode 1.5 3.6 v data hold current i dddr v dd = v dddr note 1 note 1 m a supply voltage rise time t rvd 200 m s supply voltage fall time t fvd 200 m s supply voltage hold time t hvd 0ms (from stop mode setting) stop mode release signal input time t drel 0ns data hold input high-level voltage v ihdr note 2 0.9v dddr v dddr v data hold input low-level voltage v ildr note 2 0 0.1v dddr v notes 1. under evaluation 2. p02/intp00 to p05/intp03, p06/tclr0/intp04, p07/ti0/intp05, p10/intp10, p11/intp11, p12/ intp12, p13/intp13, p14/ti1/intp14, p16/ti20/intp20, p111/ti21/intp21, p113/ti22/intp22, p115/ti23/intp23, p117/ti24/intp24, p21/intp30, p22/adtrg, p23/intp50, p24/intp51, p25/ intp52, p26/intp53, p31/rxd/si0, p32/sck0, p33/so1, p34/si1, p35/sck1, p121/si2, p122/ sck2, p124/si3, p125/sck3, mode0 to mode2, reset, p20/nmi remark typ. value is a value for your reference at t a = 25 c. t hvd v dd v dd t fvd t rvd t drel v dd v dddr reset (input) v ihdr nmi (input) (release by falling edge) v ihdr v ildr nmi (input) (release by rising edge) stop mode is set (at fifth clock after psc register has been set).
m pd70f3008 21 ac characteristics ( t a = C40 to +85 c, v dd = av dd = bv dd = cv dd = 2.7 to 3.6v, v ss = av ss = bv ss = cv ss = 0 v ) ac test input wave (a) p02/intp00 to p05/intp03, p06/tclr0/intp04, p07/ti0/intp05, p10/intp10, p11/intp11, p12/intp12, p13/intp13, p14/ti1/intp14, p16/ti20/intp20, p111/ti21/intp21, p113/ti22/intp22, p115/ti23/intp23, p117/ti24/intp24, p21/intp30, p22/adtrg, p23/intp50, p24/intp51, p25/intp52, p26/intp53, p31/ rxd/si0, p32/sck0, p33/so1, p34/si1, p35/sck1, p121/si2, p122/sck2, p124/si3, p125/sck3, mode0 to mode2, reset, p20/nmi (b) p40/ad0 to p47/ad7, p50/ad8 to p57/ad15, p60/a16 to p67/a23, p90/lbe/wrl, p91/ube, p92/r/w/ wrh, p93/dstb/rd, p94/astb, p95/hldak, p96/hldrq, clkout, wait (c) other than (a) and (b) test points 0.8v dd 0.15v dd 0.8v dd 0.15v dd v dd 0 v test points 0.7bv dd 0.2bv dd 0.7bv dd 0.2bv dd bv dd 0 v test points 0.7v dd 0.2v dd 0.7v dd 0.2v dd v dd 0 v
m pd70f3008 22 ac test output test point load condition caution if the loaded capacitance exceeds 50 pf due to the circuit configuration, decrease the load capacitance of this device to less than 50 pf by using a buffer. test points 0.7v dd 0.2v dd 0.7v dd 0.2v dd c l = 50 pf dut (tested device)
m pd70f3008 23 (1) clock timing parameter symbol condition min. max. unit x1 input cycle <1> t cyx direct mode 15 dc ns pll mode (f xx = f /5) 150 note ns pll mode (f xx = f )30 note ns x1 input high-level width <2> t wxh direct mode 4 ns pll mode (f xx = f /5) 50 ns pll mode (f xx = f )10ns x1 input low-level width <3> t wxl direct mode 4 ns pll mode (f xx = f /5) 50 ns pll mode (f xx = f )10ns x1 input rise time <4> t xr direct mode 5 ns pll mode (f xx = f /5) 15 ns pll mode (f xx = f )5ns x1 input fall time <5> t xf direct mode 5 ns pll mode (f xx = f /5) 15 ns pll mode (f xx = f )5ns cpu operating frequency f 0 33 mhz clkout output cycle <6> t cyk 30 dc ns clkout high-level width <7> t wkh 0.5t C 5 ns clkout low-level width <8> t wkl 0.5t C 5 ns clkout rise time <9> t kr 5ns clkout fall time <10> t kf 5ns clkout delay time from x1 <11> t dxk direct mode 3 17 ns note under evaluation remark t = t cyk parameter symbol condition typ. unit free-running oscillation frequency f p pll mode under evaluation mhz < 1 > < 2 > < 4 > < 11 > < 5 > < 6 > < 7 > < 9 > < 10 > < 8 > < 3 > x1 (input) clkout (output) < 11 >
m pd70f3008 24 (2) output wave (other than x1, clkout) parameter symbol condition min. max. unit output rise time <12> t or 10 ns output fall time <13> t of 10 ns (3) reset timing parameter symbol condition min. max. unit reset high-level width <14> t wrsh 500 ns reset low-level width <15> t wrsl on power application, or on releasing 500 + t os ns stop mode except on power application or except 500 ns on releasing stop mode remark t os : oscillation stabilization time 0.2v dd 0.7v dd output signal < 12 > < 13 > 0.7v dd 0.2v dd reset (input) < 14 > < 15 >
m pd70f3008 25 [memo]
m pd70f3008 26 (4) read timing (1/2) parameter symbol condition min. max. unit clkout -? address delay time <16> t dka 314ns clkout -? address float delay time <17> t fka t dka 17 ns clkout ? astb delay time <18> t dkst 314ns clkout ? dstb delay time <19> t dkd 314ns data input setup time (to clkout - ) <20> t sidk 5ns data input hold time (from clkout - ) <21> t hkid 5ns wait setup time (to clkout ) <22> t swtk 5ns wait hold time (from clkout ) <23> t hkwt 5ns address setup time (to astb ) <24> t sast 0.5t C 10 ns address hold time (from astb ) <25> t hsta 0.5t C 10 ns dstb ? address float delay time <26> t fda 0ns data input setup time (to address) <27> t said (2 + n)t C 17 ns data input setup time (from dstb ) <28> t sdid (1 + n)t C 17 ns astb ? dstb delay time <29> t dstd 0.5t C 10 ns data input hold time (from dstb - ) <30> t hdid 0ns dstb -? address output delay time <31> t dda (1 + i)t ns dstb -? astb - delay time <32> t ddst1 0.5t C 10 ns dstb -? astb delay time <33> t ddst2 (1.5 + i)t C 10 ns dstb low-level width <34> t wdl (1 + n)t C 10 ns astb high-level width <35> t wsth t C 10 ns wait setup time (to address) <36> t sawt1 n 3 1 1.5t C 15 ns <37> t sawt2 (1.5 + n)t C 15 ns wait hold time (from address) <38> t hawt1 n 3 1 (0.5 + n)t ns <39> t hawt2 (1.5 + n)t ns wait setup time (to astb ) <40> t sstwt1 n 3 1 t C 15 ns <41> t sstwt2 (1 + n)t C 15 ns wait hold time (from astb ) <42> t hstwt1 n 3 1ntns <43> t hstwt2 (1 + n)t ns remarks 1. t = t cyk 2. n indicates the number of wait clocks inserted in the bus cycle. the sampling timing differs when the programmable wait state is inserted. 3. i indicates the number of idle states (0 or 1) to be inserted in the read cycle. 4. be sure to observe at least one of data input hold times t hkid (<21>) and t hdid (<30>).
m pd70f3008 27 t1 t2 tw t3 clkout (output) a16 to a23 (output) r/w (output) uben (output) lben (output) ad0 to ad15 (i/o) astb (output) dstb (output) rd (output) wait (input) < 16 > < 21 > < 20 > < 17 > a0 to a15 (output) d0 to d15 (input) < 18 > < 24 > < 18 > < 30 > < 32 > < 31 > < 19 > < 29 > < 35 > < 28 > < 34 > < 33 > < 22 > < 23 > < 22 > < 42 > < 41 > < 43 > < 23 > < 40 > < 36 > < 39 > < 38 > < 37 > < 26 > wrl, wrh: high-level output the broken line indicates the high-impedance state. remarks 1. 2. < 19 > < 27 > < 25 > (4) read timing (2/2): 1 wait
m pd70f3008 28 (5) write timing (1/2) parameter symbol condition min. max. unit clkout -? address delay time <16> t dka 314ns clkout ? astb delay time <18> t dkst 314ns clkout -? dstb delay time <19> t dkd 314ns wait setup time (to clkout ) <22> t swtk 5ns wait hold time (from clkout ) <23> t hkwt 5ns address setup time (to astb ) <24> t sast 0.5t C 10 ns address hold time (from astb ) <25> t hsta 0.5t C 10 ns astb ? dstb delay time <29> t dstd 0.5t C 10 ns dstb -? astb - delay time <32> t ddst1 0.5t C 10 ns dstb low-level width <34> t wdl (1 + n)t C 10 ns astb high-level width <35> t wsth t C 10 ns wait setup time (to address) <36> t sawt1 1.5t C 15 ns <37> t sawt2 n 3 1 (1.5 + n)t C 15 ns wait hold time (from address) <38> t hawt1 (0.5 + n)t ns <39> t hawt2 n 3 1 (1.5 + n)t ns wait setup time (to astb ) <40> t sstwt1 t C 15 ns <41> t sstwt2 n 3 1 (1 + n)t C 15 ns wait hold time (from astb ) <42> t hstwt1 nt ns <43> t hstwt2 n 3 1 (1 + n)t ns clkout - ? data output delay time <44> t dkod 14 ns dstb ? data output delay time <45> t ddod 5ns data output setup time (to dstb - ) <46> t sodd (1 + n)t C 15 ns data output hold time (from dstb - ) <47> t hdod t C 10 ns remarks 1. t = t cyk 2. n indicates the number of wait clocks inserted in the bus cycle. the sampling timing differs when the programmable wait state is inserted.
m pd70f3008 29 t1 t2 tw t3 clkout (output) a16 to a23 (output) r/w (output) uben (output) lben (output) ad0 to ad15 (i/o) astb (output) dstb (output) wrl (output) wrh (output) wait (input) < 16 > < 44 > a0 to a15 (output) d0 to d15 (output) < 18 > < 24 > < 18 > < 32 > < 19 > < 35 > < 46 > < 29 > < 34 > < 22 > < 23 > < 22 > < 42 > < 41 > < 43 > < 23 > < 40 > < 36 > < 39 > < 38 > < 37 > rd: high-level output the broken line indicates the high-impedance state. < 25 > < 19 > < 45 > < 47 > remarks 1. 2. (5) write timing (2/2): 1 wait
m pd70f3008 30 (6) bus hold timing (1/2) parameter symbol condition min. max. unit hldrq setup time (to clkout ) <48> t shok 5ns hldrq hold time (from clkout ) <49> t hkhq 5ns clkout -? hldak delay time <50> t dkha 14 ns hldrq high-level width <51> t whqh t + 10 ns hldak low-level width <52> t whal t C 10 ns clkout - ? bus float delay time <53> t dkf note ns hldak -? bus output delay time <54> t dhac 0ns hldrq ? hldak delay time <55> t dhqha1 1.5t (2 n + 7.5)t + 20 ns hldrq -? hldak - delay time <56> t dhqha2 0.5t 1.5t + 20 ns note under evaluation remarks 1. t = t cyk 2. n indicates the number of wait clocks inserted in the bus cycle. the sampling timing differs when the programmable wait state is inserted.
m pd70f3008 31 th th th ti th clkout (output) a16 to a23 (output) hldak (output) r/w (output) uben (output) lben (output) hldrq (input) astb (output) ad0 to ad15 (i/o) d0 to d15 (input or output) < 49 > < 55 > < 56 > < 48 > < 49 > < 48 > < 48 > < 50 > < 52 > < 50 > < 54 > < 53 > dstb (output) rd (output) wrl (output) wrh (output) note note < 51 > note remark under evaluation. the broken line indicates the high-impedance state. (6) bus hold timing (2/2)
m pd70f3008 32 nmi (input) < 57 > < 58 > intpn (input) < 59 > < 60 > remark n = 00 to 05, 10 to 14, 20 to 24, 30, 50 to 53 (7) interrupt timing parameter symbol condition min. max. unit nmi high-level width <57> t wnih 500 ns nmi low-level width <58> t wnil 500 ns intpn high-level width <59> t with n = 00 to 05, 10 to 14, 20 to 24, 3t + 10 ns 30, 50 to 53 intpn low-level width <60> t witl n = 00 to 05, 10 to 14, 20 to 24, 3t + 10 ns 30, 50 to 53 remark t = t cyk
m pd70f3008 33 (8) rpu timing parameter symbol condition min. max. unit tin high-level width <61> t wtih n = 0, 1, 20 to 24 3t + 10 ns tin low-level width <62> t wtil n = 0, 1, 20 to 24 3t + 10 ns tclr0 high-level width <63> t wtch 3t + 10 ns tclr0 low-level width <34> t wtcl 3t + 10 ns remark t = t cyk ti1n (input) < 61 > < 62 > tclr1n (input) < 63 > < 64 > remark n = 0, 1, 20 to 24
m pd70f3008 34 (9) csi timing (1/2) (a) master mode (i) csi0, csi2, csi3 timing parameter symbol condition min. max. unit sckn cycle <65> t cysk output 160 ns sckn high-level width <66> t wskh output 0.5t cysk C 20 ns sckn low-level width <67> t wskl output 0.5t cysk C 20 ns sin setup time (to sckn - ) <68> t ssisk 30 ns sin hold time (from sckn - ) <69> t hsksi 0ns son output delay time (from sckn ) <70> t dskso 18 ns son output hold time (from sckn - ) <71> t hskso 0.5t cysk C 5 ns remark n = 0, 2, 3 (ii) csi1 timing parameter symbol condition min. max. unit sck1 cycle <65> t cysk output r l = 1 k w 500 ns sck1 high-level width <66> t wskh output c l = 50 pf 0.5t cysk C 70 ns sck1 low-level width <67> t wskl output 0.5t cysk C 70 ns si1 setup time (to sck1 - ) <68> t ssisk 100 ns si1 hold time (from sck1 - ) <69> t hsksi 50 ns so1 output delay time (from sck1 ) <70> t dskso r l = 1 k w, c l = 50 pf 150 ns so1 output hold time (from sck1 - ) <71> t hskso 0.5t cysk C 5 ns remark r l and c l are the load resistance and load capacitance respectively of the sck1 and so1 output lines. (b) slave mode (i) csi0, csi2, csi3 timing parameter symbol condition min. max. unit sckn cycle <65> t cysk input 160 ns sckn high-level width <66> t wskh input 50 ns sckn low-level width <67> t wskl input 50 ns sin setup time (to sckn - ) <68> t ssisk 10 ns sin hold time (from sckn - ) <69> t hsksi 10 ns son output delay time (from sckn ) <70> t dskso 30 ns son output hold time (from sckn - ) <71> t hskso t wskh ns remark n = 0, 2, 3
m pd70f3008 35 (9) csi timing (2/2) (ii) csi1 timing parameter symbol condition min. max. unit sck1 cycle <65> t cysk input 500 ns sck1 high-level width <66> t wskh input 180 ns sck1 low-level width <67> t wskl input 180 ns si1 setup time (to sck1 - ) <68> t ssisk 100 ns si1 hold time (from sck1 - ) <69> t hsksi 50 ns so1 output delay time (from sck1 ) <70> t dskso r l = 1 k w, c l = 50 pf 150 ns so1 output hold time (from sck1 - ) <71> t hskso t wskh ns remark r l and c l are the load resistance and load capacitance respectively of the sck1 and so1 output lines. (c) sckn cycle when v854 series products are connected to each other parameter symbol condition (operating mode min. max. unit of master v854) sckn cycle <65> t cysk transmission 160 ns reception 160 ns transmission/reception 160 ns remark n = 0 to 3 sckn (i/o) sin (input) son (output) < 65 > < 67 > < 66 > < 68 > < 69 > < 70 > < 71 > input data output data remarks 1. 2. the broken line indicates the high-impedance state. n = 0 to 3
m pd70f3008 36 a/d converter characteristics (t a = C40 to +85 c, v dd = av dd = bv dd = cv dd = 2.7 to 3.6v, v ss = av ss = bv ss = cv ss = 0 v) parameter symbol conditions min. typ. max unit resolution 8 bit total error note % quantization error note lsb conversion time t conv 2 note m s sampling time t samp note note m s zero-scale error 2 lsb full-scale error 2 lsb linearity error 2 lsb analog input voltage v ian C0.3 av ref + 0.3 v analog input resistance r an note m w note m w av ref input voltage av ref note v dd v av ref input current ai ref note ma note m a av dd current ai dd note m a adtrg high-level width t wadh 3t + 10 ns adtrg low-level width t wadl 3t + 10 ns note under evaluation
m pd70f3008 37 4.2 flash memory programming mode basic characteristics (under evaluation) parameter symbol conditions min. typ. max. unit operating frequency f x 33 mhz supply voltage v dd 2.7 3.6 v v ppl v pp low level detection C0.3 0.2v dd v v ppm v dd level of v pp detection 0.8v dd 1.2v dd v v pph v pp high voltage detection 7.2 7.8 v v dd supply current i do note ma v pp supply current i pp v pp = 7.5 v note ma number of rewrite c wrt 100 times number of write t wrt 50 m s erasure time t erase note s note under evaluation
m pd70f3008 38 serial write operation characteristics parameter symbol conditions min. typ. max. unit v dd -? reset - setup time <101> t drpsr note m s v pp -? reset - setup time <102> t psrrf note m s reset -? v pp count start time <103> t rfcf note m s count execution time <104> t count note note ms v pp counter high-level width <105> t ch note m s v pp counter low-level width <106> t cl note m s v pp counter rise time <107> t r note m s v pp counter fall time <108> t f note m s note under evaluation remark t = t cyk < 104 > < 101 > < 102 > < 103 > < 105 > < 108 > v dd v pp reset (input) v dd 0 v v pph v ppm v ppl v dd 0 v < 106 > < 107 >
m pd70f3008 39 5. package drawing 144 pin plastic lqfp (fine pitch) (20 20) item millimeters inches note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. a 22.0?.2 0.866?.008 b 20.0?.2 0.787 +0.009 ?.008 c 20.0?.2 0.787 +0.009 ?.008 d f 1.25 22.0?.2 0.866?.008 0.049 s144gj-50-8eu-2 s 1.7 max. 0.067 max. k 1.0?.2 0.039 +0.009 ?.008 l 0.5?.2 0.020 +0.008 ?.009 r3 3 +7 ? +7 ? g 1.25 0.049 h 0.22 0.009?.002 i 0.10 0.004 j 0.5 (t.p.) 0.020 (t.p.) m 0.145 0.006?.002 n 0.10 0.004 p 1.4?.1 0.055?.004 q 0.125?.075 0.005?.003 +0.05 ?.04 +0.055 ?.045 m 108 73 136 109 144 72 37 detail of lead end i j f g h q r p k m l n cd s a b
m pd70f3008 40 6. recommended soldering conditions undefined
m pd70f3008 41 [memo]
m pd70f3008 42 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m pd70f3008 43 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
m pd70f3008 related document : m pd70f3008y data sheet (u12755e) v850 family instruction application table (u10229j) (japanese version) reference document : electrical characteristics for microcomputer (iei-601) (japanese version) the related documents in this publication may include preliminary versions. however, preliminary versions are not marked as such. v850 family and v854 are trademarks of nec corporation. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

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