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nt512d64s8haag 512mb : 64m x 64 pc2700 unbuffered dimm 184pin tw o bank un buffered ddr sdram module based o n d dr33 3 64m x8 sdram features ? 184-pin unbuff e red 8-b y te d ual in-line memor y module ? 64mx64 do uble data rate (dd r ) sdram dimm ? performance: p c 2 7 0 0 speed sort -6 dimm cas latenc y 2 . 5 2 unit f ck c l o c k frequenc y 1 6 6 1 3 3 m h z t ck c l o c k cy c l e 6 7 . 5 n s f dq dq bu rst freq u e n cy 333 266 mhz ? intended for 100 mhz and 133 mhz applications ? inputs and outp uts are sstl- 2 compatible ? v dd = 2.5volt 0.2, v ddq = 2.5 v olt 0.2 ? single pulsed ras interface ? sdrams have 4 internal banks for concurrent op eration ? module has tw o phy sical banks ? differ e ntial cloc k inputs ? data is read or written on both clock edges ? dram d ll aligns dq and dq s tr ansitions w i th clock tr ansitions. ? address and control signals are fully s y nchronous to positive clock edge ? programmable oper ation: - dimm cas latenc y : 2, 2.5 - burst t y pe: se quential or interl eave - burst length: 2, 4, 8 - ope r ation: burs t read and w r ite ? auto-refresh ( c br) and self- r efresh modes ? automatic and controlled precha rge commands ? 13/10/2 addres sing (ro w / column /bank) ? 7.8 s max. average periodic r e fresh interval ? serial presence detect ? gold contacts ? sdrams in 66-pin tsop t y pe ii package description nt512d 64s8ha 0 g is an unbuffe r ed 184-pin doub le data rate ( d d r ) s y nch r onous dram dual in-li n e memor y mod u le (dimm), organized as a t w o - bank high-sp e ed memor y ar ra y. th e 64m x64 module is a dual-bank dimm that uses sixteen 32mx8 dd r sdrams in 400 mil tsop packages. the dimm a c hieves high-spe ed data tra n sfer r a tes of up to 266 m hz. the dimm is intended for use in applications o perating from 10 0 mhz to 133 m h z clock speeds w i th dat a rates of 200 to 266 m h z. clock enable cke0 and/or cke 1 contr o ls all devi c e s on the dimm. pr ior to any access oper ation, the device cas latency and burst t y pe/ le ngth/operation t y pe must be prog r a mmed into the dimm b y address inputs a0-a12 and i/ o in puts ba0 and ba1 using the mode register set c y cle. these dimms ar e manufactured using ra w cards developed for br oad industr y use as reference desi gns. the use of t hese common design files min i mizes electr i c al v a r i ation betw e en supplier s . the dimm uses serial presence detects impl emented via a serial e eprom using th e t w o- pin iic prot ocol. the first 12 8 b y tes of se ri al pd data are p r ogr a m m ed and locked during module as sembly . the last 128 b y tes a r e av ailable to the customer. all nan y a 184 ddr sdram di mms provide a high-perf o rmance, flexib le 8-b y te interface in a 5.25? long space-savin g footprint. ordering information part numbe r s p e e d o r g a nization leads pow e r 166mhz (6ns @ cl = 2.5) nt512d 64s8ha ag-6 133mhz (7.5ns @ cl= 2) p c 2 7 0 0 6 4 m x 6 4 g o l d 2 . 5 v rev 1.0 0 6 / 2002 1 ? n a n y a te c hnology corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8haag 512mb : 64m x 64 pc2700 unbuffered dimm pin description ck0, ck1, ck2 ck0 , ck1 , ck2 dif f erential clock input s dq0 - d q 63 dat a input/outpu t cke0, cke1 clock enable ras r o w a d d r e s s s t r o b e dqs0- d qs7 , dqs9- d qs1 6 bi-directional dat a strobes cas c o l u m n a d d r e s s s t r o b e v dd p o w e r (2. 5 v ) we w r i t e e n a b l e v ddq suppl y volt age fo r dqs (2.5v) s0 , s1 c h i p select s v ss g r o u n d a0-a9, a1 1, a12 address input s nc no connect a 1 0 / a p a d d r e s s input/au t o-precha r g e s c l serial presence detect clock input ba0, ba1 sdram bank address input s sda se rial presence detect dat a inpu t/output v ref ref. v o lt age for sstl_2 input s sa0-2 serial presence detect address input s v ddid v dd identification flag. v ddspd serial eepro m positive pow er s uppl y (2.5v ) pinout p i n f r o n t p i n b a c k p i n f r o n t p i n b a c k pin f r o n t p i n b a c k 1 v ref 9 3 v ss 3 2 a 5 124 v ss 6 2 v ddq 1 5 4 ras 2 d q 0 9 4 d q 4 3 3 d q 2 4 125 a 6 6 3 we 1 5 5 d q 4 5 3 v ss 9 5 d q 5 3 4 v ss 1 2 6 d q 2 8 6 4 d q 4 1 1 5 6 v ddq 4 d q 1 9 6 v ddq 3 5 d q 2 5 127 d q 2 9 6 5 cas 1 5 7 s0 5 d q s 0 9 7 d q s 9 3 6 d q s 3 128 v ddq 6 6 v ss 1 5 8 s1 6 d q 2 9 8 d q 6 3 7 a 4 129 d q s 1 2 6 7 d q s 5 1 5 9 d q s 1 4 7 v dd 9 9 d q 7 3 8 v dd 1 3 0 a 3 6 8 d q 4 2 1 6 0 v ss 8 d q 3 1 0 0 v ss 3 9 d q 2 6 131 d q 3 0 6 9 d q 4 3 1 6 1 d q 4 6 9 n c 1 0 1 n c 4 0 d q 2 7 132 v ss 7 0 v dd 1 6 2 d q 4 7 1 0 n c 1 0 2 n c 4 1 a 2 133 d q 3 1 7 1 n c 1 6 3 n c 11 v ss 1 0 3 n c 4 2 v ss 1 3 4 n c 7 2 d q 4 8 1 6 4 v ddq 1 2 d q 8 1 0 4 v ddq 4 3 a 1 135 n c 7 3 d q 4 9 1 6 5 d q 5 2 1 3 d q 9 1 0 5 d q 1 2 4 4 n c 136 v ddq 7 4 v ss 1 6 6 d q 5 3 1 4 d q s 1 1 0 6 d q 1 3 4 5 n c 137 c k 0 7 5 ck2 1 6 7 n c 1 5 v ddq 1 0 7 d q s 1 0 4 6 v dd 1 3 8 ck0 7 6 c k 2 1 6 8 v dd 1 6 c k 1 1 0 8 v dd 4 7 n c 139 v ss 7 7 v ddq 1 6 9 d q s 1 5 17 ck1 1 0 9 d q 1 4 4 8 a 0 140 n c 7 8 d q s 6 1 7 0 d q 5 4 1 8 v ss 1 1 0 d q 1 5 4 9 n c 141 a 1 0 7 9 d q 5 0 1 7 1 d q 5 5 1 9 d q 1 0 1 1 1 c k e 1 5 0 v ss 1 4 2 n c 8 0 d q 5 1 1 7 2 v ddq 2 0 d q 1 1 1 1 2 v ddq 5 1 n c 143 v ddq 8 1 v ss 1 7 3 n c 2 1 c k e 0 1 1 3 n c 5 2 b a 1 144 n c 8 2 v ddid 1 7 4 d q 6 0 2 2 v ddq 1 1 4 d q 2 0 ke y ke y 8 3 d q 5 6 1 7 5 d q 6 1 2 3 d q 1 6 1 1 5 a 1 2 5 3 d q 3 2 145 v ss 8 4 d q 5 7 1 7 6 v ss 2 4 d q 1 7 1 1 6 v ss 5 4 v ddq 1 4 6 d q 3 6 8 5 v dd 1 7 7 d q s 1 6 2 5 d q s 2 1 1 7 d q 2 1 5 5 d q 3 3 147 d q 3 7 8 6 d q s 7 1 7 8 d q 6 2 2 6 v ss 1 1 8 a1 1 5 6 d q s 4 148 v dd 8 7 d q 5 8 1 7 9 d q 6 3 2 7 a 9 1 1 9 dqs1 1 5 7 d q 3 4 149 d q s 1 3 8 8 d q 5 9 1 8 0 v ddq 2 8 d q 1 8 1 2 0 v dd 5 8 v ss 1 5 0 d q 3 8 8 9 v ss 1 8 1 s a 0 2 9 a 7 1 2 1 d q 2 2 5 9 b a 0 151 d q 3 9 9 0 n c 1 8 2 s a 1 3 0 v ddq 1 2 2 a 8 6 0 d q 3 5 152 v ss 9 1 s d a 1 8 3 s a 2 3 1 d q 1 9 1 2 3 d q 2 3 6 1 d q 4 0 153 d q 4 4 9 2 s c l 1 8 4 v ddspd note: nc=no co nnect; nu = not useable; du = d o not use. all pin assignment s are consistent fo r all 8-b y te un buf fered versions. rev 1.0 0 6 / 2002 2 ? n a n y a te c hnology corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8haag 512mb : 64m x 64 pc2700 unbuffered dimm input/output functional description s y mbol ty p e polarit y function ck0, ck1, ck2 (sstl) positive edge the posi t i v e l i n e of the di ffe re nti a l pai r of s y s t em cl ock i nput s. al l the ddr sdram address and cont rol inputs are sampled on t he rising edge of their associated clo c ks. ck0 , ck1 , ck2 ( s s t l ) negative edge the negative line of the differentia l pair of s y stem clock inputs. cke0, cke1 (sstl) active hi gh activates the sd ram ck signal w h en high and d eactivates the ck signal w hen lo w . b y deactivating the clocks, cke lo w initiates the power do wn mod e , or the self-r efresh mode. s0 , s1 (sstl) active lo w enables the associated sdram command dec ode r w hen lo w an d d i sables the com m and decoder w hen high. when the command decoder is disabled, new commands are ignore d but previous ope rations continue. ras , cas , we (sstl) active lo w when sampled at the positive rising edge of t he clock, ras , cas , we define the operation to be e x ecuted b y the s dram. v ref s u p p l y reference voltag e for sstl - 2 inp u ts v ddq s u p p l y isol ated po w e r suppl y for the ddr sd ram o u tput buffe rs to provi de i m prov ed noi se immunity ba0, ba1 (sstl) - select s w h ich sdram bank is to be active. a0 - a9 a10/ap a1 1, a12 (sstl) - during a ba nk activate command c y cle, a0 -a12 defines the ro w address (ra0 -ra12) w h en sampled at the rising clock edge. during a rea d or w r ite command c y cle, a0-a9 defines the column address (c a0-ca9) w h en sampled a t the rising cloc k edge. i n additio n to the column address, ap is u s ed to invoke auto-precharge op eration at the en d of t he burst read or w r ite c y cle. if ap is high, auto-pr echarge is sele cted and ba0/ba1 define the bank to be p r echarged. if ap is low , auto-pr echarge i s disabled. during a pr echarge command c ycle, ap is used in conjunction w i t h ba0/ba1 to control w h ich bank(s) to precharge. if a p is high al l 4 ba nks w ill be prech a rged rega rdless of the st ate of ba0/ba1 . if ap is low , the n ba0/ba1 are u s ed to define w h ich bank to pre-c harge. dq0 - d q 63, (sstl) - dat a and c heck bit input/output pins operate in the same man ner as on conventional drams. dq s0 - dq s7 dq s9 - dq s16 (sstl) active hi gh data strobes: output w i th re ad data, input w i th write data. edge aligned w i th rea d data, centered on write data. used to ca pture write data. v dd, v ss s u p p l y pow e r and g r oun d for the d dr s dram input buff e rs and core logi c sa0 ? sa2 - address input s. connected to either v dd or v ss on the sy stem board to configure the serial presence detect eepro m address. sda - this bi-direction al pin is u s ed to transfer data into or out of the sp d eepro m . a resistor must be connected from the s d a bus line to v dd to act as a pullup. scl - this signal is used to clock data into and out of the spd eepr o m . a resistor ma y b e connected from t he scl bus time to v dd to act as a pullup. v ddspd suppl y serial eepro m positive pow er s uppl y . rev 1.0 0 6 / 2002 3 ? n a n y a te c hnology corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8haag 512mb : 64m x 64 pc2700 unbuffered dimm functional block diagram (2 bank, 32mx8 ddr sdrams) s0 dqs9 dq0 dq1 dq2 dq7 dq4 dq6 dq5 dq3 dq8 dq9 dq1 0 dq1 5 dq1 2 dq1 4 dq1 3 dq1 1 a0 - a 1 2 ras b a 0 - ba1 ba0 - ba1 : sd ram s d0 - d 1 5 a 0 - a12 : s d r a m s d0 -d 15 ras : sdram s d0 - d 1 5 dq1 6 dq1 7 dq1 8 dq2 3 dq2 0 dq2 2 dq2 1 dq1 9 dq2 4 dq2 5 dq2 6 dq3 1 dq2 8 dq3 0 dq2 9 dq2 7 i/ o 7 i/ o 6 i/ o 3 i/ o 4 i/ o 5 i/ o 0 i/ o 1 i/ o 2 dm cs d3 i/ o 7 i/ o 6 i/ o 3 i/ o 4 i/ o 5 i/ o 0 i/ o 1 i/ o 2 dm cs d2 dqs0 dqs1 3 dqs4 i/ o 7 i/ o 6 i/ o 3 i/ o 4 i/ o 5 i/ o 0 i/ o 1 i/ o 2 dm cs d0 dqs1 0 dqs1 dqs dqs1 1 dqs2 dqs1 2 dqs3 dqs dq3 2 dq3 3 dq3 4 dq3 9 dq3 6 dq3 8 dq3 7 dq3 5 dq4 0 dq4 1 dq4 2 dq4 7 dq4 4 dq4 6 dq4 5 dq4 3 i/ o 7 i/ o 6 i/ o 3 i/ o 4 i/ o 5 i/ o 0 i/ o 1 i/ o 2 dm cs d1 dqs dqs5 dqs1 4 dq4 8 dq4 9 dq5 0 dq5 5 dq5 2 dq5 4 dq5 3 dq5 1 dq5 6 dq5 7 dq5 8 dq6 3 dq6 0 dq6 2 dq6 1 dq5 9 dqs6 dqs1 5 dqs7 dqs1 6 cke0 we cas c as : sdram s d0 - d 1 5 cke0 : sdrams d0 - d 7 w e : sdram s d8 - d 1 5 120 ohm s d r a m x 4 ck0 ck0 120 ohm s d r a m x 6 ck1 ck1 120 ohm s d r a m x 6 ck2 ck2 n o tes : 1. d q -to-i/o w r i ng m a y be chan ged w i thi n a byte. 2. d q /d qs / d m / c k e / s rel a ti ons hi ps are m a i n tai ned as show n . 3. d q /d qs / d m / d q s r e si stors a r e 22 ohm s . 4. v d d i d st rap conne cti ons (for m e m o ry d e vi ce v d d, v d d q ): st rap o u t ( o pen ) : vdd = vddq st rap i n ( vss) : v dd i s n o t equal to vd d q . dqs s1 i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d8 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d9 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d1 0 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d1 1 dqs i/ o 7 i/ o 6 i/ o 3 i/ o 4 i/ o 5 i/ o 0 i/ o 1 i/ o 2 dm cs d7 i/ o 7 i/ o 6 i/ o 3 i/ o 4 i/ o 5 i/ o 0 i/ o 1 i/ o 2 dm cs d6 i/ o 7 i/ o 6 i/ o 3 i/ o 4 i/ o 5 i/ o 0 i/ o 1 i/ o 2 dm cs d4 dqs dqs i/ o 7 i/ o 6 i/ o 3 i/ o 4 i/ o 5 i/ o 0 i/ o 1 i/ o 2 dm cs d5 dqs dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d1 2 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d1 3 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d1 4 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d1 5 dqs vddq vss d0 - d1 5 d0 - d1 5 d0 - d1 5 d0 - d1 5 vdd vref vddid s t rap: s ee n o te 4 se r i a l pd a0 a2 a1 scl wp sda s a 0 sa2 sa 1 w e : sdram s d0 - d 1 5 cke1 rev 1.0 0 6 / 2002 4 ? n a n y a te c hnology corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8haag 512mb : 64m x 64 pc2700 unbuffered dimm serial presence det ect -- part 1 of 2 spd entr y v a lue serial pd dat a e n tr y (he x adecimal) n ote by t e descr iption ddr333 -6 ddr333 -6 0 number of se rial pd b y tes w r itte n during production 1 2 8 8 0 1 t o t a l numbe r of b y tes in serial pd device 256 08 2 f u n d a m e n t al memor y t y p e sdram d d r 0 7 3 n u m b e r of ro w addresses on assembly 1 3 0 d 4 number of colu mn addresses on assembly 10 0a 5 number of dimm bank 1 01 6 dat a wid t h of assembly x64 40 7 dat a wid t h of assembly (cont?) x64 00 8 v o lt age interface level of this assembl y sstl 2.5v 04 9 ddr sdram de vi ce cy cl e t i me at cl=2.5 6ns 60 10 ddr sdram de vi ce access t i me from cl ock at cl=2.5 0 . 7 n s 7 0 1 1 d i m m configura t ion t y p e non-parit y 0 0 1 2 r e f r e s h rate/ t y p e sr/1x( 7.8 s ) 8 2 13 primar y d dr sd ram wid t h x8 08 14 error checki ng ddr sdram devi ce wi d t h n/a 00 15 ddr sdram de vi ce attr: mi n clk del a y , random col access 1 clock 01 16 ddr sdram de vi ce attri butes: burst length su pported 2 , 4 , 8 0 e 17 ddr sdram de vi ce attri butes: n u mber of device banks 4 0 4 18 ddr sdram de vi ce attri butes: c as latenci e s supported 2 / 2 . 5 0 c 19 ddr sdram de vi ce attri butes: c s latenc y 0 01 2 0 d d r sdram de vi ce attri butes: we latenc y 1 0 2 21 ddr sdram de vi ce attri butes: di f f erenti a l cl ock 20 22 ddr sdram de vi ce attri butes: general +/-0.2v v o l t age t o l e rance 00 23 minimum clock c y cle at cl=2 7.5ns 75 24 maximum dat a a ccess t i me from clock at cl=2 0 . 7 n s 7 0 25 minimum clock c y cle t i me at cl =1 n/a 00 26 maximum dat a a ccess t i me from clock at cl=1 n / a 0 0 27 minimum row p r echarge t i me (t rp ) 1 8 n s 4 8 28 minimum row a c tive to row active dela y (t rrd ) 1 2 n s 3 0 29 minimum ras to cas dela y (t rcd ) 1 8 n s 4 8 30 minimum ras pulse wid t h (t ras ) 4 2 n s 2 a 3 1 m o d u l e bank de nsity 2 5 6 m b 4 0 32 address and co mmand setup t i me before clock 0 . 7 5 n s 7 5 33 address and co mmand hold t i m e af ter clock 0 .75ns 75 34 dat a input set u p t i me before clo ck 0.45ns 45 35 dat a input hold t i me af ter clock 0.45ns 45 3 6 - 6 1 r e s e r v e d u n d e f i n e d 0 0 6 2 s p d r e v i s i o n i n i t i a l 0 0 6 3 c h e c k s u m dat a 0 a rev 1.0 0 6 / 2002 5 ? n a n y a te c hnology corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8haag 512mb : 64m x 64 pc2700 unbuffered dimm serial presence det ect -- part 2 of 2 spd entr y v a lue serial pd dat a e n tr y (he x adecimal) by t e descr iption ddr333 -6 ddr333 -6 note 64-71 manufacturer ? s jeded id code 0b 7f7f7 f 0b00000 000 72 module manufact u ring location n/a 00 73-90 module part num ber n/a 00 9 1 - 9 2 m o d u l e revision c o d e n / a 0 0 93-94 module manufact u ring dat a y ear/w eek code yy/ ww 1,2 95-98 module serial number s e r i a l n u m b e r 0 0 9 9 - 2 5 5 r e s e r v e d u n d e f i n e d 0 0 1. yy= binar y code d decimal y e a r c ode, 0-99 (decimal), 00-63 (he x ) 2. ww = bina r y code d decimal y e a r c ode, 01-52 (decimal), 01-34 (he x ) rev 1.0 0 6 / 2002 6 ? n a n y a te c hnology corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8haag 512mb : 64m x 64 pc2700 unbuffered dimm absolute maximum ratings s y mbol parameter rati ng uni t s v in , v out v o lt age on i/o pi ns relative to vss -0.5 to v ddq +0. 5 v v in v o lt age on input relative to vss -0.5 to +3.6 v v dd v o lt age on vdd supply relative to vss -0.5 to +3.6 v v ddq v o lt age on vdd q suppl y relative to vss -0.5 to +3.6 v t a oper ating t e mpe r ature (ambient) 0 to+70 c t st g s t orage t e mpe r a t ure (plastic) -55 to +150 c p d p o w e r dissip a t i o n 1 6 w i out short circuit out put cur r ent 5 0 m a note : s t resses greater than thos e listed under ?a bsolute maximu m ratings? ma y cause permanen t dam age to the device. this is stress rating onl y , and functional operation of the d e vice at these or an y othe r c onditions above those i ndicated in the operat ional sections of this specification is not im plied. exposure to absolute ma ximum rating con d itions for ex tend ed periods ma y a f fect r eliability . cap a cit a n c e parameter s y mbol m a x . uni t s n o t e s input capacitance: ck0, ck0 , ck1, ck1 , ck2, ck2 c i1 2 4 p f 1 input capacitance: a0-a12, ba0, ba1, we , ras , cas c i2 6 0 p f 1 input capacitance: cke0,cke1, s0 , s1 c i5 3 0 p f 1 input capacitance: sa0-sa2, sc l c i4 9 p f 1 input/ou t put cap a citance dq0-63 ; dqs0 -7, 9-1 6 c io1 1 4 p f 1 , 2 input/ou t put cap a citance: sda c io3 1 1 p f 1. v ddq = v dd = 2.5v 0.2v, f = 100 mhz, t a = 2 5 c, v out (d c) = v ddq /2, v out ( p eak to peak) = 0.2v. 2. dq s inputs a r e grouped w i th i/ o pins refl ecting the fact that the y are matched in lo ading to dq and dq s to facilitate trace matching at the board level. rev 1.0 0 6 / 2002 7 ? n a n y a te c hnology corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8haag 512mb : 64m x 64 pc2700 unbuffered dimm dc electrical characteristics a nd operating conditions (t a = 0 c ~ 7 0 c; v ddq = 2.5v 0.2v; v dd = 2. 5v 0.2v, see a c characte ristics) s y m b o l p a r a m e t e r m i n m a x unit s n otes v dd suppl y voltage 2.3 2.7 v 1 v ddq i/o suppl y voltage 2.3 2.7 v 1 v ss, v ssq suppl y voltage, i / o suppl y v o ltage 0 0 v v ref /o refe rence vol t age 0.49 x v dd q 0 . 5 1 x v dd q v 1 , 2 v tt i/o t e rmination voltage (s y s tem) v ref ? 0.04 v ref + 0.04 v 1,3 v ih (dc) input high (lo g ic1) voltage v ref + 0.15 v ddq + 0.3 v 1 v il (dc) input lo w (logic0) voltage -0.3 v ref - 0.15 v 1 v in (dc) input voltage le vel, ck and ck inputs -0.3 v ddq + 0.3 v 1 v id (dc) input differential voltage, ck and ck inputs 0.30 v ddq + 0.6 v 1,4 i i input leakage c u rrent an y input 0v v in v dd; (all other pins not under t e st = 0v) - 1 0 1 0 u a 1 i oz output l eakage curren t (dqs a r e disabled; 0v v out v dd q - 1 0 1 0 u a 1 i oh output high cur r ent (v out = v ddq -0. 373v, min v ref, min v tt ) - 1 6 . 8 - m a 1 i ol output l o w cu rr ent (v out = 0.373, max v ref , ma x v tt ) 1 6 . 8 - m a 1 1. inputs are no t recognized as valid until v ref stabilize s . 2. v ref is expect ed to be equal to 0.5 v ddq of the transmitting device, and to track variati ons in the dc level of the same. peak-to-pe a k noise on v ref m a y not e x ceed 2 % of the d c value. 3. v tt is not applied directly to the dimm. v tt is a sy stem suppl y fo r signal termination resistors, is ex pected to be set equal to v ref, and must track variations in the dc level of v ref . 4. v id is the mag n itude of the diffe rence bet w een th e input level on ck and the input level on ck . rev 1.0 0 6 / 2002 8 ? n a n y a te c hnology corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8haag 512mb : 64m x 64 pc2700 unbuffered dimm ac characteristics (notes 1-5 appl y to the follow i ng t abl es; electrical characte ristics and dc operating c onditions, ac oper ating conditions, oper ating, standb y , a nd refresh c u rre nts, and electrical characteristics and ac timing.) 1. all voltages referenced to v ss . 2. tests for ac ti ming, i dd , and el ectrical, ac and dc characteri stics, ma y be condu cted at nominal r e ference/suppl y voltage levels, b u t the related specifications and device operation are guarantee d for th e full voltage range specified. 3. outpu t s measured w i th equivalent load. re fer to the ac output l oad circuit below. 4. ac timing and i dd tests ma y us e a v il to v ih s w i ng of up to 1.5v i n the test environ ment, but input ti ming is still referenced to v ref (o r to the crossing point for ck, ck ), and param et er s pecifications are guarantee d for th e specified ac in put levels under normal u se conditions. the minimum slew ra te for the input si gnals is 1v/ns in the range b e t w e en v il (ac) a nd v ih (ac) unless oth e r w ise specified. 5. the ac a nd d c input level specificat i ons are as defined in the s s tl_2 standa rd (i.e . the receiver effectively s w itches as a result of the signal crossing the ac input level, and remains in t hat state as long as the signal does not ring back above (belo w ) th e dc inp ut l o w ( h igh ) level. ac output load circuit s ti m i n g ref e renc e p o i n t v tt 5 0 ohm s 30 pf o u t put v out ac operating conditions (t a = 0 c ~ 7 0 c ; vdd q = 2.5v 0.2v; vdd = 2. 5v 0.2v, see a c characte ristics) s y mbol parameter/ condi tion min max uni t notes v ih (ac) input high (lo g ic 1) voltage. v ref + 0.31 v 1, 2 v il (ac) input lo w (logic 0) voltage. v ref ?- 0. 31 v 1, 2 v id (ac) input differential voltage, ck and ck inputs 0.62 v ddq + 0.6 v 1, 2, 3 v ix (ac) input differential pair cross point voltage, ck and ck inputs (0.5*v ddq) - 0.2 (0.5*v ddq) + ? 0. 2 v 1, 2, 4 1. input slew rate = 1v/ ns. 2. inputs are no t recognized as valid until v ref stabilize s . 3. v id is the mag n itude of the diffe r ence bet w een th e input level on ck and the input level on ck. 4. the value of v ix is expected to equal 0.5*v ddq of the transmittin g device and must track va riations in the dc level of the same. rev 1.0 0 6 / 2002 9 ? n a n y a te c hnology corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8haag 512mb : 64m x 64 pc2700 unbuffered dimm operating, standby , and refresh currents (t a = 0 c ~ 70 c ; v ddq = 2.5v 0.2v; v dd = 2. 5v 0.2v, see a c characte ristics) s y mbol parameter/ condi tion pc2700 uni t notes i dd0 oper ating cur r e n t : one bank; act i ve / precharge; t rc = t rc ( m i n ) ; t ck = t ck ( m i n ) ; dq, dm, and d q s inputs changing tw ice per clock cy cle ; address and cont rol inputs changing once per clock cy cle 1 1 6 0 m a 1 , 2 i dd1 oper ating cur r e n t : one bank; act i ve / read / prech a rge; burst = 2; t rc = t rc ( m in) ; cl=2.5; t ck = t ck (m i n ) ; i out = 0ma; address and cont rol inputs changing once per clock cy cle t b d m a 1 , 2 i dd2p precharge po we r-do w n standb y curren t : all banks id le; pow e r-do w n mode; cke d v il ( m a x ) ; t ck = t ck ( m in) 4 0 0 m a 1 , 2 i dd2n idle standb y c u r r ent : cs t v ih (m in ) ; all banks idle; c ke t v ih( m i n ) ; t ck = t ck ( m in) ; a ddress and contr o l inputs changin g once per clock cy cle 5 6 0 m a 1 , 2 i dd3p active pow e r- do w n st andb y cur r ent : one bank ac tive; po w e r- do w n mod e ; cke d v il ( m a x ) ; t ck = t c k ( m in ) 4 0 0 m a 1 , 2 i dd3n active standby c u rrent : one bank ; active / prechar ge; cs t v ih ( m in ) ; cke t v ih ( m in) ; t rc = t ras ( m a x ) ; t ck = t ck ( m i n ) ; dq, dm, an d dqs inputs changing tw ice per clock c y cle; address and cont rol inputs changing once per clock cy cle 9 6 0 m a 1 , 2 i dd4r oper ating cur r e n t : one bank; bu rst = 2; reads; co ntinuous burst; address and cont rol inputs changing once per clock cy cle; dq and dqs out puts changing twice per clock cy cle; cl = 2.5; t ck = t ck ( m in) ; i out = 0ma 1 8 0 0 m a 1 , 2 i dd4 w oper ating cur r e n t : one bank; bu rst = 2; w r ites; continuous burst; address and cont rol inputs changing once per clock cy cle; dq and dqs inp u ts changing tw ic e per clock cy cle; cl=2.5; t ck = t ck ( m in) 1 6 8 0 m a 1 , 2 t rc = t rfc ( m in) 2 4 0 0 m a 1 , 2 i dd5 auto-refr e sh cu rrent : t rc = 7.8 s 2 6 4 m a 1 , 2 , 4 i dd6 self-refresh cu r r ent : cke d ?0. 2v 4 8 m a 1 , 2 , 3 i dd7 oper ating curre nt: four bank; four bank interleaving w i th bl = 4, address and control inpu ts randoml y cha nging; 50% of d a ta changing at ever y transfer; t rc = t rc (mi n ); i ou t = 0ma. t b d m a 1 1. i dd specifications are tested af ter the device is properl y initialize d . 2. input slew rate = 1v/ ns. 3. enables on-chip refresh and ad dress counters. 4. curr ent at 7.8 s is time averag ed value of i dd5 at t rfc ( m i n ) and i dd2p over 7.8 s. rev 1.0 0 6 / 2002 1 0 ? n a n y a te c hnology corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8haag 512mb : 64m x 64 pc2700 unbuffered dimm ac t i ming s p ecifications for d dr sdram devices used on module (t a = 0 c ~ 7 0 c; v ddq = 2.5v 0.2v; v dd = 2. 5v 0.2v, see a c characte ristics) (part 1 of 2) -6 s y mbol p a r a m e t e r m i n . m a x . uni t n o t e s t ac dq out put access time from ck/ ck - 0 . 7 5 + 0 . 7 5 n s 1 , 2 , 3 , 4 t dqsck dq s output access time fr om ck/ ck - 0 . 7 5 + 0 . 7 5 n s 1 , 2 , 3 , 4 t ch ck high-level w i dth 0.45 0.55 t ck 1 , 2 , 3 , 4 t cl ck low-level w i dt h 0.45 0.55 t ck 1 , 2 , 3 , 4 t ck c l = 2 . 5 7 1 2 n s 1 , 2 , 3 , 4 t ck clock cy cle time c l = 2 7 . 5 1 2 n s 1 , 2 , 3 , 4 t dh dq and dm inpu t hold time 0.5 ns 1,2,3,4,1 5,16 t ds dq and dm inpu t setup time 0.5 ns 1,2,3,4,1 5,16 t dip w dq and dm inpu t pulse w i dth ( e a c h input) 1.75 ns 1,2,3,4 t hz data-out high -impedance time fro m ck/ ck - 0 . 7 5 + 0 . 7 5 n s 1, 2, 3, 4, 5 t lz data-out lo w-imp edance time fro m ck/ ck - 0 . 7 5 + 0 . 7 5 n s 1, 2, 3, 4, 5 t dqsq dqs- dq ske w ( d qs & associated dq signals) 0.5 ns 1,2,3,4 t dqsqa dqs- dq ske w ( d qs & all dq si gnals) 0.5 ns 1,2,3,4 t hp minimum half clk period for a n y gi ven cy cle; defined b y clk high (t ch ) or clk low ( t cl ) ti me t ch or t cl t ck 1 , 2 , 3 , 4 t qh data output h o ld time from dq s t hp - 0.75ns t ck 1 , 2 , 3 , 4 t dqss write command t o 1st dqs latching transition 0.75 1.25 t ck 1 , 2 , 3 , 4 t dqsl,h dqs input lo w (h igh) pulse w i dth ( w rite c y cle) 0.35 t ck 1 , 2 , 3 , 4 t dss dqs falling edge to ck setup time ( w rite c y cle) 0.2 t ck 1 , 2 , 3 , 4 t dsh dqs falling edge hold time from c k ( w rite cy cle) 0 . 2 t ck 1 , 2 , 3 , 4 t mrd mode register se t command c y cle time 14 ns 1,2,3,4 t wp r e s write preamble s e tup time 0 ns 1, 2, 3, 4, 7 t wp s t w r i t e p o s t a m b l e 0 . 4 0 0 . 6 0 t ck 1, 2, 3, 4, 6 t wp r e w r i t e preamble 0 . 2 5 t ck 1 , 2 , 3 , 4 t ih address and control input hold time (fast slew rate) 0 . 9 n s 2, 3, 4, 9, 11, 12 t is address and control input setup time (fast slew rate) 0 . 9 n s 2, 3, 4, 9, 11, 12 t ih address and control input hold time (slow sle w rate) 1 . 0 n s 2, 3, 4, 10, 11, 12, 14 rev 1.0 0 6 / 2002 1 1 ? n a n y a te c hnology corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8haag 512mb : 64m x 64 pc2700 unbuffered dimm ac t i ming s p ecifications for d dr sdram devices used on module (t a = 0 c ~ 7 0 c; v ddq = 2.5v 0.2v; v dd = 2. 5v 0.2v, see a c characte ristics) (part 2 of 2) -6 s y mbol p a r a m e t e r m i n . m a x . uni t n o t e s t is address and control input setup time (slow sle w rate) 1 . 0 n s 2, 3, 4, 10, 11, 12, 14 t ip w i n p u t p u l s e w i d t h 2 . 2 n s 2, 3, 4, 12 t rpre r e a d pre a m b l e 0 . 9 1 . 1 t ck 1,2,3,4 t rpst r e a d postamble 0 . 4 0 0 . 6 0 t ck 1,2,3,4 t ras active to precharge command 45 120,000 ns 1,2,3,4 t rc active to active/ a uto-ref r esh command period 65 ns 1,2,3,4 t rfc auto-ref r esh to a c tive/auto-refres h command period 7 5 n s 1 , 2 , 3 , 4 t rcd active to read or write dela y 20 ns 1,2,3,4 t rap active to read command w i th au to-precha r ge 20 ns 1,2,3,4 t rp precharge comm and period 20 ns 1,2,3,4 t rrd active bank a to active bank b co mmand 15 ns 1,2,3,4 t wr write recover y ti me 15 ns 1,2,3,4 t dal auto precharg e write recover y + recharge time (t wr /t ck ) + (t rp /t ck ) t ck 1, 2, 3, 4, 13 t wt r internal w r ite to r ead command d e la y 1 t ck 1 , 2 , 3 , 4 t xsnr exit self-refresh t o non-r ead com m and 75 ns 1,2,3,4 t xsrd exit self-refresh t o read command 200 t ck 1 , 2 , 3 , 4 t refi a v e r a g e periodic refres h inte rval 7.8 s 1, 2, 3, 4, 8 rev 1.0 0 6 / 2002 1 2 ? n a n y a te c hnology corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8haag 512mb : 64m x 64 pc2700 unbuffered dimm ac t i ming s p ecification notes 1. input slew rate = 1v/ns. 2. the ck/ ck input r e ference level (fo r timing referenc e to ck/ ck ) is the point at w h ich ck and ck cross: the input refe rence level for signals other than ck/ ck is v ref . 3. inputs are no t recognized as valid until v ref sta b ilize s . 4. the output ti ming reference l e vel, as measured at the timing re ferenc e point indicated in ac char acteristics (note 3) is v tt. 5. t hz and t lz transitions occur in the same access time w i ndo w s as va lid data transitions. these parameters a r e not refer r ed to a specific voltage level, but specify w h en the device is no longer driving (hz ) , or begin s driving (lz). 6. the ma ximum limit for this parameter is not a de vice limit. the device operates w i t h a greate r value for this paramet er, but sy s t e m performa n ce (bu s turnaround ) de grades according l y . 7. the specific requirement is that dqs be valid (hi gh, low , or some point on a valid transition) on or b e fore this ck ed ge. a valid transition is defin ed as monotonic and meeting the i nput slew rate sp ecification s of the device. when no w r ites w e re pr eviously in pr ogr ess on the bus, d q s w ill be tr ansitioning fr om h i - z to logic low. if a pr evious w r ite w a s in pr ogr e ss, d q s could be h i gh , lo w , or transitioning fr om high to lo w at this time, depending on tdqss. 8. a maxi mum of ei ght auto refr esh commands can be posted to an y gi ven ddr sdr a m devi c e. 9. for comman d / address input slew rate >= 1.0 v/n s . slew rate is measured bet w e en v oh (ac) and v ol (ac). 10. for comma n d /address input slew r a te >= 0.5 v / ns and < 1.0 v/n s . slew rate is measured bet w e en v oh (ac) and v ol (ac). 11. ck/ ck slew rate s are >= 1.0 v/ns. 12. these pa ram e ters guaran tee device timi ng, bu t the y a r e not n e c essarily tested on each device, and the y ma y be guarantee d b y design or tester c haracterization. 13. for each of t he terms in pare n theses, if not alread y an inte g e r, round to th e ne xt highest integer. t ck is equal to the ac tual sy stem clock cy cle time. for e x ample, fo r pc2100 at cl= 2. 5, t dal = (1 5n s/7.5ns) +(20ns/ 7 .0ns) = 2 + 3 = 5. 14. an input setu p and hold time d e rating tabl e is used to increase t is and t ih in the case w h e r e the i nput slew rate is belo w 0 . 5 v/ns. input slew rate ?delta (tis ) d e l t a (tih ) u n i t n o t e 0.5 v/ns 0 0 ps 1,2 0.4 v/ns +50 0 ps 1,2 0.3 v/ns +100 0 ps 1,2 1. input slew rate is based on the lesser of the slew rates determine d b y either v ih ( a c) to v il ( a c) or v ih (dc) to v i l ( dc), similar l y for rising transitions. 2. these der ating paramete r s ma y be gua rantee d b y design or te st er characterization and are n o t ne cessarily tested on each devi ce. 15. an input setu p and hold time d e rating tabl e is used to increase t ds and t dh in t he case w h e r e th e i/o sle w rat e is below 0.5 v/ns. input slew rate delta (tds ) d e l t a (tdh ) u n i t n o t e 0.5 v/ns 0 0 ps 1,2 0.4 v/ns +75 +75 ps 1,2 0.3 v/ns +150 +150 ps 1,2 1. i/o sle w rat e is based on the lesser of the slew r a tes determined b y either v ih ( a c) to v il (ac) or v ih (dc) to v i l (dc) , s i mi l a rl y for rising transitions. 2. these der ating paramete r s ma y be gua rantee d b y design or te st er characterization and are n o t ne cessarily tested on each devi ce. 16. an i/o delta rise, fall derating table is used to increase t ds an d t dh in the cas e where dq, dm , and d q s slew r a tes diffe r. delta rise and f a ll rate delta (tds ) d e l t a (tdh ) u n i t n o t e 0.0 ns/v 0 0 ps 1,2,3,4 0.25 ns/v +50 +50 ps 1,2,3,4 0.5 ns/v +100 +100 ps 1,2,3,4 1. input slew rate is based on the lesser of the slew rates determine d b y either v ih ( a c) to v il ( a c) or v ih (dc) to v i l ( dc), similar l y for rising transitions. 2. input slew rate is based on the larger of ac to a c delta rise, fall rate and dc t o d c delta rise, fall rate. 3. the delta rise, fall rate is calcu l ated as : [1/(sle w rate 1)] - [1/ ( slew rate 2)] for e x ample: slew rate 1 = 0. 5 v/ ns; slew rate 2 = 0.4 v/ ns. delta ri se, fall = (1/0.5) - (1/0.4) [ n s/v] = -0.5 ns/v using the table above, this w oul d result in an increase in t ds and t dh of 100 ps. 4. these der ating paramete r s ma y be gua rantee d b y design or test er characterization and are n o t ne cessarily tested on each device. rev 1.0 0 6 / 2002 1 3 ? n a n y a te c hnology corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8haag 512mb : 64m x 64 pc2700 unbuffered dimm packag e dimensions no t e : a l l di m e ns i ons ar e t y pi c a l unl e s s ot he rw i s e s t at ed. 13 3.35 128.95 1.25 0 0.157 0.700 fr o n t sid e 0 . 394 1 . 27+ /- 0. 10 d e t a il a 1.27 p i tch d e t a il b 1.00 w i d t h 3.99 d e t a il a d e t a il b 0.091 2. 50 3.80 1.80 6.35 5. 2 5 5.077 2.3 (2x)4.00 17.80 31.7 5 10 . 0 0. 098 0.1 57 m a x . 0.05 0 + / - 0.00 4 0.05 0.039 0.071 0.25 0 0.150 4.00 0.15 7 bac k un i t : inches m illim e t e r s rev 1.0 0 6 / 2002 1 4 ? n a n y a te c hnology corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .

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