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preliminary rev. 0.3 11/10 copyright ? 2010 by silicon laboratories si5324 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si5324 a ny -f requency p recision c lock m ultiplier /j itter a ttenuator features ? generates any frequency from 2 khz to 945 mhz and select frequencies to 1.4 ghz from an input frequency of 2 khz to 710 mhz ? ultra-low jitter clock outputs as low as 290 fs rms (12khz?20mhz), 320 fs rms (50khz?80mhz) ? integrated loop filter with selectable loop bandwidth (4? 525 hz) ? meets itu-t g.8251 and telcordia gr-253-core jitter specification ? hitless input clock switching with phase build-out ? freerun, digital hold operation ? configurable signal form at per output (lvpecl, lvds, cml, cmos) ? support for itu g.709 and custom fec ratios (255/238, 255/237, 255/236, 239/237, 66/64, 239/238, 15/14, 253/221, 255/238) ? lol, los, fos alarm outputs ? i 2 c or spi programmable ? on-chip voltage regulator with high psnr ? single supply 1.8 5%, 2.5 10%, or 3.3 v 10% ? small size: 6 x 6 mm 36-lead qfn applications ? broadcast video ?3g/hd/sd-sdi, genlock ? packet optical transport systems (p-ots), mspp ? otn otu-1/2/3/4 asynchronous demapping (gapped clock) ? sonet oc-48/192/768, sdh/stm-16/64/256 line cards ? 1/2/4/8/10g fibre channel line cards ? gbe/10/40/100g synchronous ethernet (lan/wan) ? data converter clocking ? wireless base stations ? test and measurement description the si5324 is a low-bandwidth, jitter-attenuating, precision clock multiplier for applicatio ns requiring sub 1 ps jitter performance with loop bandwidths between 4 hz and 525 h z. the si5324 accepts two input clocks ranging from 2 khz to 710 mhz and generates two output clocks ranging from 2 khz to 945 mhz and select frequencies to 1.4 ghz. the two outputs are divided down separately from a common source. the si5324 can also use its external reference as a clock source for frequency synthesis. the device provides virtually any frequency translation combination across this operating range. the si 5324 input clock frequency and clock multiplication ratio are programmable via an i 2 c or spi interface. the si5324 is base d on silicon laborato ries' 3rd-generation dspll ? technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated pll solution that eliminates the need for external vcxo and filter components. the dspll loop bandwidth is digitally programmable, providing jitter performanc e optimization at the application leve l. the si5324 is id eal for providing clock multiplication an d jitter attenuation in high performance timing applications.
si5324 2 preliminary rev. 0.3 functional block diagram dspll ? loss of signal/ frequency offset xtal or refclock ckout2 ckin1 ckout1 ckin2 n31 n2 nc1_ls nc2_ls skew adjust signal detect device interrupt vdd (1.8, 2.5, or 3.3 v) gnd n32 loss of lock clock select i 2 c/spi port control rate select n1_hs xtal/refclock
si5324 preliminary rev. 0.3 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical phase noise perf ormance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.1. external reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2. additional docum entation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4. pin descriptions: si5324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6. register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 6.1. ical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8. package outline: 36-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9. recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10. si5324 device top mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
si5324 4 preliminary rev. 0.3 1. electrical specifications table 1. performance specifications (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit temperature range t a ?40 25 85 oc supply voltage v dd 2.97 3.3 3.63 v 2.25 2.5 2.75 v 1.71 1.8 1.89 v supply current i dd f out = 622.08 mhz both ckouts enabled lvpecl format output ?251279ma ckout2 disabled ? 217 243 ma f out = 19.44 mhz both ckouts enabled cmos format output ?204234ma ckout2 disabled ? 194 220 ma disable mode ? 165 ? ma input clock frequency (ckin1, ckin2) ck f input frequency and clock multiplication ratio deter- mined by programming device pll dividers. con- sult silicon laboratories con- figuration software dspll sim to determine pll divider settings for a given input frequency/clock multi- plication ratio combination. 0.002 ? 710 mhz output clock frequency (ckout1, ckout2) ck of 0.002 970 1213 ? ? ? 945 1134 1400 mhz 3-level input pins (rate0 and rate1) input mid current i imm see note 2. ?2 ? 2 a input clocks (ckin1, ckin2) differential voltage swing ckn dpp 0.25 ? ? vpp common mode voltage ckn vcm 1.8 v 5% 0.9 ? 1.4 v 2.5 v 10% 1.0 ? 1.7 v 3.3 v 10% 1.1 ? 1.95 v rise/fall time ckn trf 20?80% ? ? 11 ns duty cycle (minimum pulse width) ckn dc whichever is smaller 40 ? 60 % 2??ns notes: 1. for a more comprehensive listing of device specificat ions, please consult the silicon laboratories any-frequency precision clock family reference manual. this document can be downloaded from www.silabs.com/timing . 2. this is the amount of leakage that the 3-level input can tolerate from an external driver. see the family reference manual. in most designs an external resistor voltage divider is recommended.
si5324 preliminary rev. 0.3 5 output clocks (ckout1, ckout2) common mode v ocm lvpecl 100 ? load line-to-line v dd ?1.42 ? v dd ?1.25 v differential output swing v od 1.1 ? 1.9 v single ended output swing v se 0.5 ? 0.93 v rise/fall time cko trf 20?80%, f out = 622.08 mhz ? 230 350 ps differential duty cycle uncertainty cko dc lvpecl 100 ? load line-to-line measured at 50% point ??40ps pll performance (f in = f out = 622.08 mhz, bw = 7 hz) lock time t lock end of ical to ?? of lol loop bandwidth = 7 hz, fast_lock = 1, lockt = 1 1sec settle time t settle end of ical to 180 c of final phase 60 sec phase change after hitless switch t p-step 100 200 ps jitter generation lvpecl output format j gen 50 khz?80 mhz ? 320 420 fs rms 12 khz?20 mhz ? 290 410 fs rms 800 hz?80 mhz ? 320 450 fs rms jitter peaking j pk ??0.1db phase noise cko pn 100 hz offset ? ?95 ? dbc/hz 1 khz offset ? ?110 ? dbc/hz 10 khz offset ? ?117 ? dbc/hz 100 khz offset ? ?118 ? dbc/hz 1 mhz offset ? ?131 ? dbc/hz spurious noise sp spur max spur @ n x f3 (n > 1, n x f3 < 100 mhz) ??67?dbc package thermal resistance junction to ambient ? ja still air ? 32 ? oc/w thermal resistance case to ambient ? jc still air ? 14 ? oc/w table 1. performance specifications (continued) (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit notes: 1. for a more comprehensive listing of device specificat ions, please consult the silicon laboratories any-frequency precision clock family reference manual. this document can be downloaded from www.silabs.com/timing . 2. this is the amount of leakage that the 3-level input can tolerate from an external driver. see the family reference manual. in most designs an external resistor voltage divider is recommended.
si5324 6 preliminary rev. 0.3 table 2. absolute maximum ratings parameter symbol test condition min typ max unit dc supply voltage v dd ?0.5 ? 3.8 v lvcmos input voltage v dig ?0.3 v dd +0.3 v ckinn voltage level limits ckn vin 0?v dd v xa/xb voltage level limits xa vin 0?1.2v operating junction temperature t jct ?55 ? 150 oc storage temperature range t stg ?55 ? 150 oc esd hbm tolerance (100 pf, 1.5 k ? ); all pins except ckin+/ckin? 2??kv esd mm tolerance; all pins except ckin+/ckin? 150 ? ? v esd hbm tolerance (100 pf, 1.5 k ? ); ckin+/ckin? 750 ? ? v esd mm tolerance; ckin+/ckin? 100 ? ? v latch-up tolerance jesd78 compliant note: permanent device damage may occur if the absolute maximum ratings are exceeded. functi onal operation should be restricted to the conditions as specif ied in the operation sections of this data sheet. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
si5324 preliminary rev. 0.3 7 2. typical phase noise performance figure 1. broadcast video jitter bandwidth jitter (peak-peak) jitter (rms) 10 hz to 20 mhz 5.24 ps 484 note: number of samples: 8.91e9
si5324 8 preliminary rev. 0.3 figure 2. otn/sonet/sdh phase noise note: phase noise plot uses brick wall integration. jitter bandwidth jitter, rms sonet_oc48, 12 khz to 20 mhz 266 fs sonet_oc192_a, 20 khz to 80 mhz 283 fs sonet_oc192_b, 4 mhz to 80 mhz 155 fs sonet_oc192_c, 50 khz to 80 mhz 275 fs brick wall_800 hz to 80 mhz 287 fs note: jitter integration bands include low-pass (?20 db/dec) and hi-pass (?60 db/dec) roll-offs per telecordia gr-253-core.
si5324 preliminary rev. 0.3 9 figure 3. wireless base station phase noise jitter bandwidth jitter (peak-peak) jitter (rms) 10 hz to 20 mhz 7.28 ps 581 note: number of samples: 8.91e9
si5324 10 preliminary rev. 0.3 figure 4. si5324 typical application circuit (i 2 c control mode) figure 5. si5324 typical application circuit (spi control mode) gnd pad si5324 int_c1b c2b lol rst ckout1+ ckout1? vdd gnd ferrite bead system power supply c 1 c 2 c 3 serial data serial clock reset interrupt/ckin_1 invalid indicator ckin_2 invalid indicator pll loss of lock indicator clock outputs ckout2+ ckout2? sda scl i2c interface serial port address a[2:0] cmode control mode (l) 100 ? 0.1 f 0.1 f + ? 100 ? 0.1 f 0.1 f + ? c 4 0.1 f 0.1 f 0.1 f 1 f clock select/clock active cs_ca 1. assumes differential lvpecl termination (3.3 v) on clock inputs. 2. denotes tri-level input pins with states designated as l (ground), m (vdd/2), and h (vdd). notes: xa xb refclk+ option 2: 0.1 f refclk? 0.1 f rate[1:0] 2 crystal/ref clk rate v dd 15 k ? 15 k ? xa xb crystal option 1: input clock sources* ckin2+ ckin2? 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v ckin1+ ckin1? gnd pad si5324 rst ckout1+ ckout1? vdd gnd ferrite bead system power supply c 1 c 2 c 3 reset clock outputs ckout2+ ckout2? cmode control mode (h) ckin2+ ckin2? 100 ? 0.1 f 0.1 f + ? 100 ? 0.1 f 0.1 f + ? c 4 0.1 f 0.1 f 0.1 f 1 f ckin1+ ckin1? int_c1b c2b spi interface lol interrupt/clkin_1 invalid indicator clkin_2 invalid indicator pll loss of lock indicator serial data out serial data in sdo sdi serial clock sclk slave select ss clock select/clock active cs_ca gnd pad 1. assumes differential lvpecl termination (3.3 v) on clock inputs. 2. denotes tri-level input pins with states designated as l (ground), m (vdd/2), and h (vdd). notes: input clock sources* 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v xa xb refclk+ option 2: 0.1 f refclk? 0.1 f rate[1:0] 2 crystal/ref clk rate v dd 15 k ? 15 k ? xa xb crystal option 1:
si5324 preliminary rev. 0.3 11 3. functional description figure 6. si5324 functional block diagram the si5324 is a low loop bandwidth, jitter-attenuating clock multiplier for high performance applications. the si5324 accepts two input clocks ranging from 2 khz to 710 mhz and generates two ou tput clocks ranging from 2 khz to 945 mhz and select frequencies to 1.4 ghz. the si5324 can also use its external reference as a clock source for frequen cy synthesis. the device provides virtually any frequency translation combination across this operating range. independent dividers are available for each input clock and output clock, so the si5324 can accept input clocks at different frequencies and it can generate outpu t clocks at different frequencies. the si5324 input clock frequency and clock multiplication ratio are programmable through an i 2 c or spi interface. silicon laboratories offers a pc- based software utility, dspll sim , that can be used to determine the optimum pll divider settings for a given input frequency/clock multip lication ratio combination that minimizes phase noise and power consumption. this utility can be downloaded from http://www.silabs.com/timing . the si5324 is based on s ilicon laboratories' 3rd- generation dspll ? technology, which provides any- frequency synthesis and jitter attenuation in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the si5324 pll loop bandwidth is digitally programmable and supports a range from 4 hz to 525 hz. a fast lock feature is available to reduce lock times inherent with low loop bandwidth plls. the dspll sim software utility can be used to calcul ate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. the si5324 supports hitless switching between the two synchronous input clocks in compliance with telcordia gr-253-core that greatly minimizes the propagation of phase transients to the clock outputs during an input clock transition (maximum 200 ps phase change). manual and automatic revertive and non-revertive input clock switching options are available. the si5324 monitors both input clocks for loss-of-signal (los) and provides a los alarm when it detects missing pulses on either input clock. the device monitors the lock status of the pll. the lock detect algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. due to the low loop bandwidth of the part, the lol indicator clears before the loop fully settles. the si5324 also monitors frequency offset alarms (fos), which indicate if an input clock is within a specified frequency ppm accuracy relative to the frequency of an xa/xb reference clock. both stratum 3/3e and sonet minimum clock (smc) fos thresholds are supported. the si5324 provides a digital hold capability that allows the device to continue generation of a stable output clock when the selected inpu t reference is lost. during digital hold, the dspll generates an output frequency based on a historical average frequency that existed a fixed amount of time before the error event occurred, eliminating the effects of phase and frequency transients that may occur immediately preceding digital hold. dspll ? loss of signal/ frequency offset xtal or refclock ckout2 ckin1 ckout1 ckin2 n31 n2 nc1_ls nc2_ls skew adjust signal detect device interrupt vdd (1.8, 2.5, or 3.3 v) gnd n32 loss of lock clock select i 2 c/spi port control rate select n1_hs xtal/refclock
si5324 12 preliminary rev. 0.3 the si5324 has two differential clock outputs. the signal format of each clock output is independently programmable to suppor t lvpecl, lvds, cml, or cmos loads. when configured for cmos , four clock outputs are available. if not required, the second clock output can be powered down to minimize power consumption. in addition, the phase of one output clock may be adjusted in relation to the phase of the other output clock. the resolution varies from 800 ps to 2.2 ns depending on the pll divider settings. the dspll sim software utility determines the phase offset resolution for a given combination of input clock and multiplication ratio. for system- level debugging, a bypass mode is available which drives t he output clock directly from the input clock, bypassing the internal dspll. the device is powered by a sing le 1.8, 2.5, or 3.3 v supply with best-in-class psnr. 3.1. external reference an external, high quality 38.88 mhz clock or a low-cost 114.285 mhz 3rd overtone cryst al or external reference is used as part of a fixed-frequency osc illator within the dspll. this external re ference is required for the device to perform jitter attenuation. specific recommendations can be found in the family reference manual. in digital hold, the dspll remains locked and tracks t he external reference. note that crystals can have temperature sensitivities. due to the low bandwidth capabilities of this part, any low-frequency wander or instability on the external reference will transfer to the output clocks. to ad dress this issue, a stable external reference, txco, ocxo, or thermally- isolated crystal is recommended. for example, with a 20 ppm oscillator as the reference on the xa/xb pi ns, temperature c hanges cause the oscillator to change frequency s lightly. although the si5324 is locked to it s input on clkin, it also uses the xa/xb as a reference. 3.2. additional documentation consult the silicon laboratories an y-frequency precision clo ck family reference m anual (frm) for detailed information about th e si5324. additional de sign support is available from silicon laborator ies through your distributor. silicon laboratories offers a pc-b ased software utility called dspll sim to simplify device configuration, including frequency planning and loop bandwidth selection. the frm and this utility can be downloaded from http://www.silabs.com/timing .
si5324 preliminary rev. 0.3 13 4. pin descriptions: si5324 pin # pin name i/o signal level description 1 rst ilvcmos external reset. active low input that performs ex ternal hardware reset of device. resets all internal logic to a known state and forces the device reg- isters to their default value. clock outputs are disabled during reset. the part must be programmed after a reset or power-on to get a clock output. see family reference manual for details. this pin has a weak pull-up. 2, 9, 14, 30, 33 nc no connection. leave floating. make no external connections to this pin for normal operation. 3 int_c1b o lvcmos interrupt/ckin1 invalid indicator. this pin functions as a device inte rrupt output or an alarm output for ckin1. if used as an interrupt output, int_pin must be set to 1. the pin functions as a maskable interrupt output with active polarity con- trolled by the int_pol register bit. if used as an alarm output, the pin functions as a los (and option- ally fos) alarm indicator for ckin1. set ck1_bad_pin = 1 and int_pin =0. 0 = ckin1 present. 1 = los (fos) on ckin1. the active polarity is controlled by ck_bad_pol . if no function is selected, the pin tristates. 4c2bolvcmos ckin2 invalid indicator. this pin functions as a los (and optionally fos) alarm indicator for ckin2 if ck2_bad_pin = 1. 0 = ckin2 present. 1 = los (fos) on ckin2. the active polarity can be changed by ck_bad_pol. if ck2_bad_pin = 0, the pin tristates. note: internal register names are indi cated by underlined italics, e.g., int_pin . see si5324 register map. 1 2 3 29 30 31 32 33 34 35 36 20 21 22 23 24 25 26 27 10 11 12 13 14 15 16 17 4 5 6 7 8 nc nc rst c2b int_c1b gnd vdd xa vdd rate0 ckin2+ ckin2? nc rate1 ckin1+ ckin1? cs_ca scl sda_sdo a1 a2_ss sdi ckout1? nc gnd vdd nc ckout2? ckout2+ cmode gnd pad a0 gnd 9 18 19 28 xb lol gnd ckout1+
si5324 14 preliminary rev. 0.3 5, 10, 32 v dd v dd supply supply. the device operates from a 1.8, 2.5, or 3.3 v supply. bypass capac- itors should be associated with the following vdd pins: 50.1f 10 0.1 f 32 0.1 f a 1.0 f should also be placed as clos e to the device as is practical. 7 6 xb xa ianalog external crystal or reference clock. external crystal should be connect ed to these pins to use internal oscillator based reference. refer to family reference manual for interfacing to an external refere nce. external reference must be from a high-quality clock source (tcxo, ocxo). frequency of crys- tal or external clock is set by rate[1:0] pins. 8, 31, 20, 19 gnd gnd supply ground. must be connected to system ground. minimize the ground path impedance for optimal performance of this device. grounding these pins does not eliminate the requirement to ground the gnd pad on the bottom of the package. 11 15 rate0 rate1 i 3-level external crystal or reference clock rate. three level inputs that select the type and rate of external crystal or reference clock to be applied to the xa/xb port. refer to the family reference manual for settings. these pins have both a weak pull-up and a weak pull-down; they default to m. l setting corresponds to ground. m setting corresponds to v dd /2. h setting corresponds to v dd . some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 16 17 ckin1+ ckin1? imulti clock input 1. differential input clock. this input can also be driven with a single- ended signal. input frequency range is 2 khz to 710 mhz. 12 13 ckin2+ ckin2? imulti clock input 2. differential input clock. this input can also be driven with a single- ended signal. input frequency range is 2 khz to 710 mhz. 18 lol o lvcmos pll loss of lock indicator. this pin functions as the active high pll loss of lock indicator if the lol_pin register bit is set to 1. 0 = pll locked. 1 = pll unlocked. if lol_pin = 0, this pin will tristate. active polarity is controlled by the lol_pol bit. the pll lock status will always be reflected in the lol_int read only register bit. pin # pin name i/o signal level description note: internal register names are indi cated by underlined italics, e.g., int_pin . see si5324 register map.
si5324 preliminary rev. 0.3 15 21 cs_ca i/o lvcmos input clock select/active clock indicator. input : in manual clock selection mode , this pin functions as the manual input clock selector if the cksel_pin is set to 1. 0 = select ckin1. 1 = select ckin2. if cksel_pin = 0, the cksel_reg register bit controls this func- tion and this input tristates. if conf igured for input, must be tied high or low. output : in automatic clock selection mode, this pin indicates which of the two input clocks is currently the active clock. if alarms exist on both clocks, ck_actv will indicate the last active clock that was used before entering the digital hold state. the ck_actv_pin reg- ister bit must be set to 1 to reflect the active clock status to the ck_actv output pin. 0 = ckin1 active input clock. 1 = ckin2 active input clock. if ck_actv_pin = 0, this pin will tristate. the ck_actv status will always be reflected in the ck_actv_reg read only register bit. 22 scl i lvcmos serial clock. this pin functions as the serial clock input for both spi and i 2 c modes. this pin has a weak pull-down. 23 sda_sdo i/o lvcmos serial data. in i 2 c control mode (cmode = 0), this pin functions as the bidirec- tional serial data port. in spi control mode (cmode = 1), th is pin functions as the serial data output. 25 24 a1 a0 ilvcmos serial port address. in i 2 c control mode (cmode = 0), thes e pins function as hardware controlled address bits. the i 2 c address is 1101 [a2] [a1] [a0]. in spi control mode (cmode = 1), these pins are ignored. these pins have a weak pull-down. 26 a2_s s ilvcmos serial port address/slave select. in i 2 c control mode (cmode = 0), this pin functions as a hardware controlled address bit [a2]. in spi control mode (cmode = 1), this pin functions as the slave select input. this pin has a weak pull-down. 27 sdi i lvcmos serial data in. in i 2 c control mode (cmode = 0), this pin is ignored. in spi control mode (cmode = 1), th is pin functions as the serial data input. this pin has a weak pull-down. pin # pin name i/o signal level description note: internal register names are indi cated by underlined italics, e.g., int_pin . see si5324 register map.
si5324 16 preliminary rev. 0.3 29 28 ckout1? ckout1+ omulti output clock 1. differential output clock with a frequency range of 8 khz to 1.4175 ghz. output signal format is selected by sfout1_reg register bits. ou tput is differential fo r lvpecl, lvds, and cml compatible modes. for cmos format, both output pins drive identi- cal single-ended clock outputs. 34 35 ckout2? ckout2+ omulti output clock 2. differential output clock with a frequency range of 8 khz to 1.4175 ghz. output signal format is selected by sfout2_reg register bits. ou tput is differential fo r lvpecl, lvds, and cml compatible modes. for cmos format, both output pins drive identi- cal single-ended clock outputs. 36 cmode i lvcmos control mode. selects i 2 c or spi control mode for the si5324. 0=i 2 c control mode 1 = spi control mode this pin must not be nc. tie either high or low. gnd pad gnd gnd supply ground pad. the ground pad must provide a low thermal and electrical impedance to a ground plane. pin # pin name i/o signal level description note: internal register names are indi cated by underlined italics, e.g., int_pin . see si5324 register map.
si5324 preliminary rev. 0.3 17 5. register map all register bits that are not defined in this map shou ld always be written with the specified reset values. the writing to these bits of values other than the specif ied reset values may result in undefined device behavior. registers not listed, e.g. register 64, should never be written to. register d7 d6 d5 d4 d3 d2 d1 d0 0 free_run ckout_ always_on bypass_reg 1 ck_prior2[1:0] ck_prior[1:0] 2 bwsel_reg[3:0] 3 cksel_reg[1:0] dhold sq_ical 4 autosel_reg[1:0] hst_del[4:0] 5 icmos[1:0] 6 sleep sfout2_reg[2:0} sfout1_reg[2:0] 7 fosrefsel[2:0] 8 hlog_2[1:0] hlog_1[1:0] 9 hist_avg[4:0] 10 dsbl2_ reg dsbl1_ reg 11 pd_ck2 pd_ck1 19 fos_en fos_thr[1:0] valtime[1:0] lock[t2:0] 20 ck2_bad_pin ck1_ bad_ pin lol_pin int_pin 21 ck1_actv_pin cksel_pin 22 ck_actv_ pol ck_bad_ pol lol_pol int_pol 23 los2_msk los1_msk losx_msk 24 fos2_msk fos1_msk lol_msk 25 n1_hs[2:0] 31 nc1_ls[19:16] 32 nc1_ls[15:8] 33 nc1_ls[7:0] 34 nc2_ls[19:16] 35 nc2_ls[15:8] 36 nc2_ls[7:0] 40 n2_hs[2:0] n2_ls[19:16] 41 n2_ls[15:8] 42 n2_ls[7:0] 43 n31[18:16] 44 n31[15:8] 45 n31[7:0] 46 n32[18:16]
si5324 18 preliminary rev. 0.3 47 n32[15:8] 48 n32[7:0] 55 clkin2rate[2:0] clkin1rate[2:0] 128 ck2_actv_reg ck1_actv_reg 129 los2_int los1_int losx_int 130 dighold- valid fos2_int fos1_int lol_int 131 los2_flg los1_flg losx_flg 132 fos2_flg fos1_flg lol_flg 134 partnum_ro[11:4] 135 partnum_ro[3:0] revid_ro[3:0] 136 rst_reg ical 137 fastlock 138 los2_en [1:1] los1_en [1:1] 139 los2_en[0:0] los1_en[0:0] fos2_en fos1_en 142 independentskew1[7:0] 143 independentskew2[7:0] 185 nvm_revid[7:0] table 3. ckout_always_on and sq_ical truth table ckout_always_on sq_ical results 0 0 ckout off until after the first ical 0 1 ckout off until after the first successful ical (i.e., when lol is low) 1 0 ckout always on, including during an ical 1 1 ckout always on, including during an ical. use these settings to pr eserve output-to-output skew register d7 d6 d5 d4 d3 d2 d1 d0
si5324 preliminary rev. 0.3 19 6. register descriptions reset value = 0001 0100 register 0. bitd7d6 d5 d4d3d2d1d0 name free_run ckout_ always_on bypass_ reg type rr/wr/w rrrr/wr bit name function 7 reserved reserved. 6free_run free run. internal to the device, route xa/xb to ckin2. this allows the device to lock to its xa-xb reference. 0: disable 1: enable 5ckout_ always_on ckout always on. this will bypass the sq_ical func tion. output will be availabl e even if sq_ical is on and ical is not complete or successful. see table 3 on page 18. 0: squelch output until pa rt is calibrated (ical). 1: provide an output. notes: 1. the frequency may be significantly off until the part is calibrated. 2. must be 1 to control output to output skew. 4:2 reserved reserved. 1 bypass_ reg bypass register. this bit enables or disables the pll bypass mode. use only when the device is in digital hold or before the first ical. bypass mo de is not supported for cmos output clocks. 0: normal operation 1: bypass mode. selected input clock is c onnected to ckout buffers, bypassing pll. 0 reserved reserved.
si5324 20 preliminary rev. 0.3 reset value = 1110 0100 reset value = 0100 0010 register 1. bitd7d6d5d4d3d2d1d0 name reserved ck_prior2 [1:0] ck_prior1 [1:0] type rr/wr/w bit name function 7:4 reserved reserved. 3:2 ck_prior2 [1:0] ck_prior 2. selects which of the input clocks will be 2nd priority in the autose lection state machine. 00: ckin1 is 2nd priority. 01: ckin2 is 2nd priority. 10: reserved 11: reserved 1:0 ck_prior1 [1:0] ck_prior 1. selects which of the input clocks will be 1st priority in the autose lection state machine. 00: ckin1 is 1st priority. 01: ckin2 is 1st priority. 10: reserved 11: reserved register 2. bitd7d6d5d4d3d2d1d0 name bwsel_reg [3:0] reserved type r/w r bit name function 7:4 bwsel_reg [3:0] bwsel_reg. selects nominal f3db bandwidth for pll. see the dspllsim for settings. after bwsel_reg is written with a new value, an ical is required for the change to take effect. 3:0 reserved reserved.
si5324 preliminary rev. 0.3 21 reset value = 0000 0101 register 3. bitd7d6d5d4d3d2d1d0 name cksel_reg [1:0] dhold sq_ical reserved type r/w r/w r/w r bit name function 7:6 cksel_reg [1:0] cksel_reg. if the device is operating in regi ster-based manual clock selection mode (autosel_reg = 00), and cksel_pin = 0, then these bits select which input clock will be the active input clock. if ckse l_pin = 1 and autosel_reg = 00, the cs_ca input pin continues to co ntrol clock selection and cksel_reg is of no consequence . 00: ckin_1 selected. 01: ckin_2 selected. 10: reserved 11: reserved 5 dhold dhold. forces the part into digital hold. this bit overrides all other manual and automatic clock selection controls. 0: normal operation. 1: force digital hold mode. over rides all other settings and ignores the quality of all of the input clocks. 4 sq_ical sq_ical. this bit determines if the output clocks will remain enabled or be squelched (disabled) during an internal calibration. see table 3 on page 18. 0: output clocks enabled during ical. 1: output clocks disabled during ical. 3:0 reserved reserved.
si5324 22 preliminary rev. 0.3 reset value = 0001 0010 reset value = 1110 1101 register 4. bitd7d6d5d4d3d2d1d0 name autosel_reg [1:0] res erved hist_del [4:0] type r/w r r/w bit name function 7:6 autosel_ reg [1:0] autosel_reg [1:0] . selects method of input clock selection to be used. 00: manual (either register or pin controlled, see cksel_pin) 01: automatic non-revertive 10: automatic revertive 11: reserved 5 reserved reserved. 4:0 hist_del [4:0] hist_del [4:0]. selects amount of delay to be used in gener ating the history information used for digital hold. register 5. bitd7d6d5d4d3d2d1d0 name icmos [1:0] reserved type r/w r bit name function 7:6 icmos [1:0] icmos [1:0]. when the output buffer is set to cmos mode, these bits determine the output buffer drive strength. the first number below refers to 3.3 v operation; the second to 1.8 v operation. these values assume ckout+ is tied to ckout-. 00: 8ma/2ma. 01: 16ma/4ma 10: 24ma/6ma 11: 32ma/8ma 5:0 reserved reserved.
si5324 preliminary rev. 0.3 23 reset value = 0010 1101 register 6. bitd7d6d5d4d3d2d1d0 name reserved sleep sfout2_reg [2:0] sfout1_reg [2:0] type rr/w r/w r/w bit name function 7 reserved reserved. 6sleep sleep. in sleep mode, all clock outputs are disabled and the maximum amount of internal cir- cuitry is powered down to reduce power dissipation and noise generation. this bit over- rides the sfoutn_reg[2:0] ou tput signal format settings. 0: normal operation 1: sleep mode 5:3 sfout2_ reg [2:0] sfout2_reg [2:0]. controls output signal format and disable for ckout2 output buffer. bypass mode is not supported for cmos output clocks. 000: reserved 001: disable 010: cmos 011: low swing lvds 100: reserved 101: lvpecl 110: cml 111: lvds 2:0 sfout1_ reg [2:0] sfout1_reg [2:0]. controls output signal format and disable for ckout1 output buffer. bypass mode is not supported for cmos output clocks. 000: reserved 001: disable 010: cmos 011: low swing lvds 100: reserved 101: lvpecl 110: cml 111: lvds
si5324 24 preliminary rev. 0.3 reset value = 0010 1010 register 7. bitd7d6d5d4d3d2d1d0 name reserved fosrefsel [2:0] type rr/w bit name function 7:3 reserved. reserved. 2:0 fosrefsel [2:0] fosrefsel [2:0]. selects which input clock is used as the reference frequency fo r frequency off-set (fos) alarms. 000: xa/xb (external reference) 001: ckin1 010: ckin2 011: reserved 100: reserved 101: reserved 110: reserved 111: reserved
si5324 preliminary rev. 0.3 25 reset value = 0000 0000 reset value = 1100 0000 register 8. bitd7d6d5d4d3d2d1d0 name hlog_2[1:0] hlog_1[1:0] reserved type r/w r/w r bit name function 7:6 hlog_2 [1:0] hlog_2 [1:0]. 00: normal operation 01: holds ckout2 output at static logic 0. entrance and exit from this state will oc cur without glitches or runt pulses. 10:holds ckout2 output at static logic 1. entrance and exit from this state will oc cur without glitches or runt pulses. 11: reserved 5:4 hlog_1 [1:0] hlog_1 [1:0]. 00: normal operation 01: holds ckout1 output at static logic 0. entrance and exit from this state will oc cur without glitches or runt pulses. 10: holds ckout1 output at static logic 1. entrance and exit from this state will oc cur without glitches or runt pulses. 11: reserved 3:0 reserved reserved. register 9. bitd7d6d5d4d3d2d1d0 name hist_avg [4:0] reserved type r/w rrr bit name function 7:3 hist_avg [4:0] hist_avg [4:0]. selects amount of averaging time to be used in generating the history information for digital hold. 2:0 reserved reserved.
si5324 26 preliminary rev. 0.3 reset value = 0000 0000 reset value = 0100 0000 register 10. bitd7d6d5d4d3d2d1d0 name reserved dsbl2_ reg dsbl1_ reg reserved type rr/wr/wrr bit name function 7:4 reserved reserved. 3 dsbl2_reg dsbl2_reg. this bit controls the powerdown of the ck out2 output buffer. if disable mode is selected, the nc2 output divider is also powered down. 0: ckout2 enabled. 1: ckout2 disabled. 2 dsbl1_reg dsbl1_reg. this bit controls the powerdown of the ck out1 output buffer. if disable mode is selected, the nc1 output divider is also powered down. 0: ckout1 enabled. 1: ckout1 disabled. 1:0 reserved reserved. register 11. bitd7d6d5d4d3d2d1d0 name reserved pd_ck2 pd_ck1 type rr/wr/w bit name function 7:2 reserved reserved. 1pd_ck2 pd_ck2. this bit controls the powerdown of the ckin2 input buffer. 0: ckin2 enabled. 1: ckin2 disabled. 0pd_ck1 pd_ck1. this bit controls the powerdown of the ckin1 input buffer. 0: ckin1 enabled. 1: ckin1 disabled.
si5324 preliminary rev. 0.3 27 reset value = 0010 1100 register 19. bitd7d6d5d4d3d2d1d0 name fos_en fos_thr [1:0] valti me [1:0] lockt [2:0] type r/w r/w r/w r/w bit name function 7fos_en fos_en. frequency offset enable globally disabl es fos. see the individual fos enables (fosx_en, register 139). 0: fos disable 1: fos enabled by fosx_en 6:5 fos_thr [1:0] fos_thr [1:0]. frequency offset at which fos is declared: 00: 11 to 12 ppm (stratum 3/3e compliant, with a stratum 3/3e used for refclk 01: 48 to 49 ppm (smc) 10: 30 ppm (sonet minimum clock (smc), with a stratum 3/3e used for refclk. 11: 200 ppm 4:3 valtime [1:0] valtime [1:0]. sets amount of time for input clock to be valid before the associated alarm is removed. 00: 2 ms 01: 100 ms 10: 200 ms 11: 13 seconds 2:0 lockt [2:0] lockt [2:0]. sets retrigger interval for one shot monitoring phase detector output. one shot is trig- gered by phase slip in dspll. refer to the family reference manual for more details. to minimize lock time, the value 001 for lockt is recommended. 000: 106 ms 001: 53 ms 010: 26.5 ms 011: 13.3 ms 100: 6.6 ms 101: 3.3 ms 110: 1.66 ms 111: .833 ms
si5324 28 preliminary rev. 0.3 reset value = 0011 1110 register 20. bitd7d6d5d4 d3 d2 d1 d0 name reserved ck2_bad_pin ck1_bad_pin lol_pin int_pin type r r/w r/w r/w r/w bit name function 7:4 reserved reserved. 3 ck2_bad_pin ck2_bad_pin. the ck2_bad status can be reflected on the c2b output pin. 0: c2b output pin tristated 1: c2b status reflected to output pin 2 ck1_bad_pin ck1_bad_pin. the ck1_bad status can be reflected on the c1b output pin. 0: c1b output pin tristated 1: c1b status reflected to output pin 1lol_pin lol_pin. the lol_int status bit can be reflected on the lol output pin. 0: lol output pin tristated 1: lol_int status reflected to output pin 0int_pin int_pin. reflects the interrupt status on the int_c1b output pin. 0: interrupt status not displayed on int_ c1b output pin. if ck1_bad_pin = 0, int_c1b output pin is tristated. 1: interrupt status reflected to output pin. instead, the int_c1b pin indicates when ckin1 is bad.
si5324 preliminary rev. 0.3 29 reset value = 1111 1111 register 21. bit d7 d6d5d4d3d2 d1 d0 name reserved ck1_actv_pin cksel_ pin type r rrrrr r/w r/w bit name function 7:2 reserved reserved. 1 ck1_actv_pin ck1_actv_pin. the ck1_actv_reg status bit can be reflec ted to the cs_ca output pin using the ck1_actv_pin enable function. ck1_actv_pin is of consequence only when pin controlled clock selection is being used. 0: cs_ca output pin tristated. 1: clock active status reflected to output pin. 0 cksel_pin cksel_pin. if manual clock selection is being used, clock selection can be controlled via the cksel_reg[1:0] register bits or the cs_ca in put pin. this bit is only active when autosel_reg = manual. 0: cs_ca pin is ignored. cksel_reg[1:0] register bits control clock selection. 1: cs_ca input pin controls clock selection.
si5324 30 preliminary rev. 0.3 reset value = 1101 1111 register 22. bitd7d6d5d4 d3 d2 d1 d0 name reserved ck_actv_pol ck_bad_ pol lol_pol int_pol type r r/w r/w r/w r/w bit name function 7:4 reserved reserved. 3 ck_actv_ pol ck_actv_pol. sets the active polarity for the cs_ca signals when reflected on an output pin. 0: active low 1: active high 2 ck_bad_ pol ck_bad_pol. sets the active polarity fo r the int_c1b and c2b signals when reflected on output pins. 0: active low 1: active high 1 lol_pol lol_pol. sets the active polarity for the lol status when reflected on an output pin. 0: active low 1: active high 0int_pol int_pol. sets the active polarity fo r the interrupt status when reflected on the int_c1b out- put pin. 0: active low 1: active high
si5324 preliminary rev. 0.3 31 reset value = 0001 1111 register 23. bitd7d6d5d4d3 d2 d1 d0 name reserved los2_ msk los1_ msk losx_ msk type rr/wr/wr/w bit name function 7:3 reserved reserved. 2los2_msk los2_msk. determines if a los on ckin2 (los2_flg) is used in the generation of an interrupt. writes to this register do not change the value held in the los2_flg register. 0: los2 alarm triggers active interr upt on int_c1b output (if int_pin=1). 1: los2_flg ignored in generating interrupt output. 1los1_msk los1_msk. determines if a los on ckin1 (los1_flg) is used in the generation of an interrupt. writes to this register do not change the value held in the los1_flg register. 0: los1 alarm triggers active interr upt on int_c1b output (if int_pin=1). 1: los1_flg ignored in generating interrupt output. 0losx_msk losx_msk. determines if a los on xa/ xb(losx_flg) is used in the generation of an interrupt. writes to this register do not change the value held in the losx_flg register. 0: losx alarm triggers active interrup t on int_c1b output (if int_pin=1). 1: losx_flg ignored in generating interrupt output.
si5324 32 preliminary rev. 0.3 reset value = 0011 1111 register 24. bitd7d6d5d4d3 d2 d1 d0 name reserved fos2_msk fos1_msk lol_msk type rr/wr/wr/w bit name function 7:3 reserved reserved. 2 fos2_msk fos2_msk. determines if the fos2 _flg is used to in the generation of an interrupt. writes to this register do not change the value held in the fos2_flg register. 0: fos2 alarm triggers active interr upt on int_c1b output (if int_pin=1). 1: fos2_flg ignored in generating interrupt output. 1 fos1_msk fos1_msk. determines if the fos1_flg is used in the gen eration of an interrupt. writes to this reg- ister do not change the value held in the fos1_flg register. 0: fos1 alarm triggers active interr upt on int_c1b output (if int_pin=1). 1: fos1_flg ignored in generating interrupt output. 0lol_msk lol_msk. determines if the lol_flg is used in the generation of an interrupt. writes to this regis- ter do not change the value held in the lol_flg register. 0: lol alarm triggers active interrup t on int_c1b output (if int_pin=1). 1: lol_flg ignored in generating interrupt output.
si5324 preliminary rev. 0.3 33 reset value = 0010 0000 reset value = 0000 0000 register 25. bitd7d6d5d4d3d2d1d0 name n1_hs [2:0] reserved type r/w r bit name function 7:5 n1_hs [2:0] n1_hs [2:0]. sets value for n1 high speed divider which drives ncn_ls (n = 1 to 2) low-speed divider. 000: n1= 4 001: n1= 5 010: n1=6 011: n1= 7 100: n1= 8 101: n1= 9 110: n1= 10 111: n1= 11 4:0 reserved reserved. register 31. bitd7d6d5d4d3d2d1d0 name reserved nc1_ls [19:16] type rr/w bit name function 7:4 reserved reserved. 3:0 nc1_ls [19:16] nc1_ls [19:16]. sets value for nc1 low-speed divider, which drives ckout1 output. must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 valid divider values=[1, 2, 4, 6, ..., 2^20]
si5324 34 preliminary rev. 0.3 reset value = 0000 0000 reset value = 0011 0001 register 32. bitd7d6d5d4d3d2d1d0 name nc1_ls [15:8] type r/w bit name function 7:0 nc1_ls [15:8] nc1_ls [15:8]. sets value for nc1 low-speed divider, which drives ckout1 output. must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 valid divider values=[1, 2, 4, 6, ..., 2^20] register 33. bitd7d6d5d4d3d2d1d0 name nc1_ls [7:0] type r/w bit name function 7:0 nc1_ls [19:0] nc1_ls [7:0]. sets value for nc1 low-speed divider, which drives ckout1 output. must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 valid divider values=[1, 2, 4, 6, ..., 2^20]
si5324 preliminary rev. 0.3 35 reset value = 0000 0000 reset value = 0000 0000 register 34. bitd7d6d5d4d3d2d1d0 name reserved nc2_ls [19:16] type rr/w bit name function 7:4 reserved reserved. 3:0 nc2_ls [19:16] nc2_ls [19:16]. sets value for nc2 low-speed divider, which drives ckout2 output. must be 0 or odd. 00000000000000000000=1 00000000000000000001=2 00000000000000000011=4 00000000000000000101=6 ... 11111111111111111111=2^20 valid divider values=[1, 2, 4, 6, ..., 2^20] register 35. bitd7d6d5d4d3d2d1d0 name nc2_ls [15:8] type r/w bit name function 7:0 nc2_ls [15:8] nc2_ls [15:8] . sets value for nc2 low-speed divider, which drives ckout2 output. must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 valid divider values=[1, 2, 4, 6, ..., 2^20]
si5324 36 preliminary rev. 0.3 reset value = 0011 0001 register 36. bitd7d6d5d4d3d2d1d0 name nc2_ls [7:0] type r/w bit name function 7:0 nc2_ls [7:0] nc2_ls [7:0]. sets value for nc2 low-speed divider, which drives ckout2 output. must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 = 2 20 valid divider values = [1, 2, 4, 6, ..., 2 20 ]
si5324 preliminary rev. 0.3 37 reset value = 1100 0000 register 40. bitd7d6d5d4d3d2d1d0 name n2_hs [2:0] reserved n2_ls [19:16] type r/w r r/w bit name function 7:5 n2_hs [2:0] n2_hs [2:0]. sets value for n2 high speed divider which drives n2ls low-speed divider. 000: 4 001: 5 010: 6 011: 7 100: 8 101: 9 110: 10 111: 11 4 reserved reserved. 3:0 n2_ls [19:16] n2_ls [19:16]. sets value for n2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 = 2 20 valid divider values = [2, 4, 6, ..., 2 20 ]
si5324 38 preliminary rev. 0.3 reset value = 0000 0000 reset value = 1111 1001 register 41. bitd7d6d5d4d3d2d1d0 name n2_ls [15:8] type r/w bit name function 7:0 n2_ls [15:8] n2_ls [15:8]. sets value for n2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 = 2 20 valid divider values = [2, 4, 6, ..., 2 20 ] register 42. bitd7d6d5d4d3d2d1d0 name n2_ls [7:0] type r/w bit name function 7:0 n2_ls [7:0] n2_ls [7:0]. sets value for n2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 = 2 20 valid divider values = [2, 4, 6, ..., 2 20 ]
si5324 preliminary rev. 0.3 39 reset value = 0000 0000 reset value = 0000 0000 register 43. bitd7d6d5d4d3d2d1d0 name reserved n31 [18:16] type rr/w bit name function 7:3 reserved reserved. 2:0 n31 [18:16] n31 [18:16]. sets value for input divider for ckin1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 19 valid divider values = [1, 2, 3, ..., 2 19 ] register 44. bitd7d6d5d4d3d2d1d0 name n31_[15:8] type r/w bit name function 7:0 n31_[15:8] n31_[15:8]. sets value for input divider for ckin1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 19 valid divider values = [1, 2, 3, ..., 2 19 ]
si5324 40 preliminary rev. 0.3 reset value = 0000 1001 reset value = 0000 0000 register 45. bitd7d6d5d4d3d2d1d0 name n31_[7:0] type r/w bit name function 7:0 n31_[7:0 n31_[7:0]. sets value for input divider for ckin1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 19 valid divider values = [1, 2, 3, ..., 2 19 ] register 46. bitd7d6d5d4d3d2d1d0 name reserved n32_[18:16] type rr/w bit name function 7:3 reserved reserved. 2:0 n32_[18:16] n32_[18:16]. sets value for input divider for ckin1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 19 valid divider values = [1, 2, 3, ..., 2 19 ]
si5324 preliminary rev. 0.3 41 reset value = 0000 0000 reset value = 0000 1001 register 47. bitd7d6d5d4d3d2d1d0 name n32_[15:8] type r/w bit name function 7:0 n32_[15:8] n32_[15:8]. sets value for input divider for ckin1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 19 valid divider values = [1, 2, 3, ..., 2 19 ] register 48. bitd7d6d5d4d3d2d1d0 name n32_[7:0] type r/w bit name function 7:0 n32_[7:0] n32_[7:0]. sets value for input divider for ckin1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 19 valid divider values = [1, 2, 3, ..., 2 19 ]
si5324 42 preliminary rev. 0.3 reset value = 0000 0000 register 55. bitd7d6d5d4d3d2d1d0 name reserved clkin2rate_[2:0] clkin1rate[2:0] type rr/w r/w bit name function 7:6 reserved reserved. 5:3 clkin2rate[2:0] clkin2rate_[2:0]. ckinn frequency selection for fos alarm monitoring. 000: 10?27 mhz 001: 25?54 mhz 002: 50?105 mhz 003: 95?215 mhz 004: 190?435 mhz 005: 375?710 mhz 006: reserved 007: reserved 2:0 clkin1rate [2:0] clkin1rate[2:0]. ckinn frequency selection for fos alarm monitoring. 000: 10?27 mhz 001: 25?54 mhz 002: 50?105 mhz 003: 95?215 mhz 004: 190?435 mhz 005: 375?710 mhz 006: reserved 007: reserved
si5324 preliminary rev. 0.3 43 reset value = 0010 0000 reset value = 0000 0110 register 128. bitd7d6d5d4d3d2 d1 d0 name reserved ck2_actv_reg ck1_actv_reg type rrr bit name function 7:2 reserved reserved. 1ck2_actv_reg ck2_actv_reg. indicates if ckin2 is currently the active clock for the pll input. 0: ckin2 is not the active input clock. eith er it is not selected or los2_int is 1. 1: ckin2 is the active input clock. 0ck1_actv_reg ck1_actv_reg. indicates if ckin1 is currently the active clock for the pll input. 0: ckin1 is not the active input clock. eith er it is not selected or los1_int is 1. 1: ckin1 is the active input clock. register 129. bitd7d6d5d4d3 d2 d1 d0 name reserved los2_int los1_int losx_int type r rrr bit name function 7:3 reserved reserved. 2 los2_int los2_int. indicates the los status on ckin2. 0: normal operation. 1: internal loss-of-signal alarm on ckin2 input. 1 los1_int los1_int. indicates the los status on ckin1. 0: normal operation. 1: internal loss-of-signal alarm on ckin1 input. 0 losx_int losx_int. indicates the los status of the exte rnal reference on the xa/xb pins. 0: normal operation. 1: internal loss-of-signal alarm on xa/xb reference clock input.
si5324 44 preliminary rev. 0.3 reset value = 0000 0001 register 130. bit d7 d6 d5d4d3 d2 d1 d0 name reserved digholdvalid reserv ed fos2_int fos1_int lol_int type rrrrrr bit name function 6digholdvalid digital hold valid. indicates if the digital hold circuit has enough samples of a valid clock to meet dig- ital hold specifications. 0: indicates digital hold history register s have not been filled. the digital hold output frequency may not meet specifications. 1: indicates digital hold hist ory registers have been fille d. the digital hold output frequency is valid. 7, 5:3 reserved reserved. 2 fos2_int ckin2 frequency offset status. 0: normal operation. 1: internal frequency offset alarm on ckin2 input. 1 fos1_int ckin1 frequency offset status. 0: normal operation. 1: internal frequency offset alarm on ckin1 input. 0 lol_int pll loss of lock status. 0: pll locked. 1: pll unlocked.
si5324 preliminary rev. 0.3 45 reset value = 0001 1111 register 131. bitd7d6d5d4d3d2d1d0 name reserved los2_flg los1_flg losx_flg type r r/w r/w r/w bit name function 7:3 reserved reserved. 2los2_flg ckin2 loss-of-signal flag. 0: normal operation. 1: held version of los2_int. generates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by lo s2_msk bit. flag cleared by writing 0 to this bit. 1los1_flg ckin1 loss-of-signal flag. 0: normal operation 1: held version of los1_int. generates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by lo s1_msk bit. flag cleared by writing 0 to this bit. 0 losx_flg external reference (signal on pins xa/xb) loss-of-signal flag. 0: normal operation 1: held version of losx_int. ge nerates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by losx_msk bit. flag cleared by writing 0 to this bit.
si5324 46 preliminary rev. 0.3 reset value = 0000 0010 register 132. bitd7d6d5d4d3d2d1d0 name reserved fos2_flg fos1_flg lol_flg reserved type rr/wr/wr/wr bit name function 7:4, 0 reserved reserved. 3fos2_flg clkin_2 frequency offset flag. 0: normal operation. 1: held version of fos2_int. generates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by fo s2_msk bit. flag cleared by writing 0 to this bit. 2fos1_flg clkin_1 frequency offset flag. 0: normal operation 1: held version of fos1_int. generates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by fo s1_msk bit. flag cleared by writing 0 to this bit. 1lol_flg pll loss of lock flag. 0: pll locked 1: held version of lol_int. generates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by lo l_msk bit. flag cleared by writing 0 to this bit.
si5324 preliminary rev. 0.3 47 reset value = 0000 0001 reset value = 1010 0010 register 134. bitd7d6d5d4d3d2d1d0 name partnum_ro [11:4] type r bit name function 7:0 partnum_ro [11:0] device id (1 of 2). 0000 0001 1000: si5324 others reserved register 135. bitd7d6d5d4d3d2d1d0 name partnum_ro [3:0] revid_ro [3:0] type rr bit name function 7:4 partnum_ro [11:0] device id (2 of 2). 0000 0001 1000: si5324 others reserved 3:0 revid_ro [3:0] indicates revision number of device. 0010: revision c others reserved.
si5324 48 preliminary rev. 0.3 reset value = 0000 0000 register 136. bitd7d6d5d4d3d2d1d0 name rst_reg ical reserved type r/w r/w r bit name function 7 rst_reg internal reset (same as pin reset). note: the i2c (or spi) port may not be accessed until 10 ms after rst_reg is asserted. 0: normal operation. 1: reset of all internal logic. outputs disabled or tristated during reset. 6ical start an internal calibration sequence. for proper operation, the device must go through an internal calibration sequence. ical is a self-clearing bit. writing a one to this location initiate s an ical. the calibra- tion is complete once the lol alarm goes low. a valid stable clock (within 100 ppm) must be present to begin ical. note: any divider, clkinn_rate or bwsel _reg changes require an ical to take effect. 0: normal operation. 1: writing a "1" initiates intern al self-calibration. upon comp letion of internal self-cali- bration, lol will go low. 5:0 reserved reserved.
si5324 preliminary rev. 0.3 49 reset value = 0000 0000 reset value = 0000 1111 register 137. bitd7d6d5d4d3d2d1d0 name reserved fastlock type rr/w bit name function 7:1 reserved do not modify. 0 fastlock this bit must be set to 1 to enable fastlock. this improves initial lock time by dynamically changing the loop bandwidth. register 138. bitd7d6d5d4d3d2 d1 d0 name reserved los2_en [1 :1] los1_en [1:1] type rr/wr/w bit name function 7:2 reserved reserved. 1 los2_en [1:0] enable ckin2 los monitoring on the specified input (2 of 2). note: los2_en is split betw een two registers. 00: disable los monitoring. 01: reserved. 10: enable losa monitoring. 11: enable los monitoring. losa is a slower and less sensitive versio n of los. see the family reference manual for details. 0 los1_en [1:0] enable ckin1 los monitoring on the specified input (1 of 2). note: los1_en is split betw een two registers. 00: disable los monitoring. 01: reserved. 10: enable losa monitoring. 11: enable los monitoring. losa is a slower and less sensitive versio n of los. see the family reference manual for details.
si5324 50 preliminary rev. 0.3 reset value = 1111 1111 register 139. bitd7d6d5 d4 d3d2d1d0 name reserved los2_en [0:0] los1_en [0:0] reserved fos2_en fos1_en type r r/w r/w r r/w r/w bit name function 7:6, 3:2 reserved reserved. 5 los2_en [1:0] enable ckin2 los monitoring on the specified input (2 of 2). note: los2_en is split between two registers. 00: disable los monitoring. 01: reserved. 10: enable losa monitoring. 11: enable los monitoring. losa is a slower and less sensitive versio n of los. see the family reference manual for details. 4 los_en [1:0] enable ckin1 los monitoring on the specified input (1 of 2). note: los1_en is split between two registers. 00: disable los monitoring. 01: reserved. 10: enable losa monitoring. 11: enable los monitoring. losa is a slower and less sensitive version of los. see the family reference manual for details. 1fos2_en enables fos on a per channel basis. 0: disable fos monitoring. 1: enable fos monitoring. 0fos1_en enables fos on a per channel basis. 0: disable fos monitoring. 1: enable fos monitoring.
si5324 preliminary rev. 0.3 51 reset value = 0000 0000 reset value = 0000 0000 reset value = 0001 0011 register 142. bitd7d6d5d4d3d2d1d0 name independentskew1 [7:0] type r/w bit name function 7:0 independentskew1 [7:0] independentskew1. 8 bit field that represents a twos complement of the phase offset in terms of clocks from the high speed output divider. default = 0. register 143. bitd7d6d5d4d3d2d1d0 name independentskew2 [7:0] type r/w bit name function 7:0 independentskew2 [7:0] independentskew2. 8 bit field that represents a twos comp lement of the phase offset in terms of clocks from the high speed output divider. default = 0. register 185. bitd7d6d5d4d3d2d1d0 name nvm_revid [7:0] type r bit name function 7:0 nvm_revid [7:0] nvm_revid.
si5324 52 preliminary rev. 0.3 6.1. ical the device's registers must be configured for the intended applications. after the part is configured, the part must perform a calibration procedure when there is a stable cl ock on the selected clkinn input. the calibration process is triggered by writing a "1" to bit d6 in register 136. se e the family reference manual for details. in addition, after a successful calibration operation, changing any of the regi sters indicated in table 4 requires that a calibration be performed again by the same procedure (writing a "1" to bit d6 in register 136). table 4. ical-sensitive registers address register 0 bypass_reg 0 ckout_always_on 1 ck_prior1 1 ck_prior2 2 bwsel_reg 4hist_del 5icmos 7fosrefsel 9hist_avg 10 dsbl1_reg 10 dsbl2_reg 11 pd_ck1 11 pd_ck2 19 fos_en 19 fos_thr 19 lockt 19 valtime 25 n1hs 31 nc1_ls 34 nc2_ls 40 n2_hs 40 n2_ls 43 n31 46 n32 55 clkin1rate 55 clkin2rate
si5324 preliminary rev. 0.3 53 7. ordering guide ordering part number output clock frequency range package rohs6, pb-free temperature range si5324a-c-gm 2 khz?945 mhz 970?1134 mhz 1.213?1.417 ghz 36-lead 6 x 6 mm qfn yes ?40 to 85 c si5324b-c-gm 2 khz?808 mhz 36-lead 6 x 6 mm qfn yes ?40 to 85 c si5324c-c-gm 2 khz?346 mhz 36-lead 6 x 6 mm qfn yes ?40 to 85 c si5324d-c-gm 2 khz?150 mhz 36-lead 6 x 6 mm qfn yes ?40 to 85 c note: add an r at the end of the device to denote tape and reel options.
si5324 54 preliminary rev. 0.3 table 5. product selection guide device clock inputs clock outputs ? p control max input freq (mhz) 1 max output frequency (mhz) jitter generation (12 khz ? 20 mhz) hitless switching los alarm lol alarm fos alarm fsync realignment any-frequency precision clock multipliers (wideband. bandwidth: 30 khz to 13 mhz)) si5322 2 2 707 1050 0.6 ps rms typ ? si5325 2 2 ? 710 1400 0.6 ps rms typ ?? si5365 4 5 707 1050 0.6 ps rms typ ?? si5367 4 5 ? 710 1400 0.6 ps rms typ ?? any-frequency precision clock multipliers w/jitter attenuation 2 (narrowband. bandwidth: 60 hz to 8.4 khz) si5315 2 2 2 644 644 0.6 ps rms typ ??? si5316 3 2 1 707 710 0.3 ps rms typ ?? si5317 3 1 2 710 710 0.3 ps rms typ ?? si5319 3 11 ? 710 1400 0.3 ps rms typ ?? si5323 3 2 2 707 1050 0.3 ps rms typ ??? si5326 3 22 ? 710 1400 0.3 ps rms typ ???? si5366 3 4 5 707 1050 0.3 ps rms typ ????? si5368 3 45 ? 710 1400 0.3 ps rms typ ????? any-frequency precision clock jitter at tenuation (low bandwidth: 4 to 525 hz) si5324 2 2 ? 710 1400 0.29 ps rms typ ???? notes: 1. maximum input and output rates may be limited by sp eed rating of device. see each device?s data sheet for ordering information. 2. requires external low-cost, fixed frequency fundamental mode 40 mhz crystal or reference clock. 3. requires external low-cost, fixed frequency 3rd overt one 114.285 mhz crystal or reference clock. see the family reference manual for more details.
si5324 preliminary rev. 0.3 55 8. package outline: 36-pin qfn figure 7 illustrates the package details for the si5324. table 6 lis ts the values for the di mensions shown in the illustration. figure 7. 36-pin quad flat no-lead (qfn) table 6. package dimensions symbol millimeters symbol millimeters min nom max min nom max a 0.80 0.85 0.90 l 0.50 0.60 0.70 a1 0.00 0.02 0.05 ? ??12o b 0.18 0.25 0.30 aaa ? ? 0.10 d 6.00 bsc bbb ? ? 0.10 d2 3.95 4.10 4.25 ccc ? ? 0.08 e 0.50 bsc ddd ? ? 0.10 e 6.00 bsc eee ? ? 0.05 e2 3.95 4.10 4.25 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jede c outline mo-220, variation vjjd. 4. recommended card reflow profile is per the je dec/ipc j-std-020 specif ication for small body components.
si5324 56 preliminary rev. 0.3 9. recommended pcb layout figure 8. pcb land pattern diagram figure 9. ground pad recommended layout
si5324 preliminary rev. 0.3 57 table 7. pcb land pattern dimensions dimension min max e 0.50 bsc. e5.42 ref. d5.42 ref. e2 4.00 4.20 d2 4.00 4.20 ge 4.53 ? gd 4.53 ? x ? 0.28 y0.89 ref. ze ? 6.31 zd ? 6.31 notes (general): 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximum ma terial condition (mmc ). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. notes (solder mask design): 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes (stenc il design): 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. notes (card assembly): 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-02 0 specification for small body components.
si5324 58 preliminary rev. 0.3 10. si5324 device top mark mark method: laser font size: 0.80 mm right-justified line 1 marking: si5324q customer part number q = speed code: a, b, c, d see ordering guide for options. line 2 marking: c-gm c = product revision g = temperature range ?40 to 85 c (rohs6) m = qfn package line 3 marking: yywwrf yy = year ww = work week r = die revision f = internal code assigned by the assembly hous e. corresponds to the year and work week of the mold date. line 4 marking: pin 1 identifier circle = 0.75 mm diameter lower-left justified xxxx internal code
si5324 59 preliminary rev. 0.3 d ocument c hange l ist revision 0.1 to revision 0.2 ? updated rise/fall time values. ? updated minimum loop bw value. revision 0.2 to revision 0.25 ? updated features and applications. ? changed maximum loop bandwidth to 525 hz (global). ? updated pll performance specifications in table 1. ? added typical video phase noise plot and data. ? removed references to si5325. ? added note to register ckout_always_on on how to control output to output skew. ? added product selection guide to section ?7. ordering guide?. ? corrected typographical errors in table 1. ? updated typical phase noise performance page. ? updated functional description. ? added additional phase noise plots to section ?2. typical phase noise performance?. ? updated register map. ? revised device top mark. revision 0.25 to revision 0.3 ? changed any-rate to any-frequency ? changed table 2, ?absolute maximum ratings,? on page 6 ? added table 3, ?ckout_always_on and sq_ical truth table,? on page 18 ? added ?no bypass with cmos outputs?
si5324 60 preliminary rev. 0.3 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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