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summit microelectronics, inc. ? 300 orchard city drive, suite 131 campbell, ca 95008 telephone 408-378- 6461 fax 408-378-6586 www.summitmicro.com 1 characteristics subject to change without notice ? summit microelectronics, inc. 2000 2014 2.1 8/2/00 summit microelectronics , inc. s24163 features ? precision supply voltage monitor ? active low ? integrated memory write lockout guaranteed reset (reset#) assertion to v cc = 1v power-fail accuracy guaranteed no external components 3v and 5v system versions low power cmos ? active current less than 3ma ? standby current less than 25a memory internally organized 2k x 8 ? two wire serial interface (i 2 c?) ? bidirectional data transfer protocol ? standard 100khz and fast 400khz precision reset controller with 16k i 2 c memory high reliability ? endurance: 100,000 erase/write cycles ? data retention: 100 years 8-pin soic packages overview the s24163 is a power supervisory device with 16,384- bits of serial e 2 prom. it is fabricated using summit's advanced cmos e 2 prom technology and is suitable for both 3 and 5 volt systems. the s24163 is internally organized as 2048 x 8. it fea- tures the i 2 c serial interface and software protocol allow- ing operation on a simple two-wire bus. block diagram 3 and 5 volt systems + ? gnd v cc reset# v trip reset pulse generator 5khz oscillator reset control mode decode address decoder write control data i/o e 2 prom memory array 1.26v scl 6 sda 5 2 8 2014 t bd 2.0 4
2 s24163 2014 2.1 8/2/00 endurance and data retention the s24163 is designed for applications requiring up to 100,000 erase/write cycles and unlimited read cycles. it provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 erase/write cycles. applications the s24163 is ideal for applications requiring low voltage and low power consumption. this device provides microcontroller reset control and can be manually resettable. this device also uses a cost effective, space- saving, 8-pin soic or pdip plastic package. typical applications include alarm devices, electronic locks, meters, keys, pagers and cellular phones. reset controller description the device provides a precise reset output to a microcontroller and it ? s associated circuitry ensuring cor- rect system operation during power-up/down conditions and brownout situations. the output is open drain, allow- ing control of the reset function by multiple devices. during power-up the reset output remains in a fixed active state until v cc passes through the reset threshold and remains above the threshold for 200ms. the reset output is valid whenever v cc
s24163 3 2014 2.1 8/2/00 figure 1. typical system configuration figure 3. start and stop conditions figure 2. input data protocol data must remain stable while clock is high. data must remain stable while clock is high. change of data allowed scl sda in t hd:dat t su:dat t hd:dat 2014 ill4 1.0 scl sda in start condition stop condition 2014 ill5 1.0 sda scl (c/ p) (24163) 2014 t fig01 2.0 reset v cc master transmitter slave transmitter/ receiver master transmitter/ receiver slave receiver master transmitter/ receiver
4 s24163 2014 2.1 8/2/00 figure 4. acknowledge response from receiver input data protocol one data bit is transferred during each clock pulse. the data on the sda line must remain stable during clock high time, because changes on the data line while scl is high will be interpreted as start or stop condition (see figure 2). start and stop conditions when both the data and clock lines are high, the bus is said to be not busy. a high-to-low transition on the data line, while the clock is high, is defined as the ? start ? condition. a low-to-high transition on the data line, while the clock is high, is defined as the ? stop ? condition (see figure 3). device operation the s24163 is a 16,384-bit serial e 2 prom. the device supports the i 2 c bidirectional data transmission protocol. the protocol defines any device that sends data onto the bus as a ? transmitter ? and any device which receives data as a ? receiver. ? the device controlling data transmission is called the ? master ? and the controlled device is called the ? slave. ? since it never initiates any data transfers the s24163 is always a ? slave ? device. acknowledge (ack) acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either the master or the slave, will release the bus after transmit- ting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (see figure 4). the s24163 will respond with an acknowledge after recognition of a start condition and its slave address byte. if both the device and a write operation are selected, the s24163 will respond with an acknowledge after the receipt of each subsequent 8-bit word. figure 5. slave address byte in the read mode the s24163 transmits eight bits of data, then releases the sda line, and monitors the line for an acknowledge signal. if an acknowledge is detected, and no stop condition is generated by the master, the s24163 will continue to transmit data. if an acknowledge is not detected the s24163 will terminate further data transmis- sions and await a stop condition before returning to the standby power mode. device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are the device type identifier (see figure 5). for the s24163 this is fixed as 1010[b hex ]. word address the next three bits of the slave address are an extension of the array ? s address and are concatenated with the eight bits of address in the word address field, providing direct access to the 2,048 x 8 array. read/write bit the last bit of the data stream defines the operation to be performed. when set to ? 1 ? a read operation is selected; when set to ? 0 ? a write operation is selected. scl from master data output from transmitter data output from receiver start condition acknowledge t aa t aa 1 8 9 2014 ill6 1.0 1 0 1 0 a10 a9 a8 r/w device identifier high order word address 2014 ill7 1.0
s24163 5 2014 2.1 8/2/00 figure 6. page/byte write mode write operations the s24163 allows two types of write operations: byte write and page write. the byte write operation writes a single byte during the nonvolatile write period (t wr ). the page write operation allows up to 16 bytes in the same page to be written during t wr . byte write after the slave address is sent (to identify the slave device, specify high order word address and a read or write operation), a second byte is transmitted which contains the low 8 bit addresses of any one of the 2,048 words in the array. upon receipt of the word address, the s24163 responds with an acknowledge. after receiving the next byte of data, it again responds with an acknowledge. the master then terminates the transfer by generating a stop condi- tion, at which time the s24163 begins the internal write cycle. while the internal write cycle is in progress, the s24163 inputs are disabled, and the device will not respond to any requests from the master. refer to figure 6 for the address, acknowledge and data transfer sequence. page write the s24163 is capable of a 16-byte page write operation. it is initiated in the same manner as the byte-write operation, but instead of terminating the write cycle after the first data word, the master can transmit up to 15 more words of data. after the receipt of each word, the s24163 will respond with an acknowledge. the s24163 automatically increments the address for subsequent data words. after the receipt of each word, the four low order address bits are internally incremented by one. the high order five bits of the address byte remain constant. should the master transmit more than sixteen words, prior to generating the stop condition, the ad- dress counter will ? roll over, ? and the previously written data will be overwritten. as with the byte-write operation, all inputs are disabled during the internal write cycle. refer to figure 6 for the address, acknowledge and data transfer sequence. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 d 7 d 5 d 6 d 4 d 0 d 3 d 2 d 1 s t a r t word address data byte n data byte n+15 s t o p a c k acknowledges transmitted from 24163 to master receiver slave address device type address read/write 0= write a10,a9,a8 sda bus activity a c k a c k master sends read request to slave master writes word address to slave 1 0 1 0 0 data byte n+1 a c k master writes data to slave master transmitter to slave receiver slave transmitter to master receiver slave transmitter to master receiver master transmitter to slave receiver master transmitter to slave receiver shading denotes 24163 sda output active master transmitter to slave receiver slave transmitter to master receiver slave transmitter to master receiver master transmitter to slave receiver slave transmitter to master receiver master writes data to slave master writes data to slave acknowledges transmitted from 24163 to master receiver if single byte-write only, stop bit issued here. a 10 a 9 r w a c k a 8 2014 t fig06 2.0
6 s24163 2014 2.1 8/2/00 figure 8. current address byte read mode figure 7. acknowledge polling acknowledge polling when the s24163 is performing an internal write opera- tion, it will ignore any new start conditions. since the device will only return an acknowledge after it accepts the start, the part can be continuously queried until an acknowledge is issued, indicating that the internal write cycle is complete. to poll the device, give it a start condition, followed by a slave address for a write operation (see figure 7). read operations read operations are initiated with the r/w bit of the identification field set to ? 1. ? there are four different read options: 1. current address byte read 2. random address byte read 3. current address sequential read 4. random address sequential read current address byte read the s24163 contains an internal address counter which maintains the address of the last word accessed, incre- mented by one. if the last address accessed (either a read or write) was to address location n, the next read operation would access data from address location n+1 and incre- ment the current address pointer. when the s24163 receives the slave address field with the r/w bit set to ? 1, ? it issues an acknowledge and transmits the 8-bit word stored at address location n+1. the current address byte read operation only accesses a single byte of data. the master does not acknowledge the transfer, but does generate a stop condition. at this point, the s24163 discontinues data transmission. see figure 8 for the address acknowledge and data transfer sequence. issue start internal write cycle in progress; begin ack polling issue slave address and r/w = 0 ack returned? next operation a write? issue byte address proceed with write issue stop await next command issue stop no no yes (internal write cycle is completed) yes 2014 ill 9 1.0 s t a r t s t o p slave address device type address read/write 1= read a10,a9,a8 sda bus activity d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 master sends read request to slave slave sends data to master master transmitter to slave receiver slave transmitter to master receiver 1 1 1 00 1 lack of ack (low) from master determines last data byte to be read 1 shading denotes 24163 sda output active a 9 a 10 r w a c k a 8 data byte 2014 t fig08 2.0
s24163 7 2014 2.1 8/2/00 figure 9. random address byte read mode random address byte read random address read operations allow the master to access any memory location in a random fashion. this operation involves a two-step process. first, the master issues a write command which includes the start condi- tion and the slave address field (with the r/w bit set to write) followed by the address of the word it is to read. this procedure sets the internal address counter of the s24163 to the desired address. after the word address acknowledge is received by the master, the master immediately reissues a start condition followed by another slave address field with the r/w bit set to read. the s24163 will respond with an acknowl- edge and then transmit the 8-data bits stored at the addressed location. at this point, the master does not acknowledge the transmission but does generate the stop condition. the s24163 discontinues data transmission and reverts to its standby power mode. see figure 9 for the address, acknowledge and data transfer sequence. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 s t a r t word address s t o p a c k slave address slave address device type address read/write 0= write device type address a10,a9,a8 a10,a9,a8 sda bus activity s t a r t read/write 1= read a c k a c k master sends read request to slave master writes word address to slave master requests data from slave slave sends data to master 1010 1010 1 0 a 10 a 9 r w a 8 a 9 r w a 10 a 8 lack of ack (low) from master determines last data byte to be read 1 slave transmitter to master receiver slave transmitter to master receiver shading denotes 24163 sda output active slave transmitter to master receiver master transmitter to slave receiver master transmitter to slave receiver master transmitter to slave receiver slave transmitter to master receiver data byte 2014 t fig09 2.0
8 s24163 2014 2.1 8/2/00 sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted as with the other byte read modes (current address byte read or random address byte read); however, the master now responds with an acknowledge, indicating that it requires additional data from the s24163. the s24163 continues to output data for each acknowledge received. the master terminates the se- quential read operation by not responding with an acknowledge, and issues a stop conditions. during a sequential read operation, the internal address counter is automatically incremented with each acknowl- edge signal. for read operations, all address bits are incremented, allowing the entire array to be read using a single read command. after a count of the last memory address, the address counter will ? roll-over ? and the memory will continue to output data. see figure 10 for the address, acknowledge and data transfer sequence. figure 10. sequential read operation (starting with a random address read) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 shading denotes 24163 sda output active s t a r t word address s t o p a c k acknowledges from 24163 slave address slave address device type address read/write 0= write device type address a10,a9,a8 a10,a9,a80 sda bus activity s t a r t read/write 1= read a 9 r w a 10 acknowledge from master receiver a c k a c k a c k master sends read request to slave master writes word address to slave master requests data from slave slave sends data to master slave transmitter to master receiver slave transmitter to master receiver master transmitter to slave receiver 1010 1010 1 0 slave sends data to master a 10 a 9 r w a 8 a 8 lack of ack (low) determines last data byte to be read 1 lack of acknowledge from master receiver slave transmitter to master receiver master transmitter to slave receiver master transmitter to slave receiver master transmitter to slave receiver slave transmitter to master receiver slave transmitter to master receiver last data byte first data byte 2014 t fig10 2.0
s24163 9 2014 2.1 8/2/00 absolute maximum ratings temperature under bias ......................................................................................................... ...... -40 c to +85 c storage temperature ............................................................................................................ ......... -65 c to +125 c soldering temperature (less than 10 seconds) ................................................................................... ........... 300 c supply voltage ................................................................................................................. .......................... 0 to 6.5v voltage on any pin ............................................................................................................. ......... -0.3v to v cc +0.3v esd voltage (jedec method) ..................................................................................................... ................. 2,000v note: these are stress ratings only. appropriate conditions for operating these devices are given elsewhere in this specificati on. stresses beyond those listed here may permanently damage the part. prolonged exposure to maximum ratings may affect device reliability. dc electrical characteristics s24163, t a = -40 c to +85 c, v cc = 5v + 10% s24163-3, t a = -40 c to +85 c, v cc = 2.7v to 5.5v symbol parameter conditions min max units scl = cmos levels @ 100khz v cc =5.5v 3 ma i cc supply current (cmos) sda = open all other inputs = gnd or v cc v cc =3.3v 2 ma i sb standby current (cmos) scl = sda = v cc v cc =5.5v 50 a all other inputs = gnd i li input leakage v in = 0 to v cc 10 a i lo output leakage v out = 0 to v cc 10 a v il input low voltage s0, s1, s2, scl, sda, reset 0.3xv cc v v ih input high voltage s0, s1, s2, scl, sda 0.7xv cc v v ol output low voltage i ol = 3ma 0.4 v v cc =3.3v 25 a 2014 pgm t1 1.0 2.7v to 4.5v 4.5v to 5.5v symbol parameter conditions min max min max units f scl scl clock frequency 0 100 400 khz t low clock low period 4.7 1.3 s t high clock high period 4.0 0.6 s t buf bus free time before new transmission 4.7 1.3 s t su:sta start condition setup time 4.7 0.6 s t hd:sta start condition hold time 4.0 0.6 s t su:sto stop condition setup time 4.7 0.6 s t aa clock to output scl low to sda data out valid 0.3 3.5 0.2 0.9 s t dh data out hold time scl low to sda data out change 0.3 0.2 s t r scl and sda rise time 1000 300 ns t f scl and sda fall time 300 300 ns t su:dat data in setup time 250 100 ns t hd:dat data in hold time 0 0 ns t i noise spike width noise suppression time constant 100 100 ns @ scl, sda inputs t wr write cycle time 10 10 ms ac electrical characteristics s24163, t a = -40 c to +85 c, v cc = 5v + 10% s24163-3, t a = -40 c to +85 c, v cc = 2.7v to 5.5v 2014 pgm t2 1.0
10 s24163 2014 2.1 8/2/00 figure 11. bus timing capacitance t a = 25 c, f = 100khz symbol parameter max units c in input capacitance 5 pf c out output capacitance 8 pf 2014 pgm t3 1.0 s24163-2.7 s24163 ? a s24163 ? b symbol parameter min max min max min max unit v trip reset trip point 2.55 2.7 4.25 4.5 4.5 4.75 v t purst power-up reset timeout 130 270 130 270 130 270 ms t rpd v trip to reset output delay 5 5 5 s v rvalid reset output valid 1 1 1 v t glitch glitch reject pulse width 30 30 30 ns v olrs reset output low voltage i ol ? 1ma 0.4 0.4 0.4 v reset circuit ac and dc electrical characteristics t a = -40 c to +85 c 2014 pgm t4 1.1 scl sda in sda out t aa t r t h igh t low t su:sto t buf t su:dat t hd:dat t hd:sda t su:sda t dh 2014 ill 13 1.0 t f
s24163 11 2014 2.1 8/2/00 .228 (5.80) .244 (6.20) .016 (.40) .035 (.90) .020 (.50) .010 (.25) x45
1 2 s2416 3 2014 2.1 8/2/00 notic e summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parame t ers , and may vary depending upon a u s e r s s pe c i f i c applica t ion . w hile t he in f orma t ion in t hi s publica t ion ha s bee n carefully checked, summit microelectronics, inc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to s igni f i c an t l y a ff e ct t hei r s a f e ty o r e ff e ct i v ene ss. pr odu cts a r e no t au t ho r i z ed f o r u s e in s u c h appli c a t ion s unle ss s u mmi t microelectronics, inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. ? copyright 2000 summit microelectronics, inc. i 2 c is a trademark of philips corporation. ordering information operating v olt a g e ran g e a = 4.5v to 5.5v v trip min . @ 4.25v b = 4.5v to 5.5v v trip min . @ 4.50v 2.7 = 2.7v to 5.5v v trip min . @ 2.55v t ape & reel option blank = t ube t = t ape & reel s24163 sa t base p a r t number p a c k a g e s = 8 lead 150mil soic 2014 t ree 2.0

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