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re v .1.0 cmos 16-bit single chip micr ocontr oller s1c17651 t ec hnical man ual
? seiko epson corporation 2011, all rights reserved. no tice no part of this material may be reproduced or duplicated in an y form or by an y means without the written permission of seik o epson. seik o epson reserv es the right to mak e changes to this material without notice. seik o epson does not assume an y liability of an y kind arising out of an y inaccuracies contained in this material or due to its application or use in an y product or circuit and, furth er , there is no representation that this material is applicable to products requiring high le v el reliability , such as medical prod- ucts. moreo v er , no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or w arranty that an ything made in accordance with this material will be free from an y patent or cop yright infringement of a third party . this material or portions thereof may contain technology or the subject relating to strate gic products under the control of the f oreign exchange and f oreign t rade la w of japan and may require an e xport license from the ministry of economy , t rade and industry or other appro v al from another go v ernment agenc y . all brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies.
devices s1 c 17xxx f 00e1 packing specifications 00 : besides tape & reel 0a : tcp bl 2 directions 0b : t ape & reel ba ck 0c : tcp br 2 directions 0d : tcp bt 2 directions 0e : tcp bd 2 directions 0f : t ape & reel fr ont 0g : tcp bt 4 directions 0h : tcp bd 4 directions 0j : tcp sl 2 directions 0k : tcp sr 2 directions 0l : t ape & reel left 0m : tcp st 2 directions 0n : tcp sd 2 directions 0p : tcp st 4 directions 0q : tcp sd 4 directions 0r : t ape & reel right 99 : specs not fix ed specification package d: die form; f: qfp, b: bga model number model name c: microcomputer, digital products product classification s1: semiconductor development tools s5u1 c 17000 h2 1 packing specifications 00: standard packing version 1: version 1 tool type hx : ice dx : evaluation board ex : rom emulation board mx : emulation memory for external rom tx : a socket for mounting cx : compiler package sx : middleware package yx : writer software corresponding model number 17xxx: for s1c17xxx tool classification c: microcomputer use product classification s5u1: development tool for semiconductor products 00 00 configuration of product number
contents s1c17651 technical manual seiko epson corporation i C contents C 1 over vie w ........................................................................................................................ 1-1 1.1 f eatures ........................................................................................................................... 1-1 1.2 bloc k diag r am ........................................................................................... ....................... 1-2 1.3 pins .................................................................................................................................. 1-3 1.3.1 pin configur ation diag r am ................................................................................. 1-3 1.3.2 pin descr iptions .......................................................................................... ....... 1-5 2 cpu ................................................................................................................................ 2-1 2.1 f eatures of the s1c17 core ............................................................................................ 2-1 2.2 cpu registers .......................................................................................................... ....... 2-2 2.3 instr uction set .................................................................................................................. 2-2 2.4 reading psr ................................................................................................................... 2-5 2.5 processor inf or mation .......................................................................................... ............ 2-6 3 memor y map, bus contr ol ........................................................................................... 3-1 3.1 bus cycle ......................................................................................................................... 3-1 3.1.1 restr ictions on access siz e ............................................................................... 3-2 3.1.2 re str ictions on instr uction ex ecution cycles ..................................................... 3-2 3.2 flash area ........................................................................................................................ 3-2 3.2.1 embedded flash memor y .................................................................................. 3-2 3.2.2 flash prog r amming ...................... ..................................................................... 3-2 3.2.3 protect bits ........................................................................................................ 3-2 3.2.4 flash memor y read w ait cycle setting ........................................................... 3-3 flashc read w ait control register (flashc_w ait) .............................................. ............. 3-3 3.3 inter nal ram area ............................................................................................................ 3-3 3.3.1 embedded ram ................................................................................................ 3-3 iram siz e register (misc_iramsz) ....................................................................................... 3-4 3.4 disp la y ram area ............................................................................................................ 3-4 3.5 inter nal p er ipher al area ................................................................................................... 3-4 3.5.1 inter nal p er ipher al area 1 (0x4000C) ................................................................. 3-4 3.5.2 inter nal p er ipher al area 2 (0x5000C) ................................................................. 3-5 3.6 s1c17 core i/o area ....................................................................................................... 3-5 4 p o wer suppl y ................................................................................................................ 4-1 4.1 p o w er supply v oltage (v dd ) .......................... ................................................................... 4-1 4.2 flash prog r amming p o w er supply v oltage (v pp ) ............................................................. 4-1 4.3 inter nal p o w er supply circuit ........................................................................................... 4-1 4.3.1 v d1 and v osc regulators ......................................................... ........................... 4-1 4.3.2 lcd p o w er supply circuit .................................................................................. 4-2 4.3.3 hea vy load protection mode ............................................................................. 4-3 4.4 control register details ................................................................................................... 4-3 lcd boo ster cloc k control register (lcd_bclk) ................................................................... 4-3 lcd v oltage regulator control register (lcd_vreg) ............................................................ 4-4 v d1 control register (vd1_ctl) ............................................................................................... 4-5 5 initial reset ................................ ................................................................................... 5-1 5.1 initial reset sources ........................................................................................................ 5-1 5.1.1 #reset pin ....................................................................................................... 5-1 5.1.2 p0 p or t k e y-entr y reset ........................ ........................................................... 5-1 5.1.3 resetting b y the w atchdog timer ...................................................................... 5-1 5.2 initial reset sequence ..................................................................................................... 5-2 5.3 initial settings after an initial reset ................................................ ................................ 5-2
contents ii seiko epson corporation s1c17651 technical manual 6 interrupt contr oller (itc) ............................................................................................. 6-1 6.1 itc module ov er vie w ....................................................................................................... 6-1 6.2 v ector t ab le ...................................................................................................................... 6-2 v ect or t ab le address lo w/high registers (misc_ttbrl, misc_ttbrh) .............................. 6-3 6.3 control of maskab le interr upts ......................................................................................... 6-3 6.3.1 interr upt control bits in p er ipher al modules ...................................................... 6-3 6.3.2 itc interr upt request processing ............................. ........................................ 6-3 6.3.3 interr upt processing b y the s1c17 core ........................................................... 6-4 6.4 nmi ................................................................................................................................... 6-4 6.5 softw are interr upts ................................................................................. .......................... 6-4 6.6 hal t and sleep mode cancellation .............................................................................. 6-5 6.7 control register details ................................................................................................... 6-5 interr upt le v el setup register x (itc_l vx) ............................................................................. .. 6-5 7 cloc k generator (clg) ................................................................................................. 7-1 7.1 clg module ov er vie w ..................................................................................................... 7-1 7.2 clg input/output pins ..................................................................................................... 7-2 7.3 oscil lators ........................................................................................................................ 7-2 7.3.1 osc3b oscillator ............................................................................................... 7-2 7.3.2 osc3a oscillator ............................................................................................... 7-4 7.3.3 osc1 oscillator ... .............................................................................................. 7-4 7.4 system cloc k switching ................................................................................................... 7-7 7.5 cpu core cloc k (cclk) control ..................................................................................... 7-8 7.6 p er ipher al module cloc k (pclk) control ...... ................................................................... 7-8 7.7 cloc k exter nal output (fout a, foutb) ......................................................................... 7-9 7.8 control register details .................................................................................................. 7-10 cloc k source select register (clg_src) ......................................... ..................................... 7-11 oscillation control register (clg_ctl) .................................................................................. 7-12 fout a control register (clg_fout a) .................................................................................. 7-13 foutb control register (clg_foutb) .............................................................................. ... 7-14 oscillation stabilization w ait control register (clg_w ait) .................................................... 7-15 pclk control register (clg_pclk) ....................................................................................... 7-17 cclk control register (clg_cclk) ....................................................................................... 7-18 8 theoretical regulation (tr) ......................................................................................... 8-1 8.1 tr module ov er vie w ........................................................................................................ 8-1 8.2 tr output pin ................................................................................................................... 8-1 8.3 theoretical regulation control .... ..................................................................................... 8-1 8.3.1 setting regulation v alues .................................................................................. 8-1 8.3.2 ex ecuting theoretical regulation ...................................................................... 8-2 8.3.3 regulated cloc k exter nal monitor ......................................... ............................ 8-2 8.4 control register details ................................................................................................... 8-3 tr control register (tr_ctl) .................................................................................................. 8-3 tr v alue register (tr_v al) ................................................................................ ..................... 8-3 9 real-time cloc k (r tc) ................................................................................................. 9-1 9.1 r tc module ov er vie w ..................................................................................................... 9-1 9.2 r tc counters ........................................................................................................ .......... 9-1 9.3 r tc control ..................................................................................................................... 9-3 9.3.1 oper ating cloc k control ..................................................................................... 9-3 9.3.2 12-hour/24-hour mode selection ....................................................................... 9-3 9.3.3 r tc star t/s top .................................................................................................. 9-3 9.3.4 counter settings ................................................................................................ 9-3 9.3.5 counter read .................................................................................................... 9-4
contents s1c17651 technical manual seiko epson corporation iii 9.4 r tc interr upts .................................................................................................................. 9-5 9.5 control register details ................................................................................................... 9-5 r tc control register (r tc_ctl) ............................................................................................. 9-5 r tc interr upt enab le register (r tc_ien) ................................................................................ 9-6 r tc interr upt flag register (r tc_iflg) .................................................................................. 9-7 r tc min ute/second counter register (r tc_ms) .................................................................... 9-8 r tc hour counter register (r tc_h) ........ ............................................................................... 9-9 10 i/o p or ts (p) ................................................................................................................ 10-1 10.1 p module ov er vie w ....................................................................................................... 10-1 10.2 input/output pin function selection (p or t mux) ........................................................... 10-2 10.3 data input/output .......................................................................................................... 10-2 10.4 pull-up control .............................................................................................................. 10-3 10.5 p or t input interr upt ........................................ ................................................................ 10-3 10.6 p0 p or t chatter ing filter function ................................................................................. 10-4 10.7 p0 p or t k e y-entr y reset .............................................................................................. 10-5 10.8 control register details .............................................. .................................................. 10-5 px p or t input data registers (px_in) ....................................................................................... 10-5 px p or t output data registers (px_out) ................................................................................ 10-6 px p or t output enab le registers (px_oen) ...................................................... ...................... 10-6 px p or t pull-up control registers (px_pu) .............................................................................. 10-6 p0 p or t interr upt mask register (p0_imsk) ............................................................................. 10-7 p0 p or t interr upt edge select register (p0_edge) ................................................................ 10-7 p0 p or t int err upt flag register (p0_iflg) ............................................................................... 10-7 p0 p or t chatter ing filter control register (p0_cha t) ............................................................. 10-8 p0 p or t k e y-entr y reset configur ation register (p0_krst) .................................................. 10-9 px p or t input enab le registers (px_ien) ................. ................................................................ 10-9 p0[3:0] p or t function select register (p00_03pmux) ........................................................... 10-10 p0[7:4] p or t function select register (p04_07pmux) ........................................................... 10-11 p1[3:0] p or t function select register (p10_13pmux) ................................................... ........ 10-12 11 8-bit timer (t8) ........................................................................................................... 11-1 11.1 t8 module ov er vie w ..................................................................................................... 11-1 11.2 count cloc k ........................................................................................................... ........ 11-2 11.3 count mode ................................................................................................................... 11-2 11.4 reload data register and underflo w cycle .................................................................. 11-2 11.5 timer reset ................................................................................................................... 11 -3 11.6 timer r un/st op control ............................................................................................. 11-3 11.7 t8 output signals .......................................................................................................... 11-4 11.8 t8 interr upts .................................................................................................................. 11-4 11.9 control register details ................................................................................................ 11-5 t8 ch.x count cloc k select register (t8_clkx) ..................................................................... 11-5 t8 ch.x reload data register (t8_trx) ................................................................................. 11-5 t8 ch.x counter data regist er (t8_tcx) ................................................................................ 11-6 t8 ch.x control register (t8_ctlx) ........................................................................................ 11-6 t8 ch.x interr upt control register (t8_intx) .......................................................................... 11-7 12 16-bit pwm timer (t16a2) .......................... ............................................................... 12-1 12.1 t16a2 module ov er vie w ............................................................................................... 12-1 12.2 t16a2 input/output pins ............................................................................................... 12-2 12.3 count cloc k ........................................................... ........................................................ 12-2 12.4 t16a2 oper ating modes ............................................................................................... 12-3 12.4.1 compar ator mode and capture mode ............................................................ 12-4 12.4.2 repeat mode and one-shot mode ................................................................. 12-5 1 2.4.3 nor mal cloc k mode and half cloc k mode ...................................................... 12-5
contents iv seiko epson corporation s1c17651 technical manual 12.5 counter control ............................................................................................................ 12-6 12.5.1 counter reset ................................................................................................. 12-6 12.5.2 counter r un/st op control ........................................................................... 12-6 12.5.3 reading counter v alues ................................................................................. 12-6 12.5.4 counter oper ation and interr upt timing char ts .............................................. 12-7 12.6 timer output control ..................................................................................................... 12-7 12.7 t16a2 interr upts ........................................................ .................................................... 12-9 12.8 control register details ............................................................................................... 12-11 t16a cloc k control register ch.x (t16a_clkx) .................................................................... 12-11 t16a counter ch.x control register (t16a_ctlx) ................................................ ................ 12-12 t16a counter ch.x data register (t16a_tcx) ...................................................................... 12-14 t16a compar ator/capture ch.x control register (t16a_ccctlx) ....................................... 12-14 t16a compar ator/capture ch.x a data register (t16a_ccax) ............................................ 12-16 t16a compar ator/capture ch.x b data register (t16a_ ccbx) ............................................ 12-16 t16a compar ator/capture ch.x interr upt enab le register (t16a_ienx) ............................... 12-17 t16a compar ator/capture ch.x interr upt flag register (t16a_iflgx) ................................. 12-18 13 cloc k timer (ct) ........................................................................................................ 13-1 13.1 ct module ov er vie w ..................................................................................................... 13-1 13.2 oper ation cloc k ............................................................................................................. 13-1 13.3 timer reset ................................................................................................................... 13-1 13.4 ti mer r un/st op control ............................................................................................. 13-2 13.5 ct interr upts ................................................................................................................. 13-2 13.6 control register details ................................................................................................ 13-3 cloc k timer co ntrol register (ct_ctl) ................................................................................... 13-3 cloc k timer counter register (ct_cnt) ................................................................................. 13-4 cloc k timer interr upt mask register (ct_imsk) ..................................................................... 13-4 cloc k timer interr upt flag register (ct_iflg) . ....................................................................... 13-4 14 w atc hdog timer (wdt) .............................................................................................. 14-1 14.1 wdt module ov er vie w ................................................................................................. 14-1 14.2 oper ation cloc k ...................................................... ....................................................... 14-1 14.3 wdt control .................................................................................................................. 14-1 14.3.1 nmi/reset mode selection ............................................................................. 14-1 14.3.2 wdt run/stop control .............................................................. ..................... 14-2 14.3.3 wdt reset ..................................................................................................... 14-2 14.3.4 oper ations in hal t and sleep modes ......................................................... 14-2 14.4 control register details ................................................................................................ 14-2 w atchdog timer co ntrol register (wdt_ctl) ........................................................................ 14-2 w atchdog timer status register (wdt_st) ............................................................................ 14-3 15 u ar t ........................................................................................................................... 15-1 15.1 u ar t module ov er vie w ................ ................................................................................ 15-1 15.2 u ar t input/output pins ................................................................................................ 15-2 15.3 baud rate gener ator .................................................................................................... 15-2 15.4 t r ansf er data settings ............................ ....................................................................... 15-4 15.5 data t r ansf er control .................................................................................................... 15-5 15.6 receiv e errors ............................................................................................................... 15-7 15.7 u ar t interr upts .................................... ........................................................................ 15-8 15.8 ird a interf ace ................................................................................................................ 15-9 15.9 control register details ............................................................................................... 15-10 u ar t ch.x status register (u ar t_stx) ................... ............................................................. 15-10 u ar t ch.x t r ansmit data register (u ar t_txdx) ................................................................. 15-12 u ar t ch.x receiv e data register (u ar t_rxdx) ................................................................. 15-12
contents s1c17651 technical manual seiko epson corporation v u ar t ch.x mode register (u ar t_modx) ............................................................................. 15-12 u ar t ch.x control register (u ar t_ctlx) ............................................................................ 15-13 u ar t ch.x expansion register (u ar t_expx) ...................................................................... 15-14 u ar t ch.x baud rate register (u ar t_brx) ...... .................................................................. 15-14 u ar t ch.x fine mode register (u ar t_fmdx) ...................................................................... 15-15 u ar t ch.x cloc k control register (u ar t_clkx) .................................................................. 15-15 16 spi ......................................................................................... ...................................... 16-1 16.1 spi module ov er vie w .................................................................................................... 16-1 16.2 spi input/output pins .................................................................................................... 16-1 16.3 spi cloc k ................................................................................ ...................................... 16-2 16.4 data t r ansf er condition settings ................................................................................... 16-2 16.5 data t r ansf er control .................................................................................................... 16-3 16.6 spi interr upts ............................................................................... ................................. 16-5 16.7 control register details ................................................................................................ 16-6 spi ch.x status register (spi_stx) ........................................................................................ 16-6 spi ch.x t r ansmit data register (spi_txdx) .............................................................. ............ 16-7 spi ch.x receiv e data register (spi_rxdx) .......................................................................... 16-7 spi ch.x control register (spi_ctlx) ..................................................................................... 16-7 17 lcd driver (lcd) ....................................................................................................... 17-1 17.1 lcd m odule ov er vie w .................................................................................................. 17-1 17.2 lcd p o w er supply ........................................................................................................ 17-1 17.3 lcd cloc k ..................................................................................................................... 17-2 17.3.1 lcd ope r ating cloc k (lclk) .......................................................................... 17-2 17.3.2 f r ame signal ................................................................................................... 17-3 17.4 dr iv e duty control ......................................................................................................... 17-3 17.4.1 dr iv e duty switching ............... ........................................................................ 17-3 17.4.2 dr iv e w a v ef or m ............................................................................................... 17-4 17.5 displa y memor y ............................................................................................................ 17-7 17.6 displa y control ............................................... ............................................................... 17-8 17.6.1 displa y on/off ................................................................................................. 17-8 17.6.2 in v er ted displa y .............................................................................................. 17-8 17.7 lcd interr upt .................................................................. ............................................... 17-9 17.8 control register details ................................................................................................ 17-9 lcd timing cloc k select register (lcd_tclk) ...................................................................... 17-9 lcd displa y control register (lcd_dctl) ............................................................ ................ 17-10 lcd cloc k control register (lcd_cctl) .............................................................................. 17-11 lcd v oltage regulator control register (lcd_vreg) .......................................................... 17-12 lcd interr upt mask register (lcd_imsk) ............................................................................. 17-12 lcd interr upt flag regis ter (lcd_iflg) ................................................................................ 17-12 18 sound generator (snd) ............................................................................................ 18-1 18.1 snd module ov er vie w .................................................................................................. 18-1 18.2 snd output pins ............................ ............................................................................... 18-1 18.3 snd oper ating cloc k .................................................................................................... 18-1 18.4 buzz er f requency and v olume settings ........................................................................ 18-2 18.4.1 buzz er f requency ............................................ ............................................... 18-2 18.4.2 v olume le v el .................................................................................................... 18-2 18.5 buzz er mode and output control .................................................................................. 18-3 18.5.1 buzz er mode selection ....................................................................... ............ 18-3 18.5.2 output control in nor mal mode ..................................................................... 18-3 18.5.3 output control in one-shot mode .................................................................. 18-3 18.5.4 output control in en v elope mode ................................................................... 18-4
contents vi seiko epson corporation s1c17651 technical manual 18.6 control register details ............................................................................................... 18-5 snd cloc k control register (snd_clk) ................................................................................. 18-5 snd control register (snd_ctl) ........................................................................................... 18-5 buzz er f requency cont rol register (snd_bzfq) ................................................................... 18-7 buzz er duty ratio control register (snd_bzdt) ................................................................... 18-7 19 suppl y v olta g e detection cir cuit (svd) ................................................................... 19-1 19.1 svd module ov er vie w ................................................ .................................................. 19-1 19.2 compar ison v oltage setting .......................................................................................... 19-1 19.3 svd control .................................................................................................................. 19-2 19.4 control register details .................................................... ............................................ 19-2 svd enab le register (svd_en) .............................................................................................. 19-2 svd compar ison v oltage register (svd_cmp) ...................................................................... 19-3 svd detection result register (svd_rsl t) .................................................................... ....... 19-4 20 on-c hip deb ug g er (dbg) .......................................................................................... 20-1 20.1 resource requirements and deb ugging t ools ............................................................. 20-1 20.2 deb ug break oper ation status ..................................................................................... 20-1 20.3 additional deb ugging func tion ..................................................................................... 20-2 20.4 control register details ................................................................................................ 20-2 deb ug mode control register 1 (misc_dmode1) ................................................................. 20-2 deb ug mode control register 2 (misc_dmode2) .................. ............................................... 20-3 iram siz e select register (misc_iramsz) ........................................................................... 20-3 deb ug ram base register (dbram) ...................................................................................... 20-4 deb ug control register (dcr) ............................................................................... .................. 20-4 instr uction break address register 2 (ibar2) ......................................................................... 20-5 instr uction break address register 3 (ibar3) ......................................................................... 20-5 instr uction break address register 4 (ibar4) ......................................................................... 20-6 21 multipli er/divider (copr o) ....................................................................................... 21-1 21.1 ov er vie w ....................................................................................................................... 21-1 21.2 oper ation mode and output mode ................................................................................ 21-1 21.3 multiplication .......... ....................................................................................................... 21-2 21.4 division .......................................................................................................................... 21-3 21.5 ma c .............................................................................................................................. 21-4 21.6 readin g results ............................................................................................................ 21-6 22 electrical characteristics .......................................................................................... 22-1 22.1 absolute maxim um ratings .......................................................................................... 22-1 22.2 recommended oper ating conditions ........................................................................... 22-1 22.3 current consumption .................................................................................................... 22-2 22.4 oscillation char acter istics ............................................................................................. 22-4 22.5 exter nal cloc k input char acter istics ...... ....................................................................... 22-5 22.6 input/output pin char acter istics ................................................................................... 22-5 22.7 spi char acter istics ........................................................................................................ 22-6 22.8 lcd dr iv er char acter istics ................................ ............................................................ 22-7 22.9 svd circuit char acter istics ........................................................................................... 22-9 22.10 flash memor y char acter istics .................................................................................... 22-10 23 basic external connection dia gram ............................................. ........................... 23-1 24 p ac ka g e/chip ............................................................................................................. 24-1 24.1 tqfp p ac kage .............................................................................................................. 24-1 24.2 chip ............................................................................................... ................................ 24-2 24.2.1 p ad configur ation ........................................................................................... 24-2
contents s1c17651 technical manual seiko epson corporation vii appendix a list of i/o register s ................................................................................ ap-a-1 0x4100C0x4107, 0x506c u ar t (with ird a) ch.0 .................................... ap-a-3 0x4240C0x4248 8-bit timer ch.0 ............................................... ap-a-4 0x4306C0x4314 interr upt controller .......................................... ap-a-4 0x4320C0x4326 spi ch.0 .... ...................................................... ap-a-4 0x5000C0x5003 cloc k timer ..................................................... ap-a-5 0x5040C0x5041 w atchdog timer .............................................. ap-a-5 0x5060C0x5081 cloc k gener ator .............................................. ap-a-5 0x5078C0x5079 theoretical regulation circuit ......................... ap-a-6 0x5070C0x5071, 0 x50a0C0x50a6 lcd dr iv er ...................................................... ap-a-7 0x5100C0x5102 svd circuit ...................................................... ap-a-8 0x5120 p o w er gener ator ............................................. ap-a-8 0x506e , 0x5180C0x5182 sound gener ator ............................................. ap-a-8 0x5200C0x52a2 p p or t & p or t mux ................................... ....... ap-a-9 0x4020, 0x5322C0x532c misc registers .............................................. ap-a-10 0x5068, 0x5400C0x540c 16-bit pwm timer ch.0 .................................. ap-a-11 0x54b0 flash controller .............................................. ap-a-12 0x56c0C0x56c8 real-time cloc k .............................................. ap-a-12 0xffff84C0xffffd0 s1c17 core i/o ................... ........................... ap-a-13 appendix b p o wer sa ving .......................................................................................... ap-b-1 b .1 cloc k control p o w er sa ving ......................................................................................... ap-b-1 b .2 reducing p o w er consumption via p o w er supply control ........................................... ap-b-3 b .3 other p o w er sa ving methods ...................................................................................... ap-b-3 appendix c mounting precautions ............................................................................ ap-c-1 appendix d measures against noise ........................................................................ ap-d-1 appendix e initialization routine .......................... ..................................................... ap-e-1 re vision histor y
1 o ver view s1c17651 t echnical m anual seiko epson corporation 1-1 ov er view 1 features 1.1 the main features of the s1c17651 are listed belo w . 1.1 f eatures t ab le 1. cpu cpu core seik o epson or iginal 16-bit risc cpu core s1c17 multiplier/divider (copr o) ? ? ? embed ded flash memor y capacity 16k b ytes (f or both instr uctions and data) er ase/prog r am count three times other ? ? ? embed ded ram capacity 2k b ytes cloc k g enerator system cloc k source 3 sources (osc3b/osc3a/osc1) osc3b oscillator circuit 2m/1m/500k hz (typ .) inter nal oscillator circuit osc3a oscillator circuit 4.2 mhz (max.) cr ystal or cer amic oscillator circuit osc1b oscillator circuit 32 khz (typ .) inter nal oscillator circuit osc1a oscillator circuit 32.768 khz (typ .) cr ystal oscillator circuit oscillation adjustment b y theoretical regulation other ? ? lcd driver number of dr iv er outputs segment output: 20 pins common output: 4 pins other ? ? i/o por ts number of gener al-pur pose i/o por ts max. 12 bits (pins are shared with the per ipher al i/o .) other ? ? ? serial interfaces spi 1 channel u ar t 1 channel (ird a1.0 suppor ted) timer s/counter s 8-bit timer (t8) 1 channel (gener ates the spi cloc k.) 16-bit pwm timer (t16a2) 1 channel (pwm output, e v ent counter , and count capture functions) w atchdog timer (wdt) 1 channel (gener ates nmi/reset.) cloc k functions real-time cloc k ( r tc) 1 channel (hour , min ute , and second counters) with theoretical regulation suppor t cloc k timer (ct) 1 channel (128 hz to 1 hz counters) with theoretical regulation suppor t theoretical regulation function (tr) time adjustment function in +16/32768 to -15/32768 second units sound g enerator buzz er frequency 8 frequencies selectab le v olume control 8 steps adjustab le other ? ? analog cir cuits supply v oltage detection circuit (svd) 1 channel (detection v oltage: 13 le v els) interrupts reset interr upt #reset pin/w atchdog timer nmi w atchdog timer prog r ammab le interr upts 8 systems (8 le v els)
1 o ver view 1-2 seiko epson corporation s1c17651 t echnical m anual p o wer suppl y v olta g e oper ating v oltage (v dd ) 2.0 v to 3.6 v flash prog r amming/er asing v oltage (v pp ) 7v/7.5v operating temperature oper ating temper ature r ange -40c to 85c current consumption (t yp v alue , v dd = 2.0 v to 3.6 v) sleep state 90 na (osc1 = off , r tc = off , osc3b = off , osc3a = off) hal t state 0.42 a (osc1 = 32 khz (osc1a), r tc = off , osc3b = off , osc3a = off) 0.42 a (osc1 = 32 khz (osc1a), r tc = on, osc3b = off , osc3a = off) run state 10 a (osc1 = 32 khz (osc1a), r tc = off , osc3b = off , osc3a = off) 1200 a (osc1 = off , r tc = off , osc3b = off , osc3a = 4 mhz cer amic) 650 a (osc1 = off , r tc = off , osc3b = 2 mhz, osc3a = off) shipping f orm 1 tqfp13-64pin (12 mm 12 mm 1 mm, lead pitch: 0.5 mm) 2 die bloc k dia gram 1.2 cpu core s1c17 internal ram (2k bytes) 8-bit timer (1 ch.) clock generator (with oscillators) clock timer watchdog timer 16-bit pwm timer (1 ch.) misc register power generator flash memory (16k bytes) 32 bits 16 bits interrupt system 8/16 bits dclk, dst2, dsio v d1 , v osc , v c1C3 , ca, cb, iref_m osc1C2, osc3C4 fouta, foutb excl0, capa0/touta0, capb0/toutb0 p00C07, p10C13 #reset sin0, sout0, sclk0 sdi0, sdo0, spiclk0, #spiss0 reset circuit 8/16 bits i/o 2 (0x5000C) interrupt controller uart (1 ch.) spi (1 ch.) i/o 1 (0x4000C) i/o port/ port mux real-time clock theoretical regulation test0 test circuit sound generator bz, #bz regmon lcd driver supply voltage detection circuit seg0C19, com0C3 lfro 2.1 s1c17651 bloc k diag r am figure 1.
1 o ver view s1c17651 t echnical m anual seiko epson corporation 1-3 pins 1.3 pin configuration dia gram 1.3.1 tqfp13-64pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 n.c. n.c. seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 n.c. n.c. n.c. #reset v dd v ss test0 osc4 osc3 v d1 osc2 osc1 v osc iref_m n.c. n.c. n.c. 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ca cb v c1 v c2 v c3 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 sin0/p00 sout0/p01 sclk0/fouta/regmon/p02 excl0/regmon/lfro/p03 touta0/capa0/p04 toutb0/capb0/#spiss0/p05 bz/sdi0/p06 #bz/sdo0/p07 foutb/spiclk0/p10 p11/bz/dclk p12/#bz/dsio p13/dst2 v dd v ss v pp n.c. 3.1.1 s1c17651 pin configur ation diag r am (tqfp13-64pin) figure 1.
1 o ver view 1-4 seiko epson corporation s1c17651 t echnical m anual chip y x (0, 0) 2.418 mm 2.634 mm die no. cj651dxxx seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 1 2 3 4 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 40 39 38 37 36 35 34 33 32 31 30 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 #reset v dd v ss test0 osc4 osc3 v d1 osc2 osc1 v osc iref_m sin0/p00 sout0/p01 sclk0/fouta/regmon/p02 excl0/regmon/lfro/p03 touta0/capa0/p04 toutb0/capb0/#spiss0/p05 bz/sdi0/p06 #bz/sdo0/p07 foutb/spiclk0/p10 p11/bz/dclk p12/#bz/dsio p13/dst2 v dd v ss v pp ca cb v c1 v c2 v c3 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 3.1.2 s1c17651 p ad configur ation diag r am figure 1.
1 o ver view s1c17651 t echnical m anual seiko epson corporation 1-5 pin descriptions 1.3.2 note: the pin names descr ibed in boldf ace type are def ault settings . 3.2.1 pin descr iptions t ab le 1. pin no. name i/o default status function chip tqfp 20C1 23C17, 15C3 seg0C seg19 o o (hi-z) lcd segment output pins 24C21 27C24 com0C com3 o o (hi-z) lcd common output pins 25 28 v c3 C C lcd system po w er supply circuit output pin 26 29 v c2 C C lcd system po w er supply circuit output pin 27 30 v c1 C C lcd system po w er supply circuit output pin 28 31 cb C C v oltage boost capacitor connecting pin f or lcd system po w er supply circuit 29 32 ca C C v oltage boost capacitor co nnecting pin f or lcd system po w er supply circuit 30 36 iref_m C C iref constant current monitor pin (lea v e the pin open dur ing nor mal oper ation.) 31 37 v osc C C oscillation system v oltage regulator output pin 32 38 osc1 i i osc1a oscillation input pin 33 39 osc2 o o osc1a oscillation output pin 34 40 v d1 C C inter nal logic system v oltage regulator output pin 35 41 osc3 i i osc3a oscillation input pin 36 42 osc4 o o osc3a oscillation output pin 37 43 test0 i i (pull-d o wn) t est input pin (connect to v ss f or nor mal oper ation.) 38 44 v ss C C gnd pin 39 45 v dd C C p o w er supply pin (2.0 to 3.6 v) 40 46 #reset i i (pull-up) initial reset input pin 41 49 p00 i/o i (pull-up) i/o por t pin (with por t input interr upt function) sin0 i u ar t ch.0 data input pin 42 50 p01 i/o i (pull-up) i/o por t pin (with por t input interr upt function) sout0 o u ar t ch.0 data output pin 43 51 p02 i/o i (pull-up) i/o por t pin (with por t input inte rr upt function) sclk0 i u ar t ch.0 e xter nal cloc k input pin fout a o cloc k output pin regmon o theoretical regulation cloc k monitor output pin 44 52 p03 i/o i (pull-up) i/o por t pin (with por t input interr upt function) excl0 i t16a2 ch.0 e xter nal cloc k input pin regmon o theoretical regulation cloc k monitor output pin lfr o o lcd fr ame signal output pin 45 53 p04 i/o i (pull-up) i/o por t pin (with por t input interr upt function) t out a 0 o t16a2 ch.0 t out a signal output pin cap a0 i t16a2 ch.0 capture a tr igger signal input pin 46 54 p05 i/o i (pull-up) i/o por t pin (with por t input interr upt function) t outb0 o t16a2 ch.0 t out b signal output pin capb0 i t16a2 ch.0 capture b tr igger signal input pin #spiss0 i spi ch.0 sla v e select signal input pin 47 55 p06 i/o i (pull-up) i/o por t pin (with por t input interr upt function) bz o buzz er output pin sdi0 i spi ch.0 dat a input pin 48 56 p07 i/o i (pull-up) i/o por t pin (with por t input interr upt function) #bz o buzz er in v er ted output pin sdo0 o spi ch.0 data output pin 49 57 p10 i/o i (pull-up) i/o por t pin foutb o cloc k output pin spiclk0 i/o spi ch.0 cloc k input/output pin 50 58 dclk o o (h) on-chip deb ugger cloc k output pin p11 i/o i/o por t pin bz o buzz er output pin 51 59 dsio i/o i (pull-up) on-chip deb ugger data input/output pin p12 i/o i/o por t pin #bz o buzz er in v er ted output pin 52 60 dst2 o o (l) on-chip deb ugger status output pin p13 i/o i/o por t pin 53 61 v dd C C p o w er supply pin (2.0 to 3.6 v) 54 62 v ss C C gnd pin 55 63 v pp C C flash prog r amming/er asing po w er supply pin (7.0/7.5 v) (lea v e the pin open dur ing nor mal oper ation.)
2 cpu s1c17651 t echnical m anual seiko epson corporation 2-1 cpu 2 the s1c17651 contains the s1c17 core as its core processor . the s1c17 core is a seik o epson original 16-bit risc-type processor . it features lo w po wer consumption, high-speed operation, lar ge address space, main instructions e x ecutable in one clock c ycle, and a small sized design. the s1c17 core is suitable for embedded applications such as controllers and sequencers for which an eight-bit cp u is commonly used. f or details of the s1c17 core, refer to the s1c17 f amily s1c17 core manual. features of the s1c17 core 2.1 pr ocessor type ? seik o epson original 16-bit risc processor ? 0.35C0.15 m lo w po wer cmos process technology instruction set ? code length: 16-bit f ix ed length ? number of instructions: 111 basic instructions (184 including v ariations) ? ex ecution c ycle: main instructions e x ecut ed in one c ycle ? extended immediate instructions: immediate e xtended up to 24 bits ? compact and f ast instruction set optimized for de v elopment in c language register set ? eight 24-bit general-purpose re gisters ? t w o 24-bit special re gisters ? one 8-bit special re gister memor y space and b us ? up to 16m bytes of memory space (24-bit address) ? harv ard architecture using separated instruction b us (16 bits) and data b us (32 bits) interrupts ? reset, nmi, and 32 e xternal interrupts supported ? address misaligned interrupt ? deb ug interrupt ? direct branching from v ector table to interrupt handler routine ? programmable softw are interrupts with a v ector number specif ied (all v ector numbers specif iable) p o wer sa ving ? hal t (halt instruction) ? sleep (slp instruction) copr ocessor interface ? 16-bit 16-bit multiplier ? 16-bit 16-bit di vider ? 16-bit 16-bit + 32-bit multiply and accumulation unit
2 cpu 2-2 seiko epson corporation s1c17651 t echnical m anual cpu register s 2.2 the s1c17 core contains eight general-purpose re gisters and three special re gisters. r4 r5 r6 r7 r3 r2 r1 r0 bit 23 bit 0 general-purpose registers pc bit 23 7 6 5 4 3 2 1 0 bit 0 psr sp special registers il[2:0] 765 ie 4 c 3 v 2 z 1 n 0 2.1 registers figure 2. instruction set 2.3 the s1c17 core instruction codes are all f ix ed to 16 bits in length which, combined with pipelined processing, al- lo ws most important instructions to be e x ecuted in one c ycle. f or details, refer to the s1c17 f amily s1c17 core manual. 3.1 list of s1c17 core instr uctions t ab le 2. classification mnemonic function data tr ansf er ld.b %rd,%rs gener al-pur pose register (b yte) gener al-pur pose register (sign-e xtended) %rd,[%rb] memor y (b yte) gener al-pur pose register (sign-e xtended) memor y address post-increment, post-decrement, and pre-decrement functions can be used. %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] stac k (b yte) gener al-pur pose register (sign-e xtended) %rd,[imm7] memor y (b yte) gener al-pur pose register (sign-e xtended) [ %rb],%rs gener al-pur pose register (b yte) memor y memor y address post-increment, post-decrement, and pre-decrement functions can be used. [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs gener al-pur pose register (b yte) stac k [imm7],%rs gener al-pur pose register (b yte) memor y ld.ub %rd,%rs gener al-pur pose register (b yte) gener al-pur pose register (z ero-e xtended) %rd,[%rb] memor y (b yte) gener al-pur pose register (z ero-e xtended) memor y address post-increment, post-decrement, and pre-decrement functions can be used. %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] stac k (b yte) gener al-pur pose register (z ero-e xtended) %rd,[imm7] memor y (b yte) gener al-pur pose register (z ero-e xtended) ld %rd,%rs gener al-pur pose register (16 bits) gener al-pur pose register %rd,sign7 immediate gener al-pur pose register (sign-e xtended) %rd,[%rb] memor y (16 bits) gener al-pur pose register memor y address post-increment, post-decrement, and pre-decrement functions can be used. %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] stac k (16 bits) gener al-pur pose register %rd,[imm7] memor y (16 bits) gener al-pur pose register [%rb],%rs gener al-pur pose register (16 bits) memor y memor y address post-increment, post-decrement, and pre-decrement functions can be used. [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs gener al-pur pose register (16 bits) stac k [imm7],%rs gener al-pur pose register (16 bits) memor y ld.a %rd,%rs gener al-p ur pose register (24 bits) gener al-pur pose register %rd,imm7 immediate gener al-pur pose register (z ero-e xtended)
2 cpu s1c17651 t echnical m anual seiko epson corporation 2-3 classification mnemonic function data tr ansf er ld.a %rd,[%rb] memor y (32 bits) gener al-pur pose register (*1) memor y address post-increment, post-decrement, and pre-decrement functions can be used. %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] stac k (32 bits) gener al-pur pose register (*1) %rd,[imm7] memor y (32 bits) gener al-pur pose register (*1) [%rb],%rs gener al-pur pose register (32 bits , z ero-e xtended) memor y (*1) memor y address post-increment, post -decrement, and pre-decrement functions can be used. [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs gener al-pur pose register (32 bits , z ero-e xtended) stac k (*1) [imm7],%rs gener al-pur pose register (32 bits , z ero-e xtended) memor y (*1) %rd,%sp sp gener al-pur pose register %rd,%pc pc gener al-pur pose register %rd,[%sp] stac k (32 bits) gener al-pur pose register (*1) stac k pointer post-increment, post-decrement, and pre-decrement functions can be used. %rd,[%sp]+ %rd,[%sp]- %rd,-[%sp] [%sp],%rs gener al-pur pose register (32 bits , z ero-e xtended) stac k (*1) stac k pointer post-increment, post-decrement, and pre-decrement functions can be used. [%sp]+,%rs [%sp]-,%rs -[%sp],%rs %sp,%rs gener al-pur pose register (24 bits) sp %sp,imm7 immediate sp integer ar ithmetic oper ation add %rd,%rs 16-bit addition betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). add/c add/nc add %rd,imm7 16-bit addition of g ener al-pur pose register and immediate add.a %rd,%rs 24-bit addition betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). add.a/c add.a/nc add.a %sp,%rs 24-bit addition of sp and gener al-pur pose register %rd,imm7 24-bit addition of gener al-pur pose register and immediate %sp,imm7 24-bit addition of sp and immediate adc %rd,%rs 16-bit addition with carr y betw een gener al-pur pose registers suppor ts condit ional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). adc/c adc/nc adc %rd,imm7 16-bit addition of gener al-pur pose register and immediate with carr y sub %rd,%rs 16-bit subtr action betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). sub/c sub/nc sub %rd,imm7 16-bit subtr action of gener al-pur pose register and immediate sub.a %rd,%rs 24-bit subtr action betw een gener al-pur pose registers supp or ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). sub.a/c sub.a/nc sub.a %sp,%rs 24-bit subtr action of sp and gener al-pur pose register %rd,imm7 24-bit subtr action of gener al-pur pose register and immediate %sp,imm7 24-bit subtr action of sp and immediate sbc %rd,%rs 16-bit subtr action with carr y betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). sbc/c sbc/nc sbc %rd,imm7 16-bit subtr action of gener al-pur pose register and immediate with carr y cmp %rd,%rs 16-bit compar ison betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). cmp/c cmp/nc cmp %rd,sign7 16-bit compar ison of gener al-pur pose register and immediate cmp.a %rd,%rs 24-bit compar ison betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). cmp.a/c cmp.a/nc cmp.a %rd,imm7 2 4-bit compar ison of gener al-pur pose register and immediate cmc %rd,%rs 16-bit compar ison with carr y betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). cmc/c cmc/nc cmc %rd,sign7 16-bit compar ison of gener al-pur pose register and immediate with carr y
2 cpu 2-4 seiko epson corporation s1c17651 t echnical m anual classification mnemonic function logical oper ation and %rd,%rs logical and betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). and/c and/nc and %rd,sign7 logical and of gener al-pur pose register and immediate or %rd,%rs logical or betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). or/c or/nc or %rd,sign7 logical or of gener al-pur pose r egister and immediate xor %rd,%rs exclusiv e or betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). xor/c xor/nc xor %rd,sign7 exclusiv e or of gener al-pur pose register and immediate not %rd,%rs logical in v ersion betw een gener al-pur pose registers (1's complement) suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). not/c not/nc not %rd,sign7 logical in v ersion of gener al-pur pose register and immediate (1's complement) shift and s w ap sr %rd,%rs logical shift to the r ight with the n umber of bits speci?ed b y the register %rd,imm7 logical shift to the r ight with the n umber of bits speci?ed b y immediate sa %rd,%rs ar ithmetic shift to the r ight with the n umber of bits speci?ed b y the register %rd,imm7 ar ithmetic shift to the r ight with the n umber of bits speci?ed b y immediate sl %rd,%rs logical shift to the lef t with the n umber of bits speci?ed b y the register %rd,imm7 logical shift to the left with the n umber of bits speci?ed b y immediate swap %rd,%rs byte wise s w ap on b yte boundar y in 16 bits i m m e d i a t e e x t e n s i o n ext imm13 extend oper and in the f ollo wing instr uction con v ersion cv.ab %rd,%rs con v er ts signed 8-bit data into 24 bits cv.as %rd,%rs con v er ts signed 16-bit data into 24 bits cv.al %rd,%rs con v er ts 32-bit data into 24 bits cv.la %rd,%rs con v er ts 24-bit data into 3 2 bits cv.ls %rd,%rs con v er ts 16-bit data into 32 bits br anch jpr jpr.d sign10 pc relativ e jump dela y ed br anching possib le %rb jpa jpa.d imm7 absolute jump dela y ed br anching possib le %rb jrgt jrgt.d sign7 pc relativ e conditional jump br anch condition: !z & !(n ^ v) dela y ed br anching possib le jrge jrge.d sign7 pc relativ e conditional jump br anch condition: !(n ^ v) dela y ed br anching possib le jrlt jrlt.d sign7 pc relativ e conditional jump br anch condition: n ^ v dela y ed br anching possib le jrle jrle.d sign7 pc re lativ e conditional jump br anch condition: z | n ^ v dela y ed br anching possib le jrugt jrugt.d sign7 pc relativ e conditional jump br anch condition: !z & !c dela y ed br anching possib le jruge jruge.d sign7 pc relativ e conditional jump br anch condition: !c dela y ed br anching possib le jrult jrult.d sign7 pc relativ e conditional jump br anch condition: c dela y ed br anching possib le jrule jrule.d sign7 pc relativ e conditional jump br anch condition: z | c dela y ed br anching possib le jreq jreq.d sign7 p c relativ e conditional jump br anch condition: z dela y ed br anching possib le jrne jrne.d sign7 pc relativ e conditional jump br anch condition: !z dela y ed br anching possib le call call.d sign10 pc relativ e subroutine call dela y ed call possib le %rb calla calla.d imm7 absolute subroutine call dela y ed call possib le %rb ret ret.d retur n from subroutine dela y ed retur n possib le int imm5 softw are interr upt intl imm5,imm3 softw are interr upt with interr upt le v el setting reti reti.d retur n from interr upt handli ng dela y ed call possib le brk deb ug interr upt
2 cpu s1c17651 t echnical m anual seiko epson corporation 2-5 classification mnemonic function br anch retd retur n from deb ug processing system control nop no oper ation halt hal t mode slp sleep mode ei enab le interr upts di disab le interr upts coprocessor control ld.cw %rd,%rs t r ansf er data to coprocessor %rd,imm7 ld.ca %rd,%rs t r ansf er data to coprocessor and get results and ?ag statuses %rd,imm7 ld.cf %rd,%rs t r ansf er data to coprocessor and get ?ag statuses %rd,imm7 *1 the ld.a instr uction accesses memor ies in 32-bit length. dur ing data tr a nsf er from a register to a memor y , the 32-bit data in which the eight high-order bits are set to 0 is wr itten to the memor y . dur ing reading from a memor y , the eight high-order bits of the read data are ignored. the symbols in the abo v e table each ha v e the meanings specif ied belo w . 3.2 symbol meanings t ab le 2. symbol description %rs gener al-pur pose register , source %rd gener al-pur pose register , destination [%rb] memor y addressed b y gener al-pur pose register [%rb]+ memor y addressed b y gener al-pur pose register with address post-incremented [%rb]- memor y addressed b y gener al-pur pose register with address post-decremented -[%rb] memor y addressed b y gener al-pur pose register with address pre-decremented %sp stac k pointer [%sp],[%sp+imm7] stac k [%sp]+ stac k with a ddress post-incremented [%sp]- stac k with address post-decremented -[%sp] stac k with address pre-decremented imm3,imm5,imm7,imm13 unsigned immediate (n umer als indicating bit length) sign7,sign10 signed immediate (n umer als indicating bit length) reading psr 2.4 the s1c17651 includes the misc_psr re gister for reading the contents of the psr (processor status re gister) in the s1c17 core. reading the contents of this re gister mak es it possib le to check the contents of the psr using the application softw are. note that data cannot be written to the psr. psr register (misc_psr) register name ad dress bit name function setting init. r/w remarks psr register (misc_psr) 0x532c (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C5 psril[2:0] psr interr upt le v el (il) bits 0x0 to 0x7 0x0 r d4 psrie psr interr upt enab le (ie) bit 1 1 (enab le) 0 0 (disab le) 0 r d3 psrc psr carr y (c) flag 1 1 (set) 0 0 (cleared) 0 r d2 psrv psr o v erflo w (v) flag 1 1 (set) 0 0 (cleared) 0 r d1 psrz psr z ero (z) flag 1 1 (set) 0 0 (cleared) 0 r d0 psrn psr negativ e (n) flag 1 1 (set) 0 0 (cleared) 0 r d[15:8] reserved d[7:5] psril[2:0]: psr interrupt level (il) bits the v alue of the psr il (interrupt le v el) bits can be read out. (def ault: 0x0) d4 psrie: psr interrupt enable (ie) bit the v alue of the psr ie (interrupt enable) bit can be read out. 1 (r): 1 (interrupt enabled) 0 (r): 0 (interrupt disabled) (def ault)
2 cpu 2-6 seiko epson corporation s1c17651 t echnical m anual d3 psrc: psr carry (c) flag bit the v alue of the psr c (carry) flag can be read out. 1 (r): 1 0 (r): 0 (def ault) d2 psrv: psr overflow (v) flag bit the v alue of the psr v (o v erflo w) flag can be read out. 1 (r): 1 0 (r): 0 (def ault) d1 psrz: psr zero (z) flag bit the v alue of the psr z (zero) flag can be read out. 1 (r): 1 0 (r): 0 (def ault) d0 psrn: psr negative (n) flag bit the v alue of the psr n (ne g ati v e) flag can be read out. 1 (r): 1 0 (r): 0 (def ault) pr ocessor inf ormation 2.5 the s1c17651 has the idir re gister sho wn belo w that allo ws the application softw are to identify cpu core type. pr ocessor id register (idir) register name ad dress bit name function setting init. r/w remarks processor id register (idir) 0xffff84 (8 bits) d7C0 idir[7:0] processor id 0x10: s1c17 core 0x10 0x10 r this is a read-only re gister that contains the id code to represent a processor model. the s1c17 core s id code is 0x10.
3 memor y map , b us contr ol s1c17651 t echnical m anual seiko epson corporation 3-1 memory map, bus contr ol 3 figure 3.1 sho ws the s1c17651 memory map. reserved area * flash area (16k bytes) (device size: 16 bits) vector table internal peripheral area 2 (4k bytes) internal peripheral area 1 (1k bytes) reserved for core i/o area (1k bytes) reserved reserved reserved reserved 0xff ffff 0xff fc00 0xff fbff 0x00 c000 0x00 bfff 0x00 bffa 0x00 8000 0x00 7fff 0x00 6000 0x00 5fff 0x00 5000 0x00 4fff 0x00 4400 0x00 43ff 0x00 4000 0x00 3fff 0x00 0800 0x00 07ff 0x00 07c0 0x00 0000 0x4340C0x43ff 0x4320C0x433f 0x4300C0x431f 0x4260C0x42ff 0x4240C0x425f 0x4120C0x423f 0x4100C0x411f 0x4040C0x40ff 0x4020C0x403f 0x4000C0x401f reserved spi ch.0 interrupt controller reserved 8-bit timer ch.0 reserved uart ch.0 reserved misc registers reserved debug ram area (64 bytes) internal ram area (2k bytes) (device size: 32 bits) 0x56e0C0x5fff 0x56c0C0x56df 0x54c0C0x56bf 0x5480C0x54bf 0x5420C0x547f 0x5400C0x541f 0x53d4C0x53ff 0x53c0C0x53d3 0x5340C0x53bf 0x5320C0x533f 0x52c0C0x531f 0x52a0C0x52bf 0x5240C0x529f 0x5200C0x523f 0x51a0C0x51ff 0x5180C0x519f 0x5140C0x517f 0x5120C0x513f 0x5100C0x511f 0x50c0C0x50ff 0x50a0C0x50bf 0x5060C0x509f 0x5040C0x505f 0x5020C0x503f 0x5000C0x501f reserved real-time clock reserved flash controller reserved 16-bit pwm timer ch.0 reserved display ram (segram) reserved misc registers reserved port mux reserved p ports reserved sound generator reserved power generator supply voltage detection circuit reserved lcd driver clock generator watchdog timer reserved clock timer C (16 bits) C (16 bits) C (16 bits) C (16 bits) C (16 bits) C (8 bits) C (8 bits) C (8 bits) C (8 bits) (8 bits) C (8 bits) (8 bits) (8 bits) C (8 bits) C (16 bits) (16 bits) C (16 bits) C (8 bits) C (8 bits) C peripheral function (device size) * 0xbffaC0xbffb: reserved for the theoretical regulation function (see the setting regulation values section in the theoretical regulation chapter.) 0xbffcC0xbfff: flash protect bit area (see the protect bits section in this chapter.) 1 s1c17651 memor y map figure 3. bus cyc le 3.1 the cpu uses the system clock for b us access operations. f or more information on the system clock, see system clock switching in the clock generator (clg) chapter . accessing in one b us c ycle requires one system clock in all areas. furthermore, the number of b us accesses depends on the cpu instruction (access size) and de vice size. 1.1 number of bus ac cesses t ab le 3. de vice siz e cpu access siz e number of b us accesses 8 bits 8 bits 1 16 bits 2 32 bits* 4 16 bits 8 bits 1 16 bits 1 32 bits* 2 32 bits 8 bits 1 16 bits 1 32 bits* 1
3 memor y map , b us contr ol 3-2 seiko epson corporation s1c17651 t echnical m anual * handling the eight high-order bits dur ing 32-bit accesses the size of the s1c17 core general-purpose re gisters is 24 bits. during writing, the eight high-order bits are written as 0. during reading from a memory , the eight high-order bits are ignored. ho we v er , the stack operation in an interrupt handling reads/writes 32-bit data that consists of the psr v alue as the high-order 8 bits and the ret urn address as the lo w order 24 bits. f or more information, refer to the s1c17 core manual. restrictions on access siz e 3.1.1 the peripheral modules can be accessed with an 8-bit, 16-bit, or 32-bit instruction. ho we v er , reading for an unnec- essary re gister may change the peripheral module status and it may cause a problem. therefore, use the appropriate instructions according to the de vice size. r estrictions on instruction ex ecution cyc les 3.1.2 an instruction fetch and a data access are not performed simultaneously under one of the conditions listed belo w . this prolongs the instruction fetch c ycle for the number of data area b us c ycles. ? when the s1c17651 e x ecutes the instruction stored in the flash area and accesses data in the flash area ? when the s1c17651 e x ecutes the instruction store d in the internal ram area and accesses data in the internal ram area flash area 3.2 embed ded flash memor y 3.2.1 the 16k-byte area from address 0x8000 to address 0xbf f f contains a flash memory (4k bytes 4 sectors) for stor - ing application programs and data. address 0x8000 is def ined as the v ector table base address, therefore a v ector table (see v ector t able in the interrupt controller (itc) chapter) must be placed from the be ginning of the area. the v ector table base address can be modif ied with the misc_ttbrl/misc_ttbrh re gisters. flash pr ogramming 3.2.2 the s1c17651 supports on-board programming of the flash memory , it mak es it possible to program the flash memory with the application programs/data by using the deb ugger through an icdmini. pr otect bits 3.2.3 in order to protect th e memory contents, the flash memory pro vides tw o protection features, write protection and data read protection, that can be conf igured for e v ery 4k-byte areas. the write protection disables writing data to the conf igured area and erasing the sectors (e xcept the sector that includes the protect bits). the data-read protec- tion disables reading data from the conf igured area (the read v alue is al w ay s 0x0000). ho we v er , it does not disable the instruction fetch operation by the cpu. the flash memory pro vides the protect bits listed belo w . program the protect bit corresponding to the area to be protected to 0. the protection can only be disabled using the deb ugger .
3 memor y map , b us contr ol s1c17651 t echnical m anual seiko epson corporation 3-3 flash pr otect bits ad dress bit function setting init. r/w remarks 0xbffc (16 bits) d15C4 reser v ed C C C d3 flash wr ite-protect bit f or 0xb000C0xbfff 1 wr itab le 0 protected 1 r/w d2 flash wr ite-protect bit f or 0xa000C0xafff 1 wr itab le 0 protected 1 r/w d1 flash wr ite-protect bit f or 0x9000C0x9fff 1 wr itab le 0 protected 1 r/w d0 flash wr ite-protect bit f or 0x8000C0x8fff 1 wr itab le 0 protected 1 r/w 0xbffe (16 bits) d15C4 reser v ed C C C d3 flash data-read-protect bit f or 0xb000C0xbfff 1 readab le 0 protected 1 r/w d2 flash data-r ead-protect bit f or 0xa000C0xafff 1 readab le 0 protected 1 r/w d1 flash data-read-protect bit f or 0x9000C0x9fff 1 readab le 0 protected 1 r/w d0 reser v ed 1 1 r/w alw a ys set to 1. notes: ? be sure not to locate the area with data-read protection into the .data and .rodata sections . ? be sure to set d0 of address 0xbff e to 1. if it is set to 0, the prog r am cannot be booted. flash memor y read w ait cyc le setting 3.2.4 in order to read data from the flash memory properly , set the appropriate number of w ait c ycles according to the system clock frequenc y using the rd w ait[1:0]/flashc_w ait re gister . flashc read wait control register (flashc_wait) register name ad dress bit name function setting init. r/w remarks flashc read wait control register (flashc_ wait) 0x54b0 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7 C reser v ed C x C x when being read. d6-2 C reser v ed C C C 0 when being read. d1C0 rdwait [1:0] flash read w ait cycle rd w ait[1:0] w ait 0x3 r/w 0x3 0x2 0x1 0x0 3 w ait 2 w ait 1 w ait no w ait d[1:0] rdwait[1:0]: flash read wait cycle bits sets the number of w ait c ycles for reading from the flash memory . one w ait insertion prolongs b us c ycles by one system clock c ycle. note: set rd w ait[1:0] to 0x0 to achie v e the best perf or mance . intern al ram area 3.3 embed ded ram 3.3.1 the s1c17651 contains a ram in the 2k-byte area from address 0x0 to address 0x7f f. the ram allo ws high- speed e x ecution of the instruction codes copied into it as well as storing v ariables and other data. note: t h e 6 4 - b y t e a r e a a t t h e e n d o f t h e r a m ( 0 x 7 c 0 C 0 x 7 f f ) i s r e s e r v e d f o r t h e o n - c h i p d e b u g g e r . w h e n using the deb ug functions under application de v elopment, do not access this area from the appli- cation prog r am. this area can be used f or applications of mass-produced de vices that do not need deb ugging. the s1c17651 enables the ram size used to apply restrictions to 2kb, 1kb, or 512b. f or e xample, when using the s1c17651 to de v elop an application for a b uilt-in r om model, you can set the ram size to match that of the tar get model, pre v enting creating program s that seek to access areas outside the ram areas of the tar get product. the ram size is selected using iramsz[2:0]/misc_iramsz re gister .
3 memor y map , b us contr ol 3-4 seiko epson corporation s1c17651 t echnical m anual iram size register (misc_iramsz) register name ad dress bit name function setting init. r/w remarks iram size register (misc_iramsz) 0x5326 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 dbadr deb ug base address select 1 0x0 0 0xfffc00 0 r/w d7 C reser v ed C C C 0 when being read. d6C4 iramactsz [2:0] iram actual siz e 0x3 (= 2kb) 0x3 r d3 C reser v ed C C C 0 when being read. d2C0 iramsz[2:0] iram siz e select iramsz[2:0] siz e 0x3 r/w 0x5 0x4 0x3 other 512b 1kb 2kb reser v ed d[6:4] iramactsz[2:0]: iram actual size bits indicates the actual internal ram size embedded. (def ault: 0x3) d[2:0] iramsz[2:0]: iram size select bits selects the internal ram size used. 3.1.1 selecting inter nal ram siz e t ab le 3. iramsz[2:0] internal ram siz e 0x5 512b 0x4 1kb 0x3 2kb other reser v ed (def ault: 0x3) note: the misc_iramsz register is wr ite-protected. the wr ite-protection m ust be o v err idden b y wr iting 0x96 to the misc_pr o t register . note that the misc_pr o t register should nor mally be set to a v a l u e o t h e r t h a n 0 x 9 6 , e x c e p t w h e n w r i t i n g t o t h e m i s c _ i r a m s z r e g i s t e r . u n n e c e s s a r y p r o g r a m s ma y result in system malfunctions . displa y ram area 3.4 the display ram for the on-chip lcd dri v er is located in the 20-byte area be ginning with address 0x53c0 in the internal peripheral area. the display ram is accessed in one c ycle as a 16-bit de vice. see the display memory section in the lcd dri v er (lcd) chapter for specif ic information on the display memory . internal p eripheral area 3.5 the i/o and control re gisters for the interna l peripheral modules are located in the 1k-byte area be ginning with ad- dress 0x4000 and the 4k-byte area be ginning with address 0x5000. f or details of each control re gister , see the i/o re gister list in appendix or description for each peripheral module. internal p eripheral area 1 (0x4000C) 3.5.1 the internal peripheral area 1 be ginning with address 0x4000 contains the i/o memory for the peripheral functions listed belo w . ? misc re gister (misc, 8-bit de vice) ? u ar t (u ar t , 8-bit de vice) ? 8-bit timer (t8, 16-bit de vice) ? interrupt controller (itc, 16-bit de vice) ? spi (spi, 16-bit de vice)
3 memor y map , b us contr ol s1c17651 t echnical m anual seiko epson corporation 3-5 internal p eripheral area 2 (0x5000C) 3.5.2 the internal peripheral area 2 be ginning with address 0x5000 contains the i/o memory for the peripheral functions listed belo w . ? clock timer (ct , 8-bit de vice) ? w atchdog timer (wdt , 8-bit de vice) ? clock generator (clg, 8-bit de vice) ? lcd dri v er (lcd, 8-bit de vice) ? supply v oltage detection circuit (svd, 8-bit de vice) ? po wer generator (vd1, 8-bit de vice) ? sound generator (snd, 8-bit de vice) ? i/o port & port mux (p , 8-bit de vice) ? misc re gister (misc, 16-bit de vice) ? display ram (segram, 16-bit de vice) ? 16-bit pwm timer (t16a2, 16-bit de vice) ? flash controller (flashc, 16-bit de vice) ? real-time clock (r tc, 16-bit de vice) s1c17 core i/o area 3.6 the 1k-byte area from address 0xf f fc00 to address 0xf f f f f f is the i/o area for the cpu core in which the i/ o re gis- ters listed in the table belo w are located. 6.1 i/o map (s1c17 core i/o area) t ab le 3. p eripheral ad dress register name function s1c17 core i/o 0xffff84 idir processor id register indicates the processor id . 0xffff90 dbram deb ug ram base register indicates the deb ug ram base address . 0xffff a0 dcr deb ug control register deb ug control 0xffffb4 ibar1 instr uction break address register 1 instr uction break address #1 setting 0xffffb8 ibar2 instr uction break address register 2 instr uction break address #2 settin g 0xffffbc ibar3 instr uction break address register 3 instr uction break address #3 setting 0xffffd0 ibar4 instr uction break address register 4 instr uction break address #4 setting s e e p r o c e s s o r i n f o r m a t i o n i n t h e c p u c h a p t e r f o r m o r e i n f o r m a t i o n o n i d i r . s e e t h e o n - c h i p d e b u g g e r (dbg) chapter for more information on other re gisters. this area includes the s1c17 core re gisters, in addition to those des cribed abo v e. f or more information on these re gisters, refer to the s1c17 core manual.
4 po wer suppl y s1c17651 t echnical m anual seiko epson corporation 4-1 p o wer supply 4 p o wer suppl y v olta g e (v 4.1 dd ) the s1c17651 operates with a v oltage supplied between the v dd and v ss pins. supply a v oltage within the range sho wn belo w to the v dd pins with the v ss pins as the gnd le v el. v dd = 2.0 v to 3.6 v (v ss = gnd) the s1c17651 pro vides tw o or more v dd and v ss pins. do not lea v e an y po wer supply pins open and be sure to connect them to + po wer source and gnd. f lash pr ogramming p o wer suppl y v olta g e (v 4.2 pp ) the v pp v oltage is used for programming/erasing the embedded flash memory . supply a v oltage sho wn belo w to the v pp pin with the v ss pins as the gnd le v el to program the flash memory . v pp = 7 v (v ss = gnd) f or prog r amming v pp = 7.5 v (v ss = gnd) f or er asing note: lea v e the v pp pin open dur ing nor mal oper ation. internal p o wer suppl y cir cuit 4.3 the s1c17651 has a b uilt-in po wer supply circuit sho wn in figure 4.3.1 to generate the operating v oltages required for the internal circuits. external power supply v d1 osc3a/osc3b oscillator circuits v d1 regulator internal logic circuits i/o interface osc3, osc4 v dd v d1 v osc pxx hvld v osc v osc regulator osc1a/osc1b oscillator circuits osc1, osc2 lcd driver segxx comx v ss v c1 v c2 v c3 ca cb v ss vcsel lcd power supply circuit (v c regulator, voltage booster /halver) v c1 Cv c3 lhvld 3.1 configur ation of inter nal p o w er supply circuit figure 4. the internal po wer supply circuit consists of a v d1 re gulator , a v osc re gulator , and an lcd po wer supply circuit. note: be sure to a v oid using the outputs of the inter nal po w er supply circuit f or dr iv e e xter nal de vices . v 4.3.1 d1 and v osc regulator s the v d1 and v osc re gulators generate the operating v oltages for the internal logic and oscillat or circuits. this re gu- lator al w ays operates.
4 po wer suppl y 4-2 seiko epson corporation s1c17651 t echnical m anual lcd p o wer suppl y cir cuit 4.3.2 the lcd po wer supply circuit generates the lcd dri v e v oltages v c1 to v c3 . these v oltages are supplied to the lcd dri v er to generate lcd dri v e w a v eforms. the lcd po wer supply circuit consists of a v c re gulator and v olt- age booster/halv er . see the electrical characteristics chapter for the v c1 to v c3 v alues. v c regulator the v c re gulator generates the reference v oltage for boosting/halving (v c1 or v c2 ) from v dd . e i t h e r v c1 o r v c2 c a n b e g e n e r a t e d a n d o n e o f t h e m s h o u l d b e s e l e c t e d a c c o r d i n g t o t h e v d d v a l u e u s i n g vcsel/lcd_vreg re gister . 3.2.1 v t ab le 4. c regulator output selection p o wer suppl y v olta g e v dd vcsel setting ref erence v olta g e 2.0 to 2.2 (3.6) v 0 v c1 2.2 to 3.6 v 1 v c2 (def ault: 0) notes: ? the v c1 to v c3 v oltages cannot be obtained correctly if vcsel is set to 1 when v dd is 2.2 v or less . ? a l t h o u g h t h e r e f e r e n c e v o l t a g e c a n b e s e t t o v c1 e v e n i f v d d i s 2.2 v o r h i g h e r , c u r r e n t consumption will be increased in compar ison with v c2 . v olta g e booster/halver when v c1 is selected fo r the boosting/halving reference v oltage, the v oltage booster/halv er generates v c2 and v c3 by boosting v c1 output from the v c re gulator . when v c2 is selected for the reference v oltage, the v oltage booster/halv er generates v c1 by halving v c2 and v c3 by boosting v c2 . the boosting operation uses a clock, so it must be supplied to the lcd po wer supply circuit before lcd can start display . booster c loc k sour ce selection s e l e c t t h e c l o c k s o u r c e f o r t h e v o l t a g e b o o s t e r / h a l v e r f r o m o s c 3 b , o s c 3 a , a n d o s c 1 u s i n g lcdbclksrc[1:0]/lcd_bclk re gister . 3.2.2 cloc k source selection t ab le 4. lcdbclksrc[1:0] cloc k sour ce 0x3 reser v ed 0x2 osc3a 0x1 osc1 0x0 osc3b (def ault: 0x0) booster c loc k division ratio selection select the di vision ratio using lcdbclkd[2:0]/lcd_bclk re gister . set it so that the clock frequenc y will be within the range from 512 hz to 4 khz. 3.2.3 cloc k division ratio selection t ab le 4. lcdbclkd[2:0] division ratio cloc k sour ce = osc3b cloc k sour ce = osc3a cloc k sour ce = osc1 0x7 reser v ed reser v ed reser v ed 0x6 1/4096 1/8192 0x5 1/2048 1/4096 0x4 1/1024 1/2048 0x3 1/512 1/1024 1/64 0x2 1/256 1/512 1/32 0x1 1/128 1/256 1/16 0x0 1/64 1/128 1/8 (def ault: 0x0)
4 po wer suppl y s1c17651 t echnical m anual seiko epson corporation 4-3 booster c loc k enab le t h e b o o s t e r c l o c k s u p p l y i s e n a b l e d w i t h l c d b c l k e / l c d _ b c l k r e g i s t e r . t h e l c d b c l k e d e fa u l t setting is 0, which stops the clock. setting lcdbclke to 1 feeds the clock generated as abo v e to the lcd po wer supply circuit. if no lcd display is required, stop the clock to reduce current consumption. hea vy load pr otection mode 4.3.3 in order to ensure a stable circuit beha vior and lcd display quality e v en if the po wer supply v oltage fluctuates due to dri ving an e xternal load, the re gulators ha v e a hea vy load protection function. the table belo w lists the control bits used for setting hea vy load protection mode. 3.3.1 hea vy load protection mode control bits t ab le 4. regulator control bit v d1 regulator hvld/vd1_ctl register v osc regulator v c regulator lhvld/lcd _vreg register when the control bit is set to 1, the re gulator ensures stable output. the v d1 and v osc re gulators should be placed into hea vy load protection mode before dri ving a hea vy load such as a lamp or b uzzer with a port output. the v c re gulator should be placed into hea vy load protection mode when the d isplay has inconsistencies in density . note: current consumption increases in hea vy load protection mode , theref ore do not set hea vy load protection mode with softw are if unnecessar y . contr ol register details 4.4 4.1 list of p o w er control registers t ab le 4. ad dress register name function 0x5071 lcd_bclk lcd booster cloc k control register controls the lcd booster cloc k. 0x50a3 lcd_vreg lcd v oltage regulator control register controls the v c regulator . 0x5120 vd1_ctl v d1 control register controls the v d1 regulator . the po wer control re gisters are described in detail belo w . note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. lcd booster clock control register (lcd_bclk) register name ad dress bit name function setting init. r/w remarks lcd booster clock control register (lcd_bclk ) 0x5071 (8 bits) d7 C reser v ed C C C 0 when being read. d6C4 lcdbclkd [2:0] lcd booster cloc k division r atio select lcdb clkd [2:0] division r atio 0x0 r/w osc3b osc3a osc1 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 C 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 C 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 C C C C 1/64 1/32 1/16 1/8 d3C2 lcdbclk src[1:0] lcd booster cloc k source select lcdbclk src[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3a osc1 osc3b d1 C reser v ed C C C 0 when being read. d0 lcdbclke lc d booster cloc k enab le 1 enab le 0 disab le 0 r/w d7 reserved
4 po wer suppl y 4-4 seiko epson corporation s1c17651 t echnical m anual d[6:4] lcdbclkd[2:0]: lcd booster clock division ratio select bits selects the di vision ratio for generating the booster clock. 4.2 cloc k division ratio selection t ab le 4. lcdbclkd[2:0] division ratio cloc k sour ce = osc3b cloc k sour ce = osc3a cloc k sour ce = osc1 0x7 reser v ed reser v ed reser v ed 0x6 1/4096 1/8192 0x5 1/2048 1/4096 0x4 1/1024 1/2048 0x3 1/512 1/1024 1/64 0x2 1/256 1/512 1/32 0x1 1/128 1/256 1/16 0x0 1/64 1/128 1/8 (def ault: 0x0) d[3:2] lcdbclksrc[1:0]: lcd booster clock source select bits selects the booster clock source. 4.3 cloc k source selection t ab le 4. lcdbclksrc[1:0] cloc k sour ce 0x3 reser v ed 0x2 osc3a 0x1 osc1 0x0 osc3b (def ault: 0x0) d1 reserved d0 lcdbclke: lcd booster clock enable bit enables or disables the booster clock supply to the lcd po wer supply circuit. 1 (r/w): enabled (on) 0 (r/w): disabled (of f) (def ault) the lcdbclke def ault setting is 0, which disables the clock supply . setting lcdbclke to 1 sends the clock to the lcd po wer supply circuit. if lcd display is not required, disable the clock supply to reduce current consumption. lcd voltage regulator control register (lcd_vreg) register name ad dress bit name function setting init. r/w remarks lcd voltage regulator control register (lcd_vreg) 0x50a3 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 lhvld v c hea vy load protection mode 1 on 0 off 0 r/w d3C1 C reser v ed C C C 0 when being read. d0 vcsel ref erence v oltage select 1 v c2 0 v c1 0 r/w d[7:5] reserved d4 lhvld: v c heavy load protection mode bit sets the v c re gulator into hea vy load protection mode. 1 (r/w): hea vy load protection on 0 (r/w): hea vy load protection of f (def ault) the v c re gulator enters hea vy load protection mode by writing 1 to lhvld and it ensures stable ou t- put. use the hea vy load protection function when the display has inconsistencies in density . current consumption increases in hea vy load protection mode, therefore do not set if unnecessary . d[3:1] reserved d0 vcsel: reference voltage select bit selects the v c re gulator output v oltage (reference v oltage for boosting/halving). 1 (r/w): v c2 0 (r/w): v c1 (def ault)
4 po wer suppl y s1c17651 t echnical m anual seiko epson corporation 4-5 select either v c1 or v c2 to be generated by the v c re gulator according to the v dd v alue. 4.4 v t ab le 4. c regulator output selection p o wer suppl y v olta g e v dd vcsel setting ref erence v olta g e 2.0 to 2.2 (3.6) v 0 v c1 2.2 to 3.6 v 1 v c2 (def ault: 0) notes: ? the v c1 to v c3 v oltages cannot be obtained correctly if vcsel is set to 1 when v dd is 2.2 v or less . ? a l t h o u g h t h e r e f e r e n c e v o l t a g e c a n b e s e t t o v c1 e v e n i f v d d i s 2.2 v o r h i g h e r , c u r r e n t consumption will be increased in compar ison with v c2 . v d1 control register (vd1_ctl) register name ad dress bit name function setting init. r/w remarks v d1 control register (vd1_ctl) 0x5120 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5 hvld v d1 hea vy load protection mode 1 on 0 off 0 r/w d4C0 C reser v ed C C C 0 when being read. d[7:6] reserved d5 hvld: v d1 heavy load protection mode bit sets the v d1 and v osc re gulators into hea vy load protection mode. 1 (r/w): hea vy load protection on 0 (r/w): hea vy load protection of f (def ault) the v d1 and v osc re gulators enter hea vy load protection mode by writing 1 to hvld and the y ensure stable v d1 and v osc outpu ts. use the hea vy load protection function when a hea vy load such as a lamp or b uzzer is dri v en with a port output. current consumption increases in hea vy load protection mode, therefore do not set if unnecessary . d[4:0] reserved
5 initial reset s1c17651 t echnical m anual seiko epson corporation 5-1 initial reset 5 initial reset sour ces 5.1 the s1c17651 has three initial reset sources that initialize the internal circuits. (1) #reset pin (e xternal initial reset) (2) k e y-entry reset using the p0 ports (p00Cp03 pins) (softw are selectable e xternal initial reset) (3) w atchdog timer (softw are selectable internal initial reset) figure 5.1.1 sho ws the conf iguration of the initial reset circuit. p0 ports #reset key-entry reset signal reset input signal internal reset signal (to core and peripheral modules) wdt reset signal p00 p01 p02 p03 watchdog timer 1.1 configur ation of initial reset circuit figure 5. the cpu and peripheral circuits are initialized by the acti v e signal from an initial reset source. when the reset sig- nal is ne g ated, the cpu starts reset handling. the reset handling reads the reset v ector (reset handler start address) from the be ginning of the v ector table and starts e x ecuting the program (initial routine) be ginning with the re ad ad- dress. #reset pin 5.1.1 by setting the #reset pin to lo w le v el, the s1c17651 enters initial reset state. in order to initialize the s1c17651 for sure, the #reset pin must be held at lo w for more than the prescribed time (see input/output pin characteris- tics in the electrical characteristics chapter) after the po wer supply v oltage is supplied. when the #reset pin at lo w le v el is set to hig h le v el, the cpu starts e x ecuting the initial reset sequence. the #reset pin is equipped with a pull-up resistor . p0 p or t k e y-entr y reset 5.1.2 entering lo w le v el simultaneously to the ports (p00Cp03) selected with softw are triggers an initial reset. f or details of the k e y-entry reset function, see the i/o ports (p) chapter . note: the p0 por t k e y-entr y reset function cannot be used f or po w er-on reset as it m ust be enab led with softw are . resetting b y the w atc hdog timer 5.1.3 the s1c17651 has a b uilt-in w atchdog timer to detect runa w ay of the cpu. the w atchdog timer o v erflo ws if it is not reset with softw are (due to cpu runa w ay) in four -second c ycles. the o v erflo w signal can generate either nmi or reset. write 1 to the wdtmd/wdt_st re gister to generate reset (nmi occurs when wdtmd = 0). f or detai ls of the w atchdog timer , see the w atchdog t imer (wdt) chapter . notes: ? when using the reset function of the w atchdog timer , prog r am the w atchdog timer so that it will be reset within f our-second cycles to a v oid occurrence of an unnecessar y reset. ? the reset function of the w atchdog timer cannot be used f or po w er-on reset as it m ust be en- ab led with softw are .
5 initial reset 5-2 seiko epson corporation s1c17651 t echnical m anual initial reset sequence 5.2 ev en if the #reset pin input ne g ates the reset signal after po wer is turned on, the cpu cannot boot up until the oscillation stabilization w aiting time (64/osc3b clock frequenc y) and the internal reset hold period (32/osc3b clock frequenc y) ha v e elapsed. figure 5.2.1 sho ws the operating sequence follo wing cancellation of initial reset. the cpu starts operating in synchron ization with the osc3b (internal oscillator) clock after reset state is canceled. note: the oscillation stabilization time descr ibed in this section does not include oscillation star t time . theref ore the time inter v al until the cpu star ts e x ecuting instr uctions after po w er is tur ned on or sleep mode is canceled ma y be longer than that indicated in the figure belo w . boot vector osc3b oscillation stabilization waiting time internal reset hold period booting osc3b clock #reset internal reset internal data request internal data address internal reset canceled reset canceled 2.1 oper ation sequence f ollo wing cancellation of initial reset figure 5. initial settings after an initial reset 5.3 the cpu internal re gisters are initialized as follo ws at initial reset. r0Cr7: 0x0 psr: 0x0 (interrupt le v el = 0, interrupt disabled) sp: 0x0 pc: reset v ector stored at the be ginning of the v ector table is loaded by the reset handling. the internal ram should be initialized with softw ar e as it is not initialized at initial reset. the internal peripheral modules are initialized to the def ault v alues (e xcept some undef ined re gisters). change the settings with softw are if necessary . f or the def ault v alues set at initial reset, see the list of i/o re gisters in appendix or descriptions for each peripheral module.
6 interr upt contr oller (itc) s1c17651 t echnical m anual seiko epson corporation 6-1 interrupt contr oller (itc) 6 itc module over vie w 6.1 the interrupt controller (itc) honors interrupt requests from the peripheral modules and outputs the interrupt re- quest, interrupt le v el and v ector number signals to the s1c17 core according to the priority and interrupt le v els. the features of the itc module are listed belo w . ? supports eight maskable interrupt systems. 1. p00Cp07 input interrupt (8 types) 2. clock timer interrupt (4 types) 3. r tc interrupt (10 types) 4. lcd interrupt (1 type) 5. 16-bit pwm timer ch.0 interrupt (6 types) 6. 8-bit timer ch.0 interrupt (1 type) 7. u ar t ch.0 interrupt (4 types) 8. spi ch.0 interrupt (2 types) ? supports eight interrupt le v els to prioritize the interrupt sources. the itc enables the interrupt le v el (priority) for determining the processing sequence w hen multiple interrupts oc- cur simultaneously to be set for each interrupt system separately . each interrupt system includes the number of interrupt causes indicated in parentheses abo v e. settings to enable or disable interrupt for dif ferent causes are set by the respecti v e peripheral module re gisters. f or specif ic information on interrupt causes and their control, refer to the peripheral module e xp lanations. figure 6.1.1 sho ws the structure of the interrupt system. s1c17 core interrupt controller watchdog timer interr upt request interr upt le ve l v ector number deb ug signal reset signal interr upt request nmi interrupt level interrupt control vector number interrupt level vector number interr upt request ? ? ? ? ? ? ? ? peripheral module interrupt enable cause of interr upt 1 interrupt enable cause of interr upt n ? ? ? ? interrupt flag interrupt flag peripheral module interrupt enable cause of interr upt 1 interrupt enable cause of interr upt n ? ? ? ? interrupt flag interrupt flag 1.1 interr upt system figure 6.
6 interr upt contr oller (itc) 6-2 seiko epson corporation s1c17651 t echnical m anual v ector t ab le 6.2 the v ector table contains the v ectors to the interrupt handler routines (handler routine start address) that will be read by the s1c17 core to e x ecute the handler when an interrupt occurs. t able 6.2.1 sho ws the v ector table of the s1c17651. 2.1 v ector t ab le t ab le 6. v ector no. s o f t w a r e i n t e r r u p t n o . v ector ad dress har d ware interrupt name cause of har d ware interrupt priority 0 (0x00) ttbr + 0x00 reset ? lo w input to the #reset pin ? w atchdog timer o v er?o w *2 1 1 (0x01) ttbr + 0x04 address misaligned interr upt memor y access instr uction 2 C (0xfffc00) deb ugging interr upt brk instr uction, etc. 3 2 (0x02) ttbr + 0x08 nmi w atchdog timer o v er?o w *2 4 3 (0x03) ttbr + 0x0c reser v ed f or c compiler C C 4 (0x04) ttbr + 0x10 p0 por t interr upt p00Cp07 por t inputs high *1 5 (0x05) ttbr + 0x14 reser v ed C 6 (0x06) ttbr + 0x18 7 (0x07) ttbr + 0x1c cloc k timer interr upt ? 32 hz timer signal ? 8 hz timer signal ? 2 hz timer signal ? 1 hz timer signal 8 (0x08) ttbr + 0x20 r tc interr upt ? 32 hz, 8 hz, 4 hz, 1 hz ? 10 s , 1 m, 10 m, 1 h ? half-da y , one da y 9 (0x09) ttbr + 0x24 reser v ed C 10 (0x0a) ttbr + 0x28 lcd interr upt f r ame signal 11 (0x0b) ttbr + 0x2c 16-bit pwm timer ch.0 interr upt ? compare a/b ? capture a/b ? capture a/b o v erwr ite 12 (0x0c) ttbr + 0x30 reser v ed C 13 (0x0d) ttbr + 0x34 14 (0x0e) ttbr + 0x38 8-bit timer ch. 0 interr upt timer under?o w 15 (0x0f) ttbr + 0x3c reser v ed C 16 (0x10) ttbr + 0x40 u ar t ch.0 interr upt ? t r ansmit b uff er empty ? end of tr ansmission ? receiv e b uff er full ? receiv e error 17 (0x11) ttbr + 0x44 reser v ed C 18 (0x12) ttbr + 0x48 spi ch.0 interr upt ? t r ansmit b uff er empty ? receiv e b uff er full 19 (0x13) ttbr + 0x4c reser v ed C : : : : 31 (0x1f) ttbr + 0x7c reser v ed C lo w *1 *1 when the same interr upt le v el is set *2 either reset or nmi can be selected as the w atchdog timer interr upt with softw are . v ector numbers 4, 7, 8, 10, 11, 14, 16, and 18 are assigned to the maskable interrupts supported by the s1c17651. v ector tab le base ad dres s t h e s1c17651 a l l o w s t h e b a s e ( s t a r t i n g ) a d d r e s s o f t h e v e c t o r t a b l e t o b e s e t u s i n g t h e m i s c _ t t b r l a n d misc_ttbrh re gisters. ttbr described in t able 6.2.1 means the v alue set to these re gisters. after an ini- tial reset, the misc_ttbrl and misc_ttbrh re gisters are set to 0x8000. therefore, e v en when the v ector table location is changed, it is necessary that at least the reset v ector be written to the abo v e address. bits 7 to 0 in the misc_ttbrl re gister are f ix ed at 0, so the v ector table starting address al w ays be gins with a 256-byte boundary address.
6 interr upt contr oller (itc) s1c17651 t echnical m anual seiko epson corporation 6-3 vector table address low/high registers (misc_ttbrl, misc_ttbrh) register name ad dress bit name function setting init. r/w remarks vector table address low register (misc_ttbrl) 0x5328 (16 bits) d15C8 ttbr[15:8] v ector tab le base address a[15:8] 0x0C0xff 0x80 r/w d7C0 ttbr[7:0] v ector tab le base address a[7:0] (fix ed at 0) 0x0 0x0 r vector table address high register (misc_ttbrh) 0x532a (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 ttbr[23:16] v ector tab le base address a[23:16] 0x0C0xff 0x0 r/w note: t h e m i s c _ t t b r l a n d m i s c _ t t b r h r e g i s t e r s a r e w r i t e - p r o t e c t e d . b e f o r e t h e s e r e g i s t e r s c a n be re wr itten, wr ite protection m ust be remo v ed b y wr iting data 0x96 to the misc_pr o t register . n o t e t h a t s i n c e u n n e c e s s a r y r e w r i t e s t o t h e m i s c _ t t b r l a n d m i s c _ t t b r h r e g i s t e r s c o u l d l e a d to err atic system ope r ation, the misc_pr o t register should be set to other than 0x96 unless the v ector t ab le base registers m ust be re wr itten. contr ol of maskab le interrupts 6.3 interrupt contr ol bits in p eripheral modules 6.3.1 the peripheral module that generates interrupts includes an interrupt enable bit and an interrupt flag for each inter - rupt cause. the interrupt flag is set to 1 when the cause of interrupt occu rs. by setting the interrupt enable bit to 1 (interrupt enabled), the flag state will be sent to the itc as an interrupt request signal, generating an interrupt re- quest to the s1c17 core. the corresponding interrupt enable bits should be set to 0 for those causes for which interrupts are not desired. in this case, although the interrupt flag is set to 1 if the interrupt cause occurs, the interrup t request signal sent to the itc will not be asserted. f or specif ic information on causes of interrupts, interrupt flags, and interrupt enable bits, refer to the respecti v e pe- ripheral module descriptions. note: t o pre v ent recurrence of the interr upt due to the same cause of interr upt, alw a ys reset the inter- r upt flag in the per ipher al module bef ore enab ling the interr upt, resetting the psr, or e x ecuti ng the reti instr uction. itc interrupt request pr ocessing 6.3.2 on recei ving an interrupt signal from a peripheral module, the itc sends the interrupt request, interrupt le v el, and v ector number signals to the s1c17 core. v ector numbers are determined by the itc internal hardw are for each interrupt cause, as sho wn in t able 6.2.1. the interrupt le v el is a v alue used by the s1c17 core to compare with the il bits (psr). this interrupt le v el is used in the s1c17 core to disable subsequently occurring interrupts with the same or lo wer le v el. (see section 6.3.3.) the def ault itc settings are le v el 0 for all maskable interrupts. interrupt requests are not accepted by the s1c17 core if the le v el is 0. t h e i t c i n c l u d e s c o n t r o l b i t s f o r s e l e c t i n g t h e i n t e r r u p t l e v e l , a n d t h e l e v e l c a n b e s e t t o b e t w e e n 0 ( l o w ) a n d 7 ( h i g h ) interrupt le v els for each interrupt type. if interrupt requests are input to the itc simultaneously from tw o or more peripheral modules, the itc outputs the interrupt request with the highest priority to the s1c17 core in accordance with the follo wing conditions. 1. the interrupt with the highest interrupt le v el tak es precedence. 2. if multiple interrupt requests are input with the s ame interrupt le v el, the interrupt with the lo west v ector number tak es precedence. the other interrupts occurring at the same time are held until all interrupts with higher priority le v els ha v e been ac- cepted by the s1c17 core. if an interrupt cause with higher priority occurs while the itc is outputting an interrupt request signal to the s1c17 core (before being accepted by the s1c17 core), the itc alters the v ector number and interrupt le v el signals to the setting information on the more recent interrupt. the pre viously occurring interrupt is held. the held interrupt is canceled and no interrupt is generated if the interrupt flag in the peripheral module is reset with softw are.
6 interr upt contr oller (itc) 6-4 seiko epson corporation s1c17651 t echnical m anual 3.2.1 interr upt le v el setting bits t ab le 6. har d ware interrupt interrupt le vel setting bits register ad dress p0 por t interr upt il v0[2:0] (d[2:0]/itc_l v0 register) 0x4306 cloc k timer interr upt il v3[2:0] (d[10:8]/itc_l v1 register) 0x4308 r tc interr upt il v4[2:0] (d[2:0]/itc_l v2 register) 0x430a lcd interr upt il v6[2:0] (d[2:0]/itc_l v3 register) 0x430c 16-bit pwm timer ch.0 interr upt il v7[2:0] (d[10:8]/itc_l v3 register) 0x430c 8-bit timer ch.0 interr upt il v10 [2:0] (d[2:0]/itc_l v5 register) 0x4310 u ar t ch.0 interr upt il v12[2:0] (d[2:0]/itc_l v6 register) 0x4312 spi ch.0 interr upt il v14[2:0] (d[2:0]/itc_l v7 register) 0x4314 interrupt pr ocessing b y the s1c17 core 6.3.3 a maskable interrupt to the s1c17 core occurs when all of the follo wing conditions are met: ? the interrupt is enabled by the interrupt control bit inside the peripheral module. ? the ie (interrup t enable) bit of the psr (processor status re gister) in the s1c17 core has been set to 1. ? the cause of interrupt that has occurred has a higher interrupt le v el than the v alue set in the il f ield of the psr. ? no other cause of interrupt ha ving higher priority , such as nmi, has occurred. i f a n i n t e r r u p t c a u s e t h a t h a s b e e n e n a b l e d i n t h e p e r i p h e r a l m o d u l e o c c u r s , t h e c o r r e s p o n d i n g i n t e r r u p t f l a g i s s e t t o 1 , and this state is maintained until it is reset by the program. this means that the interrupt cause is not cleared e v en if the conditions listed abo v e are not met when the interrupt cause occurs. an interrupt occurs if the abo v e conditions are met. if multiple maskable interrupt causes occurs simultaneously , the interrupt cause with the highest interrupt le v el and lo west v ector number be comes the subject of the interrupt request to the s1c17 core. interrupts with lo wer le v els are held until the abo v e conditions are subsequently met. t h e s1c17 c o r e s a m p l e s i n t e r r u p t r e q u e s t s f o r e a c h c y c l e . o n a c c e p t i n g a n i n t e r r u p t r e q u e s t , t h e s1c17 c o r e switches to interrupt processing immediately after e x ecution of the current instruction has been completed. interrupt processing in v olv es the fol lo wing steps: (1) the psr and current program counter (pc) v alues are sa v ed to the stack. (2) the psr ie bit is reset to 0 (disabling subsequent maskable interrupts). (3) the psr il bits are set to the recei v ed interrupt le v el. (the nmi does not af fect the il bits.) (4) the v ector for the interrupt occurred is loaded to the pc to e x ecute the interrupt handler routine. when an interrupt is accepted, (2) pre v ents subsequent maskable interrupts. setting the ie bit to 1 in the interrupt handler routine allo ws handling of multiple interrupts. in this case, since il is changed by (3), only an interrupt with a higher le v el than that of the currently processed interrupt will be accepted. ending interrupt handler routines using the reti instruction returns the psr to the state before the interrupt has occur red. the program resumes processing follo wing the instruction being e x ecuted at the time the interrupt oc- curred. nmi 6.4 i n t h e s 1 c 1 7 6 5 1 , t h e w a t c h d o g t i m e r c a n g e n e r a t e a n o n - m a s k a b l e i n t e r r u p t ( n m i ) . t h e v e c t o r n u m b e r f o r n m i i s 2 , with the v ector address set to the v ector table's starting address + 8 bytes. this interrupt tak es precedence o v er other interrupts and is unconditionally accepted by the s1c17 core. f or detailed information on generating nmi, see the w atchdog t imer (wdt) chapter . software interrupts 6.5 the s1c17 core pro vides the int imm5 and intl imm5,imm3 instructions allo wing the softw are to gener - ate an y interrupts. the operand imm5 specif ies a v ector number (0C31) in the v ector table. in addition to this, the intl instruction has the operand imm3 to specify the interrupt le v el (0C7) to b e set to the il f ield in the psr. the processor performs the same interrupt processing as that of the hardw are interrupt.
6 interr upt contr oller (itc) s1c17651 t echnical m anual seiko epson corporation 6-5 hal t and sleep mode cancellation 6.6 hal t and sleep modes are cleared by the follo wing signals, which start the cpu. ? interrupt request signal sent to the cpu from the itc ? nmi signal output by the w atchdog timer ? deb ug interrupt signal ? reset signal notes: ? if the cpu is ab le to receiv e interr upts when hal t or sleep mode has been cleared b y an interr upt request f or the cpu from the itc , processing br anches to the interr upt handler rou- tine immediately after cancellation. in all other cases , the prog r am is e x ecuted f ollo wing the halt or slp instr uction. ? hal t or sleep mode clear ing due to interr upt requests cannot be mask ed (prohibited) using itc interr upt le v el settings . f or more information, see po wer sa ving by clock control in the appendix chapter . f or the oscillator circuit and system clock s tatuses after hal t or sleep mode is canceled, see the clock generator (clg) chapter . contr ol register details 6.7 7.1 list of itc registers t ab le 6. ad dress register name function 0x4306 itc_l v0 interr upt le v el setup register 0 sets the p0 interr upt le v el. 0x4308 itc_l v1 interr upt le v el setup register 1 sets the ct interr upt le v el. 0x430a itc_l v2 interr upt le v el setup register 2 sets the r tc interr upt le v el. 0x430c itc_l v3 interr upt le v el setup register 3 sets the lcd and t16a2 ch.0 interr upt le v els . 0x4310 itc_l v5 interr upt le v el setup register 5 sets the t8 ch.0 interr upt le v el. 0x4312 itc_l v6 interr upt le v el setup register 6 sets the u ar t ch.0 interr upt le v el. 0x4314 itc_l v7 interr upt le v el setup register 7 sets the spi ch.0 interr upt le v el. note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. interrupt level setup register x (itc_lvx) register name ad dress bit name function setting init. r/w remarks interrupt level setup register x (itc_lv x ) 0x4306 | 0x4314 (16 bits) d15C11 C reser v ed C C C 0 when being read. d10C8 i lv n[2:0] intn (1, 3, ... 7) interr upt le v el 0 to 7 0x0 r/w d7C3 C reser v ed C C C 0 when being read. d2C0 i lv n[2:0] intn (0, 2, ... 14) interr upt le v el 0 to 7 0x0 r/w d[15:11], d[7:3] reserved d[10:8], d[2:0] ilv n [2:0]: intn interrupt level bits (n = 0C14) sets the interrupt le v el (0 to 7) of each interrupt. (def ault: 0x0) the s1c17 core does not accept interrupts with a le v el set lo wer than the psr il v alue. the itc uses the interrupt le v el when multi ple interrupt requests occur simultaneously . i f m u l t i p l e i n t e r r u p t r e q u e s t s e n a b l e d b y t h e i n t e r r u p t e n a b l e b i t o c c u r s i m u l t a n e o u s l y , t h e i t c s e n d s t h e interrupt request with the highest le v el set by the itc_l vx re gisters (0x4306 to 0x4314) to the s1c17 core. if multiple interrupt requests with the same interrupt le v el occur simultaneously , the interrupt with the lo west v ector number is processed f irst. the other interrupts are held until all interrupts of higher priority ha v e been accepted by the s1c17 core.
6 interr upt contr oller (itc) 6-6 seiko epson corporation s1c17651 t echnical m anual if an interrupt requests of higher priority occurs while the itc outputs an interrupt request signal to the s1c17 core (before acceptance by the s1c17 core), the itc alters the v ector number and interrupt le v el signals to the setting details of the most recent interrupt. the immediately preceding interrupt is held. 7.2 interr upt le v el bits t ab le 6. register bit interrupt itc_l v0(0x4306) il v0[2:0] (d[2:0]) p0 por t interr upt (il v1[2:0] (d[10:8])) reser v ed itc_l v1(0x4308) (il v2[2:0] (d[2:0])) reser v ed il v3[2:0] (d[10:8]) cloc k timer interr upt itc_l v2(0x430a) il v4[2:0] (d[2:0]) r tc interr upt (il v5[2:0] (d[10:8])) reser v ed itc_l v3(0x430c) il v6[2:0] (d[2:0]) lcd interr upt il v7[2:0] (d[10:8]) 16-bit pwm timer ch.0 interr upt itc_l v5(0x4310) il v10[2:0] (d[2:0]) 8-bit timer c h.0 interr upt (il v11[2:0] (d[10:8])) reser v ed itc_l v6(0x4312) il v12[2:0] (d[2:0]) u ar t ch.0 interr upt (il v13[2:0] (d[10:8])) reser v ed itc_l v7(0x4314) il v14[2:0] (d[2:0]) spi ch.0 interr upt (il v15[2:0] (d[10:8])) reser v ed
7 clock genera t or (clg) s1c17651 t echnical m anual seiko epson corporation 7-1 clock generator (clg) 7 clg module over vie w 7.1 the clock generator (clg) controls the internal oscillators and the system clocks to be supplied to the s1c17 core, on-chip peripheral modules, and e xternal de vices. the features of the clg module are listed belo w . ? generates the operating clocks with the b uilt-in oscillators. - osc3b oscillator circuit: 2 mhz/1 mhz/500 khz (typ.) internal oscillator circuit - osc3a oscillator circuit: 4.2 mhz (max.) crystal or ceramic oscillator circuit - osc1b oscillator circuit: 32 khz (typ.) internal oscillator circuit - osc1a oscillator circuit: 32.768 khz (typ.) crystal oscillator circuit ? switches the system clock. the system clock source can be selected from osc3b, osc3a, and osc1 via soft- w are. ? generates the cpu core clock (cclk) and controls the clo ck supply to the core block. the cclk frequenc y can be selected from system clock 1/1, 1/2, 1/4, and 1/8. ? controls the clock supply to the peripheral modules. ? t urns the clocks on and of f according to the cpu operating status (r un, hal t , or sleep). ? supports quick-restart processing from sleep mode. t urns osc3b on forcibly and switches the system clock to osc3b when sleep mode is canceled. ? con trols tw o clock outputs to e xternal de vices. figure 7.1.1 sho ws the clock system and clg module conf iguration. cclk fouta output circuit osc3a oscillator (4.2 mhz max.) osc3b oscillator (0.5/1/2 mhz) clock gear (1/1C1/8) osc controller gate s1c17 core osc3 osc4 system clock theoretical regulation rtc reset osc1 dividing signals osc3a osc1a osc1b osc1 osc3b osc1 fouta foutb output circuit foutb osc1a oscillator (32.768 khz) osc1b oscillator (32 khz) osc1 osc2 sleep, wakeup clg t8, itc, spi, p, misc, vd1 pclk t16a2 gate lcd, uart, snd osc3a divider osc3b divider osc1a divider osc1b divider 256 hz rtc ct, wdt halt gate sleep 1.1 clg module configur ation figure 7. t o reduce current consumption, control the clock in conjunction with processing and use hal t and sleep modes. f or more information on reducing current consumption, see po wer sa ving in the appendix chapter .
7 clock genera t or (clg) 7-2 seiko epson corporation s1c17651 t echnical m anual clg input/output pins 7.2 t able 7.2.1 lists the input/output pins for the clg module. 2.1 list of clg pins t ab le 7. pin name i/o qty function osc1 i 1 osc1a oscillator input pin connect a cr ystal resonator (32.768 khz) and a gate capacitor . osc2 o 1 osc1a oscillator output pin connect a cr ystal resonator (32.768 khz). osc3 i 1 osc3a oscillator input pin connect a cr ystal or cer amic resonator (max. 4.2 mhz), and a gate capacitor . osc4 o 1 osc3a oscillator output pin connect a cr ystal or cer amic resonator (max. 4.2 mhz), and a dr ain ca pacitor . fout a o 1 fout a cloc k output pin outputs a divided osc3b , osc3a, or osc1 cloc k. foutb o 1 foutb cloc k output pin outputs a divided osc3b , osc3a, or osc1 cloc k. the clg output pins (fout a, foutb) are shared with i/o ports and are initially set as general purpose i/o port pins. the pin functions must be switched using the port function select bits to use the general purpose i/o port pins as the clg ou tput pins. f or detailed information on pin function switching, see the i/o ports (p) chapter . oscillator s 7.3 the clg module contains four internal oscillator circuits (osc3b, osc3a, osc1b, and osc1a). the osc3b and osc3a oscillators generate the main clock for high-speed operation of the s1c17 core and peripheral circuits. the osc1b or osc1a oscillator generates a sub-clock for timers and lo w-po wer operations. the osc3b clock is selected as the system clock after an initial reset. oscillator on/of f switching and system clock selection (from osc3b, osc3a, and osc1) are controlled with softw are. either the osc1b or osc1a oscillator can be selected as the osc1 clock source. osc3b oscillator 7.3.1 t h e o s c3b o s c i l l a t o r i n i t i a t e s h i g h - s p e e d o s c i l l a t i o n w i t h o u t e x t e r n a l c o m p o n e n t s . i t i n i t i a t e s o s c i l l a t i o n w h e n po wer is turned on. the s1c17 core and peripheral circuits operate with this oscillation clock after an initial reset. f osc3b clock generator oscillation stabilization wait circuit osc3ben osc3bwt[1:0] sleep/normal osc3bfsel[1:0] 3.1.1 osc3b oscillator circuit figure 7. osc3b oscillation frequenc y selection t h e o s c3b o s c i l l a t i o n f r e q u e n c y c a n b e s e l e c t e d f r o m t h r e e t y p e s s h o w n b e l o w u s i n g o s c3b f s e l [1:0] / clg_src re gister . 3.1.1 osc3b oscillation f requency setting t ab le 7. osc3bfsel[1:0] osc3b oscillation frequenc y (typ.) 0x3 reser v ed 0x2 500 khz 0x1 1 mhz 0x0 2 mhz (def ault: 0x0)
7 clock genera t or (clg) s1c17651 t echnical m anual seiko epson corporation 7-3 osc3b oscillation on/off the osc3b oscillator stops oscillating when osc3ben/clg_ctl re gister is set to 0 and starts oscillating when set to 1. the osc3b oscillator stops oscillating in sleep mode. after an initial reset, osc3ben is set to 1, and the osc3b oscillator goes on. since the osc3b clock is used as the system clock, the s1c17 core starts operating using the osc3b clock. stabilization wait time at star t of osc3b oscillation t h e o s c3b o s c i l l a t o r c i r c u i t i n c l u d e s a n o s c i l l a t i o n s t a b i l i z a t i o n w a i t c i r c u i t t o p r e v e n t m a l f u n c t i o n s d u e t o u n s t a b l e c l o c k o p e r a t i o n s a t t h e s t a r t o f o s c3b o s c i l l a t i o n e . g . , w h e n t h e o s c3b o s c i l l a t o r i s t u r n e d on with softw are. figure 7.3.1.2 sho ws the relationship between the oscillation start time and the oscillation stabilization w ait time. oscillation enab le bit (osc3ben/osc3aen/osc1en) oscillation wave fo rm digitiz ed oscillation wave fo rm oscillator output cloc k (f osc3b /f osc3a /f osc1b /f osc1a ) system supply w ait time oscillation star t time oscillation stabilization w ait time 3.1.2 oscillation star t time and oscillation stabilization w ait time figure 7. the osc3b clock is not supplied to the system until the time set for this circuit has elapsed. use osc3bwt[1:0]/clg_w ait re gister to select one of four oscillation stabilization w ait times. 3.1.2 osc3b oscillation stabilization w ait time settings t ab le 7. osc3bwt[1:0] oscillation stabilization wait time 0x3 8 cycles 0x2 16 cycles 0x1 32 cycles 0x0 64 cycles (def ault: 0x0) this is set to 64 c ycles (osc3b clock) after an initial reset. this means the cpu can start operating when the cpu operation start time at initial reset indicated belo w (at a maximum) has elapsed after the reset state is can- celed. f or the oscillation start time, see the electrical charact eristics chapter . cpu oper ation star t time at initial reset osc3b oscillation star t time (max.) + osc3b oscillation stabili- zation w ait time (64 cycles) when the system clock is switched to osc3b immediately after turning the osc3b oscillator on, the osc3b clock is supplied to the system after the osc3b clock system supply w ait time indicated belo w (at a maximum) has elapsed. if the po wer suppl y v oltage v dd has stabilized suf f iciently , osc3bwt[1:0] can be set to 0x3 to reduce the oscillation stabilization w ait time. osc3b cloc k system supply w ait time osc3b oscillation star t time (max.) + osc3b oscillation stabi- lization w ait time
7 clock genera t or (clg) 7-4 seiko epson corporation s1c17651 t echnical m anual osc3a oscillator 7.3.2 the osc3a oscillator is a high-precision, high-speed oscillator circuit that uses either a crystal resonator or a ceramic resonator . it can be switched for use with the osc3b oscillator . figure 7.3.2.1 sho ws the osc3a oscillator conf igura- tion. osc3awt[1:0] f osc3a osc3aen oscillation stabilization wait circuit v ss osc4 osc3 r f r d c d3 c g3 x'tal3 or ceramic sleep/normal 3.2.1 osc3a oscillator circuit figure 7. a cr ys ta l re so na to r (x ta l3) or ce ra mi c re so na to r (c er am ic ) sh ou ld be co nn ec te d be tw ee n th e os c3 an d os c4 pins. additionally , tw o capacitors (c g3 and c d3 ) should be connected between the osc3/osc4 pins and v ss . f or the ef fecti v e frequenc y range and oscillation characteristics, see the electrical characteristics chapter . osc3a oscillation on/off the osc3a osc illator circuit starts oscillating when osc3aen/clg_ctl re gister is set to 1 and stops oscil- lating when set to 0. the osc3a oscillator circuit stops oscillating in sleep mode. after an initial reset, osc3aen is set to 0, and the osc3a oscillator circuit is halted. stabilization wait time at star t of osc3a oscillation t h e o s c3a o s c i l l a t o r c i r c u i t i n c l u d e s a n o s c i l l a t i o n s t a b i l i z a t i o n w a i t c i r c u i t t o p r e v e n t m a l f u n c t i o n s d u e t o unstable clock operations at the start of osc3a oscillatione.g., when the osc3a oscillator is turned on with softw are. the osc3a clock is not supplied to the system until the time set for this circuit has elapsed. use os- c3a wt[1:0]/clg_w ait re gister to select one of four oscillation stabilization w ait times. f or the oscillation start time, see the electrical charac teristics chapter . 3.2.1 osc3a oscillation stabilization w ait time settings t ab le 7. osc3a wt[1:0] oscillation stabilization wait time 0x3 128 cycles 0x2 256 cycles 0x1 512 cycles 0x0 1024 cycles (def ault: 0x0) this is set to 1,024 c ycles (osc3a clock) after an initial reset. when the system clock is switched to osc3a immediately after the osc3a oscillator circuit is turned on, the osc3a clock is supplied to the system after the osc3a clock system supply w ait time indicated belo w (at a maxim um) has elapsed. f or the oscillation start time, see the electrical characteristics chapter . osc3a cloc k system supply w ait time osc3a oscillation star t time (max.) + osc3a oscillation stabilization w ait time note: o s c i l l a t i o n s t a b i l i t y w i l l v a r y , d e p e n d i n g o n t h e r e s o n a t o r a n d o t h e r e x t e r n a l c o m p o n e n t s . c a r e f u l l y consider the osc3a oscillation stabilization w ait time bef ore reducing the time . osc1 oscillator 7.3.3 the s1c17651 has tw o lo w-speed oscillator circuits (osc1a and osc1b) and either one can be selected as the osc1 oscillator . t h e o s c1 c l o c k i s g e n e r a l l y u s e d a s t h e t i m e r o p e r a t i o n c l o c k ( f o r t h e r e a l - t i m e c l o c k , c l o c k t i m e r , w a t c h d o g timer , and 16-bit pwm timer) and an operation clock for the u ar t , sound generator , and lcd dri v er . it can be used as the system clock instead of the osc3b or osc3a clock to reduce po wer consumption when no high-speed processing is required.
7 clock genera t or (clg) s1c17651 t echnical m anual seiko epson corporation 7-5 system clock to osc1 peripheral modules f osc1a f osc1b osc1a oscillator (32.768 khz) osc1b oscillator (32 khz) osc1 osc2 osc1a divider osc1b divider osc1sel osc1en theoretical regulation rtc reset 3.3.1 osc1 oscillator configur ation figure 7. osc1a oscillator the osc1a oscillator is a high-precision, lo w-speed oscillator circuit that uses a 32.768 khz crystal resonator . figure 7.3.3.2 sho ws the osc1a oscillator conf iguration. v ss f osc1a osc1en rtcrun oscillation stabilization wait circuit r d c d sleep/normal osc1awt[1:0] r f v ss c g v ss osc2 osc1 x'tal1 c g1 c d1 3.3.2 osc1a oscillator circuit figure 7. a c r y s t a l r e s o n a t o r ( x t a l 1 , t y p . 3 2 . 7 6 8 k h z ) s h o u l d b e c o n n e c t e d b e t w e e n t h e o s c 1 a n d o s c 2 p i n s . a d d i t i o n - ally , tw o capacitors (c g1 and c d1 ) should be connected between the osc1/osc2 pins and v ss . note: the osc1a divider output cloc k ma y be adjusted f or frequency correction b y the theoretical regu- lation function. also the divider is reset b y star ing the r tc . these oper ation modifies the 256 hz output cloc k cycle at that point, and this aff ects the count cycle of the timers that use the 256 hz cloc k (ct , wdt , t16a2). osc1b oscillator the osc1b oscillator generates about 32 khz clock without e xternal components. clock generator oscillation stabilization wait circuit osc1bwt[1:0] f osc1b osc1en rtcrun sleep/normal 3.3.3 osc1b oscillator circuit figure 7. osc1a/osc1b oscillator selection either osc1a or osc1b can be selected as the osc1 oscillator using osc1sel/clg_src re gister . when osc1sel is 1 (def ault), osc1b is selected. setting osc1sel to 0 selects osc1a. the osc1 oscillation con- trol bits are ef fecti v e only for the oscillator selected here. osc1 oscillation on/off the osc1 oscillator starts oscillating when osc1en/clg_ctl re gister is set to 1 and stops oscillating when set to 0.
7 clock genera t or (clg) 7-6 seiko epson corporation s1c17651 t echnical m anual when r tcr un and osc1en are both set to 1, the osc1 oscillator continues operating if the system enters sleep mode. when r tcr un = 0, the osc1 stops in sleep mode re g ardless of ho w osc1en is set. after an initial reset, osc1en and r tcr un are both set to 0, and the osc1 oscillator circuit is halted. 3.3.1 osc1 oscillator oper ating status (nor mal oper ation) t ab le 7. osc1en r tcr un osc1 oscillator 1 1 on 1 0 on 0 1 off 0 0 off 3.3.2 osc1 oscillator oper ating status (sleep mode) t ab le 7. osc1en r tcr un osc1 oscillator 1 1 on 1 0 off 0 1 off 0 0 off stabilization wait time at star t of osc1 oscillation t h e o s c 1 o s c i l l a t o r c i r c u i t i n c l u d e s a n o s c i l l a t i o n s t a b i l i z a t i o n w a i t c i r c u i t t o p r e v e n t m a l f u n c t i o n s d u e t o u n s t a - ble clock operations at the start of osc1 oscillatione.g., when the osc1 oscillator is turned on with softw are. the osc1 clock is not supplied to the system until the time set for this circuit has elapsed. use osc1a wt[1:0]/ c l g _ w a i t r e g i s t e r t o s e l e c t o n e o f f o u r o s c1a o s c i l l a t i o n s t a b i l i z a t i o n w a i t t i m e s . u s e o s c1b w t [1:0] / clg_w ait re gister for osc1b. f or the oscillation start time, see the electrical characteristics chapter . 3.3.3 osc1a oscillation stabilization w ait time settings t ab le 7. osc1a wt[1:0] oscillation stabilization wait time 0x3 2048 cycles 0x2 4096 cycles 0x1 8192 cycles 0x0 16384 cycles (def ault: 0x0) 3.3.4 osc1b oscillation stabilization w ait time settings t ab le 7. osc1bwt[1:0] oscillation stabilization wait time 0x3 8 cycles 0x2 16 cycles 0x1 32 cycles 0x0 64 cycles (def ault: 0x0) this is set to 16384 c ycles (osc1 clock) when osc1a is selected or 64 c ycles when osc1b is selected after an initial reset. when the system clock is switched to osc1 immediately after the osc1 oscillator circuit is turned on, the osc1 clock is supplied to the system after the osc1 clock sys tem supply w ait time indicated belo w (at a maxi- mum) has elapsed. f or the oscillation start time, see the electrical characteristics chapter . osc1 cloc k system supply w ait time osc1 oscillation star t time (max.) + osc1 oscillation sta- bilization w ait time notes: ? o s c i l l a t i o n s t a b i l i t y w i l l v a r y , d e p e n d i n g o n t h e r e s o n a t o r a n d o t h e r e x t e r n a l c o m p o n e n t s . carefully consider the osc1a oscillation stabi lization w ait time bef ore reducing the time . ? be sure to a v oid tur ning the osc1a or osc1b oscillator off f or at least f our seconds from s t a r t o f o s c i l l a t i o n a f t e r t h e o s c i l l a t o r i s t u r n e d o n . f o r t h e o s c i l l a t i o n s t a r t t i m e , s e e t h e e l e c t r i c a l char acter istics chapter . ? t h e o s c 1 b o s c i l l a t i o n f r e q u e n c y w i l l b e h i g h e r t h a n t h e v a l u e t h a t i s d e s c r i b e d i n t h e e l e c t r i c a l char acter istics chapter f o r about 3 ms immediately after tur ning the osc1b oscillator on.
7 clock genera t or (clg) s1c17651 t echnical m anual seiko epson corporation 7-7 system cloc k switc hing 7.4 the f igure belo w sho ws the system clock selector . system clock osc3b osc3a osc1 clksrc[1:0] 4.1 system cloc k selector figure 7. the s1c17651 has three system clock sources (osc3b, osc3a, and osc1) and it start operating with the osc3b clock after an initial reset. the system clock can be switched to the osc3a clock when a high-speed clock is re- quired for the processing, or to the osc1 clock for po wer sa ving. use clksrc[1:0]/clg_src re gister for this switching. oscillator circuits other t han those selected as the system clock source and not used for running periph- eral circuits can be shut do wn to reduce current consumption. 4.1 system cloc k selection t ab le 7. clksrc[1:0] system c loc k sour ce 0x3 reser v ed 0x2 osc3a 0x1 osc1 0x0 osc3b (def ault: 0x0) the follo wing sho ws system clock switching procedures: switc hing the system c loc k to osc3a fr om osc3b or osc1 1. set the osc3a oscillation stabilization w ait time if necessary . (osc3a wt[1:0]) 2. t urn the osc3a oscillator on if it is of f. (osc3aen = 1) 3. select the osc3a clock as the system clock. (clksrc[1:0] = 0x2) 4. t urn the osc3b or osc1 oscillator of f if peripheral modules and fout a/b output circuits ha v e not used the osc3b or osc1 clock. switc hing the system c loc k to osc1 fr om osc3b or osc3a 1. s e t t h e o s c 1 a o r o s c 1 b o s c i l l a t i o n s t a b i l i z a t i o n w a i t t i m e i f n e c e s s a r y . ( o s c 1 a w t [ 1 : 0 ] / o s c 1 b w t [ 1 : 0 ] ) 2. t urn the osc1 oscillator on if it is of f. (osc1en = 1) 3. select the osc1 clock as the system clock. (clksrc[1:0] = 0x1) 4. t u r n t h e o s c 3 b o r o s c 3 a o s c i l l a t o r o f f i f p e r i p h e r a l m o d u l e s a n d f o u t a / b o u t p u t c i r c u i t s h a v e n o t u s e d the osc3b or osc3a clock. switc hing the system c loc k to osc3b fr om osc3a or osc1 1. set the osc3b oscillation stabilization w ait time if necessary . (osc3bwt[1:0]) 2. t urn the osc3b oscillator on if it is of f. (osc3ben = 1) 3. select the osc3b clock as the system clock. (clksrc[1:0] = 0x0) 4. t urn t he osc3a or osc1 oscillator of f if peripheral modules and fout a/b output circuits ha v e not used the osc3a or osc1 clock. notes: ? t h e o s c i l l a t o r t o b e u s e d a s t h e s y s t e m c l o c k s o u r c e m u s t b e o p e r a t e d b e f o r e s w i t c h i n g the system cloc k. otherwise , the clg will not s witch the system cloc k source , e v en if clk- src[1:0] is wr itten to , and the clksrc[1:0] v alue will remain unchanged. the tab le belo w lists th e combinations of cloc k oper ating status and register settings enab ling system cloc k selection. 4.2 system cloc k switching conditions t ab le 7. osc3ben osc3aen osc1en system c loc k 1 1 1 o s c 3 b , o s c 3 a , o r o s c 1 1 1 0 osc3b or osc3a 1 0 1 osc3b or osc1 0 1 1 osc3a or osc1 ? the oscillator circuit selected as the system cloc k source cannot be tur ned off .
7 clock genera t or (clg) 7-8 seiko epson corporation s1c17651 t echnical m anual ? contin uous wr ite/read access to clksrc[1:0] is prohibited. at least one instr uction unrelated to clksrc[1:0] access m ust be inser ted betw een the wr ite and read instr uctions . ? when sleep mode is canceled, the osc3b oscillator circuit is tur ned on (osc3ben = 1) and is used as the system cloc k source (clksrc[1:0] = 0x0) regardless of the system cloc k configured bef ore the chip entered sleep mode . canceling hal t mode does not change the cloc k status configured bef ore the chip entered hal t mode . cpu core cloc k (cclk) contr ol 7.5 the clg module includes a clock gear to slo w do wn the system clock to send to the s1c17 core. t o reduce cur - rent consumption, operate the s1c17 core with the slo west possible clock speed. the halt instruction can be e x- ecuted to stop the clock supply from the clg to t he s1c17 core for po wer sa vings. osc3b osc3a osc1 cclk clock gear (1/1C1/8) gate s1c17 core gear selection system clock halt 5.1 cclk supply system figure 7. cloc k g ear settings cclkgr[1:0]/clg_cclk re gister is used to select the gear ratio to reduce system clock speeds. 5.1 cclk gear ratio selection t ab le 7. cclkgr[1:0] gear ratio 0x3 1/8 0x2 1/4 0x1 1/2 0x0 1/1 (def ault: 0x0) cloc k suppl y contr ol t h e c c l k c l o c k s u p p l y i s s t o p p e d b y e x e c u t i n g t h e halt i n s t r u c t i o n . s i n c e t h i s d o e s n o t s t o p t h e s y s t e m clock, peripheral modules will continue to operate. hal t mode is cleared by resetting, nmi, or other interrupts. the cclk supply resumes when hal t mode is cleared. ex ecuting the slp instruction suspends system clock suppl y to the clg, thereby halting the cclk supply as well. clearing sleep mode with an e xternal interrupt restarts the system clock supply and the cclk supply . p eripheral module cloc k (pclk) contr ol 7.6 the clg module also controls the clock supply to peripheral modules. the system clock is used unmodif ied for the peripheral module clock (pclk). internal peripheral modules gate on/off control pclk system clock osc3b osc3a osc1 6.1 p er ipher al module cloc k control circuit figure 7. cloc k suppl y contr ol pclk supply is controlled by pcken[1:0]/clg_pclk re gister .
7 clock genera t or (clg) s1c17651 t echnical m anual seiko epson corporation 7-9 6.1 pclk control t ab le 7. pcken[1:0] pclk suppl y 0x3 enab led (on) 0x2 setting prohibited 0x1 setting prohibited 0x0 disab led (off) (def ault: 0x3) the def ault setting is 0x3, which enables the clock supply . stop the clock supply to reduce current consumption unless all peripheral modules (modules listed belo w) within the internal peripheral circuit area need to be run- ning. note: do not set pcken[1:0]/clg_pclk register to 0x2 or 0x1, sin ce doing so will stop the oper ation of cer tain per ipher al modules . 6.2 p er ipher al modules and oper ating cloc ks t ab le 7. p eripheral modules operating c loc k remarks interr upt controller pclk the pclk supply cannot be disab led if one or more per ipher al modules in these list m ust be oper ated. the pclk supply can be disab led if all the per iph- er al circuits in these list can be stopped. 8-bit timer spi p o w er gener ator p por t & por t mux misc registers real-time cloc k divided osc1 cloc k t h e o s c1 o s c i l l a t o r c i r c u i t c a n n o t b e d i s a b l e d i f o n e o r m o r e p e r i p h e r a l m o d u l e s i n t h e s e l i s t m u s t be oper ated. the pclk supply can be disab led. cloc k timer w atchdog timer lcd dr iv er cloc k selected b y softw are (divided osc3b/osc3a/ osc1 cloc k) the oscillator circuit used as the cloc k source can- not be disab led (see section 7.7 or each per ipher al module chapter). the pclk supply can be disab led. sound gener ator 16-bit pwm timer u ar t fout a/foutb outputs clo c k external output (fout a, foutb) 7.7 di vided osc3b, osc3a, or osc1 clocks can be output to e xternal de vices. i/o port (fouta pin) divider (1/1C1/128) osc3a clock fouta output circuit on/off control clock source selection on/off control clock source selection fouta division ratio selection foutb division ratio selection divider (1/1C1/128) osc3b clock divider (1/1C1/128) osc1 clock i/o port (foutb pin) foutb output circuit 7.1 cloc k output circuit figure 7. there are tw o output systems a v ailable: fout a and foutb. the fout a and foutb output circuits ha v e the same functions.
7 clock genera t or (clg) 7-10 seiko epson corporation s1c17651 t echnical m anual output pin setting the fout a and foutb output pins are shared with i/o ports. the pin is conf igured for the i/o port by de- f ault, so the pin function should be changed using the port function select bit before the clock output can be used. see the i/o ports (p) chapter for the fout a/foutb pins and selecting pin functions. cloc k sour ce selection the clock source can be selected from osc3b, osc3a, and osc1 using fout asrc[1:0]/clg_fout a re g- ister or foutbsrc[1:0]/clg_foutb re gister . 7.1 cloc k source selection t ab le 7. fout asrc[1:0]/foutbsrc[1:0] cloc k sour ce 0x3 reser v ed 0x2 osc3a 0x1 osc1 0x0 osc3b (def ault: 0x0) cloc k frequenc y selection eight dif ferent clock output frequencies can be selected. select the di vision ratio for the source clock using fout ad[2:0]/clg_fout a re gister or foutbd[2:0]/clg_foutb re gister . 7.2 cloc k division ratio selection t ab le 7. fout ad[2:0]/foutbd[2:0] division ratio 0x7 1/128 0x6 1/64 0x5 1/32 0x4 1/16 0x3 1/8 0x2 1/4 0x1 1/2 0x0 1/1 (def ault: 0x0) cloc k output contr ol the clock output is controlled using fout ae/clg_fout a re gister or foutbe/clg_foutb re gister . set- ting fout ae/foutbe to 1 outputs the fout a/foutb clock from the fout a/foutb pin. setting it to 0 disables output. foutae (foutbe) fouta (foutb) output 00 1 7.2 fout a/foutb output figure 7. notes: ? since the fout a/foutb signal is not synchroniz ed with fout ae/foutbe wr iting, s witching output on or off will gener ate cer tain hazards . ? there ma y be a time lag betw een setting fout ae/foutbe to 1 and star t of fout a/foutb signal output due to the oscillation stabilization w ait time and other conditions . contr ol register details 7.8 8.1 list of clg registers t ab le 7. ad dress register name function 0x5060 clg_src cloc k source select register selects the cloc k source . 0x5061 clg_ctl oscillation control register controls oscillation. 0x5064 clg_fout a fout a control register controls fout a cloc k output. 0x5065 clg_foutb foutb control register controls foutb cloc k output. 0x507d clg_w ait oscillation stabilization w ait control register controls oscillation stabilization w aiting time . 0x508 0 clg_pclk pclk control register controls the pclk supply . 0x5081 clg_cclk cclk control register configures the cclk division r atio .
7 clock genera t or (clg) s1c17651 t echnical m anual seiko epson corporation 7-11 the clg module re gisters are described in detail belo w . note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. clock source select register (clg_src) register name ad dress bit name function setting init. r/w remarks clock source select register (clg_src) 0x5060 (8 bits) d7C6 osc3b fsel[1:0] osc3b frequency select o s c 3 b f s e l [ 1 : 0 ] f requency 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed 500 khz 1 mhz 2 mhz d5 C reser v ed C C C 0 when being read. d4 osc1sel osc1 source select 1 osc1b 0 osc1a 1 r/w d3C2 C reser v ed C C C 0 when being read. d1C0 clksrc[1:0] system cloc k source select clksrc[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3a osc1 osc3b d[7:6] osc3bfsel[1:0]: osc3b frequency select bits selects the osc3b oscillation frequenc y . 8.2 osc3b oscillation f requency setting t ab le 7. osc3bfsel[1:0] osc3b oscillation frequenc y (typ.) 0x3 reser v ed 0x2 500 khz 0x1 1 mhz 0x0 2 mhz (def ault: 0x0) d5 reserved d4 osc1sel: osc1 source select bit selects the osc1 clock source. 1 (r/w): osc1b (def ault) 0 (r/w): osc1a d[3:2] reserved d[1:0] clksrc[1:0]: system clock source select bits selects the system clock source. 8.3 system cloc k selection t ab le 7. clksrc[1:0] system c loc k sour ce 0x3 reser v ed 0x2 osc3a 0x1 osc1 0x0 osc3b (def ault: 0x0) select osc3b or osc3a for normal (high-speed) operations. if no high-speed clock is required, osc1 can be set as the system clock and osc3b and osc3a stopped to reduce current consumption. notes: ? t h e o s c i l l a t o r t o b e u s e d a s t h e s y s t e m c l o c k s o u r c e m u s t b e o p e r a t e d b e f o r e s w i t c h i n g the system cloc k. otherwise , the clg will not s witch the system cloc k source , e v en if clk- src[1:0] is wr itten to , and the clksrc[1:0] v alue will remain unchanged. the tab le belo w lists the combinations of cloc k oper ating status and register settings en- ab ling system cloc k selection.
7 clock genera t or (clg) 7-12 seiko epson corporation s1c17651 t echnical m anual 8.4 system cloc k switching conditions t ab le 7. osc3ben osc3aen osc1en system c loc k 1 1 1 o s c 3 b , o s c 3 a , o r o s c 1 1 1 0 osc3b or osc3a 1 0 1 osc3b or osc1 0 1 1 osc3a or osc1 ? the oscillator circuit selected as the system cloc k source cannot be tur ned off . ? contin uous wr ite/read access to clksrc[1:0] is prohibited. at least one instr uction unre- lated to clksrc[1:0] access m ust be inser ted betw een the wr ite and read instr uctions . ? w h e n s l e e p m o d e i s c a n c e l e d , t h e o s c3b o s c i l l a t o r c i r c u i t i s t u r n e d o n ( o s c3b e n = 1) and is used as the system cloc k source (clksrc[1:0] = 0x0) regardless of the system cloc k configured bef ore the chip entered sleep mode . canceling hal t mode does not change the cloc k status configured bef ore the chip entered hal t mode . oscillation control register (clg_ctl) register name ad dress bit name function setting init. r/w remarks oscillation control register (clg_ctl) 0x5061 (8 bits) d7C3 C reser v ed C C C 0 when being read. d2 osc3ben osc3b enab le 1 enab le 0 disab le 1 r/w d1 osc1en osc1 enab le 1 enab le 0 disab le 0 r/w d0 osc3aen osc3a enab le 1 enab le 0 disab le 0 r/w d[7:3] reserved d2 osc3ben: osc3b enable bit enables or disables osc3b oscillator operations. 1 (r/w): enabled (on) (def ault) 0 (r/w): disabled (of f) note: the osc3b oscillator cannot be stopped if the osc3b clock is being used as the s y s t e m cloc k. d1 osc1en: osc1 enable bit enables or disables osc1 oscillator operations. 1 (r/w): enabled (on) 0 (r/w): disabled (of f) (def ault) notes: ? be sure to select the osc1 cloc k source (osc1a or osc1b) using osc1sel/clg_src register bef ore star ting osc1 oscillation. ? t h e o s c1 o s c i l l a t o r c a n n o t b e s t o p p e d i f t h e o s c1 c l o c k i s b e i n g u s e d a s t h e s y s t e m cloc k. d0 osc3aen: osc3a enable bit enables or disables osc3a oscillator operations. 1 (r/w): enabled (on) 0 (r/w): disabled (of f) (def ault) note: the osc3a oscillator cannot be stopped if the osc3a clock is being used as the system cloc k.
7 clock genera t or (clg) s1c17651 t echnical m anual seiko epson corporation 7-13 fouta control register (clg_fouta) register name ad dress bit name function setting init. r/w remarks fouta control register (clg_fouta ) 0x5064 (8 bits) d7 C reser v ed C C C 0 when being read. d6C4 foutad [2:0] fout a cloc k division r atio select fout ad[2:0] division r atio 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 d3C2 foutasrc [1:0] fout a cloc k source select fout asrc[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3a osc1 osc3b d1 C reser v ed C C C 0 when being read. d0 foutae fout a output enab le 1 enab le 0 disab le 0 r/w d7 reserved d[6:4] foutad[2:0]: fouta clock division ratio select bits selects the source clock di vision ratio to set the fout a clo ck frequenc y . 8.5 cloc k division ratio selection t ab le 7. fout ad[2:0] division ratio 0x7 1/128 0x6 1/64 0x5 1/32 0x4 1/16 0x3 1/8 0x2 1/4 0x1 1/2 0x0 1/1 (def ault: 0x0) d[3:2] foutasrc[1:0]: fouta clock source select bits selects the fout a clock source. 8.6 fout a cloc k source selection t ab le 7. fout asrc[1:0] cloc k sour ce 0x3 reser v ed 0x2 osc3a 0x1 osc1 0x0 osc3b (def ault: 0x0) d1 reserved d0 foutae: fouta output enable bit enables or disables fout a clock e xternal output. 1 (r/w): enabled (on) 0 (r/w): disabled (of f) (def ault) setting fout ae to 1 outputs the fout a clock from the fout a pin. setting it to 0 stops the output.
7 clock genera t or (clg) 7-14 seiko epson corporation s1c17651 t echnical m anual foutb control register (clg_foutb) register name ad dress bit name function setting init. r/w remarks foutb control register (clg_foutb ) 0x5065 (8 bits) d7 C reser v ed C C C 0 when being read. d6C4 foutbd [2:0] foutb cloc k division r atio select foutbd[2:0] division r atio 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 d3C2 foutbsrc [1:0] foutb cloc k source select foutbsrc[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3a osc1 osc3b d1 C reser v ed C C C 0 when being read. d0 foutbe foutb output enab le 1 enab le 0 disab le 0 r/w d7 reserved d[6:4] foutbd[2:0]: foutb clock division ratio select bits selects the source clock di vision ratio to set the foutb clo ck frequenc y . 8.7 cloc k division ratio selection t ab le 7. foutbd[2:0] division ratio 0x7 1/128 0x6 1/64 0x5 1/32 0x4 1/16 0x3 1/8 0x2 1/4 0x1 1/2 0x0 1/1 (def ault: 0x0) d[3:2] foutbsrc[1:0]: foutb clock source select bits selects the foutb clock source. 8.8 foutb cloc k source selection t ab le 7. foutbsrc[1:0] cloc k sour ce 0x3 reser v ed 0x2 osc3a 0x1 osc1 0x0 osc3b (def ault: 0x0) d1 reserved d0 foutbe: foutb output enable bit enables or disables foutb clock e xternal output. 1 (r/w): enabled (on) 0 (r/w): disabled (of f) (def ault) setting foutbe to 1 outputs the foutb clock from the foutb pin. setting it to 0 stops the output.
7 clock genera t or (clg) s1c17651 t echnical m anual seiko epson corporation 7-15 oscillation stabilization wait control register (clg_wait) register name ad dress bit name function setting init. r/w remarks oscillation stabilization wait control register (clg_wait) 0x507d (8 bits) d7C6 osc3bwt [1:0] osc3b stabilization w ait cycle select osc3bwt[1:0] w ait cycle 0x0 r/w 0x3 0x2 0x1 0x0 8 cycles 16 cycles 32 cycles 64 cycles d5C4 osc3awt [1:0] osc3a stabilization w ait cycle select osc3a wt[1:0] w ait cycle 0x0 r/w 0x3 0x2 0x1 0x0 128 cycles 256 cycles 512 cycles 1024 cycles d3C2 osc1bwt [1:0] osc1b stabilization w ait cycle select osc1bwt[1:0] w ait cycle 0x0 r/w 0x3 0x2 0x1 0x0 8 cycles 16 cycles 32 cycles 64 cycles d1C0 osc1awt [1:0] osc1a stabilization w ait cycle select osc1a wt[1:0] w ait cycle 0x0 r/w 0x3 0x2 0x1 0x0 2048 cycles 4096 cycles 8192 cycles 16384 cycles d[7:6] osc3bwt[1:0]: osc3b stabilization wait cycle select bits an oscillation stabilization w ait time is set to pre v ent malfunctions due to unstable clock operations at the start of osc3b oscillation. the osc3b clock is not supplied to the system immediately after osc3b oscillation starts until the time set here has elapsed. 8.9 osc3b oscillation stabilizat ion w ait time settings t ab le 7. osc3bwt[1:0] oscillation stabilization wait time 0x3 8 cycles 0x2 16 cycles 0x1 32 cycles 0x0 64 cycles (def ault: 0x0) this is set to 64 c ycles (osc3b clock) after an initial reset. this means the cpu can start operating when the cpu operation start time at initial reset indicated belo w (at a maximum) has elapsed after the reset state is canceled. cpu oper ation star t time at initial reset osc3b oscillati on star t time (max.) + osc3b oscillation stabilization w ait time (64 cycles) when the system clock is switched to osc3b immediately after turning the osc3b oscillator on, the osc3b clock is supplied to the system after the osc3b clock system supply w ait time indicated be- lo w (at a maximum) has elapsed. if the po wer supply v oltage v dd has stabilized suf f iciently , osc3b- wt[1:0] can be set to 0x3 to reduce the oscillation stabilization w ait time. osc3b cloc k system supply w ait time osc3b oscillation star t time (max.) + osc3b os- cillation stabilization w ait time d[5:4] osc3awt[1:0]: osc3a stabilization wait cycle select bits a n o s c i l l a t i o n s t a b i l i z a t i o n w a i t t i m e i s s e t t o p r e v e n t m a l f u n c t i o n s d u e t o u n s t a b l e c l o c k o p e r a t i o n at the start of osc3a oscillation. the osc3a clock is not supplied to the system immediately after osc3a oscillation starts until the time set here has elapsed. 8.10 osc3a oscillation stabilization w ait time settings t ab le 7. osc3a wt[1:0] oscillation stabilization wait time 0x3 128 cycles 0x2 256 cycles 0x1 512 cycles 0x0 1024 cycles (def ault: 0x0)
7 clock genera t or (clg) 7-16 seiko epson corporation s1c17651 t echnical m anual this is set to 1,024 c ycles (osc3a clock) after an initial reset. when the system clock is switched to osc3a immediately after the osc3a oscillator circuit is turned on, the osc3a clock is supplied to the system after the osc3a clock system supply w ait time indi- cated belo w (at a maximum) has elapsed. osc3a clock system supply wait time osc3a oscillation start time (max.) + osc3a os- cillation stabilization w ait time note: oscillation stability will vary, depending on the resonator and other external components. carefully consider the osc3a oscillation stabilization wait time before reducing the time. d[3:2] osc1bwt[1:0]: osc1b stabilization wait cycle select bits an oscillation stabilization w ait time is set to pre v ent malfunc tions due to unstable clock operation at the start of osc1b oscillation. the osc1 clock is not supplied to the system immediately after osc1b oscillation starts until the time set here has elapsed. 8.11 osc1b oscillation stabilization w ait time settings t ab le 7. osc1bwt[1:0] oscillation stabilization wait time 0x3 8 cycles 0x2 16 cycles 0x1 32 cycles 0x0 64 cycles (def ault: 0x0) this is set to 64 c ycles (osc1 clock) after an initial reset. when the system clock is switched to osc1 immediately after the osc1b oscillator circuit is turned on, the osc1 clock is supplied to the system after the osc1 clock system supply w ait time indicated belo w (at a maximum) has elaps ed. osc1 clock system supply wait time osc1b oscillation start time (max.) + osc1b oscil- lation stabilization w ait time d[1:0] osc1awt[1:0]: osc1a stabilization wait cycle select bits an oscillation stabilization w ait time is set to pre v ent malfunctions due to unstable clock operation at t h e s t a r t o f o s c 1 a o s c i l l a t i o n . t h e o s c 1 c l o c k i s n o t s u p p l i e d t o t h e s y s t e m i m m e d i a t e l y a f t e r o s c 1 a oscillation starts until the time set here has elapsed. 8.12 osc1a oscillation stabilization w ait time settings t ab le 7. osc1a wt[1:0] oscillation stabilization wait time 0x3 2048 cycles 0x2 4096 cycles 0x1 8192 cycles 0x0 16384 cycles (def ault: 0x0) this is set to 16384 c ycles (osc1 clock) after an initial reset. when the system clock is switched to osc1 immediately after the osc1a oscillator circuit is turned on, the osc1 clock is supplied to the system after the osc1 clock system supply w ait time indicated belo w (at a maxim um) has elapsed. osc1 clock system supply wait time osc1a oscillation start time (max.) + osc1a oscil- lation stabilization w ait time note: oscillation stability will vary, depending on the resonator and other external components. carefully consider the osc1a oscillation stabilization wait time before reducing the time.
7 clock genera t or (clg) s1c17651 t echnical m anual seiko epson corporation 7-17 pclk control register (clg_pclk) register name ad dress bit name function setting init. r/w remarks pclk control register (clg_pclk ) 0x5080 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 pcken[1:0] pclk enab le pcken[1:0] pclk supply 0x3 r/w 0x3 0x2 0x1 0x0 enab le not allo w ed not allo w ed disab le d[7:2] reserved d[1:0] pcken[1:0]: pclk enable bits enables or disables clock (pclk) supply to the internal peripheral modules. 8.13 pclk control t ab le 7. pcken[1:0] pclk suppl y 0x3 enab led (on) 0x2 setting prohibited 0x1 setting prohibited 0x0 disab led (off) (def ault: 0x3) the pcken[1:0] def ault setting is 0x3, which enables clock supply . p er ipher al modules that use pclk ? interrupt controller ? 8-bit timer ch.0 ? spi ch.0 ? po wer generator ? p port & port mux ? misc re gisters the pclk supply cannot be disabled if one or more peripheral modules in the se list must be oper - ated. the pclk supply can be disabled if all the peripheral circuits in these list can be stopped. stop the pclk supply to reduce current consumption if all the peripheral modules listed abo v e are not required. p er ipher al modules/functions that do not use pclk ? real-time clock ? clock timer ? w atchdog timer ? lcd dri v er ? sound generator ? svd circuit ? 16-bit pwm time r ch.0 ? u ar t ch.0 ? fout a/foutb outputs these peripheral modules/functions can operate e v en if pclk is stopped. note: do not set pcken[1:0] to 0x2 or 0x1, since doing so will stop the operation of certain per iph- er al modules .
7 clock genera t or (clg) 7-18 seiko epson corporation s1c17651 t echnical m anual cclk control register (clg_cclk) register name ad dress bit name function setting init. r/w remarks cclk control register (clg_cclk ) 0x5081 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 cclkgr[1:0] cclk cloc k gear r atio select cclkgr[1:0] gear r atio 0x0 r/w 0x3 0x2 0x1 0x0 1/8 1/4 1/2 1/1 d[7:2] reserved d[1:0] cclkgr[1:0]: cclk clock gear ratio select bits selects the gear ratio for reducing system clock speed and sets the cclk clock speed for operating the s1c17 core. t o reduce current consumption, operate the s1c17 core using the slo west possible clock speed. 8.14 cclk gear ratio selection t ab le 7. cclkgr[1:0] gear ratio 0x3 1/8 0x2 1/4 0x1 1/2 0x0 1/1 (def ault: 0x0)
8 theoretical regula tion (tr) s1c17651 t echnical m anual seiko epson corporation 8-1 theor etical regulation (tr) 8 tr module over vie w 8.1 the s1c17651 has a theoretical re gulation function that theoretically corrects time clock errors due to de viation in oscillation frequencies. ? adjusts the osc1a clock (32.768 khz t yp.) (note that the osc1b clock cannot be adjusted.) ? adjustable range: -15/32768 to +16/32768 [second] in a correction operation ? peripheral modules that use the re gu lated clock (f256) 1. real-time clock (r tc) 2. clock timer (ct) 3. w atchdog timer (wdt) 4. 16-bit pwm timer (t16a2) * only when f256 is selected as the count clock ? softw are can e x ecute theoretical re gulation at an y time f256 (256 hz) rtc reset to rtc, ct, wdt, and t16a2 osc1a osc1a oscillator (32.768 khz) clg tr osc1a divider regulation value register (tr_val) theoretical regulation control circuit regmon 1.1 tr module configur ation figure 8. tr output pin 8.2 t able 8.2.1 sho ws the tr output pin. 2.1 tr output pin t ab le 8. pin name i/o qty function regmon o 1 theoretical regulation monitor output pin this pin outputs a regulated cloc k (f256 (256 hz) or f1 (1 hz)) f or monitor ing the theoretical regulation results . the tr output pin (regmon) is shared with an i/o port and is initially set as a general-purpose i/o port pin. the pin function must be switched using the port function select bit to use the general-purpose i/o por t pin as the tr output pin. f or detailed information on pin function switching, see the i/o ports (p) chapter . theoretical regulation contr ol 8.3 setting regulation v alues 8.3.1 the correction v alue (-15/32768 to +16/32768) for theoretical re gulation is specif ied using trim[4:0]/tr_v al re gister .
8 theoretical regula tion (tr) 8-2 seiko epson corporation s1c17651 t echnical m anual 3.1.1 regulation v alue settings t ab le 8. trim[4:0] amount of correction/ one adjustment (n/32768) rate * (seconds/da y) trim[4:0] amount of correction/ one adjustment (n/32768) rate * (seconds/da y) 0x10 -15 +3.955 0x00 +1 -0.264 0x11 -14 +3.691 0x01 +2 -0.527 0x12 -13 +3.428 0x02 +3 -0.791 0x13 -12 +3.164 0x03 +4 -1.055 0x14 -11 +2.900 0x04 +5 -1.318 0x15 -10 +2.637 0x05 +6 -1.582 0x16 -9 +2.373 0x06 +7 -1.846 0x17 -8 +2.109 0x07 +8 -2.109 0x18 -7 +1.846 0x08 +9 -2.373 0x19 -6 +1.582 0x09 +10 -2.637 0x1a -5 +1. 318 0x0a +11 -2.900 0x1b -4 +1.055 0x0b +12 -3.164 0x1c -3 +0.791 0x0c +13 -3.428 0x1d -2 +0.527 0x0d +14 -3.691 0x1e -1 +0.264 0x0e +15 -3.955 0x1f 0 0 0x0f +16 -4.219 * rates when theoretical regulation is e x ecuted in 10-second cycles (def ault: 0x0) addresses 0xbf f a to 0xbf fb in the flash memory are reserv ed for storing the correction v alue. the correction v alue should be programmed in this area by the user and use it for settin g trim[4:0]. the ic will be shipped with this area emptied, therefore, do not place an y program code or data in these addresses. ex ecuting theoretical regulation 8.3.2 w r i t i n g 1 t o r e g t r i g / t r _ c t l r e g i s t e r s t a r t s t h e o r e t i c a l r e g u l a t i o n t h a t i s p e r f o r m e d i n t h e o s c 1 a c l o c k ( 3 2 . 7 6 8 khz) di vider . this operation e xtends or reduces the c ycle time of the 256 hz clock output by the osc1a di vider f o r t h e r e g u l a t i o n v a l u e s p e c i f i e d b y t r i m [4:0] . t h e o r e t i c a l r e g u l a t i o n i s p e r f o r m e d o n l y o n c e b y w r i t i n g 1 t o regtrig. t o perform theoretical re gulation periodically , use a timer interrupt handler to write 1 to regtrig. n o t e t h a t a m a x i m u m 16.6 m s o f d e l a y o c c u r s b e f o r e t h e o r e t i c a l r e g u l a t i o n a c t u a l l y s t a r t s a f t e r w r i t i n g t o regtrig. writing 1 to regtrig in this period is inef fecti v e, so to write 1 to regtr ig successi v ely , an interv al at least 16.6 ms is necessary between writings. the re gulated clock (f256) will be supplied to the osc1 peripheral circuits such as the clock timer . note: use an interr upt from a per ipher al timer module that r uns with the regulated cloc k (f256) to e x- ecute theoretical regulation. an interr upt from the timer that r uns all the time should be used to reduce current consumption . regulated cloc k external monitor 8.3.3 e i t h e r t h e 256 h z ( f256) o r 1 h z ( f1) r e g u l a t e d c l o c k c a n b e o u t p u t f r o m t h e r e g m o n p i n f o r m o n i t o r i n g . rclkfsel/tr_ctl re gister is used to select the clock to be monitored from f256 and f1. when rclkfsel is 0 (def ault), f256 is selected; when rclkfsel is set to 1, f1 is selected. the selected clock is output from the regmon pin by setting rclkmon to 1. sett ing rclkmon to 0 stops the clock output and the regmon pin goes lo w (v ss ) le v el. notes: ? bef ore the 256 hz regulated cloc k can be monitored, either the cloc k timer (ct) or w atchdog timer (wdt) m ust be tur ned on. or tur n the 16-bit pwm timer (t16a2) on after f256 (256 hz regulated cloc k) is selected as its cloc k. ? bef ore the 1 hz regulated cloc k can be monitored, the real-time cloc k (r tc) m ust be tur n ed on.
8 theoretical regula tion (tr) s1c17651 t echnical m anual seiko epson corporation 8-3 contr ol register details 8.4 4.1 list of tr registers t ab le 8. ad dress register name function 0x5078 tr_ctl tr control register controls theoretical regulation. 0x5079 tr_v al tr v alue register sets a regulation v alue . the tr module re gisters are described in detail belo w . note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. tr control register (tr_ctl) register name ad dress bit name function setting init. r/w remarks tr control register (tr_ctl ) 0x5078 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 rclkfsel monitor cloc k frequency select 1 1 hz 0 256 hz 0 r/w d2 rclkmon regulated cloc k monitor enab le 1 enab le 0 disab le 0 r/w d1 C reser v ed C C C 0 when being read. d0 regtrig regulation tr igger 1 t r igger 0 ignored 0 w d[7:4] reserved d3 rclkfsel: monitor clock frequency select bit selects the re gulated clock to be output from the regmon pin for monitoring. 1 (r/w): f1 (1 hz) 0 (r/w): f256 (256 hz) (def ault) d2 rclkmon: regulated clock monitor enable bit controls the clock monitor output from the regmo n pin. 1 (r/w): enabled (on) 0 (r/w): disabled (of f) (def ault) setting rclkmon to 1 outputs the clock selected by rclkfsel from the regmon pin. d1 reserved d0 regtrig: regulation trigger bit ex ecutes theoretical re gulation. 1 (w): t rigger 0 (w): ignored (def ault) theoretical re gulation is performed only once by writing 1 to regtrig. note that a maximum 16.6 ms of delay occurs before theoretical re gulation actually starts after writing to reg trig. writing 1 to regtrig in this period is inef fecti v e, so to write 1 to regtrig succes- si v ely , an interv al at least 16.6 ms is necessary between writings. tr value register (tr_val) register name ad dress bit name function setting init. r/w remarks tr value register (tr_val) 0x5079 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4C0 trim[4:0] regulation v alue trim[4:0] regulation v alue 0x0 r/w 0xf 0x e : 0x1 0x0 +16 +15 : +2 +1 0x1f 0x1e : 0x11 0x10 0 -1 : -14 -15 d[7:5] reserved d[4:0] trim[4:0]: regulation value bits specif ies the correction v alue (-15/32768 to +16/32768) for theoretical re gulation.
8 theoretical regula tion (tr) 8-4 seiko epson corporation s1c17651 t echnical m anual 4.2 regulation v alue settings t ab le 8. trim[4:0] amount of correction/ one adjustment (n/32768) rate * (seconds/da y) trim[4:0] amount of correction/ one adjustment (n/32768) rate * (seconds/da y) 0x10 -15 +3.955 0x00 +1 -0.264 0x11 -14 +3.691 0x01 +2 -0.527 0x12 -13 +3.428 0x02 +3 -0.791 0x13 -12 +3.164 0x03 +4 -1.055 0x14 -11 +2.900 0x04 +5 -1.318 0x15 -10 +2.637 0x05 +6 -1.582 0x16 -9 +2.373 0x06 +7 -1.846 0x17 -8 +2.109 0x07 +8 -2.109 0x18 -7 +1.846 0x08 +9 -2.373 0x19 -6 +1.582 0x09 +10 -2.637 0x1a -5 +1. 318 0x0a +11 -2.900 0x1b -4 +1.055 0x0b +12 -3.164 0x1c -3 +0.791 0x0c +13 -3.428 0x1d -2 +0.527 0x0d +14 -3.691 0x1e -1 +0.264 0x0e +15 -3.955 0x1f 0 0 0x0f +16 -4.219 * rates when theoretical regulation is e x ecuted in 10-second cycles (def ault: 0x0)
9 real-time clock (r tc) s1c17651 t echnical m anual seiko epson corporation 9-1 real-t ime clock (r tc) 9 r tc module over vie w 9.1 the s1c17651 incorporates a real-time clock (r tc). the main features of the r tc are outlined belo w . ? contains time counters (seconds, minutes, and hours). ? the r tc operates with the osc1a oscillator circuit e v en in sleep mode. ? either binary or bcd data can be read from and written to the counters. ? capable of controlling the starting and stoppin g of time clocks. ? 24-hour or 12-hour mode can be selected. ? periodic interrupts (32 hz, 8 hz, 4 hz, 1 hz, 10 second, 1 minute, 10 minutes, 1 hour , 10 hours, half-day , and 1 day) are possible. figure 9.1.1 sho ws a block diagram of the r tc. to itc 10 s, 1 m interrupt control second counter controller minute counter hour counter 10 m, 1 h half-day, 1 day 32 khz f256 osc1a oscillator osc1a divider 32 khz osc1b oscillator osc1b divider theoretical regulation clg & tr osc1sel 1 hz 32 hz, 8 hz, 4 hz, 1 hz internal data bus divider am/pm rtc reset rtcrun 1.1 r tc bloc k diag r am figure 9. r tc counter s 9.2 the r tc contains the follo wing three counters, whose count v alues can be read out as either binary or bcd data from the respecti v e re gisters. each counter can also be set to an y desired time by writing data to the respecti v e re g- ister . second counter this 7-bit binary counter counts from 0 to 59 seconds synchronously with the 1 hz signal deri v ed fro m the di- vider . this counter is also used as a 3-bit (0 to 5) + 4-bit (0 to 9) bcd counter by setting bcdmd/r tc_ctl re gister to 1. the counter data can be read/written using r tcsec[6:0]/r tc_ms re gister . the counter is reset to 0 when it reaches 60 seconds and outputs a carry o v er of 1 to the minute counter . rtcsec[6:0] binary mode 0C59 rtcsec[3:0] bcd mode 0C9 (1-second digit) rtcsec[6:4] 0C5 (10-second digit) 2.1 second counter figure 9.
9 real-time clock (r tc) 9-2 seiko epson corporation s1c17651 t echnical m anual min ute counter this 7-bit binary counter counts from 0 to 59 minutes with 1 carried o v er from the second counter . this counter is also used as a 3-bit (0 to 5) + 4-bit (0 to 9) bcd counter by setting bcdmd/r tc_ctl re gister to 1. the counter data can be read/written using r tcmin[6:0]/r tc_ms re gister . the counter is reset to 0 when it reach- es 60 minutes and outputs a carry o v er of 1 to the hour cou nter . rtcmin[6:0] binary mode 0C59 rtcmin[3:0] bcd mode 0C9 (1-minute digit) rtcmin[6:4] 0C5 (10-minute digit) 2.2 min ute counter figure 9. hour counter this 6-bit binary counter counts from 0 to 23 oclock (24-hour mode) or from 1 to 12 oclock (12-hour mode) with 1 carried o v er from the minute counter . this counter is also used as a 2-bit (0 to 2 or 0 to 1) + 4-bit (0 t o 9) b c d c o u n t e r b y s e t t i n g b c d m d / r t c _ c t l r e g i s t e r t o 1. t h e c o u n t e r d a t a c a n b e r e a d / w r i t t e n u s i n g r tchour[5:0]/r tc_h re gister . ampm 0 (am)/1 (pm) 0/1 ampm 0/1 rtchour[5:0] 24-hour mode binary mode 0C23 rtchour[3:0] bcd mode 0C9 (1-hour digit) rtchour[5:4] 0C2 (10-hour digit) rtchour[5:0] 12-hour mode 1C12 rtchour[3:0] 0C9 (1-hour digit) rtchour[5:4] 0C1 (10-hour digit) 2.3 hour counter figure 9. 2.1 hour counter v alues t ab le 9. time 24-hour mode 12-hour mode r tchour[5:0] (binar y) r tchour[5:0] (bcd) r tchour[5:0] (binar y) r tchour[5:0] (bcd) ampm 0 o'cloc k (12am) 0x0 0x00 0xc 0x12 0 1 o'cloc k (1am) 0x1 0x01 0x1 0x01 0 2 o'cloc k (2am) 0x2 0x02 0x2 0x02 0 3 o'cloc k (3am) 0x3 0x03 0x3 0x03 0 4 o'cloc k (4am) 0x4 0x04 0x4 0x04 0 5 o'cloc k (5am) 0x5 0x05 0x5 0x05 0 6 o'cloc k (6am) 0x6 0x06 0x6 0x06 0 7 o'cloc k (7am) 0x7 0x07 0x7 0x07 0 8 o'cloc k (8am) 0x8 0x08 0x8 0x08 0 9 o 'cloc k (9am) 0x9 0x09 0x9 0x09 0 10 o'cloc k (10am) 0xa 0x10 0xa 0x10 0 11 o'cloc k (11am) 0xb 0x11 0xb 0x11 0 12 o'cloc k (12pm) 0xc 0x12 0xc 0x12 1 13 o'cloc k (1pm) 0xd 0x13 0x1 0x01 1 14 o'cloc k (2pm) 0x e 0x14 0x2 0x02 1 15 o'cloc k (3pm) 0xf 0x15 0x3 0x03 1 16 o'cloc k (4pm) 0x10 0x16 0x4 0x04 1 17 o'cloc k (5pm) 0x11 0x17 0x5 0x05 1 18 o'cloc k (6pm) 0x12 0x18 0x6 0x06 1 19 o'cloc k (7pm) 0x13 0x19 0x7 0x07 1 20 o'cloc k (8pm) 0x14 0x20 0x8 0x08 1 21 o'cloc k (9pm) 0x15 0x21 0x9 0x09 1 22 o'cloc k (10pm) 0x16 0x22 0xa 0x10 1 23 o'cloc k (11pm) 0x17 0x23 0xb 0x11 1 initial counter v alues an initial reset does not initialize the counter v alues. be sure to initialize the counters via softw are.
9 real-time clock (r tc) s1c17651 t echnical m anual seiko epson corporation 9-3 r tc contr ol 9.3 operating cloc k contr ol 9.3.1 t h e r t c m o d u l e u s e s t h e 256 h z c l o c k o u t p u t b y t h e c l g m o d u l e a s t h e o p e r a t i o n c l o c k ( n o r m a l l y , r t c i s clock ed by the f256 clock (re gulated 256 hz clock) deri v ed from the osc1a di vider). therefore, the osc1 oscil- lator must be turned on before starting the r tc. ho we v er , the clock is not supplied to the r tc module while r tc is s t o p p e d e v e n i f t h e o s c 1 o s c i l l a t o r i s o n . f o r d e t a i l e d i n f o r m a t i o n o n c l o c k c o n t r o l , s e e t h e c l o c k g e n e r a t o r ( c l g ) and theoretical re gulation (tr) chapters. notes: ? t h e r t c m o d u l e i n p u t c l o c k f r e q u e n c y i s 256 h z o n l y w h e n t h e o s c1 c l o c k f r e q u e n c y i s 32.768 k h z . t h e f r e q u e n c y d e s c r i b e d i n t h i s c h a p t e r w i l l v a r y a c c o r d i n g l y f o r o t h e r o s c1 cloc k frequencies . ? the r tc module can also be oper ated with the osc1b divider cloc k (about 256 hz) e v en if osc1b is selected as the osc1 cloc k source in the clg. ho w e v er , the r tc cannot be used as an accur ate cloc k. ? t h e o s c 1 a d i v i d e r i s r e s e t w h e n t h e r t c s t a r t s r u n n i n g ( w h e n 1 i s w r i t t e n t o r t c r u n / r t c _ ctl register). this aff ects the count oper ations of the timer modules (ct , wdt , and t16a2), as ne w 256 hz cycle begins from that point. ? after an initial reset, r tcr un is set to 0 and the r tc idles . the osc1 oscillator circuit is also idle . theref ore , resetting the ic suspends the r tc oper ation f or the per iod sho wn belo w . r tc idle time = [#rest = lo w per iod] + [osc3b oscillation stabilization time] + [time until osc1 is star ted] + [osc1 oscillation stabilization time] + [time until r tc is restar ted] 12-hour/24-hour mode selection 9.3.2 whether to use the clock i n 12-hour or 24-hour mode can be selected using r tc24h/r tc_ctl re gister . r tc24h = 1: 12-hour mode r tc24h = 0: 24-hour mode the count range of the hour counter changes with this selection. basically , this setting should be changed while the counters are idle. r tc24h is allocated to the same address as the control bits that start the counters. therefore, 12-hour mode or 24-hour mode can be selected a t the same time the counters are started. chec king a.m./p .m. with 12-hour mode selected when 12-hour mode is selected, ampm/r tc_h re gister that indicates a.m. or p .m. is enabled. ampm = 0: a.m. ampm = 1: p .m. f or 24-hour mode, ampm is f ix ed to 0. when setting the time of day , write either of the v alues abo v e to this bit to specify a.m. or p .m. r tc star t/stop 9.3.3 the r tc starts counting when r tcr u n/r tc_ctl re gister is set to 1, and stops counting when this bit is set to 0. t h e o s c 1 a d i v i d e r i n t h e c l g m o d u l e i s r e s e t b y w r i t i n g 1 t o r t c r u n a n d i t s t a r t s d i v i s i o n o f t h e o s c 1 a c l o c k . counter settings 9.3.4 counter v alues should be set in the procedure sho wn belo w . 1. stop the r tc by writing 0 to r tcr un/r tc_ctl re gister . 2. w ait until r tcst/r tc_ctl re gister is reset to 0 (the r tc actually stops operating).
9 real-time clock (r tc) 9-4 seiko epson corporation s1c17651 t echnical m anual 3. write the counter v alues to the r tc_ms and r tc_h re gisters. 4. start the r tc by writing 1 to r tcr un/r tc_ctl re gister . rtcrun 0 register write rtcrun 1 rtcst = 0? no yes counter setting end 3.4.1 procedure f or setting counters figure 9. notes: ? do not set the counters while the r tc is r unning, as proper settings to the counters cannot be guar anteed. ? counter v alues to be set m ust be within the eff ectiv e r ange according to binar y/bcd mode . the counter will be undefined if a v alue out of the r ange is wr itten. ? depending on the v alue set, an interr upt ma y occur immediately after star ting the r tc . counter read 9.3.5 if 1 is being carried o v er while the counters are being read, correct time may not be read. counter v alues should be read in the procedure sho wn belo w . read pr ocedure 1 1. read the r tc_ms and r tc_h re gisters. 2. read the r tc_ms and r tc_h re gisters ag ain. 3. if the same v alue is read out in steps 1 and 2, use it as the correct time. if dif ferent v alues are read out, try ag ain from step 1. read the r tc_ms and r tc_h registers (a) read the r tc_ms and r tc_h registers (b) current time = a (b) a = b? no yes counter read end 3.5.1 procedure f or reading counters figure 9. read pr ocedure 2 after a 1 hz interrupt (or 10-second to 1 day interrupt) occurs, read the r tc_ms and r tc_h re gisters within one second.
9 real-time clock (r tc) s1c17651 t echnical m anual seiko epson corporation 9-5 r tc interrupts 9.4 the r tc can generate interrupts in 10 dif ferent c ycles listed in t able 9.4.1. t o generate interrupts, set the inter - rupt enable bits for the interrupt c ycles to 1. if an interrupt enable bit is set to 0 (def ault), interrupt requests for the cause will not be sent to the itc. 4.1 interr upt cycles and interr upt control bits t ab le 9. interr upt cycle interr upt timing interr upt flag (r tc_iflg register) interr upt enab le bit (r tc_ien register) one da y hour counter = 230 (24-hour mode) hour counter = 11pm12am (12-hour mode) int1d int1den half-da y hour counter = 1112, 230 (24-hour mode) hour counter = 11am12pm, 11pm12am (12-hour mode) inthd inthden 1 hour min ute counter = 590 int1h int1hen 10 min utes min ute counter = 910, 1920, 2930, 3940, 49 50, 590 int10m int10men 1 min ute second counter = 590 int1m int1men 10 seconds second counter = 910, 1920, 2930, 3940, 4950, 590 int10s int10sen 1 hz divider 1 hz signal cycles int1hz int1hzen 4 hz divider 4 hz signal cycles int4hz int4hzen 8 hz divider 8 hz signal cycles int8hz int8hzen 32 hz divider 32 hz signal cycles int32hz int32hzen when the interrupt enable bit is set to 1, the corresponding interrupt flag w ill be set to 1 in the timing sho wn abo v e and the interrupt request will be sent to the itc. since the r tc is acti v e e v en in sleep mode, r tc interrupt requests may be used to cancel sleep mode. f or e x- ample, the r tc interrupt can be used for e x ecuting periodical theoretical re gulation processing when the theoretical re gulation type osc1a oscillator is used. f or more information on interrupt processi ng, see the interrupt controller (itc) chapter . notes: ? t o pre v ent interr upt recurrences , the interr upt flag m ust be reset in the interr upt handler rou- tine after an r tc interr upt has occurred. the interr upt flag is reset b y wr iting 1. ? t o pre v ent unw anted interr upts , reset the interr upt flags bef ore enab ling interr upts with the in- terr upt enab le bits . contr ol register details 9.5 5.1 list of r tc registers t ab le 9. ad dress register name function 0x56c0 r tc_ctl r tc control register controls the r tc . 0x56c2 r tc_ien r tc interr upt enab le register enab les/disab les interr upts . 0x56c4 r tc_iflg r tc interr upt flag register displa ys/sets interr upt occurrence status . 0x56c6 r tc_ms r tc min ute/second counter register min ute/second counter data 0x56c8 r tc_h r tc hour counter register hour counter data the follo wing describes each r tc re gister . note: when data is wr itten to the register , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. rtc control register (rtc_ctl) register name ad dress bit name function setting init. r/w remarks rtc control register (rtc_ctl) 0x56c0 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 rtcst r tc r un/stop status 1 running 0 stop 0 r d7C6 C reser v ed C C C 0 when being read. d5 bcdmd bcd mode select 1 bcd mode 0 b i n a r y m o d e 0 r/w d4 rtc24h 24h/12h mode select 1 12h 0 24h 0 r/w d3C1 C reser v ed C C C 0 when being read. d0 rtcrun r tc r un/stop control 1 run 0 stop 0 r/w
9 real-time clock (r tc) 9-6 seiko epson corporation s1c17651 t echnical m anual d[15:9] reserved d8 rtcst: rtc run/stop status bit indicates the r tc operating status. 1 (r): running 0 (r): stop (def ault) r tcst goes 1 when the r tc starts running by writing 1 to r tcr un. r tcst re v erts to 0 when the count operation is actually stopped after 0 is written to r tcr un. when setting counter v alues, write 0 to r tcr un and mak e sure that r tcst is reset to 0 before writing data. d[7:6] reserved d5 bcdmd: bcd mode select bit sets the second, minute, and hour counters into bcd mode . 1 (r/w): bcd mode 0 (r/w): binary mode (def ault) by def ault, each counter operates as a binary counter and a binary v alue is read or written as counter data. setting bcdmd to 1 conf igures the counter so that tw o-digit bcd v alue can be read or written. see section 9.2 for the conf iguration of the counter in each mode. d4 rtc24h: 24h/12h mode select bit selects whether to use the hour counter in 24-hour or 12-hour mode. 1 (r/w): 2 4-hour mode 0 (r/w): 12-hour mode (def ault) t h e c o u n t r a n g e o f t h e h o u r c o u n t e r c h a n g e s w i t h t h i s s e l e c t i o n . b a s i c a l l y , t h i s s e t t i n g s h o u l d b e changed while the counters are idle. since this re gister is assigned a control bit (d0) to start the coun- ters, 12-hour or 24-hour mode may be selected when starting the counters. d[3:1] reserved d0 rtcrun: rtc run/stop control bit starts or stops the r tc. 1 (r/w): start 0 (r/w): stop (def ault) t h e r t c r u n d e f a u l t s e t t i n g i s 0 , w h i c h s t o p s t h e r t c . s e t t i n g r t c r u n t o 1 e n a b l e s t h e c l g t o s e n d the clock to the r tc. when r tcr un is set to 1, the osc1a oscillator circuit does not stop e v en if the ic enters sleep mode (the osc1 clock will be supplied to the r tc only). writing 1 to r tcr un resets the osc1a di vider in the clg module. rtc interrupt enable register (rtc_ien) register name ad dress bit name function setting init. r/w remarks rtc interrupt enable register (rtc_ien) 0x56c2 (16 bits) d15C10 C reser v ed C C C 0 when being read. d9 int1den 1-da y interr upt enab le 1 enab le 0 disab le 0 r/w d8 inthden half-da y interr upt enab le 1 enab le 0 disab le 0 r/w d7 int1hen 1-hour interr upt enab le 1 enab le 0 disab le 0 r/w d6 int10men 10-min ute interr upt enab le 1 enab le 0 disab le 0 r/w d5 int1men 1-min ute interr upt enab le 1 enab le 0 disab le 0 r/w d4 int10sen 10-second interr upt enab le 1 enab le 0 disab le 0 r/w d3 int1hzen 1 hz interr upt enab le 1 enab le 0 disab le 0 r/w d2 int4hzen 4 hz interr upt enab le 1 enab le 0 disab le 0 r/w d1 int8hzen 8 hz interr upt enab le 1 enab le 0 disab le 0 r/w d0 int32hzen 32 hz interr upt enab le 1 enab le 0 disab le 0 r/w this re gister is used to enable/disable r tc interrupts. when the interrupt enable bit for an interrupt c ycle is set to 1, the corresponding interrupt flag will be set to 1 in the interrupt c ycles and the interrupt request will be sent to the itc. if an interrupt enable bit is set to 0, the interrup t request will not be sent to the itc. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault)
9 real-time clock (r tc) s1c17651 t echnical m anual seiko epson corporation 9-7 d[15:10] reserved d9 int1den: 1-day interrupt enable bit enables or disables 1-day interrupt requests to the itc. d8 inthden: half-day interrupt enable bit enables or disables half-day interrupt requests to the itc. d7 int1hen: 1-hour interrupt enable bit enables or disables 1-hour interrupt requests to the itc. d6 int10men: 10-minute interrupt enable bit enables or disables 10-minute interrupt requests to the itc. d5 int1men: 1-minute interrupt enable bit enables or disables 1-minute interrupt requests to the itc. d4 int10sen: 10-second interrupt enable bit enables or disables 10-second interrupt requests to the itc. d3 int1hzen: 1 hz interrupt enable bit enables or disables 1 hz interrupt requests to the itc. d2 int4hzen: 4 hz interrupt enable bit enables or disables 4 hz interrupt requests to the itc. d1 int8hzen: 8 hz interrupt enable bit enables or disables 8 hz interrupt requests to the itc. d0 int32hzen: 32 hz interrupt enable bit enables or disables 32 hz interrupt requests to the itc. rtc interrupt flag register (rtc_iflg) register name ad dress bit name function setting init. r/w remarks rtc interrupt flag register (rtc_iflg) 0x56c4 (16 bits) d15C10 C reser v ed C C C 0 when being read. d9 int1d 1-da y interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d8 inthd half-da y interr upt flag 0 r/w d7 int1h 1-hour interr upt flag 0 r/w d6 int10m 10-min ute interr upt flag 0 r/w d5 int1m 1-min ute interr upt flag 0 r/w d4 int10s 10-second interr upt flag 0 r/w d3 int1hz 1 hz interr upt flag 0 r/w d2 int4hz 4 hz interr upt flag 0 r/w d1 int8hz 8 hz interr upt flag 0 r/w d0 int32hz 32 hz interr up t flag 0 r/w t h i s r e g i s t e r i n d i c a t e s r t c i n t e r r u p t c a u s e o c c u r r e n c e s t a t u s . w h e n t h e c o r r e s p o n d i n g i n t e r r u p t e n a b l e b i t i s s e t t o 1 , the interrupt flag will be set to 1 in the interrupt c ycles and the interrupt request will be sent to the itc. the inter - rupt flags are reset to 0 by writing 1. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is res et 0 (w): ignored d[15:10] reserved d9 int1d: 1-day interrupt flag bit indicates 1-day interrupt cause occurrence status. int1d is set to 1 at the same time the hour counter changes from 23 to 0 (in 24-hour mode) or 11pm to 12am (in 12-hour mode). d8 inthd: half-day interrupt flag bit i n d i c a t e s h a l f - d a y i n t e r r u p t c a u s e o c c u r r e n c e s t a t u s . i n t h d i s s e t t o 1 a t t h e s a m e t i m e t h e h o u r counter changes from 11 to 12, 23 to 0 (in 24-hour mode), or 11am to 12pm, 11pm to 12am (in 12-hour mode ).
9 real-time clock (r tc) 9-8 seiko epson corporation s1c17651 t echnical m anual d7 int1h: 1-hour interrupt flag bit i n d i c a t e s 1- h o u r i n t e r r u p t c a u s e o c c u r r e n c e s t a t u s . i n t1h i s s e t t o 1 a t t h e s a m e t i m e t h e m i n u t e counter changes from 59 to 0. d6 int10m: 10-minute interrupt flag bit indicates 10-minute interrupt cause occurrence status. int10m is set to 1 at the same time the minute counter changes from 9 to 10, 19 to 20, 29 to 30, 39 to 40, 49 to 50, or 59 to 0. d5 int1m: 1-minute interrupt flag bit indicates 1-minute interrupt cause occurrence status. int1m is set to 1 at the same time the second counter changes from 59 to 0. d4 int10s: 10-second interrupt flag bit indicates 10-second interrupt cause occurrence status. int10s is set to 1 at the same time the second counter changes from 9 to 10, 19 to 20, 29 to 30, 39 to 40, 49 to 50, or 59 to 0. d3 int1hz: 1 hz interrupt flag bit indicates 1 hz interrupt cause occurrence status. int1hz is set to 1 in the di vider 1 hz signal c ycles. d2 int4hz: 4 hz interrupt flag bit indicates 4 hz interrupt cause occurrence status. int4hz is set to 1 in the di vider 4 hz signal c ycles. d1 int8hz: 8 hz interrupt flag bit indicates 8 hz interrupt cause occurrence status. int8hz is set to 1 in the di vider 8 hz signal c ycles. d0 int32hz: 32 hz interrupt flag bit i n d i c a t e s 32 h z i n t e r r u p t c a u s e o c c u r r e n c e s t a t u s . i n t32h z i s s e t t o 1 i n t h e d i v i d e r 32 h z s i g n a l c ycles. rtc minute/second counter register (rtc_ms) register name ad dress bit name function setting init. r/w remarks rtc minute/second counter register (rtc_ms) 0x56c6 (16 bits) d15 C reser v ed C C C 0 when being read. d14C8 rtcmin [6:0] min ute counter 0x0 to 0x3b (binar y mode) 0x00 to 0x59 (bcd mode) x r/w d7 C reser v ed C C C 0 when being read. d6C0 rtcsec [6:0] second counter 0x0 to 0x3b (binar y mode) 0x00 to 0x59 (bcd mode) x r/w d15 reserved d[14:8] rtcmin[6:0]: minute counter bits these bits are used to read and write data from/to the minute counter . (def ault: undef ined) the ef fecti v e range of the read/setting v alues are as follo ws: ? r tcmin[6:0] = 0x 0 to 0x3b (0 to 59 minutes) in binary mode (bcdmd = 0) ? r tcmin[6:4] = 0x0 to 0x5 (10-minute digit) and r tcmin[3:0] = 0x0 to 0x9 (1-minute digit) in bcd mode (bcdmd = 1) d7 reserved d[6:0] rtcsec[6:0]: second counter bits these bits are used to read and write data from/to the second counter . (def ault: undef ined) the ef fecti v e range of the read/setting v alues are as follo ws: ? r tcsec[6:0] = 0x0 to 0x3b (0 to 59 seconds) in binary mode (bcdmd = 0) ? r t c s e c [6:4] = 0x0 t o 0x5 (10- s e c o n d d i g i t ) a n d r t c s e c [3:0] = 0x0 t o 0x9 (1- s e c o n d d i g i t ) i n bcd mode (bcdmd = 1) notes: ? f or the counter read and wr ite procedures , see section 9.3.5, counter read, and section 9.3.4, counter settings . ? do not set the counters while the r tc is r unning, as proper settings to the counters cannot be guar anteed.
9 real-time clock (r tc) s1c17651 t echnical m anual seiko epson corporation 9-9 ? counter v alues to be set m ust be within the eff ectiv e r ange according to binar y/bcd mode . the counter will be undefined if a v alue out of the r ange is wr itten. ? depending on the v alue set, an interr upt ma y occur immediately after star ting the r tc . rtc hour counter register (rtc_h) register name ad dress bit name function setting init. r/w remarks rtc hour counter register (rtc_h) 0x56c8 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7 ampm am/pm 1 pm 0 am x r/w d6 C reser v ed C C C 0 when being read. d5C0 rtchour [5:0] hour counter 0x0 to 0x17 (binar y mode) 0x00 to 0x23 (bcd mode) x r/w d[15:8] reserved d7 ampm: am/pm bit indicates a.m. or p .m. when 12-hour mode is selected. (def ault: undef ined) 1 (r/w): p .m. 0 (r/w): a.m. this bit is only ef fecti v e when r tc24h/r tc_ctl re gister is set to 1 (12-hour mode). when 24-hour mode is selected, this bit is f ix ed to 0. in this case, do not write 1 to ampm. note: the ampm bit will be fixed at 0 immediately after r tc24h/r tc_ctl register is changed from 12-hour mode to 24-hour mode. d6 reserved d[5:0] rtchour[5:0]: hour counter bits these bits are used to read and write data from/to the hour counter . (def ault: undef ined) the ef fecti v e range of the read/setting v alues in binary mode (bcdmd = 0) are as follo ws: ? r tchour[5:0] = 0x0 to 0x17 (0 to 23 oclock) in 24-hour mode ? r tchour[5:0] = 0x1 to 0xc (1 to 12 oclock) in 12-hour mode the ef fecti v e r ange of the read/setting v alues in bcd mode (bcdmd = 1) are as follo ws: ? r tchour[5:4] = 0x0 to 0x2 (10-hour digit) and r tchour[3:0] = 0x0 to 0x9 (1-hour digit) in 24- hour mode ? r tchour[5:4] = 0x0 to 0x1 (10-hour digit) and r tchour[3:0] = 0x0 to 0x9 (1-hour digit) in 12- hour mode notes: ? f or the counter read and wr ite procedures , see section 9.3.5, counter read, and section 9.3.4, counter settings . ? do not set the counters while the r tc is r unning, as proper settings to the counters cannot be guar anteed. ? counter v alues to be set m ust be within the eff ectiv e r ange according to binar y/bcd mode . the counter will be undefined if a v alue out of the r ange is wr itten. ? depending on the v alue set, an interr upt ma y occur immediately after star ting the r tc .
10 i/o por ts (p) s1c17651 t echnical m anual seiko epson corporation 10-1 i/o p orts (p) 10 p module over vie w 10.1 the p ports are general-purpose digital inputs/outputs that allo w softw are to control the input/output direction and pull-up resistor . these ports are shared with internal peripheral module inputs/outputs, and the pin functions can be s w i t c h e d b y s e t t i n g t h e r e g i s t e r s . a n u m b e r o f p o r t g r o u p s c a n g e n e r a t e i n t e r r u p t s c a u s e d b y a t r a n s i t i o n o f t h e i n p u t signal . the follo wing sho ws the features of the p module: ? maximum 12 i/o ports (p0[7:0], p1[3:0]) are a v ailable. * the number of ports for general-purpose use depends on the peripheral functions used. ? each port has a pull-up resistor that can be enabled with softw are. ? input interf ace le v el: cmos schmitt ? the p0 ports can generate input interrupts at the signal edge selected with softw are. ? the p0 ports include a chattering f ilter . ? can generate an initial reset by entering lo w le v el simultaneously to the p0 ports selected with softw are. ? all port pro vide a port function select bit to conf igure the pin function (for gpio or peripheral functions). figure 10.1.1 sho ws the i/o port conf iguration. peripheral output peripheral i/o control pxpuy pxoeny pxouty pxymux pull-up enable output enable output data function selection v dd v ss internal data bus pxy peripheral module input pxieny p0cf1[2:0]/p0cf2[2:0] chattering filter (p0) input enable 1.1 i/o p or t configur ation figure 10. notes: ? the pclk cloc k m ust be supplied from the cloc k gener ator to access the i/o por t. the pclk cloc k is also needed to oper ate the p0 chatter ing filter . ? the xy in the register and bit names ref ers to the por t n umber (pxy, x = 0 and 1, y = 0 to 7). example: pxiny/px_in register p00: p0in0/p0_in register p13: p1in3/p1_in register
10 i/o por ts (p) 10-2 seiko epson corporation s1c17651 t echnical m anual input/output pin function selection (p or t mux) 10.2 the i/o port pins share peripheral module input/output pins. each pin can be conf igured for use as an i/o port or for a peripheral module function via the corresponding port function-select bits. pins not used for peripheral mod- ules can be used as general-purpose i/o ports. 2.1 input/output pin function selection t ab le 10. pin function 1 pxymux[1:0] = 0x0 pin function 2 pxymux[1:0] = 0x1 pin function 3 pxymux[1:0] = 0x2 pin function 4 pxymux[1:0] = 0x3 p or t function select bits p00 sin0 (u ar t) C C p00mux[1:0]/p00_03pmux register p01 sout0 (u ar t) C C p01mux[1:0]/p00_03pmux register p02 sclk0 (u ar t) fout a (clg) regmon (tr) p02mux[1:0]/p00_03pmux register p03 excl0 (t16a2) regmon (tr) lfr o (lcd) p03mux[1:0]/p00_03pmux register p04 t out a0/cap a0 (t16a 2) C C p04mux[1:0]/p04_07pmux register p05 t o u t b 0 / c a p b 0 ( t 1 6 a 2 ) #spiss0 (spi) C p05mux[1:0]/p04_07pmux register p06 bz (snd) sdi0 (spi) C p06mux[1:0]/p04_07pmux register p07 #bz (snd) sdo0 (spi) C p07mux[1:0]/p04_07pmux register p10 foutb (clg) spiclk0 (spi) C p10mux[1:0]/p10_13pmux register dclk (dbg) p11 bz (snd) C p11mux[1:0]/p10_13pmux register dsio (dbg) p12 #bz (snd) C p12mux[1:0]/p10_13pmux register dst2 (dbg) p13 C C p13mux[1: 0]/p10_13pmux register at initial reset, each i/o port pin (pxy) is initialized for the def ault function (pin function 1 in t able 10.2.1). f or information on functions other than the i/o ports, see the descriptions of the peripheral modules indicated in parentheses. the sections belo w describe port functions with the pins set as general-purpose i/o ports. data input/output 10.3 data input/output con tr ol t h e i / o p o r t s a l l o w s e l e c t i o n o f t h e d a t a i n p u t / o u t p u t d i r e c t i o n f o r e a c h b i t u s i n g p x o e n y / p x _ o e n r e g i s t e r a n d pxieny/px_ien re gister . pxoeny enables and disables data output, while pxieny enables and disables data input. 3.1 data input/output status t ab le 10. pxoeny output contr ol pxieny input contr ol pxpuy pull-up contr ol p or t status 0 1 0 functions as an input por t (pull-up off). the por t pin (e xter nal input signal) v alue can be read out from pxiny (input data). output is disab led. 0 1 1 functions as an input por t (pull-up on). (def ault) the por t pin (e xter nal input signal) v alue can be read out from pxiny (input data). output is disab led. 1 0 1 or 0 functions as an out put por t (pull-up off). input is disab led. the v alue read from pxiny (input data) is 0. 1 1 1 or 0 functions as an output por t (pull-up off). input is also enab led. the por t pin v alue (output v alue) can be read out from pxiny (input data). 0 0 0 the pin is placed into high-impedance status (pull-up off). output and input are both disab led. the v alue read from pxiny (input data) is 0. 0 0 1 the pin is placed into high-impedance status (pull-up on). output and input are both disab led. the v alue read from pxiny (input data) is 0. the input/output direction of ports with a peripheral module function selected is controlled by the peripheral module. pxoeny and pxieny settings are ignored.
10 i/o por ts (p) s1c17651 t echnical m anual seiko epson corporation 10-3 data input t o input the port pin status and read out the v alue, enable input by setting pxieny to 1 (def ault). t o input an e xternal signal, pxoeny should also be set to 0 (def ault). the i/o port is placed into high-imped- ance status and it functions as an input port (input mode). the port is pulled up if pull-up is enabled by pxpuy/ px_pu re gister . in input mode, the input pin status can be read ou t directly from pxiny/px_in re gister . the v alue read will be 1 when the input pin is at high (v dd ) le v el and 0 when it is at lo w (v ss ) le v el. the port pin status is al w ays input when pxieny is 1, e v en if output is enabled (pxoeny = 1) (output mode). in this case, the v alue actually output from the port can be read out from pxiny. when pxieny is set to 0, input is disabled, and 0 will be read out f rom pxiny. data output t o output data from the port pin, enable output by setting pxoeny to 1 (set to output mode). the i/o port then functions as an output port, and the v alue set in the pxouty/px_out re gister is output from the port pin. the port pin outputs high (v dd ) le v el when pxouty is set to 1 and lo w (v ss ) le v el when set to 0. note that the port will not be pulled up in output mode, e v en if pull-up is enabled by pxpuy. writing to pxouty is possible without af fecting pin status, e v en in input mode. pull-up contr ol 10.4 the i/o port contains a pull-up resistor that can be enabled or disabled indi vidually for each bit using pxpuy/px_ pu re gister . setting pxpuy to 1 (def ault) enables the pull-up resistor and pulls up the port pin in input mode. it will not be pulled up if set to 0. the px puy setting is ignored and not pulled up in output mode, re g ardless of ho w the pxieny is set. i/o ports that are not used should be set with pull-up enabled. the pxpuy setting is also ignored if a pin function other than pxy i/o port is selected. in this case, the pull-up resis- tor is automatically enabled/disabled according to the pin function selected. a delay will occur in the w a v eform rising edge depending on time constants such as pull-up resistance and pin load capacitance if the port pin is switched from lo w le v el to high le v el through the internal pull-up resistor . an ap- propriate w ait time must be set for the i/o port loading. the w ait time set should be a v alue not less than that calcu- lated from the follo wing equation. w ait time = r in (c in + load capacitance on board) 1.6 [s] r i n : pull-up resistance maximum v alue, c in : pin capacitance maximum v alue p or t input interrupt 10.5 the p0 ports include input interrupt functions. select which of the 8 ports are to be used for interrupts based on requirements. y ou can also select whether inter - rupts are generated for either the rising edge or f alling edge of the input signals. figure 10.5.1 sho ws the port input interrupt circuit conf iguration. p0 port interrupt request (to itc) chattering filter interrupt flag interrupt enable interrupt edge selection p00 p0cf1[2:0] p0edge0 p0if0 p0ie0 p07 p0cf2[2:0] p0edge7 p0if7 p0ie7 ? ? ? 5.1 p or t input interr upt circuit configur ation figure 10.
10 i/o por ts (p) 10-4 seiko epson corporation s1c17651 t echnical m anual interrupt por t selection select the port generating an interrupt using p0iey/p0_imsk re gister . setting p0iey to 1 enables interrupt generation by the corresponding port. setting to 0 (def ault) disables inter - rupt generation. interrupt edg e selection p o r t i n p u t i n t e r r u p t s c a n b e g e n e r a t e d a t e i t h e r t h e r i s i n g e d g e o r f a l l i n g e d g e o f t h e i n p u t s i g n a l . s e l e c t t h e e d g e used to generate interrupts using p0edgey/p0_edge re gister . setting p0edgey to 1 generates port input interrupts at the input signal f alling edge. setting it to 0 (def ault) generates interrupts at the rising edge. interrupt fla gs the itc is able to accept one interrupt request from the p0 ports, and the p port module contains interrupt flags p0ify/p0_iflg re gister corresponding to the indi vidual eight ports to enable indi vidual co ntrol of the eight p0[7:0] port interrupts. p0ify is set to 1 at the specif ied edge (rising or f alling edge) of the input signal. if the corresponding p0iey has been set to 1, an interrupt request signal is also output to the itc at the same time. an interrupt is generated if the itc and s1c17 core interrupt conditions are satisf ied. p0ify is reset by writing 1. f or specif ic information on interru pt processing, see the interrupt controller (itc) chapter . notes: ? the p por t module interr upt flag p0ify m ust be reset in the interr upt handler routine after a por t interr upt has occurred to pre v ent recurr ing interr upts . ? t o pre v ent gener ating unnecessar y interr upts , reset the rele v ant p0ify bef ore enab ling inter- r upts f or the required por t using p0iey. p0 p or t chattering filter function 10.6 the p 0 ports include a chattering f ilter circuit for k e y entry that can be disabled or enabled with a check time speci- f ied indi vidually for the four p0[3:0] and p0[7:4] ports using p0cf1[2:0]/p0_cha t re gister and p0cf2[2:0]/p0_ cha t re gister , respecti v ely . 6.1 chatter ing filter function settings t ab le 10. p0cf1[2:0]/p0cf2[2:0] chec k time * 0x7 16384/f pclk (8 ms) 0x6 8192/f pclk (4 ms) 0x5 4096/f pclk (2 ms) 0x4 2048/f pclk (1 ms) 0x3 1024/f pclk (512 s) 0x2 512/f pclk (256 s) 0x1 256/f pclk (128 s) 0x0 no chec k time (off) (def ault: 0x0, * when pclk = 2 mhz) notes: ? a n u n e x p e c t e d i n t e r r u p t m a y o c c u r a f t e r s l e e p s t a t u s i s c a n c e l e d i f t h e s l p i n s t r u c t i o n i s e x ecuted while the chatter ing filter function is enab led. the c hatter ing filter m ust be disab led bef ore placing the cpu into sleep status . ? t h e c h a t t e r i n g f i l t e r c h e c k t i m e r e f e r s t o t h e m a x i m u m p u l s e w i d t h t h a t c a n b e f i l t e r e d . gener ating an input interr upt requires an input time of twice the chec k time . ? the p0 por t interr upt m ust be disab led bef ore setting the p0_cha t register . setting the regis- ter while the interr upt is enab led ma y gener ate inadv er tent p0 por t interr upt. also the chatter- ing filter circuit requires a maxim um of twice the chec k time f or stabilizing the oper ation status . bef ore enab ling the interr upt, mak e sure that the stabilization time has elapsed.
10 i/o por ts (p) s1c17651 t echnical m anual seiko epson corporation 10-5 p0 p or t k e y-entr y reset 10.7 entering lo w le v el simultaneously to the ports (p00Cp03) selected with softw are triggers an initial reset. the ports used for the reset function can be selected with the p0krst[1:0]/p0_krst re gister . 7.1 configur ation of p0 p or t k e y-entr y reset t ab le 10. p0krst[1:0] p or t used f or resetting 0x3 p00, p01, p02, p03 0x2 p00, p01, p02 0x1 p00, p01 0x0 not used (def ault: 0x0) f or e xample, if p0krst[1:0] is set to 0x3, an initial reset will tak e place when the four ports p00Cp03 are set to lo w le v el at the same time. notes: ? the p0 por t k e y-entr y reset function cannot be used f or po w er-on reset as it m ust be enab led with softw are . ? when using the p0 por t k e y-entr y res et function, mak e sure that the designated input por ts will not be sim ultaneously set to lo w le v el while the application prog r am is r unning. contr ol register details 10.8 8.1 list of i/o p or t control registers t ab le 10. ad dress register name function 0x5200 p0_in p0 p or t input data register p0 por t input data 0x5201 p0_out p0 p or t output data register p0 por t output data 0x5202 p0_oen p0 p or t output enab le register enab les p0 por t outputs . 0x5203 p0_pu p0 p or t pull-up control register controls the p0 por t pull-up resistor . 0x5205 p0_imsk p0 p or t interr upt mask register enab les p0 por t interr upts . 0x5206 p0_edge p0 p or t interr upt edge sel ect register selects the signal edge f or gener ating p0 por t interr upts . 0x5207 p0_iflg p0 p or t interr upt flag register indicates/resets the p0 por t interr upt occurrence status . 0x5208 p0_cha t p0 p or t chatter ing filter control register controls the p0 por t chatter ing filter . 0x5209 p0_krst p0 p or t k e y-entr y reset configur ation register configures the p0 por t k e y-entr y reset function. 0x520a p0_ien p0 p or t input en ab le register enab les p0 por t inputs . 0x5210 p1_in p1 p or t input data register p1 por t input data 0x5211 p1_out p1 p or t output data register p1 por t output data 0x5212 p1_oen p1 p or t output enab le register enab les p1 por t outputs . 0x5213 p1_pu p1 p or t pull-up control register controls the p1 por t pull-up resistor . 0x521a p1_ien p1 p or t input enab le register enab les p1 por t inputs . 0x52a0 p00_03pmux p0[3:0] p or t function select register selects the p0[3:0] por t functions . 0x52a1 p04_07pmux p0[7:4] p or t function select register selects the p0[7:4] por t functions . 0x52a2 p10_13pmux p1[3:0] p or t function select register selects the p1[3:0] por t functions . the i/o port re gisters are described in detail belo w . note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. px port input data registers (px_in) register name ad dress bit name function setting init. r/w remarks px port input data register (px_in) 0x5200 0x5210 (8 bits) d7C0 pxin[7:0] px[7:0] por t input data 1 1 (h) 0 0 (l) r note: p1in[3:0] only are a v ailab le f or the p1 por ts . other bits are reser v ed and alw a ys read as 0. d[7:0] px in[7:0]: px [7:0] port input data bits the port pin status can be read out. (def ault: e xternal input status) 1 (r): high le v el 0 (r): lo w le v el
10 i/o por ts (p) 10-6 seiko epson corporation s1c17651 t echnical m anual pxiny corresponds directly to the pxy pin. the pin v oltage le v el can be read out when input is enabled (pxieny = 1) (e v en if output is also enabled (pxoeny = 1)). the v alue read out will be 1 when the pin v oltage is high and 0 when lo w . the v alue read out is 0 when input is disabled (pxieny = 0). writing operations to the read-only pxiny is disabled. px port output data registers (px_out) register name ad dress bit name function setting init. r/w remarks px port output data register (px_out) 0x5201 0x5211 (8 bits) d7C0 pxout[7:0] px[7:0] por t output data 1 1 (h) 0 0 (l) 0 r/w note: p1out[3:0] only are a v ailab le f or the p1 por ts . other bits are reser v ed and alw a ys read as 0. d[7:0] px out[7:0]: px [7:0] port output data bits sets the data to be output from the port pin. 1 (r/w): high le v el 0 (r/w): lo w le v el (def ault) pxouty corresponds directly to the pxy pins. the data written will be output unchanged from the port pins when output is enabled (pxoeny = 1 ). the port pin will be high when the data bit is set to 1 and lo w when set to 0. port data can also be written when output is disabled (pxoeny = 0) (the pin status is unaf fected). px port output enable registers (px_oen) register name ad dress bit name function setting init. r/w remarks px port output enable register (px_oen) 0x5202 0x5212 (8 bits) d7C0 pxoen[7:0] px[7:0] por t output enab le 1 enab le 0 disab le 0 r/w note: p1oen[3:0] only are a v ailab le f or the p1 por ts . other bits are reser v ed and alw a ys read as 0. d[7:0] px oen[7:0]: px [7:0] port output enable bits enables or disables port outputs. 1 (r/w): enabled 0 (r/w): disabled (def ault) pxoeny is the output enable bit that corresponds directly to pxy port. setting to 1 enables output and the data set in pxouty is output from the port pin. output is disabled when pxoeny is set to 0, and the port pin is set into high-impedance status. the peripheral module determines whether output is enabled or disabled when the port is used for a peripheral module function. refer to t able 10.3.1 for more information on input/output status for ports, including settings other than for the pxoen re gister . px port pull-up control registers (px_pu) register name ad dress bit name function setting init. r/w remarks px port pull-up control register (px_pu) 0x5203 0x5213 (8 bits) d7C0 pxpu[7:0] px[7:0] por t pull-up enab le 1 enab le 0 disab le 1 (0xff) r/w note: p1pu[3:0] only are a v ailab le f or the p1 por ts . other bits are reser v ed and alw a ys read as 0. d[7:0] px pu[7:0]: px [7:0] port pull-up enable bits enables or disables the pull-up resistor included in each port. 1 (r/w): enabled (def ault) 0 (r/w): disabled
10 i/o por ts (p) s1c17651 t echnical m anual seiko epson corporation 10-7 pxpuy is the pull-up control bit that corresponds directly to the pxy port. setting to 1 enables the pull- up resistor and the port pin will be pulled up when output is disabled (pxoeny = 0). when pxpuy is set to 0, the pin will not be pulled up. when output is enabled (pxoeny = 1), the pxpuy setting is ignored, and the pin is not pulled up. i/o ports that are not used should be set with pull-up en abled. the pxpuy setting is also ignored if a pin function other than pxy i/o port is selected. in this case, the pull-up resis- tor is automatically enabled/disabled according to the pin function selected. p0 port interrupt mask register (p0_imsk) register name ad dress bit name function setting init. r/w remarks p0 port interrupt mask register (p0_imsk) 0x5205 (8 bits) d7C0 p0ie[7:0] p0[7:0] por t interr upt enab le 1 enab le 0 disab le 0 r/w note: this register is a v ailab le f or the p0 por ts . d[7:0] p0ie[7:0]: p0[7:0] port interrupt enable bits enables or disables each port interrupt. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting p0iey to 1 enables the corresponding p0y port input interrupt, while setting to 0 disables the in- terrupt. status changes for the input pins with interrupt disabled do not af fect interrupt occurrence. p0 port interrupt edge select register (p0_edge) register name ad dress bit name function setting init. r/w remarks p0 port interrupt edge select register (p0_edge) 0x5206 (8 bits) d7C0 p0edge[7:0] p0[7:0] por t interr upt edge select 1 f alling edge 0 rising edge 0 r/w note: this register is a v ailab le f or the p0 por ts . d[7:0] p0edge[7:0]: p0[7:0] port interrupt edge select bits selects the input signal edge for generating each port interrupt. 1 (r/w): f alling edge 0 (r/w): rising edge (def ault) port interrupts are generated at the input signal f alling edge when p0edgey is set to 1 and at the rising edge when set to 0. p0 port interrupt flag register (p0_iflg) register name ad dress bit name function setting init. r/w remarks p0 port interrupt flag register (p0_iflg) 0x5207 (8 bits) d7C0 p0if[7:0] p0[7:0] por t interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. note: this register is a v ailab le f or the p0 por ts . d[7:0] p0if[7:0]: p0[7:0] port interrupt flag bits these are interrupt flags indicating the interrupt cause occurrence status. 1 (r): interrupt cause occurred 0 (r): no interrupt cause occurred (def ault) 1 (w): reset flag 0 (w): ignored p0ify is the interrupt flag correspon ding to the indi vidual eight p0 ports. it is set to 1 at the specif ied edge (rising or f alling edge) of the input signal. when the corresponding p0iey/p0_imsk re gister has been set to 1, a port interrupt request signal is also output to the itc at the same time. an interrupt is generated if the itc and s1c17 core interrupt conditions are satisf ied.
10 i/o por ts (p) 10-8 seiko epson corporation s1c17651 t echnical m anual p0ify is reset by writing 1. notes: ? the p por t module interr upt flag p0ify m ust be reset in the interr upt handler routine after a por t interr upt has occurred to pre v ent recurr ing interr upts . ? t o pre v ent gener ating unnecessar y interr upts , reset the rele v ant p0ify bef ore enab ling in- terr upts f or the required por t using p0iey/p0_imsk register . p0 port chattering filter control register (p0_chat) register name ad dress bit name function setting init. r/w remarks p0 port chattering filter control register (p0_chat) 0x5208 (8 bits) d7 C reser v ed C C C 0 when being read. d6C4 p0cf2[2:0] p0[7:4] chatter ing filter time select p0cf2[2:0] filter time 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 16384/f pclk 8192/f pclk 4096/f pclk 2048/f pclk 1024/f pclk 512/f pclk 256/f pclk none d3 C reser v ed C C C 0 when being read. d2C0 p0cf1[2:0] p0[3:0] chatter ing filter time select p0cf1[2:0] filter time 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 16384/f pclk 8192/f pclk 4096/f pclk 2048/f pclk 1024/f pclk 512/f pclk 256 /f pclk none note: this register is a v ailab le f or the p0 por ts . d7 reserved d[6:4] p0cf2[2:0]: p0[7:4] chattering filter time select bits conf igures the chattering f ilter circuit for the p0[7:4] ports. d3 reserved d[2:0] p0cf1[2:0]: p0[3:0] chattering filter time select bits conf igures the chattering f ilter circuit for the p0[3:0] ports. the p0 ports include a chattering f ilter circuit for k e y entry that can be disabled or enabled with a check time specif ied indi vidually for the four p0[3:0] and p0[7:4] ports using p0cf1[2:0] and p0cf2[2:0], re specti v ely . 8.2 chatter ing filter function settings t ab le 10. p0cf1[2:0]/p0cf2[2:0] chec k time * 0x7 16384/f pclk (8 ms) 0x6 8192/f pclk (4 ms) 0x5 4096/f pclk (2 ms) 0x4 2048/f pclk (1 ms) 0x3 1024/f pclk (512 s) 0x2 512/f pclk (256 s) 0x1 256/f pclk (128 s) 0x0 no chec k time (off) (def ault: 0x0, * when pclk = 2 mhz) notes: ? an une xpected interr upt ma y occur after sleep status is canceled if the slp instr uction is e x ecuted while the chatter ing filter function is enab led. the c hatter ing filter m ust be disab led bef ore placing the cpu into sleep status . ? the chatter ing filter chec k time ref ers to the maxim um pulse width that can be filtered. gen- er ating an input interr upt requires an input time of twice the chec k time .
10 i/o por ts (p) s1c17651 t echnical m anual seiko epson corporation 10-9 ? t h e p0 p o r t i n t e r r u p t m u s t b e d i s a b l e d b e f o r e s e t t i n g t h e p0_ c h a t r e g i s t e r . s e t t i n g t h e register while the interr upt is enab led ma y gener ate inadv er tent p0 interr upt. also the chat- ter ing filter circuit requires a maxim um of twice the chec k time f or stabilizing the oper ation status . bef ore enab ling the interr upt, mak e sure that the stabilization time has elapsed. p0 port key-entry reset configuration register (p0_krst) register name ad dress bit name function setting init. r/w remarks p0 port key- entry reset configuration register (p0_krst) 0x5209 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 p0krst[1:0] p0 por t k e y-entr y reset configur ation p0krst[1:0] configur ation 0x0 r/w 0x3 0x2 0x1 0x0 p0[3:0] p0[2:0] p0[1:0] disab le d[7:2] reserved d[1:0] p0krst[1:0]: p0 port key-entry reset configuration bits selects the port combination used for p0 port k e y-entry reset. 8.3 p0 p or t k e y-entr y reset settings t ab le 10. p0krst[1:0] p or ts used f or resetting 0x3 p00, p01, p02, p03 0x2 p00, p01, p02 0x1 p00, p01 0x0 not used (def ault: 0x0) the k e y-entry reset function performs an initial reset by inputting lo w le v el simultaneously to the ports selected here. f or e xample, if p0krst[1:0] is set to 0x3, an initial reset is performed when the four ports p00 to p03 are simultaneously set to lo w le v el. set p0krst[1:0] to 0x0 when t his reset function is not used. notes: ? the p0 por t k e y-entr y reset function is disab led at initial reset and cannot be used f or po w- er-on reset. ? when using the p0 por t k e y-entr y reset function, mak e sure that the designated input por ts will not be sim ultaneously set to lo w le v el while the application prog r am is r unning. px port input enable registers (px_ien) register name ad dress bit name function setting init. r/w remarks px port input enable register (px_ien) 0x520a 0x521a (8 bits) d7C0 pxien[7:0] px[7:0] por t input enab le 1 enab le 0 disab le 1 (0xff) r/w note: p1ien[3:0] only are a v ailab le f or the p1 por ts . other bits are reser v ed and alw a ys read as 0. d[7:0] px ien[7:0]: px [7:0] port input enable bits enables or disables port inputs. 1 (r/w): enable (def ault) 0 (r/w): disable pxieny is the input enable bit that corresponds directly to the pxy port. setting to 1 enables input and the corresponding port pin input or output signal le v el can be read out from the px_in re gister . setting to 0 disables input. refer to t able 10.3.1 for more information on port input/output status, including settings other than for the px_ien re gister .
10 i/o por ts (p) 10-10 seiko epson corporation s1c17651 t echnical m anual p0[3:0] port function select register (p00_03pmux) register name ad dress bit name function setting init. r/w remarks p0[3:0] port function select register (p00_03pmux) 0x52a0 (8 bits) d7C6 p03mux[1:0] p03 por t function select p03mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 lfr o regmon excl0 p03 d5C4 p02mux[1:0] p02 por t function select p02mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 regmon fout a sclk0 p02 d3C2 p01mux[1:0] p01 por t function select p01mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed sout0 p01 d1C0 p00mux[1:0] p00 por t function select p00mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed sin0 p00 the p00 to p03 port pins are shared wit h the peripheral module pins. this re gister is used to select ho w the pins are used. d[7:6] p03mux[1:0]: p03 port function select bits 0x3 (r/w): lfr o (lcd) 0x2 (r/w): regmon (tr) 0x1 (r/w): excl0 (t16a2 ch.0) 0x0 (r/w): p03 port (def ault) d[5:4] p02mux[1:0]: p02 port function select bits 0x3 (r/w): regmon (tr) 0x2 (r/w): fout a (clg) 0x1 (r/w): sclk0 (u ar t) 0x0 (r/w): p02 port (def ault) d[3:2] p01mux[1:0]: p01 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): sout0 (u ar t) 0x0 (r/w): p01 port (def ault) d[1:0] p00mux[1:0]: p00 port function select bits 0x3 (r/w): r eserv ed 0x2 (r/w): reserv ed 0x1 (r/w): sin0 (u ar t) 0x0 (r/w): p00 port (def ault)
10 i/o por ts (p) s1c17651 t echnical m anual seiko epson corporation 10-11 p0[7:4] port function select register (p04_07pmux) register name ad dress bit name function setting init. r/w remarks p0[7:4] port function select register (p04_07pmux) 0x52a1 (8 bits) d7C6 p07mux[1:0] p07 por t function select p07mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed sdo0 #bz p07 d5C4 p06mux[1:0] p06 por t function select p06mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed sdi0 bz p06 d3C2 p05mux[1:0] p05 por t function select p05mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed #spiss0 t outb0/capb0 p05 d1C0 p04mux[1:0] p04 por t function select p04mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed t out a0/cap a0 p04 the p04 to p07 port pins ar e shared with the peripheral module pins. this re gister is used to select ho w the pins are used. d[7:6] p07mux[1:0]: p07 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): sdo0 (spi ch.0) 0x1 (r/w): #bz (snd) 0x0 (r/w): p07 port (def ault) d[5:4] p06mux[1:0]: p06 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): sdi0 (spi ch.0) 0x1 (r/w): bz (snd) 0x0 (r/w): p06 port (def ault) d[3:2] p05mux[1:0]: p05 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): #spiss0 (spi ch.0) 0x1 (r/w): t outb0 (t16a2 ch.0 comparator mode) or capb0 (t16a2 ch.0 capture mode) 0x0 (r/w): p05 port (def ault) d[1:0] p04mux[1:0]: p04 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): t out a0 (t16a2 ch.0 comparator mode) or cap a0 (t16a2 ch.0 capture mode) 0x0 (r/w): p04 port (def ault)
10 i/o por ts (p) 10-12 seiko epson corporation s1c17651 t echnical m anual p1[3:0] port function select register (p10_13pmux) register name ad dress bit name function setting init. r/w remarks p1[3:0] port function select register (p10_13pmux) 0x52a2 (8 bits) d7C6 p13mux[1:0] p13 por t function select p13mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed p13 dst2 d5C4 p12mux[1:0] p12 por t function select p12mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed #bz p12 dsio d3C2 p11mux[1:0] p11 por t function select p11mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed bz p11 dclk d1C0 p10mux[1:0] p10 por t function select p10mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed spiclk0 foutb p10 the p10 to p13 port pins are shared with t he peripheral module pins. this re gister is used to select ho w the pins are used. d[7:6] p13mux[1:0]: p13 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): p13 port 0x0 (r/w): dst2 (dbg) (def ault) d[5:4] p12mux[1:0]: p12 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): #bz (snd) 0x1 (r/w): p12 port 0x0 (r/w): dsio (dbg) (def ault) d[3:2] p11mux[1:0]: p11 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): bz (snd) 0x1 (r/w): p11 port 0x0 (r/w): dclk (dbg) (def ault) d[1:0] p10mux[1:0]: p10 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): spiclk 0 (spi ch.0) 0x1 (r/w): foutb (clg) 0x0 (r/w): p10 port (def ault)
11 8-bit timer (t8) s1c17651 t echnical m anual seiko epson corporation 11-1 8-bit t imer (t8) 11 t8 module over vie w 11.1 the s1c17651 includes an 8-bit timer module (t8). the features of the t8 module are listed belo w . ? consists of one timer channel (t8 ch.0). ? 8-bit presettable do wn counter with an 8-bit reload data re gister for setting the preset v alue ? generates the spi operating clock from the counter underflo w signals. ? generates underflo w interrupt signals to the inte rrupt controller (itc). ? an y desired time interv als and serial transfer rates can be programmed by selecting an appropriate count clock and preset v alue. figure 11.1.1 sho ws the t8 conf iguration. reload data register t8_trx prun df[3:0] underflow run/stop control internal data bus count clock select interrupt request clock outputs to itc to spi pclk preser timer reset down counter t8_tcx control circuit count mode select trmd 8-bit timer ch.x divider (1/1C1/16k) clg 1.1 t8 configur ation figure 11. the t8 module consists of an 8-bit presettable do wn counter and an 8-bit reload data re gister holding the preset v alue. the timer counts do wn from the initial v alue set in the reload data re gister and outputs an underflo w signal when the counter underflo ws. the underflo w signal is used to generate an interrupt and an internal serial interf ace clock. the underflo w c yc le can be programmed by selecting the count clock and reload data, enabling the applica- tion program to obtain time interv als and serial transfer rates as required. note: the letter x in register names ref ers to a channel n umber (0). example: t8_ctlx register ch.0: t8_ctl0 register
11 8-bit timer (t8) 11-2 seiko epson corporation s1c17651 t echnical m anual count cloc k 11.2 the count clock is generated by di viding the pclk clock into 1/1 to 1/16k. the di vision ratio can be selected from the 15 types sho wn belo w using df[3:0]/t8_clkx re gister . 2.1 pclk division ratio selection t ab le 11. df[3:0] division ratio df[3:0] division ratio 0xf reser v ed 0x7 1/128 0x e 1/16384 0x6 1/64 0xd 1/8192 0x5 1/32 0xc 1/4096 0x4 1/16 0xb 1/2048 0x3 1/8 0xa 1/1024 0x2 1/4 0x9 1/512 0x1 1/2 0x8 1/256 0x0 1/1 (def ault: 0x0) notes: ? the cloc k gener ator (clg) m ust be configured to supply pclk to the per ipher al modules be- f ore r unning the timer . ? mak e sure the counter is halted bef ore setting the count cloc k. f or detailed information on the clg control, see the clock generator (clg) chapter . count mode 11.3 t h e t8 m o d u l e f e a t u r e s t w o c o u n t m o d e s : r e p e a t m o d e a n d o n e - s h o t m o d e . t h e s e m o d e s a r e s e l e c t e d u s i n g trmd/t8_ctlx re gister . repeat mode (trmd = 0, default) setting trmd to 0 sets t8 to repeat mode. in this mode, once the count starts, the timer continues running until stopped by the application program. when the counter underflo ws, the timer presets the reload data re gister v alue into the counter and continues the count. thus, the timer periodically outputs an underflo w pulse. t8 should be set to this mode to generate periodic in- terrupts at desired interv als or to generate a serial transfer clock. one-shot mode (trmd = 1) setting trmd to 1 sets t8 to one-shot mode. in this mode, the timer stops automatically as soon as the counter underflo ws. this means only one interrupt can be generated after the timer starts. note that the timer presets the reload data re gister v alue to the counter , then stops after an underflo w has occurred. t8 should be set to this mode to set a specif ic w ait time. reload data register and underflo w cyc le 11.4 the reload data re gister t8_trx is used to set the initial v alue for the do wn counter . the initial counter v alue set in the reload data re gister is preset to the do wn counter if the timer is reset or the coun- ter underflo ws. if the timer is started after resetting, it counts do wn from the reload v alue (initial v alue). this means that the reload v alue and the input clock frequenc y determine the time elapsed from the point at which the timer starts until the underflo w occurs (or betwe en underflo ws). the time determined is used to obtain the specif ied w ait time, the interv als between periodic interrupts, and the programmable serial interf ace transfer clock.
11 8-bit timer (t8) s1c17651 t echnical m anual seiko epson corporation 11-3 one-shot mode counter repeat mode counter 0 1 n-1 n n preset by resetting the timer preset by resetting the timer preset automatically underflow preset automatically (n = reload data) 0 1 n-1 n n underflow timer starts timer starts preset automatically 0 1 n-1 n underflow 4.1 preset timing figure 11. the underflo w c ycle can be calculated as follo ws: tr + 1 ct_clk underflo w interv al = [s] underflo w c ycle = [hz] ct_clk tr + 1 ct_clk: count clock frequenc y [hz] tr: reload data (0C255) timer reset 11.5 the timer is reset by writing 1 to preser/t8_ctlx re gister . the reload data is preset and the counter is initial- ized. timer r un/st op contr ol 11.6 mak e the follo wing set tings before starting the timer . (1) select the count clock. see section 11.2. (2) set the count mode (one-shot or repeat). see section 11.3. (3) calculate the initial counter v alue and set it to the reload data re gister . see section 11.4. (4) reset the timer to preset the counter to the initial v alue. see section 11.5. (5) when using timer interrupts, set the interrupt le v el and enable interrupts for the rele v ant timer channel. see section 11.8. t o start the timer , write 1 to pr un/t8_ctlx re gister . t h e t i m e r s t a r t s c o u n t i n g d o w n f r o m t h e i n i t i a l v a l u e o r f r o m t h e c u r r e n t c o u n t e r v a l u e i f n o i n i t i a l v a l u e w a s p r e s e t . when the counter underflo ws, the timer outputs an underflo w pulse and presets the counter to the initial v alue. an interrupt request is sent simultaneously to the interrupt controlle r (itc). in one-shot mode, the timer stops counting. in repeat mode, the timer continues counting from the reloaded initial v alue. write 0 to pr un to stop the timer via the application program. the counter stops counting and retains the current counter v alue until either the timer is reset or restarted. t o restart the count from the initial v alue, the timer should be reset before writing 1 to pr un.
11 8-bit timer (t8) 11-4 seiko epson corporation s1c17651 t echnical m anual count clock preser write prun counter interrupt request 0 1 n-1 n n count clock preser write prun counter interrupt request 0 1 n-1 n n 0 1 n-1 n n-1 one-shot mode repeat mode reset by hardware set by software set by software reset by software 6.1 count oper ation figure 11. t8 output signals 11.7 the t8 module outputs underflo w pulses when the counter underflo ws. these pulses are used for timer interrupt requests. these pulses are also used to generate the serial transfer clock for the internal serial interf ace. the clock generated is sent to the spi module. use the follo wing equations to calculate the reload data re gister v alue for obtaini ng the desired transfer rate: ct_clk spi cloc k tr = - 1 bps 2 ct_clk: count clock frequenc y (hz) tr: reload data (0C255) bps: t ransfer rate (bits/s) t8 interrupts 11.8 the t8 module outputs an interrupt request to the interrupt controller (itc) when the counter underflo ws. underflo w interrupt when the counter underflo ws, the interrupt flag t8if/t8_intx re gister , which is pro vided for the t8 module , is set to 1. at the same time, an interrupt request is sent to the itc if t8ie/t8_intx re gister has been set to 1 (interrupt enabled). an interrupt is generated if the itc and s1c17 core interrupt conditions are satisf ied. if t8ie is set to 0 (interrupt disabled, def ault), no interrupt request will be sent to the itc. f or specif ic information on interrupt processing, see the interrupt controlle r (itc) chapter . notes: ? the t8 module interr upt flag t8if m ust be reset in the interr upt handler routine after a t8 in- terr upt has occurred to pre v ent recurr ing interr upts . ? reset t8if bef ore enab ling t8 interr upts with t8ie to pre v ent occurrence of unw anted inter- r upt. t8if is reset b y wr iting 1.
11 8-bit timer (t8) s1c17651 t echnical m anual seiko epson corporation 11-5 contr ol register details 11.9 9.1 list of t8 registers t ab le 11. ad dress register name function 0x4240 t8_clk0 t8 ch.0 count cloc k select register selects a count cloc k. 0x4242 t8_tr0 t8 ch.0 reload data register sets reload data. 0x4244 t8_tc0 t8 ch.0 counter data register counter data 0x4246 t8_ctl0 t8 ch.0 control register sets the timer mode and star ts/stops the timer . 0x4248 t8_int0 t8 ch.0 interr upt control register controls the interr upt. the t8 re gisters are described in deta il belo w . note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. t8 ch.x count clock select register (t8_clkx) register name ad dress bit name function setting init. r/w remarks t8 ch.x count clock select register (t8_clkx) 0x4240 (16 bits) d15C4 C reser v ed C C C 0 when being read. d3C0 df[3:0] count cloc k division r atio select df[3:0] division r atio 0x0 r/w s o u r c e c l o c k = p c l k 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 d[15:4] reserved d[3:0] df[3:0]: count clock division ratio select bits selects a pclk di vision ratio to generate the count clock. 9.2 pclk division ratio selection t ab le 11. df[3:0] division ratio df[3:0] division ratio 0xf reser v ed 0x7 1/128 0x e 1/16384 0x6 1/64 0xd 1/8192 0x5 1/32 0xc 1/4096 0x4 1/16 0xb 1/2048 0x3 1/8 0xa 1/1024 0x2 1/4 0x9 1/512 0x1 1/2 0x8 1/256 0x0 1/1 (def ault: 0x0) note: mak e sure the counter is halted bef ore setting the count cloc k. t8 ch.x reload data register (t8_trx) register name ad dress bit name function setting init. r/w remarks t8 ch.x reload data register (t8_trx) 0x4242 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 tr[7:0] reload data tr7 = msb tr0 = lsb 0x0 to 0xff 0x0 r/w d[15:8] reserved d[7:0] tr[7:0]: reload data bits sets the counter initial v alue. (def ault: 0x0) the reload data set in this re gister is preset to the counter when the timer is reset or the counter under - flo ws. if the timer is started after resetting, it counts do wn from the reload v alue (initial v alue).
11 8-bit timer (t8) 11-6 seiko epson corporation s1c17651 t echnical m anual this means that the reload v alue and the input clock frequenc y determine the time elapsed from the point at which the timer starts until the underflo w occurs (or between underflo ws). the time determined is used to obtain the desired w ait time, the interv als between periodic interrupts, and the programmable serial interf ace transfer clock. t8 ch.x counter data register (t8_tcx) register name ad dress bit name function setting init. r/w remarks t8 ch.x counter data register (t8_tcx) 0x4244 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 tc[7:0] counter data tc7 = msb tc0 = lsb 0x0 to 0xff 0xff r d[15:8] reserved d[7:0] tc[7:0]: counter data bits the counter data can be read out. (def ault: 0xf f) this re gister is read-only and cannot be written to. t8 ch.x control register (t8_ctlx) register name ad dress bit name function setting init. r/w remarks t8 ch.x control register (t8_ctlx) 0x4246 (16 bits) d15C5 C reser v ed C C C do not wr ite 1. d4 trmd count mode select 1 one shot 0 repeat 0 r/w d3C2 C reser v ed C C C 0 when being read. d1 preser timer reset 1 reset 0 ignored 0 w d0 prun timer r un/stop control 1 run 0 stop 0 r/w d[15:5] reserved (do not write 1.) d4 trmd: count mode select bit selects the count mode. 1 (r/w): one-shot mode 0 (r/w): repeat mode (def ault) setting trmd to 0 sets the timer to repeat mode. in this mode, once the count starts, the timer contin- ues to run until stopped by the application program. when the counter underflo ws, the timer presets the counter to the reload data re gister v alue and continues the count. thus, the timer periodically outputs an underflo w pulse. set the timer to this mode to generate periodic interrupts or to generate a serial trans- fer clock. setting trmd to 1 sets the timer to one-shot mode. in this mode, the 8-bit timer stops automatica lly as soon as the counter underflo ws. this means only one interrupt can be generated after the timer starts. note that the timer presets the counter to the reload data re gister v alue, then stops when an underflo w occurs. set the timer to this mode to set a specif ic w ait time. d[3:2] reserved d1 preser: timer reset bit resets the timer . 1 (w): reset 0 (w): ignored 0 (r): al w ays 0 when read (def ault) writing 1 to this bit presets the coun ter to the reload data v alue. d0 prun: timer run/stop control bit controls the timer r un/st op . 1 (r/w): run 0 (r/w): stop (def ault) the timer starts counting when pr un is written as 1 and stops when written as 0. when the timer is stopped, the counter data is retained until reset or until the ne xt r un state.
11 8-bit timer (t8) s1c17651 t echnical m anual seiko epson corporation 11-7 t8 ch.x interrupt control register (t8_intx) register name ad dress bit name function setting init. r/w remarks t8 ch.x inter - rupt control register (t8_intx) 0x4248 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 t8ie t8 interr upt enab le 1 enab le 0 disab le 0 r/w d7C1 C reser v ed C C C 0 when being read. d0 t8if t8 interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d[15:9] reserved d8 t8ie: t8 interrupt enable bit enables or disables interrupts caused by counter underflo ws. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting t8ie to 1 enables t8 interrupt requests to the itc; setting to 0 disables interrupts. d[7:1] reserved d0 t8if: t8 interrupt flag bit indicates whether the cause of counter underflo w interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored t8if is the t8 module interrupt flag that is set to 1 when the counter underflo ws. t8if is reset by writing 1.
12 16-bit pwm timer (t16a2) s1c17651 t echnical m anual seiko epson corporation 12-1 16-bit pwm t imer (t16a2) 12 t16a2 module over vie w 12.1 t h e s1c17651 i n c l u d e s a 16- b i t p w m t i m e r ( t16a2) m o d u l e t h a t c o n s i s t s o f c o u n t e r b l o c k s a n d c o m p a r a t o r / capture blocks. this timer can be used as an interv al timer , pwm w a v eform generator , e xternal e v ent counter and a count capture unit to measure e xternal e v ent periods. the features of t16a2 are listed belo w . ? one channel of 16-bit up counter b lock ? one channel of comparator/capture block ? allo ws selection of a count clock asynchronously with the cpu clock. ? supports e v ent counter function using an e xternal clock. ? the comparator compares the counter v alue with tw o specif ied comparison v alues to generate interrupts and a pwm w a v eform. ? the capture unit captures counter v alues using tw o e xternal trigger signals and generates interrupts. figure 12.1.1 sho ws the t16a2 conf iguration. capture circuit comparator circuit compare b buffer compare a buffer comparator circuit tout control circuit interrupt control circuit touta0 toutb0 capa0 capb0 interrupt request compare b/capture b register t16a_ccb0 compare a/capture a register t16a_cca0 counter block ch.0 comparator/capture block ch.0 counter t16a_tc0 osc3b 0 1 2 3 osc3a excl0 divider (1/1C1/16384) t16aclkd[3:0] /t16a_clk0 t16aclke /t16a_clk0 t16aclksrc[1:0] /t16a_clk0 osc1 divider (1/1C1/256) hcm, trmd, preset, prun /t16a_ctl0 compare a signal compare b signal divider (1/1C1/16384) gate clock controller ch.0 16-bit pwm timer (t16a2) cbufen /t16a_ctl0 cbufen /t16a_ctl0 t16a_iflg0 t16a_ccctl0 t16a_ien0 10 10 1.1 t16a2 configur ation figure 12. cloc k contr oller t16a2 includes a clock controller that generates the count clock for the counter . the clock source and di vision ratio can be selected with softw are. counter b loc k the counter block includes a 16-bit up-counter that operates with an osc3b, osc3a, or osc1 di vision clock, or the e xternal count clock input from outside the ic. the t16a2 module allo ws softw are to run and stop the counter , and to reset the counter v alue (cleared to 0) as well as selection of the count clock. the counter can also be reset by the compare b signal output from the comparator/capture block.
12 16-bit pwm timer (t16a2) 12-2 seiko epson corporation s1c17651 t echnical m anual comparator/capture b loc k the comparator/capture block pro vides a counter comparison function (comparator mode) and a count capture function (capture mode). when comparator mode is selected via softw are, the comparator/capture block can be used as a pwm w a v eform or clock generator . when capture mode is selected, this block can be used as a count capture unit for measuring e xternal e v ent periods/c yc les. the comparator circuit generates the compare a and b signals that represent matching between compare a/b re gister v alues (set via softw are) and the counter v alue, and outputs the signals to the t out control circuit and the interrupt control circuit. the t out control circuit generates a pwm or other signal from the compare a and b signals and outputs it to the e xternal t out ax and t outbx pins. the capture circuit loads the counter v alue to the capture a or b re gister using the cap ax or capbx input signal that represents e xternal e v ents issued as a trigger . the interrupt control circuit outputs an interrupt signal to the interrupt controller (itc) module according to the interrupt condition that has been set. comparator mode and capture mode cannot be used simultaneously in the same chan nel. note: the letter x in register and pin names ref ers to a channel n umber (0). example: t16a_ctlx register , t out ax pin ch.0: t16a_ctl0 register , t out a0 t16a2 input/output pins 12.2 t able 12.2.1 lists the input/output pins for the t16a2 module. 2.1 list of t16a2 pins t ab le 12. pin name i/o qty function excl0 (f or ch.0) i 1 exter nal cloc k input pins inputs an e xter nal cloc k f or the e v ent counter function. cap a0, capb0 (f or ch.0) i 2 counter-capture tr igger signal input pins (eff ectiv e in capture mode) t h e s p e c i f i e d e d g e ( f a l l i n g e d g e , r i s i n g e d g e , o r b o t h ) o f t h e s i g n a l i n p u t t o t h e c a p a x p i n c a p t u r e s t h e c o u n t e r d a t a i n t o t h e c a p t u r e a register . the capbx pin input signal captures t he counter data into the capture b register . t out a0, t outb0 (f or ch.0) o 2 timer gener ating signal output pins (eff ectiv e in compar ator mode) t16a2 has tw o output pins and the signals gener ated in diff erent condi- tions can be output. the t16a2 input/output pins (exclx, cap ax, capbx, t out ax, and t outbx) are shared with i/o ports and are initially set as general purpose i/o port pins. the pin functions mu st be switched using the port function select bits to use the general purpose i/o port pins as t16a2 input/output pins. f or detailed information on pin function switching, see the i/o ports (p) chapter . count cloc k 12.3 the clock controller includes a clock source selector , di viders, and a g ate circuit for controlling the count clock. osc1 clock external clock (exclx) osc3a clock counter ch.x divider (1/1C1/16k) divider (1/1C1/256) clock controller ch.x osc3b clock divider (1/1C1/16k) t16aclksrc[1:0] t16aclkd[3:0] t16aclke 3.1 cloc k controller figure 12.
12 16-bit pwm timer (t16a2) s1c17651 t echnical m anual seiko epson corporation 12-3 cloc k sour ce selection the clock source can be selected from osc3b, osc3a, osc1, or e xternal clock using t16a clksrc[1:0]/ t16a_clkx re gister . 3.1 cloc k source selection t ab le 12. t16a clksrc[1:0] cloc k sour ce 0x3 exter nal cloc k (exclx) 0x2 osc3a 0x1 osc1 0x0 osc3b (def ault: 0x0) when e xternal clock is selected, the timer can be used as an e v ent counter or for measuring pulse widths by inputting an e xternal clock or pulses. the table belo w lists the e xternal clock input pins. it is not necessary to switch their pin functions from general-purpose i/o port. ho we v er , do not set the i/o p ort to output mode. 3.2 exter nal cloc k input pins t ab le 12. channel external c loc k input pin t16a2 ch.0 excl0 internal c loc k division ratio selection when an internal clock (osc3b, osc3a, or osc1) is selected, use t16a clkd[3:0]/t16a_clkx re gister to select the di vision ratio. 3.3 inter nal cloc k division ratio selection t ab le 12. t16a clkd[3:0] division ratio cloc k sour ce = osc3b or osc3a cloc k sour ce = osc1 0xf reser v ed 0x e 1/16384 reser v ed 0xd 1/8192 reser v ed 0xc 1/4096 reser v ed 0xb 1/2048 reser v ed 0xa 1/1024 reser v ed 0x9 1/512 f256 (regulated 256 hz cloc k) 0x8 1/256 0x7 1/128 0x6 1/64 0x5 1/32 0x4 1/16 0x3 1/8 0x2 1/4 0x1 1/2 0x0 1/1 (def ault: 0x0) cloc k enab le clock supply to the counter is controlled using t16a clke/t16a_clkx re gister . the t16a clke def ault set- t ing is 0, which disables the clock supply . setting t16a clke to 1 sends the clock generated as abo v e to the counter . if t16a2 is not required, disable the clock supply to reduce current consumption. note: mak e sure the t16a2 count is stopped bef ore setting the count cloc k. t16a2 operating modes 12.4 the t16a2 module pro vides some operating modes to support v arious usages. this section describes the func tions of each operating mode and ho w to enter the mode.
12 16-bit pwm timer (t16a2) 12-4 seiko epson corporation s1c17651 t echnical m anual comparator mode and capture mode 12.4.1 the t16a_ccax and t16a_ccbx re gisters that are embedded in the comparator/capture block can be set to com- p a r a t o r m o d e o r c a p t u r e m o d e , i n d i v i d u a l l y . t h e t16a _ c c a x r e g i s t e r m o d e i s s e l e c t e d u s i n g c c a m d / t16a _ ccctlx re gister and the t16a_ccbx re gister mode is selected using ccbmd/t16a_ccctlx re gister . comparator mode (ccamd/ccbmd = 0, default) the comparator mo de compares the counter v alue and the comparison v alue set via softw are. it generates an interrupt and toggles the timer output signal le v el when the v alues are matched. the t16a_ccax and t16a_ ccbx re gisters function as the compare a and compare b re gisters that are used for loading compare v alues in this mode. when the counter reaches the v alue set in the compare a re gister during counting, the c omparator asserts the compare a signal. at the same time the compare a interrupt flag is set and the interrupt signal of the timer channel is output to the itc if the interrupt has been enabled. when the counter reaches the v alue set in the compare b re gister , the comparator asserts the compare b signal. at the same time the compare b interrupt flag is set and the interrupt signal of the timer cha nnel is output to the itc if the interrupt is enabled. furthermore, the counter is reset to 0. the compare a period (time from start of counting to occurrence of a compare a interrupt) and the compare b period (time from start of counting to occurrence of a compare b interrupt) can be calculated as follo ws: compare a period = (cca + 1) / ct_clk [second] compare b period = (ccb + 1) / ct_clk [sec ond] cca: compare a re gister v alue set (0 to 65535) ccb: compare b re gister v alue set (0 to 65535) ct_clk: count clock frequenc y [hz] the compare a and compare b signals are also used to generate a timer output w a v eform (t out). see section 12.6, t imer output control, for more information. t o generate pwm w a v eform, the t16a_ccax and t16a_ccbx re gisters must be both placed into comparator mode. compare b uff er s the compare b uf fer is used to synchronize the comparison data update timings and the counter operation. setting cb ufen/t16a_ctlx re gister to 1 enables the compare b uf fer . the compare a and b signals will be generated by comparing the counter v alues with the compare a and b b uf fer v alues instead of the com- pare a and b re gister v alues. the compare a and b re gister v alues written vi a softw are are loaded to the compare a and b b uf fers when the compare b signal is generated. note: when wr iting data to the t16a_ccax or t16a_ccbx register successiv ely , data should be wr it- ten at inter v als of one or more t16a2 count cloc k cycles . capture mode (ccamd/ccbmd = 1) the capture mode captures the counter v alue when an e xternal e v ent such as a k e y entry occurs (at the specif ied edge of the e x ternal input signal). in this mode, the t16a_ccax and/or t16a_ccbx re gisters function as the capture a and/or capture b re gisters. the table belo w lists the input pins of the e xternal trigger signals used for capturing counter v alues. the pin function of the corresponding ports must be switched for trigger input in adv ance. see the i/o ports (p) chap- ter for switching the pin function. 4.1.1 lis t of counter capture t r igger signal input pins t ab le 12. channel t rig g er input pins capture a capture b t16a2 ch.0 cap a0 capb0 the trigger edge of the signal can be selected using the cap a trg[1:0]/t16a_ccctlx re gister for capture a and capbtrg[1:0]/t16a_ccctlx re gister for capture b.
12 16-bit pwm timer (t16a2) s1c17651 t echnical m anual seiko epson corporation 12-5 4.1.2 capture t r igger edge selection t ab le 12. cap a trg[1:0]/ capbtrg[1:0] t rig g er edg e 0x3 f alling edge and r ising edge 0x2 f alling edge 0x1 rising edge 0x0 not tr iggered (def ault: 0x0) when a specif ied trigger edge is input during counting, the current counter v alue is loaded to the capture re gis- ter . at the same time the capture a or capture b interrupt flag is set and the interrupt signal of the timer channel is output to the itc if the interrupt has been enabled. this interrupt can be used to read the captured data from the t16a_ccax or t16a_ccbx re gister . f or e xample, e xternal e v ent c ycles and pulse widths can be measured from the dif ference between tw o captured counter v alues read. if the captured data is o v erwritten by the ne xt trigger when the capture a or capture b interrupt flag has already been set, the o v erwrite interrupt flag wil l be set. this interrupt can be used to e x ecute an o v erwrite error han- dling. t o a v oid occurrence of unnecessary o v erwrite interrupt, the capture a or capture b interrupt flag must be reset after the captured data has been read from the t16a_ccax or t16a_ccbx re gister . notes: ? the correct captured data ma y not be obtained if the captured data is read at the same time the ne xt v alue is being captured. read the capture register twice to chec k if the read data is correct as necessar y . ? t o capture counter data proper ly , both the high and lo w per iod of the capx tr igger signal m ust be longer than the source cloc k cycle time . the setting of cap a trg[1:0] or capbtrg[1:0] is inef fecti v e in comparator mode. no counter capturing op- eration will be performed e v en if a trigger edge is specif ied. the captur e mode cannot generate/output the t out signal as no compare signal is generated. repeat mode and one-shot mode 12.4.2 t16a2 f e a t u r e s t w o c o u n t m o d e s : r e p e a t m o d e a n d o n e - s h o t m o d e . t h e c o u n t m o d e i s s e l e c t e d u s i n g t r m d / t16a_ctlx re gister . repeat mode (trmd = 0, default) setting trmd to 0 sets the corresponding counter to repeat mode. in this mode, once the count starts, the counter continues runnin g until stopped by the application program. the counter continues the count e v en if the counter returns to 0 due to a counter o v erflo w . the counter should be set to this mode to generate periodic interrupts at desired interv als or to generate a timer output w a v eform. one-shot mode (trmd = 1) setting trmd to 1 sets the corresponding counter to one-shot mode. in this mode, the counter stops automatic ally as soon as the compare b signal is generated. the counter should be set to this mode to set a specif ic w ait time or for pulse width measurement. normal cloc k mode and half cloc k mode 12.4.3 t16a2 supports half clock mode to control the duty ratio of the pwm output w a v eform with high accurac y . in half clock mode, t16a2 uses the dual-edge counter , which counts at the rising and f alling edges of the count clock, to compare with the compare a re gister . this mak es it possible to control the duty ratio with double accurac y as compared to normal clock mode. use hcm/t16a_ctlx re gister to select half clock mode. normal c loc k mode (hcm = 0, default) in normal clock mode, t16a2 generates a compare a signal when the t16a_tcx re gister v alue matches the t16a_ccax re gister .
12 16-bit pwm timer (t16a2) 12-6 seiko epson corporation s1c17651 t echnical m anual half c loc k mode (hcm = 1) in half clock mode, t16a2 generates a compare a signal when the dual-edge counter v alue matches the t16a_ ccax re gister . notes: ? t16a2 m ust be placed into compar ator mode to set half cloc k mode , as it is eff ectiv e only when pwm w a v ef or m is gener ated. be sure to set t16a2 to nor mal cloc k mode (hcm = 0) under a condition sho wn belo w . (1) when t16a2 is placed into capture mode (2) when t out amd/t16a_ccctlx register is set to 0x2 or 0x3 (3) when t outbmd/t16a_ccctlx register is set to 0x2 or 0x3 ? the dual-edge counter v alue cannot be read. ? do not use the compare a interr upt in half cloc k mode . ? in half cloc k mode , the t16a_ccbx register setting v alue m ust be less than [t16a_ccax set- ting v alue / 2 + 0x8000]. counter contr ol 12.5 counter reset 12.5.1 the counter can be reset to 0 by writing 1 to preset/t16a_ctlx re gister . normally , the counter should be reset by writing 1 to this bit before starting the count. the counter is reset by the hardw are if the counter reaches the compare b re gister v alue after the count starts. counter r un/st op contr ol 12.5.2 mak e the follo wing settings before starting the count operation. (1) switch the input/output pin functions to be used for t16a2. refer to the i/o port (p) chapter . (2) select operating modes. see section 12.4. (3) select the clock source. see section 12.3. (4) conf igure the timer outputs (t out). see section 12.6. (5) if using interrupts, set the interrupt le v el and enable the t16a2 interrupts. see section 12.7. (6) reset the counter to 0. see section 12.5.1. (7) set comparison data (in comparator mode). see sec tion 12.4.1. t16a2 pro vides pr un/t16a_ctlx re gister to control the counter operation. th e cou nt er st art s cou nt in g whe n 1 is wri tt en to pr un. wri ti ng 0 to pr un di sab les clo ck in pu t and st op s th e count. this control does not af fect the counter data. the counter data is retained e v en when the count is halted, allo wing resumption of the count from that data. if pr un and preset are written as 1 simultaneou sly , the counter starts counting after reset. reading counter v alues 12.5.3 the counter v alue can be read from t16a2tc[15:0]/t16a_tcx re gister e v en if the counter is running. ho we v er , the counter v alue should be read at once using a 16-bit transfer instruction. if data is read twice using an 8-bit trans- fer instruction, the correct v alue may not be obtained due to occurrence of count up between rea dings.
12 16-bit pwm timer (t16a2) s1c17651 t echnical m anual seiko epson corporation 12-7 counter operation and interrupt timing char ts 12.5.4 comparator mode prun preset t16a_ccax t16a_ccbx count clock t16a_tcx reset compare a interrupt reset and compare b interrupt compare a interrupt reset and compare b interrupt 01 2 3 4 5 0 1 2 3 4 5 0 1 0x2 0x5 5.4.1 oper ation timing in compar ator mode figure 12. capture mode prun preset cap(a) cap(b) count clock t16a_tcx t16a_ccax t16a_ccbx (when capatrg[1:0] = 0x1, capbtrg[1:0] = 0x3) reset capture a interrupt capture b interrupt capture b interrupt (and capture b overwrite interrupt if capbif = 1) 01 2 3 4 5 6 7 8 9 10 11 12 13 3 6 11 5.4.2 oper ation timing in capture mode figure 12. timer output contr ol 12.6 the timer that has been set in comparator mode can generate t out signals using the compare a and compare b signals and can output it to e xternal de vices. t16a2 pro vides tw o t out outputs, thus the t16a2 module can out- put up to four t out signals. figure 12.6.1 sho ws the t out output circuit. tout a output control compare a signal compare b signal toutamd[1:0] toutainv toutax tout b output control compare a signal compare b signal toutbmd[1:0] toutbinv toutbx comparator/capture block ch.x 6.1 t out output circuit figure 12. t16a2 includes tw o t out output circuits and their signal generation and output can be controlled indi vidually . al- though the output circuit and re gister names use letters a and b to distinguish tw o systems, it does not mean that the y correspond to compare a and b signals.
12 16-bit pwm timer (t16a2) 12-8 seiko epson corporation s1c17651 t echnical m anual t out output pins t able 12.6.1 lists correspondence between the t out pins and the timer channels. the pin function of the cor - responding ports must be switched for t out output in adv ance. see the i/o ports (p) chapter for switching the pin function. 6.1 list of t out output pins t ab le 12. channel t out output pin system a system b t16a2 ch.0 t out a0 t outb0 t out g eneration mode t out amd[1:0]/t16a_ccctlx re gister (for system a) or t outbmd[1:0]/t16a_ccctlx re gister (for sys- tem b) is used to set ho w the t out signal is changed by the compare a and compare b signals. 6.2 t out gener ation mode t ab le 12. t out amd[1:0]/ t outbmd[1:0] when compare a occur s when compare b occur s 0x3 no change t oggle 0x2 t oggle no change 0x1 rise f all 0x0 disab le output (def ault: 0x0) t out amd[1:0] and t outbmd[1:0] are also used to turn the t out outputs on and of f. t out signal polarity selection b y d e f a u l t , a n a c t i v e h i g h o u t p u t s i g n a l i s g e n e r a t e d . t h i s l o g i c c a n b e i n v e r t e d u s i n g t o u t a i n v / t16a _ c c c t l x r e g i s t e r ( f o r s y s t e m a ) o r t o u t b i n v / t16a _ c c c t l x r e g i s t e r ( f o r s y s t e m b ) . w r i t i n g 1 t o t out ainv/t outbinv sets the timer to generate an acti v e lo w t out signal. resetting the counter sets the t out signal to the inacti v e le v el. figure 12.6.2 illustrates the t out output w a v eform. count clock preset prun counter value compare a signal compare b signal tout(a) output (toutamd[1:0] = 0x0, toutainv = 0) (toutamd[1:0] = 0x0, toutainv = 1) (toutamd[1:0] = 0x1, toutainv = 0) (toutamd[1:0] = 0x1, toutainv = 1) (toutamd[1:0] = 0x2, toutainv = 0) (toutamd[1:0] = 0x2, toutainv = 1) (toutamd[1:0] = 0x3, toutainv = 0) (toutamd[1:0] = 0x3, toutainv = 1) 1 2 3 4 5 0 0 1 2 3 4 5 0 1 2 3 4 5 0 1 (when t16a_ccax = 3, t16a_ccbx = 5) 6.2 t out output w a v ef or m figure 12.
12 16-bit pwm timer (t16a2) s1c17651 t echnical m anual seiko epson corporation 12-9 pwm wa vef orm output timings normal c loc k mode (hcm = 0) count clock t16a_tcx toutax/toutbx t16a_ccax (when toutamd[1:0] = toutbmd[1:0] = 0x1 and toutainv = toutbinv = 0) n0 0 12 n-1 n0 1 1 2 n-2 n-1 (n = t16a_ccbx) count clock t16a_tcx toutax/toutbx example: hcm = 0, t16a_ccax = 1, and t16a_ccbx = 5 (when toutamd[1:0] = toutbmd[1:0] = 0x1 and toutainv = toutbinv = 0) 5 012 450 1 3 6.3 pwm w a v ef or m output timings in nor mal cloc k mode figure 12. half c loc k mode (hcm = 1) count clock t16a_tcx dual-edge counter toutax/toutbx t16a_ccax (when toutamd[1:0] = toutbmd[1:0] = 0x1 and toutainv = toutbinv = 0) n 2n 0 C0 0 1234 2n-3 2n-2 2n-1 2n C01 12 n-1 n0 1 1 2 3 4 2n-4 2n-3 2n-2 2n-1 (n = t16a_ccbx) count clock t16a_tcx dual-edge counter toutax/toutbx example: hcm = 1, t16a_ccax = 1, and t16a_ccbx = 5 (when toutamd[1:0] = toutbmd[1:0] = 0x1 and toutainv = toutbinv = 0) 5 10 0 C01234 789 10 C01 12 450 1 56 3 6.4 pwm w a v ef or m output timings in half cloc k mode figure 12. t16a2 interrupts 12.7 the t16a2 module can generate the follo wing six kinds of interrupts: ? compare a interrupt (in comparator mode) ? compare b interrupt (in comparator mode) ? capture a interrupt (in capture mode) ? capture b interrupt (in capture mode) ? capture a o v erwrite interrupt (in capture mode) ? capture b o v erwrite interrupt (in c apture mode) the t16a2 module outputs a single interrupt signal shared by the abo v e interrupt causes to the interrupt controller (itc). read the interrupt flags in the t16a2 module to identify the interrupt cause that has been occurred.
12 16-bit pwm timer (t16a2) 12-10 seiko epson corporation s1c17651 t echnical m anual interrupts in comparator mode compare a interrupt this interrupt request is generated when the counter matches the compare a re gister v alue during counting in comparator mode. it sets the interrupt flag caif/t16a_iflgx re gister in the t16a2 module to 1. t o use this interrupt, set caie/t16a_ienx re gister to 1. if caie is set to 0 (def ault), interrupt requests for this cause is not sent to the itc. compare b interrupt this interrupt request is generated when the counter matches the compare b re gister v alue during counting in comparator mode. it sets the interrupt flag cbif/t16a_iflgx re gister in the t16a2 module to 1. t o use this interrupt, set cbie/t16a_ienx re gister to 1. if cbie is set to 0 (def ault), interrupt requests for this cause is not sent to the itc. interrupts in capture mode cap ture a interrupt this interrupt request is generated when the counter v alue is captured in the capture a re gister by an e xter - nal trigger during counting in capture mode. it sets the interrupt flag cap aif/t16a_iflgx re gister in the t16a2 module to 1. t o use this interrupt, set cap aie/t16a_ienx re gister to 1. if cap aie is set to 0 (def ault), interrupt re- quests for this cause is not sent to the itc . capture b interrupt this interrupt request is generated when the counter v alue is captured in the capture b re gister by an e xter - nal trigger during counting in capture mode. it sets the interrupt flag capbif/t16a_iflgx re gister in the t16a2 module to 1. t o use this interrupt, set capbie/t16a_ienx re gister to 1. if capbie is set to 0 (def ault), interrupt re- quests for this cause is not sent to th e itc. capture a o verwrite interrupt this interrupt request is generated if the capture a re gister is o v erwritten by a ne w e xternal trigger when the capture a interrupt flag cap aif has been set (a counter v alue has already been loaded to the capture a re gister). it sets the interrupt flag cap a o wif/t16a_iflgx re gister in the t16a2 module to 1. t o u s e t h i s i n t e r r u p t , s e t c a p a o w i e / t16a _ i e n x r e g i s t e r t o 1. i f c a p a o w i e i s s e t t o 0 ( d e f a u l t ) , interrupt requests for this cause is not sent to the itc. cap a o wif will be set if the capture a re gister is o v erwritten when cap aif has been set re g ardless of whether the capture a re gister has been read or not. therefore, be sure to reset cap aif immediately after the capture a re gister is read. capture b o verwrite interrupt this interrupt request is genera ted if the capture b re gister is o v erwritten by a ne w e xternal trigger when the capture b interrupt flag capbif has been set (a counter v alue has already been loaded to the capture b re gister). it sets the interrupt flag capbo wif/t16a_iflgx re gister in the t16a2 module to 1. t o u s e t h i s i n t e r r u p t , s e t c a p b o w i e / t16a _ i e n x r e g i s t e r t o 1. i f c a p b o w i e i s s e t t o 0 ( d e f a u l t ) , interrupt requests for this cause is not sent to the itc. capbo wif will be set if the capture b re gister is o v erwritten when capbif has been set re g ardless of whether the capture b re gister has been read or not. therefore, be sure to reset capbif immediately after the capture b re gister is read. if the interrupt flag is set to 1 when the interrupt has been enabled, the t16a2 module outputs an interrupt request to the itc. an interrupt is generated if the itc and s1c17 core interrupt conditions are satisf ied. f or more information on interrupt control re gisters and the operation when an interrupt occurs, see the interrupt controller (itc) chapter .
12 16-bit pwm timer (t16a2) s1c17651 t echnical m anual seiko epson corporation 12-11 notes: ? reset the interr upt flag bef ore enab ling interr upts with the interr upt enab le bit to pre v ent oc- currence of unw anted interr upt. the interr upt flag is reset b y wr iting 1. ? after an interr upt occurs , the interr upt flag in the t16a2 module m ust be reset in the interr upt handler routine . contr ol register details 12.8 8.1 list of t16a2 registers t ab le 12. ad dress register name function 0x5068 t16a_clk0 t16a cloc k control register ch.0 controls the t16a2 ch.0 cloc k. 0x5400 t16a_ctl0 t16a counter ch.0 control register controls the counter . 0x5402 t16a_tc0 t16a counter ch.0 data register counter data 0x5404 t16a_ccctl0 t16a compar ator/capture ch.0 control register controls the compar ator/capture b loc k and t out . 0x5406 t16a_cca0 t16a compare/capture ch.0 a data register co mpare a/capture a data 0x5408 t16a_ccb0 t16a compare/capture ch.0 b data register compare b/capture b data 0x540a t16a_ien0 t16a compare/capture ch.0 interr upt enab le register enab les/disab les interr upts . 0x540c t16a_iflg0 t16a compare/capture ch.0 interr upt flag register displa ys/sets interr upt occurrence status . the t16a2 re gisters are described in detail belo w . note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. t16a clock control register ch. x (t16a_clkx) register name ad dress bit name function setting init. r/w remarks t16a clock control register ch.x (t16a_clkx) 0x5068 (8 bits) d7C4 t16aclkd [3:0] cloc k division r atio select t16a clkd[3:0] division r atio 0x0 r/w osc3a or osc3b osc1 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 C 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 C C C C C C f256 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 d3C2 t16aclk src[1:0] cloc k source select t16a clksrc [1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 exter nal cloc k osc3a osc1 osc3b d1 C reser v ed C C C 0 when being read. d0 t16aclke cou nt cloc k enab le 1 enab le 0 disab le 0 r/w d[7:4] t16aclkd[3:0]: clock division ratio select bits selects the di vision ratio for generating the count clock when an internal clock (osc3b, osc3a, or osc1) is used.
12 16-bit pwm timer (t16a2) 12-12 seiko epson corporation s1c17651 t echnical m anual 8.2 inter nal cloc k division ratio selection t ab le 12. t16a clkd[3:0] division ratio cloc k sour ce = osc3b or osc3a cloc k sour ce = osc1 0xf reser v ed 0x e 1/16384 reser v ed 0xd 1/8192 reser v ed 0xc 1/4096 reser v ed 0xb 1/2048 reser v ed 0xa 1/1024 reser v ed 0x9 1/512 f256 (regulated 256 hz cloc k) 0x8 1/256 0x7 1/128 0x6 1/64 0x5 1/32 0x4 1/16 0x3 1/8 0x2 1/4 0x1 1/2 0x0 1/1 (def ault: 0x0) d[3:2] t16aclksrc[1:0]: clock source select bits selects the count clock source. 8.3 cloc k source selection t ab le 12. t16a clksrc[1:0] cloc k sour ce 0x3 exter nal cloc k (exclx) 0x2 osc3a 0x1 osc1 0x0 osc3b (def ault: 0x0) when using an e xternal clock as the count clock, supply the clock to the exclx pin. d1 reserved d0 t16aclke: count clock enable bit enables or disables the count clock supply to the counter . 1 (r/w): enabled (on) 0 (r/w): disabled (of f) (def ault) the t16a clke def ault setting is 0, which disables the clock supply . setting t16a clke to 1 sends the clock sel ected as abo v e to the counter . if timer operation is not required, disable the clock supply to reduce current consumption. t16a counter ch.x control register (t16a_ctlx) register name ad dress bit name function setting init. r/w remarks t16a counter ch.x control register (t16a_ctlx) 0x5400 (16 bits) d15C7 C reser v ed C C C 0 when being read. d6 hcm half cloc k mode enab le 1 enab le 0 disab le 0 r/w d5C4 C reser v ed C C C 0 when being read. d3 cbufen compare b uff er enab le 1 enab le 0 disab le 0 r/w d2 trmd count mode select 1 one-shot 0 repeat 0 r/w d1 preset counter reset 1 reset 0 ignored 0 w 0 when being read. d0 prun counter r un/stop control 1 run 0 stop 0 r/w d[15:7] reserved d6 hcm: half clock mode enable bit sets t16a2 to half clock mode. 1 (r/w): enabled (half clock mode) 0 (r/w): disabled (norma l clock mode) (def ault) setting hcm to 1 places t16a2 into half clock mode. in half clock mode, t16a2 uses the dual-edge counter , which counts at the rising and f alling edges of the count clock, to generate a compare a signal when the dual-edge counter v alue matches the t16a_ccax re gister . this mak es it possible to control the duty ratio with double accurac y as compared to normal clock mode.
12 16-bit pwm timer (t16a2) s1c17651 t echnical m anual seiko epson corporation 12-13 setting hcm to 0 places t16a2 into normal clock mode. in normal clock mode, t16a2 generates a compare a signal when the t16a_tcx re gister v alue matches the t16a_ccax re gister . notes: ? t16a2 m ust be placed into compar ator mode to set half cloc k mode , as it is eff ectiv e only when pwm w a v ef or m is gener ated. be sure to set t16a2 to nor mal cloc k mode under a condition sho wn belo w . (1) when t16a2 is pla ced into capture mode (2) when t out amd/t16a_ccctlx register is set to 0x2 or 0x3 (3) when t outbmd/t16a_ccctlx register is set to 0x2 or 0x3 ? the dual-edge counter v alue cannot be read. ? do not use the compare a interr upt in half cloc k mode . ? in half cloc k mode , the t16a_ccbx register setting v alue m ust be less than [t16a_ccax setting v alue / 2 + 0x8000]. d[5:4] reserved d3 cbufen: compare buffer enable bit enables or disables writing to the c ompare b uf fer . 1 (r/w): enabled 0 (r/w): disabled (def ault) setting cb ufen to 1 enables the compare b uf fer . the compare a and b signals will be generated by comparing the counter v alues with the compare a and b b uf fer v alues instead of the compare a and b re gister v alues. the compare a and b re gister v alues written via softw are are loaded to the compare a and b b uf fers when the compare b signal is generated. setting cb ufen to 0 disables the compare b uf fer . the compare a and b signals will be generated by comparing the counter v alues with the compare a and b re gister v alues. note: make sure the counter is halted (prun = 0) before setting cbufen. d2 trmd: count mode select bit selects the count mode. 1 (r/w): one-shot mode 0 (r/w): repeat mode (def ault) setting trmd to 0 sets the counter to repeat mode. in this mode, once the count starts, the counter con- tinues counting until stopped by t he application program. setting trmd to 1 sets the counter to one-shot mode. in this mode, the counter stops counting auto- matically as soon as the compare b signal is generated. d1 preset: counter reset bit resets the counter . 1 (w): reset 0 (w): ignored 0 (r): normally 0 when read out (def ault) writing 1 to this bit resets the counter to 0. d0 prun: counter run/stop control bit starts/stops the count. 1 (w): run 0 (w): stop 1 (r): counting 0 (r): stopped (de f ault) the counter starts counting when pr un is written as 1 and stops when written as 0. the counter data is retained e v en if the counter is stopped.
12 16-bit pwm timer (t16a2) 12-14 seiko epson corporation s1c17651 t echnical m anual t16a counter ch.x data register (t16a_tcx) register name ad dress bit name function setting init. r/w remarks t16a counter ch.x data register (t16a_tcx) 0x5402 (16 bits) d15C0 t16a2tc [15:0] counter data t16a2tc15 = msb t16a2tc0 = lsb 0x0 to 0xffff 0x0 r d[15:0] t16a2tc[15:0]: counter data bits counter data can be read out. (def ault: 0x0) the counter v alue can be read out e v en if the counter is running. ho we v er , the counter v alue should be read at once using a 16-bit transfer instruction. if data is read twice using an 8-bit transfer instruction, the correct v alue may not be obtained due to occurrence of count up between readings. t16a comparator/capture ch.x control register (t16a_ccctlx) register name ad dress bit name function setting init. r/w remarks t16a comparator/ capture ch.x control register (t16a_ccctlx) 0x5404 (16 bits) d15C14 capbtrg [1:0] capture b tr igger select capbtrg[1:0] t r igger edge 0x0 r/w 0x3 0x2 0x1 0x0 and none d13C12 toutbmd [1:0] t out b mode select t outbmd[1:0] mode 0x0 r/w 0x3 0x2 0x1 0x0 cmp b: or cmp a: or cmp a: , b: off d11C10 C reser v ed C C C 0 when being read. d9 toutbinv t out b in v er t 1 in v er t 0 nor mal 0 r/w d8 ccbmd t16a_ccb register mode select 1 capture 0 compar ator 0 r/w d7C6 capatrg [1:0] capture a tr igger select cap a trg[1:0] t r igger edge 0x0 r/w 0x3 0x2 0x1 0x0 and none d5C4 toutamd [1:0] t out a mode select t out amd[1:0] mode 0x0 r/w 0x3 0x2 0x1 0x0 cmp b: or cmp a: or cmp a: , b: off d3C2 C reser v ed C C C 0 when being read. d1 toutainv t out a in v er t 1 in v er t 0 nor mal 0 r/w d0 ccamd t16a_cca register mode select 1 capture 0 compar ator 0 r/w d[15:14] capbtrg[1:0]: capture b trigger select bits selects the trigger edge(s) of the e xternal signal (capbx) at which the counter v alue is captured in the capture b re gister . 8.4 capture b t r igger edge sel ection t ab le 12. capbtrg[1:0] t rig g er edg e 0x3 f alling edge and r ising edge 0x2 f alling edge 0x1 rising edge 0x0 not tr iggered (def ault: 0x0) capbtrg[1:0] are control bits for capture mode and are inef fecti v e in comparator mode. d[13:12] toutbmd[1:0]: tout b mode select bits c o n f i g u r e s h o w t h e t o u t b s i g n a l w a v e f o r m ( t o u t b x o u t p u t ) i s c h a n g e d b y t h e c o m p a r e a a n d compare b signals. these bits are also used to turn the t out b output on and of f. 8.5 t out b gener ation mode t ab le 12. t outbmd[1:0] when compare a occur s when compare b occur s 0x3 no change t oggle 0x2 t oggle no change 0x1 rise f all 0x0 disab le output (def ault: 0x0)
12 16-bit pwm timer (t16a2) s1c17651 t echnical m anual seiko epson corporation 12-15 t outbmd[1:0] are control bits for comparator mode and are inef fecti v e in capture mode. d[11:10] reserved d9 toutbinv: tout b invert bit selects the t out b signal (t outbx output) polarity . 1 (r/w): in v erted (acti v e lo w) 0 (r/w): normal (acti v e high) (def ault) writing 1 to t outbinv generates an acti v e lo w signal (of f le v el = high) for the t out b output. when t outbinv is 0, an acti v e high signal (of f le v el = lo w) is generated. t outbinv is a cont rol bit for comparator mode and is inef fecti v e in capture mode. d8 ccbmd: t16a_ccb register mode select bit selects the t16a_ccbx re gister function (comparator mode or capture mode). 1 (r/w): capture mode 0 (r/w): comparator mode (def ault) writing 1 to ccbmd conf igures the t16a_ccbx re gister as the capture b re gister (capture mode) to which the counter data will be loaded by the e xternal trigger signal. when ccbmd is 0, the t16a_ ccbx re gi ster functions as the compare b re gister (comparator mode) for writing a comparison v alue to generate the compare b signal. d[7:6] capatrg[1:0]: capture a trigger select bits selects the trigger edge(s) of the e xternal signal (cap ax) at which the counter v alue is captured in the capture a re gister . 8.6 capture a t r igger edge selection t ab le 12. cap a trg[1:0] t rig g er edg e 0x3 f alling edge and r ising edge 0x2 f alling edge 0x1 rising edge 0x0 not tr iggered (def ault: 0x0) cap a trg[1:0] are control bits for capture mode and are inef fecti v e in comparator mode. d[5:4] toutamd[1:0]: tout a mode select bits c o n f i g u r e s h o w t h e t o u t a s i g n a l w a v e f o r m ( t o u t a x o u t p u t ) i s c h a n g e d b y t h e c o m p a r e a a n d compare b signals. these bits are also used to turn the t out a output on and of f. 8.7 t out a gener ation mode t ab le 12. t out amd[1:0] when compare a occur s when compare b occur s 0x3 no change t oggle 0x2 t oggle no change 0x1 rise f all 0x0 disab le output (def ault: 0x0) t out amd[1:0] are control bits for comparator mode and are inef fecti v e in capture mode. d[3:2] reserved d1 toutainv: tout a invert bit selects the t out a signal (t out ax output) polarity . 1 (r/w): in v erted (acti v e lo w) 0 (r/w): normal (acti v e high) (def ault) writing 1 to t out ainv generates an acti v e lo w signal (o f f le v el = high) for the t out a output. when t out ainv is 0, an acti v e high signal (of f le v el = lo w) is generated. t out ainv is a control bit for comparator mode and is inef fecti v e in capture mode.
12 16-bit pwm timer (t16a2) 12-16 seiko epson corporation s1c17651 t echnical m anual d0 ccamd: t16a_cca register mode select bit selects the t16a_ccax re gister function (comparator mode or capture mode). 1 (r/w): capture mode 0 (r/w): comparator mode (def ault) writing 1 to ccamd conf igures the t16a_ccax re gister as the capture a re gister (capture mode) to which the counter data will be loaded by the e xternal trigger signal. when ccamd is 0, the t16a_ ccax re gister functions as the compare a re gister (comparator mode) for writing a comparison v alue to generate the compare a signal. t16a comparator/capture ch.x a data register (t16a_ccax) register name ad dress bit name function setting init. r/w remarks t16a comparator/ capture ch.x a data register (t16a_ccax) 0x5406 (16 bits) d15C0 cca[15:0] compare/capture a data cca15 = msb cca0 = lsb 0x0 to 0xffff 0x0 r/w d[15:0] cca[15:0]: compare/capture a data bits in compar ator mode (ccamd/ t16a_ccctlx register = 0) sets a compare a data, which will be compared with the counter v alue, through this re gister . when cb ufen/t16a_ctlx re gister is set to 0, compare a data will be set to the compare a re gister after a lapse of tw o t16a2 count clock c ycles from the time when it is written to this re gister . when cb ufen is set to 1, the data written to this re gister is loaded to the compare a b uf fer . the b uf fer contents are loaded into the compare a re gister when the compare b signal is generated. the compare a re gister is al w ays directly accessed when being read re g ardless of the cb ufen setting. the data set is compared with the counter data. when the counter reaches the comparison v alue set, the compare a signal is asserted and a cause of compare a interrupt occurs. furthermore, the t out output w a v eform changes when t out amd[1:0]/t16a_ccctlx re gister or t outbmd[1:0]/t16a_ ccctlx re gister is set to 0x2 or 0x1. these processes do not af fect the counter data and the count up operation. in capture mode (ccamd = 1) w h e n t h e c o u n t e r v a l u e i s c a p t u r e d a t t h e e x t e r n a l t r i g g e r s i g n a l ( c a p a x ) e d g e s e l e c t e d u s i n g cap a trg[1:0]/t16a_ccctlx re gister , the captured v alue is loaded to this re gister . at the same time a capture a interrupt can be generated, thus the captured counter v alue can be read out in the interrupt handler . t16a comparator/capture ch.x b data register (t16a_ccbx) register name ad dress bit name function setting init. r/w remarks t16a comparator/ capture ch.x b data register (t16a_ccbx) 0x5408 (16 bits) d15C0 ccb[15:0] compare/capture b data ccb15 = msb ccb0 = lsb 0x0 to 0xffff 0x0 r/w d[15:0] ccb[15:0]: compare/capture b data bits sets a compare b data, which will be compared with the counter v alue, through this re gister . when cb ufen/t16a_ctlx re gister is set to 0, compare b data will be set to the compare b re gister after a lapse of tw o t16a2 count clock c ycles from the time when it is written to this re gister . when cb ufen is set to 1, the data written to this re gister is loaded to the compare b b uf fer . the b uf fer contents are loaded into the compare b re gister when the compare b signal is generated. the compare b re gister is al w ays directly accessed when being read re g ardless of the cb ufen setting. the data set is compared with the counter data. when the counter reaches the comparison v alue set, the compare b signal is asserte d and a cause of compare b interrupt occurs. the counter is reset to 0. furthermore, the t out output w a v eform changes when t out amd[1:0]/t16a_ccctlx re gister or t outbmd[1:0]/t16a_ccctlx re gister is set to 0x3 or 0x1.
12 16-bit pwm timer (t16a2) s1c17651 t echnical m anual seiko epson corporation 12-17 in capture mode (ccbmd = 1) when the counter v alue is captured at the e xternal trigger signal (capbx) edge selected using capb- t r g [1:0] / t16a _ c c c t l x r e g i s t e r , t h e c a p t u r e d v a l u e i s l o a d e d t o t h i s r e g i s t e r . a t t h e s a m e t i m e a capture b interrupt can be generated, thus the captured counter v alue can be read out in the interrupt handler . t16a comparator/capture ch.x interrupt enable register (t16a_ienx) register name ad dress bit name function setting init. r/w remarks t16a comparator/ capture ch.x interrupt enable register (t16a_ienx) 0x540a (16 bits) d15C6 C reser v ed C C C 0 when being read. d5 capbowie capture b o v erwr ite interr upt enab le 1 enab le 0 disab le 0 r/w d4 capaowie capture a o v erwr ite interr upt enab le 1 enab le 0 disab le 0 r/w d3 capbie capture b interr upt enab le 1 enab le 0 disab le 0 r/w d2 capaie capture a interr upt enab le 1 enab le 0 disab le 0 r/w d1 cbie compare b interr upt enab le 1 enab le 0 disab le 0 r/w d0 caie compare a interr upt enab le 1 enab le 0 disab le 0 r/w d[15:6] reserved d5 capbowie: capture b overwrite interrupt enable bit enables or disables capture b o v e rwrite interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting capbo wie to 1 enables capture b o v erwrite interrupt requests to the itc. setting it to 0 dis- ables interrupts. d4 capaowie: capture a overwrite interrupt enable bit enables or disables capture a o v erwrite interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting cap a o wie to 1 enables capture a o v erwrite interrupt requests to the itc . setting it to 0 dis- ables interrupts. d3 capbie: capture b interrupt enable bit enables or disables capture b interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting capbie to 1 enables capture b interrupt requests to the itc. setting it to 0 disables interrupts. d2 capaie: capture a interrupt enable bit enables or disables capture a interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting cap aie to 1 enables capture a interrupt requests to the itc. setting it to 0 disables interrupts. d1 cbie: compare b interrupt enable bit enables or disables compare b interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting cbie to 1 enables compare b interrupt requests to the itc. setting it to 0 disables interrupts. d0 caie: compare a interrupt enable bit enables or disables compare a interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting caie to 1 enables compare a interrupt requests to the itc. setting it to 0 disables interrupts.
12 16-bit pwm timer (t16a2) 12-18 seiko epson corporation s1c17651 t echnical m anual t16a comparator/capture ch.x interrupt flag register (t16a_iflgx) register name ad dress bit name function setting init. r/w remarks t16a comparator/ capture ch.x interrupt flag register (t16a_iflgx) 0x540c (16 bits) d15C6 C reser v ed C C C 0 when being read. d5 capbowif capture b o v erwr ite interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d4 capaowif capture a o v erwr ite interr upt flag 0 r/w d3 capbif capture b interr upt flag 0 r/w d2 capaif capture a interr upt flag 0 r/w d1 cbif compare b interr upt flag 0 r/w d0 caif compare a interr upt flag 0 r/w d[15:6] reserved d5 capbowif: capture b overwrite interrupt flag bit indicates whether the cause of capture b o v erwrite interr upt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored c a p b o w i f i s a t 1 6 a 2 i n t e r r u p t f l a g t h a t i s set to 1 when the capture b re gister is o v erwritten. capbo wif is reset by writing 1. d4 capaowif: capture a overwrite interrupt flag bit indicates whether the cause of capture a o v erwrite interrupt has occurred or not. 1 (r): cause of interrupt has occurr ed 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored c a p a o w i f i s a t 1 6 a 2 i n t e r r u p t f l a g t h a t i s set to 1 when the capture a re gister is o v erwritten. cap a o wif is reset by writing 1. d3 capbif: capture b interrupt flag bit indicates whether the cause of capture b interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is r eset 0 (w): ignored capbif is a t16a2 interrupt flag that is set to 1 when the counter v alue is captured in the capture b re gister . capbif is reset by writing 1. d2 capaif: capture a interrupt flag bit indicates whether the cause of capture a interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored cap aif is a t16a2 interrupt flag that is set to 1 when the counter v alue is captured in the capture a re gister . cap aif is reset by writing 1. d1 cbif: compare b interrupt flag bit indicates whether the cause of compare b interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored
12 16-bit pwm timer (t16a2) s1c17651 t echnical m anual seiko epson corporation 12-19 cbif is a t16a2 interrupt flag that is set to 1 when the counter reaches the v alue set in the compare b re gister . cbif is reset by writing 1. d0 caif: compare a interrupt flag bit indicates whether the cause of compare a interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored caif is a t16a2 interrupt flag that is set to 1 when the counter reaches the v alue set in the compare a re gister . caif is reset by writing 1.
13 clock timer (ct) s1c17651 t echnical m anual seiko epson corporation 13-1 clock t imer (ct) 13 ct module over vie w 13.1 the s1c17651 includes a clock timer module (ct) that uses the osc1 oscillator as its clock source. this timer can be used for generating c yclic interrupts to implement a softw are clock function. the features of the ct module are listed belo w . ? 8-bit binary counter (128 hz to 1 hz) ? 32 hz, 8 hz, 2 hz, and 1 hz interrupts can be generated. figure 13.1.1 sho ws the ct conf iguration. internal data bus clock timer interrupt request to itc 128 hz 64 hz 32 hz 16 hz 8 hz 4 hz 2 hz 1 hz count control circuit interrupt control circuit run/stop control interrupt enable ctrun ctie32 ctie8 ctie2 ctie1 timer reset ctrst ct_cnt d0 d1 d2 d3 d4 d5 d6 d7 clock timer rtc reset 32 khz f256 osc1a oscillator osc1a divider 32 khz osc1b oscillator osc1b divider theoretical regulation clg & tr osc1sel sleep/normal 1.1 ct configur ation figure 13. the ct module consists of an 8-bit binary counter that uses the 256 hz signal di vided from the osc1 clock as the input clock and allo ws data for each bit (128 hz to 1 hz) to be read out by softw are. the clock timer can also gen- erate interrupts using the 32 hz, 8 hz, 2 hz, and 1 hz signals. this clock timer is normally used for v arious timing functions, such as a clo ck. operation cloc k 13.2 the ct module uses the 256 hz clock output by the clg module as the operation clock (normally , the ct module is clock ed by the f256 clock (re gulated 256 hz clock) deri v ed from the osc1a di vider). therefore, the osc1 os- cillator must be turned on before starting the ct module. ho we v er , the clock is not supplied to the ct module in sleep mode e v en if the osc1 oscillator is on . f or detailed information on clock control, see the clock generator (clg) and theoretical re gulation (tr) chapter . notes: ? t h e c t m o d u l e i n p u t c l o c k f r e q u e n c y i s 256 h z o n l y w h e n t h e o s c1 c l o c k f r e q u e n c y i s 32.768 k h z . t h e f r e q u e n c y d e s c r i b e d i n t h i s c h a p t e r w i l l v a r y a c c o r d i n g l y f o r o t h e r o s c1 cloc k frequencies . ? the ct module can also be oper ated with the osc1b divider cloc k (about 256 hz) e v e n if osc1b is selected as the osc1 cloc k source in the clg. ho w e v er , the ct module cannot be used as an accur ate cloc k. ? t h e o s c 1 a d i v i d e r i s r e s e t w h e n t h e r t c s t a r t s r u n n i n g ( w h e n 1 i s w r i t t e n t o r t c r u n / r t c _ ctl register). this aff ects the count oper ations of the ct module , as ne w 256 hz cycle begins from that point. timer reset 13.3 reset the timer by writing 1 to ctrst/ct_ctl re gister . this cle ars the counter to 0. apart from this operation, the counter is also cleared by an initial reset.
13 clock timer (ct) 13-2 seiko epson corporation s1c17651 t echnical m anual timer r un/st op contr ol 13.4 mak e the follo wing settings before starting ct . (1) if using interrupts, set the interrupt le v el and enable interrupts for the clock timer . see section 13.5. (2) reset the timer . see section 13.3. the clock timer includes ctr un/ct_ctl re gister for run/stop control. the clock timer starts operating when 1 is written to ctr un. writing 0 to ctr un disables clock input and stops the operation. this control does not af fect the counter (ct_cnt re gister) data. the counter data is retained e v en when the count is halted, allo wing resumption of the count from that data. if 1 is written to both ctr un and ctrst simultaneously , the clock timer starts counting after resetting. a cause of interrupt occurs during counting at the 32 hz, 8 hz, 2 hz, and 1 hz signal f alling edges. if inte rrupts are enabled, an interrupt request is sent to the interrupt controller (itc). 256 hz 128 hz 64 hz 32 hz 16 hz 8 hz 4 hz 2 hz 1 hz 32 hz interrupt 8 hz interrupt 2 hz interrupt 1 hz interrupt osc1/128 ctcnt0 ctcnt1 ctcnt2 ctcnt3 ctcnt4 ctcnt5 ctcnt6 ctcnt7 4.1 cloc k timer timing char t figure 13. notes: ? the cloc k timer s witches to run/stop status synchroniz ed with the 256 hz signal f alling edge after data is wr itten to ctr un. when 0 is wr itten to ctr un, the timer stops after counting an additional +1. 1 is retained f or ctr un reading until the timer actually stops . figure 13.4.2 sho ws the run/stop control timing char t. ctrun(wr) ct_cnt register 0x57 0x58 0x59 0x5a 0x5b 0x5c ctrun(rd) 256 hz 4.2 run/stop control timing char t figure 13. ? ex ecuting the slp instr uction while the timer is r unning (ctr un = 1) will destabiliz e the timer o p e r a t i o n d u r i n g r e s t a r t i n g f r o m s l e e p s t a t u s . w h e n s w i t c h i n g t o s l e e p s t a t u s , s t o p t h e timer (ctr un = 0) bef ore e x ecuting the slp instr uction. ct interrupts 13.5 the ct module includes functions for generating the follo wing four kinds of interrupts: 32 hz, 8 hz, 2 hz, and 1 hz interrupts the ct module outputs a single interrupt signal shared by the abo v e four interrupt causes to the interrupt controller (itc). the interrupt flag in the ct module should be read to identify the cause of interrupt that occurred.
13 clock timer (ct) s1c17651 t echnical m anual seiko epson corporation 13-3 32 hz, 8 hz, 2 hz, and 1 hz interrupts t h e 3 2 h z , 8 h z , 2 h z , a n d 1 h z s i g n a l f a l l i n g e d g e s s e t t h e c o r r e s p o n d i n g i n t e r r u p t f l a g i n t h e c t m o d u l e t o 1 . at the same time, an interrupt request is sent to the itc if the corresponding interrupt enable bit has been set to 1 (interrupt enabled). an interrupt is generated if the itc and s1c17 core interrupt conditions are satisf ied. if the interrupt enab le bit is set to 0 (interrupt disabled, def ault), no interrupt request will be sent to the itc. 5.1 ct interr upt flags and interr upt enab le bits t ab le 13. cause of interrupt interrupt fla g interrupt enab le bit 32 hz interr upt ctif32/ct_iflg register ctie32/ct_imsk register 8 hz interr upt ctif8/ct_iflg register ctie8/ct_imsk register 2 hz interr upt ctif2/ct_iflg register ctie2/ct_imsk register 1 hz interr upt ctif1/ct_iflg register ctie1/ct_imsk register f or specif ic information on interrupt processing, see the interrupt controller (itc) chapter . notes: ? the ct m odule interr upt flag m ust be reset in the interr upt handler routine after a ct interr upt has occurred to pre v ent recurr ing interr upts . ? reset the interr upt flag bef ore enab ling ct interr upts with the interr upt enab le bit to pre v ent occurrence of unw anted interr upt. the interr upt flag is reset b y wr iting 1. contr ol register details 13.6 6.1 list of ct registers t ab le 13. ad dress register name function 0x5000 ct_ctl cloc k timer control register resets and star ts/stops the timer . 0x5001 ct_cnt cloc k timer counter register counter data 0x5002 ct_imsk cloc k timer interr upt mask register enab les/disab les interr upt. 0x5003 ct_iflg cloc k timer interr upt flag register indicates/resets interr upt occurrence status . the ct re gisters are described in detail belo w . note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. clock timer control register (ct_ctl) register name ad dress bit name function setting init. r/w remarks clock timer control register (ct_ctl) 0x5000 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 ctrst cloc k timer reset 1 reset 0 ignored 0 w d3C1 C reser v ed C C C d0 ctrun cloc k timer r un/stop control 1 run 0 stop 0 r/w d[7:5] reserved d4 ctrst: clock timer reset bit resets the clock timer . 1 (w): reset 0 (w): ignored 0 (r): al w ays 0 when read (def ault) writing 1 to this bit resets the counter to 0x0. when reset in run state, the clock timer restarts immedi- ately after resetting. the reset data 0x0 is retained when in stop state. d[3:1] reserved d0 ctrun: clock timer run/stop control bit controls the clock timer run/stop. 1 (r/w): run 0 (r/w): stop (def ault) the clock timer starts counting when ctr un is written as 1 and stops when written as 0. the counter data is retained at stop state until a reset or the ne xt run state.
13 clock timer (ct) 13-4 seiko epson corporation s1c17651 t echnical m anual clock timer counter register (ct_cnt) register name ad dress bit name function setting init. r/w remarks clock timer counter register (ct_cnt) 0x5001 (8 bits) d7C0 ctcnt[7:0] cloc k timer counter v alue 0x0 to 0xff 0x0 r d[7:0] ctcnt[7:0]: clock timer counter value bits the counter data can be read out. (def ault: 0x0) this re gister is read-only and cannot be written to. the bits correspond to v arious frequencies, as follo ws: d7: 1 hz, d6: 2 hz, d5: 4 hz, d4: 8 hz, d3: 16 hz, d2: 32 hz, d1: 64 hz, d0: 128 hz note: the correct counter v alue ma y not be read out (reading is unstab le) if the register is read while counting is underw a y . read the counter register twice in succession and treat the v alue as v alid if the v alues read are identical. clock timer interrupt mask register (ct_imsk) register name ad dress bit name function setting init. r/w remarks clock timer interrupt mask register (ct_imsk) 0x5002 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 ctie32 32 hz interr upt enab le 1 enab le 0 disab le 0 r/w d2 ctie8 8 hz interr upt enab le 1 enab le 0 disab le 0 r/w d1 ctie2 2 hz interr upt enab le 1 enab le 0 disab le 0 r/w d0 ctie1 1 hz interr upt enab le 1 enab le 0 disab le 0 r/w this re gister enables or disables interrupt requests indi vidually for the 32 hz, 8 hz, 2 hz, and 1 hz signals. setting ctie* to 1 enables ct interrupts for the corresponding freque nc y signal f alling edge, while setting to 0 disables interrupts. d[7:4] reserved d3 ctie32: 32 hz interrupt enable bit enables or disables 32 hz interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) d2 ctie8: 8 hz interrupt enable bit enables or disables 8 hz interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) d1 ctie2: 2 hz interrupt enable bit enables or disables 2 hz interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) d0 ctie1: 1 hz interrupt enable bit enables or disables 1 h z interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) clock timer interrupt flag register (ct_iflg) register name ad dress bit name function setting init. r/w remarks clock timer interrupt flag register (ct_iflg) 0x5003 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 ctif32 32 hz interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d2 ctif8 8 hz interr upt flag 0 r/w d1 ctif2 2 hz interr upt flag 0 r/w d0 ctif1 1 hz interr upt flag 0 r/w this re gister indicates the occurrence state of interrupt causes due to 32 hz, 8 hz, 2 hz, and 1 hz signals. if a ct interrupt occurs, identify the interrupt cause (freq uenc y) by reading the interrupt flag in this re gister . ctif* is a ct module interrupt flag that is set to 1 at the f alling edge of the corresponding 32 hz, 8 hz, 2 hz, or 1 hz interrupt. ctif* is reset by writing 1.
13 clock timer (ct) s1c17651 t echnical m anual seiko epson corporation 13-5 d[7:4] reserved d3 ctif32: 32 hz interrupt flag bit indicates whether the cause of 32 hz interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored d2 ctif8: 8 hz interrupt flag bit indicates whether the cause of 8 hz interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored d1 ctif2: 2 hz interrupt flag bit indica tes whether the cause of 2 hz interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored d0 ctif1: 1 hz interrupt flag bit indicates whether the cause of 1 hz interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored
14 w a tchdog timer (wdt) s1c17651 t echnical m anual seiko epson corporation 14-1 w atchdog t imer (wdt) 14 wdt module over vie w 14.1 the s1c17651 includes a w atchdog timer module (wdt) that uses the osc1 oscillator as its clock source. this timer is used to detect cpu runa w ay . the features of wdt are listed belo w . ? 10-bit up counter ? either reset or nmi can be generated if the counter o v erflo ws. figure 14.1.1 sho ws the wdt conf iguration. nmi reset 10-bit counter interrupt control circuit run/stop control nmi/reset mode select wdtrun[3:0] wdtmd watchdog timer reset wdtrst watchdog timer rtc reset 32 khz f256 osc1a oscillator osc1a divider 32 khz osc1b oscillator osc1b divider theoretical regulation clg & tr osc1sel sleep/normal 1.1 wdt configur ation figure 14. the wdt module generates an nmi or reset (selectable via softw are) to the cpu if not reset within 131,072/f osc1 seconds (4 seconds when f osc1 = 32.768 khz). reset wdt via softw are within this c ycle to pre v ent nmi/resets, which in turn enables runa w ay detection for pro- grams that do not pass through the handler routine. operation cloc k 14.2 the wdt module uses the 256 hz clock output by the clg module as the operation clock (normally , the wdt module is clock ed by the f256 clock (re gulated 256 hz clock) deri v ed from the osc1a di vider). therefore, the o s c 1 o s c i l l a t o r m u s t b e t u r n e d o n b e f o r e s t a r t i n g t h e w d t m o d u l e . h o w e v e r , t h e c l o c k i s n o t s u p p l i e d t o t h e w d t module in sleep mode e v en if the osc1 oscillator is on. f or detailed information on clock control, see the clock generator (clg) and theoretical re gulation (tr) chapter . notes: ? the wdt module input cloc k frequency is 256 hz only when the osc1 cloc k frequency is 32.768 khz. the frequency and time descr ibed in this chapter will v ar y accordingly f or other osc1 cloc k frequencies . ? the wdt module can also be oper ated with the osc1b divider cloc k (about 256 hz) e v en if osc1b is selected as the osc1 clo c k source in the clg. ? t h e o s c 1 a d i v i d e r i s r e s e t w h e n t h e r t c s t a r t s r u n n i n g ( w h e n 1 i s w r i t t e n t o r t c r u n / r t c _ ctl register). this aff ects the count oper ations of the wdt module , as ne w 256 hz cycle be- gins from that point. wdt contr ol 14.3 nmi/reset mode selection 14.3.1 wdtmd/wdt_st re gister is used to select whether an nmi signal or a reset signal is output when wdt has not been reset within th e nmi/reset generation c ycle. t o generate an nmi, set wdtmd to 0 (def ault). set to 1 to generate a reset.
14 w a tchdog timer (wdt) 14-2 seiko epson corporation s1c17651 t echnical m anual wdt run/stop contr ol 14.3.2 wdt starts counting when a v alue other than 0b1010 is written to wdtr un[3:0]/wdt_ctl re gister and stops when 0b1010 is written. at initial reset, wdtr un[3:0] is set to 0b1010 to stop the w atchdog timer . since an nmi or reset may be generated immediately after running depending on the counter v alue, wdt should also be reset concurrently (before running the w atchdog timer), as e xplained in the follo wing section. wdt reset 14.3.3 t o reset wdt , write 1 to wdtrst/wdt_ctl re gister . a location should be pro vided for periodically processing the routine for resetting wdt before an nmi or reset is generated when using wdt . process this routine within 131,072/f osc1 second (4 seconds when f osc1 = 32.768 khz) c ycle. after resetting, wdt starts counting with a ne w nmi/reset genera tion c ycle. if wdt is not reset within the nmi/reset generation c ycle for an y reason, the cpu is switched to interrupt pro- cessing by nmi or reset, the interrupt v ector is read out, and the interrupt handler routine is e x ecuted. the reset and nmi v ector addresses are ttbr + 0x0 and ttbr + 0x08. if the counter o v erflo ws and generates an nmi without wdt being reset, wdtst/wdt_st re gister is set to 1. this bit is pro vided to conf irm that wdt w as the source of the nmi. the wdtst set to 1 is cleared to 0 by reset- ting wdt . operations in hal t and sleep modes 14.3.4 hal t mode t h e wdt m o d u l e o p e r a t e s i n h a l t m o d e , a s t h e c l o c k i s s u p p l i e d . h a l t m o d e i s t h e r e f o r e c l e a r e d b y a n n m i o r r e s e t i f i t c o n t i n u e s f o r m o r e t h a n t h e n m i / r e s e t g e n e r a t i o n c y c l e . t o d i s a b l e wdt w h i l e i n h a l t m o d e , s t o p wdt b y w r i t i n g 0 b 1 0 1 0 t o w d t r u n [ 3 : 0 ] / w d t _ c t l r e g i s t e r b e f o r e e x e c u t i n g t h e halt i n s t r u c t i o n . r e s e t wdt b e f o r e r e s u m i n g o p e r a t i o n s a f t e r h a l t m o d e i s c l e a r e d . sleep mode t h e c l o c k s u p p l i e d f r o m t h e c l g m o d u l e i s s t o p p e d i n s l e e p m o d e , w h i c h a l s o s t o p s wdt . t o p r e v e n t g e n e r a t i o n o f a n u n n e c e s s a r y n m i o r r e s e t a f t e r c l e a r i n g s l e e p m o d e , r e s e t wdt b e f o r e e x e c u t i n g t h e slp i n s t r u c t i o n . wdt s h o u l d a l s o b e s t o p p e d a s r e q u i r e d u s i n g w d t r u n [ 3 : 0 ] . contr ol register details 14.4 t ab le 14.4.1 list of wdt registers ad dress register name function 0x5040 wdt_ctl w atchdog timer control register resets and star ts/stops the timer . 0x5041 wdt_st w atchdog timer status register sets the timer mode and indicates nmi status . the wdt re gisters are described in detail belo w . note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. watchdog timer control register (wdt_ctl) register name ad dress bit name function setting init. r/w remarks watchdog timer control register (wdt_ctl) 0x5040 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 wdtrst w atchdog timer reset 1 reset 0 ignored 0 w d3C0 wdtrun[3:0] w atchdog timer r un/stop control o t h e r t h a n 1 0 1 0 run 1010 stop 1010 r/w d[7:5] reserved
14 w a tchdog timer (wdt) s1c17651 t echnical m anual seiko epson corporation 14-3 d4 wdtrst: watchdog timer reset bit resets wdt . 1 (w): reset 0 (w): ignored 0 (r): al w ays 0 when read (def ault) note: to use wdt, it must be reset by writing 1 to this bit within the nmi/reset generation cycle (4 seconds when f osc1 = 32.768 khz). this resets the up-counter to 0 and starts counting with a new nmi/reset generation cycle. d[3:0] wdtrun[3:0]: watchdog timer run/stop control bits controls wdt run/stop. v alues other than 0b1010 (r/w): run 0b1010 (r/w): stop (def ault) note: wdt must also be reset to prevent generation of an unnecessary nmi or reset before start - ing wdt. watchdog timer status register (wdt_st) register name ad dress bit name function setting init. r/w remarks watchdog timer status register (wdt_st) 0x5041 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1 wdtmd nmi/reset mode select 1 reset 0 nmi 0 r/w d0 wdtst nmi status 1 n m i o c c u r r e d 0 n o t o c c u r r e d 0 r d[7:2] reserved d1 wdtmd: nmi/reset mode select bit selects nmi or reset generation on counter o v erflo w . 1 (r/w): reset 0 (r/w): nmi (def ault) setting this bit to 1 outputs a reset signal when the counter o v erflo ws. setting to 0 outputs an nmi sig- nal. d0 wdtst: nmi status bit indicates a counter o v erflo w and nmi occurrence. 1 (r): nmi occurred (counter o v erflo w) 0 (r): nmi not occurred (def ault) this bit conf irms that wdt w as the source of the nmi. the wdtst set to 1 is cleared to 0 by resetting wdt . this is also set by a counter o v erflo w if reset output is selected, b ut is cleared by initial reset and cannot be conf irmed.
15 u ar t s1c17651 t echnical m anual seiko epson corporation 15-1 u ar t 15 u ar t module over vie w 15.1 the s1c17651 includes a u ar t module for asynchronous communication. it includes a 2-byte recei v e data b uf fer and 1-byte transmit data b uf fer allo wing successi v e data transfer . the u ar t module also includes an rzi modula- tor/demodulator circuit that enables ird a 1.0-compatible infrared communications simply by adding basic e xternal circuits. the follo wing sho ws the main features of the u ar t : ? number of channels: 1 channel ? t ransfer rate: 150 to 230,400 bps (150 to 115,200 bps in ird a mode) ? t ransfer clock: internal clock (baud rate generator output) or an e xternal clock (sclk input) can be se- lected. ? character length: 7 or 8 bits (lsb f irst) ? p arity mode: ev en, odd, or no parity ? stop bit: 1 or 2 bits ? start bit: 1 bit f ix ed ? supports full-duple x communicat ions. ? includes a 2-byte recei v e data b uf fer and a 1-byte transmit data b uf fer . ? includes a baud rate generator with f ine adjustment function. ? includes an rzi modulator/demodulator circuit to support ird a 1.0-compatible infrared communications. ? can detect parity error , framing error , and o v errun error during recei ving. ? can generate recei v e b uf fer full, transmit b uf fer empty , end of transmissi on and recei v e error interrupts. figure 15.1.1 sho ws the u ar t conf iguration. shift register receive data buffer (2 bytes) sinx internal bus itc uart ch.x bus i/f and control registers sclkx shift register transmit data buffer (1 byte) clock/transfer control soutx rzi demodulator rzi modulator interrupt control sclk baud rate generator 1.1 u ar t configur ation figure 15. note: the letter x in register and pin names ref ers to a channel n umber (0). example: u ar t_ctlx register ch.0: u ar t_ctl0 register
15 u ar t 15-2 seiko epson corporation s1c17651 t echnical m anual u ar t input/output pins 15.2 t able 15.2.1 lists the u ar t input/output pins. 2.1 list of u ar t pins t ab le 15. pin name i/o qty function sin0 (ch.0) i 1 u ar t data input pin inputs ser ial data sent from an e xter nal ser ial de vice . sout0 (ch.0) o 1 u ar t data output pin outputs ser ial data sent to an e xter nal ser ial de vice . sclk0 (ch.0) i 1 u ar t cloc k input pin inputs the tr ansf er cloc k when an e xter nal cloc k is used. the u ar t input/output pins (sinx, soutx, sclkx) are shared with i/o ports and are initially set as general pur - p ose i/o port pins. the pin functions must be switched using the port function select bits to use the general purpose i/o port pins as u ar t input/output pins. f or detailed information on pin function switching, see the i/o ports (p) chapter . baud rate generator 15.3 the u ar t module includes a baud rate generator to generate the transfer (sampling) clock. it consists of an 8-bit programmable timer w ith f ine mode. the timer counts do wn from the initial v alue set via softw are and outputs an underflo w signal when the counter underflo ws. the underflo w signal is used to generate the transfer clock. the un- derflo w c ycle can be programmed by selecting the clock source and initial data, enabling the application program to obtain serial transfer rates as required. fine mode pro vides a function that m inimizes transfer rate errors. baud rate register uart_brx underflow fine mode setting clock enable ct_clk division ratio selection clock source selection utclke utclkd[1:0] utclksrc[1:0] down counter control circuit fmd[3:0] baud rate generator for uart ch. x osc1 clock external clock (sclkx) osc3a clock divider (1/1C1/8) osc3b clock divider (1/1C1/8) serial transfer clock sclk sclk16 1/16 3.1 baud rate gener ator figure 15. cloc k sour ce settings t h e c l o c k s o u r c e c a n b e s e l e c t e d f r o m o s c3b , o s c3a , o s c1, o r e x t e r n a l c l o c k u s i n g u t c l k s r c [1:0] / u ar t_clkx re gister . 3.1 cloc k source selection t ab le 15. utclksrc[1:0] cloc k sour ce 0x3 exter nal cloc k (sclkx) 0x2 osc3a 0x1 osc1 0x0 osc3b (def ault: 0x0) note: when inputting the e xter nal cloc k via the sclkx pin, the cloc k duty r atio m ust be 50%. when osc3b or osc3a is selected as the clock source, use utclkd[1:0]/u ar t_clkx re gister to select the di vision ratio.
15 u ar t s1c17651 t echnical m anual seiko epson corporation 15-3 3.2 osc3b/osc3a division ratio selection t ab le 15. utclkd[1:0] division ratio 0x3 1/8 0x2 1/4 0x1 1/2 0x0 1/1 (def ault: 0x0) clock supply to the counter is controlled using utclke/u ar t_clkx re gister . the utclke def ault setting is 0, which disables the clock supply . setting utclke to 1 sends the clock selected to the counter . initial counter v alue setting br[7:0]/u ar t_brx re gister is used to set the initial v alue for the do wn counter . the initial counter v alu e is preset to the do wn counter if the counter underflo ws. this means that the initial counter v alue and the count clock frequenc y determine the time elapsed between underflo ws. underflow signal/ baud rate generator output (sclk16) baud rate generator output (sclk) 123 81 6 3.2 counter underflo w and cloc k gener ated figure 15. use the follo wing equations to calculate the initial counter v alue for obtaining the desired transfer rate. ct_clk bps = {(br + 1) 16 + fmd} ct_clk br = ( - fmd - 16 ) 16 bps ct_clk: count clock frequenc y (hz) br: br[7:0] setting (0 to 255) bps: t ransfer rate (bit/s) fmd: fmd[3:0] (f ine mode) setting (0 to 15) note: the u ar t tr ansf er r ate is capped at 230,400 bps (115,200 bps in ird a mode). do not set f aster tr ansf er r ates . fine mode fine mode pro vides a function that minimizes transfer rate errors. the baud rate generator output clock can be set to the required frequenc y by selecting the appropriate clock source and initial counter data. note that errors may occur , depending on the transfer rate. fine mode e xtends the output clock c ycle by delaying the underflo w pulse from the counter . this delay can be specif ied with the fmd[3:0]/u ar t_fmdx re gister . fmd[3:0] speci- f ies the delay pattern to be inserted into a 16 underflo w period. inserting one delay e xtends the output clock c ycle by one count clock c ycle. 3.3 dela y p atter ns specified b y fmd[3:0] t ab le 15. fmd[3:0] underflo w n umber 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0x0 C C C C C C C C C C C C C C C C 0x1 C C C C C C C C C C C C C C C d 0x2 C C C C C C C d C C C C C C C d 0x3 C C C C C C C d C C C d C C C d 0x4 C C C d C C C d C C C d C C C d 0x5 C C C d C C C d C C C d C d C d 0x6 C C C d C d C d C C C d C d C d 0x7 C C C d C d C d C d C d C d C d 0x8 C d C d C d C d C d C d C d C d 0x9 C d C d C d C d C d C d C d d d 0xa C d C d C d d d C d C d C d d d 0xb C d C d C d d d C d d d C d d d 0xc C d d d C d d d C d d d C d d d 0xd C d d d C d d d C d d d d d d d 0x e C d d d d d d d C d d d d d d d 0xf C d d d d d d d d d d d d d d d d: indicates the inser tion of a dela y cycle .
15 u ar t 15-4 seiko epson corporation s1c17651 t echnical m anual count clock underflow signal (not corrected) underflow signal (corrected) sclk (not corrected) sclk (corrected) delayed 15 16 15 16 1 1 3.3 dela y cycle inser tion in fine mode figure 15. at initial reset, fmd[3:0] is set to 0x0, pre v enting insertion of delay c ycles. note: mak e sure the u ar t is halted (rxen/u ar t_ctlx register = 0) bef ore setting the baud r ate gen- er ator . t ransf er data settings 15.4 set the follo wing conditions to conf igure the transfer data format. ? data length: 7 or 8 bits ? start bit: fix ed at 1 bit ? stop bit: 1 or 2 bi ts ? p arity bit: ev en, odd, or no parity note: mak e sure the u ar t is halted (rxen/u ar t_ctlx register = 0) bef ore changing tr ansf er data f or mat settings . data length the data length is selected by chln/u ar t_modx re gister . setting chln to 0 (def ault) conf igures the data length to 7 bits. setting chln to 1 conf igures it to 8 bits. stop bit the stop bit length is selected by stpb/u ar t_modx re gister . setting stpb to 0 (def ault) conf igures the stop bit length to 1 bit. setting stpb to 1 conf igures it to 2 bits. p arity bit whether the parity function is enabled or disabled is selected by pren/u ar t_modx re gister . setting pren to 0 (def ault) disables the parity function. in this case, no parity bit is added to the transfer data and the data is not check ed for parity when recei v ed. setting pren to 1 enables the parity function. in this case, a parity bit is added to the transfer data and the data is check ed for parity when recei v ed. when the parity function is enabled, the parity mode is selected by pmd/u ar t_modx re gister . setting pmd to 0 (def ault) adds a parity bit and checks for e v en parity . setting pmd to 1 adds a parity bit and checks for odd parity . sampling clock (sclk) chln = 0, pren = 0, stpb = 0 chln = 0, pren = 1, stpb = 0 chln = 0, pren = 0, stpb = 1 chln = 0, pren = 1, stpb = 1 chln = 1, pren = 0, stpb = 0 chln = 1, pren = 1, stpb = 0 chln = 1, pren = 0, stpb = 1 chln = 1, pren = 1, stpb = 1 s1 d0 d1 d2 d3 d4 d5 d6 s2 s1 d0 d1 d2 d3 d4 d5 d6 p s2 s1 d0 d1 d2 d3 d4 d5 d6 s2 s3 s1 d0 d1 d2 d3 d4 d5 d6 p s2 s3 s1 d0 d1 d2 d3 d4 d5 d6 d7 s2 s1 d0 d1 d2 d3 d4 d5 d6 d7 p s2 s1 d0 d1 d2 d3 d4 d5 d6 d7 s2 s3 s1 d0 d1 d2 d3 d4 d5 d6 d7 p s2 s3 s1: start bit, s2 & s3: stop bit, p: parity bit figure 15.4.1 t r ansf er data f or mat
15 u ar t s1c17651 t echnical m anual seiko epson corporation 15-5 data t ransf er contr ol 15.5 mak e the follo wing settings before starting data transfers. (1) select the input clock. (see section 15.3.) (2) program the baud rate generator to output the transfer clock. (see section 15.3.) (3) set the transfer data format. (see section 15.4.) (4) t o use the ird a interf ace, set ird a mode. (see section 15.8.) (5) set interrupt conditions to use u ar t interrupts. (see sectio n 15.7.) note: mak e sure the u ar t is halted (rxen/u ar t_ctlx register = 0) bef ore changing the abo v e set- tings . enab ling data transf er s s e t r x e n / u a r t _ c t l x r e g i s t e r t o 1 t o e n a b l e d a t a t r a n s f e r s . t h i s p u t s t h e t r a n s m i t t e r / r e c e i v e r c i r c u i t i n r e a d y - to-transmit/recei v e status. note: do not set rxen to 0 while the u ar t is sending or receiving data. data transmission contr ol t o start data transmission, write the transmit data to txd[7:0]/u ar t_txdx re gister . the data is written to the transmit data b uf fer , and the transmitter circuit starts sending data. the b uf fer data is sent to the transmit shift re gister , and the start bit is output from the soutx pin. the data in the shift re gister is then output from the lsb. the transfer data bit is shifted in sync with the sampling clock rising edge and output in s equence via the soutx pin. f ollo wing output of msb, the parity bit (if parity is en- abled) and the stop bit are output. the transmitter circuit includes three status flags: tdbe/u ar t_stx re gister , trbs/u ar t_stx re gister , and tred/u ar t_stx re gister . the tdbe flag indicates the transmit data b uf fer status. this flag switches to 0 when the application program writes data to the transmit data b uf fer a nd re v erts to 1 when the b uf fer data is sent to the transmit shift re gister . an interrupt can be generated when this flag is set to 1 (see section 15.7). subsequent data is sent after con- f irming that the transmit data b uf fer is empty either by using this interrupt or by reading the tdbe flag. the transmit data b uf fer size is 1 byte, b ut a shift re gister is pro vided separately to allo w data to be written while the pre vious data is being sent. al w ays conf irm that the transmit data b uf fer is empty before writing transmit data. writing data while the tdbe flag is 0 will o v erwrite earlier transmit data inside the transmit data b uf fer . the trbs flag indicates the shift re gister status. this flag switches to 1 when transmit data is loaded from the transmit data b uf fer to the shift re gister and r e v erts to 0 once the data is sent. read this flag to check whether the transmitter circuit is operating or at standby . the tred switches to 1 when the trbs flag re v erts to 0 from 1, indicating that transmit operation has com- pleted. an interrupt can be generated when this flag is set to 1 (see section 15.7). use this interrupt for trans- mission end processing. the tred flag is reset to 0 by writin g 1. s1: start bit, s2: stop bit, p: parity bit, wr: data write to transmit data buffer sampling clock (sclk) soutx tdbe trbs tred interrupt s1 d0 d1 d2 d3 d4 d5 d6 d7 p s2 s1 d0 d1 d7 p s2 s1 d0 d1 d7 p wr wr wr s2 transmit buffer empty interrupt request end of transmission interrupt request 5.1 data t r ansmission timing char t figure 15.
15 u ar t 15-6 seiko epson corporation s1c17651 t echnical m anual data reception contr ol the recei v er circuit is acti v ated by setting rxen to 1, enabling data to be recei v ed from an e xternal serial de- vice. when the e xternal serial de vice sends a start bit, the recei v er circuit detects its lo w le v el and starts sampling the follo wing data bits. the data bits are sampled at the sampling clock rising edge, and the lead bit is loaded into the recei v e shift re gister as lsb. once the msb has been recei v ed into the shift re gister , the recei v ed data is loaded into the recei v e data b uf fer . if parity checking is enabled, the recei v er circuit checks the recei v ed data at the same time by checking the parity bit recei v ed immediately after the msb. the recei v e data b uf fer , a 2-byte fifo, recei v es data until full. recei v ed data in the b uf fer can be read from rxd[7:0]/ u ar t_rxdx re gister . the oldest data is read out f irst and data is cleared by reading. the recei v er circuit includes tw o b uf fer status flags: rdr y/u ar t_stx re gister and rd2b/u ar t_stx re gis- ter . the rdr y flag indicates that the recei v e data b uf fer still contains data. the rd2b flag indicates that the re- cei v e data b uf fer is full. (1) rdr y = 0, rd2b = 0 the recei v e data b uf fer contents need not be rea d, since no data has been recei v ed. (2) rdr y = 1, rd2b = 0 one 8-bit data has been recei v ed. read the recei v e data b uf fer contents once. this resets the rdr y flag. the b uf fer re v erts to state (1) abo v e. if the recei v e data b uf fer contents are read twice, the second data read will be in v alid. (3) rdr y = 1, rd2b = 1 t w o 8- b i t d a t a h a v e b e e n r e c e i v e d . r e a d t h e r e c e i v e d a t a b u f f e r c o n t e n t s t w i c e . t h e r e c e i v e d a t a b u f f e r outputs the oldest data f irst. this resets the rd2b flag. the b uf fer then re v erts to the state in (2) abo v e. the second read outputs the most recent recei v ed data, after which the b uf fer re v erts to the state in (1) abo v e. ev en when the recei v e data b uf fer is full, the shift re gister can start recei ving 8-bit data one more time. an o v errun error will occur if recei ving is f inishe d before the recei v e data b uf fer has been read. in this case, the last recei v ed data cannot be read. the contents of the recei v e data b uf fer must be read out before an o v errun error occurs. f or detailed information on o v errun errors, refer to section 15.6. the v olume of data recei v ed can be check ed by reading these flags. the u ar t allo ws recei v e b uf fer full interrupts to be generated once data has been recei v ed in the recei v e data b uf fer . these interrupts can be used to read the recei v e data b uf fer . by def ault, a recei v e b uf fer full interrupt occurs when the recei v e data b uf fer recei v es one 8-bit data (status (2) abo v e). this can be changed by setting rbfi/u ar t_ctlx re gister to 1 so that an interrupt occurs when the recei v e data b uf fer recei v es tw o 8-bit data. three error flags are also pr o vided in addition to the flags pre viously mentioned. see section 15.6 for detailed information on flags and recei v e errors.
15 u ar t s1c17651 t echnical m anual seiko epson corporation 15-7 receive buffer full interrupt request (rbfi = 0) overrun error interrupt request sampling clock (sclk) sinx receive data buffer rdry rd2b rxd[7:0] interrupt data 1 s1 d0 p s2 s1 d0 p s2 s1 d0 p s2 s1 d0 p s2 s1 d0 p s2 s1 d0 p s2 data 2 data 3 data 4 data 5 data 6 rd rd data 3, 4 data 2 data 1 C data 2, 3 data 3 data 3 data 2 data 1 s1: start bit, s2: stop bit, p: parity bit, rd: data read from rxd[7:0] 5.2 data receiving timing char t figure 15. disab ling data transf er s write 0 to rxen to disable data transfers. the data being transferred cannot be guaranteed if rxen is set to 0 while data is being sent or recei v ed. before setting rxen to 0, check the data transfer status with softw are in consideration of the communication procedure. the data transmit status can be check ed using the trbs flag. note: s etting rxen to 0 empties the tr ansmit data b uff er , clear ing an y remaining data. the data being tr ansf erred cannot be guar anteed if rxen is set to 0 while data is being sent or receiv ed. mak e sure that the tdbe flag is 1 and the trbs and rdr y flags are both 0 bef ore disab ling data tr ansf er . receive err or s 15.6 three dif ferent recei v e errors may be detected while recei ving data. since recei v e errors a re interrupt causes, the y can be processed by generating interrupts. f or more information on u ar t interrupt control, see section 15.7. p arity err or if pren/u ar t_modx re gister has been set to 1 (parity enabled), data recei v ed is check ed for parity . data recei v ed in the shift re gister is check ed for parity when sent to the recei v e data b uf fer . the matching is check ed ag ainst the pmd/u ar t_modx re giste r setting (odd or e v en parity). if the result is a non-match, a parity error is issued, and the parity error flag per/u ar t_stx re gister is set to 1. ev en if this error occurs, the data recei v ed is sent to the recei v e data b uf fer , and the recei ving operation continues. ho we v er , the recei v ed data cannot be guaranteed if a parity error occurs. the per flag is reset to 0 by writing 1. framing err or a f raming error occurs if the stop bit is recei v ed as 0 and the u ar t determines loss of sync. if the stop bit is set to tw o bits, only the f irst bit is check ed. the framing error flag fer/u ar t_stx re gister is set to 1 if this error occurs. the recei v ed data is still trans- ferred to the recei v e data b uf fer if this error occurs and the recei ving operation continues, b ut the data cannot be g u a r a n t e e d , e v e n i f n o f r a m i n g e r r o r o c c u r s f o r s u b s e q u e n t d a t a r e c e i v i n g . t h e f e r f l a g i s r e s e t t o 0 b y w r i t i n g 1 . overrun err or ev en if the recei v e data b uf fer is full (tw o 8-bit data already recei v ed), the third data can be recei v ed in the shift re gister . ho we v er , if the recei v e data b uf fer is not emptied (by reading out data recei v ed) by the time this data has been recei v ed, the third data recei v ed in the s hift re gister will not be sent to the b uf fer and generate an o v er - run error . if an o v errun error occurs, the o v errun error flag oer/u ar t_stx re gister is set to 1. the recei ving operation continues e v en if this error occurs. the oer flag is reset to 0 by writing 1.
15 u ar t 15-8 seiko epson corporation s1c17651 t echnical m anual u ar t interrupts 15.7 the u ar t includes a function for generating the follo wing four dif ferent types of interrupts. ? t ransmit b uf fer empty interrupt ? end of transmission interrupt ? recei v e b uf fer full interrupt ? recei v e error interrupt the u ar t outputs one interrupt signal shared by the four abo v e interrupt causes to the interrupt controller (itc). inspect the status flag and error flag to determine the interrupt cause occurred. t ransmit b uff er empty interrupt t o use this interrupt, set tien/u ar t_ctlx re gister to 1. if tien is set to 1 while tdbe/u ar t_stx re gister is 1 (transmit data b uf fer empty) or if tdbe is set to 1 (when the transmit data b uf fer becomes empty by load- ing the transmit data written to it to the shift re gister) while tien is 1, an interrupt request is sent to the itc. an in terrupt occurs if other interrupt conditions are met. if tien is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. y ou can inspect the tdbe flag in the u ar t interrupt handler routine to determine whether the u ar t interrupt is attrib utable to a transmit b uf fer empty . if tdbe is 1, the ne xt transmit data can be written to the transmit data b uf fer by the interrupt han dler routine. end of transmission interrupt t o use this interrupt, set teien/u ar t_ctlx re gister to 1. if teien is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. when the trbs flag is reset to 0, the u ar t sets tred/u ar t_stx re gister to 1, indicating that the transmit operation has completed. if end of transmission interrupts are enabled (teien = 1), an interrupt r equest is sent simultaneously to the itc. an interrupt occurs if other interrupt conditions are met. y ou can inspect the tred flag in the u ar t interrupt h a n d l e r r o u t i n e t o d e t e r m i n e w h e t h e r t h e u a r t i n t e r r u p t i s a t t r i b u t a b l e t o a n e n d o f t r a n s m i s s i o n . i f t r e d i s 1 , the transmission processing can be terminated. receive b uff er full interrupt t o use this interrupt, set rien/u ar t_ctlx re gister to 1. i f rien is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. if the specif ied v olume of recei v ed data is loaded into the recei v e data b uf fer when a recei v e b uf fer full interrupt is enabled (rien = 1), the u ar t outputs an interrupt request to the itc. if rbfi/u ar t_ctlx re gister is 0, an interrupt request is output as soon as one recei v ed data is loaded into the recei v e data b uf fer (when rdr y/ u ar t_stx re gister is set to 1). if rbfi is 1, an interrupt request is output as soon as tw o recei v ed data are loaded into the recei v e data b uf fer (when rd2b/u ar t_stx re gister is set to 1). an interrupt occurs if other interrupt conditions are met. y ou can inspect the rdr y and rd2b flags in the u ar t interrupt handler routine to determine whether the u ar t interrupt is attri b utable to a recei v e b uf fer full. if rdr y or rd2b is 1, the recei v ed data can be read from the recei v e data b uf fer by the interrupt handler rou- tine. receive err or interrupt t o u s e t h i s i n t e r r u p t , s e t r e i e n / u a r t _ c t l x r e g i s t e r t o 1 . i f r e i e n i s s e t t o 0 ( d e f a u l t ) , i n t e r r u p t r e q u e s t s f o r this cause will not be sent to the itc. the u ar t sets an error flag, per, fer, or oer/u ar t_stx re gister to 1 if a parity error , framing error , or o v errun error is detected when recei ving data. if recei v e error interrupts are enabled (reien = 1), an interrupt request is sent simultaneously to the itc. if other interrupt conditions are satisf ied, an interrupt occurs. y ou can inspect the per, fer, and oer flags in the u ar t interrupt handler routine to determine whether the u ar t interrupt w as caused by a recei v e error . if an y of the error flags has the v alue 1, the interrupt handler routine will proceed with error reco v ery . f or more information on interrupt processing, see the interrupt controller (itc) chapter .
15 u ar t s1c17651 t echnical m anual seiko epson corporation 15-9 ird a interface 15.8 t h i s u a r t m o d u l e i n c l u d e s a n r z i m o d u l a t o r / d e m o d u l a t o r c i r c u i t e n a b l i n g i m p l e m e n t a t i o n o f i r d a 1 . 0 - c o m p a t i b l e infrared communication function simply by adding basic e xternal circuits. the transmit data output from the u ar t transmit shift re gister is input to the modulator circuit and output from the soutx pin after the lo w pulse has been modulated to a 3 sclk16 c ycle. sclk16 modulator input (shift register output) modulator output (soutx) 12 38 91 01 11 6 3 sclk16 modulator input (shift register output) modulator output (soutx) s1 d0 d1 d2 d3 d4 d5 d6 d7 ps 2s 3 (s1: start bit, s2 & s3: stop bits, p: parity bit) 8.1 t r ansmission signal w a v ef or m figure 15. the recei v ed ird a signal is input to the demodulator circuit and the lo w pulse width is con v erted to 16 sclk16 c y c l e s b e f o r e e n t r y t o t h e r e c e i v e s h i f t r e g i s t e r . t h e d e m o d u l a t o r c i r c u i t u s e s t h e p u l s e d e t e c t i o n c l o c k s e l e c t e d separately from the transfer clock to detect lo w pulses input (when minimum pulse width = 1.41 s/115,200 bps). (s1: start bit, s2 & s3: stop bits, p: parity bit) sclk16 demodulator input (sinx) demodulator output (shift register input) 1 234 16 16 sclk16 2 sclk16 or more demodulator input (sinx) demodulator output (shift register input) s1 d0 d1 d2 d3 d4 d5 d6 d7 ps 2s 3 8.2 receiv e signal w a v ef or m figure 15. ird a enab le t o use the ird a interf ace function, set irmd/u ar t_expx re gister to 1. this enables the rzi modulator/de- modulator circuit. note: this setting m ust be perf or med bef ore setting other u ar t conditions . serial data transf er contr ol data transfer control in ird a mode is identical to that for normal interf aces. f or detailed information on data format settings and data transfer and interrupt control methods, refer to the preceding sections.
15 u ar t 15-10 seiko epson corporation s1c17651 t echnical m anual contr ol register details 15.9 9.1 list of u ar t registers t ab le 15. ad dress register name function 0x4100 u ar t_st0 u ar t ch.0 status register indicates tr ansf er , b uff er and error statuses . 0x4101 u ar t_txd0 u ar t ch.0 t r ansmit data register t r ansmit data 0x4102 u ar t_rxd0 u ar t ch.0 receiv e data register receiv e data 0x4103 u ar t_mod0 u ar t ch.0 mode register sets tr ansf er data f or mat. 0x4104 u ar t_ctl0 u ar t ch.0 control register controls data tr ansf er . 0x4105 u ar t_exp0 u ar t ch.0 expansion regist er sets ird a mode . 0x4106 u ar t_br0 u ar t ch.0 baud rate register sets baud r ate . 0x4107 u ar t_fmd0 u ar t ch.0 fine mode register sets fine mode . 0x506c u ar t_clk0 u ar t ch.0 cloc k control register selects the baud r ate gener ator cloc k. the u ar t re gisters are described in detail belo w . notes: ? w h e n d a t a i s w r i t t e n t o t h e r e g i s t e r s , t h e r e s e r v e d b i t s m u s t a l w a y s b e w r i t t e n a s 0 a n d n o t 1 . ? the f ollo wing u ar t bits shoul d be set with tr ansf ers disab led (rxen = 0). - all u ar t_modx register bits (stpb , pmd , pren, chln) - rbfi bit in the u ar t_ctlx register - all u ar t_expx register bits (irmd) - all u ar t_brx register bits (br[7:0]) - all u ar t_fmdx register bits (fmd[3:0]) - all u ar t_clkx register bits (utclkd[1:0], utclksrc[1:0], utclke) uart ch. x status register (uart_stx) register name ad dress bit name function setting init. r/w remarks uart ch. x status register (uart_st x) 0x4100 (8 bits) d7 tred end of tr ansmission flag 1 completed 0 n o t c o m p l e t e d 0 r/w reset b y wr iting 1. d6 fer f r aming error flag 1 error 0 nor mal 0 r/w d5 per p ar ity error flag 1 error 0 nor mal 0 r/w d4 oer ov err un error flag 1 error 0 nor mal 0 r/w d3 rd2b second b yte receiv e flag 1 ready 0 empty 0 r d2 trbs t r ansmit b usy flag 1 busy 0 idle 0 r shift register status d1 rdry receiv e data ready flag 1 ready 0 empty 0 r d0 tdbe t r ansmit data b uff er empty flag 1 empty 0 not empty 1 r d7 tred: end of transmission flag bit indicate s whether the transmit operation has completed or not. 1 (r): completed 0 (r): not completed (def ault) 1 (w): reset to 0 0 (w): ignored tred is set to 1 when the trbs flag is reset to 0 (when transmission has completed). tred is reset by writing 1. d6 fer: framing error flag bit indicates whether a framing error has occurred or not. 1 (r): error occurred 0 (r): no error (def ault) 1 (w): reset to 0 0 (w): ignored fer is set to 1 when a framing error occurs. framing errors occur when data is recei v ed with the stop bit set to 0. fer is reset by writing 1.
15 u ar t s1c17651 t echnical m anual seiko epson corporation 15-11 d5 per: parity error flag bit indicates whether a parity error has occurred or not. 1 (r): error occurred 0 (r): no error (def ault) 1 (w): reset to 0 0 (w): ignored per is set to 1 when a parity error occurs. p arity checking is enabled only when pren/ u ar t_modx re gister is set to 1 and is performed when recei v ed data is transferred from the shift re gister to the re- cei v e data b uf fer . per is reset by writing 1. d4 oer: overrun error flag bit indicates whe ther an o v errun error has occurred or not. 1 (r): error occurred 0 (r): no error (def ault) 1 (w): reset to 0 0 (w): ignored oer is set to 1 when an o v errun error occurs. ov errun errors occur if the recei v e data b uf fer is full when data is recei v ed in the shift re gister . the recei v e data b uf fer is not o v erwritten e v en if this error occurs. the shift re gister is o v erwritten as soon as the error occu rs. oer is reset by writing 1. d3 rd2b: second byte receive flag bit indicates that the recei v e data b uf fer contains tw o recei v ed data. 1 (r): second byte can be read 0 (r): second byte not recei v ed (def ault) rd2b is set to 1 when the second byte of data is loaded into the recei v e data b uf fer and is reset to 0 when the f irst data is read from the recei v e data b uf fer . d2 trbs: transmit busy flag bit indicates the transmit shift re gister status. 1 (r): operating 0 ( r): standby (def ault) trbs is set to 1 when transmit data is loaded from the transmit data b uf fer into the shift re gister and is reset to 0 when the data transfer is completed. inspect trbs to determine whether the transmit circuit is operating or at standby . d1 rdry: receive data ready flag bit indicates that the recei v e data b uf fer contains v alid recei v ed data. 1 (r): data can be read 0 (r): buf fer empty (def ault) rdr y is set to 1 when recei v ed data is loaded into the recei v e data b uf fer and is reset to 0 when all data has been read from the recei v e data b uf fer . d0 tdbe: transmit data buffer empty flag bit indicates the transmit data b uf fer status. 1 (r): buf fer empty (def ault) 0 (r): data e xists tdbe is reset to 0 when transmit data is written to the transmit data b uf fer and is set to 1 when the data is transferred to the shift re gister .
15 u ar t 15-12 seiko epson corporation s1c17651 t echnical m anual uart ch. x transmit data register (uart_txdx) register name ad dress bit name function setting init. r/w remarks uart ch. x transmit data register (uart_txd x) 0x4101 (8 bits) d7C0 txd[7:0] t r ansmit data txd7(6) = msb txd0 = lsb 0x0 to 0xff (0x7f) 0x0 r/w d[7:0] txd[7:0]: transmit data write transmit data to be set in the transmit data b uf fer . (def ault: 0x0) the u ar t starts transmitting when data is written to this re gister . data written to txd[7:0] is retained until sent to the transmit data b uf fer . t ransmitting data from within the transmit data b uf fer generates a cause of transmit b uf fer empty inter - rupt. txd7 (msb) is in v alid in 7-bit mode. serial con v erted data is output from the soutx pin be ginning with the lsb, in which the bits set to 1 are output as high le v el and bits set to 0 as lo w le v el signals. this re gister can also be read. uart ch. x receive data register (uart_rxdx) register name ad dress bit name function setting init. r/w remarks uart ch. x receive data register (uart_rxd x) 0x4102 (8 bits) d7C0 rxd[7:0] receiv e data in the receiv e data b uff er rxd7(6) = msb rxd0 = lsb 0x0 to 0xff (0x7f) 0x0 r o l d e r d a t a i n t h e b u f - f er is read out first. d[7:0] rxd[7:0]: receive data data in the recei v e data b uf fer is read out in sequence, starting with the oldest. recei v ed data is placed in the recei v e data b uf fer . the recei v e data b uf fer is a 2-byte fifo that allo ws proper data reception until it f ills, e v en if data is not re ad out. if the b uf fer is full and the shift re gister also contains recei v ed data, an o v errun error will occur , unless the data is read out before reception of the subsequent data starts. t h e r e c e i v e c i r c u i t i n c l u d e s t w o r e c e i v e b u f f e r s t a t u s f l a g s : r d r y / u a r t _ s t x r e g i s t e r a n d r d2b / u ar t_stx re gister . the rdr y flag indicates the presence of v alid recei v ed data in the recei v e data b uf fer , while the rd 2b flag indicates the presence of tw o recei v ed data in the recei v e data b uf fer . a recei v e b uf fer full interrupt occurs when the recei v ed data in the recei v e data b uf fer reaches the num- ber specif ied by rbfi/u ar t_ctlx re gister . 0 is loaded into rxd7 in 7-bit mode. serial data input via the sinx pin is con v erted to parallel, with the initial bit as lsb, the high le v el bit as 1, and the lo w le v el bit as 0. this data is then loaded into the recei v e data b uf fer . this re gister is read-only . (def ault: 0x0) uart ch. x mode register (uart_modx) register name ad dress bit name function setting init. r/w remarks uart ch. x mode register (uart_mod x) 0x4103 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 chln char acter length select 1 8 bits 0 7 bits 0 r/w d3 pren p ar ity enab le 1 with par ity 0 no par ity 0 r/w d2 pmd p ar ity mode select 1 odd 0 ev en 0 r/w d1 stpb stop bit select 1 2 bits 0 1 bit 0 r/w d0 C reser v ed C C C 0 when being read. d[7:5] reserved d4 chln: character length select bit selects the serial transfer data length. 1 (r/w): 8 bits 0 (r/w): 7 bits (def ault)
15 u ar t s1c17651 t echnical m anual seiko epson corporation 15-13 d3 pren: parity enable bit enables the parity function. 1 (r/w): w ith parity 0 (r/w): no parity (def ault) pren is used to select whether recei v ed data parity checking is performed and whether a parity bit is added to transmit data. setting pren to 1 parity-checks the recei v ed data. a parity bit is automatically added to the transmit data. if pren is set to 0, no parity bit is check ed or added. d2 pmd: parity mode select bit selects the parity mode. 1 (r/w): odd parity 0 (r/w): ev en parity (def ault) writing 1 to pmd selects odd parity; writing 0 to it selects e v en parity . p arity checking and parity bit addition are enabled only when pren is set to 1. the pmd setting is disabled if pren is 0. d1 stpb: stop bit select bit selects the stop bit length. 1 (r/w): 2 bits 0 (r/w): 1 bit (def ault) writing 1 to stpb selects 2 stop bits; writing 0 to it selects 1 bit. the start bit is f ix ed at 1 bit. d0 reserved uart ch. x control register (uart_ctlx) register name ad dress bit name function setting init. r/w remarks uart ch. x control register (uart_ctl x) 0x4104 (8 bits) d7 teien end of tr ansmission int. enab le 1 enab le 0 disab le 0 r/w d6 reien receiv e error int. enab le 1 enab le 0 disab le 0 r/w d5 rien receiv e b uff er full int. enab le 1 enab le 0 disab le 0 r/w d4 tien t r ansmit b uff er empty int. enab le 1 enab le 0 disab le 0 r/w d3C2 C reser v ed C C C 0 when being read. d1 rbfi r e c e i v e b u f f e r f u l l i n t . c o n d i t i o n s e t u p 1 2 b ytes 0 1 b yte 0 r/w d0 rxen u ar t enab le 1 enab le 0 disab le 0 r/w d7 teien: end of transmission interrupt enable bit enables interrupt requests to the itc when tr ansmit operation has completed. 1 (r/w): enabled 0 (r/w): disabled (def ault) set this bit to 1 to terminate transmit processing using interrupts. d6 reien: receive error interrupt enable bit enables interrupt requests to the itc when a recei v e error occurs. 1 (r/w): enabled 0 (r/w): disabled (def ault) set this bit to 1 to process recei v e errors using interrupts. d5 rien: receive buffer full interrupt enable bit enables interrupt requests to the itc caused when the recei v ed data quantity i n the recei v e data b uf fer reaches the quantity specif ied in rbfi. 1 (r/w): enabled 0 (r/w): disabled (def ault) set this bit to 1 to read recei v ed data using interrupts. d4 tien: transmit buffer empty interrupt enable bit enables interrupt requests to the itc caused when transmission data in the transmit data b uf fer is sent to the shift re gister (i.e. when data transmission be gins). 1 (r/w): enabled 0 (r/w): disabled (def ault) set this bit to 1 t o write data to the transmit data b uf fer using interrupts.
15 u ar t 15-14 seiko epson corporation s1c17651 t echnical m anual d[3:2] reserved d1 rbfi: receive buffer full interrupt condition setup bit sets the quantity of data in the recei v e data b uf fer to generate a recei v e b uf fer full interrupt. 1 (r/w): 2 bytes 0 (r/w): 1 byte (def ault) if recei v e b uf fer full interrupts are enabled (rien = 1), the u ar t outputs an interrupt request to the itc when the quantity of recei v ed data specif ied by rbfi is loaded into the recei v e data b uf fer . if rbfi is 0, an interrupt request is output as soon as one recei v ed data is loaded into the recei v e data b uf fer (when rdr y/u ar t_stx re gister is set to 1). if rbfi is 1, an interrupt request is output as soon a s t w o r e c e i v e d d a t a a r e l o a d e d i n t o t h e r e c e i v e d a t a b u f f e r ( w h e n r d 2 b / u a r t _ s t x r e g i s t e r i s s e t t o 1 ) . d0 rxen: uart enable bit enables data transfer by the u ar t . 1 (r/w): enabled 0 (r/w): disabled (def ault) set rxen to 1 before starting u ar t transfers. setting rxen to 0 disables data transfers. set the trans- fer conditions while rxen is 0. disabling transfers by writing 0 to rxen also clears the transmit data b uf fer . uart ch. x expansion register (uart_expx) register name ad dress bit name function setting init. r/w remarks uart ch. x expansion register (uart_exp x) 0x4105 (8 bits) d7C1 C reser v ed C C C 0 when being read. d0 irmd ird a mode select 1 on 0 off 0 r/w d[7:1] reserved d0 irmd: irda mode select bit switches the ird a interf ace function on and of f. 1 (r/w): on 0 (r/w): of f (def ault) set irmd to 1 to use the ird a interf ace. when irmd is set to 0, this module functions as a normal u ar t , with no ird a functions. uart ch. x baud rate register (uart_brx) register name ad dress bit name function setting init. r/w remarks uart ch. x baud rate register (uart_br x) 0x4106 (8 bits) d7C0 br[7:0] baud r ate setting 0x0 to 0xff 0x0 r/w d[7:0] br[7:0]: baud rate setting bits sets the initial counter v alue of the baud rate generator . (def ault: 0x0) the counter in the baud rate generator repeats counting from the v alue set in this re gister to occurrence of counter underflo w to generate the transfer (sampling) clock. use the follo wing equations to calculate the initial counter v alue for obtaining the desired trans fer rate. ct_clk bps = {(br + 1) 16 + fmd} ct_clk br = ( - fmd - 16 ) 16 bps ct_clk: count clock frequenc y (hz) br: br[7:0] setting (0 to 255) bps: t ransfer rate (bit/s) fmd: fmd[3:0] (f ine mode) setting (0 to 15)
15 u ar t s1c17651 t echnical m anual seiko epson corporation 15-15 uart ch. x fine mode register (uart_fmdx) register name ad dress bit name function setting init. r/w remarks uart ch. x fine mode register (uart_fmd x) 0x4107 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C0 fmd[3:0] fine mode setup 0x0 to 0xf 0x0 r/w s e t a n u m b e r o f t i m e s to inser t dela y into a 16-underflo w per iod. d[7:4] reserved d[3:0] fmd[3:0]: fine mode setup bits corrects the transfer rate error . (def ault: 0x0) fmd[3:0] specif ies the delay pattern to be inserted into a 16 underflo w period of the baud rate genera- tor output clock. inserting one delay e xtends the output clock c ycle by one count clock c ycle . 9.2 dela y p atter ns specified b y fmd[3:0] t ab le 15. fmd[3:0] underflo w n umber 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0x0 C C C C C C C C C C C C C C C C 0x1 C C C C C C C C C C C C C C C d 0x2 C C C C C C C d C C C C C C C d 0x3 C C C C C C C d C C C d C C C d 0x4 C C C d C C C d C C C d C C C d 0x5 C C C d C C C d C C C d C d C d 0x6 C C C d C d C d C C C d C d C d 0x7 C C C d C d C d C d C d C d C d 0x8 C d C d C d C d C d C d C d C d 0x9 C d C d C d C d C d C d C d d d 0xa C d C d C d d d C d C d C d d d 0xb C d C d C d d d C d d d C d d d 0xc C d d d C d d d C d d d C d d d 0xd C d d d C d d d C d d d d d d d 0x e C d d d d d d d C d d d d d d d 0xf C d d d d d d d d d d d d d d d d: indicates the inser tion of a dela y cycle . count clock underflow signal (not corrected) underflow signal (corrected) sclk (not corrected) sclk (corrected) delayed 15 16 15 16 1 1 9.1 dela y cycle inser tion in fine mode figure 15. uart ch. x clock control register (uart_clkx) register name ad dress bit name function setting init. r/w remarks uart ch. x clock control register (uart_clk x) 0x506c (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 utclkd [1:0] cloc k division r atio select utclkd[1:0] division r atio 0x0 r/w when the cloc k source is osc3b or osc3a 0x3 0x2 0x1 0x0 1/8 1/4 1/2 1/1 d3C2 utclksrc [1:0] cloc k source select utclksrc [1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 exter nal cloc k osc3a osc1 osc3b d1 C reser v ed C C C 0 when being read. d0 utclke count cloc k enab le 1 enab le 0 disab le 0 r/w d[7:6] reserved
15 u ar t 15-16 seiko epson corporation s1c17651 t echnical m anual d[5:4] utclkd[1:0]: clock division ratio select bits s e l e c t s t h e d i v i s i o n r a t i o f o r g e n e r a t i n g t h e c o u n t c l o c k o f t h e b a u d r a t e g e n e r a t o r w h e n o s c3b o r osc3a is used as the clock source. 9.3 osc3b/osc3a division ratio selection t ab le 15. utclkd[1:0] division ratio 0x3 1/8 0x2 1/4 0x1 1/2 0x0 1/1 (def ault: 0x0) d[3:2] utclksrc[1:0]: clock source select bits selects the count clock source for the baud rate generator . 9.4 cloc k source selection t ab le 15. utclksrc[1:0] cloc k sour ce 0x3 exter nal cloc k (sclkx) 0x2 osc3a 0x1 osc1 0x0 osc3b (def ault: 0x0) d1 reserved d0 utclke: count clock enable bit enables or disables the count clock supply to the counter of the baud rate generator . 1 (r/w): enabled (on) 0 (r/w): disabled (of f) (def ault) the utclke def ault setting is 0, which disables the clock supply . setting utclke to 1 sends the clock selected to the counter .
16 spi s1c17651 t echnical m anual seiko epson corporation 16-1 spi 16 spi module over vie w 16.1 the s1c17651 includes a synchronized serial interf ace module (spi). the follo wing sho ws the main features of the spi: ? number of channels: 1 channel ? supports both master and sla v e modes. ? data length: 8 bits f ix ed ? supports both msb f irst and lsb f irst modes. ? contains one-byte recei v e data b uf fer and one-byte transmit data b uf fer . ? supports full-duple x communicati ons. ? data transfer timing (clock phase and polarity v ariations) is selectable from among 4 types. ? can generate recei v e b uf fer full and transmit b uf fer empty interrupts. figure 16.1.1 sho ws the spi module conf iguration. shift register receive data buffer (1 byte) sdix pclk internal bus itc spi ch.x bus i/f and control registers spiclkx #spissx shift register transmit data buffer (1 byte) clock/transfer control sdox t8 ch.0 output clock interrupt control 1/4 1.1 spi module configur ation figure 16. note: the letter x in register and pin names ref ers to a channel n umber (0). example: spi_ctlx register ch.0: spi_ctl0 register spi input/output pins 16.2 t able 16.2.1 lists the spi pins. 2.1 list of spi pins t ab le 16. pin name i/o qty function sdi0 (ch.0) i 1 spi data input pin inputs ser ial data from spi b us . sdo0 (ch.0) o 1 spi data output pin outputs ser ial data to spi b us . spiclk0 (ch.0) i/o 1 spi e xter nal cloc k input/output pin outputs spi cloc k when spi is in master mode . inputs e xter nal cloc k when spi is used in sla v e mode . #spiss0 (ch.0) i 1 spi sla v e select signal (activ e lo w) input pin spi (sla v e mode) is selected as a sla v e de vice b y lo w input to this pin.
16 spi 16-2 seiko epson corporation s1c17651 t echnical m anual note: use an i/o (p) por t to output the sla v e select signal when the spi module is configured to master mode . the spi input/output pins (sdix, sdox, spiclkx, #spissx) are shared with i/o ports and are initially set as gen- eral purpose i/o port pins. the pin functions must be switched using the port function select bits to use the general purpose i/o port pins as spi input/output pins. f or detailed info rmation on pin function switching, see the i/o ports (p) chapter . spi cloc k 16.3 the master mode spi uses the 8-bit timer (t8) ch.0 output clock or a pclk/4 clock to generate the spi clock. this clock is output from the spiclkx pin to the sla v e de vice while also dri ving the shift re gister . use mclk/spi_ctlx re gister to select whether the t8 ch.0 output clock or pclk/4 clock is used. setting mclk to 1 selects the t8 ch.0 output clock; setting to 0 selects the pclk/4 clock. using the t8 ch.0 output clock enables programmable transfer rates. f or more information on t8 control, see the 8-bit timer (t8) chapter . pclk 8-bit timer ch.0 output clock or pclk/4 spi clock (spiclkx output) 3.1 master mode spi cloc k figure 16. in sla v e mode, the spi clock is input via the spiclkx pin. data t ransf er condition settings 16.4 t h e s p i m o d u l e c a n b e s e t t o m a s t e r o r s l a v e m o d e s . t h e s p i c l o c k p o l a r i t y / p h a s e a n d b i t d i r e c t i o n ( m s b f i r s t / l s b f irst) can also be set via the spi_ctlx re gister . the data length is f ix ed at 8 bits. note: mak e sure the spi module is halted (spen/spi_ctlx register = 0) b ef ore master/sla v e mode se- lection and cloc k condition settings . master/sla ve mode selection mssl/spi_ctlx re gister is used to set the spi module to master mode or sla v e mode. setting mssl to 1 sets master mode; setting it to 0 (def ault) sets sla v e mode. in master mode, data is transferred using the internal clock. in sla v e mode, data is transferred by inputting the master de vice clock. spi c loc k po larity and phase settings the spi clock polarity is selected by cpol/spi_ctlx re gister . setting cpol to 1 treats the spi clock as ac- ti v e lo w; setting it to 0 (def ault) treats it as acti v e high. the spi clock phase is selected by cpha/spi_ctlx re gister . as sho wn belo w , these control bits set transfer timing.
16 spi s1c17651 t echnical m anual seiko epson corporation 16-3 spiclkx (cpol = 1, cpha = 1) spiclkx (cpol = 1, cpha = 0) spiclkx (cpol = 0, cpha = 1) spiclkx (cpol = 0, cpha = 0) sdix/sdox fetching received data into shift register d7 (msb) d0 (lsb) 4.1 cloc k and data t r ansf er timing figure 16. msb fir st/lsb fir st settings use mlsb/spi_ctlx re gister to select whether the data msb or lsb is input/output f irst. msb f irst is selected when mlsb is 0 (def ault); lsb f irst is selected when mlsb is 1. data t ransf er contr ol 16.5 mak e the follo wing settings before starting data transfers. (1) select the spi clock source. (see section 16.3.) (2) select mast er mode or sla v e mode. (see section 16.4.) (3) set clock conditions. (see section 16.4.) (4) set the interrupt conditions to use spi interrupts. (see section 16.6.) note: mak e sure the spi is halted (spen/spi_ctlx register = 0) bef ore setting the abo v e conditions . enab ling data transf er s set spen/spi_ctlx re gister to 1 to enable spi operations. this enables spi transfers and clock input/output. note: do not set spen to 0 when the spi module is tr ansf err ing data. data transmission contr ol t o start data transmission, write the transmit data to sptdb[7:0]/spi_txdx re gister . the data is written to the transmit data b uf fer , and the spi module starts sending data. the b uf fer data is sent to the transmit shift re gister . in master mode, the module starts clock output from the spiclkx pin. in sla v e mode, the m odule a w aits clock input from the spiclkx pin. the data in the shift re gister is shifted in sequence a t t h e c l o c k r i s i n g o r f a l l i n g e d g e , a s d e t e r m i n e d b y c p h a / s p i _ c t l x r e g i s t e r a n d c p o l / s p i _ c t l x r e g i s t e r ( s e e figure 16.4.1) and sent from the sdox pin. note: mak e sure that spen is set to 1 bef ore wr iting data to the spi_txdx register . the spi module includes tw o status flags for transfer control: sptb e/spi_stx re gister and spbsy/spi_stx re gister . the sptbe flag indicates the transmit data b uf fer status. this flag switches to 0 when the application program writes data to the spi_txdx re gister (transmit data b uf fer) and re v erts to 1 when the b uf fer data is sent to the transmit shift re gister . an interrupt can be generated when this flag is set to 1 (see section 16.6). subsequent data is sent aft er conf irming that the transmit data b uf fer is empty either by using this interrupt or by inspecting the sptbe flag. the transmit data b uf fer size is 1 byte, b ut a shift re gister is pro vided separately to allo w data to be written while the pre vious data is being sent. al w ays conf irm that the transmit data b uf fer is empty before writing transmit data. writing data while the sptbe flag is 0 will o v e rwrite earlier transmit data inside the transmit data b uf fer . in master mode, the spbsy flag indicates the shift re gister status. this flag switches to 1 when transmit data is loaded from the transmit data b uf fer to the shift re gister and re v erts to 0 once the data is sent. read this flag to check whether the spi module is operating or at standby . in sla v e mode, spbsy flag indicates the spi sla v e selection signal (#spissx pin) status. the flag is set to 1 when the spi module is selected as a sla v e module and is set to 0 when the module is not selected.
16 spi 16-4 seiko epson corporation s1c17651 t echnical m anual note: when the spi module is used in master mode with cpha set to 0, the cloc k ma y change a mini- m um of one system cloc k (pclk) cycle time from change of the first tr ansmit data bit. pclk 8-bit timer output spi_txdx register spiclkx sdox wr ite minimum 1/f pclk 5.1 sdo figure 16. x and spiclk x change timings when cpha = 0 the half spiclkx cycle will be secured from change of data to change of the cloc k f or the second and f ollo wing tr ansmit data bits and the second and f ollo wing b ytes dur ing contin uous tr ansf er . data reception contr ol in master mode, write dummy data to sptdb[7:0]/spi_txdx re gister . writing to the spi_txdx re gister cre- ates the trigger for reception as well as transmission start. writing actual transmit data enables simultaneous transmission and reception. this starts the spi clock output from the spiclkx pin. note: mak e sure that spen is set to 1 bef ore wr iting data to the spi_txdx register . in sla v e mode, the module w aits until the clock is input from the spiclkx pin. there is no need to write to the spi_txdx re gister if no transmiss ion is required. the recei ving operation is started by the clock input from the master de vice. if data is transmitted simultaneously , write transmit data to the spi_txdx re gister before the clock is input. the data is recei v ed in sequence in the shift re gister at the rising or f alling edge of the clock determined by cpha/spi_ctlx re gister and cpol/spi_ctlx re gister . (see figure 16.4.1.) the recei v ed data is loaded into the recei v e data b uf fer once the 8 bits of data are recei v ed in the shift re gister . t h e r e c e i v e d d a t a i n t h e b u f f e r c a n b e r e a d f r o m s p r d b [ 7 : 0 ] / s p i _ r x d x r e g i s t e r . the spi module includes sprbf/spi_stx re gister for reception control. the sprbf flag indicates the recei v e data b uf fer status. this flag is set to 1 when the data recei v ed in the shift re gister is loaded into the r ecei v e data b uf fer , indicating that the recei v ed data can be read out. it re v erts to 0 when the b uf fer data is read out from the spi_rxdx re gister . an interrupt can be generated as soon as the flag is set to 1 (see section 16.6). the recei v ed data should be read out either by using this interrupt or by inspecting the sprbf flag to conf irm that the recei v e data b uf fer contains v alid recei v ed data. the recei v e data b uf fer is 1 byte in size, b ut a shift re gister is also pro vided, enabling recei v ed data to be retained in the b uf fer e v en while the subsequent data is being recei v ed. note that the recei v e data b uf fer should be read out before recei ving the subsequent data is complete. if recei ving the subsequent data is complete before the recei v e data b uf fer contents are read out, the ne wly rece i v ed data will o v erwrite the pre vious recei v ed data in the b uf fer . in master mode, the spbsy flag indicating the shift re gister status can be used in the same w ay while transfer - ring data.
16 spi s1c17651 t echnical m anual seiko epson corporation 16-5 pclk spen spi_txdx register shift register spiclkx pin (cpol = 0, cpha = 1) spiclkx pin (cpol = 0, cpha = 0) sdox pin sdix pin spi_rxdx register spbsy sptbe sprbf a d7 a d6 a d5 a d4 a d3 a d0 data a data b data c data a' data b' wr ite wr ite wr ite read read a d1 a d2 b d7 b d6 b d5 b d4 b d3 b d0 b d1 b d2 a' d7 a' d6 a' d5 a' d4 a' d3 a' d0 a' d1 a' d2 b' d7 b' d6 b' d5 b' d4 b' d3 b' d0 b' d1 b' d2 5.2 data t r ansmission/receiving timing char t (msb first) figure 16. disab ling data transf er s after a data transfer is completed (both transmission and reception), write 0 to spen to disable data transfers. conf irm that the sptbe flag is 1 and the spbsy flag is 0 before disabling data transfer . the data being transferred cannot be guaranteed if spen is set to 0 while data is being sent or recei v ed. s pi interrupts 16.6 each channel of the spi module includes a function for generating the follo wing tw o dif ferent types of interrupts. ? t ransmit b uf fer empty interrupt ? recei v e b uf fer full interrupt t h e s p i c h a n n e l o u t p u t s o n e i n t e r r u p t s i g n a l s h a r e d b y t h e t w o a b o v e i n t e r r u p t c a u s e s t o t h e i n t e r r u p t c o n t r o l l e r ( i t c ) . inspect the status flag to determine the interrupt cause occurred. t ransmit b uff er empty interrupt t o use this interrupt, set sptie/spi_ctlx re gister to 1. if sptie is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. when transmit data written to the transmit data b uf fer is transferred to the shift re gister , the spi module sets sptbe/spi_stx re gister to 1, indicating that the transmit data b uf fer is empty . if transmit b uf fer empty inter - rupts ar e enabled (sptie = 1), an interrupt request is sent simultaneously to the itc. an interrupt occurs if other interrupt conditions are met. y ou can inspect the sptbe flag in the spi interrupt handler routine to determine whether the spi interrupt is attrib utable to a transmit b uf fer empty . if sptbe is 1, the ne xt transmit data can be written to the transmit data b uf fer by the interrupt handler routi ne. receive b uff er full interrupt t o use this interrupt, set sprie/spi_ctlx re gister to 1. if sprie is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. when data recei v ed in the shift re gister is loaded into the recei v e data b uf fer , the spi module sets sprbf/spi_ stx re gister to 1, indicating that the recei v e data b uf fer contains readable recei v ed data. if recei v e b uf fer full interrupts are enabled (sprie = 1), an interrupt request is output to the itc at the same time. an interrupt occurs if other interrupt conditions are met. y ou can inspect the sprbf flag in the spi interrupt handler routine to determine whether the spi interrupt is attrib utable to a recei v e b uf fer full. if sprbf is 1, the recei v ed data can be read from the recei v e data b uf fer by the inte rrupt handler routine. f or more information on interrupt processing, see the interrupt controller (itc) chapter .
16 spi 16-6 seiko epson corporation s1c17651 t echnical m anual contr ol register details 16.7 7.1 list of spi registers t ab le 16. ad dress register name function 0x4320 spi_st0 spi ch.0 status register indicates tr ansf er and b uff er statuses . 0x4322 spi_txd0 spi ch.0 t r ansmit data register t r ansmit data 0x4324 spi_rxd0 spi ch.0 receiv e data register receiv e data 0x4326 spi_ctl0 spi ch.0 control register sets the spi mode and enab les data tr ansf er . the spi re gisters are described in detail belo w . note: when data is wr itten to the registers , the rese r v ed bits m ust alw a ys be wr itten as 0 and not 1. spi ch.x status register (spi_stx) register name ad dress bit name function setting init. r/w remarks spi ch.x status register (spi_stx) 0x4320 (16 bits) d15C3 C reser v ed C C C 0 when being read. d2 spbsy t r ansf er b usy flag (master) 1 busy 0 idle 0 r ss signal lo w flag (sla v e) 1 ss = l 0 ss = h d1 sprbf receiv e data b uff er full flag 1 full 0 not full 0 r d0 sptbe t r ansmit data b uff er empty flag 1 empty 0 not empty 1 r d[15:3] reserved d2 spbsy: transfer busy flag bit (master mode)/ss signal low flag bit (slave mode) master mode indicates the spi transfer status. 1 (r): operating 0 (r): standby (def ault) spbsy is set to 1 when the spi starts data transfer in master mode and is maintained at 1 while transfer is underw ay . it is cleared to 0 once the transfer is complete. sla v e mode indicates the sla v e selection (#spissx) signal status. 1 (r): lo w le v el (this spi is selected) 0 (r): high le v el (this spi is not selected) (def ault) spbsy is set to 1 when the master de vice asserts the #spissx signal to select this spi module (sla v e d e v i c e ) . i t i s r e t u r n e d t o 0 w h e n t h e m a s t e r d e v i c e c l e a r s t h e s p i m o d u l e s e l e c t i o n b y n e ga t i n g t h e #spissx signal. d1 sprbf: receive data buffer full flag bit indicates the recei v e data b uf fer status. 1 (r): data full 0 (r): no data (def ault) sprbf is set to 1 when data recei v ed in the shift re gister is sent to the recei v e data b uf fer (when recei v- ing is completed), indicating that the data can be read. it re v erts to 0 once the b uf fer data is read from the spi_rxdx re gister . d0 sptbe: transmit data buffer empty flag bit indi cates the transmit data b uf fer status. 1 (r): empty (def ault) 0 (r): data e xists sptbe is set to 0 when transmit data is written to the spi_txdx re gister (transmit data b uf fer), and is set to 1 when the data is transferred to the shift re gister (when transmission starts). t ransmission data must be written to the spi_txdx re gister when this bit is 1.
16 spi s1c17651 t echnical m anual seiko epson corporation 16-7 spi ch.x transmit data register (spi_txdx) register name ad dress bit name function setting init. r/w remarks spi ch.x transmit data register (spi_txdx) 0x4322 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 sptdb[7:0] spi tr ansmit data b uff er sptdb7 = msb sptdb0 = lsb 0x0 to 0xff 0x0 r/w d[15:8] reserved d[7:0] sptdb[7:0]: spi transmit data buffer bits sets transmit data to be written to the transmit data b uf fer . (def ault: 0x0) in master mode, transmission is started by writing data to this re gister . in sla v e mode, the contents of this re gister are sent to the shift re gister and transmission be gins when the clock is input from the mas- ter . sptbe/spi_stx re gister is set to 1 (empty) as soon as data written to this re gister has been transferred to the shift re gister . a transmit b uf fer empty interrupt is generated at the same time. the subsequent transmit data can then be written, e v en while data is being transmitted. serial con v erted data is output from the sdox pin, with the bit set to 1 as high le v el and the bit s et to 0 as lo w le v el. note: mak e sure that spen is set to 1 bef ore wr iting data to the spi_txdx register to star t data tr ans- mission/reception. spi ch.x receive data register (spi_rxdx) register name ad dress bit name function setting init. r/w remarks spi ch.x receive data register (spi_rxdx) 0x4324 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 sprdb[7:0] spi receiv e data b uff er sprdb7 = msb sprdb0 = lsb 0x0 to 0xff 0x0 r d[15:8] reserved d[7:0] sprdb[7:0]: spi receive data buffer bits contains the recei v ed data. (def ault: 0x0) sprbf/spi_stx re gister is set to 1 (data full) as soon as data is recei v ed and the shift re gister data has been transferred to the recei v e data b uf fer . a recei v e b uf fer full interrupt is generated at the same time. data can then be re ad until subsequent data is recei v ed. if recei ving the subsequent data is completed before the re gister has been read out, the ne w recei v ed data o v erwrites the contents. serial data input from the sdix pin is con v erted to parallel, with the high le v el bit set to 1 and the lo w le v el bit set to 0. the data is the loaded into this re gister . this re gister is read-only . spi ch.x control register (spi_ctlx) register name ad dress bit name function setting init. r/w remarks spi ch.x con- trol register (spi_ctlx) 0x4326 (16 bits) d15C10 C reser v ed C C C 0 when being read. d9 mclk spi cloc k source select 1 t8 ch.0 0 pclk/4 0 r/w d8 mlsb lsb/msb first mode select 1 lsb 0 msb 0 r/w d7C6 C reser v ed C C C 0 when being read. d5 sprie receiv e data b uff er full int. enab le 1 enab le 0 disab le 0 r/w d4 sptie t r ansmit data b uff er empty int. enab le 1 enab le 0 disab le 0 r/w d3 cpha cloc k phase select 1 data out 0 data in 0 r/w these bits m ust be set bef ore setting spen to 1. d2 cpol cloc k polar ity s elect 1 activ e l 0 activ e h 0 r/w d1 mssl master/sla v e mode select 1 master 0 sla v e 0 r/w d0 spen spi enab le 1 enab le 0 disab le 0 r/w note: do not access to the spi_ctlx register while spbsy/spi_stx register is set to 1 or sprbf/ spi_stx register is set to 1 (while data is being tr ansmitted/receiv ed). d[15:10] reserved
16 spi 16-8 seiko epson corporation s1c17651 t echnical m anual d9 mclk: spi clock source select bit selects the spi clock source. 1 (r/w): 8-bit timer ch.0 0 (r/w): pclk/4 (def ault) d8 mlsb: lsb/msb first mode select bit selects whether data is transferred with msb f irst or lsb f irst. 1 (r/w): lsb f irst 0 (r/w): msb f irst (def ault) d[7:6] reserved d5 sprie: receive data buffer full interrupt enable bit enables or disables spi recei v e data b uf fer full interrupts. 1 (r/w): enabled 0 (r/w): disabled (def ault) setting sprie to 1 enables the output of spi interrupt requests to the itc due to a recei v e da ta b uf fer full. these interrupt requests are generated when the data recei v ed in the shift re gister is transferred to the recei v e data b uf fer (when reception is completed). spi interrupts are not generated by recei v e data b uf fer full if sprie is set to 0. d4 sptie: transmit data buffer empty interrupt enable bit enables or disables spi transmit data b uf fer empty interrupts. 1 (r/w): enabled 0 (r/w): disabled (def ault) setting sptie to 1 enables the outp ut of spi interrupt requests to the itc due to a transmit data b uf fer empty . these interrupt requests are generated when the data written to the transmit data b uf fer is trans- ferred to the shift re gister (when transmission starts). spi interrupts are not generated by transmit data b uf fer empty if sptie is set to 0. d3 cpha: clock phase select bit selects the spi clock phase. (def ault: 0) set the data transfer timing together wi th cpol. (see figure 16.7.1.) d2 cpol: clock polarity select bit selects the spi clock polarity . 1 (r/w): acti v e lo w 0 (r/w): acti v e high (def ault) set the data transfer timing together with cpha. (see figure 16.7.1.) spiclkx (cpol = 1, cpha = 1) spiclkx (cpol = 1, cpha = 0) spiclkx (cpol = 0, cpha = 1) spiclkx (cpol = 0, cpha = 0) sdix/sdox fetching received data into shift register d7 (msb) d0 (lsb) 7.1 cloc k and data t r ansf er timing figure 16. d1 mssl: master/slave mode select bit sets the spi module to master or sla v e mode. 1 (r/w): master mode 0 (r/w): sla v e mode (def ault)
16 spi s1c17651 t echnical m anual seiko epson corporation 16-9 setting mssl to 1 selects master mode; setting it to 0 selects sla v e mode. master mode performs data transfer with the internal clock. in sla v e mode, data is transferred by inputting the clock from the master de vice. d0 spen: spi enable bit enables or disables spi module operation. 1 (r/w): enabled 0 (r/w): disabled (def ault) setting spen to 1 starts the spi module operation, enabling data transfer . setting spen to 0 s tops the spi module operation. note: the spen bit should be set to 0 bef ore setting the cpha, cpol, and mssl bits .
17 lcd driver (lcd) s1c17651 t echnical m anual seiko epson corporation 17-1 lcd dri v er (lcd) 17 lcd module over vie w 17.1 the s1c17651 includes an lcd dri v er capable of dri ving an lcd panel with up to 80 se gments (20 se gments 4 commons). the main features of the lcd dri v er are listed belo w . ? number of seg and com outputs 20 seg 4/3/2/1 com ? dri v e bias 1/3 bias (f ix ed) ? display data ram 20 bytes ? frame frequenc y conf iguration selectable from four dif ferent frequencies ? lcd display mode normal display mode all on mode all of f mode in v erted display mode ? other functions lfr o signal output, frame interrupt figure 17.1.1 sho ws the lcd dri v er and dri v e po wer supply conf iguration. comx segx lfro dspar dspc[1:0] lduty[2:0] frmcnt[1:0] dsprev to itc frame interrupt request v c1 Cv c3 lcd power supply circuit display memory driver control circuit clock control circuit ifrmen interrupt control circuit power supply circuit lcd driver lhvld vcsel lclk osc3a osc1 osc3b divider (1/1024C1/8192) divider (1/64) gate lcdtclke lcdtclkd[1:0] lcdtclksrc[1:0] 1.1 lcd dr iv er and dr iv er p o w er supply configur ation figure 17. lcd p o wer suppl y 17.2 the lcd dri v e v oltages v c1 to v c3 are ge nerated by the on-chip lc d po wer supply circuit. n o e xternal po wer sup- ply is needed. f or more information on the lcd po wer supply , see the po wer supply chapter .
17 lcd driver (lcd) 17-2 seiko epson corporation s1c17651 t echnical m anual lcd cloc k 17.3 figure 17.3.1 sho ws the lcd clock supply system. lfro output lclk frame signal lcdtclke frmcnt[1:0] divider osc3a osc1 osc3b divider (1/1024C1/8192) divider (1/64) lcdtclkd[1:0] lcdtclksrc[1:0] 3.1 lcd cloc k system figure 17. lcd operating cloc k (lclk) 17.3.1 cloc k sour ce selection select the clock source from osc3b, osc3a, and osc1 using lcdtclksrc[1:0]/lcd_tclk re gister . 3.1.1 cloc k source selection t ab le 17. lcdtclksrc[1:0] cloc k sour ce 0x3 reser v ed 0x2 osc3a 0x1 osc1 0x0 osc3b (def ault: 0x0) cloc k division ratio selection when the c loc k sour ce is osc1 no di vision ratio needs to be selected when osc1 is selected for the clock source. the osc1 clock is used as lclk after di viding by 64 (typ. 512 hz). when the c loc k sour ce is osc3b/osc3a when osc3b/osc3a is selected for the clock source, use lcdtclkd[1:0]/lcd_tcl k re gister to se- lect the di vision ratio. 3.1.2 osc3b/osc3a division ratio selection t ab le 17. lcdtclkd[1:0] division ratio 0x3 1/8192 0x2 1/4096 0x1 1/2048 0x0 1/1024 (def ault: 0x0) select a di vision ratio so that it will generate the lclk frequenc y nearest 512 hz. cloc k enab le t h e l c l k s u p p l y i s e n a b l e d w i t h l c d t c l k e / l c d _ t c l k r e g i s t e r . t h e l c d t c l k e d e f a u l t s e t t i n g i s 0, which stops the clock. setting lcdtclke to 1 feeds the clock generated as abo v e to the lcd dri v er . if no lcd display is required, s top the clock to reduce current consumption. if lclk is not supplied, the lcd cannot display . ho we v er , the lcd dri v er control re gisters and display mem- ory can be accessed e v en if lclk is stopped. note: be sure to set lcdtclke to 0 bef ore selecting a cloc k division r atio .
17 lcd driver (lcd) s1c17651 t echnical m anual seiko epson corporation 17-3 frame signal 17.3.2 the lcd dri v er generates the frame signal by di viding lclk. the clock di vision ratio can be set using frm- cnt[1:0]/lcd_cctl re gister . figures 17.4.2.1 to 17.4.2.4 sho w one c ycle of the frame frequenc y as 1 frame. t ables 17.3.2.1 and 17.3.2.2 list the frame frequencies that can be programmed. when the c loc k sour ce is osc1 3.2.1 f r ame f requency settings (when the cloc k source is osc1 = 32.768 khz (lclk = 512 hz)) t ab le 17. drive duty (lduty[2:0] setting) frmcnt[1:0] setting (lclk division ratio) 0x0 0x1 0x2 0x3 1/4 duty (0x3) 128 hz (1/4) 64 hz (1/8) * 42.67 hz (1/12) 32 hz (1/16) 1/3 duty (0x2) 85.33 hz (1/6) 56.89 hz (1/9) 42.67 hz (1/12) 34.13 hz (1/15) 1/2 duty (0x1) 128 hz (1/4) 64 hz (1/8) 42.67 hz (1/12) 32 hz (1/16) static (0x0) 128 hz (1/4) 64 hz (1/8) 42.67 hz (1/12) 32 hz (1/16) * def ault setting when the c loc k sour ce is osc3b/osc3a 3.2.2 f r ame f requency settings (when the cloc k source is osc3b/osc3a) t ab le 17. drive duty (lduty[2:0] setting) frmcnt[1:0] setting 0x0 0x1 0x2 0x3 1/4 duty (0x3) f osc3 lcdtclkd CCCCCCCC CCCCCCCC 4 f osc3 lcdtclkd * CCCCCCCC CCCCCCCC 8 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 12 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 16 1/3 duty (0x2) f osc3 lcdtclkd CCCCCCCC CCCCCCCC 6 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 9 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 12 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 15 1/2 duty (0x1) f osc3 lcdtclkd C CCCCCCC CCCCCCCC 4 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 8 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 12 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 16 static (0x0) f osc3 lcdtclkd CCCCCCCC CCCCCCCC 4 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 8 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 12 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 16 * def ault setting f osc3 : osc3b or osc3a cloc k frequency lcdtclkd: osc3b/osc3a division r atio (1/1024 to 1/8192) the frame signal gen erated can be output to an e xternal de vice via the lfr o pin. ho we v er , the output pin must be switched for lfr o output using the port function select bit, as the pin is conf igured for an i/o port by def ault. f or detailed information on pin function switching, see the i/o ports (p) chapter . drive duty contr ol 17.4 drive duty switc hing 17.4.1 dri v e duty can be set to 1/4, 1/3, 1/2 or static dri v e us ing lduty[2:0]/lcd_cctl re gister . t able 17.4.1.1 sho ws the correspondence between lduty[2:0] settings, dri v e duty , and maximum number of display se gments. 4.1.1 dr iv e duty settings (s1c17624/622) t ab le 17. lduty[2:0] duty v alid com pins v alid seg pins max. n umber of displa y segments 0x7C0x4 reser v ed C C C 0x3 1/4 com0 to com3 seg0 to seg19 80 segments 0x2 1/3 com0 to com2 seg0 to seg19 60 segments 0x1 1/2 com0 to com1 seg0 to seg19 40 segments 0x0 static com0 seg0 to seg19 20 segments (def ault: 0x3) the dri v e bias is f ix ed at 1/3 (three potentials v c1 , v c2 , v c3 ) for all duty settings.
17 lcd driver (lcd) 17-4 seiko epson corporation s1c17651 t echnical m anual drive w a vef orm 17.4.2 figures 17.4.2.1 to 17.4.2.4 sho ws the dri v e w a v eforms according to the duty selections. 01 23 01 23 lfro com0 com1 v dd v ss v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss com2 v c3 v c2 v c1 v ss com3 v c3 v c2 v c1 v ss com0 1 2 3 segx v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss segx 1 frame frame interrupt frame interrupt lcd display status off on 4.2.1 1/4 duty dr iv e w a v ef or m figure 17.
17 lcd driver (lcd) s1c17651 t echnical m anual seiko epson corporation 17-5 0 1 2 0 1 2 lfro com0 com1 v dd v ss v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss com2 v c3 v c2 v c1 v ss com0 1 2 segx v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss segx 1 frame frame interrupt frame interrupt lcd display status off on 4.2.2 1/3 duty dr iv e w a v ef or m figure 17.
17 lcd driver (lcd) 17-6 seiko epson corporation s1c17651 t echnical m anual 0 1 0 1 lfro com0 com1 v dd v ss v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss com0 1 segx v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss segx 1 frame frame interrupt frame interrupt lcd display status off on 4.2.3 1/2 duty dr iv e w a v ef or m figure 17. 0 0 lfro com0 1 frame frame interrupt frame interrupt lcd display status v dd v ss v c3 v c2 v c1 v ss com0 segx v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss off on segx 4.2.4 static dr iv e w a v ef or m figure 17.
17 lcd driver (lcd) s1c17651 t echnical m anual seiko epson corporation 17-7 displa y memor y 17.5 the s1c17651 includes a 20-byte display memory (address 0x53c0 to address 0x53d3). f i g u r e s 17.5.1 t o 17.5.4 s h o w t h e c o r r e s p o n d e n c e b e t w e e n d i s p l a y m e m o r y a n d c o m / s e g p i n s f o r e a c h d r i v e duty . writing 1 to a display memory bit corresponding to a se gment on the lcd panel turns the se gment on, while writ- ing 0 turns the se gment of f. since the display memory is a ram allo wing readin g and writing, bits can be con- trolled indi vidually using logic operation instructions (read-modify-write instructions). bits (d[3:0]) not assigned to the display area within the display memory can be used as general-purpose ram that can be read and written to. bit address com pin 0x53c0 0x53c1 0x53c2 0x53c3 0x53c4 0x53c5 0x53c6 0x53c7 0x53c8 0x53c9 0x53ca 0x53cb 0x53cc 0x53cd 0x53ce 0x53cf 0x53d0 0x53d1 0x53d2 0x53d3 d0 com0 d1 displa y area com1 d2 com2 d3 com3 d4 una v ailab le area (0 when being read) C d5 C d6 C d7 C seg pin seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 5.1 displa y memor y map (1/4 duty) figure 17. bit address com pin 0x53c0 0x53c1 0x53c2 0x53c3 0x53c4 0x53c5 0x53c6 0x53c7 0x53c8 0x53c9 0x53ca 0x53cb 0x53cc 0x53cd 0x53ce 0x53cf 0x53d0 0x53d1 0x53d2 0x53d3 d0 com0 d1 displa y area com1 d2 com2 d3 un used area (gener al-pur pose memor y) C d4 una v ailab le area (0 when being read) C d5 C d6 C d7 C seg pin seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 5.2 displa y memor y map (1/3 duty) figure 17. bit address com pin 0x53c0 0x53c1 0x53c2 0x53c3 0x53c4 0x53c5 0x53c6 0x53c7 0x53c8 0x53c9 0x53ca 0x53cb 0x53cc 0x53cd 0x53ce 0x53cf 0x53d0 0x53d1 0x53d2 0x53d3 d0 displa y area com0 d1 com1 d2 un used area (gener al-pur pose memor y) C d3 C d4 una v ailab le area (0 when being read) C d5 C d6 C d7 C seg pin seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 5.3 displa y memor y map (1/2 duty) figure 17.
17 lcd driver (lcd) 17-8 seiko epson corporation s1c17651 t echnical m anual bit address com pin 0x53c0 0x53c1 0x53c2 0x53c3 0x53c4 0x53c5 0x53c6 0x53c7 0x53c8 0x53c9 0x53ca 0x53cb 0x53cc 0x53cd 0x53ce 0x53cf 0x53d0 0x53d1 0x53d2 0x53d3 d0 displa y area com0 d1 un used area (gener al-pur pose memor y) C d2 C d3 C d4 una v ailab le area (0 when being read) C d5 C d6 C d7 C seg pin seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 5.4 displa y memor y map (static dr iv e) figure 17. displa y contr ol 17.6 displa y on/off 17.6.1 the lcd display state is controlled using dspc[1:0]/lcd_dctl re gister . 6.1.1 lcd displa y control t ab le 17. dspc[1:0] lcd displa y 0x3 all off (static) 0x2 all on (dynamic) 0x1 nor mal displa y 0x0 displa y off (def ault: 0x0) f or normal display , set dspc[1:0] to 0x1. note that the clock must be supplied. (see section 17.3.) if display of f is selected, the dri v e v oltage supplied from the lcd po wer supply circuit stops, and the v c1 to v c3 pins are all set to v ss le v el. since all on and all of f directly control the d ri ving w a v eform output by the lcd dri v er , display memory data is not altered. com pins are set to dynamic dri v e for all on and to static dri v e for all of f. this function can be used to mak e the display flash on and of f without altering the display memory . dspc[1:0] is reset to 0x0 (display of f) after an initial reset. dspc[1:0] is also reset to 0x0 when the slp instruction is e x ecuted and it re v er ts to the pre vious setting after sleep mode is canceled. in ver ted displa y 17.6.2 the lcd display can be in v erted (black/white in v ersion) using merely control bit manipulation, without changing the display memory . setting dsprev/lcd_dctl re gister to 0 in v erts the display; setting to 1 returns the display to normal status. note that the display will not be in v erted if all of f is selected using dspc[ 1:0]. the display will be in v erted when all on is selected.
17 lcd driver (lcd) s1c17651 t echnical m anual seiko epson corporation 17-9 lcd interrupt 17.7 the lcd module includes a function for generating interrupts using the frame signal. frame interrupt t h i s c a u s e o f i n t e r r u p t o c c u r s e v e r y f r a m e a n d s e t s t h e i n t e r r u p t f l a g i f r m f l g / l c d _ i f l g r e g i s t e r i n t h e lcd module to 1. see figures 17.4.2.1 to 17.4.2.4 for interrupt timings. t o use this interrupt, set ifrmen/lcd_imsk re gister to 1. when ifrmen is set to 0 (def ault), interrupt r e- quests for this interrupt cause are not sent to the interrupt controller (itc). if ifrmflg is set to 1 while ifrmen is set to 1 (interrupt enabled), the lcd module outputs an interrupt re- quest to the itc. an interrupt is generated if the itc and s1c17 core interrupt conditions are satisf ied. f or more information on interrupt processing, see the interrupt controller (itc) chapter . notes: ? t o pre v e nt interr upt recurrences , the lcd module interr upt flag ifrmflg m ust be reset in the interr upt handler routine after an lcd interr upt has occurred. ? t o p r e v e n t u n w a n t e d i n t e r r u p t s , i f r m f l g s h o u l d b e r e s e t b e f o r e e n a b l i n g l c d i n t e r r u p t s w i t h ifrmen. contr ol register details 17.8 8.1 list of lcd registers t ab le 17. ad dress register name function 0x5070 lcd_tclk lcd cloc k select register selects the lcd cloc k. 0x50a0 lcd_dctl lcd displa y control register controls the lcd displa y . 0x50a2 lcd_cctl lcd cloc k control register controls the lcd dr iv e duty . 0x50a3 lcd_vreg lcd v oltage regulator control register controls the lcd dr iv e v oltage regulator . 0x50a5 lcd_imsk lcd interr upt mask register enab les/disab les interr upts . 0x50a6 lcd_iflg lcd interr upt flag register indicates/resets interr upt occurrence status . the lcd module re gisters are described in detail belo w . note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. lcd timing clock select register (lcd_tclk) register name ad dress bit name function setting init. r/w remarks lcd timing clock select register (lcd_tclk ) 0x5070 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 lcdtclkd [1:0] lcd cloc k division r atio select lcdtclkd [1:0] division r atio 0x0 r/w osc3b/ osc3a osc1 0x3 0x2 0x1 0x0 1/8192 1/4096 1/2048 1/1024 1/64 1/64 1/64 1/64 d3C2 lcdtclk src[1:0] lcd cloc k source select lcdtclk src[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3a osc1 osc3b d1 C reser v ed C C C 0 when being read. d0 lcdtclke lcd cloc k enab le 1 enab le 0 disab le 0 r/w d[7:6] reserved d[5:4] lcdtclkd[1:0]: lcd clock division ratio select bits selects the di vision ratio when osc3b or osc3a is selected as the lcd clock source.
17 lcd driver (lcd) 17-10 seiko epson corporation s1c17651 t echnical m anual 8.2 cloc k division ratio selection t ab le 17. lcdtclkd[1:0] division ratio 0x3 1/8192 0x2 1/4096 0x1 1/2048 0x0 1/1024 (def ault: 0x0) no di vision ratio needs to be selected if osc1 is selected as the lcd clock source (f ix ed at 1/64). d[3:2] lcdtclksrc[1:0]: lcd clock source select bits selects the lcd clock source. 8.3 cloc k source selection t ab le 17. lcdtclksrc[1:0] cloc k sour ce 0x3 reser v ed 0x2 osc3a 0x1 osc1 0x0 osc3b (def ault: 0x0) d1 reserved d0 lcdtclke: lcd clock enable bit enables or disables the lcd clock supply to the lcd dri v er . 1 (r/w): enabled (on) 0 (r/w): disabled (of f) (def ault) the lcdtclke def ault setting is 0, which stops the clock. setting lcdtclke to 1 feeds the clock to the lcd dri v er . if no lcd display is required, stop the clock to reduce current consumption. lcd display control register (lcd_dctl) register name ad dress bit name function setting init. r/w remarks lcd display control register (lcd_dctl) 0x50a0 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 dsprev re v erse displa y control 1 nor mal 0 re v erse 1 r/w d3C2 C reser v ed C C C 0 when being read. d1C0 dspc[1:0] lcd displa y control dspc[1:0] displa y 0x0 r/w 0x3 0x2 0x1 0x0 all off all on nor mal displa y displa y off d[7:5] reserved d4 dsprev: reverse display control bit in v erts (ne g ati v e display) the lcd display . 1 (r/w): normal display (def ault) 0 (r/w): in v erted display setting dsprev to 0 in v erts the lcd panel display; setting to 1 returns the display to normal status. this operation does not af fect the contents of the display memory . d[3:2] reserved d[1:0] dspc[1:0]: lcd display control bits controls the lcd display . 8.4 lcd displa y control t ab le 17. dspc[1:0] lcd displa y 0x3 all off (static) 0x2 all on (dynamic) 0x1 nor mal displa y 0x0 displa y off (def ault: 0x0)
17 lcd driver (lcd) s1c17651 t echnical m anual seiko epson corporation 17-11 f or normal display , set dspc[1:0] to 0x1. note that the clock must be supplied. (see section 17.3.) if display of f is selected, the dri v e v oltage supplied from the lcd po wer supply circuit stops, and the v c1 to v c3 pins are all set to v ss le v el. since all on and all of f directly control the dri ving w a v eform output by the lcd dri v er , display memory data is not altered. com pins are set to dy namic dri v e for all on and to static dri v e for all of f. this function can be used to mak e the display flash on and of f without altering the display memo- ry . dspc[1:0] is reset to 0x0 (display of f) after an initial reset. dspc[1:0] is also reset to 0x0 when the slp instruction is e x ecuted and it re v erts to the pre vious setting after sleep mode is canceled. lcd clock control register (lcd_cctl) register name ad dress bit name function setting init. r/w remarks lcd clock control register (lcd_cctl) 0x50a2 (8 bits) d7C6 frmcnt[1:0] f r ame frequency control frmcnt[1:0] division r atio 0x1 r/w source cloc k: lclk 0x3 0x2 0x1 0x0 1/16 1/12 1/8 1/4 d5C3 C reser v ed C C C 0 when being read. d2C0 lduty[2:0] lcd duty select lduty[2:0] duty 0x3 r/w 0x7C0x4 0x3 0x2 0x1 0x0 reser v ed 1/4 1/3 1/2 static d[7:6] frmcnt[1:0]: frame frequency control bits sets the frame frequenc y . 8.5 f r ame f requency settings (when the cloc k source is osc1 = 32.768 khz (lclk = 512 hz)) t ab le 17. drive duty (lduty[2:0] setting) frmcnt[1:0] setting (lclk division ratio) 0x0 0x1 0x2 0x3 1/4 duty (0x3) 128 hz (1/4) 64 hz (1/8) * 42.67 hz (1/12) 32 hz (1/16) 1/3 duty (0x2) 85.33 hz (1/6) 56.89 hz (1/9) 42.67 hz (1/12) 34.13 hz (1/15) 1/2 duty (0x1) 128 hz (1/4) 64 hz (1/8) 42.67 hz (1/12) 32 hz (1/16) static (0x0) 128 hz (1/4) 64 hz (1/8) 42.67 hz (1/12) 32 hz (1/16) * def ault setting 8.6 f r ame f requency settings (when the cloc k source is osc3b/osc3a) t ab le 17. drive duty (lduty[2:0] setting) frmcnt[1:0] setting 0x0 0x1 0x2 0x3 1/4 duty (0x3) f osc3 lcdtclkd CCCCCCCC CCCCCCCC 4 f osc3 lcdtclkd * CCCCCCCC CCCCCCCC 8 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 12 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 16 1/3 duty (0x2) f osc3 lcdtclkd CCCCCCCC CCCCCCCC 6 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 9 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 12 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 15 1/2 duty (0x1) f osc3 lcdtclkd C CCCCCCC CCCCCCCC 4 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 8 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 12 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 16 static (0x0) f osc3 lcdtclkd CCCCCCCC CCCCCCCC 4 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 8 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 12 f osc3 lcdtclkd CCCCCCCC CCCCCCCC 16 * def ault setting f osc3 : osc3b or osc3a cloc k frequency lcdtclkd: osc3b/osc3a division r atio (1/1024 to 1/8192) d[5:3] reserved
17 lcd driver (lcd) 17-12 seiko epson corporation s1c17651 t echnical m anual d[2:0] lduty[2:0]: lcd duty select bits selects the dri v e duty . 8.7 dr iv e duty settings t ab le 17. lduty[2:0] duty v alid com pins v alid seg pins max. n umber of displa y segments 0x7C0x4 reser v ed C C C 0x3 1/4 com0 to com3 seg0 to seg19 80 segments 0x2 1/3 com0 to com2 seg0 to seg19 60 segments 0x1 1/2 com0 to com1 seg0 to seg19 40 segments 0x0 static com0 seg0 to seg19 20 segments (def ault: 0x3) lcd voltage regulator control register (lcd_vreg) register name ad dress bit name function setting init. r/w remarks lcd voltage regulator control register (lcd_vreg) 0x50a3 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 lhvld v c hea vy load protection mode 1 on 0 off 0 r/w d3C1 C reser v ed C C C 0 when being read. d0 vcsel ref erence v oltage select 1 v c2 0 v c1 0 r/w f o r m o r e i n f o r m a t i o n o n t h e c o n t r o l b i t , s e e l c d v o l t a g e r e g u l a t o r c o n t r o l r e g i s t e r ( l c d _ v r e g ) i n t h e p o w e r supply chapter . lcd interrupt mask register (lcd_imsk) register name ad dress bit name function setting init. r/w remarks lcd interrupt mask register (lcd_imsk) 0x50a5 (8 bits) d7C1 C reser v ed C C C 0 when being read. d0 ifrmen f r ame signal interr upt enab le 1 enab le 0 disab le 0 r/w d[7:1] reserved d0 ifrmen: frame signal interrupt enable bit enables or disables frame interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting ifrmen to 1 enables lcd interrupt requests to the itc. setting to 0 disables interrupts. lcd interrupt flag register (lcd_iflg) register name ad dress bit name function setting init. r/w remarks lcd interrupt flag register (lcd_iflg) 0x50a6 (8 bits) d7C1 C reser v ed C C C 0 when being read. d0 ifrmflg f r ame signal interr upt flag 1 occurred 0 n o t o c c u r r e d 0 r/w reset b y wr iting 1. d[7:1] reserved d0 ifrmflg: frame signal interrupt flag bit indicates the frame interrupt cause occurrence status. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored ifrmflg is set to 1 at the frame signal rising edge. ifrmflg is reset to 0 by writing 1.
18 sound genera t or (snd) s1c17651 t echnical m anual seiko epson corporation 18-1 sound generator (snd) 18 snd module over vie w 18.1 the s1c17651 includes a sound generator (snd) for generating a b uzzer signal. the main features of the snd module are outlined belo w . ? pro vides b uzzer in v erted and non-in v erted output pins to directly dri v e a piezoelectric b uzzer . ? programmable b uzzer signal frequenc y (eight frequencies) and v olume le v el (eight le v els) ? duty ratio controlled digital en v elope function (attenuation time is selectable from four types.) ? one-shot output function (output time is selectable from four types.) figure 18.1.1 sho ws the snd conf iguration. bz #bz osc1 gate programmable divider duty ratio control circuit envelope addition circuit one-shot buzzer control circuit buzzer output control circuit snd sndclke bzmd[1:0] bztm[1:0] bzen bzfq[2:0] bzdt[2:0] 1.1 snd module configur ation figure 18. snd output pins 18.2 t able 18.2.1 lists the snd pins. 2.1 list of snd pins t ab le 18. pin name i/o qty function bz o 1 buzz er non-in v er ted output pin outputs the b uzz er signal gener ated b y the sound gener ator . #bz o 1 buzz er in v er ted output pin outputs the in v er ted b uzz er signal gener ated b y the sound gener ator . the snd module output pins (bz, #bz) are shared with i/o ports and are initially set as general purpose i/o port pins. the pin functions must be switched using the port function sele ct bits to use the general purpose i/o port pins as snd module output pins. f or detailed information on pin function switching, see the i/o ports (p) chapter . snd operating cloc k 18.3 the snd module uses the osc1 clock (32.768 khz t yp.) output from the clg as its operating clock. the osc1 clock supply to the snd module is enabled with sndclke/snd_clk re gister . the sndclke de- f ault setting is 0, wh ich stops the clock. setting sndclke to 1 feeds the osc1 clock to the snd module. set sndclke to 1 before performing b uzzer output. if no b uzzer output is required, stop the clock to reduce current consumption. f or more information on osc1 oscillator control, see the clock generator (clg) chapter . note: this chapter descr ibes b uzz er frequencies and one-shot output times assuming that the osc1 cloc k f requency is 32.768 khz. the frequencies and times v ar y depending on the osc1 cloc k fre- quency .
18 sound genera t or (snd) 18-2 seiko epson corporation s1c17651 t echnical m anual buzz er frequenc y and v olume settings 18.4 buzz er frequenc y 18.4.1 the snd module generates the b uzzer signal by di viding the osc1 clock (32.768 khz). the b uzzer frequenc y can be selected from among the eight types with dif ferent di vision ratios. bzfq[2:0]/snd_bzfq is used for this selec- tion. 4.1.1 buzz er f requency selections t ab le 18. bzfq[2:0] buzz er frequenc y (hz) 0x7 1170.3 0x6 1365.3 0x5 1638.4 0x4 2048.0 0x3 2340.6 0x2 2730.7 0x1 3276.8 0x0 4096.0 (def ault: 0x0) v olume le vel 18.4.2 the b uzzer v olume le v el is controlled by changing the duty ratio of the b uzzer signal. the v olume le v el can be selected from among eight types using bzdt[2:0]/snd_bzdt re gister . 4.2.1 v olume le v el settings t ab le 18. v olume le vel bzdt[2:0] duty ratio b y b uzz er frequenc y (hz) 4096.0 3276.8 2730.7 2340.6 2048.0 1638.4 1365.3 1170.3 le v el 1 (max.) 0x0 8/16 8/20 12/24 12/28 le v el 2 0x1 7/16 7/20 11/24 11/28 le v el 3 0x2 6/16 6/20 10/24 10/28 le v el 4 0x3 5/16 5/20 9/24 9/28 le v el 5 0x4 4/16 4/20 8/24 8/28 le v el 6 0x5 3/16 3/20 7/24 7/28 le v el 7 0x6 2/16 2/20 6/24 6/28 le v el 8 (min.) 0x7 1/16 1/20 5/24 5/28 (def ault: 0x0) setting bzdt[2:0] to 0x0 turns the v olume up to maxim um le v el; setting it to 0x7 turns the v olume do wn to mini- mum le v el. level 1 (max.) level 2 level 3 level 4 level 5 level 6 level 7 level 8 (min.) h duty ratio = cycle h cycle 4.2.1 buzz er signal w a v ef or ms b y diff erent duty ratios figure 18. note: b z d t [2:0] i s i n e f f e c t i v e i n e n v e l o p e m o d e , a s t h e d u t y r a t i o i s a u t o m a t i c a l l y c o n t r o l l e d b y t h e hardw are .
18 sound genera t or (snd) s1c17651 t echnical m anual seiko epson corporation 18-3 buzz er mode and output contr ol 18.5 buzz er mode selection 18.5.1 the snd module supports three b uzzer modes that allo w dif ferent types of b uzzer outputs. bzmd[1:0]/snd_ctl re gister is used to select a b uzzer mode. 5.1.1 buzz er mode t ab le 18. bzmd[1:0] buzz er mode 0x3 reser v ed 0x2 en v elope mode a softw are tr igger star ts b uzz er output. the snd module automatically tur ns do wn the v ol- ume from le v el 1 (maxim um) and stops output when the v olume reaches le v el 8 (minim um). 0x1 one-shot mode this mode is pro vided f or gener ating shor t b uzz er sounds such as k e y oper ation sounds . the b uzz er output star ts b y a softw are tr igger and stops automatically afte r the specified time has elapsed. 0x0 nor mal mode buzz er output is tur ned on and off via softw are . (def ault: 0x0) output contr ol in normal mode 18.5.2 in normal mode, setting bzen/snd_ctl re gister to 1 starts b uzzer output and setting it to 0 stops the output. the b uzzer frequenc y setting with bzfq[2:0] and v olume setting with bzdt[2:0] are both ef fecti v e. bzen bz output #bz output 1 00 5.2.1 buzz er output in nor mal mode figure 18. note: the b uzz er signal is gener ated asynchronously to bzen, so a hazard ma y occur when the signal is tur ned on or off b y setting bzen. output contr ol in one-shot mode 18.5.3 the snd module has a one-shot output function for generating short b uzzer sounds such as k e y operation sounds. output time selection the one-shot b uzzer output time can be selected f rom among four types sho wn belo w using bztm[1:0]/snd_ ctl re gister . 5.3.1 one-shot buzz er output time selections t ab le 18. bztm[1:0] output time 0x3 125 ms 0x2 62.5 ms 0x1 31.25 ms 0x0 15.63 ms (def ault: 0x0) output contr ol writing 1 to bzen/snd_ctl re gister starts one-shot b uzzer output. when this trigger is issued, a b uzzer sig- nal is output from the b uzzer output pin. when the set time has elapsed, the b uzzer output stops. bzen functions as a status bit. it retains 1 while a one-shot b uzzer signal is being output and re v erts to 0 upon completion of the output.
18 sound genera t or (snd) 18-4 seiko epson corporation s1c17651 t echnical m anual writing 0 to bzen while a one-shot b uzzer signal is being output stops the output immediately . writing 1 to bzen ag ain before a one-shot b uzzer output is f inished, a ne w one-shot output be gins from that point. the b uzzer frequenc y setting with bzfq[2:0] and v olume setting with bzdt[2:0] are both ef fecti v e in one- shot mode. figure 18.5.3.1 sho ws a timing chart in one-shot mode. bzen (wr) bzen (rd) bz output #bz output 125/62.5/31.25/15.63 ms write 1 write 0 write 1 5.3.1 buzz er output in one-shot mode figure 18. output contr ol in en velope mode 18.5.4 in en v elope mode, a digital en v elope by duty control can be added to the b uzzer signal. the snd module controls en v elope by changing the duty ratio from le v el 1 (maximum) to le v el 8 (minimum) listed in t able 18.4.2.1. atten uation time selection the en v elope attenuation time (time to change the duty ratio) can be s elected from among four types using bztm[1:0]/snd_ctl re gister . 5.4.1 en v elope atten uation time selections t ab le 18. bztm[1:0] atten uation time 0x3 125 ms 0x2 62.5 ms 0x1 31.25 ms 0x0 15.63 ms (def ault: 0x0) output contr ol writing 1 to bzen/snd_ctl re gister starts b uzzer output in en v elope mode. the duty ratio is set to le v el 1 (maximum) at the be ginning of the output and is stepped do wn e v ery attenuation time selected. when attenu- ated do wn to le v el 8 (minimum), the b uzzer output stops. bzen functions as a status bit. it retains 1 while a b uzzer signal is being output and re v erts to 0 upon comple- tion of the output. writing 0 to bzen while a b uzzer signal is being output stops the output immediately . writing 1 to bzen ag ain before a b uzzer output is f inished, the duty ratio returns to the maximum le v el and a ne w en v elope output be gins from that point. figure 18.5.4.1 sho ws a timing chart in en v elope mode.
18 sound genera t or (snd) s1c17651 t echnical m anual seiko epson corporation 18-5 bzen (wr) bzen (rd) bz output #bz output duty ratio (volume level) write 1 125/62.5/31.25/15.63 ms write 0 write 1 level 1 2 3 4 5 6 7 8 5.4.1 buzz er output in en v elope mode figure 18. contr ol register details 18.6 6.1 list of snd registers t ab le 18. ad dress register name function 0x506e snd_clk snd cloc k control register controls the snd cloc k. 0x5180 snd_ctl snd control register controls b uzz er outputs . 0x5181 snd_bzfq buzz er f requency control register sets the b uzz er frequency . 0x5182 snd_bzdt buzz er duty ratio control register sets the b uzz er signal duty r atio . the snd module re gisters are described in detail belo w . note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. snd clock control register (snd_clk) register name ad dress bit name function setting init. r/w remarks snd clock control register (snd_clk) 0x506e (8 bits) d7C1 C reser v ed C C C 0 when being read. d0 sndclke snd cloc k enab le 1 enab le 0 disab le 0 r/w d[7:1] reserved d0 sndclke: snd clock enable bit enables or disables the osc1 clock supply to the snd module. 1 (r/w): enabled (on) 0 (r/w): disabled (of f) (def ault) the sndclke def ault setting is 0, which disables the clock supply . setting sndclke to 1 sends the osc1 clock to the snd module to enable b uzzer outputs. if no b uzzer output is required, stop the c lock to reduce current consumption. snd control register (snd_ctl) register name ad dress bit name function setting init. r/w remarks snd control register (snd_ctl) 0x5180 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 bztm[1:0] buzz er en v elope time/one-shot output time select bztm[1:0] time 0x0 r/w 0x3 0x2 0x1 0x0 125 ms 62.5 ms 31.25 ms 15.63 ms d3C2 bzmd[1:0] buzz er mode select bzmd[1:0] mode 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed en v elope one-shot nor mal d1 C reser v ed C C C 0 when being read. d0 bzen buzz er output control 1 on/t r igger 0 off 0 r/w d[7:6] reserved
18 sound genera t or (snd) 18-6 seiko epson corporation s1c17651 t echnical m anual d[5:4] bztm[1:0]: buzzer envelope time/one-shot output time select bits selects an en v elope attenuation time or a one-shot output time. 6.2 en v elope atten uation time/one-shot buzz er output time selections t ab le 18. bztm[1:0] a t t e n u a t i o n t i m e / o n e - s h o t o u t p u t t i m e 0x3 125 ms 0x2 62.5 ms 0x1 31.25 ms 0x0 15.63 ms (def ault: 0x0) i n e n v e l o p e m o d e , a n a t t e n u a t i o n t i m e ( t i m e t o c h a n g e t h e d u t y r a t i o ) c a n b e s e l e c t e d ( s e e f i g u r e 18.5.4.1). in one-shot mode, a one-shot b uzzer output time can be selected (see figure 18.5.3.1). bztm[1:0] does not af fect b uzzer outputs in normal mode. d[3:2] bzmd[1:0]: buzzer mode select bits selects a b uzzer mode. 6.3 buzz er mode t ab le 18. bzmd[1:0] buzz er mode 0x3 reser v ed 0x2 en v elope mode a softw are tr igger star ts b uzz er output. the snd module automatically tur ns do wn the v o l u m e f r o m l e v e l 1 ( m a x i m u m ) a n d s t o p s o u t p u t w h e n t h e v o l u m e r e a c h e s l e v e l 8 (minim um). 0x1 one-shot mode this mode is pro vided f or gener ating shor t b uzz er sounds such as k e y oper ation sounds . the b uzz er output star ts b y a softw are tr igger and stops automatically after the specified time has elapsed. 0x0 nor mal mode buzz er output is tur ned on and off via softw are . (def ault: 0x0) d1 reserved d0 bzen: buzzer output control bit controls b uzzer output. 1 (r/w): on/t rigger 0 (r/w): of f (def ault) nor mal mode setting bzen to 1 starts b uzzer output and setting it to 0 stops the output. one-shot mode writing 1 to bzen starts one-shot b uzzer output. when the time set with bztm[1:0] has elapsed, the b uzzer output stops. bzen functions as a status bit. it retains 1 while a one-shot b uzzer signal is being output and re v erts to 0 upon completion of the output. writing 0 to bzen while a one-shot b uzzer signal is being output stops the output immediately . writing 1 to bzen ag ain before a one- shot b uzzer output is f inished, a ne w one-shot output be gins from that point. en v elope mode w r i t i n g 1 t o b z e n s t a r t s b u z z e r o u t p u t i n e n v e l o p e m o d e . t h e d u t y r a t i o i s s e t t o l e v e l 1 ( m a x i m u m ) at the be ginning of the output and is stepped do wn e v ery attenuation time selected. when attenuated do wn to le v el 8 (minimum), the b uzzer output stops. bzen functions as a status bit. it retains 1 while a b uzzer signal is being output and re v erts to 0 upon completion of the output. writing 0 to bzen while a b uzzer signal is being outpu t stops the output immediately . writing 1 to bzen ag ain before a b uzzer output is f inished, the duty ratio returns to the maximum le v el and a ne w en v elope output be gins from that point.
18 sound genera t or (snd) s1c17651 t echnical m anual seiko epson corporation 18-7 buzzer frequency control register (snd_bzfq) register name ad dress bit name function setting init. r/w remarks buzzer frequency control register (snd_bzfq) 0x5181 (8 bits) d7C3 C reser v ed C C C 0 when being read. d2C0 bzfq[2:0] buzz er frequency select bzfq[2:0] f requency 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 1170.3 hz 1365.3 hz 1638.4 hz 2048.0 hz 2340.6 hz 2730.7 hz 3276.8 hz 4096.0 hz d[7:3] reserved d[2:0] bzfq[2:0]: buzzer frequency select bits selects a b uzzer signal frequenc y . 6.4 buzz er f requency selections t ab le 18. bzfq[2:0] buzz er frequenc y (hz) 0x7 1170.3 0x6 1365.3 0x5 1638.4 0x4 2048.0 0x3 2340.6 0x2 2730.7 0x1 3276.8 0x0 4096.0 (def ault: 0x0) buzzer duty ratio control register (snd_bzdt) register name ad dress bit name function setting init. r/w remarks buzzer duty ratio control register (snd_bzdt) 0x5182 (8 bits) d7C3 C reser v ed C C C 0 when being read. d2C0 bzdt[2:0] buzz er duty r atio select bzdt[2:0] duty (v olume) 0x0 r/w 0x7 : 0x0 le v el 8 (min.) : le v el 1 (max.) d[7:3] reserved d[2:0] bzdt[2:0]: buzzer duty ratio select bits selects a duty ratio that determines the b uzzer v olume le v el. 6.5 v olume le v el settings t ab le 18. v olume le vel bzdt[2:0] duty ratio b y b uzz er frequenc y (hz) 4096.0 3276.8 2730.7 2340.6 2048.0 1638.4 1365.3 1170.3 le v el 1 (max.) 0x0 8/16 8/20 12/24 12/28 le v el 2 0x1 7/16 7/20 11/24 11/28 le v el 3 0x2 6/16 6/20 10/24 10/28 le v el 4 0x3 5/16 5/20 9/24 9/28 le v el 5 0x4 4/16 4/20 8/24 8/28 le v el 6 0x5 3/16 3/20 7/24 7/28 le v el 7 0x6 2/16 2/20 6/24 6/28 le v el 8 (min.) 0x7 1/16 1/20 5/24 5/28 (def ault: 0x0) setting bzdt[2:0] to 0x0 turns the v olume up to maxi mum le v el; setting it to 0x7 turns the v olume do wn to minimum le v el. note: b z d t [2:0] i s i n e f f e c t i v e i n e n v e l o p e m o d e , a s t h e d u t y r a t i o i s a u t o m a t i c a l l y c o n t r o l l e d b y t h e hardw are .
19 suppl y v ol t a ge detection circuit (svd) s1c17651 t echnical m anual seiko epson corporation 19-1 supply v oltage detection cir cuit 19 (svd) svd module over vie w 19.1 t h e s 1 c 1 7 6 5 1 i n c l u d e s a n s v d ( s u p p l y v o l t a g e d e t e c t i o n ) c i r c u i t t o m o n i t o r t h e p o w e r v o l t a g e s u p p l i e d t o t h e v d d pin. it can be used to check whether the po wer supply v oltage drops belo w the detection le v el set with softw are or not. the follo wing sho ws the features of the svd module: ? po wer supply v oltage to be detected: v dd ? detec tion v oltage le v els: 13 le v els (2.0 v to 3.2 v) figure 19.1.1 sho ws the svd conf iguration. v dd internal data bus voltage comparator comparison voltage setting circuit detection result svddt svd svden svdc[4:0] 1.1 svd configur ation figure 19. comparison v olta g e setting 19.2 the svd circuit compares the po wer supply v oltage (v dd ) ag ainst the comparison v oltage set by softw are and out- puts results indicating whether the po wer supply v oltage e xceeds this comparison v oltage. the comparison v oltage can be selected from among the 17 le v els listed in t able 19.2.1 with the svdc[4:0]/svd_cmp re gister . 2.1 compar i son v oltage settings t ab le 19. svdc[4:0] comparison v olta g e svdc[4:0] comparison v olta g e 0x1f reser v ed 0xf 2.10 v 0x1e 0x e 2.00 v 0x1d 0xd reser v ed 0x1c 0xc 0x1b 0xb 0x1a 3.20 v 0xa 0x19 3.10 v 0x9 0x18 3.00 v 0x8 0x17 2.90 v 0x7 0x16 2.80 v 0x6 0x15 2.70 v 0x5 0x14 2.60 v 0x4 0x13 2.50 v 0x3 0x12 2.40 v 0x2 0x11 2.30 v 0x1 0x10 2.20 v 0x0 (def ault: 0x0) note: the compar ison v oltage is eff ectiv e only when it is set within the oper ating v oltage r ange . if the compar ison v oltage set is out of the oper ating v oltage r ange , no correct detection results will be obtained.
19 suppl y v ol t a ge detection circuit (svd) 19-2 seiko epson corporation s1c17651 t echnical m anual svd contr ol 19.3 po wer supply v oltage detection using the svd circuit is initiated by writing 1 to svden/svd_en re gister . af- ter that, the supply v oltage detection results can be read out from svddt/svd_rsl t re gister . by writing 0 to svden, the svd circuit sets the detection result at that point to svddt and stops detection. the detection results and svddt readings are as follo ws. ? when po wer suppl y v oltage (v dd ) comparison v oltage: svddt = 0 ? when po wer supply v oltage (v dd ) < comparison v oltage: svddt = 1 notes: s a n s v d c i r c u i t - e n a b l e r e s p o n s e t i m e i s r e q u i r e d t o o b t a i n s t a b l e d e t e c t i o n r e s u l t s a f t e r svden is altered from 0 to 1. also when svdc[4:0] is altered, an svd circuit response time is required to obtain stab le detection results . w ait until the response time has elapsed bef ore r e a d i n g s v d d t . a l s o w h e n r e a d i n g t h e d e t e c t i o n r e s u l t s a f t e r s t o p p i n g t h e s v d c i r c u i t , svden should be set to 0 after the response time has elapsed. f or these response times , see electr ical char acter istics . s oper ating the svd circuit increases current consumption. if po w er supply v oltage detection is not required, stop svd oper ations b y setting svden to 0. contr ol register details 19.4 4.1 list of svd registers t ab le 19. ad dress register name function 0x5100 svd_en svd enab le register enab les/disab les the svd oper ation. 0x5101 svd_cmp svd compar ison v oltage register sets the compar ison v oltage . 0x5102 svd_rsl t svd detection result register v oltage detection results the svd module re gisters are described in detail belo w . note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. svd enable register (svd_en) register name ad dress bit name function setting init. r/w remarks svd enable register (svd_en) 0x5100 (8 bits) d7C1 C reser v ed C C C 0 when being read. d0 svden svd enab le 1 enab le 0 disab le 0 r/w d[7:1] reserved d0 svden: svd enable bit enables or disables svd operations. 1 (r/w): enabled 0 (r/w): disabled (def ault) setting svden to 1 initiates po wer supply v oltage detection; setting to 0 stops detection after loading the detection results to svddt/svd_rsl t re gister . notes: s a n s v d c i r c u i t - e n a b l e r e s p o n s e t i m e i s r e q u i r e d t o o b t a i n s t a b l e d e t e c t i o n r e s u l t s a f t e r svden is altered from 0 to 1. also when svdc[4:0] is altered, an svd circuit response time is required to obtain stab le detection results . w ait until the response time has elapsed b e f o r e r e a d i n g s v d d t . a l s o w h e n r e a d i n g t h e d e t e c t i o n r e s u l t s a f t e r s t o p p i n g t h e s v d circuit, svden should be set to 0 after the response time has elapsed. f or these response times , see electr ical char acter isti cs . s oper ating the svd circuit increases current consumption. if po w er supply v oltage detection is not required, stop svd oper ations b y setting svden to 0.
19 suppl y v ol t a ge detection circuit (svd) s1c17651 t echnical m anual seiko epson corporation 19-3 svd comparison voltage register (svd_cmp) register name ad dress bit name function setting init. r/w remarks svd comparison voltage register (svd_cmp) 0x5101 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4C0 svdc[4:0] svd compar ison v oltage select svdc[4:0] v oltage 0x0 r/w 0x1fC0x1b 0x1a 0x19 0x18 0x17 0x16 0x15 0x14 0x13 0x12 0x11 0x10 0xf 0x e 0xdC0x0 reser v ed 3.20 v 3.10 v 3.00 v 2.90 v 2.80 v 2.70 v 2.60 v 2.50 v 2.40 v 2.30 v 2.20 v 2.10 v 2.00 v reser v ed d[7:5] reserved d[4:0] svdc[4:0]: svd comparison voltage select bits selects one of 13 comparison v oltages for detecting v oltage drops. 4.2 compar ison v oltage settings t ab le 19. svdc[4:0] comparison v olta g e svdc[4:0] comparison v olta g e 0x1f reser v ed 0xf 2.10 v 0x1e 0x e 2.00 v 0x1d 0xd reser v ed 0x1c 0xc 0x1b 0xb 0x1a 3.20 v 0xa 0x19 3.10 v 0x9 0x18 3.00 v 0x8 0x17 2.90 v 0x7 0x16 2.80 v 0x6 0x15 2.70 v 0x5 0x14 2.60 v 0x4 0x13 2.50 v 0x3 0x12 2.40 v 0x2 0x11 2.30 v 0x1 0x10 2.20 v 0x0 (def ault: 0x0) t h e s v d c i r c u i t c o m p a r e s t h e p o w e r s u p p l y v o l t a g e ( v d d ) a g a i n s t t h e c o m p a r i s o n v o l t a g e s e t b y svdc[4:0], and outputs result s indicating whether the po wer supply v oltage e xceeds this comparison v oltage. note: the comparison voltage is effective only when it is set within the operating voltage range. if the comparison voltage set is out of the operating voltage range, no correct detection results will be obtained.
19 suppl y v ol t a ge detection circuit (svd) 19-4 seiko epson corporation s1c17651 t echnical m anual svd detection result register (svd_rslt) register name ad dress bit name function setting init. r/w remarks svd detection result register (svd_rslt) 0x5102 (8 bits) d7C1 C reser v ed C C C 0 when being read. d0 svddt svd detection result 1 lo w 0 nor mal r d[7:1] reserved d0 svddt: svd detection result bit indicates the po wer supply v oltage detection results. 1 (r): po wer supply v oltage (v dd ) < comparison v oltage 0 (r): po wer supply v oltage (v dd ) comparison v oltage the svd circuit compares the po wer supply v oltage (v dd ) ag ainst the v oltage set in svdc[4:0]/svd_ c m p r e g i s t e r w h i l e s v d e n / s v d _ e n r e g i s t e r = 1. t h e c u r r e n t p o w e r s u p p l y v o l t a g e s t a t u s c a n b e monitored by reading svddt . also the detection result is set to svddt by writing 0 to svden, so the po wer supply v oltage status can be check ed by reading svddt after that.
20 on-chip deb ugger (dbg) s1c17651 t echnical m anual seiko epson corporation 20-1 on-chip deb ugger (dbg) 20 resour ce requirements and deb ug ging t ools 20.1 deb ug ging w ork area deb ugging requires a 64-byte deb ugging w ork area. f or more information on the w ork area location, see the memory map, bus control chapter . the start address for this deb ugging w ork area can be read from the dbram re gister (0xf f f f90). deb ug ging tools d e b u g g i n g i n v o l v e s c o n n e c t i n g i c d m i n i ( s 5 u 1 c 1 7 0 0 1 h ) t o t h e s 1 c 1 7 6 5 1 d e b u g p i n s a n d i n p u t t i n g t h e d e b u g instruction from the deb ugger on the personal computer . the follo wing tools are required: ? s1c17 f amily in-circuit deb ugger icdmini (s5u1c17001h) ? s1c17 f amily c compiler package (e.g., s5u1c17001c) deb ug pins the follo wing deb ug pins are used to connect icdmini (s5u1c17001h). 1.1 list of deb ug pins t ab le 20. pin name i/o qty function dclk o 1 on-chip deb ugger cloc k output pin outputs a cloc k to the icdmini (s5u1c17001h). dsio i/o 1 on-chip deb ugger data input/output pin used to input/output deb ugging data and input the break signal. dst2 o 1 on-chip deb ugger status signal output pin outputs the processor status dur ing deb ugging. the on-chip deb ugger input/output pins (dclk, dst2, dsio) are shared with i/o ports and are initially set as the deb ug pins. if the deb ugging function is not used, these pins can be switched using the port function select bits to enable use as general-purpose i/o port pins. f or detailed information on pin function switching, see the i/o ports (p) chapter . deb ug break operation status 20.2 the s1c17 core enters deb ug mode when the brk instruction is e x ecuted or a deb ug interrupt is gene rated by a break signal (lo w) input to the dsio pin. this state persists until the retd instruction is e x ecuted. during this time, hardw are interrupts and nmis are disabled. the def ault setting halts peripheral circuit operations. this setting can be modif ied e v en when deb ugging is under - w ay . the peripheral circuits that operate with pclk will continue running in deb ug mode by setting dbr un1/misc_ d mode1 re gister to 1. setting dbr un1 to 0 (def ault) will stop these peripheral circuits in deb ug mode. the peripheral circuits that operate with a clock other than pclk will continue running in deb ug mode by setting dbr un2/misc_dmode2 re gister to 1. setting dbr un2 to 0 (def ault) will stop these peripheral circuits in de- b ug mode. some peripheral circuits, such as spi and t16a2, that run with an e xter nal input clock will not stop operating e v en if the s1c17 core enters deb ug mode. the lcd dri v er and r tc continue the operating status at occurrence of the deb ug interrupt.
20 on-chip deb ugger (dbg) 20-2 seiko epson corporation s1c17651 t echnical m anual ad ditional deb ug ging function 20.3 the s1c17651 e xpands the follo wing on-chip deb ugging functions of the s1c17 core. branc hing destination in deb ug mode when a deb ug interrupt is generated, the s1c17 core enters deb ug mode and branches to the deb ug processing routine. in this process, the s1c17 core is designed to branch to address 0xf f fc00. in addition to this branching destination, the s1c17651 a lso allo ws designation of address 0x0 (be ginning address of the internal ram) as the branching destination when deb ug mode is acti v ated. the branching destination address is selected using db adr/misc_iramsz re gister . when the db adr is set to 0 (def ault), the branching destination is set to 0xf f fc00. when it is set to 1, the branching destination is set to 0x0. ad ding instruction breaks the s1c17 co re supports tw o instruction breaks (hardw are pc breaks). the s1c17651 increased this number to f i v e, adding the control bits and re gisters gi v en belo w . ? ibe2/dcr re gister: enables instruction breaks #2. ? ibe3/dcr re gister: enables instruction breaks #3. ? ibe4/dcr re gister: enables instruction breaks #4. ? ib ar2[23:0]/ib ar2 re gister: set instruction break address #2. ? ib ar3[23:0]/ib ar3 re gister : set instruction break address #3. ? ib ar4[23:0]/ib ar4 re gister: set instruction break address #4. note that the deb ugger included in the s5u1c17001c (v er . 1.2.1) or later is required to use f i v e hardw are pc breaks. contr ol register details 20.4 4.1 list of deb ug registers t ab le 20. ad dress register name function 0x4020 misc_dmode1 deb ug mode control register 1 enab les per ipher al oper ations in deb ug mode (pclk). 0x5322 misc_dmode2 deb ug mode control register 2 enab les per ipher al oper ations in deb ug mode (e xcept pclk). 0x5326 misc_iramsz iram siz e select register selects the iram siz e . 0xffff90 dbram deb ug ram base register indicates the deb ug ram base address . 0xffff a0 dcr deb ug control register c ontrols deb ugging. 0xffffb8 ibar2 instr uction break address register 2 sets instr uction break address #2. 0xffffbc ibar3 instr uction break address register 3 sets instr uction break address #3. 0xffffd0 ibar4 instr uction break address register 4 sets instr uction break address #4. the deb ug re gisters are described in detail belo w . notes: ? w h e n d a t a i s w r i t t e n t o t h e r e g i s t e r s , t h e r e s e r v e d b i t s m u s t a l w a y s b e w r i t t e n a s 0 a n d n o t 1 . ? f or deb ug registers not descr ibed here , ref er to the s1c17 core man ual. debug mode control register 1 (misc_dmode1) register name ad dress bit name function setting init. r/w remarks debug mode control register 1 (misc_dmode1) 0x4020 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1 dbrun1 run/stop select in deb ug mode 1 run 0 stop 0 r/w d0 C reser v ed C C C 0 when being read. d[7:2] reserved d1 dbrun1: run/stop select bit in debug mode selects the operating status of the peripheral circuits that operate with pclk in deb ug mode. 1 (r/w): run 0 (r/w): stop (def ault)
20 on-chip deb ugger (dbg) s1c17651 t echnical m anual seiko epson corporation 20-3 setting dbr un1 to 1 enables the peripheral circuits that operate with pclk to run e v en in deb ug mode. setting it to 0 will stop them when the s1c17 core enters deb ug mode. set dbr un1 to 1 to maintain running status for these peripheral circuits in deb ug mode. d0 reserved debug mode control register 2 (misc_dmode2) register name ad dress bit name function setting init. r/w remarks debug mode control register 2 (misc_dmode2) 0x5322 (16 bits) d15C1 C reser v ed C C C 0 when being read. d0 dbrun2 run/stop select in deb ug mode (e xcept pclk per ipher al circuits) 1 run 0 stop 0 r/w d[15:1] reserved d0 dbrun2: run/stop select bit in debug mode (except pclk peripheral circuits) selects the operating status of the peripheral circuits that operate with a clock other than pclk in deb ug mode. 1 (r/w): run 0 (r/w): stop (def ault) s e t t i n g d b r u n2 t o 1 e n a b l e s t h e p e r i p h e r a l c i r c u i t s t h a t o p e r a t e w i t h a c l o c k o t h e r t h a n p c l k t o run e v en in deb ug mode. setting it to 0 will stop them when the s1c17 core enters deb ug mode. set dbr un2 to 1 to maintain running status for these peripheral circuits in deb ug mode. s ome peripheral circuits, such as spi and t16a2, that run with an e xternal input clock will not stop op- erating e v en if the s1c17 core enters deb ug mode. the lcd dri v er and r tc continue the operating status at occurrence of the deb ug interr upt. iram size select register (misc_iramsz) register name ad dress bit name function setting init. r/w remarks iram size register (misc_iramsz) 0x5326 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 dbadr deb ug base address select 1 0x0 0 0xfffc00 0 r/w d7 C reser v ed C C C 0 when being read. d6C4 iramactsz [2:0] iram actual siz e 0x3 (= 2kb) 0x3 r d3 C reser v ed C C C 0 when being read. d2C0 iramsz[2:0] iram siz e select iramsz[2:0] siz e 0x3 r/w 0x5 0x4 0x3 other 512b 1kb 2kb reser v ed d[15:9] reserved d8 dbadr: debug base address select bit selects the branching destination address when a deb ug interrupt occurs. 1(r/w): 0x0 0(r/w): 0xf f fc00 (def ault) d7 reserved d[6:4] iramactsz[2:0]: iram actual size bits indicates the actual internal ram size embedded. (def ault: 0x3) d3 reserved d[2:0] iramsz[2:0]: iram size select bits selects the size of the internal ram to be used.
20 on-chip deb ugger (dbg) 20-4 seiko epson corporation s1c17651 t echnical m anual 4.2 inter nal ram siz e selection t ab le 20. iramsz[2:0] internal ram siz e 0x5 512b 0x4 1kb 0x3 2kb other reser v ed (def ault: 0x3) note: the misc_iramsz register is wr ite-protected. t o alter this register settings , y ou m ust o v err ide this wr ite-protection b y wr iting 0x96 to the misc_pr o t register . nor mally , the misc_pr o t reg- ister should be set to a v alue other than 0x96, e xcept when alter ing the misc_iramsz register . unnecessar y re wr iting of the misc_irams z register ma y result in system malfunctions . debug ram base register (dbram) register name ad dress bit name function setting init. r/w remarks debug ram base register (dbram) 0xffff90 (32 bits) d31C24 C un used (fix ed at 0) 0x0 0x0 r d23C0 dbram[23:0] deb ug ram base address 0x7c0 0x7c0 r d[31:24] not used (fixed at 0) d[23:0] dbram[23:0]: debug ram base address bits read-only re gister containing the be ginning address of the deb ugging w ork area (64 bytes). debug control register (dcr) register name ad dress bit name function setting init. r/w remarks debug control register (dcr) 0xffffa0 (8 bits) d7 ibe4 instr uction break #4 enab le 1 enab le 0 disab le 0 r/w d6 ibe3 instr uction break #3 enab le 1 enab le 0 disab le 0 r/w d5 ibe2 instr uction break #2 enab le 1 enab le 0 disab le 0 r/w d4 dr deb ug request flag 1 occurred 0 n o t o c c u r r e d 0 r/w reset b y wr iting 1. d3 ibe1 instr uction break #1 enab le 1 enab le 0 disab le 0 r/w d2 ibe0 instr uction break #0 enab le 1 enab le 0 disab le 0 r/w d1 se single step enab le 1 enab le 0 disab le 0 r/w d0 dm deb ug mode 1 d e b u g m o d e 0 user mode 0 r d7 ibe4: instruction break #4 enable bit enables or disables instruction break #4. 1 (r/w): enabled 0 (r/w): disabled (def ault) if this bit is set to 1, the instruction fetch address and the v alue set in the ib ar4 re gister are compared. if the y match, an instruction break is generated. if this bit is set to 0, no comparison is performed. d6 ibe3: instruction break #3 enable bit enables or disables instruction break #3. 1 (r/w): enabled 0 (r/w): disabled (def ault) if this bit is set to 1, the instruction fetch address and the v alue set in the ib ar3 re gister are compared. if the y match, an instruction break is generated. if this bit is set to 0, no comparison is performed. d5 ibe2: instruction break #2 enable bit enables or disables instruction break #2. 1 (r/w): enabled 0 (r/w): disabled (def ault) if this bit is set to 1, the instruction fetch address and the v alue set in the ib ar2 re gister are compared. if the y match, an instruction break is generated. if this bit is set to 0, no comparison is performed.
20 on-chip deb ugger (dbg) s1c17651 t echnical m anual seiko epson corporation 20-5 d4 dr: debug request flag bit indicates the presence or absence of an e xternal deb ug request. 1 (r): request generated 0 (r): request not generated (def ault) 1 (w): flag is reset 0 (w): ignored this flag is cleared (reset to 0) when 1 is written. it must be cleared before the deb ug processing routine is terminated by the retd instruction. d3 ibe1: instruction break #1 enable bit enables or disables instruction break #1. 1 (r/w): enabled 0 (r/w): disabled (def ault) if this bit is set to 1, the instruction fetch address and the v alue set in the ib ar1 re gister are compared. if the y match, an instruction break is generated. if this bit is set to 0, no comparison is performed. d2 ibe0: instruction break #0 enable bit enables or disables instruction break #0. 1 (r/w): enabled 0 (r/w): disabled (def ault) if this bit is set to 1, the instruction fetch address and the v alue set in the ib ar0 re gister are compared. if the y match, an instruction break is generated. if this bit is set to 0, no comparison is performed. d1 se: single step enable bit enables or disables single-step operations. 1 (r/w): enabled 0 (r/w): disabled (def ault) d0 dm: debug mode bit indicates the processor operating mode (deb ug mode or user mode). 1 (r): deb ug mode 0 (r): user mode (def ault) instruction break address register 2 (ibar2) register name ad dress bit name function setting init. r/w remarks instruction break address register 2 (ibar2) 0xffffb8 (32 bits) d31C24 C reser v ed C C C 0 when being read. d23C0 ibar2[23:0] instr uction break address #2 ibar223 = msb ibar20 = lsb 0x0 to 0xffffff 0x0 r/w d[31:24] reserved d[23:0] ibar2[23:0]: instruction break address #2 bits sets instruction break address #2. (def ault: 0x000000) instruction break address register 3 (ibar3) register name ad dress bit name function setting init. r/w remarks instruction break address register 3 (ibar3) 0xffffbc (32 bits) d31C24 C reser v ed C C C 0 when being read. d23C0 ibar3[23:0] instr uction break address #3 ibar323 = msb ibar30 = lsb 0x0 to 0xffffff 0x0 r/w d[31:24] reserved d[23:0] ibar3[23:0]: instruction break address #3 bits sets instruction break address #3. (def ault: 0x000000)
20 on-chip deb ugger (dbg) 20-6 seiko epson corporation s1c17651 t echnical m anual instruction break address register 4 (ibar4) register name ad dress bit name function setting init. r/w remarks instruction break address register 4 (ibar4) 0xffffd0 (32 bits) d31C24 C reser v ed C C C 0 when being read. d23C0 ibar4[23:0] instr uction break address #4 ibar423 = msb ibar40 = lsb 0x0 to 0xffffff 0x0 r/w d[31:24] reserved d[23:0] ibar4[23:0]: instruction break address #4 bits sets instruction break address #4. (def ault: 0x000000)
21 mul tiplier/divider (copr o) s1c17651 t echnical m anual seiko epson corporation 21-1 multiplier/di vider (copr o) 21 over vie w 21.1 the s1c17651 has an embedded coprocessor that pro vides multiplier/di vider functions. the follo wing sho ws the features of the multiplier/di vider: ? multiplication: supports signed/unsigned multiplications. (16 bits 16 bits = 32 bits) can be e x ecuted in 1 c ycle. ? multiplication and accumulation (ma c): supports signed ma c operations with o v erflo w detecti on function (16 bits 16 bits + 32 bits = 32 bits) can be e x ecuted in 1 c ycle. ? di vision: supports signed/unsigned di visions. (16 bits 16 bits = 16 bits with 16-bit residue) can be e x ecuted in 17 to 20 c ycles. s1c17 core ar ithmetic unit operation result register mode setting selector argument 2 argument 1 coprocessor output flag output operation result 1.1 multiplier/divider bloc k diag r am figure 21. operation mode and output mode 21.2 the multiplier/di vider operates according to the operation mode specif ied by the application program. as listed in t able 21.2.1, the multiplier/di vider supports nine operations. the multiplication, di vision and ma c results are 32-bit data, therefore, the s1c17 core cannot read them in one access c ycle. the output mod e is pro vided to specify the high-order 16 bits or lo w-order 16 bits of the operation results to be read from the multiplier/di vider . the operation and output modes can be specif ied with a 7-bit data by writing it to the mode setting re gister in the multiplier/di vider . use a ld.cw instruction for this writing. ld.cw %rd,%rs %rs[6:0] is written to the mode setting re gister . (%rd: not used) ld.cw %rd,imm7 imm7[6:0] is written to the mode setting re gister . (%rd: not used) 6 4 3 0 output mode setting v alue oper ation mode setting v alue 2.1 mode setting register figure 21.
21 mul tiplier/divider (copr o) 21-2 seiko epson corporation s1c17651 t echnical m anual 2.1 mode settings t ab le 21. setting v alue (d[6:4]) output mode setting v alue (d[3:0]) operation mode 0x0 16 low-order bits output mode t h e l o w - o r d e r 16- b i t s o f o p e r a t i o n r e s u l t s can be read as the coprocessor output. 0x0 initialize mode 0 clears the oper ation result register to 0x0. 0x1 16 high-order bits output mode t h e h i g h - o r d e r 16- b i t s o f o p e r a t i o n r e s u l t s can be read as the coprocessor output. 0x1 initialize mode 1 l o a d s t h e 16- b i t a u g e n d i n t o t h e l o w - o r d e r 16 bits of the oper ation result register . 0x2C0x7 reser v ed 0x2 initialize mode 2 l o a d s t h e 32- b i t a u g e n d i n t o t h e o p e r a t i o n result register . 0x3 operation result read mode outputs the data in the oper ation result reg- ister without computation. 0x4 unsigned multiplication mode p erf or ms unsigned m ultiplication. 0x5 signed multiplication mode p erf or ms signed m ultiplication. 0x6 reser v ed 0x7 signed mac mode p erf or ms signed ma c oper ation. 0x8 unsigned division mode p erf or ms unsigned division. 0x9 signed division mode p erf or ms signed division. 0xaC0xf reser v ed multiplication 21.3 the multiplication function performs a (32 bits) = b (16 b its) c (16 bits). t o perform a multiplication, set the operation mode to 0x4 (unsigned multiplication) or 0x5 (signed multiplication). then send the 16-bit multiplicand (b) and 16-bit multiplier (c) to the multiplier/di vider using a ld.ca instruc- tion. the one-half (16 bits according to the output mode) result (a[15:0] or a[31:16]) and the flag status will be returned to the cpu re gisters. another one-half should be read by setting the multiplier/di vider into operation result read mode. s1c17 core operation result register selector argument 2 argument 1 16 bits 32 bits coprocessor output (16 bits) flag output operation result 3.1 data p ath in multiplication mode figure 21.
21 mul tiplier/divider (copr o) s1c17651 t echnical m anual seiko epson corporation 21-3 3.1 oper ation in multiplication mode t ab le 21. m o d e s e t t i n g v alue instruction operations fla gs remarks 0x04 or 0x05 ld.ca %rd,%rs res[31:0] %rd %rs %rd res[15:0] psr (cvzn) 0b0000 t h e o p e r a t i o n r e s u l t r e g i s t e r k eeps the oper ation result until i t i s r e w r i t t e n b y o t h e r o p e r a - tion. (ext imm9) ld.ca %rd,imm7 res[31:0] %rd imm7/16 %rd res[15:0] 0x14 or 0x15 ld.ca %rd,%rs res[31:0] %rd %rs %rd res[31:16] (ext imm9) ld.ca %rd,imm7 res[31:0] %rd imm7/16 %rd res[31:16] res: oper ation result register example: ld.cw %r0,0x4 ; sets the modes (unsigned multiplication mode and 16 lo w-order bits output mode). ld.ca %r0,%r1 ; performs res = %r0 %r1 and loads the 16 lo w-order bits of the result to %r0. ld.cw %r0,0x13 ; sets the modes (operation result read mode and 16 high-order bits output mode). ld.ca %r1,%r0 ; loads the 16 high-order bits of the result to %r1. division 21.4 the di vision function performs b (16 bits) c (16 bits) = a (16 bits), residue d (16 bits). t o perfo rm a di vision, set the operation mode to 0x8 (unsigned di vision) or 0x9 (signed di vision). then send the 16-bit di vidend (b) and 16-bit di visor (c) to the multiplier/di vider using a ld.ca instruction. the quotient and the residue will be stored in the lo w-order 16 bits and the high-order 16 bits of the operation result re gister , respec- ti v ely . the 16-bit quotient or residue according to the output m ode specif ication and the flag status will be returned to the cpu re gisters. another 16-bit result should be read by setting the multiplier/di vider into operation result read mode. s1c17 core operation result register selector argument 2 argument 1 16 bits 16 bits coprocessor output (16 bits) flag output operation result 4.1 data p ath in division mode figure 21. 4.1 oper ation in division mode t ab le 21. m o d e s e t t i n g v alue instruction operations fla gs remarks 0x08 or 0x09 ld.ca %rd,%rs res[31:0] %rd %rs %rd res[15:0] (quotient) psr (cvzn) 0b0000 t h e o p e r a t i o n r e s u l t r e g i s t e r k eeps the oper ation result until i t i s r e w r i t t e n b y o t h e r o p e r a - tion. (ext imm9) ld.ca %rd,imm7 res[31:0] %rd imm7/16 %rd res[15:0] (quotient) 0x018 or 0x19 ld.ca %rd,%rs res[31:0] %rd %rs %rd res[31:16] (residue) (ext imm9) ld.ca %rd,imm7 res[31:0] %rd imm7/16 %rd res[31:16] (residue) res: o per ation result register
21 mul tiplier/divider (copr o) 21-4 seiko epson corporation s1c17651 t echnical m anual example: ld.cw %r0,0x8 ; sets the modes (unsigned di vision mode and 16 lo w-order bits output mode). ld.ca %r0,%r1 ; performs res = %r0 %r1 and loads the 16 lo w-order bits of the result (quotient) to %r0. ld.cw %r0,0x13 ; sets the modes (operation result read mode and 16 high-order bits output mode). ld.ca %r1,%r0 ; loads the 16 high-order bits of the result (residue) to %r1. ma c 21.5 the ma c (multiplication and accumulation) function performs a (32 bits) = b (16 bits) c (16 bits) + a (32 bits). before performing a ma c operation, the initial v alue (a) must be set to the operation result re gister . t o clear the operation result re gister (a = 0), just set the operation mode to 0x0. it is not necessary to send 0x0 to the multiplier/di vider with another instruction. t o load a 16-bit v alue or a 32-bit v alue to the operation result re gister , se t the operation mode to 0x1 (16 bits) or 0x2 (32 bits), respecti v ely . then send the initial v alue to the multiplier/di vider using a ld.cf instruction. s1c17 core operation result register selector argument 2 argument 1 16 bits 32 bits coprocessor output (16 bits) flag output 5.1 data p ath in initializ e mode figure 21. 5.1 initializing the oper ation result register t ab le 21. m o d e s e t t i n g v alue instruction operations remarks 0x0 C res[31:0] 0x0 setting the oper ating mode e x ecutes the initialization without sending data. 0x1 ld.cf %rd,%rs res[31:16] 0x0 res[15:0] %rs (ext imm9) ld.cf %rd,imm7 res[31:16] 0x0 res[15:0] imm7/16 0x2 ld.cf %rd,%rs res[31:16] %rd res[15:0] %rs (ext imm9) ld.cf %rd,imm7 res[31:16] %rd res[15:0] imm7/16 res: oper ation result register t o perform a ma c operation, set the operation mode to 0x7 (signed ma c). then send t he 16-bit multiplicand (b) and 16-bit multiplier (c) to the multiplier/di vider using a ld.ca instruction. the one-half (16 bits according to the output mode) result (a[15:0] or a[31:16]) and the flag status will be returned to the cpu re gisters. another one-half should be read by setting the multiplier/di vider into operation result read mode. the o v erflo w (v) flag in the psr may be set to 1 according to the result. other flags are set to 0. when repeating the ma c operation without operation result read mode inserted, send multiplicand and multiplier data for number of required times. in this case it is not necessary to set the ma c mode e v ery time.
21 mul tiplier/divider (copr o) s1c17651 t echnical m anual seiko epson corporation 21-5 s1c17 core operation result register selector argument 2 argument 1 16 bits 32 bits 32 bits coprocessor output (16 bits) flag output operation result 5.2 data p ath in ma c mode figure 21. 5.2 oper ation in ma c mode t ab le 21. m o d e s e t t i n g v alue instruction operations fla gs remarks 0x07 ld.ca %rd,%rs res[31:0] %rd %rs + res[31:0] %rd res[15:0] psr (cvzn) 0b0100 if an o v erflo w has oc- curred otherwise psr (cvzn) 0b0000 t h e o p e r a t i o n r e s u l t r e g i s t e r k e e p s t h e o p e r a t i o n r e s u l t u n - t i l i t i s r e w r i t t e n b y other oper ation. (ext imm9) ld.ca %rd,imm7 r e s [ 3 1 : 0 ] % r d imm7/16 + r e s [ 3 1 : 0 ] %rd res[15:0] 0x17 ld.ca %rd,%rs res[31:0] %rd %rs + res[31:0] %rd res[31:16] (ext imm9) ld.ca %rd,imm7 r e s [ 3 1 : 0 ] % r d imm7/16 + r e s [ 3 1 : 0 ] %rd res[31:16] res: oper ation result register example: ld.cw %r0,0x7 ; sets the modes (signed ma c mode and 16 lo w-order bits output mode). ld.ca %r0,%r1 ; performs res = %r0 %r1 + res and loads the 16 lo w-order bits of the result to %r0. ld.cw %r0,0x13 ; sets the modes (operation result read mode and 16 high-order bits output mode). ld.ca %r1,%r0 ; loads the 16 high-order bits of the result to %r1. conditions to set the o verflo w (v) fla g an o v erflo w occurs in a ma c operation and the o v erflo w (v) flag is set to 1 when the signs of the multiplica- tion result, operation result re gister v alue, and multiplication & accumulation result match the follo wing condi- tions: 5.3 conditions to set the ov erflo w (v) flag t ab le 21. mode setting v alue sign of m ultiplication result sign of operation result register v alue sign of m ultiplication & ac- cum ulation result 0x07 0 (positiv e) 0 (positiv e) 1 (negativ e) 0x07 1 (negativ e) 1 (negativ e) 0 (positiv e) an o v erflo w occurs when a ma c operation performs addition of positi v e v alues and a ne g ati v e v alue results, or it performs addition of ne g ati v e v alues and a positi v e v alue results. the copr ocessor holds the operation result when the o v erflo w (v) flag is cleared. conditions to c lear the o verflo w (v) fla g the o v erflo w (v) flag that has been set will be cleared when an o v erflo w has not been occurred during e x ecu- tion of the ld.ca instruction for ma c operation or when the ld.ca or ld.cf instruction is e x ecuted in an operation mode other than operation result read mode.
21 mul tiplier/divider (copr o) 21-6 seiko epson corporation s1c17651 t echnical m anual reading results 21.6 t h e ld.ca i n s t r u c t i o n c a n n o t l o a d a 3 2 - b i t o p e r a t i o n r e s u l t t o a c p u r e g i s t e r , s o a m u l t i p l i c a t i o n o r m a c o p e r a - tion returns the one-half (16 bits according to the output mode) result (a[15:0] or a[31:16]) and the flag status to the cpu re gisters. another one-half should be read by setting the multiplier/di vider into operation result read mode. the operation result re gister k eep s the loaded operation result until it is re written by other operation. s1c17 core operation result register selector argument 2 argument 1 coprocessor output (16 bits) flag output 6.1 data p ath in oper ation result read mode figure 21. 6.1 oper ation in oper ation result read mode t ab le 21. m o d e s e t t i n g v alue instruction operations fla gs remarks 0x03 ld.ca %rd,%rs %rd res[15:0] psr (cvzn) 0b0000 t h i s o p e r a t i o n m o d e d o e s n o t aff ect the oper ation result reg- ister . ld.ca %rd,imm7 %rd res[15:0] 0x13 ld.ca %rd,%rs %rd res[31:16] ld.ca %rd,imm7 %rd res[31:16] res: oper ation result register
22 electrical chara cteristics s1c17651 t echnical m anual seiko epson corporation 22-1 electrical characteristics 22 absolute maxim um ratings 22.1 (v ss = 0v) item symbol condition rated v alue unit p o w er supply v oltage v dd -0.3 to 4.0 v flash prog r amming v oltage v pp 8 v lcd po w er supply v oltage v c3 -0.3 to 4.0 v input v oltage v i -0.3 to v dd + 0.5 v output v oltage v o -0.3 to v dd + 0.5 v high le v el output current i oh 1 pin -10 ma t otal of all pins -20 ma lo w le v el output current i ol 1 pin 10 ma t otal of all pins 20 ma stor age temper ature tstg -65 to 125 c solder ing temper ature/time tsol 260c , 10 secon ds (lead section) C recommended operating conditions 22.2 (v ss = 0v) item symbol condition min. t yp. max. unit oper ating po w er supply v oltage v dd nor mal oper ation mode 2.0 3.6 v flash prog r amming v oltage v pp p 6.8 7.0 7.2 v flash prog r amming temper ature t pp 10 40 c flash er asing v oltage v pp e 7.3 7.5 7.7 v oper ating frequency f osc3a cr ystal/cer amic oscillation 0.2 8.2 mhz f osc1a cr ystal oscillation 32.768 khz oper ating temper ature t a dur ing nor mal oper ation (flash read only) -40 85 c dur ing flash prog r amming a nd er asing 10 40 c capacitor betw een v ss and v d1 c 1 0.1 f capacitor betw een v ss and v osc c 2 0.1 f capacitor betw een v ss and v c1 *1 c 3 0.1 f capacitor betw een v ss and v c2 *1 c 4 0.1 f capacitor betw een v ss and v c3 *1 c 5 0.1 f capacitor betw een ca and cb *1 c 6 0.1 f *1 the capacitors are not required when lcd dr iv er is not used. in this case , lea v e the v c1 to v c3 , ca, and cb pins open.
22 electrical chara cteristics 22-2 seiko epson corporation s1c17651 t echnical m anual current consumption 22.3 unless otherwise specified: v dd = 2.0 to 3.6v , v ss = 0v , t a = 25c , pcken[1:0] = 0x3 (on), rd w ait[1:0] = 0x0 (no w ait), osc1a = no theoretical regulation correction, cclkgr[1:0] = 0x0 (gear r atio 1/1), r tcr un = 0 (off), hvld = 0, lcd = off item symbol condition min. t yp. max. unit current consumption in sleep mode i slp osc1a = off , osc1b = off , osc3b = off 90 160 na osc1a = 32khz, osc3b = off , osc3a = off , r tcr un = 1 (on) 170 220 na osc1b = 32khz, osc3b = off , osc3a = off , r tcr un = 1 (on) 770 1000 na current consumption in hal t mode i hal t1 osc1a = 32khz, osc3b = off , osc3a = off , pcken[1:0] = 0x0 (off) 0.42 0.55 a osc1a = 32khz, osc3b = off , osc3a = off , pcke n[1:0] = 0x0 (off), r tcr un = 1 (on) 0.42 0.55 a osc1a = 32khz, osc3b = off , osc3a = off 0.88 1.10 a osc1b = 32khz, osc3b = off , osc3a = off , pcken[1:0] = 0x0 (off) 0.95 1.20 a i hal t2 osc1a = 32khz, osc3b = off , osc3a = on (1mhz cer amic) 67 100 a osc1a = 32khz, osc3b = off , osc3a = on (4mhz cer amic) 130 180 a i hal t3 osc1a = 32khz, osc3b = on ( 500khz), osc3a = off 68 120 a osc1a = 32khz, osc3b = on ( 1mhz), osc3a = off 87 150 a osc1a = 32khz, osc3b = on ( 2mhz), osc3a = off 130 200 a current consumption dur ing e x ecution *1 i exe1 osc1a = 32khz, osc3b = off , osc3a = off , cpu = osc1a 10 13 a osc1a = 32khz, osc3b = off , osc3a = off , cpu = osc1a, cclkgr[1:0] = 0x2 ( gear r atio 1/4) 4.0 5.5 a i exe2 osc1a = 32khz, osc3b = off , osc3a = on (1mhz cer amic), cpu = osc3a 350 480 a osc1a = 32khz, osc3b = off , osc3a = on (1mhz cer amic), cpu = osc3a , cclkgr[1:0] = 0x2 ( gear r atio 1/4) 200 280 a osc1a = 32khz, osc3b = off , osc3a = on (4mhz cer amic), cpu = osc3a 1200 1800 a osc1a = 32khz, osc3b = off , osc3a = on (4mhz cer amic), cpu = osc3a, cclkgr[1:0] = 0x2 ( gear r atio 1/4) 530 750 a i exe3 osc1a = 32khz, osc3b = on (500khz), osc3a = off , cpu = osc3b 230 310 a osc1a = 32khz, osc3b = on (1mhz), osc3a = off , cpu = osc3b 370 510 a osc1a = 32khz, osc3b = on (2mhz ), osc3a = off , cpu = osc3b 650 900 a osc1a = 32khz, osc3b = on (2mhz), osc3a = off , cpu = osc3b , cclkgr[1:0] = 0x2 ( gear r atio 1/4) 320 450 a current consumption dur ing e x ecution in hea vy load protection mode *1 i exe1h osc1a = 32khz, osc3b = off , osc3a = off , cpu = osc1a, hvld = 1 21 27 a *1 the v alues of current consumption dur ing e x ecution w ere measured when a test prog r am consisting of 60.5% alu instr uct ions , 17% br anch instr uctions , 12% memor y read instr uctions , and 10.5% memor y wr ite instr uctions w as e x ecuted contin uously in the flash memor y .
22 electrical chara cteristics s1c17651 t echnical m anual seiko epson corporation 22-3 current consumption-temperature c haracteristic current consumption-temperature c haracteristic in sleep mode in hal t mode (osc1a operation) osc1a = off , osc1b = off , osc3b = off , osc3a = off , osc1a = 32.768khz cr ystal, osc3b = off , osc3a = off , t yp . v alue pcken[1:0] = 0x3, cclkgr[1:0] = 0x0, t yp . v alue -50 300 250 200 150 100 50 0 -25 02 55 07 5 100 ta [c] i slp [na] -50 1.0 0.8 0.6 0.4 0.2 0 -25 02 55 07 5 100 ta [c] i hal t1 [a] current consumption-temperature c haracteristic current consumption-temperature c haracteristic in hal t mode (osc1b operation) during e x ecution with osc1a + c loc k g ear osc1b = 32khz, osc3b = off , osc3a = off , osc1a = 32.768khz cr ystal, osc3b = off , osc3a = off , pcken[1:0] = 0x0, cclkgr[1:0] = 0x0, t yp . v alue pcken[1:0] = 0x3, t yp . v alue -50 1.5 1 0.5 0 -25 02 55 07 5 100 ta [c] i hal t1 [a] -50 12 10 8 6 4 2 0 -25 02 55 07 5 100 ta [c] i exe1 [a] 1/1 1/2 1/4 1/8 gear ratio current consumption-temperature c haracteristic current consumption-frequenc y c haracteristic during e x ecution with osc3a + c loc k g ear during e x ecution with osc3a osc3a = on (4mhz cer amic) , osc3b = off , osc3a = on, osc3b = off , osc1a = 32.768khz cr ystal, osc1a = 32.768khz cr ystal, pcken[1:0] = 0x3, t yp . v alue pcken[1:0] = 0x3, t a = 25c , t yp . v alue -50 1500 1000 500 0 -25 02 55 07 5 100 ta [c] i exe2 [a] 1/1 1/2 1/4 1/8 gear ratio 0.0 1400 1200 1000 800 600 400 200 0 1.0 2.0 3.0 4.0 5.0 f osc3a [mhz] i exe2 [a] 1/1 1/2 1/4 1/8 gear ratio
22 electrical chara cteristics 22-4 seiko epson corporation s1c17651 t echnical m anual current consumption-temperature c haracteristic current consumption-frequenc y c haracteristic during e x ecution with osc3b + c loc k g ear during e x ecution with osc3b osc3b = on (2mhz), osc3a = off , osc3b = on, osc3a = off , osc1a = 32.768khz cr ystal, osc1a = 32.768khz cr ystal, pcken[1:0] = 0x3, t yp . v alue pcken[1:0] = 0x3, cclkgr[1:0] = 0x2, t a = 25c , t yp . v alue -50 800 700 600 500 400 300 200 100 0 -25 02 55 07 5 100 ta [c] i exe3 [a] 1/1 1/2 1/4 1/8 gear ratio 0.0 700 600 500 400 300 200 100 0 0.5 1.0 1.5 2.0 2.5 f osc3b [mhz] i exe3 [a] 1/1 1/2 1/4 1/8 gear ratio oscillation characteristics 22.4 oscillation characteristics change depending on conditions (board pattern, components used, etc.). use the follo w- ing characteristics as reference v alues. osc1a cr ystal oscillation unless otherwise specified: v dd = 2.0 to 3.6v , v ss = 0v , t a = 25c , c g = b uilt-in, c d = b uilt-in, r f = b uilt-in, r d = b uilt-in, c g1 = 3pf , c d1 = 3pf item symbol condition min. t yp. max. unit oscillation star t time *1 t sta 3 s built-in gate capacitance c g in case of the chip 10 pf built-in dr ain capacitance c d in case of the chip 5 pf *1 cr ystal resonator = c-002rx: man uf actured b y epson t o y ocom (r 1 = 50kw max., c l = 7pf) mc-146: man uf actured b y epson t o y ocom (r 1 = 65kw max., c l = 7pf) osc1b oscillation unless otherwise specified: v dd = 2.0 to 3.6v , v ss = 0v , t a = 2 5c item symbol condition min. t yp. max. unit oscillation star t time t sta 200 s oscillation frequency *1 *2 f osc1b t yp . 0.95 32.768 t yp . 1.05 khz dependence of oscillation frequency on temper ature *2 tf osc1b f requency accur acy per 1c change in temper ature (with ref erence to 25c) 0.12 0.3 %/c *1 in chip mounting, the v alue ma y e xceed the r ange sho wn abo v e according to the mount condition on the board. *2 ref erence v alue osc3a cr ystal oscillation unless otherwise specified: v dd = 2.0 to 3.6v , v ss = 0v , t a = 25c , r f = b uilt-in, r d = b uilt-in, c g3 = 15pf , c d3 = 15pf item symbol condition min. t yp. max. unit oscillation star t time *1 *2 t sta 20.0 ms *1 cr ystal resonator = ma-406: man uf actured b y epson t o y ocom *2 the oscillation star t time v ar ies according to the cr ystal resonator used and the c g3 and c d3 v alues . osc3a ceramic oscillation unless otherwise specified: v dd = 2.0 to 3.6v , v ss = 0v , t a = 25c , r f = b uilt-in, r d = b uilt-in item symbol condition min. t yp. max. unit oscillation star t time *1 *2 t sta 1.0 ms *1 cer amic resonator = cstcc2m00g56-r0: man uf actured b y mur ata man uf actur ing co ., ltd. ( smd , c g3 = c d3 = 47pf b uilt-in) cstcr4m00g53-r0: man uf actured b y mur ata man uf actur ing co ., ltd. ( smd , c g3 = c d3 = 15pf b uilt-in) cstls4m00g53-b0: man uf actured b y mur ata man uf actur ing co ., ltd. (leaded , c g3 = c d3 = 15pf b uilt-in) *2 the osc illation star t time v ar ies according to the cer amic resonator used and the c g3 and c d3 v alues .
22 electrical chara cteristics s1c17651 t echnical m anual seiko epson corporation 22-5 osc3b oscillation unless otherwise specified: v dd = 2.0 to 3.6v , v ss = 0v , t a = 25c item symbol condition min. t yp. max. unit oscillation star t time t sta 5.0 s oscillation frequency *1 f osc3b osc3bfsel[1:0] = 0x0 (2mhz) t yp . 0.95 1.936 t yp . 1.05 mhz osc3bfsel[1:0] = 0x1 (1mhz) 1.002 mhz osc3bfsel[1:0] = 0x2 (500khz) 0.511 mhz dependence of oscillation frequency on temper ature *1 tf osc3b osc3bfsel[1:0] = 0x0C0x2, f requency accur acy per 1c change in temper ature (with ref erence to 25c) 0.05 0.07 %/c *1 ref erence v alue external cloc k input characteristics 22.5 exclx t ech t ecl t cf t cr v ih v il sclkx t cf t cr v ih v il unless otherwise specified: v dd = 2.0 to 3.6v , v ss = 0v , v ih = 0.8v dd , v il = 0.2v dd , t a = -40 to 85c item symbol min. t yp. max. unit exclx input high pulse width t ech 60 ns exclx input lo w pulse width t ecl 60 ns u ar t tr ansf er r ate r u 230400 bps u ar t tr ansf er r ate (ird a mode) r uird a 115200 bps input r ise time t cr 80 ns input f all time t cf 80 ns input/output pin characteristics 22.6 unless otherwise specified: v dd = 2.0 to 3.6v , v ss = 0v , t a = -40 to 85c item symbol condition min. t yp. max. unit high le v el schmitt input threshold v oltage v t+ pxx, #reset 0.5v dd 0.9v dd v lo w le v el schmitt input threshold v oltage v t - pxx, #reset 0.1v dd 0.5v dd v hysteresis v oltage dv t pxx, #reset 0.1v dd v high le v el output current i oh pxx, v oh = 0.9v dd -0.5 ma lo w le v el output current i ol pxx, v ol = 0.1v dd 0.5 ma leakage current i leak pxx, #reset -100 100 na input pull-up resistance r in pxx, #reset 100 500 kw pin capac itance c in pxx, v in = 0v , f = 1mhz, t a = 25c 15 pf reset lo w pulse width t sr v ih = 0.8v dd , v il = 0.2v dd 100 s oper ating po w er v oltage v sr 2.0 v #reset po w er-on reset time t psr 1.0 ms sc hmitt input threshold v olta g e v dd 0 v t + v t - 0 v in (v) v out (v) v dd
22 electrical chara cteristics 22-6 seiko epson corporation s1c17651 t echnical m anual high-le vel output current c haracteristic lo w-le vel output current c haracteristic t a = 85c , max. v alue t a = 85c , min. v alue 0.0 0 -2 -4 -6 -8 -10 -12 0.2 0.4 0.6 0.8 1.0 v dd Cv oh [v] i oh [ma] v dd = 2.0 v v dd = 3.6 v 0.0 7 6 5 4 3 2 1 0 i ol [ma] v ol [v] 0.2 0.4 0.6 0.8 1.0 v dd = 2.0 v v dd = 3.6 v reset pulse #reset t sr v ih v il #reset po wer -on reset timing power on v dd t psr v sr #reset #reset v ss 0.5v dd 0.1v dd cres note: be sure to set the #reset pin to 0.1 v dd or less when perf or ming a po w er-on reset after the po w er is tur ned off . spi characteristics 22.7 spiclkx (cpol = 0) spiclkx (cpol = 1) sdix sdox t spck t sdo t sdh t sds master mode unless otherwise specified: v dd = 2.0 to 3.6v , v ss = 0v , t a = -40 to 85c item symbol min. t yp. max. unit spiclkx cycle time t spck 500 ns sdix setup time t sds 70 ns sdix hold time t sdh 10 ns sdox output dela y time t sdo 20 ns
22 electrical chara cteristics s1c17651 t echnical m anual seiko epson corporation 22-7 sla ve mode unless otherwise specified: v dd = 2.0 to 3.6v , v ss = 0v , t a = -40 to 85c item symbol min. t yp. max. unit spiclkx cycle time t spck 500 ns sdix setup time t sds 30 ns sdix hold time t sdh 50 ns sdox output dela y time t sdo 80 ns lcd driver characteristics 22.8 the typical v alues in the follo wing lcd dri v er characteristics v aries depending on the panel load (panel size, dri v e d u t y , n u m b e r o f d i s p l a y p i x e l s a n d d i s p l a y c o n t e n t s ) , s o e v a l u a t e t h e m b y c o n n e c t i n g t o t h e a c t u a l l y u s e d l c d p a n e l . lcd drive v olta g e unless otherwise specified: v dd = 2.2 to 3.6v , v ss = 0v , t a = 25c , c 3 Cc 6 = 0.1f , chec k er patter n displa y ed, no panel load, vcsel = 1 (v c2 ref erence v oltage), lcd_bclk[1:0] = 0x1 (2khz/osc1a = 32khz source cloc k), frmcnt[1:0] = 0x1 (64hz/osc1a = 32khz (lclk = 512hz)), lduty[2:0] = 0x3 (1/4 duty), dspc[1:0] = 0x1(nor mal displa y) item symbol condition min. t yp. max. unit lcd dr iv e v oltage (v c2 ref erence v oltage) v c1 connect 1mw load resistor betw een v ss and v c1 t yp . 0.96 0.974 t yp . 1.04 v v c2 connect 1mw load resistor betw een v ss and v c2 1.958 v v c3 connect 1mw load resistor betw een v ss and v c3 2.900 v unless otherwise specified: v dd = 2.0 to 3.6v , v ss = 0v , t a = 25c , c 3 Cc 6 = 0.1f , chec k er patter n displa y ed, no panel load, vcsel = 0 (v c 1 ref erence v oltage), lcd_bclk[1:0] = 0x1 (2khz/osc1a = 32khz source cloc k), frmcnt[1:0] = 0x1 (64hz/osc1a = 32khz (lclk = 512hz)), lduty[2:0] = 0x3 (1/4 duty), dspc[1:0] = 0x1(nor mal displa y) item symbol condition min. t yp. max. unit lcd dr iv e v oltage (v c1 ref erence v oltage) v c1 connect 1mw load resistor betw een v ss and v c1 t yp . 0.96 0.977 t yp . 1.04 v v c2 connect 1mw load resistor betw een v ss and v c2 1.884 v v c3 connect 1mw load resistor betw een v ss and v c3 2.800 v lcd drive v olta g e-suppl y v olta g e c haracteristic lcd drive v olta g e-suppl y v olta g e c haracteristic (when v c2 ref erence v olta g e is selected) ( when v c1 ref erence v olta g e is selected) v dd = 1.6 to 3.6v , lcd_bclk[1:0] = 0x1 (2khz/osc1a = 32khz v dd = 1.6 to 3.6v , lcd_bclk[1:0] = 0x1 (2khz/osc1a = 32khz source cloc k), frmcnt[1:0] = 0x1 (64hz/osc1a = 32khz source cloc k), frmcnt[1:0] = 0x1 (64hz/osc1a = 32khz (lclk = 512hz)), lduty[2:0] = 0x3 (1/4 duty), (lclk = 512hz)), lduty[2:0] = 0x3 (1/4 duty), dspc[1:0] = 0x1(nor mal displa y), when a 1 mw load resistor dspc[1:0] = 0x1(nor mal displa y), when a 1 mw load resistor is connected betw een v ss Cv c1 , v ss Cv c2 , and v ss Cv c3 is connected betw een v ss Cv c1 , v ss Cv c2 , and v ss Cv c3 (no panel load), chec k er patter n displa y ed, t a = 25c, t yp . v alue (no panel load), chec k er patter n displa y ed, t a = 25c, t yp . v alue 1.5 2.0 2.5 3.0 3.5 4.0 4.0 3.0 2.0 1.0 v dd [v] v c3 [v] 1.5 4.0 3.0 2.0 1.0 v dd [v] v c3 [v] 2.0 2.5 3.0 3.5 4.0
22 electrical chara cteristics 22-8 seiko epson corporation s1c17651 t echnical m anual lcd drive v olta g e-temperature c haracteristic lcd drive v olta g e-load c haracteristic v dd = 3.0v , lcd_bclk[1:0] = 0x1 (2khz/osc1a = 32khz v dd = 2.2v (v c2 ref erence)/v dd = 1.8v (v c1 ref erence), source cloc k), frmcnt[1:0] = 0x1 (64hz/osc1a = 32khz lcd_bclk[1:0] = 0x1 (2khz/osc1a = 32khz (lclk = 512hz)), lduty[2:0] = 0x3 (1/4 duty), source cloc k), frmcnt[1:0] = 0x1 (64hz/osc1a = 32khz dspc[1:0] = 0x1(no r mal displa y), when a 1 mw load resistor (lclk = 512hz)), lduty[2:0] = 0x3 (1/4 duty), is connected betw een v ss Cv c1 , v ss Cv c2 , and v ss Cv c3 dspc[1:0] = 0x1(nor mal displa y), when a 1 mw load resistor (no panel load), chec k er patter n displa y ed, t yp . v alue is connected betw een v ss Cv c1 , v ss Cv c2 , and v ss Cv c3 (no panel load), chec k er patter n displa y ed, t a = 25c, t yp . v alue -50 1.04v c3 1.03v c3 1.02v c3 1.01v c3 1.00v c3 0.99v c3 0.98v c3 0.97v c3 0.96v c3 -25 02 55 07 5 100 ta [c] v c3 [v] v c2 ref erence v c1 ref erence -i vc3 [a] v c3 [v] 0 3.0 2.8 2.6 2.4 2.2 2.0 v c1 ref erence v c2 ref erence 51 03 0 15 20 25 seg/com output c haracteristics unless otherwise specified: v dd = 2.0 to 3.6v , v ss = 0v , t a = -40 to 85c item symbol condition min. t yp. max. unit segment/common output current i segh segxx, comxx, v segh = v c3 - 0.1v -10 a i segl segxx, comxx, v segl = 0.1v 10 a lcd driver cir cuit current consumption unless otherwise specified: v dd = 2.2 to 3.6v (v c2 ref erence)/2.0 to 3.6v (v c1 ref erence), v ss = 0v , t a = 25c , c 3 Cc 6 = 0.1f , chec k er patter n displa y ed, no panel load, pcken[1:0] = 0x0 (off), lcd_bclk[1:0] = 0x1 (2khz/osc1a = 32khz source cloc k), frmcnt[1:0] = 0x1 (64hz/osc1a = 32khz (lclk = 512hz)), lduty[2:0] = 0x3 (1/4 duty), dspc[1:0] = 0x1(nor mal displa y) item symbol condition min. t yp. max. unit lcd circuit current with v c2 ref erence v oltage *1 i lcd2 vcsel = 1 200 215 na lcd circuit current with v c1 ref erence v oltage *1 i lcd1 vcsel = 0 300 330 na hea vy load protection mode lcd circuit current with v c2 ref erence v oltage *1 i lcd2h lhvld = 1, vcsel = 1 2.2 3.5 a hea vy load protection mode lcd circuit current with v c1 ref erence v oltage *1 i lcd1h lhvld = 1, vcsel = 0 1.3 2 .0 a *1 this v alue is added to the current consumption in hal t mode or current consumption dur ing e x ecution when the lcd circuit is ac- tiv e . current consumption increases according to the displa y contents and panel load. lcd frame frequenc y dependence current consumption c haracteristic v dd = 3.0v , t a = 25c , lcd_bclk[1:0] = 0x1 (2khz/osc1a = 32khz source cloc k), frmcnt[1:0] = 0x0 to 0x3 (128 to 32hz /osc1a = 32khz (lclk = 512hz)), lduty[2:0] = 0x3 (1/4 duty), dspc[1:0] = 0x1(nor mal displa y), chec k er patter n displa y ed, no panel load, pcken[1:0] = 0x0 (off), t yp . v alue 0 20 40 60 80 100 120 140 500 400 300 200 100 0 lcd_frm [hz] i lcd1_fr [na] v c2 ref erence v c1 ref erence
22 electrical chara cteristics s1c17651 t echnical m anual seiko epson corporation 22-9 lcd boost c loc k frequenc y dependence current consumption c haracteristic/ drive v olta g e c haracteristic common conditions: t a = 25c , lcd_bclk[1:0] = 0x0 to 0x3 (4khz to 512hz/osc1a = 32khz source cloc k), frmcnt[1:0] = 0x1 (64hz/osc1a = 32khz (lclk = 512hz)), lduty[2:0] = 0x3 (1/4 duty), dspc[1:0] = 0x1(nor mal displa y), chec k er patter n displa y ed, no panel load, pcken[1:0] = 0x0 (off), t yp . v alue current consumption char acter istic conditions: v dd = 3.0v dr iv e v oltage char acter istic conditions: v dd = 1.8v (v c1 ref erence)/v dd = 2.2v (v c2 ref erence) , when a 1 mw load resistor is connected betw een v ss Cv c1 and v ss Cv c2 , and a 1a load is connected to v c3 0.0 500 400 300 200 100 0 3.0 2.5 2.0 1.5 1.0 0.5 0.0 lcd_bclk [khz] i lcd1_bclk [na] v c3 [v] 1.0 2.0 3.0 4.0 5.0 v c2 ref erence v c1 ref erence v c3 (v c1 ref erence) v c3 (v c2 ref erence) current consumption character istic dr iv e v oltage character istic svd cir cuit characteristics 22.9 analog c haracteristics unless otherwise specified: v dd = 2.0 to 3.6v , v ss = 0v , t a = -40 to 85c item symbol condition min. t yp. max. unit svd v oltage v svd svdc[4:0] = 0x0 t yp . 0.96 C t yp . 1.04 v svdc[4:0] = 0x1 C v svdc[4:0] = 0x2 C v svdc[4:0] = 0x3 C v svdc[4:0] = 0x4 C v svdc[4:0] = 0x5 C v svdc[4:0] = 0x6 C v svdc[4:0] = 0x7 C v svdc[4:0] = 0x8 C v svdc[4:0] = 0x9 C v svdc[4:0] = 0xa C v svdc[4:0] = 0xb C v svdc[4:0] = 0xc C v svdc[4:0] = 0xd C v svdc[4:0] = 0x e 2.00 v svdc[4:0] = 0xf 2.10 v svdc[4:0] = 0x10 2.20 v svdc[4:0] = 0x11 2.30 v svdc[4:0 ] = 0x12 2.40 v svdc[4:0] = 0x13 2.50 v svdc[4:0] = 0x14 2.60 v svdc[4:0] = 0x15 2.70 v svdc[4:0] = 0x16 2.80 v svdc[4:0] = 0x17 2.90 v svdc[4:0] = 0x18 3.00 v svdc[4:0] = 0x19 3.10 v svdc[4:0] = 0x1a 3.20 v svdc[4:0] = 0x1b C v svdc[4:0] = 0x1c C v svdc[4:0] = 0x1d C v
22 electrical chara cteristics 22-10 seiko epson corporation s1c17651 t echnical m anual item symbol condition min. t yp. max. unit svd v oltage v svd svdc[4:0] = 0x1e t yp . 0.96 C t yp . 1.04 v svdc[4:0] = 0x1f C v svd circuit-enab le response time *1 t svden 500 s svd circuit response time *2 t svd 60 s *1 this time is required to obtain stab le detection results after svden is altered from 0 to 1. *2 this time is required to obtain stab le detection results after svdc[4:0] is altered. svd cir cuit current consumpt ion unless otherwise specified: v dd = 2.0 to 3.6v , v ss = 0v , t a = 25c item symbol condition min. t yp. max. unit svd circuit current *1 i svd v dd = 3.6v , svdc[4:0] = 0x e (2.0v) 12 17 a *1 this v alue is added to the current consumption dur ing sleep/hal t/e x ecution (with or without hea vy load protection mode) when the svd circuit is activ e . flash memor y characteristics 22.10 unless otherwise specified: v dd = 2.0 to 3.6v , v pp = 7.0v (f or prog r amming)/7.5v (f or er asing), v ss = 0v , t a = 10 to 40c item symbol condition min. t yp. max. unit prog r amming count *1 c fep prog r ammed data is guar anteed to be retained f or 10 y ears . 3 times *1 assumed that er asing + prog r amming as count of 1. the count includes prog r amming in the f actor y .
23 b asic external connection dia gram s1c17651 t echnical m anual seiko epson corporation 23-1 basic exter nal connection diagram 23 p00/sin0 p01/sout0 p02/sclk0/fouta/regmon p03/excl0/regmon/lfro p04/touta0/capa0 p05/toutb0/capb0/#spiss0 p07/#bz/sdo0 p10/foutb/spiclk0 p06/bz/sdi0 dsio/p12/#bz dst2/p13 dclk/p11/bz s1c17651 c g1 c 1 c 2 c 3 c 4 c 5 c 6 x'tal1 *1 *2 c p + x'tal3 or ceramic c g3 c d3 c d1 r 1 2.0C3.6 v seg0 seg19 com0 com3 i/o lcd panel [the potential of the substrate (back of the chip) is v ss .] v dd icdmini or i/o buzzer v dd v dd osc1 osc2 osc3 osc4 v d1 v osc v c1 v c2 v c3 ca cb iref_m #reset test0 v ss v pp cres *1: this e xter nal circuit is required only when the osc1a oscillator is used. *2: this e xter nal circuit is required only when the osc3a oscillator is used.
23 b asic external connection dia gram 23-2 seiko epson corporation s1c17651 t echnical m anual recommended v alues f or e xternal par ts exter nal par ts f or the osc1a oscillator circuit symbol resonator recommended man ufacturer frequenc y [hz] pr oduct n umber recommended v alues recommended o p e r a t i n g c o n d i t i o n c d1 [pf] c g1 [pf] t emperature rang e [c] x'tal1 cr ystal epson t o y ocom cor por ation 32.768k c - 0 0 2 r x ( r 1 = 5 0 k w ( m a x . ) , c l = 7 pf) 3 3 -10 to 60c mc-146 (r 1 = 65 kw (max.), c l = 7 pf) 3 3 -40 to 85c exter nal par ts f or the osc3a oscillator circuit symbol resonator recommended man ufacturer frequenc y [hz] pr oduct n umber recommended v alues * recommended o p e r a t i n g c o n d i t i o n c d3 [pf] c g3 [pf] t emperature rang e [c] x'tal3 cr ystal epson t o y ocom cor por ation 4m ma-406 15 15 -20 to 70c cer amic cer amic mur ata man uf actur ing co ., ltd. 2m cstcc2m00g56-r0 (smd) (47) (47) -40 to 85c 4m cstcr4m00g53-r0 (smd) (15) (15) -40 to 85c 4m cstls4m00g53-b0 (lead) (15) (15) -40 to 85c * the c d3 and c g3 v alues enclosed with ( ) are the b uilt-in capacitances of the resonator . other symbol name recommended v alue cp capacitor f or po w er supply 3.3 f c g1 gate capacitor 3 pf c d1 dr ain capacitor 3 pf c g3 gate capacitor 15 pf c d3 dr ain capacitor 15 pf cres capacitor f or #reset pin 0.47 f c 1 capacitor betw een v d1 and v ss 0.1 f c 2 capacitor betw een v osc and v ss 0.1 f c 3 capacitor betw een v c1 and v ss 0.1 f c 4 capacitor betw een v c2 and v ss 0.1 f c 5 capacitor betw een v c3 and v ss 0.1 f c 6 capacitor betw een ca and cb 0 .1 f r 1 dsio pull-up resistor 10 kw notes: ? the v alues in the abo v e tab le are sho wn only f or ref erence and not guar anteed. ? cr ystal and cer amic resonators are e xtremely sensitiv e to influence of e xter nal components and pr inted-circuit boards . bef ore using a resonator , please contact the man uf acturer f or fur- ther inf or mation on conditions of use .
24 p a cka ge/chip s1c17651 t echnical m anual seiko epson corporation 24-1 p ackage/chip 24 tqfp p ac ka g e 24.1 tqfp13-64pin pac ka g e (unit: mm) 10 12 33 48 10 12 17 32 index 0.17C0.27 16 1 64 49 1 0.1 1.2 max 1 0.3C0.75 0C10 0.09C0.2 0.5 1.1 tqfp13-64pin p ac kage dimensions figure 24.
24 p a cka ge/chip 24-2 seiko epson corporation s1c17651 t echnical m anual chip 24.2 p ad configuration 24.2.1 y x (0, 0) 2.418 mm 2.634 mm die no. cj651dxxx 1 2 3 4 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 40 39 38 37 36 35 34 33 32 31 30 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2.1.1 s1c17651 p ad configur ation diag r am figure 24. chip siz e x = 2.634 mm, y = 2.418 mm p ad opening no . 1 to 13, 30 to 40: x = 76 m, y = 85 m no . 14 to 29, 41 to 55: x = 85 m, y = 76 m chip thic kness 400 m
24 p a cka ge/chip s1c17651 t echnical m anual seiko epson corporation 24-3 2.1.1 s1c17651 p ad coordinates t ab le 24. no. name x (m) y (m) no. name x (m) y (m) 1 seg19 -337.0 -1106.5 30 iref_m 564.0 1106.5 2 seg18 -247.0 -1106.5 31 v osc 474.0 1106.5 3 seg17 -157.0 -1106.5 32 osc1 384.0 1106.5 4 seg16 -67.0 -1106.5 33 osc2 294.0 1106.5 5 seg15 23.0 -1106.5 34 v d1 -315.0 1106.5 6 seg14 113.0 -1106.5 35 osc3 -405.0 1106.5 7 seg13 203.0 -1106.5 36 osc4 -495.0 1106.5 8 seg12 293.0 -1106.5 37 test0 -585.0 1106.5 9 seg11 383.0 -1106.5 38 v ss -675.0 1106.5 10 seg10 473.0 -1106.5 39 v dd -765.0 1106.5 11 seg9 563.0 -1106.5 40 #reset -855.0 11 06.5 12 seg8 653.0 -1106.5 41 p00/sin0 -1214.5 1048.0 13 seg7 743.0 -1106.5 42 p01/sout0 -1214.5 958.0 14 seg6 1214.5 -999.0 43 p02/sclk0/fout a/regmon -1214.5 868.0 15 seg5 1214.5 -909.0 44 p03/excl0/regmon/lfr o -1214.5 778.0 16 seg4 1214.5 -819.0 45 p04/t out a0/cap a0 -1214.5 688.0 17 seg3 1214.5 -729.0 46 p05/t outb0/capb0/#spiss0 -1214.5 598.0 18 seg2 1214.5 -639.0 47 p06/bz/sdi0 -1214.5 508.0 19 seg1 1214.5 -549.0 48 p07/#bz/sdo0 -1214.5 418.0 20 seg0 1214.5 -459.0 49 p10/fo utb/spiclk0 -1214.5 328.0 21 com3 1214.5 -357.0 50 dclk/p11/bz -1214.5 -586.0 22 com2 1214.5 -267.0 51 dsio/p12/#bz -1214.5 -676.0 23 com1 1214.5 -177.0 52 dst2/p13 -1214.5 -766.0 24 com0 1214.5 -87.0 53 v dd -1214.5 -856.0 25 v c3 1214.5 640.5 54 v ss -1214.5 -946.0 26 v c2 1214.5 730.5 55 v pp -1214.5 -1036.0 27 v c1 1214.5 820.5 28 cb 1214.5 910.5 29 ca 1214.5 1000.5
appendix a list of i/o registers s1c17651 t echnical m anual seiko epson corporation ap-a-1 a ppendix a list of i/o registers internal peripheral cir cuit area 1 (0x4000C0x43ff) p eripheral ad dress register name function misc register (8-bit de vice) 0x4020 misc_ dmode1 deb ug mode control register 1 e n a b l e s p e r i p h e r a l o p e r a t i o n s i n d e b u g m o d e (pclk). u ar t (with ird a) ch.0 (8-bit de vice) 0x4100 u ar t_st0 u ar t ch.0 status register indicates tr ansf er , b uff er and error statuses . 0x4101 u ar t_txd0 u ar t ch.0 t r ansmit data register t r ansmit data 0x4102 u ar t_rxd0 u ar t ch.0 receiv e data register receiv e data 0x4103 u ar t_mod0 u ar t ch.0 mode register sets tr ansf er data f or mat. 0x4104 u ar t_ctl0 u ar t ch.0 control register controls data tr ansf er . 0x4105 u ar t_exp0 u ar t ch.0 expansion register sets ird a mode . 0x4106 u ar t_br0 u ar t ch.0 baud rate register sets baud r ate . 0x4107 u ar t_fmd0 u ar t ch.0 fine mode register sets fine mode . 8-bit timer ch. 0 (16-bit de vice) 0x4240 t8_clk0 t8 ch.0 count cloc k select register selects a count clo c k. 0x4242 t8_tr0 t8 ch.0 reload data register sets reload data. 0x4244 t8_tc0 t8 ch.0 counter data register counter data 0x4246 t8_ctl0 t8 ch.0 control register sets the timer mode and star ts/stops the timer . 0x4248 t8_int0 t8 ch.0 interr upt control register controls the interr upt. interr upt controller (16-bit de vice) 0x4306 itc_l v0 interr upt le v el setup register 0 sets the p0 interr upt le v el. 0x4308 itc_l v1 interr upt le v el setup register 1 sets the ct interr upt le v el. 0x430a itc_l v2 interr upt le v el setup register 2 sets the r tc interr upt le v el. 0x430c itc_l v3 interr upt le v el setup register 3 s e t s t h e l c d a n d t 1 6 a 2 c h . 0 i n t e r r u p t l e v e l s . 0x4310 itc_l v5 interr upt le v el setup register 5 sets the t8 ch.0 interr upt le v el. 0x4312 itc_l v6 interr upt le v el setup register 6 sets the u ar t ch.0 interr upt le v el. 0x4314 itc_l v7 interr upt le v el s etup register 7 sets the spi ch.0 interr upt le v el. spi ch.0 (16-bit de vice) 0x4320 spi_st0 spi ch.0 status register indicates tr ansf er and b uff er statuses . 0x4322 spi_txd0 spi ch.0 t r ansmit data register t r ansmit data 0x4324 spi_rxd0 spi ch.0 receiv e data register receiv e data 0x4326 spi_ctl0 spi ch.0 control register sets the spi mode and enab les data tr ansf er . internal p eripheral cir cuit area 2 (0x5000C0x5fff) p eripheral ad dress register name function cloc k timer (8-bit de vice) 0x5000 ct_ctl cloc k timer control register resets and star ts/stops the timer . 0x5001 ct_cnt cloc k timer counter register counter data 0x5002 ct_imsk cloc k timer interr upt mask register enab les/disab les interr upt. 0x5003 ct_iflg cloc k timer interr upt flag register indicates/resets interr upt occurrence status . w atchdog timer (8-bit de vice) 0x5040 wdt_ctl w a tchdog timer control register resets and star ts/stops the timer . 0x5041 wdt_st w atchdog timer status register s e t s t h e t i m e r m o d e a n d i n d i c a t e s n m i s t a t u s . c l o c k g e n e r a t o r /theoretical regulation (8-bit de vice) (t16a2, u ar t , snd , lcd , tr) 0x5060 clg_src cloc k source select register selects the cloc k source . 0x5061 clg_ctl oscillation control register controls oscillation. 0x5064 clg_fout a fout a control register contro ls fout a cloc k output. 0x5065 clg_foutb foutb control register controls foutb cloc k output. 0x5068 t16a_clk0 t16a2 cloc k control register ch.0 controls the t16a2 ch.0 cloc k. 0x506c u ar t_clk0 u ar t ch.0 cloc k control register selects the baud r ate gener ator cloc k. 0x506e snd_clk snd cloc k control register controls the snd cloc k. 0x5070 lcd_tclk lcd timing cloc k control register controls the lcd cloc k. 0x5071 lcd_bclk lcd booster cloc k control register controls the lcd booster cloc k. 0x5078 tr_ctl tr control register controls theoretical regulation. 0x5079 tr_v al tr v alue register sets a regulation v alue . 0x507d clg_w ait oscillation stabilization w ait control register controls oscillation stabilization w aiting time . 0x5080 clg_pclk pclk control register controls the pclk supply . 0x5081 clg_cclk cclk control register configures the cclk division r atio . lcd dr iv er (8-bit de vice) 0x5063 lcd_tclk lcd cloc k select register selects the lcd cloc k. 0x50a0 lcd_dctl lcd displa y control register controls the lcd displa y . 0x50a2 lcd_cctl lcd cloc k control register controls the lcd dr iv e duty . 0x50a3 lcd_vreg lcd v oltage regulator control register controls the lcd dr iv e v oltage regulator . 0x50a5 lcd_imsk lcd interr upt mask register enab les/disab les interr upts . 0x 50a6 lcd_iflg lcd interr upt flag register indicates/resets interr upt occurrence status . svd circuit (8-bit de vice) 0x5100 svd_en svd enab le register enab les/disab les the svd oper ation. 0x5101 svd_cmp svd compar ison v oltage register sets the compar ison v oltage . 0x5102 svd_rsl t svd detection result register v oltage detection results p o w e r g e n e r a t o r (8-bit de vice) 0x5120 vd1_ctl v d1 control register controls the v d1 regula tor hea vy load protec- tion mode . sound gener ator (8-bit de vice) 0x5180 snd_ctl snd control register controls b uzz er outputs . 0x5181 snd_bzfq buzz er f requency control register sets the b uzz er frequency . 0x5182 snd_bzdt buzz er duty ratio control register sets the b uzz er signal duty r atio .
appendix a list of i/o registers ap-a-2 seiko epson corporation s1c17651 t echnical m anual p eripheral ad dress register name function p por t & por t mux (8-bit de vice) 0x5200 p0_in p0 p or t input data register p0 por t input data 0x5201 p0_out p0 p or t output data register p0 por t output data 0x5202 p0_oen p0 p or t output enab le register enab les p0 por t outputs . 0x5203 p0_pu p0 p or t pull-up control register controls the p0 por t pull-up resistor . 0x5205 p0_imsk p0 p or t interr upt mask register enab les p0 por t interr upt s . 0x5206 p0_edge p0 p or t interr upt edge select register selects the signal edge f or gener ating p0 por t interr upts . 0x5207 p0_iflg p0 p or t interr upt flag register indicates/resets the p0 por t interr upt occur- rence status . 0x5208 p0_cha t p0 p or t chatter ing filter control register controls the p0 por t chatter ing filter . 0x5209 p0_krst p0 p or t k e y-entr y reset configur ation register c o n f i g u r e s t h e p 0 p o r t k e y - e n t r y r e s e t f u n c t i o n . 0x520a p0_ien p0 p or t input enab le register enab les p0 por t inputs . 0x5210 p1_in p1 p or t input data register p1 por t input data 0x5211 p1_out p1 p or t output data register p1 por t output data 0x5212 p1_oen p1 p or t output enab le register enab les p1 por t outputs . 0x5213 p1_pu p1 p or t pull-up control register controls the p1 por t pull-up resistor . 0x521a p1_ien p1 p or t input enab le register enab les p1 por t inp uts . 0x52a0 p00_03pmux p0[3:0] p or t function select register selects the p0[3:0] por t functions . 0x52a1 p04_07pmux p0[7:4] p or t function select register selects the p0[7:4] por t functions . 0x52a2 p10_13pmux p1[3:0] p or t function select register selects the p1[3:0] por t functions . misc registers (16-bit de vice) 0x5322 misc_ dmode2 deb ug mode control register 2 e n a b l e s p e r i p h e r a l o p e r a t i o n s i n d e b u g m o d e (e xcept pclk) . 0x5324 misc_pr o t misc protect register enab les wr iting to the misc registers . 0x5326 misc_iramsz iram siz e select register selects the iram siz e . 0x5328 misc_ttbrl v ector t ab le address lo w register sets v ector tab le address . 0x532a misc_ttbrh v ector t ab le address high register 0x532c misc_psr psr register indicates the s1c17 core psr v alues . 16-bit pwm timer ch.0 (16-bit de vice) 0x5400 t16a_ctl0 t16a counter ch.0 contr ol register controls the counter . 0x5402 t16a_tc0 t16a counter ch.0 data register counter data 0x5404 t16a_ccctl0 t16a compar ator/capture ch.0 control register controls the compar ator/capture b loc k and t out . 0x5406 t16a_cca0 t16a compare/capture ch.0 a data register compare a/capture a data 0x5408 t16a_ccb0 t16a compare/capture ch.0 b data register compare b/capture b data 0x540a t16a_ien0 t16a compare/capture ch.0 interr upt enab le register enab les/disab les interr upts . 0x540c t16a_iflg0 t16a compare/capture ch.0 interr upt flag register displa ys/sets interr upt occurrence status . flash controller (16-bit de vice) 0x54b0 flashc_ w ait flashc read w ait control register sets flash read w ait cycle . real-time cloc k (16-bit de vice) 0x56c0 r tc_ctl r tc control register controls the r tc . 0x56c2 r tc_ien r tc interr upt enab le register enab les/di sab les interr upts . 0x56c4 r tc_iflg r tc interr upt flag register displa ys/sets interr upt occurrence status . 0x56c6 r tc_ms r tc min ute/second counter register min ute/second counter data 0x56c8 r tc_h r tc hour counter register hour counter data core i/o reser ved area (0xffff84C0xffffd0) p eripheral ad dress register name function s1c17 core i/o 0xffff84 idir processor id register indicates the processor id . 0xffff90 dbram deb ug ram base register indicates the deb ug ram base address . 0xffff a0 dcr deb ug control register controls deb ugging. 0xffffb4 ibar1 instr uction break address register 1 sets instr uction break address #1. 0xffffb8 ibar2 instr uction break address register 2 sets instr uction break address #2. 0xffffbc ibar3 instr uction break address register 3 sets instr uction break address #3. 0xffffd0 ibar4 instr uction break address register 4 sets instr uction break address #4. note: addresses mar k ed as reser v ed or un used per ipher al circuit areas not mar k ed in the tab le m ust not be accessed b y application prog r ams .
appendix a list of i/o registers s1c17651 t echnical m anual seiko epson corporation ap-a-3 0x4100C0x4107, 0x506c uart (with irda) ch.0 register name ad dress bit name function setting init. r/w remarks uart ch.0 status register (uart_st0) 0x4100 (8 bits) d7 tred end of tr ansmission flag 1 completed 0 n o t c o m p l e t e d 0 r/w reset b y wr iting 1. d6 fer f r aming error flag 1 error 0 nor mal 0 r/w d5 per p ar ity error flag 1 error 0 nor mal 0 r/w d4 oer ov err un error flag 1 error 0 nor mal 0 r/w d3 rd2b second b yte receiv e flag 1 ready 0 empty 0 r d2 trbs t r ansmit b usy flag 1 busy 0 idle 0 r shift register status d1 rdry receiv e data ready flag 1 ready 0 empty 0 r d0 tdbe t r ansmit data b uff er empty flag 1 empty 0 not empty 1 r uart ch.0 transmit data register (uart_txd0) 0x4101 (8 bits) d7C0 txd[7:0] t r ansmit data txd7(6) = msb txd0 = lsb 0x0 to 0xff (0x7f) 0x0 r/w uart ch.0 receive data register (uart_rxd0) 0x4102 (8 bits) d7C0 rxd[7:0] receiv e data in the receiv e data b uff er rxd7(6) = msb rxd0 = lsb 0x0 to 0xff (0x7f) 0x0 r o l d e r d a t a i n t h e b u f - f er is read out first. uart ch.0 mode register (uart_mod0) 0x4103 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 chln char acter length select 1 8 bits 0 7 bits 0 r/w d3 pren p ar ity enab le 1 with par ity 0 no par ity 0 r/w d2 pmd p ar ity mode select 1 odd 0 ev en 0 r/w d1 stpb stop bit select 1 2 bits 0 1 bit 0 r/w d0 C reser v ed C C C 0 when being read. uart ch.0 control register (uart_ctl0) 0x4104 (8 bits) d7 teien end of tr ansmission int. enab le 1 enab le 0 disab le 0 r/w d6 reien receiv e error int. enab le 1 enab le 0 disab le 0 r/w d5 rien receiv e b uff er full int. enab le 1 enab le 0 disab le 0 r/w d4 tien t r ansmit b uff er empty int. enab le 1 enab le 0 disab le 0 r/w d3C2 C reser v ed C C C 0 when being read. d1 rbfi r e c e i v e b u f f e r f u l l i n t . c o n d i t i o n s e t u p 1 2 b ytes 0 1 b yte 0 r/w d0 rxen u ar t enab le 1 enab le 0 disab le 0 r/w uart ch.0 expansion register (uart_exp0) 0x4105 (8 bits) d7C1 C reser v ed C C C 0 when being read. d0 irmd ird a mode select 1 on 0 off 0 r/w uart ch.0 baud rate register (uart_br0) 0x4106 (8 bits) d7C0 br[7:0] baud r ate setting 0x0 to 0xff 0x0 r/w uart ch.0 fine mode register (uart_fmd0) 0x4107 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C0 fmd[3:0] fine mode setup 0x0 to 0xf 0x0 r/w s e t a n u m b e r o f t i m e s to inser t dela y into a 16-underflo w per iod. uart ch.0 clock control register (uart_clk0) 0x506c (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 utclkd [1:0] cloc k division r atio select utclkd[1:0] division r atio 0x0 r/w when the cloc k source is osc3b or osc3a 0x3 0x2 0x1 0x0 1/8 1/4 1/2 1/1 d3C2 utclksrc [1:0] cloc k source select utclksrc [1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 exter nal cloc k osc3a osc1 osc3b d1 C reser v ed C C C 0 when being read. d0 utclke u ar t cloc k enab le 1 enab le 0 disab le 0 r/w
appendix a list of i/o registers ap-a-4 seiko epson corporation s1c17651 t echnical m anual 0x4240C0x4248 8-bit timer ch.0 register name ad dress bit name function setting init. r/w remarks t8 ch.0 count clock select register (t8_clk0) 0x4240 (16 bits) d15C4 C reser v ed C C C 0 when being read. d3C0 df[3:0] count cloc k division r atio select df[3:0] division r atio 0x0 r/w s o u r c e c l o c k = p c l k 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 t8 ch.0 reload data register (t8_tr0) 0x4242 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 tr[7:0] reload data tr7 = msb tr0 = lsb 0x0 to 0xff 0x0 r/w t8 ch.0 counter data register (t8_tc0) 0x4244 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 tc[7:0] counter data tc7 = msb tc0 = lsb 0x0 to 0xff 0xff r t8 ch.0 control register (t8_ctl0) 0x4246 (16 bits) d15C5 C reser v ed C C C do not wr ite 1. d4 trmd count mode select 1 one shot 0 repeat 0 r/w d3C2 C reser v ed C C C 0 when being read. d1 preser timer reset 1 reset 0 ignored 0 w d0 prun timer r un/stop control 1 run 0 stop 0 r/w t8 ch.0 interrupt control register (t8_int0) 0x4248 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 t8ie t8 interr upt enab le 1 enab le 0 disab le 0 r/w d7C1 C reser v ed C C C 0 when being read. d0 t8if t8 interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. 0x4306C0x4314 interrupt controller register name ad dress bit name function setting init. r/w remarks interrupt level setup register 0 (itc_lv0) 0x4306 (16 bits) d15C3 C reser v ed C C C 0 when being read. d2C0 ilv0[2:0] p0 interr upt le v el 0 to 7 0x0 r/w interrupt level setup register 1 (itc_lv1) 0x4308 (16 bits) d15C11 C reser v ed C C C 0 when being read. d10C8 ilv3[2:0] ct interr upt le v el 0 to 7 0x0 r/w d7C0 C reser v ed C C C 0 when being read. interrupt level setup register 2 (itc_lv2) 0x430a (16 bits) d15C3 C reser v ed C C C 0 when being read. d2C0 ilv4[2:0] r tc interr upt le v el 0 to 7 0x0 r/w interrupt level setup register 3 (itc_lv3) 0x430c (16 bits) d15C11 C reser v ed C C C 0 when being read. d10C8 ilv7[2:0] t16a2 ch.0 interr upt le v el 0 to 7 0x0 r/w d7C3 C reser v ed C C C 0 when being read. d2C0 ilv6[2:0] lcd interr upt le v el 0 to 7 0x0 r/w interrupt level setup register 5 (itc_lv5) 0x4310 (16 bits) d15C3 C reser v ed C C C 0 when being read. d2C0 ilv10[2:0] t8 ch.0 interr upt le v el 0 to 7 0x0 r/w interrupt level setup register 6 (itc_lv6) 0x4312 (16 bits) d15C3 C reser v ed C C C 0 when being read. d2C0 ilv12[2:0] u ar t ch.0 interr upt le v el 0 to 7 0x0 r/w interrupt level setup register 7 (itc_lv7) 0x4314 (16 bits) d15C3 C reser v ed C C C 0 when being read. d2C0 ilv14[2:0] spi ch.0 interr upt le v el 0 to 7 0x0 r/w 0x4320C0x4326 spi ch.0 register name ad dress bit name function setting init. r/w remarks spi ch.0 status register (spi_st0) 0x4320 (16 bits) d15C3 C reser v ed C C C 0 when being read. d2 spbsy t r ansf er b usy flag (master) 1 busy 0 idle 0 r ss signal lo w flag (sla v e) 1 ss = l 0 ss = h d1 sprbf receiv e data b uff er full flag 1 full 0 not full 0 r d0 sptbe t r ansmit data b uff er empty flag 1 empty 0 not empty 1 r
appendix a list of i/o registers s1c17651 t echnical m anual seiko epson corporation ap-a-5 register name ad dress bit name function setting init. r/w remarks spi ch.0 transmit data register (spi_txd0) 0x4322 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 sptdb[7:0] spi tr ansmit data b uff er sptdb7 = msb sptdb0 = lsb 0x0 to 0xff 0x0 r/w spi ch.0 receive data register (spi_rxd0) 0x4324 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 sprdb[7:0] spi receiv e data b uff er sprdb7 = msb sprdb0 = lsb 0x0 to 0xff 0x0 r spi ch.0 control register (spi_ctl0) 0x4326 (16 bits) d15C10 C reser v ed C C C 0 when being read. d9 mclk spi cloc k source select 1 t8 ch.0 0 pclk/4 0 r/w d8 mlsb lsb/msb first mode select 1 lsb 0 msb 0 r/w d7C6 C reser v ed C C C 0 when being read. d5 sprie receiv e data b uff er full int. enab le 1 enab le 0 disab le 0 r/w d4 sptie t r ansmit data b uff er empty int. enab le 1 enab le 0 disab le 0 r/w d3 cpha cloc k phase select 1 data out 0 data in 0 r/w these bits m ust be set bef ore setting spen to 1. d2 cpol cloc k polar ity select 1 activ e l 0 activ e h 0 r/w d1 mssl master/sla v e mode select 1 master 0 sla v e 0 r/w d0 spen spi enab le 1 enab le 0 disab le 0 r/w 0x5000C0x5003 clock timer register name ad dress bit name function setting init. r/w remarks clock timer control register (ct_ctl) 0x5000 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 ctrst cloc k timer reset 1 reset 0 ignored 0 w d3C1 C reser v ed C C C d0 ctrun cloc k timer r un/stop control 1 run 0 stop 0 r/w clock timer counter register (ct_cnt) 0x5001 (8 bits) d7C0 ctcnt[7:0] cloc k timer counter v alue 0x0 to 0xff 0 r clock timer interrupt mask register (ct_imsk) 0x5002 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 ctie32 32 hz interr upt enab le 1 enab le 0 disab le 0 r/w d2 ctie8 8 hz interr upt enab le 1 enab le 0 disab le 0 r/w d1 ctie2 2 hz interr upt enab le 1 enab le 0 disab le 0 r/w d0 ctie1 1 hz interr upt enab le 1 enab le 0 disab le 0 r/w clock timer interrupt flag register (ct_iflg) 0x5003 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 ctif32 32 hz interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d2 ctif8 8 hz interr upt flag 0 r/w d1 ctif2 2 hz interr upt flag 0 r/w d0 ctif1 1 hz interr upt flag 0 r/w 0x5040C0x5041 watchdog timer register name ad dress bit name function setting init. r/w remarks watchdog timer control register (wdt_ctl) 0x5040 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 wdtrst w atchdog timer reset 1 reset 0 ignored 0 w d3C0 wdtrun[3:0] w atchdog timer r un/stop control o t h e r t h a n 1 0 1 0 run 1010 stop 1010 r/w watchdog timer status register (wdt_st) 0x5041 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1 wdtmd nmi/reset mode select 1 reset 0 nmi 0 r/w d0 wdtst nmi status 1 n m i o c c u r r e d 0 n o t o c c u r r e d 0 r 0x5060C0x5081 clock generator register name ad dress bit name function setting init. r/w remarks clock source select register (clg_src) 0x5060 (8 bits) d7C6 osc3b fsel[1:0] osc3b frequency select o s c 3 b f s e l [ 1 : 0 ] f requency 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed 500 khz 1 mhz 2 mhz d5 C reser v ed C C C 0 when being read. d4 osc1sel osc1 source select 1 osc1b 0 osc1a 1 r/w d3C2 C reser v ed C C C 0 when being read. d1C0 clksrc[1:0] system cloc k source select clksrc[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3a osc1 osc3b oscillation control register (clg_ctl) 0x5061 (8 bits) d7C3 C reser v ed C C C 0 when being read. d2 osc3ben osc3b enab le 1 enab le 0 disab le 1 r/w d1 osc1en osc1 enab le 1 enab le 0 disab le 0 r/w d0 osc3aen osc3a enab le 1 enab le 0 disab le 0 r/w
appendix a list of i/o registers ap-a-6 seiko epson corporation s1c17651 t echnical m anual register name ad dress bit name function setting init. r/w remarks fouta control register (clg_fouta ) 0x5064 (8 bits) d7 C reser v ed C C C 0 when being read. d6C4 foutad [2:0] fout a cloc k division r atio select fout ad[2:0] division r atio 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 d3C2 foutasrc [1:0] fout a cloc k source select fout asrc[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3a osc1 osc3b d1 C reser v ed C C C 0 when being read. d0 foutae fout a output enab le 1 enab le 0 disab le 0 r/w foutb control register (clg_foutb ) 0x5065 (8 bits) d7 C reser v ed C C C 0 when being read. d6C4 foutbd [2:0] foutb cloc k division r atio select foutbd[2:0] division r atio 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 d3C2 foutbsrc [1:0] foutb cloc k source select foutbsrc[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3a osc1 osc3b d1 C reser v ed C C C 0 when being read. d0 foutbe foutb output enab le 1 enab le 0 disab le 0 r/w oscillation stabilization wait control register (clg_wait) 0x507d (8 bits) d7C6 osc3bwt [1:0] osc3b stabilization w ait cycle select osc3bwt[1:0] w ait cycle 0x0 r/w 0x3 0x2 0x1 0x0 8 cycles 16 cycles 32 cycles 64 cycles d5C4 osc3awt [1:0] osc3a stabilization w ait cycle select osc3a wt[1:0] w ait cycle 0x0 r/w 0x3 0x2 0x1 0x0 128 cycles 256 cycles 512 cycles 1024 cycles d3C2 osc1bwt [1:0] osc1b stabilization w ait cycle select osc1bwt[1:0] w ait cycle 0x0 r/w 0x3 0x2 0x1 0x0 8 cycles 16 cycles 32 cycles 64 cycles d1C0 osc1awt [1:0] osc1a stabilization w ait cycle select osc1a wt[1:0] w ait cycle 0x0 r/w 0x3 0x2 0x1 0x0 2048 cycles 4096 cycles 8192 cycles 16384 cycles pclk control register (clg_pclk ) 0x5080 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 pcken[1:0] pclk enab le pcken[1:0] pclk supply 0x3 r/w 0x3 0x2 0x1 0x0 enab le not allo w ed not allo w ed disab le cclk control register (clg_cclk ) 0x5081 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 cclkgr[1:0] cclk cloc k gear r atio select cclkgr[1:0] gear r atio 0x0 r/w 0x3 0x2 0x1 0x0 1/8 1/4 1/2 1/1 0x5078C0x5079 theoretical regulation circuit register name ad dress bit name function setting init. r/w remarks tr control register (tr_ctl ) 0x5078 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 rclkfsel monitor cloc k frequency select 1 1 hz 0 256 hz 0 r/w d2 rclkmon regulated cloc k monitor enab le 1 enab le 0 disab le 0 r/w d1 C reser v ed C C C 0 when being read. d0 regtrig regulation tr igger 1 t r igger 0 ignored 0 w
appendix a list of i/o registers s1c17651 t echnical m anual seiko epson corporation ap-a-7 register name ad dress bit name function setting init. r/w remarks tr value register (tr_val) 0x5079 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4C0 trim[4:0] regulation v alue trim[4:0] regulation v alue 0x0 r/w 0xf 0x e : 0x1 0x0 +16 +15 : +2 +1 0x1f 0x1e : 0x11 0x10 0 -1 : -14 -15 0x5070C0x5071, 0x50a0C0x50a6 lcd driver register name ad dress bit name function setting init. r/w remarks lcd timing clock select register (lcd_tclk ) 0x5070 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 lcdtclkd [1:0] lcd cloc k division r atio select lcdtclkd [1:0] division r atio 0x0 r/w osc3b/ osc3a osc1 0x3 0x2 0x1 0x0 1/8192 1/4096 1/2048 1/1024 1/64 1/64 1/64 1/64 d3C2 lcdtclk src[1:0] lcd cloc k source select lcdtclk src[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3a osc1 osc3b d1 C reser v ed C C C 0 when being read. d0 lcdtclke lcd cloc k enab le 1 enab le 0 disab le 0 r/w lcd booster clock control register (lcd_bclk ) 0x5071 (8 bits) d7 C reser v ed C C C 0 when being read. d6C4 lcdbclkd [2:0] lcd booster cloc k division r atio select lcdb clkd [2:0] division r atio 0x0 r/w osc3b osc3a osc1 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 C 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 C 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 C C C C 1/64 1/32 1/16 1/8 d3C2 lcdbclk src[1:0] lcd booster cloc k source select lcdbclk src[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3a osc1 osc3b d1 C reser v ed C C C 0 when being read. d0 lcdbclke lc d booster cloc k enab le 1 enab le 0 disab le 0 r/w lcd display control register (lcd_dctl) 0x50a0 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 dsprev re v erse displa y control 1 nor mal 0 re v erse 1 r/w d3C2 C reser v ed C C C 0 when being read. d1C0 dspc[1:0] lcd displa y control dspc[1:0] displa y 0x0 r/w 0x3 0x2 0x1 0x0 all off all on nor mal displa y displa y off lcd clock control register (lcd_cctl) 0x50a2 (8 bits) d7C6 frmcnt[1:0] f r ame frequency control frmcnt[1:0] division r atio 0x1 r/w source cloc k: lclk 0x3 0x2 0x1 0x0 1/16 1/12 1/8 1/4 d5C3 C reser v ed C C C 0 when being read. d2C0 lduty[2:0] lcd duty select lduty[2:0] duty 0x3 r/w 0x7C0x4 0x3 0x2 0x1 0x0 reser v ed 1/4 1/3 1/2 static lcd voltage regulator control register (lcd_vreg) 0x50a3 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 lhvld v c hea vy load protection mode 1 on 0 off 0 r/w d3C1 C reser v ed C C C 0 when being read. d0 vcsel ref erence v oltage select 1 v c2 0 v c1 0 r/w
appendix a list of i/o registers ap-a-8 seiko epson corporation s1c17651 t echnical m anual register name ad dress bit name function setting init. r/w remarks lcd interrupt mask register (lcd_imsk) 0x50a5 (8 bits) d7C1 C reser v ed C C C 0 when being read. d0 ifrmen f r ame signal interr upt enab le 1 enab le 0 disab le 0 r/w lcd interrupt flag register (lcd_iflg) 0x50a6 (8 bits) d7C1 C reser v ed C C C 0 when being read. d0 ifrmflg f r ame signal interr upt flag 1 occurred 0 n o t o c c u r r e d 0 r/w reset b y wr iting 1. 0x5100C0x5102 svd circuit register name ad dress bit name function setting init. r/w remarks svd enable register (svd_en) 0x5100 (8 bits) d7C1 C reser v ed C C C 0 when being read. d0 svden svd enab le 1 enab le 0 disab le 0 r/w svd comparison voltage register (svd_cmp) 0x5101 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4C0 svdc[4:0] svd compar ison v oltage select svdc[4:0] v oltage 0x0 r/w 0x1fC0x1b 0x1a 0x19 0x18 0x17 0x16 0x15 0x14 0x13 0x12 0x11 0x10 0xf 0x e 0xdC0x0 reser v ed 3.20 v 3.10 v 3.00 v 2.90 v 2.80 v 2.70 v 2.60 v 2.50 v 2.40 v 2.30 v 2.20 v 2.10 v 2.00 v reser v ed svd detection result register (svd_rslt) 0x5102 (8 bits) d7C1 C reser v ed C C C 0 when being read. d0 svddt svd detection result 1 lo w 0 nor mal r 0x5120 power generator register name ad dress bit name function setting init. r/w remarks v d1 control register (vd1_ctl) 0x5120 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5 hvld v d1 hea vy load protection mode 1 on 0 off 0 r/w d4C0 C reser v ed C C C 0 when being read. 0x506e, 0x5180C0x5182 sound generator register name ad dress bit name function setting init. r/w remarks snd clock control register (snd_clk) 0x506e (8 bits) d7C1 C reser v ed C C C 0 when being read. d0 sndclke snd cloc k enab le 1 enab le 0 disab le 0 r/w snd control register (snd_ctl) 0x5180 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 bztm[1:0] buzz er en v elope time/one-shot output time select bztm[1:0] time 0x0 r/w 0x3 0x2 0x1 0x0 125 ms 62.5 ms 31.25 ms 15.63 ms d3C2 bzmd[1:0] buzz er mode select bzmd[1:0] mode 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed en v elope one-shot nor mal d1 C reser v ed C C C 0 when being read. d0 bzen buzz er output control 1 on/t r igger 0 off 0 r/w buzzer frequency control register (snd_bzfq) 0x5181 (8 bits) d7C3 C reser v ed C C C 0 when being read. d2C0 bzfq[2:0] buzz er frequency select bzfq[2:0] f requency 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 1170.3 hz 1365.3 hz 1638.4 hz 2048.0 hz 2340.6 hz 2730.7 hz 3276.8 hz 4096.0 hz
appendix a list of i/o registers s1c17651 t echnical m anual seiko epson corporation ap-a-9 register name ad dress bit name function setting init. r/w remarks buzzer duty ratio control register (snd_bzdt) 0x5182 (8 bits) d7C3 C reser v ed C C C 0 when being read. d2C0 bzdt[2:0] buzz er duty r atio select bzdt[2:0] duty (v olume) 0x0 r/w 0x7 : 0x0 le v el 8 (min.) : le v el 1 (max.) 0x5200C0x52a2 p port & port mux register name ad dress bit name function setting init. r/w remarks p0 port input data register (p0_in) 0x5200 (8 bits) d7C0 p0in[7:0] p0[7:0] por t input data 1 1 (h) 0 0 (l) r p0 port output data register (p0_out) 0x5201 (8 bits) d7C0 p0out[7:0] p0[7:0] por t output data 1 1 (h) 0 0 (l) 0 r/w p0 port output enable register (p0_oen) 0x5202 (8 bits) d7C0 p0oen[7:0] p0[7:0] por t output enab le 1 enab le 0 disab le 0 r/w p0 port pull-up control register (p0_pu) 0x5203 (8 bits) d7C0 p0pu[7:0] p0[7:0] por t pull-up enab le 1 enab le 0 disab le 1 (0xff) r/w p0 port interrupt mask register (p0_imsk) 0x5205 (8 bits) d7C0 p0ie[7:0] p0[7:0] por t interr upt enab le 1 enab le 0 disab le 0 r/w p0 port interrupt edge select register (p0_edge) 0x5206 (8 bits) d7C0 p0edge[7:0] p0[7:0] por t interr upt edge select 1 f alling edge 0 rising edge 0 r/w p0 port interrupt flag register (p0_iflg) 0x5207 (8 bits) d7C0 p0if[7:0] p0[7:0] por t interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. p0 port chattering filter control register (p0_chat) 0x5208 (8 bits) d7 C reser v ed C C C 0 when being read. d6C4 p0cf2[2:0] p0[7:4] chatter ing filter time p0cf2[2:0] filter time 0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 16384/f pclk 8192/f pclk 4096/f pclk 2048/f pclk 1024/f pclk 512/f pclk 256/f pclk none 0x0 r/w d3 C reser v ed C C C 0 when being read. d2C0 p0cf1[2:0] p0[3:0] chatter ing filter time p0cf1[2:0] filter time 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 16384/f pclk 8192/f pclk 4096/f pclk 2048/f pclk 1024/f pclk 512/f pclk 256/f pclk none p0 port key- entry reset configuration register (p0_krst) 0x5209 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 p0krst[1:0] p0 por t k e y-entr y reset configur ation p0krst[1:0] configur ation 0x0 r/w 0x3 0x2 0x1 0x0 p0[3:0] = 0 p0[2:0] = 0 p0[1:0] = 0 disab le p0 port input enable register (p0_ien) 0x520a (8 bits) d7C0 p0ien[7:0] p0[7:0] por t input enab le 1 enab le 0 disab le 1 (0xff) r/w p1 port input data register (p1_in) 0x5210 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C0 p1in[3:0] p1[3:0] por t input data 1 1 (h) 0 0 (l) r p1 port output data register (p1_out) 0x5211 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C0 p1out[3:0] p1[3:0] por t output data 1 1 (h) 0 0 (l) 0 r/w p1 port output enable register (p1_oen) 0x5212 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C0 p1oen[3:0] p1[3:0] por t output enab le 1 enab le 0 disab le 0 r/w
appendix a list of i/o registers ap-a-10 seiko epson corporation s1c17651 t echnical m anual register name ad dress bit name function setting init. r/w remarks p1 port pull-up control register (p1_pu) 0x5213 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C0 p1pu[3:0] p1[3:0] por t pull-up enab le 1 enab le 0 disab le 1 (0xf) r/w p1 port input enable register (p1_ien) 0x521a (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C0 p1ien[3:0] p1[3:0] por t input enab le 1 enab le 0 disab le 1 (0xf) r/w p0[3:0] port function select register (p00_03pmux) 0x52a0 (8 bits) d7C6 p03mux[1:0] p03 por t function select p03mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 lfr o regmon excl0 p03 d5C4 p02mux[1:0] p02 por t function select p02mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 regmon fout a sclk0 p02 d3C2 p01mux[1:0] p01 por t function select p01mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed sout0 p01 d1C0 p00mux[1:0] p00 por t function select p00mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed sin0 p00 p0[7:4] port function select register (p04_07pmux) 0x52a1 (8 bits) d7C6 p07mux[1:0] p07 por t function select p07mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed sdo0 #bz p07 d5C4 p06mux[1:0] p06 por t function select p06mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed sdi0 bz p06 d3C2 p05mux[1:0] p05 por t function select p05mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed #spiss0 t outb0/capb0 p05 d1C0 p04mux[1:0] p04 por t function select p04mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed t out a0/cap a0 p04 p1[3:0] port function select register (p10_13pmux) 0x52a2 (8 bits) d7C6 p13mux[1:0] p13 por t function select p13mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed p13 dst2 d5C4 p12mux[1:0] p12 por t function select p12mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed #bz p12 dsio d3C2 p11mux[1:0] p11 por t function select p11mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed bz p11 dclk d1C0 p10mux[1:0] p10 por t function select p10mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed spiclk0 foutb p10 0x4020, 0x5322C0x532c misc registers register name ad dress bit name function setting init. r/w remarks debug mode control register 1 (misc_dmode1) 0x4020 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1 dbrun1 run/stop select in deb ug mode 1 run 0 stop 0 r/w d0 C reser v ed C C C 0 when being read.
appendix a list of i/o registers s1c17651 t echnical m anual seiko epson corporation ap-a-11 register name ad dress bit name function setting init. r/w remarks debug mode control register 2 (misc_dmode2) 0x5322 (16 bits) d15C1 C reser v ed C C C 0 when being read. d0 dbrun2 run/stop select in deb ug mode (e xcept pclk per ipher al circuits) 1 run 0 stop 0 r/w misc protect register (misc_prot) 0x5324 (16 bits) d15C0 prot[15:0] misc register wr ite protect wr iting 0x96 remo v es the wr ite protection of the misc regis- ters (0x5326C0x532a). wr iting another v alue set the wr ite protection. 0x0 r/w iram size select register (misc_iramsz) 0x5326 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 dbadr deb ug base address select 1 0x0 0 0xfffc00 0 r/w d7 C reser v ed C C C 0 when being read. d6C4 iramactsz [2:0] iram actual siz e 0x3 (= 2kb) 0x3 r d3 C reser v ed C C C 0 when being read. d2C0 iramsz[2:0] iram siz e select iramsz[2:0] siz e 0x3 r/w 0x5 0x4 0x3 other 512b 1kb 2kb reser v ed vector table address low register (misc_ttbrl) 0x5328 (16 bits) d15C8 ttbr[15:8] v ector tab le base address a[15:8] 0x0C0xff 0x80 r/w d7C0 ttbr[7:0] v ector tab le base address a[7:0] (fix ed at 0) 0x0 0x0 r vector table address high register (misc_ttbrh) 0x532a (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 ttbr[23:16] v ector tab le base address a[23:16] 0x0C0xff 0x0 r/w psr register (misc_psr) 0x532c (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C5 psril[2:0] psr interr upt le v el (il) bits 0x0 to 0x7 0x0 r d4 psrie psr interr upt enab le (ie) bit 1 1 (enab le) 0 0 (disab le) 0 r d3 psrc psr carr y (c) flag 1 1 (set) 0 0 (cleared) 0 r d2 psrv psr o v erflo w (v) flag 1 1 (set) 0 0 (cleared) 0 r d1 psrz psr z ero (z) flag 1 1 (set) 0 0 (cleared) 0 r d0 psrn psr negativ e (n) flag 1 1 (set) 0 0 (cleared) 0 r 0x5068, 0x5400C0x540c 16-bit pwm timer ch.0 register name ad dress bit name function setting init. r/w remarks t16a clock control register ch.0 (t16a_clk0) 0x5068 (8 bits) d7C4 t16aclkd [3:0] cloc k division r atio select t16a clkd[3:0] division r atio 0x0 r/w f256: regulated 256 hz cloc k osc3a or osc3b osc1 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 C 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 C C C C C C f256 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 d3C2 t16aclk src[1:0] cloc k source select t16a clksrc [1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 exter nal cloc k osc3a osc1 osc3b d1 C reser v ed C C C 0 when being read. d0 t16aclke count cloc k enab le 1 enab le 0 disab le 0 r/w t16a counter ch.0 control register (t16a_ctl0) 0x5400 (16 bits) d15C7 C reser v ed C C C 0 when being read. d6 hcm half cloc k mode enab le 1 enab le 0 disab le 0 r/w d5C4 C reser v ed C C C 0 when being read. d3 cbufen compare b uff er enab le 1 enab le 0 disab le 0 r/w d2 trmd count mode select 1 one-shot 0 repeat 0 r/w d1 preset counter reset 1 reset 0 ignored 0 w 0 when being read. d0 prun counter r un/stop control 1 run 0 stop 0 r/w
appendix a list of i/o registers ap-a-12 seiko epson corporation s1c17651 t echnical m anual register name ad dress bit name function setting init. r/w remarks t16a counter ch.0 data register (t16a_tc0) 0x5402 (16 bits) d15C0 t16atc [15:0] counter data t16a tc15 = msb t16a tc0 = lsb 0x0 to 0xffff 0x0 r t16a comparator/ capture ch.0 control register (t16a_ccctl 0 ) 0x5404 (16 bits) d15C14 capbtrg [1:0] capture b tr igger select capbtrg[1:0] t r igger edge 0x0 r/w 0x3 0x2 0x1 0x0 and none d13C12 toutbmd [1:0] t out b mode select t outbmd[1:0] mode 0x0 r/w 0x3 0x2 0x1 0x0 cmp b: or cmp a: or cmp a: , b: off d11C10 C reser v ed C C C 0 when being read. d9 toutbinv t out b in v er t 1 in v er t 0 nor mal 0 r/w d8 ccbmd t16a_ccb register mode select 1 capture 0 compar ator 0 r/w d7C6 capatrg [1:0] capture a tr igger select cap a trg[1:0] t r igger edge 0x0 r/w 0x3 0x2 0x 1 0x0 and none d5C4 toutamd [1:0] t out a mode select t out amd[1:0] mode 0x0 r/w 0x3 0x2 0x1 0x0 cmp b: or cmp a: or cmp a: , b: off d3C2 C reser v ed C C C 0 when being read. d1 toutainv t out a in v er t 1 in v er t 0 nor mal 0 r/w d0 ccamd t16a_cca register mode select 1 capture 0 compar ator 0 r/w t16a comparator/ capture ch.0 a data register (t16a_cca0) 0x5406 (16 bits) d15C0 cca[15:0] compare/capture a data cca15 = msb cca0 = lsb 0x0 to 0xffff 0x0 r/w t16a comparator/ capture ch.0 b data register (t16a_ccb0) 0x5408 (16 bits) d15C0 ccb[15:0] compare/capture b data ccb15 = msb ccb0 = lsb 0x0 to 0xffff 0x0 r/w t16a comparator/ capture ch.0 interrupt enable register (t16a_ien0) 0x540a (16 bits) d15C6 C reser v ed C C C 0 when being read. d5 capbowie capture b o v erwr ite interr upt enab le 1 enab le 0 disab le 0 r/w d4 capaowie capture a o v erwr ite interr upt enab le 1 enab le 0 disab le 0 r/w d3 capbie capture b interr upt enab le 1 enab le 0 disab le 0 r/w d2 capaie capture a interr upt enab le 1 enab le 0 disab le 0 r/w d1 cbie compare b interr upt enab le 1 enab le 0 disab le 0 r/w d0 caie compare a interr upt enab le 1 enab le 0 disab le 0 r/w t16a comparator/ capture ch.0 interrupt flag register (t16a_iflg0) 0x540c (16 bits) d15C6 C reser v ed C C C 0 when being read. d5 capbowif capture b o v erwr ite interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d4 capaowif capture a o v erwr ite interr upt flag 0 r/w d3 capbif capture b interr upt flag 0 r/w d2 capaif capture a interr upt flag 0 r/w d1 cbif compare b interr upt flag 0 r/w d0 caif compare a interr upt flag 0 r/w 0x54b0 flash controller register name ad dress bit name function setting init. r/w remarks flashc read wait control register (flashc_ wait) 0x54b0 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7 C reser v ed C x C x when being read. d6-2 C reser v ed C C C 0 when being read. d1C0 rdwait [1:0] flash read w ait cycle rd w ait[1:0] w ait 0x3 r/w 0x3 0x2 0x1 0x0 3 w ait 2 w ait 1 w ait no w ait 0x56c0C0x56c8 real-time clock register name ad dress bit name function setting init. r/w remarks rtc control register (rtc_ctl) 0x56c0 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 rtcst r tc r un/stop status 1 running 0 stop 0 r d7C6 C reser v ed C C C 0 when being read. d5 bcdmd bcd mode select 1 bcd mode 0 b i n a r y m o d e 0 r/w d4 rtc24h 24h/12h mode select 1 12h 0 24h 0 r/w d3C1 C reser v ed C C C 0 when being read. d0 rtcrun r tc r un/stop control 1 run 0 stop 0 r/w
appendix a list of i/o registers s1c17651 t echnical m anual seiko epson corporation ap-a-13 register name ad dress bit name function setting init. r/w remarks rtc interrupt enable register (rtc_ien) 0x56c2 (16 bits) d15C10 C reser v ed C C C 0 when being read. d9 int1den 1-da y interr upt enab le 1 enab le 0 disab le 0 r/w d8 inthden half-da y interr upt enab le 1 enab le 0 disab le 0 r/w d7 int1hen 1-hour interr upt enab le 1 enab le 0 disab le 0 r/w d6 int10men 10-min ute interr upt enab le 1 enab le 0 disab le 0 r/w d5 int1men 1-min ute interr upt enab le 1 enab le 0 disab le 0 r/w d4 int10sen 10-second interr upt enab le 1 enab le 0 disab le 0 r/w d3 int1hzen 1 hz interr upt enab le 1 enab le 0 disab le 0 r/w d2 int4hzen 4 hz interr upt enab le 1 enab le 0 disab le 0 r/w d1 int8hzen 8 hz interr upt enab le 1 enab le 0 disab le 0 r/w d0 int32hzen 32 hz interr upt enab le 1 enab le 0 disab le 0 r/w rtc interrupt flag register (rtc_iflg) 0x56c4 (16 bits) d15C10 C reser v ed C C C 0 when being read. d9 int1d 1-da y interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d8 inthd half-da y interr upt flag 0 r/w d7 int1h 1-hour interr upt flag 0 r/w d6 int10m 10-min ute interr upt flag 0 r/w d5 int1m 1-min ute interr upt flag 0 r/w d4 int10s 10-second interr upt flag 0 r/w d3 int1hz 1 hz interr upt flag 0 r/w d2 int4hz 4 hz interr upt flag 0 r/w d1 int8hz 8 hz interr upt flag 0 r/w d0 int32hz 32 hz interr up t flag 0 r/w rtc minute/second counter register (rtc_ms) 0x56c6 (16 bits) d15 C reser v ed C C C 0 when being read. d14C8 rtcmin [6:0] min ute counter 0x0 to 0x3b (binar y mode) 0x00 to 0x59 (bcd mode) x r/w d7 C reser v ed C C C 0 when being read. d6C0 rtcsec [6:0] second counter 0x0 to 0x3b (binar y mode) 0x00 to 0x59 (bcd mode) x r/w rtc hour counter register (rtc_h) 0x56c8 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7 ampm am/pm 1 pm 0 am x r/w d6 C reser v ed C C C 0 when being read. d5C0 rtchour [5:0] hour counter 0x0 to 0x17 (binar y mode) 0x00 to 0x23 (bcd mode) x r/w 0xffff84C0xffffd0 s1c17 core i/o register name ad dress bit name function setting init. r/w remarks processor id register (idir) 0xffff84 (8 bits) d7C0 idir[7:0] processor id 0x10: s1c17 core 0x10 0x10 r debug ram base register (dbram) 0xffff90 (32 bits) d31C24 C un used (fix ed at 0) 0x0 0x0 r d23C0 dbram[23:0] deb ug ram base address 0x7c0 0x7c0 r debug control register (dcr) 0xffffa0 (8 bits) d7 ibe4 instr uction break #4 enab le 1 enab le 0 disab le 0 r/w d6 ibe3 instr uction break #3 enab le 1 enab le 0 disab le 0 r/w d5 ibe2 instr uction break #2 enab le 1 enab le 0 disab le 0 r/w d4 dr deb ug request flag 1 occurred 0 n o t o c c u r r e d 0 r/w reset b y wr iting 1. d3 ibe1 instr uction break #1 enab le 1 enab le 0 disab le 0 r/w d2 ibe0 instr uction break #0 enab le 1 enab le 0 disab le 0 r/w d1 se single step enab le 1 enab le 0 disab le 0 r/w d0 dm deb ug mode 1 d e b u g m o d e 0 user mode 0 r instruction break address register 1 (ibar1) 0xffffb4 (32 bits) d31C24 C reser v ed C C C 0 when being read. d23C0 ibar1[23:0] instr uction break address #1 ibar123 = msb ibar10 = lsb 0x0 to 0xffffff 0x0 r/w instruction break address register 2 (ibar2) 0xffffb8 (32 bits) d31C24 C reser v ed C C C 0 when being read. d23C0 ibar2[23:0] instr uction break address #2 ibar223 = msb ibar20 = lsb 0x0 to 0xffffff 0x0 r/w instruction break address register 3 (ibar3) 0xffffbc (32 bits) d31C24 C reser v ed C C C 0 when being read. d23C0 ibar3[23:0] instr uction break address #3 ibar323 = msb ibar30 = lsb 0x0 to 0xffffff 0x0 r/w instruction break address register 4 (ibar4) 0xffffd0 (32 bits) d31C24 C reser v ed C C C 0 when being read. d23C0 ibar4[23:0] instr uction break address #4 ibar423 = msb ibar40 = lsb 0x0 to 0xffffff 0x0 r/w
appendix b po wer sa ving s1c17651 t echnical m anual seiko epson corporation ap-b-1 a ppendix b p o wer sa ving c u r r e n t c o n s u m p t i o n w i l l v a r y d r a m a t i c a l l y , d e p e n d i n g o n c p u o p e r a t i n g m o d e , o p e r a t i o n c l o c k f r e q u e n c y , a n d t h e peripheral circuits being operated. listed belo w are the control methods for sa ving po wer . cloc k contr ol p o wer sa ving b.1 this section describes clock systems that can be controlled via softw are and po wer -sa ving control details. f or more information on control re gi sters and control methods, refer to the respecti v e module sections. system sleep ? ex ecute the slp instruction (when r tc is stopped) w h e n t h e e n t i r e s y s t e m c a n b e s t o p p e d , s t o p t h e r t c a n d e x e c u t e t h e slp i n s t r u c t i o n . t h e c p u e n t e r s s l e e p m o d e a n d t h e o s c1/ o s c3a / o s c3b c l o c k s s t o p . t h i s a l s o s t o p s a l l p e r i p h e r a l c i r c u i t s u s i n g t h e osc1/osc3a/osc3b clocks. starting up the cpu from sleep mode is therefore limited to startup using a port (described later). ? ex ecute the slp instruction (when r tc is running) when the system e xcept the r tc for time k eeping can be stopped, maintain the r tc in running state and e x- ecute the slp instruction. the cpu enters sleep mode and the osc3a /osc3b clocks stop. this also stops all peripheral circuits using the osc3a/osc3b clocks. starting up the cpu from sleep mode is th erefore limited to startup using a port or r tc (described later). system c loc ks ? select a lo w-speed clock source (clg module) select a lo w-speed oscillator for the system clock source. y ou can reduce current consumption by selecting the osc1 clock when lo w-speed processing is possible. ? disable unnecessary oscillator circuits (clg module) operate the oscillator comprising the system clock source. w here possible, stop the other oscillators. y ou can reduce current consumption by using osc1 as the system clock and disable the osc3b and osc3a oscilla- tors. cpu c loc k (cclk) ? ex ecute the halt instruction ex ecute the halt instruction when program e x ecution by the cpu is not required, for e xample, when the system is w aiting for an interrupt. the cpu enters hal t mode and suspends operations, b ut the periphe ral circuits maintain the status in place at the time of the halt instruction, enabling use of peripheral circuits for generating interrupts and the lcd dri v er . y ou can reduce po wer consumption e v en further by suspending un- necessary oscillator and peripheral circuits before e x ecuting the halt instruction. the cpu is started from hal t mode by an interrupt from a port or the peripheral circuit operating in hal t mode. ? select a lo w-speed clock gear (clg module) th e cl g mo du le c an r e du ce c pu c loc k sp e ed s to be tw ee n 1/ 1 an d 1/ 8 of t he s ys te m c loc k vi a th e cl oc k ge a r settings. y ou can reduce current consumption by operating the cpu at the minimum speed required for the application. regulated c loc k (f256) ? use an interrupt from a peripheral timer module that runs with the re gulated clock (f256) to e x ec ute theoreti- cal re gulation. an interrupt from the timer that runs all the time should be used to reduce current consump- tion. p eripheral c loc k (pclk) ? stop pclk (clg module) s t o p t h e p c l k c l o c k s u p p l i e d f r o m t h e c l g t o p e r i p h e r a l c i r c u i t s i f n o n e o f t h e f o l l o w i n g p e r i p h e r a l c i r c u i t s is required.
appendix b po wer sa ving ap-b-2 seiko epson corporation s1c17651 t echnical m anual peripheral circuits that use pclk ? interrupt controller ? 8-bit timer ch.0 ? spi ch.0 ? po wer generator ? p ports and port mux (control re gisters, chattering f ilters) ? misc re gisters pclk is not required for the peripheral modules/functions sho wn belo w . peripheral circuits/functions that do not use pclk ? real-time clock ? clock timer ? w atchdog timer ? lcd dri v er ? sound generator ? svd circui t ? 16-bit pwm timer ch.0 ? u ar t ch.0 ? fout a/foutb outputs t able b.1.1 sho ws a list of methods for clock control and starting/stopping the cpu. 1.1 cloc k control list t ab le b . current consumption osc1 osc3b/ osc3a cpu (cclk) pclk peripheral r tc osc1 peripheral cpu stop method cpu star tup method lo w stop stop stop stop stop stop ex ecute slp instr uction 1 oscillation (f or r tc) stop stop stop run stop ex ecute slp instr uction 1, 2 oscillation (f or r tc) stop stop stop run stop ex ecute halt instr uction 1, 2 oscillation (system clk) stop stop stop run run ex ecute halt instr uction 1, 2, 3 oscillation (system clk) stop stop run run run ex ecute halt ins tr uction 1, 2, 3, 4 oscillation (system clk) stop run (1/1) run run run oscillation oscillation (system clk) stop run run run ex ecute halt instr uction 1, 2, 3, 4 oscillation oscillation (system clk) run (lo w gear) run run run high oscillation oscillation (system clk) run (1/1) run run run hal t and sleep mode cancelation methods (cpu star tup method) 1. star tup b y por t star ted up b y an i/o por t interr upt or a deb ug interr upt (icd f orced b reak). 2. star tup b y r tc star ted up b y an r tc interr upt. 3. star tup b y osc1 per ipher al circuit star ted up b y a cloc k timer or w atchdog timer interr upt. 4. star tup b y pclk per ipher al circuit star ted up b y a pclk per ipher al circuit interr upt.
appendix b po wer sa ving s1c17651 t echnical m anual seiko epson corporation ap-b-3 reducing p o wer consumption via p o wer suppl y contr ol b.2 the a v ailable po wer supply controls are listed belo w . v d1 /v osc regulator s ? note that turning on internal v oltage re gulator hea vy load protection will increase current consumption. t urn of f hea vy load protection for normal operations. t urn on only if operations are unstable. lcd po wer suppl y cir cuit ? setting vcsel to 0 (v c1 reference v oltage) wi ll increase current consumption. set vcsel to 1 (v c2 reference v oltage) if the po wer supply v oltage v dd is 2.2 v or higher . ? t urning on the lcd po wer supply hea vy load protection will increase current consumption. t urn of f hea vy load protection for normal operations. t urn on only if the display is unstable. p o wer suppl y v olta g e detection (svd) cir cuit ? operating the svd circuit will increase curren t consumption. t urn of f po wer supply v oltage detection unless it is required. other p o wer sa ving methods b.3 theoretical regulation ? when data input from the i/o port is used to set the theoretical re gulation v alue re gister (tr_v al), place the port into output mode and set the read data as the output data after data is read. this reduces the pull-up resistor current that constantly flo ws.
appendix c mounting preca utions s1c17651 t echnical m anual seiko epson corporation ap-c-1 a ppendix c mounting pr ecautions this section describes v arious precautions for circuit board design and ic mounting. oscillator cir cuit ? oscillation characteristics depend on f actors such as components used (resonator , c g , c d ) and circuit board patterns. in particular , with ceramic or crystal resonators, select the appropriate capacitors (c g , c d ) only af- ter fully e v aluating components actually mounted on the circuit board. ? oscillator clock disturbances caused by noise may cause malfunctions. t o pre v ent such disturbances, consid- er the follo wing points. the latest de vices, in particular , are manuf actured by microscopic processes, making them especially susceptible to noise. a r e a s i n w h i c h n o i s e c o u n t e r m e a s u r e s a r e e s p e c i a l l y i m p o r t a n t i n c l u d e t h e o s c2 p i n a n d r e l a t e d c i r c u i t c o m p o n e n t s a n d w i r i n g . o s c1 p i n h a n d l i n g i s e q u a l l y i m p o r t a n t . t h e n o i s e p r e c a u t i o n s r e q u i r e d f o r t h e osc1 and osc2 pins are described belo w . w e also recommend applying similar noise countermeasures to the high-speed oscillator circuit, such as the osc3 and osc4 pins and wiring. (1) c o m p o n e n t s s u c h a s a r e s o n a t o r , r e s i s t o r s , a n d c a p a c i t o r s c o n n e c t e d t o t h e o s c 1 ( o s c 3 ) a n d o s c 2 ( o s c 4 ) pins should ha v e the shor test connections possible. (2) where v er possible, a v oid locating digital signal lines within 3 mm of the osc1 (osc3) and osc2 (osc4) pins or related circuit components and wiring. rapidly-switching signals, in particular , should be k ept at a distance from these components. since the spacing between layers of multi-layer printed circuit boards is a mere 0.1 mm to 0.2 mm, the abo v e precautions also a pply when positioning digital signal lines on other layers. ne v er place digital signal lines alongside such components or wiring, e v en if more than 3 mm distance or located on other layers. a v oid crossing wires. (3) u s e v s s t o s h i e l d o s c 1 ( o s c 3 ) a n d o s c 2 ( o s c 4 ) p i n s a n d r e l a t e d w i r i n g ( i n c l u d i n g w i r i n g f o r a d j a c e n t c i r c u i t b o a r d l a y e r s ) . l a y e r s w i r e d s h o u l d b e a d e q u a t e l y s h i e l d e d a s s h o w n t o t h e r i g h t . f u l l y g r o u n d a d j a c e n t l a y - ers, where possible. at minimum, shield the area at least 5 mm around the abo v e pins and wiring. ev en after implementing these precautions, a v oid conf iguring digital signal lines in parallel, as described in (2) abo v e. a v oid crossing e v en on discrete layers, e xcept for lines carrying signals with lo w switching frequencies. (4) after implementing these precautions, che ck the output clock w a v eform by running the actual application program within the product. use an oscilloscope to check the fout a or foutb pin output. y ou can check the quality of the osc3 output w a v eform via the fout a/b output. conf irm that the fre- quenc y is as designed, is free of noise, and has minimal jitter . y ou can check the quality of the osc1 w a v eform via the fout a/b output. in particula r , enlar ge the areas before and after the clock rising and f alling edges and tak e special care to conf irm that the re gions approxi- mately 100 ns to either side are free of clock or spiking noise. f ailure to observ e precautions (1) to (3) adequately may lead to jitter in the osc3 output and noise in the osc1 output. jitter in the osc3 output will reduce operating frequencies, while noise in the osc 1 output will destabilize timers operated by the osc1 clock as well as cpu core operations when the system clock switches to osc1. reset cir cuit ? the reset signal input to the #reset pin when po wer is turned on will v ary , depending on v arious f actors, such as po wer supply start-up time, components used, and circuit board patterns. constants such as capaci- tance and resistance should be determined t hrough testing with real-w orld products. ? components such as capacitors and resistors connected to the #reset pin should ha v e the shortest connec- tions possible to pre v ent noise-induced resets. osc4 osc3 v ss sample v ss pattern (osc3)
appendix c mounting preca utions ap-c-2 seiko epson corporation s1c17651 t echnical m anual p o wer suppl y cir cuit sudden po wer supply fluctuations due to noise will cause malfunctions. consider the follo wing issues. (1) connections from the po wer supply to the v dd and v ss pins should be implemented via the shortest, thick- est patterns possible. (2) if a bypass capacitor is connected between v dd and v ss , connections between the v dd and v ss pins should be as short as possible. v dd v ss bypass capacitor connection example v dd v ss signal line location ? t o pre v ent electromagnetically-induced noise arising from mutual induction, lar ge-current signal lines should not be positioned close to circuits susceptible to noise, such as oscillators. ? locating signal lines in parallel o v er signif icant distances or crossing signal lines operating at high speed will cause malfunctions due to noise generated by mutual interference. specif i cally , a v oid positioning crossing signal lines operating at high speed close to circuits susceptible to noise, such as oscillators. osc1, osc3 osc2, osc4 v ss large current signal line high-speed signal line prohibited pattern handling of light (f or bare c hip mounting) the characteristics of semiconductor components can v ary when e xposed to light. ics may malfunction or non- v olatile memory data may be corrupted if ics are e xposed to light. consider the follo wing precautions for circuit boards and products in which this ic is mounted to pre v ent ic malfunctions attrib utable to light e xposure. (1) design and mount the produ ct so that the ic is shielded from light during use. (2) shield the ic from light during inspection processes. (3) shield the ic on the upper , underside, and side f aces of the ic chip. (4) mount the ic chip within one week of opening the package. if the ic chip must be stored before mounting, tak e measures to ensure light shielding. (5) adequate e v aluations are required to assess non v olatile memory da ta retention characteristics before prod- uct deli v ery if the product is subjected to heat stress e xceeding re gular reflo w conditions during mounting processes.
appendix c mounting preca utions s1c17651 t echnical m anual seiko epson corporation ap-c-3 un used pins (1) i/o port (p) pins unused pins should be left open. the control re gisters should be f ix ed at the initial status (input with pull- up enabled). (2) osc1, osc2, osc3, and osc4 pins if the osc1a or osc3a oscillator circuit is not used, the osc1 and osc2 pins or the osc3 and osc4 pins should be left open. the control re gisters should be f ix ed at the initial status (oscillation disabled). (3) v c1C3 , ca, cb, segx, and comx pins if the lcd dri v er is not used, these pins should be left open. the control re gisters should be f ix ed at the initial status (display of f). the unused segx pins that are not required to connect should be left open e v en if the lcd dri v er is used. miscellaneous this product series is manuf actured using microscopic processes. although it is designed to ensure basi c ic reliability meeting eiaj and mil standards, minor v ariations o v er time may result in electrical damage arising from disturbances in the form of v oltages e xceeding the absolute maximum rating when mounting the product in addition to ph ysical damage. the follo wing f actors can gi v e rise to these v ariations: (1) electromagnetically-induced noise from industrial po wer supplies used in mounting refl o w , re w orking after mounting, and indi vidual characteristic e v aluation (testing) processes (2) electromagnetically-induced noise from a solder iron when soldering in particular , during soldering, tak e care to ensure that the soldering iron gnd (tip potential) has the same po- tential as the ic gnd.
appendix d measures a gainst noise s1c17651 t echnical m anual seiko epson corporation ap-d-1 a ppendix d measur es against noise t o impro v e noise immunity , tak e measures ag ainst noise as follo ws: noise measures f or v dd and v ss p o wer suppl y pins the ic will malfunction at the instant when noise f alling belo w the rated v oltage is input. t ak e measures on the circuit board, including close patterns for circuit board po wer supply circuits, noise-f iltering decoupling capaci- tors, and sur ge/nois e pre v ention components on the po wer supply line. f or the recommended patterns on the circuit board, see mounting precautions in appendix. noise measures f or #reset pin the pull-up resistor for the #reset pin included in this product has a relati v ely high impedance of 100 kw to 500 kw and is not noise-resistant. extraneous noise may pull the #reset pin do wn to a lo w le v el and this will cause the ic to reset. therefore, the circuit board must be designed properly taking noise measures into consid- eration. f or the recommended patterns on the circuit board, see mounting precautions in appendix. noise measures f or oscillator pins the oscillator input pins must pass a signal of small amplitude, so the y are h ypersensiti v e to noise. therefore, the circuit board must be designed properly taking noise measures into consideration. f or the recommended patterns on the circuit board, see mounting precautions in appendix. noise measures f or deb ug pins this product pro vides the input/output pins (dclk, dst2, and dsio) to connect icdmini (s5u1c17001h) for deb ugging. if noise is input to these pins, the s1c17 core may enter deb ug mode. t o pre v ent une xpected transitions to deb ug mode caused by e x traneous noise, switch the dclk, dst2, and dsio pins to general- purpose i/o port pins within the initialization routine when the deb ug functions are not used. f or details of the pin functions and the function switch control, see the i/o ports (p) chapter . note: do not perf or m the function s witching sho wn abo v e when the application is under de v elopment, a s t h e d e b u g f u n c t i o n s m u s t b e u s e d . t h e d e b u g g i n g c a n n o t b e p e r f o r m e d a f t e r t h e p i n f u n c t i o n i s s witched. the abo v e processing m ust be added after the application de v elopment has completed and deb ugging is no longer necessar y . the dsio pin should be pulled up with a 10 kw resistor when using the deb ug pin functions. the pull-up resis- tor for the dsio pin included in this product has a relati v ely high impedance of 100 kw to 500 kw and is not n oise-resistant. noise measures f or interrupt input pins this product is able to generate a port input interrupt when the input signal changes. the interrupt is generated when an input signal edge is detected, therefore, an interrupt may occur if the signal changes due to e xtraneous noise. t o pre v ent occurrence of une xpected interrupts due to e xtraneous noise, enable the chattering f ilter circuit wh en using the port input interrupt. f or details of the port input interrupt and chattering f ilter circuit, see the i/o ports (p) chapter .
appendix d measures a gainst noise ap-d-2 seiko epson corporation s1c17651 t echnical m anual noise measures f or u ar t pins this product includes a u ar t module for asynchronous communications. the u ar t starts recei v e operation when it detects a lo w le v el input from the sinx pin. therefore, a recei v e operation may be started if the sinx pin is set to lo w due to e xtraneous noise. in this case, a recei v e error will occur or in v alid data will be recei v ed. t o pre v ent u ar t from malfunction cau sed by e xtraneous noise, tak e the follo wing measures: ? stop the u ar t operations (rxen/u ar t_ctlx re gister = 0) while asynchronous communication is not per - formed. ? ex ecute the resending process via softw are after e x ecuting the recei v e error handler with a parity check. f or details of the pin functions and the function switch control, see the i/o ports (p) chapter . f or the u ar t control and details of recei v e errors, see the u ar t chapter .
appendix e initializa tion r outine s1c17651 t echnical m anual seiko epson corporation ap-e-1 a ppendix e initialization routine the follo wing lists typical v ector tables and initialization routines: boot.s .org 0x8000 .section .rodata ...(1) ; ====================================================================== ; vector table ; ====================================================================== ; interrupt vector interrupt ; number offset source .long boot ; 0x00 0x00 reset ...(2) .long unalign_handler ; 0x01 0x04 unalign .long nmi_handler ; 0x02 0x08 nmi .long int03_handler ; 0x03 0x0c - .long p0_handler ; 0x04 0x10 p0 port .long int05_handler ; 0x05 0x14 - .long int06_handler ; 0x06 0x18 - .long ct_handler ; 0x07 0x1c ct .long rtc_handler ; 0x08 0x20 rtc .long int09_handler ; 0x09 0x24 - .long lcd_handler ; 0x0a 0x28 lcd .long t16a2_0_handler ; 0x0b 0x2c t16a2 ch0 .long int0c_handler ; 0x0c 0x30 - .long int0d_handler ; 0x0d 0x34 - .long t8_0_handler ; 0x0e 0x38 t8 ch0 .long int0f_handler ; 0x0f 0x3c - .long uart_0_handler ; 0x10 0x40 uart ch0 .long int11_handler ; 0x11 0x44 - .long spi_0_handler ; 0x12 0x48 spi ch0 .long int13_handler ; 0x13 0x4c - .long int14_handler ; 0x14 0x50 - .long int15_handler ; 0x15 0x54 - .long int16_handler ; 0x16 0x58 - .long int17_handler ; 0x17 0x5c - .long int18_handler ; 0x18 0x60 - .long int19_handler ; 0x19 0x64 - .long int1a_handler ; 0x1a 0x68 - .long int1b_handler ; 0x1b 0x6c - .long int1c_handler ; 0x1c 0x70 - .long int1d_handler ; 0x1d 0x74 - .long int1e_handler ; 0x1e 0x78 - .long int1f_handler ; 0x1f 0x7c - ; ====================================================================== ; program code ; ====================================================================== .text ...(3) .align 1 boot: ; ===== initialize =========================================== ; ----- stack pointer -------------------- xld.a %sp, 0x07c0 ...(4) ; ----- memory controller ---------------- xld.a %r1, 0x54b0 ; flashc register address ; flash read wait cycle xld.a %r0, 0x00 ; no wait ld.b [%r1], %r0 ; [0x54b0] <= 0x00 ...(5) ; ===== main routine ========================================= ...
appendix e initializa tion r outine ap-e-2 seiko epson corporation s1c17651 t echnical m anual ; ====================================================================== ; interrupt handler ; ====================================================================== ; ----- address unalign -------------------------- unalign_handler: ... ; ----- nmi ------------------------------------- nmi_handler: ... (1) a .rodata section is declared to locate the v ector table in the .vector section. (2) interrupt handler routine addresses are def ined as v ectors. intxx_handler can be used for softw are interrupts. (3) the program code is written in the .text section. (4) sets the stack pointer . (5) sets the number of flash memory w ait c ycles. can be set to no w ait in the s1c17651. (see the memory map, bus control chapter .)
revision hist or y re vision histor y code no. p a g e contents 412120600 all ne w estab lishment
america epson electronics america, inc. 2580 orchard parkway, san jose, ca 95131, usa phone: +1-800-228-3964 fax: +1-408-922-0238 europe epson europe electronics gmbh riesstrasse 15, 80992 munich, germany phone: +49-89-14005-0 fax: +49-89-14005-110 asia epson (china) co., ltd. 7f, jinbao bldg., no.89 jinbao st., dongcheng district, beijing 100005, china phone: +86-10-8522-1199 fax: +86-10-8522-1125 shanghai branch 7f, block b, hi-tech bldg., 900 yishan road, shanghai 200233, china phone: +86-21-5423-5577 fax: +86-21-5423-4677 shenzhen branch 12f, dawning mansion, keji south 12th road, hi-tech park, shenzhen 518057, china phone: +86-755-2699-3828 fax: +86-755-2699-3838 epson hong kong ltd. 20/f, harbour centre, 25 harbour road, wanchai, hong kong phone: +852-2585-4600 fax: +852-2827-4346 telex: 65542 epsco hx epson taiwan technology & trading ltd. 14f, no. 7, song ren road, taipei 110, taiwan phone: +886-2-8786-6688 fax: +886-2-8786-6660 epson singapore pte., ltd. 1 harbourfront place, #03-02 harbourfront tower one, singapore 098633 phone: +65-6586-5500 fax: +65-6271-3182 seiko epson corp. korea office 5f, kli 63 bldg., 60 yoido-dong, youngdeungpo-ku, seoul 150-763, korea phone: +82-2-784-6027 fax: +82-2-767-3677 seiko epson corp. microdevices operations division device sales & marketing dept. 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 international sales operations document code: 412120600 issue apr il 2011 in j ap an l

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