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january 2008 rev 1 1/32 32 L6228Q dmos driver for bipolar stepper motor features operating supply voltage from 8 to 52 v 2.8a output peak current (1.4 a rms) r ds(on) 0.73 ? typ. value @ t j = 25 c operating frequency up to 100 khz non dissipative overcurrent protection dual independent constant t off pwm current controllers fast/slow decay mode selection fast decay quasi-synchronous rectification decoding logic for stepper motor full and half step drive cross conduction protection thermal shutdown under voltage lockout integrated fast free wheeling diodes applications bipolar stepper motor description the L6228Q is a dmos fully integrated stepper motor driver with non-dissipative overcurrent protection, realized in multipower-bcd technology, which combines isolated dmos power transistors with cmos and bipolar circuits on the same chip. the device includes all the circuitry needed to drive a two-phase bipolar stepper motor including: a dual dmos full bridge, the constant off time pwm current controller that performs the chopping regulation and the phase sequence generator, that generates the stepping sequence. available in vfqfpn-32 5x5 package, the L6228Q features a non-dissipative overcurrent protection on the high side power mosfets and thermal shutdown. vfqfpn 5x5 32l www.st.com figure 1. block diagram gate logic stepping sequence generation over current detection over current detection gate logic vcp vboot en control cw/ccw vref a v boot 5v 10v vs a vs b out1 a out2 a out1 b out2 b sense a charge pump voltage regulator one shot monostable masking time thermal protection v boot v boot ocd b ocd a 10v 10v bridge a sense comparator bridge b d01in1225 rc a + - sense b vref b rc b half/full clock reset pwm
contents L6228Q 2/32 contents 1 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 pwm current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.5 stepping sequence generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.6 half step mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.7 normal drive mode (full-step two-phase-on) . . . . . . . . . . . . . . . . . . . . . . 18 4.8 wave drive mode (full-step one-phase-on) . . . . . . . . . . . . . . . . . . . . . . . 18 4.9 non-dissipative overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.10 thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 output current capability and ic power dissipation . . . . . . . . . . . . . . 25 7 thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
L6228Q electrical data 3/32 1 electrical data 1.1 absolute maximum ratings 1.2 recommended operating conditions table 1. absolute maximum ratings symbol parameter parameter value unit v s supply voltage v sa = v sb = v s 60 v v od differential voltage between vs a , out1 a , out2 a , sense a and vs b , out1 b , out2 b , sense b v sa = v sb = v s = 60 v; v sensea = v senseb = gnd 60 v v boot bootstrap peak voltage v sa = v sb = v s v s + 10 v v in ,v en input and enable voltage range -0.3 to +7 v v refa , v refb voltage range at pins v refa and v refb -0.3 to +7 v v rca, v rcb voltage range at pins rc a and rc b -0.3 to +7 v v sensea, v senseb voltage range at pins sense a and sense b -1 to +4 v i s(peak) pulsed supply current (for each v s pin), internally limited by the overcurrent protection v sa = v sb = v s ; t pulse < 1 ms 3.55 a i s rms supply current (for each v s pin) v sa = v sb = v s 1.4 a t stg , t op storage and operating temperature range -40 to 150 c table 2. recommended operating conditions symbol parameter parameter min max unit v s supply voltage v sa = v sb = v s 852v v od differential voltage between vs a , out1 a , out2 a , sense a and vs b , out1 b , out2 b , sense b v sa = v sb = v s ; v sensea = v senseb 52 v v refa , v refb voltage range at pins v refa and v refb -0.1 5 v v sensea, v senseb voltage range at pins sense a and sense b (pulsed t w < t rr ) (dc) -6 -1 6 1 v v i out rms output current 1.4 a t j operating junction temperature -25 +125 c f sw switching frequency 100 khz
electrical data L6228Q 4/32 1.3 thermal data table 3. thermal data symbol parameter value unit r th(ja) thermal resistance j unction-ambient max. 32 c/w
L6228Q pin connection 5/32 2 pin connection figure 2. pin connection (top view) note: 1 the pins 2 to 8 are connected to die pad. 2 the die pad must be connected to gnd pin.
pin connection L6228Q 6/32 table 4. pin description n pin type function 1, 21 gnd gnd ground terminals. 9out1 b power output bridge b output 1. 11 rc b rc pin rc network pin. a parallel rc network connected between this pin and ground sets the current controll er off-time of the bridge b. 12 sense b power supply bridge b source pin. this pin must be connected to power ground through a sensing power resistor. 13 vref b analog input bridge b current controller reference voltage. do not leave this pin open or connected to gnd. 14 half/full logic input step mode selector. high logic level sets half step mode, low logic level sets full step mode. if not used, it has to be connected to gnd or +5 v. 15 control logic input decay mode selector. high logic level sets slow decay mode. low logic level sets fast decay mode. if not used, it has to be connected to gnd or +5 v. 16 en logic input (1) chip enable. low logic level switc hes off all power mosfets of both bridge a and bridge b. this pin is also connected to the collector of the overcurrent and thermal protection to implement over current protection. if not used, it has to be connected to +5 v through a resistor. 17 vboot supply voltage bootstrap voltage needed for driving the upper power mosfets of both bridge a and bridge b. 19 out2 b power output bridge b output 2. 20 vs b power supply bridge b power supply voltage. it must be connected to the supply voltage together with pin vs a 22 vs a power supply bridge a power supply voltage. it must be connected to the supply voltage together with pin vs b 23 out2 a power output bridge a output 2. 24 vcp output charge pump oscillator output. 25 reset logic input reset pin. low logic level restores the home state (state 1) on the phase sequence generator state machine. if not used, it has to be connected to +5 v. 26 vref a analog input bridge a current controller reference voltage. do not leave this pin open or connected to gnd. 27 clock logic input step clock input. the state machine makes one step on each rising edge. 28 cw/ccw logic input selects the direction of the rotation. high logic level sets clockwise direction, whereas low logic level sets counterclockwise direction. if not used, it has to be connected to gnd or +5 v. 29 sense a power supply bridge a source pin. this pin must be connected to power ground through a sensing power resistor. 30 rc a rc pin rc network pin. a parallel rc network connected between this pin and ground sets the current controll er off-time of the bridge a. 31 out1 a power output bridge a output 1. 1. also connected at the output drain of the over current and thermal protection mosfet. ther efore, it has to be driven putting in series a resistor with a value in the range of 2.2 k ? - 180 k ? , recommended 100k ?
L6228Q electrical characteristics 7/32 3 electrical characteristics table 5. electrical characteristcs (t a = 25 c, vs = 48 v, unless otherwise specified) symbol parameter test condition min typ max unit v sth(on) turn-on threshold 5.8 6.3 6.8 v v sth(off) turn-off threshold 5 5.5 6 v i s quiescent supply current all bridges off; t j = -25 c to 125 c (1) 510ma t j(off) thermal shutdown temperature 165 c output dmos transistors r ds(on) high-side + low-side switch on resistance t j = 25 c 1.47 1.69 ? t j =125 c (1) 2.35 2.70 ? i dss leakage current en = low; out = v s 2ma en = low; out = gnd -0.3 ma source drain diodes v sd forward on voltage i sd = 1.4 a, en = low 1.15 1.3 v t rr reverse recovery time i f = 1.4 a 300 ns t fr forward recovery time 200 ns logic inputs (en, control, ha lf/full, clock, reset, cw/ccw) v il low level logic input voltage -0.3 0.8 v v ih high level logic input voltage 2 7 v i il low level logic input current gnd logic input voltage -10 a i ih high level logic input current 7v logic input voltage 10 a v th(on) turn-on input threshold 1.8 2.0 v v th(off) turn-off input threshold 0.8 1.3 v v th(hys) input threshold h ysteresis 0.25 0.5 v switching characteristics t d(on)en enable to output turn-on delay time (2) i load =1.4 a, resistive load 500 650 800 ns t d(off)en enable to output turn-off delay time (2) i load =1.4 a, resistive load 500 800 1000 ns t rise output rise time (2) i load =1.4 a, resistive load 40 250 ns t fall output fall time (2) i load =1.4 a, resistive load 40 250 ns t dclk clock to output delay time (3) i load =1.4 a, resistive load 2 s t clk(min)l minimum clock time (4) 1s t clk(min)h minimum clock time (4) 1s
electrical characteristics L6228Q 8/32 f clk clock frequency 100 khz t s(min) minimum set-up time (5) 1s t h(min) minimum hold time (5) 1s t r(min) minimum reset time (5) 1s t rclk(min) minimum reset to clock delay time (5) 1s t dt dead time protection 0.5 1 s f cp charge pump frequency t j = -25 c to 125 c (1) 0.6 1 mhz pwm comparator and monostable i rca, i rcb source current at pins rc a and rc b v rca = v rcb = 2.5 v 3.5 5.5 ma v offset offset voltage on sense comparator v refa, v refb = 0.5 v 5 mv t prop turn off propagation delay (6) 500 ns t blank internal blanking time on sense pins 1 s t on(min) minimum on time 2.5 3 s t off pwm recirculation time r off = 20 k ?; c off = 1 nf 13 s r off = 100 k ?; c off = 1 nf 61 s i bias input bias current at pins vref a and vref b 10 a over current protection i sover input supply overcurrent protection threshold t j = -25 c to 125 c (1) 2.8 a r opdr open drain on resistance i = 4 ma 40 60 w t ocd(on) ocd turn-on delay time (7) i = 4 ma; c en < 100 pf 200 ns t ocd(off) ocd turn-off delay time (7) i = 4 ma; c en < 100 pf 100 ns 1. tested at 25 c in a restricted r ange and guaranteed by characterization 2. see figure 3 . 3. see figure 4 . 4. see figure 5 . 5. see figure 6 . 6. measured applying a voltage of 1 v to pin sense and a voltage drop from 2 v to 0 v to pin vref. 7. see figure 7 . table 5. electrical characteristcs (continued) (t a = 25 c, vs = 48 v, unless otherwise specified) symbol parameter test condition min typ max unit
L6228Q electrical characteristics 9/32 figure 3. switching char acteristic definition figure 4. clock to output delay time v th(on) v th(off) 90% 10% en i out t t t fall t d(off)en t rise t d(on)en d01in1316 clock i out t t t dclk v th(on) d01in1317
electrical characteristics L6228Q 10/32 figure 5. minimum timing definition; clock input figure 6. minimum timing definition; logic inputs figure 7. overcurrent de tection timing definition clock t clk(min)h t clk(min)l v th(off) v th(on) d01in1318 v th(off) clock reset t s(min) t h(min) t r(min) t rclk(min) logic inputs d01in1319 v th(off) v th(on) v th(on) i sover 90% 10% i out v en t ocd(off) t ocd(on) d02in1399 on off bridge
L6228Q circuit description 11/32 4 circuit description 4.1 power stages and charge pump the L6228Q integrates two independent power mos full bridges. each power mos has an r ds(on) = 0.73 ? (typical value @ 25 c), with intrin sic fast freewheeling diode. switching patterns are generated by the pwm current controller and the phase sequence generator (see below). cross conduction protecti on is achieved using a dead time (t dt = 1 s typical value) between the switch off and switch on of two power mosfets in one leg of a bridge. pins vs a and vs b must be connected together to the supply voltage v s . the device operates with a supply voltage in the range from 8 v to 52 v. it has to be noticed that the r ds(on) increases of some percents when the supply voltage is in the range from 8 v to 12 v. using n-channel power mos for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. the bootstrapped supply voltage v boot is obtained through an internal oscillator and few external components to realize a charge pump circuit as shown in figure 8 . the oscillator output (vcp) is a squa re wave at 600 khz (typical) with 10v amplitude. recommended values/part numbers for the charge pump circuit are shown in ta b l e 6 . figure 8. charge pump circuit table 6. charge pump external components values c boot 220 nf c p 10 nf r p 100 ? d1 1n4148 d2 1n4148 d2 c boot d1 r p c p v s vs a vcp vboot vs b d01in132 8
circuit description L6228Q 12/32 4.2 logic inputs pins control, half/full, clock, reset and cw/ccw are ttl/cmos and uc compatible logic inputs. the in ternal structure is shown in figure 9 . typical value for turn-on and turn-off thresholds are respectively v th(on) = 1.8 v and v th(off) = 1.3 v. pin en (enable) has identical input structure with the exception that the drain of the overcurrent and thermal protection mosfet is also connected to this pin. due to this connection some care needs to be taken in driving this pin. the en input may be driven in one of two configurations as shown in figure 10 or figure 11 . if driven by an open drain (collector) structure, a pull-up resistor r en and a capacitor c en are connected as shown in figure 10 . if the driver is a standard push-pull structure the resistor r en and the capacitor c en are connected as shown in figure 11 . the resistor r en should be chosen in the range from 2.2 k ? to 180 k ? . recommended values for r en and c en are respectively 100 k ? and 5.6nf. more information on selecting the values is found in the overcurrent protection section. figure 9. logic inputs internal structure figure 10. en pin open collector driving figure 11. en pin push-pull driving 5v d01in1329 esd protection 5v 5v open collector output r en c en en d01in133 0 esd protection 5v push-pull output r en c en en d01in1331 esd protection
L6228Q circuit description 13/32 4.3 pwm current control the L6228Q includes a constant off time pwm current controller for each of the two bridges. the current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the two lower power mos transistors and ground, as shown in figure 12 . as the current in the motor builds up the voltage across the sense resistor increases proportionally. when the voltage drop across the sense resistor becomes greater than the voltage at the reference input (vref a or vref b ) the sense comparator triggers the monostable switching the bridge off. the power mos remain off for the time set by the monostable and the motor current recirculates as defined by the selected decay mode, described in the next section. when the monostable times out the bridge will again turn on. since t he internal dead time, used to prevent cross conduction in the bridge, delays the turn on of the power mos, the effective off time is the sum of the monostable time plus the dead time. figure 12. pwm current controller simplified schematic figure 13 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the rc pin voltage and the status of the bridge. more details regarding the synchronous rectification and the output stage configuration are included in the next section. immediately after the power mos turns on, a high peak current flows through the sensing resistor due to the reverse recovery of the freewheeling diodes. the L6228Q provides a 1 s blanking time t blank that inhibits the comparator output so that this current spike cannot prematurely re-trigger the monostable. drivers + dead time s q r drivers + dead time 2h 1h 2l 1l out2 a(or b) sense a(or b) r sense d01in1332 rc a(or b) r off c off vref a(or b) i out out1 a(or b) + + - - 1 s 5ma blanker sense comparator comparator output monostable set 2.5v 5v from the low-side gate drivers 2 phase stepper motor blanking time monostable vs a (or b ) to gate logic (0) (1)
circuit description L6228Q 14/32 figure 13. output current regulation waveforms figure 14 shows the magnitude of the off time t off versus c off and r off values. it can be approximately calculated from the equations: t rcfall = 0.6 r off c off t off = t rcfall + t dt = 0.6 r off c off + t dt where r off and c off are the external component values and t dt is the internally generated dead time with: 20 k ? r off 100 k ? 0.47 nf c off 100 nf t dt = 1 s (typical value) therefore: t off(min) = 6.6 s t off(max) = 6 ms these values allow a sufficient range of t off to implement the drive circuit for most motors. the capacitor value chosen for c off also affects the rise time t rcrise of the voltage at the pin rcoff. the rise time t rcrise will only be an issue if the capacitor is not completely charged before the next time the monostable is triggered. therefore, the on time t on , which depends by motors and supply parameters, has to be bigger than t rcrise for allowing a good current regulation by the pwm stage. furthermore, the on time t on can not be smaller than the minimum on time t on(min) . off bc dd a t on t off t off bc on 2.5v 0 fast decay fast decay slow decay slow decay 1 s t blank t rcrise 1 s t dt 1 s t dt t rcrise t rcfall t rcfall synchronous or quasi synchronous rectification 1 s t blank 5v v rc v sense v ref i out v ref r sense d01in1334
L6228Q circuit description 15/32 t rcrise = 600 c off figure 15 shows the lower limit for the on time t on for having a good pwm current regulation capacity. it has to be said that t on is always bigger than t on(min) because the device imposes this condition, but it can be smaller than t rcrise - t dt . in this last case the device continues to work but the off time t off is not more constant. so, small c off value gives more flexibility for the app lications (allows smaller on time and, therefore, higher switching frequency), but, the smaller is the value for c off , the more influential will be the noises on the circuit performance. figure 14. t off versus c off and r off t on t on min () > 2.5 s = t on t rcrise t dt ? > ?? ?? ?? (typ. value) 0.1 1 10 100 1 10 100 1 . 10 3 1 . 10 4 coff [nf] toff [ s] r off = 100k ? r off = 47k ? r off = 20k ?
circuit description L6228Q 16/32 figure 15. area where t on can vary maintaining the pwm regulation. 4.4 decay modes the control input is used to select the behavior of the bridge during the off time. when the control pin is low, the fast decay mode is selected and both transistors in the bridge are switched off during the off time. when the control pin is high, the slow decay mode is selected and only the low side transistor of the bridge is switched off during the off time. figure 16 shows the operation of the bridge in the fast decay mode. at the start of the off time, both of the power mos are switched off and the current recirculates through the two opposite free wheeling diodes. the current decays with a high di/dt since the voltage across the coil is essentially the power supply voltage. after the dead time, the lower power mos in parallel with the conducting diode is turned on in synchronous rectification mode. in applications where the motor current is low it is possible that the current can decay completely to zero during the off time. at this point if both of the power mos were operating in the synchronous rectification mode it would then be possible for the current to build in the opposite direction. to prevent this only the lower power mos is operated in synchronous rectification mode. this oper ation is called quasi-synchronous rectification mode. when the monostable times out, the power mos are turned on again after some delay set by the dead time to prevent cross conduction. figure 17 shows the operation of the bridge in the slow decay mode. at the start of the off time, the lower power mos is switched off and the current recirculates around the upper half of the bridge. since the voltage across the coil is low, the current decays slowly. after the dead time the upper power mos is operated in the synchronous rectification mode. when the monostable times out, the lower power mos is turned on again after some delay set by the dead time to prevent cross conduction. 0.1 1 10 100 1 10 100 coff [nf] ton(min) [us] 2.5 s (typ. value)
L6228Q circuit description 17/32 figure 16. fast decay mode output stage configurations figure 17. slow decay mode output stage configurations 4.5 stepping sequence generation the phase sequence generator is a state machine that provides the phase and enable inputs for the two bridges to drive a stepper motor in either full step or half step. two full step modes are possible, the normal drive mode where both phases are energized each step and the wave drive mode where only one phase is energized at a time. the drive mode is selected by the half/full input and the current state of the sequence generator as described below. a rising edge of the clock input advances the state machine to the next state. the direction of rotation is set by the cw/ccw input. the reset input resets the state machine to state 1. 4.6 half step mode a high logic level on the half/ful l input selects half step mode. figure 18 shows the motor current waveforms and the state diagram for the phase sequencer generator. at start-up or after a reset the phase sequencer is at state 1. after each clock pulse the state changes following the sequence 1,2,3,4,5,6,7,8,? if cw/ccw is high (clockwise movement) or 1,8,7,6,5,4,3,2,? if cw/ccw is low (counterclockwise movement). a) on time b) 1 s dead time c) quasi-synchronous rectification d) 1 s slow decay d01in1335 a) on time b) 1 s dead time c) synchronous rectification d) 1 s dead time d01in1336
circuit description L6228Q 18/32 4.7 normal drive mode (f ull-step two-phase-on) a low level on the half/full input selects the full step mode. when the low level is applied when the state machine is at an odd numbered state the normal drive mode is selected. figure 19 shows the motor current waveform state diagram for the state machine of the phase sequencer generator. the normal drive mode can easily be selected by holding the half/full input lo w and applying a reset. at st art -up or after a reset the state machine is in state 1. while the half/full input is kept low, state changes following the sequence 1,3,5,7,? if cw/ccw is high ( clockwise movement) or 1,7,5,3,? if cw/ccw is low (counterclockwise movement). 4.8 wave drive mode (full-step one-phase-on) a low level on the pin half/full input select s the full step mode. when the low level is applied when the state machine is at an even numbered state the wave drive mode is selected. figure 20 shows the motor current waveform and the state diagram for the state machine of the phase sequence generator. to enter the wave drive mode the state machine must be in an even numbered state. the most direct method to select the wave drive mode is to first apply a reset, then wh ile keeping the half/full input high apply one pulse to the clock input then take the half/full input low. this sequence first forces the state machine to state 1. the clock pulse, with the half/full input high advances the state machine from state 1 to either state 2 or 8 depending on the cw/ccw input. starting from this point, after each clock pulse (rising edge) will advance the state machine following the sequence 2,4,6,8,? if cw/ccw is high ( clockwise movement) or 8,6,4,2,? if cw/ccw is low (counterclockwise movement). figure 18. half step mode figure 19. normal drive mode 3 2 4 5 1 d01in1320 2345678 6 1 8 7 i outa i outb clock start up or reset 2 4 1 d01in1322 3571357 6 8 i outa i outb clock 35 17 start up or reset
L6228Q circuit description 19/32 figure 20. wave drive mode 4.9 non-dissipative overcurrent protection the L6228Q integrates an overcurrent detection circuit (ocd) for full protection. this circuit provides protection agai nst a short circuit to ground or between two phases of the bridge. with this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. figure 21 shows a simplified schematic of the overcurrent detection circuit. to implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power mos. since this current is a small fraction of the output current there is very little additional power dissipation. this current is compared with an internal reference current i ref . when the output current reaches the detection threshold (typically 2.8 a) the ocd comparator signals a fault condition. when a fault condition is detected, the en pin is pulled below the turn off threshold (1.3 v typical) by an internal ope n drain mos with a pull down capability of 4 ma. by using an external r-c on the en pin, the off time before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. 2 4 2 d01in1321 4682468 6 8 i outa i outb clock 3 5 1 7 start up or reset
circuit description L6228Q 20/32 figure 21. overcurrent protection simplified schematic figure 22 shows the overcurrent detection operation. the disable time t disable before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. it is affected whether by c en and r en values and its magnitude is reported in figure 23 . the delay time t delay before turning off the bridge when an overcurrent has been detected depends only by c en value. its magnitude is reported in figure 24 . c en is also used for providing immunity to pin en against fast transient noises. therefore the value of c en should be chosen as big as possible according to the maximum tolerable delay time and the r en value should be chosen according to the desired disable time. the resistor r en should be chosen in the range from 2.2 k ? to 180 k ? . recommended values for r en and c en are respectively 100 k ? and 5.6 nf that allow obtaining 200 s disable time. + over temperature i ref (i 1a +i 2a ) / n i 1a / n power sense 1 cell power sense 1 cell power dmos n cells power dmos n cells high side dmoss of the bridge a out1 a out2 a vs a i 1a i 2a i 2a / n from the bridge b ocd comparator ocd comparator to gate logic internal open-drain r ds(on) 40 ? typ. c en . r en .en v dd c or logic d01in1337
L6228Q circuit description 21/32 figure 22. overcurrent protection waveforms i sover i out v th(on) v th(off) v en(low) v dd t ocd(on) t d(on)en t en(fall) t en(rise) t disable t delay t ocd(off) t d(off)en v en bridge on off ocd on off d02in1400
circuit description L6228Q 22/32 figure 23. t disable versus c en and r en (v dd = 5 v). figure 24. t delay versus c en (v dd = 5v). 4.10 thermal protection in addition to the ovecurrent protection, the L6228Q integrates a thermal protection for preventing the device destruction in case of junction over temperature. it works sensing the die temperature by means of a sensible element integrated in the die. the device switch-off when the junction temperature reaches 165 c (typ. value) with 15 c hysteresis (typ. value). 1 10 100 1 10 100 1 . 10 3 c en [nf] t disable [s] r en = 220 k ? r en = 100 k ? r en = 47 k ? r en = 33 k ? r en = 10 k ? 1 10 100 1 10 100 1 . 10 3 c en [nf] t disable [s] r en = 220 k ? r en = 100 k ? r en = 47 k ? r en = 33 k ? r en = 10 k ? 110100 0.1 1 10 cen [nf] tdelay [ s]
L6228Q application information 23/32 5 application information a typical bipolar stepper motor driver application using L6228Q is shown in figure 25 . typical component values for the application are shown in ta b l e 7 . a high quality ceramic capacitor in the range of 100 to 200 nf should be placed between the power pins (vs a and vs b ) and ground near the L6228Q to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. the capacitor connected from the en input to ground sets the shut down time when an over current is detected (see overcurrent protection). the two current sensing inputs (sense a and sense b ) should be connected to the sensing resistors with a trace length as short as possible in the layout. the sense resistors should be non-inductive resistors to minimize the di/dt transients across the resistor. to increa se noise immunity, unused logic pins (except en) are best connected to 5 v (high logic le vel) or gnd (low logic level) (see pin description). it is recommended to keep power ground and signal ground separated on pcb. table 7. component values for typical application component value c 1 100f c 2 100nf c a 1nf c b 1nf c boot 220nf c p 10nf c en 5.6nf c ref 68nf d 1 1n4148 d 2 1n4148 r a 39k ? r b 39k ? r en 100k ? r p 100 ? r sensea 0.6 ? r senseb 0.6 ?
application information L6228Q 24/32 figure 25. typical application note: to reduce the ic thermal resistance, therefore improve the dissipation path, the nc pins can be connected to gnd.
L6228Q output current capability and ic power dissipation 25/32 6 output current capability and ic power dissipation in figure 26 , figure 27 , figure 28 and figure 29 are shown the approximate relation between the output current and the ic power dissipation using pwm current control driving a two-phase stepper motor, for different driving sequences: half step mode ( figure 26 ) in which alternately one phase / two phases are energized. normal drive (full-st ep two phase on) mode ( figure 27 ) in which two phases are energized during each step. wave drive (full-step one phase on) mode ( figure 27 ) in which only one phase is energized at each step. microstepping mode ( figure 29 ), in which the current fo llows a sine-wave profile, provided through the v ref pins. for a given output current and driving sequence the power dissipated by the ic can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125 c maximum). figure 26. ic power dissipation versus output current in half step mode no pwm f sw = 30 khz (slow decay) test conditions: supply voltage = 24v i a i b i out i out p d [w] i out [a ] half step 0 0.25 0.5 0.75 1 1.25 1.5 0 2 4 6 8 10
output current capability and ic power dissipation L6228Q 26/32 figure 27. ic power dissipation versus output current in normal mode (full step two phase on) figure 28. ic power dissipation versus output current in wave mode (full step one phase on) figure 29. ic power dissipation versus output current in microstepping mode no pwm f sw = 30 khz (slow decay) test conditions: supply volt age = 24 v i a i b i out i out p d [w ] i out [a ] norm al drive 0 0.25 0.5 0.75 1 1.25 1.5 0 2 4 6 8 10 no pwm f sw = 3 0 khz (slow decay) test conditions: supply voltage = 24v i a i b i out i out wave drive p d [w] i out [a] 0 0.25 0.5 0.75 1 1.25 1.5 0 2 4 6 8 10 f sw = 50 k hz (slow decay) f sw = 30 k hz (slow decay) i a i b i out i out microstepping p d [w] i out [a] test conditions: supply voltage = 24v 0 0.25 0.5 0.75 1 1.25 1.5 0 2 4 6 8 10
L6228Q thermal management 27/32 7 thermal management in most applications the power dissipation in the ic is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. therefore, it has to be taken into account very carefully. besides the available space on the pcb, the right package should be chosen considering the power dissipation. heat sinking can be achieved using copper on the pcb with proper area and thickness. for instance, using a vfqfpn32l 5x5 package the typical r th(j-amb) is about 32 c/w.
package mechanical data L6228Q 28/32 8 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com note: vfqfpn stands for thermally enhanced very thin profile fine pitch quad flat package no lead. very thin profile: 0.80 < a < 1.00mm. details of terminal 1 are optional but must be located on the top surface of the package by using either a mold or marked features. table 8. vfqfpn 5x5x1.0 32l pitch 0.50 dim. databook (mm) min typ max a 0.80 0.85 0.95 b 0.18 0.25 0.30 b1 0.165 0.175 0.185 d 4.85 5.00 5.15 d2 3.00 3.10 3.20 d3 1.10 1.20 1.30 e 4.85 5.00 5.15 e2 4.20 4.30 4.40 e3 0.60 0.70 0.80 e0.50 l 0.30 0.40 0.50 ddd 0.08
L6228Q package mechanical data 29/32 figure 30. package dimensions
order codes L6228Q 30/32 9 order codes table 9. order codes part number package packaging L6228Q vfqfpn 5x5x1.0 32l tube
L6228Q revision history 31/32 10 revision history table 10. document revision history date revision changes 14-jan-2008 1 first release
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