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pi2125 cool-oring tm series 30 volt, 12 amp full-function active oring solution description the cool-oring tm pi2125 is a complete full-function active oring solution with a high-speed oring mosfet controller and a very low on-state resistance mosfet designed for use in redundant power system architectures. the pi2125 cool-oring solution is offered in an extremely small, thermally enhanced 5mm x 7mm lga package and can be used in high side active oring applications on bus voltages up to 12v. the pi2125 enables extremely low power loss with fast dynamic response to fault conditions, critical for high availability systems. a master/slave feature allows the paralleling of pi2125 solutions for high cu rrent active oring requirements. the pi2125, with its 5.5m internal mosfet provide s very high efficiency and low power loss during steady state operation, while achieving high- speed turn-off of the internal mosfet during input power source fault conditions that cause reverse current flow. the pi2125 provides an active low fault flag output to the sy stem during excessive forward current, light load, reverse current, over- voltage, under-voltage and over-temperature fault conditions. a temperature sensing function indicates a fault if the maximum junction temperature exceeds 160 c. the under-voltage and over- voltage thresholds are programmable via an external resistor divider. features ? integrated high performance 12a, 5.5m mosfet ? very-small, high density fully-optimized solution providing simple pcb layout. ? fast dynamic response to power source failures, with 160ns reverse current turn-off delay time ? accurate sensing capability to indicate system fault conditions ? programmable under & over-voltage functions ? over temperature fault detection ? adjustable reverse current blanking timer ? master/slave i/o for paralleling ? active low fault flag output applications ? n+1 redundant power systems ? servers & high end computing ? telec om systems ? high-side active oring ? high current active oring ( 12vbus) package information ? 17-pin 5mm x 7mm thermally enhanced lga package typical application: figure 1: pi2125 high side active oring figure 2: pi2125 input current de-rating based on maximum t j =150c vs. ambient temperature. picor corporation ? picorpower.com pi2125 rev 1.0 page 1 of 20 not recommended for new design
pin description pin name pin num ber description d 1, 15, 16, 17 drain- t he drain of the internal n-channel mosfet, connect to the output load. s 2, 3, 4, 5 source- the sou rce of the internal n-channel mosfet, connect to the input power source bus voltage. sp 6 positive sense input & clamp: co nnect sp pin to the s pin. the polarity of the voltage difference between sp and sn provides an indication of current flow direction through the mosfet. ft 7 fault state output: t his open collector pin pulls low when a fault occurs. fault logic inputs are vc under-voltage, input under-voltage, input over-voltage, forward over-current, light load, reverse current, and over-temper ature. leave this pin open if unused. bk 8 blanking timer input-output: connec t a resistor from bk to gnd to set the blanking time for the reverse comparator function. to conf igure in slave mode, connect bk to vc. to configure in master mode with the fastest tu rn-off response connect bk directly to gnd. sl 9 slave input-output: this pin is used for paralleling multiple pi2125 solutions in high power appli cations. when the pi2125 is configured as the master, this pin functions as an output capable of driving up to 10 sl pins of slaved pi2125 devices. it serves as an input when the pi2125 is configured in slave mode. vc 10 input supply pin: this pin is the su pply pin for the control circuitry and gate driver. connect a 1 f capacitor between vc pin and the gnd pin. voltage on this pin is limited to 15.5v by an internal shunt regulator in high auxiliary voltage applications. for high voltage auxiliary supply applications connect a shunt resistor between vc and the auxiliary supply. gnd 11 ground: thi s pin is ground for the gate driver and control circuitry. ov 12 input over voltage input: the ov pin is used to det ect an input source over-voltage condition in ground referenced applications . when the ov pin voltage crosses the ov threshold, the ft pin pulls low indicating a fault condition. the input voltage ov threshold is programmable through an external resistor divider. connect ov to gnd to disable this function. uv 13 input under-voltage input: th e uv pin is used to detect an input source under-voltage condition in ground referenced applications. when the uv pin voltage drops below the uv threshold, the ft pin pulls low indicating a fault condition. the input voltage uv threshold is programmable through an external resistor divi der. connect uv to vc to disable this function. sn 14 negative sense input & clamp- connect sn to d pin. the polarity of the voltage difference between sp and sn provides an indication of current flow direction through the mosfet. package pin-out 17 pin lga (5mm x 7mm) top view picor corporation ? picorpower.com pi2125 rev 1.0 page 2 of 20 not recommended for new design
absolute maximum ratings drain-to-source voltage (v ds ) 30v @ 25c source current (i s ) continuous 12a source current (i s ) pulsed (10 s) 60a thermal resistance r ja (3) 54 c/w vc -0.3v to 17.3v / 40ma sn -0.3v to 30v / 10ma -0.3v to 8.0v / 10ma sp, ov, sl -0.3v to 17.3v / 10ma uv,bk, ft gnd -0.3v / 5a peak -65 o c to 150 o c storage temperature -40 o c to over temperature fault (t ft ) operating junction temperature 250 o c lead temperature (soldering, 20 sec) esd rating 2kv hbm electrical specifications unless otherwise specified: -40 c < t j < 125 c, vc =12v, c vc = 1uf, c sl = 10pf parameter symbol min typ max units conditions vc supply operating supply range (4) v vc-gnd 4.5 13.2 v no vc limiting resistors quiescent current i vc 3.7 4.2 ma normal operating condition, no faults vc clamp voltage v vc-clm 15 15.5 16 v i vc =10ma vc clamp shunt resistance r vc 7.5 delta i vc =10ma vc under-voltage rising threshold v vcuvr 4.3 4.5 v vc under-voltage falling threshold v vcuvf 4.0 4.15 v vc under-voltage hysteresis v vcuv-hs 150 mv internal n-channel mosfet drain-to-source breakdown voltage bv dss 30 v in off state, i d =250a , tj=25c, figure 10, page 11 source current continuous i s 12 a in on state, tj=25c drain leakage current i dlk 10 a in off state, v ds =30v, tj=25c drain-to-source on resistance r dson 5.5 7.0 m in on state, i s =8a, tj=25c vc-v(s) 5v body diode forward voltage v f-bd 0.7 1.0 v in on state, i s =4a, tj=25c fault under-voltage rising threshold v uvr 500 540 mv under-voltage falling threshold v uvf 440 475 mv under-voltage threshold hysteresis v uv-hs 25 mv under-voltage bias current i uv -1 1 a over-voltage rising threshold v ovr 500 540 mv over-voltage falling threshold v ovf 440 475 mv picor corporation ? picorpower.com pi2125 rev 1.0 page 3 of 20 not recommended for new design
picor corporation ? picorpower.com pi2125 rev 1.0 page 4 of 20 electrical specifications unless otherwise specified: -40 c < t j < 125 c, vc =12v, c vc = 1uf, c sl = 10pf parameter symbol min typ max units conditions fault (continued) over-voltage threshold hysteresis v ov-hs 25 mv over-voltage bias current i ov -1 1 a fault output low voltage v ftl 0.2 0.5 v i ft =2ma, vc>3.5v fault output high leakage current i ft-lc 10 a v ft =14v fault delay time t ft-del 20 40 60 s includes output glitch filter over temperature fault (1) t ft 160 c over temperature fault hysteresis (1) t ft-hs -10 c differential amplifier and comparators common mode input voltage v cm -0.1 5.5 v sp to gnd & sn to gnd vc to sp differential (1) v vc-sp 3.5 v differential operating input voltage v sp-sn -50 125 mv sp-sn sp input bias current i sp -50 -37 a sp=sn=1.25v sn input bias current i sn 3.5 8 a sp=sn=1.25v sn voltage v sn 26.4 v sp=0v reverse comparator threshold v rvs-th -10 -6 -2 mv v cm = 3.3v reverse comparator hysteresis v rvs-hs 2 5 mv v cm = 3.3v reverse fault to slave low delay time t rvs-ms 160 200 ns v sp-sn = -50mv step, v bk =0 (minimum blanking) reverse fault to slave low delay time t rvs-sl 430 600 ns v sp-sn = -50mv step, v bk = v vc (maximum blanking) forward comparator threshold v fwd-th 2 6 9 mv v cm = 3.3v forward comparator hysteresis v fwd-hs -5 -2 mv v cm = 3.3v forward over current comparator threshold v oc-th 60 66 70 mv v cm = 3.3v forward over current comparator hysteresis v oc-hs -8 -4 mv v cm = 3.3v slave slave source current i sl -60 -25 a v sl = 1v, normal operating conditions, no faults slave output voltage high v sl-hi 4.3 5.5 v normal operating conditions, no fault s slave output voltage low v sl-lo 0.2 0.5 v i sl =4ma slave hold-off voltage at vc uvlo v sl-uv 0.7 1 v i sl =5 a,1.5v picor corporation ? picorpower.com pi2125 rev 1.0 page 5 of 20 electrical specifications unless otherwise specified: -40 c < t j < 125 c, vc =12v, c vc = 1uf, c sl = 10pf parameter symbol min typ max units conditions blank blank source current i bk -60 -45 -30 a v bk =0v blank output voltage v bk 0.77 0.9 v i bk =5 a connected to gnd blank slave mode threshold v bk-th 1.2 1.45 1.7 v note 1 : th ese parameters are not production tested but ar e guaranteed by design, characterization and correlation with statistical process control. note 2: current sourced by a pin is reported with a negative sign. note 3: thermal resistance characte ri zed on pi2125-eval2 evaluation board with 0 lfm airflow. note 4: refer to the auxiliary power supply section in the application information for details on the vc requirement to fully enhance the internal mosfet. not recommended for new design
functional description: the pi2125 integrated cool-o ring product takes advantage of two different technologies combining a 5.5m on-state resistance (rds(on)) single n- channel mosfet with high density control circuitry. this combination provides superior density, minimizing pcb space to achieve an ideal oring diode function, significantly reducing power dissipation and eliminating the need for heat sinking, while minimizing design complexity. the pi2125?s 5.5m on-state res istance mosfet used in the conduction path enables a dramatic reduction in power dissipation versus the performance of a diode used in conventional oring applications due to its high forward voltage drop. this can allow for the elimination of complex heat sinking and other thermal management requirements. due to the i nherent characteristics of the integrated mosfet, while the gate remains enhanced above the gate threshold voltage it will allow current to flow in the forward and reverse direction. ideal oring applications do not allow for reverse current flow, so the integrated controller has to be capable of very fast and accurate detection of reverse current caused by input power source failures, and turn off the gate of the mosfet as quickly as possible. once the gate voltage falls below the gate threshold, the mosfet is off and the body diode will be reverse biased preventing reverse current flow and subsequent excessive voltage droop on the redundant bus. during forward over- current conditions caused by load faults, the controller maintains gate drive to the mosfet to keep power dissipation as low as possible, otherwise the inherent body diode of the mosfet would conduct, which has higher effective forward drop. conventional oring solutions using diodes offer no protection against forward over-current conditions. during the forward over-current condition, the pi2125 will provide an active-low fault flag to the system via the fault pin. the fault flag is also issued during the reverse current condition, light load conditions, vc under-voltage, input under- voltage and over-voltage and over-temperature conditions. differential amplifier: the pi2125 integrates a high-speed, low offset voltage differential amplifi er to sense the difference between the sense positive (sp) pin voltage and sense negative (sn) pin voltage with high accuracy. the amplifier output is connected to three comparators: reverse comparator, forward comparator, and forward ov er-current comparator. reverse comparator: rvs the reverse comparator is the most critical comp arator. it looks for negative voltage caused by reverse current. when the sn pin is 6mv higher than the sp pin, the reverse comparator will enable the bk current source to charge an internal 2pf capacitor. the blanking timer provides noise filtering for typical switching powe r conversion that might cause premature reverse current detection. once the voltage across the capacitor reaches the timer threshold voltage (1.25v) the mosfet will be turned off. the shortest blanking time is 50ns when bk is connected to ground. the blanking time will be added to the controller delay time. the electrical specifications in the differential amplifier and comparator section for reverse fault to slave low delay time ?t rvs-ms or t rvs-sl ? is the controller delay time plus the blanking time. reverse blanking timer: bk connecting an external resistor ( ) between the bk pin and ground will increase the blanking time as shown in the following chart. bk r where: ? kr bk 200 if bk is connected to vc for slave mode operation, then the blanking time will be about 320ns typically, and total delay time will be 430ns. the reverse comparator has 3mv of hysteresis referenc ed to sp-sn. if the conditions are met for a reverse current fault, then the active-low fault flag output will also indicate a fault to the system after the 40s fault delay time. picor corporation ? picorpower.com pi2125 rev 1.0 page 6 of 20 not recommended for new design
forward voltage comparator: fwd the fwd comparator detects when a forward current condition exists and sp is 6mv positive with respect to sn. when sp-sn is less than 6mv, the fwd comparator will assert the fault flag to report a fault condition indicative of a light load or ?load not present? condition or possible shorted mosfet. forward over current comparator: foc the foc comparator indicates an excessive forward curre nt condition when sp is 66mv (typical) higher than sn. when the fet is in the on-state and sp- sn is higher than 66mv (typical) the pi2125 will initiate a fault condition via the ft pin. slave: in high current applications that exceed the single pi2125 current handling capability, multiple pi2125?s can be paralleled and synchronized by using the slave function. the slave function synchronizes multiple pi2125?s together a nd allows for localized control of each paralleled mosfet. one pi2125 will be designated as the master and it will c ontrol the response of the slaved pi2125?s. when the pi2125 is configured in the ?master mode? by co nnecting the bk to ground, the sl will be an output having the same signal characteristics as the internal gate driver. in this configuration, the sl output is capable of driving up to ten pi2125?s, configured in ?slave mode?, through their corresponding sl pins. logic high for the sl pin is limited to 5.5v (max). when the bk pin is tied to vc, the pi2125 becomes a slave and the sl pin will be an input. the internal gate driver section and reverse current section are the only active circuits in the slaved pi2125 while the master performs the diagnostics and gate drive control. vc and internal voltage regulator: the pi2125 has a separate i nput (vc) that provides power to the control circuitry and the internal gate driver. an internal regulator clamps the vc voltage to 15.5v. for high side applications, the vc input should be at least 6v above the bus voltage (vin) to properly enhance the internal n-channel mosfet. for bus voltages higher than 10v ( 15.5v ? 5.5v), the pi2125 should be floated to vin as shown in figure 23, and a resister has to be added in series between vaux and vc. the required resister value calculation is shown in the application section of this document. the internal regulator circuit has a comparator to mo nitor the vc voltage and initiates a fault condition when vc is lower than the vc under- voltage threshold uv: the under-voltage (uv) input trip point can be prog rammed through an external resistor divider to monitor the input voltage, when the pi2125 is used in ground referenced applications. the uv comparator initiates a fault condition and pulls the ft pin low, when uv falls below the under- voltage falling threshold. if the pi2125 is configured in a floating application, where the gnd pin is connected to the input voltage, as shown in fig 23, the uv pin cannot detect the input voltage. in this case, the uv pin should be disabled by connecting it to the vc pin. ov: the over-voltage (ov) input trip point can be prog rammed through an external resistor divider to monitor the input voltage, when the pi2125 is used in ground referenced applications. the ov comparator initiates a fault condition and pulls the ft pin low when ov rises above the over-voltage rising threshold. if the pi2125 is configured in a floating application, where the gnd pin is connected to the input voltage, as shown in fig 23, the ov pin cannot detect the input voltage. in this case, the ov pin should be disabled by connecting it to controller ground pin. over-temperature detection: the internal over-temperature block monitors the junctio n temperature of the controller. the over- temperature threshold is set to 160 c with -10 c of hysteresis. when the controller temperature exceeds this threshold, the over-temperature circuit initiates a fault condition and pulls the ft pin low. fault: the fault circuit output is an open collector with 40 s delay to prev ent any false triggering. the ft pin will be pulled low when any of the following faults occurs: ? reverse current ? forward over-current ? forward low current ? over-temp erature ? input under-voltage ? input over-voltage ? vc pin under-voltage picor corporation ? picorpower.com pi2125 rev 1.0 page 7 of 20 not recommended for new design
a gate voltage detector prevents foc or fwd from initiating a fault when the mosfet is in an off condition. the only fault condition that initiates gate turn-off of the mosfet (as well as a fault flag signal) is when the reverse current fault conditions are met. all other fault conditions issue only a fault flag signal via the ft pin, but do not affect the gate of the mosfet. the ft pin serves as an indicator that a fault condition may be present. this information can be reported to a host to signal that some system level maintenance may be required. figure 3 : pi2125 internal block diagram figure 4: comparator hysteresis, values are for reference only . please refer to the electrical specifications. picor corporation ? picorpower.com pi2125 rev 1.0 page 8 of 20 not recommended for new design
figure 5: ti ming diagram for two pi2125 solutions in an active oring application picor corporation ? picorpower.com pi2125 rev 1.0 page 9 of 20 not recommended for new design
figure 6: pi2125 state dia gram, master mode picor corporation ? picorpower.com pi2125 rev 1.0 page 10 of 20 not recommended for new design
typical characteristics: figure 7: re verse condition internal mosfet turn off delay time vs. temperature. figure 8: re verse comparator threshold vs. temperature. v cm : common mode voltage figure 9: co ntroller bias current vs. temperature figure 10: internal mosfet drain to source b reakdown voltage vs. temperature figure 12: internal mosfet source to drain diode forward voltage (pulsed 300 s) figure 11: internal mosfet on-state resi stance vs. temperature picor corporation ? picorpower.com pi2125 rev 1.0 page 11 of 20 not recommended for new design
thermal characteristics: figure 13: junction temperature vs. input current (0lfm) figure 14: junction temperature vs. input current (200lfm) figure 15: pi2125 mounted on pi2125-eval thermal image picture, iout=12a, t a =25c, air flow=0lfm figure 16: pi2125 mounted on pi2125-eval thermal image picture, iout=12a, t a =25c, air flow=200lfm figure 17: pi2125 input current de-rating based on maximum t j =150c vs. ambient temperature picor corporation ? picorpower.com pi2125 rev 1.0 page 12 of 20 not recommended for new design
figure 18: plot of pi2125 response time to reverse current detection (example 1, figure 23) application information the pi2125 is designed to replace oring diodes in high current, low voltage redundant power architectures. replacing a traditional diode with a pi2125 will result in significant power dissipation reduction as well as board space reduction, efficiency improvement and additional protection features. this section describes in detail the procedure to follow when designing with the pi2125 active oring solution. fault indication: the f t output pin is an open collector and should be pulled up to the logic voltage or to the controller vc via a resistor (10k ? ). in a floating configuration, the f t pin is referenced to the pi2125 gnd pin which is referenced to the input voltage, vin. the f t output status can be reference to the system ground by adding a level shifting circuit, as shown in figure 19. the level shift circuit can be designed with one small and inexpensive off-the-shelf device, a dual bias resistor transistor, containing npn and pnp transistors with their bias resistors, nsbc114epdxv6t1. figure 19: f t level shift circuit picor corporation ? picorpower.com pi2125 rev 1.0 page 13 of 20 not recommended for new design
blanking timer: connect the blanking timer pin (bk) to gnd to program the device for the fastest reverse comparator response time of 160ns typical. to increase the blanking time, connect the bk pin to gnd via a resistor to avoid the fault response to short reverse current pulses. refer to the plot in the reverse comparator functional description for resistor values versus the reverse blanking time. auxiliary power supply (vaux): vaux is an independent pow er source required to supply power to the vc input. the vaux voltage should be 6v higher than vin (redundant power source output voltage) to fully enhance the internal mosfet. a bias resistor (rbias) is required if vaux is higher than 15v. rbias should be connected between the vc pin and vaux. minimize the resistor value for low vaux voltage levels to avoi d a voltage drop that may reduce the vc voltage lower than required to drive the gate of the internal mosfet. select the value of rbias using the following equatio ns: max min ic vc vaux rbias clamp ? = rbias maximum power dissipation: r bias vc vaux pd clamp rbias 2 max ) ( ? = where: min vaux : vaux minimum voltage max vaux : vaux maximum voltage clamp vc : controller clamp voltage, 15.5v max ic : controller maximum bias current, use 4.2ma example: vaux 20v to 30v = ? = ? = k ma vv ic vc vaux rbias clamp 07.1 2.4 5.1520 max min mw k vv r bias vc vaux pd clamp rbias 196 07.1 )5.1530( ) ( 2 2 max = ? = ? = internal n-channel mosfet bvdss: the pi2125?s internal n-channel mosfet brea kdown voltage (bvdss) is rated for 30v at 25c and will degrade at -40c to 28v, refer to figure 10. in an application when the mosfet is turned off due to a reverse fault, the series parasitic elements in the circuit may contribute to the mosfet being exposed to a voltage higher than its voltage rating. in active oring applications when one of the input power sources is shorted, a large reverse current is sourced from the circuit output through the mosfet. depending on the output impedance of the system, the reverse cu rrent may reach over 60a in some conditions before the mosfet is turned off. such high current conditio ns will store energy even in a small parasitic element. for example: a 1nh parasitic inductance with 60a reverse current will generate 1.8j (?li 2 ). when the mosfet is turned off, the stored energy will be released and produce a high negative voltage ringing at the mosfet source. at the same time the energy stored at the drain side of the internal mosfet will be released and produce a voltage higher than the load voltage. this event will create a high voltage difference between the drain and source of the mosfet. to reduce the magnitude of the ringing voltage, add a ceramic capacitor very close to the source that can react to the voltage ringing frequency and another capacitor close to the drain. recommended values for the ceramic capacitors are 1f, refer to c4 and c6 in figure 24. slave : for a high current application where one pi2125 can not handl e the total load current, multiple pi2125?s can be paralleled in a master / slave configuration to support the total current per input. in the master / slave mode, one pi2125 is configured as the master and the rest are configured as slaves. the slave ( sl ) pin of the master unit will act as an output driving the units configur ed in slave mode. the sl pins of the slave units will act as inputs under the control of the master. tie the bk pin to vc to configure the unit in slave mode. power dissipation: in active oring circuits the mosfet is always on in steady state operation mode and the power dissipation is derived from the total source current and the on-state resistance of the internal mosfet. picor corporation ? picorpower.com pi2125 rev 1.0 page 14 of 20 not recommended for new design
the pi2125 internal mosfet power dissipation can be calculated with the following equation: )( 2 onrdsis pd mosfet ?= where: is : source current rds(on) : mosfet on-st ate resistance note: calculate with rds(on) at maximum mosfet tem perature because rds(on) is temperature dependent, refer to figure 11 for normalized rds(on) values over temperature. pi2125 nominal rds(on) at 25c is 3m ? and will increase by 35% at 125c junction temperature. the junction temperature rise is a function of power dissipatio n and thermal resistance. )( 2 onrdsisrth pdrthtrise ja mosfet ja ??=?= , where: : junction-to -ambient thermal resistance (54c/watt) ja rth (3) this may require iteration to get to the final junction temperature. figures 13, 14, and 17 show the pi2125 internal mosfet final junction temperature curves versus conducted current at given ambient temperatures and air flow. ov/uv resistor selection: the uv and ov comparators inputs are used to monitor the i nput voltage and will indicate a fault condition when this voltage is out of range. it can be used to monitor the input voltage (vin) level if the pi2125 is referenced to the same ground as vin. if the pi2125 is floating on vin then ov and uv can not monitor vin and should be disabled by connecting uv to the vc pin and ov to the gnd pin of the same pi2125. the fault pin ( f t ) will indicate a fault (active low) when the uv pin is below the threshold or when the ov pin is above the threshold. the threshold is 0.50v typical with 25mv hysteresis and the input current is less than 1a. it is important to consider the maximum current that will flow in the resistor divider and maximum error due to uv and ov input current. set the resistor current to 100a or higher to maintain better than 1% accuracy for uv and ov due to the bias current. the three-resistor voltage divider configuration for both uv and ov to monitor the same voltage node is shown in figure 20: ra th i ovv ra )( = set value b ased on system allowable current ra ra i ? ? ? ? ? ? ? ? ? = 1 )( )( uvv ovv rarb () ? ? ? ? ? ? ? ? ? += 1 )( )( th uvv uvv rbrarc where: )( th uvv : uv threshold voltage at vin. )( th ovv : ov threshold voltage at vin. )( uvv : uv voltage set ra i : current. ra figure 20: uv & ov three-res istor divider configuration alternatively, a two-resistor voltage divider config uration can be used and is shown in figure 21. figure 21 : uv & ov two-resi stor divider configuration uv resistor voltage divider from the following equatio ns: ruv th uv i uvv r )( 1 = set value ba sed on system allowable current uv r 1 a i ruv 100 ? ? ? ? ? ? ? ? ? = 1 )( )( 12 th uv uv uvv uvv rr where: v(uv th ) : uv threshold voltage ruv i : current uv r 1 picor corporation ? picorpower.com pi2125 rev 1.0 page 15 of 20 not recommended for new design
ruv th uv i uvv r )( 1 = set value ba sed on system allowable current ov r 1 a i ruv 100 ? ? ? ? ? ? ? ? ? = 1 )( )( 12 th ov ov ovv ovv rr where: )( th ovv : ov threshold voltage rov i : current. ov r 1 typical application example 1: requirement: redundant bus voltage = 12v load current = 10a (assume through each redu ndant path) maximum ambient temperature = 70c; no air flow auxiliary voltage = 24v10% (21.6v to 26.4v). solution: a single pi2125 for each redundant 12v power sou rce should be used. vin is 12v which is higher than the sp pin maximum voltage rating of 8v, so the pi2125 should be configured in the floating configuration as shown in figure 23. pi2125 is floated on vin by connecting it?s gnd pin and the low side of the vc coupling capacitor to vin. vaux: m ake sure that the vaux voltage is always higher than vin (dc-dc converter output) by 6.0v to ensure that the internal mosfet is fully enhanced. since the auxiliary voltage is higher than the pi2125 vc cla mp voltage a bias resistor (rbias) is needed in series with the vc pin. rbias value: = ? = k ma vv rbias 45.1 2.4 5.156.21 or 1.43k ? rbias power dissipation rating mw k v pd rbias 83 43.1 )5.154.26( 2 = ? = based on the resultant power dissipation on the bias resi stor, use a ?w rated resistor. sp and sn pins: sin ce the pi2125 is floating, the gnd pin and s pin are connected to vin, so connect the sp pin directly to the pi2125 gnd pin to reduce the effect of parasitics between the sp pin and the gnd pin. this will avoid negative voltages on the sp pin with respect to the gnd pin. connect sn to the d pin. bk pin: connect the bk pin to the gnd pin to achieve the minimum reverse current response time sl pin: not required, so leave floating fault pin : the ft pin output is referenced to the pi2125 gnd pin which is connected to vin. a level shift circuit can be added to make ft output referenced to the system ground. the recommended level shift circuit is shown in figure 23. the level shift circuit uses a dual bias resistor picor corporation ? picorpower.com pi2125 rev 1.0 page 16 of 20 not recommended for new design
transistor circuit which is available as a small device that contains two transistor s and their bias resistors. recalculate t j : cma w c ct j = ? ? ? ? ? ? ?? += 121 45.9)10( 54 70 2 uv and ov inputs: in floating appli cations these pins can not be used to monitor vin. connect uv to the vc pin and ov to the gnd pin to disable their function. maximum power dissipation at 121c: mw maonrdsiinpd 94545.9)10()( 2 2 max =?=?= power dissipation and junction temperature: first use figure 13 (junction temperature vs. input cu rrent) to find the final junction temperature at 10a load current and 70c ambient temperature. in figure 13 (illustrated in fi gure 22) draw a vertical line from 10a to intersect the ta=70c line. at the 10a and ta=70c line intersection draw a horizontal line towards the y-axis (junction temperature). the junction temperature at full load current (10a) and 70c ambient is 120c. rds(on) is 7.0m ? maxi mum at 25c and will increase as the junction temperature increases. from figure 11, at 120c rds(on) will increase by ~35%, then figure 23 : pi2125, 12v floating active oring application reverse current threshold: the following procedure demonstrates how to cal culate the minimum required reverse current in the internal mosfet to generate a reverse fault condition and turn off the internal mosfet. at room temperature (25c) typical rds(on): figure 22: example 1 fin al junction temperature at 10a/70c t a a m mv onrds reversevth reverseis 1.1 5.5 6 )( . . ?= ? = = =?= m monrds 45.935.10.7)( maximum at 120c at maximum junction temperature (121c) and maximum rds(on): ja rth : 54c/w ma m mv onrds reversevth reverseis 635 45.9 6 )( . . ?= ? = = )( 2 onrdsisrthtt ja aj ??+= picor corporation ? picorpower.com pi2125 rev 1.0 page 17 of 20 not recommended for new design
layout recommendation: use the following general guidelines when designing printed circuit boards. an example of the typical land pattern for the pi2125 in floating configuration is shown in figure 24: picor corporation ? picorpower.com pi2125 rev 1.0 page 18 of 20 ? make sure to have a sold ground (return) plane to reduce circuit parasitics. ? in floating configuration, connect the gnd pin to the s pins with a solid plane. in the event it can not be done on the top plane, create a plane on the second layer and use multiple vias from the s pins to the second layer to reduce parasitics. connect the sp pin directly to the pi2125 gnd pin to reduce parasitics between the sp pin and the gnd pin to avoid negative voltages on the sp pin with respect to the gnd pin. ? connect all s pads together with a wide trace to reduce trace parasitics to accommodate the high input current, and also connect all d pads together with a wide trace to accommodate the high output current. ? use 1oz of copper or thicker if possible to reduce trace resistance and reduce power dissipation. ? the vc bypass capacitor should be located as close as possible to the vc and gnd pins. place the pi2125 and bypass capacitor on the same layer of the board. the vc pin and c vc pcb trace should not contain any vias. ? keep the power source very close to s input pins, since any parasitic in the trace connecting the power source and s pins will have inductive kick back when there is high current flow in the trace and the mosfet turns off due to reverse current fault conditions. the inductive kick back will produce a high volt age across the mosfet. if it is not possible to connect the power source and s pins with a very short trace or common point, connect the capacitor (shown as c4 in figure 24) close to the s pins and return (ground). also for the same reason use c6, in figure 24 at the output. figure 25: pi2125 mounted on pi2125-eval2 please visit www.picorpower.com for information on pi2125-eval2 figure 24: pi2125 layo ut recommendation not recommended for new design
package drawing picor corporation ? picorpower.com pi2125 rev 1.0 page 19 of 20 thermal resistance ratings parameter symbol typical max unit junction-to-ambient (3) ja - 54 c/w junction-to-pcb jc 14 - c/w note 3: thermal resistance characte rized on pi2125-eval2 evaluation board with 0 lfm airflow. ordering information part number package transport media PI2125-00-LGIZ 5x7mm 17-pin lga tape & reel not recommended for new design
picor corporation ? picorpower.com pi2125 rev 1.0 page 20 of 20 warranty vicor products are guaranteed for two years from date of shipment against defects in material or workmanship whe n in normal use and service. this warranty does no t extend to products subjected to misuse, accident, or improper application or maintenance. vicor shall not be liable for collateral or consequential damage. this warranty is extended to the original purchaser only. except for the foregoing express warranty, vicor makes no warranty, express or limited, incl uding, but not limited to, the warranty of merchantability or fitness for a particular purpose. vicor will repair or replace defective products in accordance with its own best judgment. for service under this warra nty, the buyer must contact vicor to obtain a re turn material authorization (rma) number and shipping instructions. products returned without prior authorizati on will be returned to the buyer. the buyer will pay all charges incurred in returning the product to the factory. vicor will pay all reshipment charges if the product was defective within the terms of this warranty. information published by vicor has been carefully ch e cked and is believed to be accurate; however, no responsibility is assumed for inaccura cies. vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. vicor does not assume any liability arising out of the application or use of any product or ci rcuit; neither does it convey any licens e under its patent rights nor the rights of others. vicor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or in jury. per vicor terms and conditions of sale, the user of vicor components in life support applications assumes a ll risks of such use and indemnifies vicor against all damages. vicor?s comprehensive line of power solu tions includes high density ac-dc and dc-dc modules and accessory components, fully configurable ac-dc and dc-dc power supplies, and complete custom power systems. information furnished by vicor is believed to be accurate and reliable. however, no responsibility is assumed by vicor for its use. vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in inju ry or death. all sales are subject to vicor?s terms and conditions of sale, which are available upon request. specifications are subject to change without notice. vicor corpo ration picor corporation 25 fro ntage road 51 industrial drive andover, ma 0181 0 north smithfield, ri 02896 usa usa customer service: custserv@vicorpower.com technical support: apps@vicorpower.com tel: 800-735-6200 fax: 978-475-6715 not recommended for new design

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