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wed3el7216s, ddr sr wed3el7216s, ddr sr wed3el7216s, ddr sr wed3el7216s, ddr sr wed3el7216s, ddr sr am, 2.5v core/ 2.5v io am, 2.5v core/ 2.5v io am, 2.5v core/ 2.5v io am, 2.5v core/ 2.5v io am, 2.5v core/ 2.5v io #
$% advanced* features initialization general description core supply voltage = 2.5v +/- 0.2v io supply voltage = 2.5v +/- 0.2v bidirectional data strobe (dqs) internal, pipelined, double data rate architecture differential clock inputs positive edge; command execution dll for alignment of dq and dqs transitions four internal banks for concurrent operation data mask (dm) for masking write data programmable iol/ioh programmable burst length: 2,4, or 8 auto precharge option auto refresh and self refresh modes the white electronic designs ddr sdram (x72/80) is a syn- chronous dynamic random-access memory supporting data transfer on each of the clock edges within a single cycle, and is configured internally as a quad bank architecture which supports concurrent operations. the double data rate (ddr) architecture is referenced to as a 2n-pre-fetch architecture with an interface designed to transfer two data words per clock cycle. a single read or write access consists of a single 2n-bit wide, one clock cycle data transfer at the internal dram core and two cor- responding n-bit wide, one half clock cycle data transfers at the i/o pins. the wed3el7216s devices contain differential clock inputs; the crossing of ck going through its voltage transition to a high true, and ck\ going through its voltage transition to a low true references a positive edge. commands as well as address(s) and control(s) are registered on positive edges, data is registered on both edges as well as output data is referenced on both edges of the clock. read and write accesses to the ddr sdram are burst ori- ented; accesses start at a selected location and continue for a programmed number of locations, as defined by the programmable burst command. ddr sdrams must be initialized via properly powering up. operation and use of this device outside of established procedure(s) may result in undefined operation. power must be first applied to vcc and vccq simultaneously and then vref (and system vtt) must be applied after vccq in order to avoid device latch-up. vref may be applied any time af- ter vccq but is normally expected at coincidence with vtt. except for cke (clock enable) inputs are not recognized as valid until after vref is applied. cke is an sstl_2 input but will detect an lvcmos low level after vcc is applied. main- taining an lvcomos low level on cle during power-up is required to ensure that the dq and dqs outputs will be in the high-z state where they will remain until driven in a normal read operation. once the power supply, and ref- erence voltage is stable, the ddr sdram device re- quires 200us delay prior to execution of a command se- quence. once the 200us delay requirement has been meet, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a precharge all command should be applied. next a load mode register command is to be issued for the extended mode register (enabling the dll) followed by another load mode register command to be issued to reset the dll and program the operating parameters. two hundred (200) clock cycles are required between the dll reset and any read command. a precharge all command should then be applied, placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. additionally, a load mode register command for the mode register with the reset dll bit deactivated is required. following these requirements, the ddr sdram is ready for normal operation.

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programmable ioh/iol the normal full drive strength for all outputs are specified to be sstl class 2. the wed3el7216 supports an option for reduced drive. this option is intended for the support of the lighter load and or point-to-point environments. the command and placement of this device into reduced drive mode will place the output drive at ~54% of the sstl-2. deselect the deselect command prevents new commands from being executed by the wed3el7216s devices. no operation (nop) the nop command is used to instruct the selected ddr sdram device to perform idle or wait states. during these states, the ddr sdram device is unable to register new commands, operations already in progress are not affected. the mode registers are loaded via inputs a0-a11. the load mode register command can only be issued when all ddr sdram internal banks are idle. load mode register the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, ant the address pro- vided on inputs a0-a11 selects the row. the row remains active for accesses until a precharge command is issued. a precharge command must be issued before opening a different row in the same bank. active the read command is used to initiate a burst read ac- cess to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0- ax. addressed location of the array will drive its contents onto the dq?s or the device read the write command is used to initiate a burst write. input data appearing on the dq?s will be written into the address location of the array. write the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a speci- fied time (trp) after the precharge command is issued. precharge

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functional block diagram

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pin configuration

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bga locations symbol description f4, f16, g5, g15, ckx, ckx\ clock: ckx and ckx\ are differential clock inputs. all address and k1, k12, l2, l13, cont rol input signals are sampled on t he crossing of t he posit ive n6, m8 edge o f ckx and negat ive edge of ckx\. out put dat a ( dq? s and dqs) is referenced to the crossings of the differential clock inputs g4, g16, k2, k13 ckex clock enable: cke cont rols t he clock input s. cke high enables, m6 cke low disables the clock input pins. driving cke low pro-vides precharge power-down and self refresh operations, or active power-down. cke is synchronous for power-down ent ry and exit , and for self refresh ent ry cke is asynchronous for self refresh exit and for disabling the outputs. cke must be maintained high throughout read and writ e accesses. input buffers are disabled during power-down input buffers are disabled during self refresh. cke is an sstl-2 input but will det ect an lvcmos low level aft er vcc is applied g1, g13, k4, k16 csx\ chip select: csx\ enagles t he command regist er(s) of each of m12 t he five (5) cont ained words. all commands are masked when csx\ is registered high. csx\ provides for external bank selection on systems with multiple banks. csx\ is considered part of the command code. f4, f16, g5, g15, rasx\, casx\ command input s: rasx, casx, and wex\ define t he command k1, k12, l2, l13, wex\ being ent ered n7, m9 g4, g16, k2, k14 dqmlx, dqmhx input data mask. dm is an input mask signal for write data. m7 input dat a is masked when dqmlx or hx is sampled high at t ime of a write access. dm is sampled on bot h edges of dqslx and dqshx e8, e9 ba0, ba1 bank address inputs: ba0, ba1 define which bank an active read, write, or precharge command is being applied a7, a8, a9, a10, b7 a0-a11, a12 address input : provide the row address for active commands, and b8, b9, b10, c7, c8 t he column address and aut o precharge bit (a10) for read/write c9, c10, d7 commands to select one location out of the memory array int the respective bank. a10 sampled during a precharge command det ermines whether t he precharge applies t o one bank or all banks. t he address input s also provide t he op-code during a mode resi st er se t c o mma n d. pin descriptions

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pin descriptions bga locations symbol description a2, a3, a4, a13, a14 dq0-79 dat a i/o b1, b2, b3, b4, b13 b14, b15, b16, c1, c2,c3,c4,c13,c14, c15,c16,d1,d2,d3, d4,d13,d14,d15,d16 e1,e16,m1,m16,n1 n2,n3,n4,n13,n14, n15,n16,p1,p2,p3, p4,p13,p14,p15,p16 r1,r2,r3,r4,r13, r14,r15,r16,t2,t3, t4,t13,t14,t15,n7, n8,n9,n10,p7,p8,p9 p10,r7,r8,r9,r10 t7,t8,t9,t10 e6, e7, e10, e11, f5, dqslx, dqshx data strobe: output with read data, input with write data. dqs is k5,l12,n5,n12,e5 edge-aligned wit h read dat a, cent ered in writ e dat a. it is used to capture data. b11,b12,c5,c6,e3, vcc core power supply f3,g3,h3,h12,h16, j3,j12,j16,k3,l3,m3 p11,p12,r5,r6,t16 a11,a12,d5,d6,h4, vccq i/o power supply h15,j4,j15,t5,t6 a5,a6,a16,b5,b6, vss ground (digital) c11,c12,d11,d12, e14,f14,g14,h1,h2, h5,h13,h14,j1,j2,j5 j13,j14,k14,l14 p5,p6,r11,r12,t1, t11,t12, m14 e12 vref sstl-2 reference voltage

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mode register definition extended mode register definition

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recommended io consideration(s) x72 designs x80 designs

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mechanical

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power dissipation projections descriptions conditions symbol typ 7 75 8 units notes operating supply all inputs vil or vih; idd tbd 800 825 775 ma 1 current cycle time tkhkh (min) outputs open standby tkhkh = tkhkh (min) isb1 tbd 250 220 190 ma current device in nop state all addresses / data static capacitance max descriptions conditions sym typ units notes address; a0-a21 ca 10 pf input/output and io cntl: dqs, dqslx, dqshx cl,co 5 pf dqmlx, dqmhx ta = 25 c; f = 1mhz clocks; clkx, clkx\ cck 10 pf clock enable(s): ckex ccnt. 5 pf note(s): power calculated with outputs unloaded note(s): power calculated with outputs unloaded

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parameter symbol 7 7 75 75 8 8 access window of dqs from clkx / clkx\ tac -0.75 0.75 -0.75 0.75 -0.80 0.80 clkx high level width tch 0.45 0.55 0.45 0.55 0.45 0.55 clkx low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 clock cycle time tck 7.50 13.00 7.50 13.00 8.00 13.00 tck 7.50 13.00 10.00 13.00 10.00 13.00 dq and dm input hold time relative to dqs tdh 0.50 0.50 0.60 dq and dm input setup time relative to dqs tds 0.50 0.50 0.60 dq and dm input pulse width tdipw 1.75 1.75 2.00 access window of dqs frm clkx / clkx\ tdqsck -0.75 0.75 -0.75 0.75 -0.80 0.80 dqs input high pulse width tdqsh 0.35 0.35 0.35 dqs input low pulse width tdqsl 0.35 0.35 0.35 dqs-dq skew, dqs to last dq valid, per group, per access tdqsq 0.50 0.50 0.60 wrtie command to first dqs latching transition tdqss 0.75 1.25 0.75 1.25 0.75 1.25 dqs falling edge to clkx rising - setup time tdss 0.20 0.20 0.20 dqs falling edge to clkx rising - hold time tdsh 0.20 0.20 0.20 half clock period thp tch,tcl tch,tcl tch,tcl data-out high impedance window from clk/clk\ thz 0.75 0.75 0.80 data-out low impedance window from clk/clk\ tlz -0.75 -0.75 -0.80 address and control input hold time tih 0.90 0.90 1.10 address and control input setup time tis 1.00 1.00 1.10 load mode register tmrd 15.00 15.00 16.00 dq-dqs hold, dqs to first dq to go non-valid tqh thp - tqhs thp - tqhs thp - tqhs data hold skew factor tqhs 0.75 0.75 1.00 active to precharge command tras 40.00 120k 40.00 120k 40.00 120k active to read with auto precharge command trap tras (min) - (burst length x tclk/e) active to active/auto refresh command period trc 65.00 65.00 70.00 auto refresh command period trfc 75.00 75.00 80.00 active to read or write trcd 20.00 20.00 20.00 precharge command period trp 20.00 20.00 20.00 dqs read preamble trpre 0.90 1.10 0.90 1.10 0.90 1.10 dqs read postamble trpst 0.40 0.60 0.40 0.60 0.40 0.60 active bank to active bank b command trrd 15.00 15.00 15.00 dqs write preamble twpre 0.25 0.25 0.25 dqs write preamble setup time twpres 0.00 0.00 0.00 half clock period twpst 0.40 0.60 0.40 0.60 0.40 0.60 data-out high impedance window from clk/clk\ twr 15.00 15.00 15.00 data-out low impedance window from clk/clk\ trefc 140.60 140.60 140.60 address and control input hold time txsnr 75.00 75.00 80.00 address and control input setup time txsrd 200.00 200.00 200.00 ac electrical characteristics cl=2.5 cl = 2

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ordering information part number configuration technology frequency vcc temp wed3el7216s7es 16m x 72 sdram; ddr 133/266 mhz 2.5 eng. samples wed3el7216s75es 16m x 72 sdram; ddr 133/266 mhz 2.5 eng. samples wed3el7216s8es 16m x 72 sdram; ddr 100/200 mhz 2.5 eng. samples WED3EL7216S7BC 16m x 72 sdr am; ddr 133/266 mhz 2.5 0c - 70c wed3el7216s75bc 16m x 72 sdr am; ddr 133/266 mhz 2.5 0c - 70c wed3el7216s8bc 16m x 72 sdr am; ddr 100/200 mhz 2.5 0c - 70c

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