View HCTL-1101_7041500.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HCTL-1101 general purpose control ics. data sheet esd warning: normal handling precautions should be taken to avoid static discharge. description the HCTL-1101 series is a high performance, general purpose motion control ic, fabricated in avago cmos technology. it frees the host processor for other tasks by performing all the time-intensive functions of digital motion control. the programmability of all control para- meters provides maximum fexibility and quick design of control systems with a minimum number of components. in addition to the HCTL-1101, the complete control sys - tem consists of a host processor to specify commands, an amplifer, and a motor with an incremental encoder (such as the heds-5xxx, -6xxx, -9xxx series). no analog com - pensation or velocity feedback is necessary. note: HCTL-1101 series are a pin-to-pin and functionability compatible with the hctl-1100 series. customers are advised to evaluate the hctl- 1101 series for their production use. pinout features ? low power cmos ? pdip and plcc versions available ? dc, dc brushless, and step motor control ? position and velocity control ? programmable digital filter and commutator ? 8-bit parallel, and pwm motor command ports ? ttl compatible ? sync pin for coordinating multiple HCTL-1101 ics ? 100 khz to 2 mhz operation ? encoder input port. applications typical applications for the HCTL-1101 include printers, medical instruments, material handling machines, and industrial automation. HCTL-1101: 40 pin dip package HCTL-1101-plc: 44 pin plcc package
2 description HCTL-1101 max. supply current 30 ma max. power dissipation 165 mw max. tri-state output leakage current 5 a operating frequency 100 khz-2 mhz operating temperature range -20c to +85c storage temperature range -55c to +125c synchronize 2 or more ics yes preset actual position reg - isters yes read flag register yes limit and stop pins must be pulled up to vdd if not used. hard reset required plcc package available yes theory of operations the HCTL-1101 is a general purpose motor controller which provides position and velocity control for dc, dc brushless and stepper motors. the internal block dia - gram of the HCTL-1101 is shown in figure 1. the hctl- 1101 receives its input commands from a host processor and position feedback from an incremental encoder with quadrature output. an 8-bit bi-directional multiplexed ad - dress/data bus interfaces the HCTL-1101 to the host pro - cessor. the encoder feedback is decoded into quadrature counts and a 24-bit counter keeps track of position. the HCTL-1101 executes any one of four control algorithms selected by the user. the four control modes are: ? position control ? proportional velocity control ? trapezoidal profle control for point to point moves ? integral velocity control with continuous velocity profling using linear acceleration. the resident position profle generator calculates the nec - essary profles for trapezoidal profle control and integral velocity control. the HCTL-1101 compares the desired position (or velocity) to the actual position (or veloc - ity) to compute compensated motor commands using a programmable digital flter d(z). the motor command is externally available at the motor command port as an 8- bit byte and at the pwm port as a pulse width modulated (pwm) signal. the HCTL-1101 has the capability of providing electronic commutation for dc brushless and stepper motors. using the encoder position information, the motor phases are enabled in the correct sequence. the commutator is fully programmable to encompass most motor/encoder com - binations. in addition, phase overlap and phase advance can be programmed to improve torque ripple and high speed performance. the HCTL-1101 contains a number of fags including two externally available fags, profle and initialization, which allow the user to see or check the status of the controller. it also has two emergency inputs, limit and stop, which allow operation of the HCTL-1101 to be interrupted under emergency conditions. the HCTL-1101 controller is a digitally sampled data sys - tem. while information from the host processor is accept - ed asynchronously with respect to the control functions, the motor command is computed on a discrete sample time basis. the sample timer is programmable. system block diagram hctl- 1101 host processor amp m e
3 package dimensions
4 figure 1. internal block diagram. figure 2. operating mode flowchart.
5 electrical specifcation parameter symbol min. typ. max. units operating temperature t a -20 85 c storage temperature t s -55 125 c supply voltage v dd -0.3 7 v input voltage v in -0.3 v dd +0.3 v maximum operating clock frequency f clk 2 mhz dc electrical characteristics v dd = 5 v 5%; ta = -20c to +85c parameter symbol min. typ. max. units test conditions supply voltage v dd 4.75 5.00 5.25 v supply current i dd / i op 15 30 ma input leakage current i in 10 100 na v in = 0.00 and 5.25 v input pull-up current (ale, cs, oe, index, reset) i up -150 a v in = 0.00 v tristate output leakage current (addb/db) i oz 5 a v out = -0.3 to 5.25 input low voltage v il -0.3 0.8 v input high voltage v ih 2.0 vdd v output low voltage v ol -0.3 0.4 v iol = 2.2 ma , v dd = 4.5v output high voltage v oh 2.4 v dd v ioh = -200 a , v dd =4.5v power dissipation p d 165 mw input capacitance c in 20 pf output capacitance c out 100 pf
6 note: *general formula for determining ac characteristics for other clock frequencies (clk), between 100 khz and 2 mhz. ac electrical characteristics vdd = 5v + 5%; ta = -200c to +850c; units + nsec id # signal symbol clock frequency formula* 2 mhz 1 mhz min. max. min. max. min. max. 1 clock period (clk) t cper 500 1000 2 pulse width, clock high t cpwh 230 300 3 pulse width, clock low t cpwl 200 200 200 4 clock rise and fall time t cr 20 20 20 5 input pulse width reset t irst 2500 5000 5 clk 6 input pulse width stop, limit t ip 600 1100 1 clk + 100 ns 7 input pulse width index t ix 1600 3100 3 clk + 100 ns 8 input pulse width cha, chb t iab 1600 3100 3 cl + 100 ns 9 delay cha to chb transition t ab 600 1100 1 clk + 100 ns 10 input rise/fall time (cha, chb, index) t iabr 150 300 300(clk < 1 mhz) 11 input rise/fall time reset, ale, cs, oe, stop, limit t ir 20 20 20 12 input pulse width ale, cs t ipw 80 80 80 13 delay time, ale rise to cs rise t ca 50 50 50 14 address setup time before ale fall/rise t asr1 20 20 20 15 address setup time before cs fall/rise t asr 20 20 20 16 write data setup time before cs rise t dsr 20 20 20 17 address/data hold time t h 20 20 20 18 setup time, r/w before cs rise t wcs 20 20 20 19 hold time, r/w after cs rise t wh 20 20 20 20 delay time, write cycle, cs rise to ale fall t csal 1700 3400 3.4 clk 21 delay time, read/write, cs rise to cs fall t cscs 1500 3000 3 clk 22 write cycle, ale fall to ale fall for next write t wc 1850 3700 3.7 clk 23 delay time, cs rise to oe fall t csoe 1700 3200 3 clk + 200 ns 24 delay time, oe fall to data bus valid t oedb 100 100 100 25 input pulse width oe t ipwoe 100 100 100 26 hold time, data held after oe rise t doeh 20 20 20 27 delay time, read cycle, cs rise to ale fall t csalr 1820 3320 3 clk + 320 ns 28 read cycle, ale fall to ale fall for next read t rc 1950 3450 3 clk + 450 ns 29 output pulse width, prof, init, pulse, sign, pha-phd, mc port t of 500 1000 1 clk 30 output rise/fall time, prof, init, pulse, sign, pha-phd, mc port t or 10 100 20 150 10 150 31 delay time, clock rise to output rise (prof,init,pulse,sign,phase) t ep 300 300 300 32 pulse width, sync low t sync 9000 18000 18 clk
7 HCTL-1101 i/o timing diagrams input logic level values are the ttl logic levels vil = 0.8 v and vih = 2.0 v. output logic levels are vol = 0.4 v and voh = 2.4 v.
8 HCTL-1101 i/o timing diagrams there are three diferent timing confgurations which can be used to give the user fexibility to interface the HCTL-1101 to most microprocessors. see the i/o interface section for more details.
9 HCTL-1101 i/o timing diagrams
10 HCTL-1101 i/o timing diagrams
11 pin descriptions and functions input/output pins symbol pin number description pdip plcc ad0/db00- ad5/db5 2-7 3-8 address/data bus C lower 6 bits of 8-bit i/o port which are multiplexed between address and data. db6, db7 8, 9 9, 10 data bus C upper 2 bits of 8-bit i/o port used for data only. input signals symbol pin number description pdip plcc cha/chb 31, 30 34, 33 channel a, b C input pins for position feedback from an incremental shaft encoder. two channels, a and b, 90 degrees out of phase are required. index 33 36 index pulse C input from the reference or index pulse of an incremental encoder. used only in conjunction with the commutator. either a low or high true signal can be used with the index pin. see timing diagrams and encoder interface section for more detail. r/w 37 41 read/write C determines direction of data exchange for the i/o port. ale 38 42 address latch enable C enables lower 6 bits of external data bus into internal address latch. cs 39 43 chip select C performs i/o operation dependent on status of r/w line. for a write, the external bus data is written into the internal addressed location. for read, data is read from an internal location into an internal output latch. oe 40 44 output enable C enables the data in the internal output latch onto the external data bus to complete a read operation. limit 14 15 limit switch C an internal fag which when externally set, triggers an unconditional branch to the initialization/idle mode before the next control sample is executed. motor command is set to zero. status of the limit fag is monitored in the status register. stop 15 16 stop flag C an internal fag that is externally set. when fag is set during integral velocity control mode, the motor command is decelerated to a stop. reset 36 40 reset C a hard reset of internal circuitry and a branch to reset mode. extclk 34 37 external clock v dd 11, 35 12, 38 voltage supply C both v dd pins must be connected to a 5.0 volt supply. gnd 10, 32 1, 11, 23, 35 circuit ground sync 1 2 used to synchronize multiple HCTL-1101 sample timers. nc C 17, 39 not connected. these pins should be left foating.
12 output signal symbol pin number description pdip plcc mc0-mc7 18-25 20-22, 24-28 motor command port C 8-bit output port which contains the digital motor command adjusted for easy bipolar dac interfacing. mc7 is the most signifcant bit (msb). pulse 16 18 pulse C pulse width modulated signal whose duty cycle is proportional to the motor command magnitude. the frequency of the signal is external clock/100 and pulse width is resolved into 100 external clocks. sign 17 19 sign C gives the sign/direction of the pulse signal. pha-phd 26-29 29-32 phase a, b, c, d C phase enable outputs of the commutator. prof 12 13 profle flag C status fag which indicates that the controller is executing a profled position move in the trapezoidal profle control mode. init 13 14 initialization/idle flag C status fag which indicates that the controller is in the initialization/idle mode. pin functionality sync pin the sync pin is used to synchronize two or more ics. it is only valid in the init/idle mode (see operating the hctl- 1101). when this pin is pulled low, the internal sample tim - er is cleared and held to zero. when the level on the pin is returned to high, the internal sample timer instantly starts counting down from the programmed value. connecting all sync pins together in the system and puls - ing the sync signal from the host processor will synchro - nize all controllers. limit pin this emergency-fag input is used to disable the control modes of the HCTL-1101. a low level on this input pin causes the internal limit fag to be set. if this pin is not used, it must be pulled up to v dd . if it is not connected, the pin could foat low, and possibly trigger a false emergency condition. the limit fag, when set in any control mode, causes the HCTL-1101 to go into the initialization/ idle mode, clear - ing the motor command and causing an immediate mo - tor shutdown. when the limit fag is set, none of the three control mode fags (f0, f3, or f5) are cleared as the hctl- 1101 enters the initialization/idle mode. the user should be aware that these fags are still set before commanding the HCTL-1101 to re-enter one of the four control modes from initialization/idle mode. in general, the user should clear all control mode fags after the limit pin has been pulled low, then proceed. stop pin the stop fag afects the HCTL-1101 only in the integral velocity mode. when a low level is present on this emergency-fag input, the internal stop fag is set. if this pin is not used, it must be pulled up to v dd . if it is not connected, the pin could foat low, and possibly trigger a false emergency condition. when the stop fag is set, the system will come to a de - celerated stop and stay in this mode with a command velocity of zero until the stop fag is cleared and a new command velocity is specifed. notes on limit and stop flags stop and limit fags are set by a low level input at their respective pins. the fags can only be cleared when the input to the corresponding pin goes high, signifying that the emergency condition has been corrected, and a write to the status register (r07h) is executed. that is, after the emergency pin has been set and cleared, the fag also must be cleared by writing to r07h. any word that is writ - ten to r07h after the emergency pin is set and cleared will clear the emergency fag. the lower four bits of that word will also reconfgure the status register.
13 this topic is further discussed in the register section un - der motor command register r08h. pulse width modulation (pwm) output port (pulse, sign). the pwm port consists of the pulse and sign pins. the pwm port outputs the motor command as a pulse width modulated signal with the correct polarity. this topic is further discussed in the register section under pwm motor command register r09h. trapezoid profle pin (prof) the trapezoid profle pin is internally connected to soft - ware fag bit 4 in the status register. this fag is also rep - resented by bit 0 in the flag register (r00h). see the reg - ister section for more information. both the pin and the flag indicate the status of a trapezoid profle move. when the HCTL-1101 begins a trapezoid move, this fag is set by the controller (a high level appears on the pin), indicating the move is in progress. when the HCTL-1101 fnishes the move, this fag is cleared by the controller. note that the instant the fag is cleared may not be the same instant the motor stops. the fag indicates the com - pletion of the command profle, not the actual profle. if the motor is stalled during the move, or cannot physically keep up with the move, the fag will be cleared before the move is fnished. init/idle pin (init) this pin indicates that the HCTL-1101 is in the init/idle mode, waiting to begin control. this pin is internally connected to the software fag bit 5 in the status register r07h. this fag is also represented by bit 1 in the flag register (r00h) (see the register section for more information). commutator pins (pha-phd) these pins are connected only when using the commuta - tor of the HCTL-1101 to drive a brushless motor or step motor. the four pins can be programmed to energize each winding on a multiphase motor. encoder input pins (cha, chb, index) the HCTL-1101 accepts ttl compatible outputs from 2 and 3 channel incremental encoders such as the heds- 5xxx, 6xxx, and 9xxx series encoders. channels a and b are internally decoded into quadrature counts which increment or decrement the 24-bit position counter. for example, a 500-count encoder is decoded into 2000 quadrature counts per revolution. the position counter will be incremented when channel b leads channel a. the index channel is used only for the commutator and its function is to serve as a reference point for the internal ring counter. the HCTL-1101 employs an internal 3-bit state delay flter to remove any noise spikes from the encoder inputs to the HCTL-1101. this 3-bit state delay flter requires the encod - er inputs to remain stable for three consecutive clock ris - ing edges for an encoder pulse to be considered valid by the HCTL-1101s actual position counter (i.e., an encoder pulse must remain at a logic level high or low for three consecutive clock rising edges for the HCTL-1101s actual position counter to be incremented or decremented.) the designer should therefore generally avoid creating the en - coder pulses of less than 3 clock cycles. the index signal of an encoder is used in conjunction with the commutator. it resets the internal ring counter which keeps track of the rotor position so that no cumula - tive errors are generated. the index pin of the HCTL-1101 also has a 3-bit flter on its input. the index pin is active low and level transition sensitive. it detects a valid high- to-low transition and qualifes the low input level through the 3-bit flter. at this point, the index signal is internally detected by the commutator logic. this type of confgu - ration allows an index signal to be used to generate the reference mark for commutator operation as long as the ac specifcations for the index signal are met. motor command port (mc0mc7) the 8-bit motor command port consists of register r08h whose data goes directly to external pins mc0-mc7. mc7 is the most signifcant bit. r08h can be read and written to; however, it should be written to only during the initial - ization/idle mode. during any of the four control modes, the controller writes the motor command into r08h.
14 operations of the HCTL-1101 registers the HCTL-1101 operation is controlled by a bank of 64 8- bit registers, 35 of which are user accessible. these reg - isters contain command and confguration information necessary to properly run the controller chip. the 35 user- accessible registers are listed in tables 1 and 2. the regis - figure 3. register block. ter number is also the address. a functional block diagram of the HCTL-1101 which shows the role of the user-acces - sible registers is also included in figure 3. the other 29 registers are used by the internal cpu as scratch registers and should not be accessed by the user.
15 table 1. register reference by mode
16 notes: 1. consult appropriate section for data format and use. 2. upper 4 bits are read only. 3. writing to r0eh (lsb) latches all 24 bits. 4. reading r14h (lsb) latches data in r12h and r13h. 5. writing to r13h clears actual position counter to zero. 6. the scalar data is limited to positive numbers (00h to 7fh). 7. the commutator registers (r18h, r1ch, r1fh) have further limits which are discussed in the commutator section of this data sheet. 8. writing to r17h (r23d) latches all 24 bits (only in init/idle mode). table 1. (continued).
17 notes: 1. consult appropriate section for data format and use. 2. upper 4 bits are read only. 3. writing to r0eh (lsb) latches all 24 bits. 4. reading r14h (lsb) latches data in r12h and r13h. 5. writing to r13h clears actual position counter to zero. 6. the scalar data is limited to positive numbers (00h to 7fh). 7. the commutator registers (r18h, r1ch, r1fh) have further limits which are discussed in the commutator section of this data sheet. 8. writing to r17h (r23d) latches all 24 bits (only in init/idle mode). table 2. register reference table by register number
18 notes: 1. consult appropriate section for data format and use. 2. upper 4 bits are read only. 3. writing to r0eh (lsb) latches all 24 bits. 4. reading r14h (lsb) latches data in r12h and r13h. 5. writing to r13h clears actual position counter to zero. 6. the scalar data is limited to positive numbers (00h to 7fh). 7. the commutator registers (r18h, r1ch, r1fh) have further limits which are discussed in the commutator section of this data sheet. 8. writing to r17h (r23d) latches all 24 bits (only in init/idle mode). table 2. register reference table by register number
19 register descriptions C general control, output, filter, and commutator flag register (r00h) the flag register contains fags f0 through f5. this register is a read/write register. each fag is set and cleared by writ - ing an 8-bit data word to r00h. when writing to r00h, the upper four bits are ignored by the HCTL-1101, bits 0,1,2 specify the fag address, and bit 3 specifes whether to set (bit=1) or clear (bit=0) the addressed fag. flag descriptions f0 C trapezoidal profle flag C set by the user to execute trapezoidal profle control. the fag is reset by the control - ler when the move is completed. the status of f0 can be monitored at the profle pin and in status register r07h bit 4. f1 C initialization/idle flag C set/ cleared by the HCTL-1101 to indicate execution of the initialization/idle mode. the status of f1 can be monitored at the initialization/idle pin and in bit 5 of the status register (r07h). the user should not attempt to set or clear f1. f2 C unipolar flag C set/cleared by the user to specify bipo - lar (clear) or unipolar (set) mode for the motor command port. f3 C proportional velocity control flag C set by the user to specify proportional velocity control. f4 C hold commutator fag C set/ cleared by the user or au - tomatically by the align mode. when set, this fag inhib - its the internal commutator counters to allow open loop stepping of a motor by using the commutator. (see ofset register description in the commutator section.) f5 Cintegral velocity control C set by the user to specify in - tegral velocity control. also set and cleared by the hctl- 1101 during execution of the trapezoidal profle mode. this is transparent to the user except when the limit fag is set. (see emergency flags section). writing to the flag register when writing to the fag register, only the lower four bits are used. bit 3 indicates whether to set or clear a certain fag, and bits 0,1,and 2 indicate the desired fag. the fol - lowing table shows the bit map of the flag register: bit number function 7-4 don't care 3 1=set 0=clear 2 ad2 1 ad1 0 ad0 the following table outlines the possible writes to the flag register: flag set clear f0 08h 00h f1 - - f2 0ah 02h f3 0bh 03h f4 0ch 04h f5 0dh 05h reading the flag register reading register r00h returns the status of the fags in bits 0 to 5. for example, if bit 0 is set (logic 1), then fag f0 is set. if bit 4 is set, then fag f4 is set. if bits 0 and 5 are set, then both fags f0 and f5 are set. the following table outlines the flag register read bit number flag (1=set) (0=clear) 8-6 don't care 5 f5 4 f4 3 f3 2 f2 1 f1 0 f0 notes: 1. a soft reset (writing 00h to r05h) will not reset the fags in the fag register. a hard reset (reset pin low) is required to reset all the fags. the fags can also be reset by writing the proper word to the flag register as explained above. 2. while in trapezoid profle mode, flag f0 will be set, and flag f5 may be set. f5 is used for internal purposes. both fags will be cleared at the end of the profle. program counter register (r05h) the program counter, which is a write-only register, ex - ecutes the preprogrammed functions of the controller. the program counter is used along with the control fags f0, f3, and f5 in the flag register (r00h) to change control modes. the user can write any of the following four com - mands to the program counter.
20 HCTL-1101 writes values to register r08h. the motor command port operates in two modes, bipolar and unipolar, when under control of internal software. bi - polar mode allows the full range of values in r08h (-128d to +127d). the data written to the motor command port by the control algorithms is the internally computed 2s- complement motor command with an 80h ofset added. this allows direct interfacing to a dac. connecting the motor command port to a dac, bipolar mode allows the full voltage swing (positive and negative). unipolar mode functions such that with the same dac circuit, the motor command output is restricted to posi - tive values (80h to ffh) when in a control mode. unipolar mode is used with multi-phase motors when the commu - tator controls the direction of movement. (if needed, the sign pin could be used to indicate direction). in unipolar mode, the user can still write a negative value to r08h in init/idle mode. unipolar mode or bipolar mode is programmed by setting or clearing fag f2 in the flag register r00h. internally, the HCTL-1101 operates on data of 24, 16 and 8 bit lengths to produce the 8-bit motor command, avail - able externally. many times the computed motor com - mand will be greater than 8 bits. at this point, the motor command is saturated by the controller. the saturated value output by the controller is not the full scale value 00h (00d), or ffh (255d). the saturated value is adjusted to 0fh (15d) (negative saturation) and f0h (240d) (posi - tive saturation). saturation levels for the motor command port are in figure 4. pwm motor command register (r09h) the pwm port outputs the motor command as a pulse width modulated signal with the correct sign of polar - ity. the pwm port consists of the pulse and sign pins and r09h. the pwm signal at the pulse pin has a frequency of exter - nal clock/100 and the duty cycle is resolved into the 100 clocks. (for example, a 2 mhz clock gives a 20 khz pwm frequency.) the sign pin gives the polarity of the com - mand. low output on sign pin is positive polarity. the 2s-complement contents of r09h determine the duty cycle and polarity of the pwm command. for example, d8h (C40d) gives a 40% duty cycle signal at the pulse pin and forces the sign pin high. data outside the 64h (+100d) to 9ch (C100d) linear range gives 100% duty cycle. r09h can be read and written to. however, the user should only write to r09h when the controller is in the initialization/ idle mode. figure 5 shows the pwm output versus the in - ternal motor command. value written to r05h action 00h software reset 01h enter init/idle mode 02h enter align mode (only from init/idle mode) 03h enter control mode (only from init/ idle mode) these commands are discussed more detail in the oper - ating mode section. status register (r07h) the status register indicates the status of the HCTL-1101. each bit decodes into one signal. all 8 bits are user read - able and are decoded as shown below. only the lower 4 bits can be written to by the user to confgure the hctl- 1101. to set or clear any of the lower 4 bits, the user writes an 8-bit word to r07h. the upper 4 bits are ignored. each of the lower 4 bits directly sets/clears the corresponding bit of the status register as shown below. for example, writing xxxx0101 to r07h sets the pwm sign reversal inhibit, sets the commutator phase confguration to 3 phase, and sets the commutator count confguration to full. table 3. status register status bit function 0 pwm sign reversal inhibit : 0 = of 1 = on 1 commutator phase confguration : 0 = 3 phase 1 = 4 phase 2 commutator count confguration: 0 = quadrature 1 = full 3 should always be set to 0 4 trapezoidal profle flag f0: 1 = in profle control 5 initialization/idle flag f1 : 1 = in initialization/idle mode 6 stop flag : 0 = set (stop triggered) 1 = cleared (no stop) 7 limit flag : 0 = set (limit triggered) 1 = cleared (no limit) motor command register (r08h) the 8-bit motor command port consists of register r08h. the register is connected to external pins mc0-mc7. mc7 is the most signifcant bit. r08h can be read and written to; however, it should be written to only in the initializa - tion/idle mode. during any of the four control modes, the
21 figure 4. motor command port output. when any control mode is being executed, the unadjust - ed internal 2s-complement motor command is written to r09h. because of the hardware limit on the linear range (64h to 9ch, 100d), the pwm port saturates sooner than the 8-bit motor command port (00h to ffh, +127d to C128d). when the internal motor command saturates above 8 bits, the pwm port is saturated to the full 100% duty cycle level. figure 5 shows the actual values inside the pwm port. note that the unipolar fag, f2, does not afect the pwm port. for commutation of brushless motors with the pwm port, only use the pulse pin from the pwm port as the commu - tator already contains sign information. (see figure 9.) the pwm port has an option that can be used with h- bridge type amplifers. the option is sign reversal inhibit, which inhibits the pulse output for one pwm period after a sign polarity reversal. this allows one pair of transistors to turn of before others are turned on and thereby avoids a short across the power supply. bit 0 in the status register (r07h) controls the sign reversal.
22 figure 5. pwm port output. figure 6. sign reversal inhibit. actual position registers read, clear : r12h, r13h, r14h preset : r15h, r16h, and r17h the actual position register is accessed by two sets of reg - isters in the HCTL-1101. when reading the actual position from the HCTL-1101, the host processor will read registers r12h (msb), r13h, and r14h (lsb). when presetting the actual position register, the processor will write to regis - ters r15h (msb), r16h, and r17h (lsb). when reading the actual position registers, the order should be r14h, r13h, and r12h. these registers are latched, such that, when reading register r14h, all three bytes will be latched so that count data does not change while reading three separate bytes. when presetting the actual position register, write to r15h and r16h frst. when r17h is written to, all three bytes are simultaneously loaded into the actual position register. note that presetting the actual position registers is only allowed while the HCTL-1101 is in init/ idle mode. the actual position registers can be simultaneously cleared at any time by writing any value to r13h. digital filter registers zero (a) r20h pole (b) r21h gain (k) r22h all control modes use some part of the programmable digital flter d (z) to compensate for closed loop system stability. the compensation d (z) has the form: where: z = the digital domain operator k = digital flter gain (r22h) a = digital flter zero (r20h) b = digital flter pole (r21h)
23 the compensation is a frst-order lead flter which in com - bination with the sample timer t (r0fh) afects the dy - namic step response and stability of the control system. the sample timer, t, determines the rate at which the control algorithm gets executed. all parameters, a, b, k, and t, are 8-bit scalars that can be changed by the user any time. as shown in equations [2] and [3], the digital flter uses previously sampled data to calculate d(z). this old inter - nally sampled data is cleared when the initialization/idle mode is executed. in position control, integral velocity control, and trapezoi - dal profle control the digital flter is implemented in the time domain as shown below: where: n = current sample time n-1 = previous sample time mcn = motor command output at n mcn-1 = motor command output at n-1 xn = (command position Cactual position) at n xn-1 = (command position Cactual position) at n-1 in proportional velocity control the digital compensation flter is implemented in the time domain as: where: yn = (command velocity Cactual velocity) at n sample timer register (r0fh) the contents of this register set the sampling period of the hctl- 1101. the sampling period is: t = 16(t+1) (1/frequency of the external clock) [4] where: t = contents of register r0fh the sample timer has a limit on the minimum allowable sample time depending on the control mode being ex - ecuted. the limits are given in table 4 below. the minimum value limits are to make sure the internal programs have enough time to complete proper execu - tion. the maximum value of t (r0fh) is ffh (255d). with a 2 mhz clock, the sample time can vary from 64 sec to 2048 sec. with a 1 mhz clock, the sample time can vary from 128 sec to 4096 sec. digital closed-loop systems with slow sampling times will have lower stability and a lower bandwidth compared to similar systems with faster sampling times. this rule of thumb must be balanced by the needs of the veloc - ity range to be controlled. velocities are specifed to the HCTL-1101 in terms of quadrature encoder counts per sample time. hardware description the sample timer consists of a bufer and a decrement counter. each time the counter reaches 00h, the sampler timer value t (value written to r0fh) is loaded from the bufer into the counter, which immediately begins to dec - rement from t. writing to the sample timer register data written to r0fh will be latched into the internal buf - fer and used by the counter after it completes the pres - ent sample time cycle by decrementing to 00h. the next sample time will use the newly written data. reading the sample timer register reading r0fh gives the values directly from the decre - menting counter. therefore, the data read from r0fh will have a value anywhere between t and 00h, depending where in the sample time cycle the counter is. example : 1. on reset, the value of the timer is preset to 40h. 2. reading r0fh shows 3eh . . . 2bh . . . 08h . . . 3ch... . table 4.
24 synchronizing multiple axes synchronizing multiple axes with HCTL-1101s can be achieved by using the sync pin as explained in the pin discussion section. some users may not only want to syn - chronize several HCTL-1101s but also follow custom pro - fles for each axis. to do this, the user may need to write a new command position or command velocity during each sample time for the duration of the profle. in this case, data written to the HCTL-1101 has to be coordinated with the sample timer. this is so that only one command posi - tion or velocity is received during any one sample period, and that it is written at the proper time within a sample period. at the beginning of each sample period, the HCTL-1101 is performing calculations and executions. new command positions and velocities should not be written to the hctl- 1101 during this time. if they are, the calculations may be thrown of and cause unpredictable control. the user can read the sample timer register to avoid writ - ing too early during a sample period. since the sample timer register continuously counts down from its pro - grammed value, the user can check if enough time has passed in the sample period to insure the completion of the internal calculations. the length of time needed by the HCTL-1101 to do its calculations is given by the minimum limits of r0fh (sample timer register) as shown in table 4. for position control mode, the user should wait for the sample timer to count down 07h from its programmed value before writing the next command position or veloc - ity. if the programmed sample timer value is 39h, wait un - til the sample timer register reads 32h. writing between 32h and 00h will make the command information avail - able for the next sample period. commutator status register (r07h) commutator ring (r18h) x register (r1ah) y phase overlap (r1bh) ofset (r1ch) max. phase advance (r1fh) velocity timer (r19h) the commutator is a digital state machine that is confg - ured by the user to properly select the phase sequence for electronic commutation of multiphase motors. the com - mutator is designed to work with 2, 3, and 4-phase motors of various winding confgurations and with various en - coder counts. along with providing the correct phase en - able sequence, the commutator provides programmable phase overlap, phase advance, and phase ofset. phase overlap is used for better torque ripple control. it can also be used to generate unique state sequences which can be further decoded externally to drive more complex amplifers and motors. phase advance allows the user to compensate for the frequency characteristics of the motor/amplifer combination. by advancing the phas - es enable command (in position), the delay in reaction of the motor/amplifer combination can be ofset and higher performance can be achieved. phase ofset is used to adjust the alignment of the com - mutator output with the motor torque curves. by correctly aligning the HCTL-1101s commutator output with the motors torque curves, maximum motor output torque can be achieved. the inputs to the commutator are the three encoder sig - nals, channel a, channel b, and index and the confgura - tion data stored in registers. the commutator uses both channels and the index pulse of an incremental encoder. the index pulse of the encod - er must be physically aligned to a known torque curve lo - cation because it is used as the reference point of the rotor position with respect to the commutator phase enables. the index pulse should be permanently aligned during motor encoder assembly to the last motor phase. this is done by energizing the last phase of the motor during assembly and permanently attaching the encoder code - wheel to the motor shaft such that the index pulse is ac - tive as shown in figures 7 and 8. fine tuning of alignment for commutation purposes is done electronically by the ofset register (r1ch) once the complete control system is set up.
25 figure 7.index pulse alignment to motor torque curves. each time an index pulse occurs; the internal commuta - tor ring counter is reset to 0. the ring counter keeps track of the current position of the rotor based on the encoder feedback. when the ring counter is reset to 0, the com - mutator is reset to its origin (last phase going low, phase a going high) as shown in figure 10. the output of the commutator is available as pha, phb, phc, and phd. the HCTL-1101s commutator acts as the electrical equivalent of the mechanical brushes in a mo - tor. therefore, the outputs of the commutator provide only proper phase sequencing for bidirectional opera - tion. the magnitude information is provided to the mo - tor via the motor command and pwm ports. the outputs of the commutator must be combined with the outputs of one of the motor ports to provide proper dc brushless and stepper motor control. figure 9 shows an example of circuitry which uses the outputs of the commutator with the pulse output of the pwm port to control a dc brush - less or stepper motor. a similar procedure could be used to combine the commutator outputs pha-phd with a lin - ear amplifer interface output (figure 16) to create a linear amplifer system. the commutator is programmed by the data in the fol - lowing registers. figure 10 shows an example of the rela - tionship between all the parameters.
26 figure 8. codewheel index pulse alignment. figure 9. pwm interface to brushles dc motors. figure 10. commuter confgurations.
27 n f = full encoder counts/ revolution. v = velocity (revolutions/ second) the hold commutator fag (f4) in the flag register (r07h). when the values 0, 1, or 2 are written to the ofset reg - ister, phase a will be enabled. when the values 3, 4 or 5 are written to the ofset register, phase b will be enabled. and, when the values 6, 7, or 8 are written to the ofset register, phase c will be enabled. no values larger than the value programmed into the ring register should be pro - grammed into the ofset register. phase advance registers (r19h, r1fh) the velocity timer register and maximum advance regis - ter linearly increment the phase advance according to the measured speed for rotation up to a set maximum. the velocity timer register (r19h) contains scalar data which determines the amount of phase advance at a giv - en velocity. the phase advance is interpreted in the units set for the ring counter by bit #2 in r07h. the velocity is measured in revolutions per second. the maximum advance register (r1fh) contains scalar data which sets the upper limit for phase advance regard - less of rotor speed. figure 11 shows the relationship between the phase ad - vance registers. note: if the phase advance feature is not used, set both r19h and r1fh to 0. commutator constraints and use when choosing a three-channel encoder to use with a dc brushless or stepper motor, the user should keep in mind that the number of quadrature encoder counts (4x the number of slots in the encoders codewheel) must be an integer multiple (1x, 2x, 3x, 4x, 5x, etc.) of the number of pole pairs in the dc brushless motor or steps in a stepper motor. to take full advantage of the commutators over - lap feature, the number of quadrature counts should be at least 3 times the number of pole pairs in the dc brushless motor or steps in the stepper motor. for example, a 1.8, (200 step/revolution) stepper motor should employ at least a: 150 slot codewheel = 600 quadrature counts/revolution = 3 x 200 steps/revolution. there are several numerical constraints the user should be aware of to use the commutator. status register (r07h) bit #1- 0 = 3-phase confguration, pha, phb, and phc are active outputs. 1 = 4-phase confguration, pha C phd are active outputs. bit #2- 0 = rotor position measured in quadrature counts (4x decoding). 1 = rotor position measured in full counts (1 count = 1 codewheel bar and space.) bit #2 only afects the commutators counting method. this includes the ring register (r18h), the x and y regis - ters (r1ah & r1bh), the ofset register (r1ch), the velocity timer register (r19h), and the maximum advance register (r1fh). quadrature counts (4x decoding) are always used by the HCTL-1101 as a basis for position, velocity, and accelera - tion control. ring register (r18h) the ring register is defned as 1 electrical cycle of the com - mutator which corresponds to 1 torque cycle of the mo - tor. the ring register is scalar and determines the length of the commutation cycle measured in full or quadrature counts as set by bit #2 in the status register (r07h). the value of the ring must be limited to the range of 0 to 7fh. x register (r1ah) this register contains scalar data which sets the interval during which only one phase is active. y register (r1bh) this register contains scalar data which set the interval during which two sequential phases are both active. y is phase overlap. x and y must be specifed such that: x + y = ring/(# of phases) [5] these three parameters defne the basic electrical com - mutation cycle. ofset register (r1ch) the ofset register contains twos-complement data which determines the relative start of the commutation cycle with respect to the index pulse. since the index pulse must be physically referenced to the rotor, ofset performs fne alignment between the electrical and mechanical torque cycles. the hold commutator fag (f4) in the status register (r07h) is used to decouple the internal commutator counters from the encoder input. flag (f4) can be used in conjunction with the ofset register to allow the user to advance the commutator phases open loop. this tech - nique may be used to create a custom commutator align - ment procedure. for example, in figure 10, case 1, for a three-phase motor where the ring = 9, x = 3, and y = 0, the phases can be made to advance open loop by setting
28 figure 11. phase advance vs. motor velocity. the parameters of ring, x, y, and max advance must be positive numbers (00h to 7fh). additionally, the following equation must be satisfed: in order to utilize the greatest fexibility of the commuta - tor, it must be realized that the commutator works on a circular ring counter principle, whose range is defned by the ring register (r18h). this means that for a ring of 96 counts and a needed ofset of 10 counts, numerically the ofset register can be programmed as 0ah (10d) or aah (-86d), the latter satisfying equation 8. if bit #2 in the status register is set to allow the commuta - tor to count in full counts, a higher resolution codewheel may be chosen for precise motor control without violating the commutator constraints equation (equation 8). example: suppose you want to commutate a 3-phase 15 deg/step variable reluctance motor attached to a 192 count en - coder. 1. select 3-phase and quadrature mode for commutator by writing 0 to r07h. 2. with a 3-phase 15 degree/step variable reluctance motor the torque cycle repeats every 45 degrees or 8 times/revolution. 3. ring register = (4)(192) counts/revolution = 8/revolution = 96 quadrature counts = 1 commutation cycle 4 by measuring the motor torque curve in both directions, it is determined that an ofset of 3 mechanical degrees and a phase overlap of 2 mechanical degrees is needed.
29 to create the 3 mechanical degree ofset, the ofset regis - ter (r1ch) could be programmed with either a6h (-90d) or 06h (+06d). however, because 06h (+06d) would vio - late the commutator constraints equation 8, a6h (-90d) is used. for the purposes of this example, the velocity timer and maximum advance are set to 0. operation flowchart the HCTL-1101 executes any one of three setup routines or four control modes selected by the user. the three setup routines include: ? reset ? initialization/idle ? align. the four control modes available to the user include: ? position control ? proportional velocity control ? trapezoidal profle control ? integral velocity control the HCTL-1101 switches from one mode to another as a result of one of the following three mechanisms: 1. the user writes to the program counter. 2. the user sets/clears fags f0, f3, or f5 by writing to the flag register (r00h). 3. the controller switches automatically when certain initial conditions are provided by the user. this section describes the function of each setup routine and control mode and the initial conditions which must be provided by the user to switch from one mode to an - other. figure 12 shows a fowchart of the setup routines and control modes, and shows the commands required to switch from one mode to another. figure 12. operational flowchart.
30 setup modes hard reset executed by: ? pulling the reset pin low (required at power up) when a hard reset is executed (reset pin goes low), the following conditions occur: ? all output signal pins are held low except sign, data bus, and motor command. ? all fags (f0 to f5) are cleared. ? the pulse pin of the pwm port is set low while the reset pin is held low. after the reset pin is released (goes high) the pulse pin goes high for one cycle of the external clock driving the HCTL-1101. the pulse pin then returns to a low output. ? the motor command port (r08h) is preset to 80h (128d). ? the commutator logic is cleared. ? the i/o control logic is cleared. a soft reset is automatically executed. soft reset executed by: ? writing 00h to r05h, or ? automatically called after a hard reset when a soft reset is executed, the following conditions occur: ? the digital flter parameters are preset to a (r20h) = e5h (229d) b (r21h) = k (r22h) = 40h (64d) ? the sample timer (r0fh) is preset to 40h (64d). ? the status register (r07h) is cleared. ? the actual position counters (r12h, r13h, r14h) are cleared to 0. from reset mode, the HCTL-1101 goes automatically to initialization/idle mode. initialization/idle executed by: ? writing 01h to r05h, or ? automatically executed after a hard reset, soft reset, or ? limit pin goes low. the initialization/idle mode is entered either automati - cally from reset, by writing 01h to the program counter (r05h) under any conditions, or pulling the limit pin low. in the initialization/idle mode, the following occur: ? the initialization/idle fag (f1) is set. ? the pwm port r09h is set to 00h (zero command). ? the motor command port (r08h) is set to 80h (128d) (zero command). ? previously sampled data stored in the digital flter is cleared. it is at this point that the user should pre-program all the necessary registers needed to execute the desired control mode. the HCTL-1101 stays in this mode (idling) until a new mode command is given. align executed by: ? writing 02h to r05h the align mode is executed only when using the com - mutator feature of the HCTL-1101. this mode automati - cally aligns multiphase motors to the HCTL-1101s internal commutator. the align mode can be entered only from the initializa - tion/idle mode by writing 02h to the program counter register (r05h). before attempting to enter the align mode, the user should clear all control mode fags and set both the com - mand position registers (r0ch, r0dh, and r0eh) and the actual position registers (r12h, r13h, and r14h) to zero. after the align mode has been executed, the HCTL-1101 will automatically enter the position control mode and go to position zero. by following this procedure, the largest movement in the align mode will be one torque cycle of the motor. the align mode assumes: the encoder index pulse has been physically aligned to the last motor phase during encoder/motor assembly, the commutator parameters have been correctly preprogrammed (see the section called commutator for details), and a hard reset has been executed while the motor is stationary.
31 the align mode frst disables the commutator and with open loop control enables the frst phase (pha) and then the last phase (phc or phd) to orient the motor on the last phase torque detent. each phase is energized for 2048 sys - tem sampling periods (t). for proper operation, the motor must come to a complete stop during the last phase en - able. at this point the commutator is enabled and com - mutation is closed loop. the HCTL-1101 then automatically switches from the align mode to position control mode. control modes control fags f0, f3, and f5 in the flag register (r00h) de - ter-mine which control mode is executed. only one con - trol fag can be set at a time. after one of these control fags is set, the control modes are entered either auto - matically from align or from the initialization/idle mode by writing 03h to the program counter (r05h). position control mode flags: f0 cleared f3 cleared f5 cleared registers used: register function r00h r00d flag register r12h r18d read actual position msb r13h r19d read actual position r14h r20d read actual position lsb r0ch r12d command position msb r0dh r13d command position r0eh r14d command position lsb position control performs point-to-point position moves with no velocity profling. the user specifes a 24-bit posi - tion command, which the controller compares to the 24- bit actual position. the position error is calculated, the full digital lead compensation is applied and the motor com - mand is output. the controller will remain position-locked at a destination until a new position command is given. the actual and command position data is 24-bit twos- complement data stored in six 8-bit registers. position is measured in encoder quadrature counts.the command position resides in r0ch (msb), r0dh, r0eh (lsb). writ - ing to r0eh latches all 24 bits at once for the control algo - rithm. therefore, the command position is written in the sequence r0ch, r0dh and r0eh. the command registers can be read in any desired order. the actual position resides in r12h (msb), r13h, and r14h (lsb). reading r14h latches the upper two bytes into an internal bufer. therefore, actual position registers are read in the order of r14h, r13h, and r12h for correct in - stantaneous position data. the largest position move possible in position con - trol mode is 7fffffh (8,388,607d) quadrature encoder counts. proportional velocity mode flags: f0 cleared f3 set f5 cleared registers used: register function r00h r00d flag register r23h r35d command velocity lsb r24h r36d command velocity msb r34h r52d actual velocity lsb r35h r53d actual velocity msb proportional velocity control performs control of motor speed using only the gain factor, k, for compensation. the dynamic pole and zero lead compensation are not used. (see the digital filter section of this data sheet.
32 the command and actual velocity are 16-bit twos-com - plement words. the command velocity resides in registers r24h (msb) and r23h (lsb). these registers are unlatched which means that the command velocity will change to a new velocity as soon as the value in either r23h or r24h is changed. the registers can be read or written to in any order. the units of velocity are quadrature counts/sample time. to convert from rpm to quadrature counts/sample time, use the formula shown below: where: vq = velocity in quadrature counts/sample time vr = velocity in rpm n = 4 times the number of slots in the codewheel (i.e., quadrature counts). t = the HCTL-1101 sample time in seconds. (see the section on the HCTL-1101s sample timer regis - ter). because the command velocity registers (r24h and r23h) are internally interpreted by the HCTL-1101 as 12 bits of integer and 4 bits of fraction, the host processor must multiply the desired command velocity (in quadrature counts/sample time) by 16 before programming it into the HCTL-1101s command velocity registers.
33 the actual velocity is computed only in this algorithm and stored in scratch registers r35h (msb) and r34h (lsb). there is no fractional component in the actual ve - locity registers and they can be read in any order. the controller tracks the command velocity continuously until new mode command is given. the system behavior after a new velocity command is governed only by the system dynamics until a steady state velocity is reached. integral velocity mode flags: f0 cleared f3 cleared f5 set to begin move registers used: register function r00h r00d flag register r26h r38d acceleration lsb r27h r39d acceleration msb r3ch r60d command velocity integral velocity control performs continuous veloc - ity profling which is specifed by command velocity and command acceleration. figure 13 shows the capability of this control algorithm. the user can change velocity and acceleration any time to continuously profle velocity in time. once the speci - fed velocity is reached, the HCTL-1101 will maintain that velocity until a new command is specifed. changes be - tween actual velocities occur at the presently specifed linear acceleration. the command velocity is an 8-bit twos-complement word stored in r3ch. the units of velocity are quadrature counts/sample time. the conversion from rpm to quadrature counts/sample time is shown in equation 9. the command velocity regis - ter (r3ch) contains only integer data and has no fractional component. while the overall range of the velocity command is 8 bits, twos-complements, the diference between any two se - quential commands cannot be greater than 7 bits in mag - nitude (i.e., 127 decimal). for example, when the hctl- 1101 is executing a command velocity of 40h (+64d), the next velocity command must fall in the range of 7fh (+127d), the maximum command range, c1h (-63d), the largest allowed diference. the command acceleration is a 16-bit scalar word stored in r27h and r26h. the upper byte (r27h) is the integer part and the lower byte (r26h) is the fractional part pro - vided for resolution. the integer part has a range of 00h to 7fh. the contents of r26h are internally divided by 256 to produce the fractional resolution.
34 the units of acceleration are quadrature counts/sample time squared. to convert from rpm/sec to quadrature counts/[sample time]2, use the formula shown below: where: aq = acceleration in quadrature counts/[sample time]2 ar = acceleration in rpm/sec n = 4 times the number of slots in the codewheel (i.e.,quadrature counts) t = the HCTL-1101 sample time in seconds. (see the section on the HCTL-1101s sample timer regis - ter). because the command acceleration registers (r27h and r26h) are internally interpreted by the HCTL-1101 as 8 bits of integer and 8 bits of fraction, the host processor must multiply the desired command acceleration (in quadra - ture counts/[sample time]2) by 256 before programming it into the HCTL-1101s command acceleration registers. internally, the controller performs velocity profling through position control. figure 13. integral velocity modes. each sample time, the internal profle generator uses the information which the user has programmed into the command velocity register (r3ch) and the command ac - celeration registers (r27h and r26h) to determine the val - ue which will be automatically loaded into the command position registers (r0ch, r0dh, and r0eh). after the new command position has been generated, the diference between the values in the actual position registers (r12- r13h, and r14h) and the new value in the command posi - tion registers is calculated as the new position error. this new position error is used by the full digital compensation flter to compute a new motor command output by this sample time. the register block in figure 3 further shows how the internal profle generator works in integral ve - locity mode. in control theory terms, integral compensa - tion has been added and there-fore, this system has zero steady-state error. although integral velocity control mode has the advan - tage over proportional velocity mode of zero steady state velocity error, its disadvantage is that the closed loop sta - bility is more difcult to achieve. in integral velocity con - trol mode the system is actually a position control system and therefore the complete dynamic compensation d(z) is used. if the external stop fag f6 is set during this signaling an emergency situation, the controller automatically deceler - ates to zero velocity at the presently specifed acceleration factor and stays in this condition until the falg is cleared. the user then can specify new velocity profling data.
35 trapezoid profle mode flags: f0 set to begin move f3 cleared f5 cleared registers used: register function r00h r00d flag register velocity r07h r07d status register r12h r18d read actual position msb r13h r19d read actual position r14h r20d read actual position lsb r29h r41d final position lsb r2ah r42d final position r2bh r43d final position msb r26h r38d acceleration lsb r27h r39d acceleration msb r28h r40d maximum velocity trapezoid profle control performs point-to-point position moves and profles the velocity trajectory to a trapezoid or triangle. the user specifes only the desired fnal position, acceleration and maximum velocity. the controller com - putes the necessary profle to conform to the command data. if maximum velocity is reached before the distance halfway point, the profle will be trapezoidal; otherwise the profle will be triangular. figure 14 shows the possible trajectories with trapezoidal profle control. the command data for trapezoidal profle control mode consists of a fnal position, command acceleration, and a maximum velocity. the 24-bit twos-complement fnal position is written to registers r2bh, (msb), r2ah, and r29h (lsb). the 16-bit command acceleration resides in registers r27h (msb) and r26h (lsb). the command ac - celeration has the same integer and fraction format as dis - cussed in the integral velocity control mode section. the 7-bit maximum velocity is a scalar value with the range of 00h to 7fh (0d to 127d). the maximum velocity has the units of quadrature counts per sample time, and resides in register r28h. the command data registers may be read or written to in any order.
36 the internal profle generator produces a position profle using the present command position (r0ch-r0eh) as the starting point and the final position (r2bh-r29h) as the end point. once the desired data is entered, the user sets fag f0 in the flag register (r00h) to commence motion (if the hctl- 1101 is already in position control mode). when the profle generator sends the last position com - mand to the command position registers to complete the trapezoidal move, the controller clears fag f0. the hctl- 1101 then automatically goes to position control mode with the fnal position of the trapezoidal move as the com - mand position. when the HCTL-1101 clears fag f0 it does not indicate that the motor and encoder are at the fnal position nor that the motor and encoder have stopped. the fag indi - cates that the command profle has fnished. the motor and encoders true position can only be determined by reading the actual position registers. the only way to de - termine if the motor and encoder have stopped is to read the actual position registers at successive intervals. figure 14. trapezoidal profle mode. the status of the profle fag can be monitored both in the status register (r07) and at the external profle pin at any time. while the profle fag is high no new command data should be sent to the controller. each sample time, the internal profle generator uses the information which the user has programmed into the maximum velocity register (r28h), the command accel - eration registers (r27h and r26h), and the final position registers (r2bh, r2ah, and r29h) to determine the value which will be automatically loaded into the command position registers (r0eh, r0dh, and r0ch). after the new command position has been generated, the diference between the value in the actual position registers (r12h, r13h, and r14h) and the new value in the command posi - tion registers is calculated as the new position error. this new position error is used by the full digital compensa - tion flter to compute a new motor command output for the sample time. (the register block diagram in figure 3 further shows how the internal profle generator works in trapezoidal profle mode.)
37 applications of the HCTL-1101 interfacing the HCTL-1101 to host processors the HCTL-1101 looks to the host microprocessor like a bank of 8-bit registers to which the host processor can read and write (i.e., the host processor treats the hctl- 1101 like ram). the data in these registers controls the operation of the HCTL-1101. the host processor commu - nicates to the HCTL-1101 over a bidirectional multiplexed 8-bit data bus. the four i/o control lines. ale, cs, oe, and r/w execute the data transfer (see figure 15). there are three diferent timing confguration which can be used to give the user greater fexibility to interface hctl- 1101 to most microprocessors (see timing diagrams). they are diferentiated from one another by the arrangement of the ale signal with respect to the cs signal. the three timing confguration are listed below: ? ale, cs non-overlapped ? ale, cs overlapped ? ale within cs any i/o operation starts by asserting the ale signal which starts sampling the external bus into an internal address latch. rising ale or falling cs during ale stops the sam - pling into the address latch. cs low after rising ale samples the external bus into the data latch. rising cs stops the sampling into the data latch, and starts the internal synchronous process. in the case of a write, the data in the data latch is written into the addressed location. in the case of a read, the ad - dressed location is written into an internal output latch.
38 above the minimums shown in table 5 the user may per - form 16 additional i/o operations per sample time. interfacing the HCTL-1101 to amplifers and motors the motor command port is the ideal interface to an 8- bit dac, confgured for bipolar output. the data written to the 8-bit motor command port by the control algorithms is the internally computed 2s-complement motor com - mand with an 80h ofset added. this allows direct inter - facing to a dac. figure 16 shows a typical dac interface to the HCTL-1101. an inexpensive dac, such as mc1408 or equivalent, has its digital inputs directly connected to the motor command port. the dac pro-duces an output current which is converted to a voltage by an operational amplifer. ro and rg control the analog ofset and gain. the circuit is easily adjusted for +5 v to C5 v operations by frst writing 80h to r08h and adjusting ro for 0 v output. then ffh is written to r08h and r is adjusted until the output is 5 v. note that 00h in r08h corresponds to C5 v out. figure 17 shows an example of how to interface the HCTL-1101 to an h-bridge amplifer. an h-bridge ampli - fer allows bipolar motor operation with a unipolar power supply. table 5. maximum number of i/o allowed oe low enables the internal outputs latch onto the exter - nal bus. the oe signal and the internal output latch allow the i/o port to be fexible and avoid bus conficts during read operations. it is important that the host microprocessor does not attempt to perform too many i/o operations in a single sample time of the HCTL-1101. each i/o operation inter - rupts the execution of the HCTL-1101s internal code for 1 clock cycle. although extra clock cycles have been allotted in each sample time for i/o operations, the number of extra cycles is reduced as the value programmed into the sample tim - er register (r0fh) is reduced. table 5 shows the maximum number of i/o operations al - lowed under the given conditions. the number of external clock cycles available for i/o oper - ations in any of the four control modes can be increased by increasing the value in the sample timer register (r0fh). for every unit increase in the sample timer register (r0fh)
39 figure 16. linear amplifer interface. figure 17. h-bridge amplifer interface. figure 15. i/o port block diagram. v cc v ref+ i o v ee comp v ref+ gnd a 8 (lsb) a 7 a 6 a 5 a 4 a 3 a 2 a 1 (msb) 15 2 2.5 k 13 14 2.5 k +5 v 4 3 ?12 v 75 pf 16 18 12 19 11 20 10 21 9 22 8 23 7 24 6 25 5 mc1408 (lsb) mc 0 mc 1 mc 2 mc 3 mc 4 mc 5 mc 6 (msb) mc 7 HCTL-1101 +5 v 5 k r o 5 k r l v out 6 2 3 x? x+ lf356 1 2 3 4 5 6 7 8 9 10 11 12 rc v cc ph oe a k logic k a udn2954w sign pulse dc motor +v motor +5 v 10 f 30 k
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2009 avago technologies. all rights reserved. av02-1257en - september 30, 2009 additional information from avago technologies application notes and application briefs regarding the HCTL-1101 are from the avago technologies motion con - trol factory. please contact your local avago sales representative for more information. ordering information HCTL-1101: 40 pin dip package HCTL-1101 #plc: 44 pin plcc package

▲Up To Search▲

Price & Availability of HCTL-1101

	To Download HCTL-1101 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .