description: the memory stack? series is a family of interchangeable memory moduels. the 256 megabit double data rate synchronous dram module is a member of this family which utilizes the space saving lp-stack? tsop stacking technology. the devices are constructed with two 32 meg x 4 ddr sdrams. this 128 megabit based lp-stack? module, dpdd64mx4tsay5, has been designed to fit in the same footprint as the 32 meg x 4 ddr sdram tsop monolithic. this allows system upgrade without electrical or mechanical redesign, providing an immediate and low cost memory solution. features: configuration available: 64 meg x 4 (2 banks of 8 meg x 4 bits x 4 banks) clock frequency: 100, 125, 133, 143, 167 mhz (max.) 2.5 volt dq supply jedec standard sstl_2 interface for all inputs/outputs four bank operation programmable burst type: burst length and read latency refresh: 4096 cycles/64ms refresh types: auto and self ipc-a-610 manufacturing standards jedec approved footprint and pinout package: 66-pin leaded tsop stack (top view) 60 n.c. vdd 1 2 54 n.c. vddq 3 53 n.c. 4 52 vssq dq0 5 51 dqs vssq 6 50 n.c. n.c. 7 49 vref 8 48 vss vddq 9 47 n.c. 10 46 ck dq1 11 45 ck vssq 12 44 cke0 n.c. 13 43 cke1 n.c. 14 42 n.c. vddq 15 41 a11 n.c. 16 40 a9 n.c. 17 39 a8 vdd 18 38 a7 *nu/qfc 19 37 a6 n.c. 20 36 a5 we 21 35 a4 cas 22 34 vss ras 23 59 n.c. cs0 24 58 vssq cs1 25 57 n.c. ba0 26 56 dq2 ba1 27 55 vddq n.c. n.c. dm n.c. 33 vdd 32 a3 31 a2 30 a1 29 a0 28 a10/ap vddq 61 dq3 62 n.c. 63 vssq 64 n.c. 65 vss 66 1 30a234-00 rev. d 3/02 this document contains information on a product that is currently released to production at dpac technologies. dpac reserves the right to change products or specifications herein without prior notice. 256 megabit cmos ddr sdram dpdd64mx4tsay5 dm cas we dq0-dq3 cs0 ras ck dqs cs1 ck a0-a11 vref cke1 cke0 ba0-ba1 *qfc (8 meg x 4 bits x 4 banks) 128 mb ddr sdram (8 meg x 4 bits x 4 banks) 1 pin-out diagram advanced components packaging * this pin is a no connect for some manufacturers. a0-a11 row address: a0-a11 column address: a0-a9, a11 ba0,ba1 bank select address a10/ap auto precharge dq0-dq3 data in/data out cas column address strobe cs0, cs1 chip selects ras row address strobe we data write enable ck, ck differential clock inputs cke0, cke1 clock enables dqs data strobe dm data mask qfc dq fet switch control v dd power supply (+2.5v) vss ground v ddq dq power supply (+2.5v) vss q dq ground v ref reference voltage for inputs n.c. no connect nu not used, electrical connect is present pin names functional block diagram
20 15 dp xx - cas double data rate synchronous dram prefix cas latency 1.5 cas latency 2.0 dd 64m x 4 y5 package memory desig memory type memory module without support logic depth width desig t 128 megabit based stackable tsop manufacturer code * xx - mfr id supplier dp supplier code * i/o type s sstl inputs/outputs width device a x4 memory based cas latency 3.0 30 cycle xx time latency 60 6ns (166mhz) 7ns (143mhz) 7.5ns (133mhz) 8ns (125mhz) 10ns (100mhz) 10 75 08 70 cas latency 2.5 25 ordering information 30a234-00 rev. d 3/02 2 1 .015 [.18] .0256 [.65] .102 max pin 1 index top view side view bottom view end view .502.008 .885.010 .427 [10.85] .417 [10.59] .527 [13.39] .517 [13.13] .0256 [.65] bsc .016 [.41] standard tsop pad layout is acceptable, however, when possible, the following pad layout is recommended for optimal manufacture and inspection. see application note 53a001-00 for further information. [12.75.20] [22.48.25] [2.59 max] .819 [20.80] bsc .020 [.51] typ typ dpac technologies products & services for the integration age 7321 lincoln way, garden grove, ca 92841 te l 714 898 0007 fax 714 897 1772 www.dpactech.com nasdaq: dpac ?2001 dpac technologies, all rights reserved. dpac technologies?, memory stack?, system stack?, cs stack? are trademarks of dpa c technologies corp. dpdd64mx4tsay5 256 megabit cmos ddr sdram mechanical drawing * contact your sales representative for supplier and manufacturer codes.
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