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| ? msm64p155 user's manual cmos 4-bit microcontroller first edition issue date: mar. 1996
notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 1996 oki electric industry co., ltd. printed in japan preface msm64p155 is a 4-bit microcontroller, which uses built-in one time prom (otp) in place of built-in mask rom in msm64155a. msm64p155 is manufactured with the n-well eprom process instead of the p-well cmos process. that is why the polarity of msm64p155's power supply is different than the polarity of the chip with the p-well cmos structure. otp version chips alone are not supplied to custom- ers. this manual explains the specific hardware of msm64p155 and the differences from the mask rom version of msm64155a. see "msm64155 user's manual" for further reference relating to other hardware and instruction set. table of contents chapter 1 general description 1.1 overview ................................................................................................................. 1-1 1.2 features .................................................................................................................. 1- 1 1.3 block diagram ........................................................................................................ 1-3 1.4 pin configuration .................................................................................................... 1-4 1.5 explanation of pins ................................................................................................. 1-5 1.5.1 explanation of each pin ................................................................................ 1-5 1.5.2 prom-related pins .................................................................................... 1-10 1.5.3 processing of unused pins ........................................................................ 1-11 chapter 2 power supply system 2.1 overview ................................................................................................................. 2-1 2.2 power supply system circuit configuration .......................................................... 2-2 2.3 logic power supply and backup circuits .............................................................. 2-3 2.3.1 configuration of logic power supply ........................................................... 2-3 2.3.2 operations of optional 1.5v logic power supply circuits ........................... 2-4 2.3.3 operations of optional 3.0v logic power supply circuits ........................... 2-4 chapter 3 crystal oscillation circuit 3.1 overview ................................................................................................................. 3-1 3.2 configuration of crystal oscillation circuit ............................................................ 3-1 chapter 4 prom 4.1 overview ................................................................................................................. 4-1 4.2 explanation of pins ................................................................................................. 4-1 4.3 prom mode ........................................................................................................... 4-3 4.3.1 setting the prom mode .............................................................................. 4-3 4.3.2 prom mode functions ................................................................................ 4-3 4.3.3 connection to the eprom writer ................................................................. 4-4 chapter 5 tst3 pin 5.1 overview ................................................................................................................. 5-1 5.2 registers to be changed by tst3 ........................................................................ 5-3 appendixes appendix a package dimensional drawing .................................................... appendix-1 appendix b electrical characteristics ............................................................. appendix-2 chapter 1 general description 1-1 chapter 1 chapter 1 chapter 1 chapter 1 chapter 1 general description general description general description general description general description 1.1 overview msm64p155 is a microcontroller which uses built-in one time prom (otp) in place of built-in rom of msm64155a. since the msm64p155 has a different configuration of the mask rom with p-well cmos configuration, it is manufactured with the n-well eprom process. that is why the polarity of the power source used for lcd bias generation is reversed, and the arrangement of additional circuits is different from the arrangement of this chip. in addition, unlike the mask rom version, the prom (otp version) chip alone has no supply. for these reasons, this otp version of msm64p155 should be used mainly for verification of application program functions. the msm64p155 has two operation modes; microcontroller operation mode and prom mode. the microcontroller operation mode is a mode to make the same operation as a mask rom and the prom mode is a mode to write/read prom. the descriptions on the microcontroller operation mode are omitted in this manual. therefore, see "msm64155a user's manual". this manual explains different specifications from the mask rom version in chapters 2 and 3, and chapter 4 explains the prom mode. 1.2 features 1) a rich set of instructions including byte calculating instructions ? 148 types of instructions ? byte addition and subtraction, byte transmission, byte comparing instructions ? bit operation instructions ? data exchange instructions 2) rich addressing modes ? two types of indirect addressing modes for hl registers and xy registers ? bit operations for all data memory areas ? byte calculation for all data memory areas 3) operating frequency : crystal oscillation at 32.768 khz (minimum instruction execution time: 91 m s) : rc oscillation at about 32 khz 4) built-in program memory : 4064 bytes (prom) 5) built-in data memory : 256 nibbles 1-2 6) i/o ports : a total of 18 ports ? 4 bit input-output ports (selectable open drain output/cmos output, selectable additional pull-down resistance input) 2 ? 2-bit input port (selectable additional pull-down resistance input) ? 4-bit input port (selectable additional pull-down resistance input) ? 4-bit output port (cmos output) 7) melody output: 2 outputs 8) lcd driver: a total of 64 drivers ? common driver 4 ? segment driver 60 ? 1/4 duty, during 1/3 bias: 240 segments (60 4) ? 1/3 duty, during 1/3 bias: 180 segments (60 3) 9) event counter: 1 channel 10) interrupt sources: 10 sources ? four external sources, four time base sources, two melody sources (when tst3="1", six time base sources) 11) external appearance ? flat package with 100 pins product name: msm64p155-ngs-bk (blanked prom) MSM64P155L-NGS-BK (blanked prom) msm64p155-xxxgs-bk (written prom) msm64p155l-xxxgs-bk (written prom) 12) operating power supply voltage: (mask option) 1.5 v : msm64p155 3.0 v : msm64p155l 13) clock generation circuit (mask option) ? crystal/rc oscillation 1-3 1.3 block diagram figure 1-1 shows the block diagram of msm64p155. bsr halt mief tr2 tr0 tr1 c alu ba pcm pcl (4) (4) (4) pch hl xy a11~a8 a7~a0 db7~0 (8) vdd1 vdd2 vdd3 c1 c2 bias prom 4064b program data/address com1 lcd ram 256n port address md0 md1 md0 md0 md1 md1 ir intc (8) romr sp clk rst tst timing controller tbc i?r decoder db7~0 port address capr port2 event port3 port6 port7 osc0 osc1 reset tst1 tst2 tst3 p2.0 p2.1 p2.2 p2.3 p3.0 p3.1 p6.0 p6.1 p6.2 p6.3 p7.0 p7.1 p7.2 p7.3 items inside the dotted line indicate the cpu core (nx-4/20). vpp int int com2 com3 com4 seg0 seg59 int 4 int int int int vss port4 p4.0 p4.1 p4.2 p4.3 figure 1-1 block diagram of msm64p155 1-4 1.4 pin configuration figure 1-2 shows the pin configuration of msm64p155. figure 1-2 pin configuration of msm64p155 (qfp) note: please do not connect anything to the nc pin. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 vdd1 vdd2 vdd3 c1 c2 com1 com2 com3 com4 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 reset osc0 osc1 vpp p2.3 p2.2 p2.1 p2.0 p3.1 p3.0 p4.3 p4.2 p4.1 p4.0 p6.3 p6.2 p6.1 p6.0 p7.3 p7.2 p7.1 p7.0 vss md0 md0 md1 md1 tst3 tst2 tst1 seg59 seg58 seg57 seg56 seg55 seg54 seg53 seg52 seg51 (nc) seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 1-5 1.5 explanation of pins 1.5.1 explanation of each pin table 1-1 shows basic functions of each of the msm64p155 pins and table 1-2 shows their secondary functions. table 1-1 (a) explanation of pins (basic functions) type pin name pin no. function power supply vss 23 digital 0v power supply digital plus side power supply (for 1.5v specs) lcd drive bias output (for 3.0v specs) vdd1 100 digital plus side power supply (for 3.0v specs) lcd drive bias output (for 1.5v specs) vdd2 99 vdd3 98 lcd drive bias output (+4.5v) c1 97 lcd drive bias generating condenser connection pin c2 96 vpp 4 plus side power supply for prom writing (+12.5v) osc0 2 input clock oscillation pin: connect to crystal oscillator (32.768 khz) and condenser (10 pf~30 pf) or resistor (1m w ) are connected. osc1 3 output oscillation tst1 30 input input pin for tests these are pulled down to vss internally. tst2 29 input tst3 28 input test reset 1 input system reset input: when this pin reaches the level "l" t "h", internal status initialization is conducted and instructions are executed from address 000h. built-in pull-down resistance on vss. input/ output reset when this pin is set to "h" level, the 256hz and 4hz interrupts are enabled, and the msm64p155 can be used as an otp version of the msm64152a, msm64153a and msm64158a. 1-6 table 1-1 (b) explanation of pins (basic functions) type pin name pin no. function port p2.0 8 input 4-bit input port (port 2): this is a 4-bit input port permitting selection of the pull-down resistance input/high impedance input for each bit through the controller register of port 2 (p2con). its secondary functios are trigger input of capture circuits and an external interrupt function. also, system reset is run when p2.0~p2.3 reach the "h" level. p2.1 7 p2.2 6 p2.3 5 p3.0 10 input 2-bit input port (port 3): this is a 2-bit input port permitting selection of the pull-down resistance input/high impedance input through the controller register of port 3 (p3con). its secondary functions are input functions for the event counter by p3.1 and an external interrupt by p3.0. p3.1 9 p6.0 18 input/ output 4-bit input/output port (port 6): this is a 4-bit input/output port permitting selection of input/output through the controller register (p6con) of port 6 (p6con), selection of the pull-down resistance input/high impedance input during input, and selection of open drain output/cmos output during output operations. its secondary function is to allocate external interrupt functions. input/ output p6.1 17 p6.2 16 p6.3 15 p7.0 22 input/ output 4-bit input/output port (port 7): this is a 4-bit input/output port permitting selection of input/output through the controller register of port 7 (p7con), selection of the pull-down resistance input/high impedance input during input, and selection of open drain output/cmos output during output. its secondary function is external interrupt function. p7.1 21 p7.2 20 p7.3 19 md0 25 output this is the output pin of melody driver 0. md0 24 output this is the reversed phase output pin for md0 output. md1 26 output this is the output pin of melody driver 1. md1 27 output this is the reversed phase pin of md1 output. melody driver com1 95 output these are the lcd common signal output pins. lcd driver com2 94 output com3 93 output com4 92 output p4.0 14 output 4-bit output port (port 4): this is a 4-bit cmos output port. p4.1 13 p4.2 12 p4.3 11 1-7 table 1-1 (c) explanation of pins (basic functions) type pin name pin no. function lcd driver seg0 91 output lcd segment signal output pins input/ output seg1 90 output seg2 89 output seg3 88 output seg4 87 output seg5 86 output seg6 85 output seg7 84 output seg8 83 output seg9 82 output seg10 81 output seg11 80 output seg12 79 output seg13 78 output seg14 77 output seg15 76 output seg16 75 output seg17 74 output seg18 73 output seg19 72 output seg20 71 output seg21 70 output seg22 69 output seg23 68 output seg24 67 output seg25 66 output seg26 65 output seg27 64 output seg28 63 output seg29 62 output seg30 61 output seg31 60 output seg32 59 output seg33 58 output seg34 57 output seg35 56 output 1-8 table 1-1 (d) explanation of pins (basic functions) type pin name pin no. function lcd driver seg36 55 output lcd segment signal output pins input/ output seg37 54 output seg38 53 output seg39 52 output seg40 51 output seg41 50 output seg42 49 output seg43 48 output seg44 47 output seg45 46 output seg46 45 output seg47 44 output seg48 43 output seg49 42 output seg50 41 output seg51 39 output seg52 38 output seg53 37 output seg54 36 output seg55 35 output seg56 34 output seg57 33 output seg58 32 output seg59 31 output (nc) 40 1-9 table 1-2 explanation of pins (secondary functions) type pin name pin no. function external interrupt p2.0 8 input secondary functions of p2.0~p2.3: an external interrupt input pin which enables reception through a modified level. also enables selection between allowed/prohibited for each bit interrupt through the p2 interrupt enable register (p21e). the system reset mode is activated after all p2.0~p2.3 pins reached the "h" level for at least two seconds. secondary functions of p2.0 and p2.1: trigger input pin for capture circuits. input/ output p2.1 7 p2.2 6 p2.3 5 p3.0 10 input secondary function of p3.0: external interrupt input pin reception of rising and falling edge signal and rising/falling signal enable on both edges by external interrupt input pins. p6.0 18 input secondary function of p6.0~p6.3: an external interrupt input pin which enables reception through a modified level. p6.1 17 p6.2 16 p6.3 15 p7.0 22 input secondary function of p7.0~p7.3: an external interrupt input pin which enables reception through a modified level. p7.1 21 p7.2 20 p7.3 19 p3.1 9 input secondary function of p3.1: input pin for event counter. event counter input 1-10 1.5.2 prom-related pins table 1-3 shows pins used to write program data to msm64p155. table 1-3 explanation of pins (prom functions) type pin name pin no. function prom function vss 23 output 0v power supply input/ output vdd1* 100 plus side power supply pin (+5v supplies) vdd2* 99 plus side power supply pin (+5v supplies) vpp 4 prom write power supply (+12.5v supplied) reset 1 input prom write setting pins prom mode is set by h level input tst1 30 input tst2 29 input seg0/d0 91 i/o pins for writing and reading of program data seg1/d1 90 i/o seg2/d2 89 i/o seg3/d3 88 i/o seg4/d4 87 i/o seg5/d5 86 i/o seg6/d6 85 i/o seg7/d7 84 i/o seg8/ ce 83 i/o prom chip enable pin seg9/ oe 82 i/o prom output enable signal seg10/a0 81 input program address input pins seg11/a1 80 input seg12/a2 79 input seg13/a3 78 input seg14/a4 77 input seg15/a5 76 input seg16/a6 75 input seg17/a7 74 input seg18/a8 73 input seg19/a9 72 input seg20/a10 71 input seg21/a11 70 input * prom mode should be supplied with 5v both to vdd1 and vdd2. seg22 69 input normally input h level 1-11 1.5.3 processing of unused pins table 1-4 shows processing of unused pins. table 1-4 processing of unused pins pin recommended pin connection tst1~3 open p2.0~p2.3 "l" level or open p3.0~p3.1 "l" level or open p6.0~p6.3 for input setting: "l" level or open (initial value is input mode) for output setting: open p7.0~p7.3 for input setting: "l" level or open (initial value is input mode) for output setting: open md0, md1 md0 , md1 open com1~4 open seg0~59 open p4.0~p4.3 open chapter 2 power supply system 2-1 chapter 2 power supply system 2.1 overview msm64p155 (otp version) is manufactured using eprom process for the n-well that is different from the p-well cmos structure of the mask rom of msm64155a (mask rom). because of this, the polarity of the power supply system is completely reversed when compared to the mask rom. in addition, note that the names of the power supply pins have also been changed. table 2-1 shows a table of the power supply pin functions and table 2-2 shows the differences between msm64155a and msm64p155. table 2-1 list of power supply pin functions pin name pin no. function vss 23 0v power supply input/ output vdd1 100 plus side power supply (for 1.5v specifications) bias output for lcd drive (+1.5v) (for 3.0v specifications) vdd2 99 plus side power supply (for 3.0v specifications) bias output for lcd drive (+3.0v) (for 1.5v specifications) vdd3 98 bias output for lcd drive (+4.5v) vpp 4 plus side power supply for prom write (+12.5v) table 2-2 differences between msm64p155 and msm64155a different from msm64p155 vss (0v) vdd (0v) msm64p155 msm64155a vdd1 (+1.5v) vss1 (-1.5v) power supply has reversed phase with 1.5v specifications vdd2 (+3.0v) vss2 (-3.0v) power supply has reversed phase with 3.0v specifications vdd3 (+4.5v) vss3 (-4.5v) vpp (+12.5v) vssl no external capacitor is required 2-2 vssl vss3 vss2 vss1 vdd msm64155a 1.5v option 4 98 99 100 23 (mask rom) vpp vdd3 vdd2 vdd1 vss msm64p155 1.5v option 4 98 99 100 23 (otp version) 1.5v condenser is unnecessary. 1.5v (a) configuration of the power supply system with the 1.5v option vssl vss3 vss2 vss1 vdd msm64155a 3.0v option 4 98 99 120 23 (mask rom) vpp vdd3 vdd2 vdd1 vss msm64p155 3.0v option 4 98 99 100 23 (otp version) 3.0v condenser is unnecessary. 3.0v (b) configuration of the power supply system with the 3.0v option figure 2-1 power supply system circuit configuration 2.2 power supply system circuit configuration figure 2-1 shows the circuit configuration of the power supply including the differences between msm64p155 and msm64155a. 2-3 2.3 logic power supply and backup circuits msm64p155 has no built-in logic power supply constant voltage (vr) or backup circuits. internal logic is driven by the vdd1 level both for the 1.5v option and 3.0v option. the backup controller register (bupcon) is identical to msm64155a, it enables both reading and writing, and the 0 bit (bupf) of the backup controller register (bupcon) has no influence on the logic power source. 2.3.1 configuration of the logic power supply figure 2-2 shows the configuration of driving circuits of the logic power supply. figure 2-2 logic power supply driving circuits vddl vss logic circuit msm64p155 (1.5v option) vdd1 vss ca 1.5v vddl vss logic circuit msm64p155l (3.0v option) vdd1 vss ca 3.0v vdd2 cb bias generating circuit (+1.5v) 2-4 2.3.2 operations of optional 1.5v logic power supply circuits 1.5v optional logic power supply circuits are supplied as a power source with ordinary logic circuits for ic power supply voltage vdd1. 2.3.3 operations of optional 3.0v logic power supply circuits with the 3.0v option, ic power supply voltage vdd2 is supplied to the logic circuit in the system reset mode, and 1/2 descending power output voltage is supplied for other modes. figure 2-3 shows the logic supply status for the system reset mode. reset0 (internal reset signal) crystal oscillation output logic power source vss 32.768 khz 0.5sec vdd2 3.0v 1.5v vdd2 vdd1 figure 2-3 logic power supply status for system reset mode (3.0v option) chapter 3 crystal oscillation circuit 3-1 chapter 3 crystal oscillation circuit 3.1 overview the crystal oscillation circuit, oscillating at 32.768 khz, can be fine-adjusted with an external capacitor, but since the phase of the power supply of msm64p155 is reversed against msm64155a, location of the attachment position of an external capacitor cg is placed between the vss and osc0 pin. if rc oscillation is selected by mask option, use an external 1m w resistor like the msm64155a. 3.2 configuration of crystal oscillation circuit figure 3-1 shows the configurations of the crystal oscillation circuit both for msm64155a (mask rom) and msm64p155. time base clock (32.768 khz) vdd cg osc0 32.768 khz crystal vdd cd rf vssl msm64155a (mask rom) 32.768 khz crystal oscillation circuit time base clock (32.768 khz) cg osc0 32.768 khz crystal vss cd rf msm64p155 (otp version) logic power source vss osc1 osc1 (a) configuration of crystal oscillation circuit for msm64155a (b) configuration of crystal oscillation circuit for msm64p155 figure 3-1 configurations of crystal oscillation circuit chapter 4 prom 4-1 chapter 4 prom 4.1 overview msm64p155 uses built-in prom as program memory. the capacity of this prom is 4064 bytes that omitted 32 bytes from the 0fe0h address to the 0fffh address, forming the test data area of the mask rom. in order to write the program data to this prom, msm64p155 uses a special adapter (otp 64155f-100) which is connected to a general eprom writer for writing. see the adapter manual for further reference. 4.2 explanation of pins table 4-1 shows prom-related pins of msm64p155. table 4-1 (a) prom related pins pin name pin no. note vss 23 0v power supply input/ output vdd1 100 plus side power supply pin (+5v supplied) vdd2 99 plus side power supply pin (+5v supplied) vpp 4 power supply for prom writing (+12.5v supplied) reset 1 input prom mode setting pins prom mode is activated when the "h" level is input to these pins. tst1 30 input tst2 29 input 4-2 table 4-1 (b) prom-related pins pin name pin no. function seg0/d0 91 i/o program data write and read pins input/ output seg1/d1 90 i/o seg2/d2 89 i/o seg3/d3 88 i/o seg4/d4 87 i/o seg5/d5 86 i/o seg6/d6 85 i/o seg7/d7 84 i/o seg8/ ce 83 input prom chip enable pin seg9/ oe 82 input prom output enable signal seg10/a0 81 input program address input pins seg11/a1 80 input seg12/a2 79 input seg13/a3 78 input seg14/a4 77 input seg15/a5 76 input seg16/a6 75 input seg17/a7 74 input seg18/a8 73 input seg19/a9 72 input seg20/a10 71 input seg21/a11 70 input seg22 69 input normally input "h" level 4-3 4.3 prom mode msm64p155 has two different modes; prom mode used to write to prom and read from prom and microcontroller operation mode used to execute programs written to prom. when msm64p155 is set in the prom mode, it simply operates as prom. these operations are explained under prom mode. 4.3.1 setting the prom mode setting of the prom mode is done with reset, tst1, and tst2, listed in table 4-2. when the prom mode is set, lcd pins become prom-related pins. table 4-2 prom mode setting reset hh h mode tst1 tst2 prom mode 4.3.2 prom mode functions prom mode functions are shown in table 4-3. table 4-3 prom mode functions mode d7~d0 oe vdd1 vdd2 read ce vpp l l 5v 5v program data output program l h 12.5v 5v program data input program verify h l 12.5v 5v program data output 4-4 4.3.3 connection to the eprom writer use the msm64p155 dedicated adaptor (otp64155f-100) when writing the program data with a commercial general-purpose eprom writer. set a rom type for the eprom writer to the 27c256 type intel fast-writing mode (v pp =12.5v, program pulse width=1ms). set the write addresses of 0000h to 0fdfh. chapter 5 tst3 pin 5-1 chapter 5 tst3 pin 5.1 overview in the msm64p155, when the tst pin is set to "h" level, the 256hz and 4hz interrupt sources are added. the two added interrupt sources enable the msm64p155 to be used as an otp version of the msm64152a, msm64153a or msm64158a. table 5-1 lists the interrupt sources when tst3="h" and figure 5-1 shows the interrupt control equivalent circuit. table 5-1 interrupt sources (tst3="h") no. melody 0 interrupt interrupt start address symbol 023h md0int 1 interrupt source melody 1 interrupt 026h md1int 2 port 3 external interrupt 029h p3int 3 port 2 external interrupt 02ch p2int 4 port 6 external interrupt 02fh p6int 5 port 7 external interrupt 032h p7int 6 256hz interrupt 038h 256hzint 7 128hz interrupt 03bh 128hzint 8 32hz interrupt 03eh 32hzint 9 16hz interrupt 041h 16hzint 10 4hz interrupt 044h 4hzint 11 1hz interrupt 047h 1hzint 12 if two or more different interrupts occur at the same time, an interrupt with a smaller interrupt start address number is serviced first. when the tst3 pin is open or set to "l" level, the contents of interrupt sources are the same as those of the msm64155a. 5-2 irq0 irq0.1 qmd0 irq0.2 qmd1 irq0.3 qp3 ie0 ie0.1 emd0 ie0.2 emd1 ie0.3 ep3 md0int md1int p3int irq1 irq1.0 qp2 irq1.1 irq1.2 qp7 ie1 ie1.0 ep2 ie1.1 ep6 ie1.2 ep7 p2int p6int p7int irq2 irq2.1 q128hz irq2.2 q32hz irq2.3 q16hz ie2 ie2.1 e128hz ie2.2 e32hz ie2.3 e16hz qp6 irq3 irq3.1 q1hz ie3 ie3.1 e1hz 1hzint mi interrupt vector address interrupt request priority encoder irq2.0 q256hz ie2.0 e256hz 256hzint 128hzint 32hzint 16hzint irq3.0 q4hz ie3.0 e4hz 4hzint tst3 interrupt request signals interrupt request registers interrupt enable registers figure 5-1 interrupt control equivalent circuit 5-3 5.2 registers to be changed by tst3 when the tst3 pin is set to "h" level, the 256hz interrupt and 4hz interrupt are added to the interrupt request registers (irq2, irq3) and interrupt enable registers (ie2, ie3), respectively. q32hz q16hz b 3 b 2 b 1 b 0 16 hz interrupt request flag 0: not requested (initial value) 1: requested 32 hz interrupt request flag 0: not requested (initial value) 1: requested 128 hz interrupt request flag 0: not requested (initial value) 1: requested 256 hz interrupt request flag 0: not requested (initial value) 1: requested irq2 (3eh) (r/w) q128hz q256hz bit 3: q16hz set to "1" at the falling edge of a 16hz output from the time base counter. bit 2: q32hz set to "1" at the falling edge of a 32hz output from the time base counter. bit 1: q128hz set to "1" at the falling edge of a 128hz output from the time base counter. bit 0: q256hz set to "1" at the falling edge of a 256hz output from the time base counter. 5-4 ? ? b 3 b 2 b 1 b 0 1 hz interrupt request flag 0: not requested (initial value) 1: requested 4 hz interrupt request flag 0: not requested (initial value) 1: requested *researved bit: fixed to "1". write is disabled. irq3 (3fh) (r/w) q1hz q4hz bit 1: q1hz set to "1" at the falling edge of a 1hz output from the time base counter. bit 0: q4hz set to "1" at the falling edge of a 4hz output from the time base counter. e32hz e16hz b 3 b 2 b 1 b 0 16 hz interrupt enable flag 0: disabled (initial value) 1: enabled 32 hz interrupt enable flag 0: disabled (initial value) 1: enabled 128 hz interrupt enable flag 0: disabled (initial value) 1: enabled 256 hz interrupt enable flag 0: disabled (initial value) 1: enabled ie2 (3ah) (r/w) e128hz e256hz 5-5 ? ? b 3 b 2 b 1 b 0 1 hz interrupt enable flag 0: disabled (initial value) 1: enabled 4 hz interrupt enabled flag 0: disabled (initial value) 1: enabled *researved bit: fixed to "1". write is disabled. ie3 (3bh) (r/w) e1hz e4hz table 5-2 lists the registers to be changed by tst3 table 5-2 tst3-related registers interrupt enable register 2 symbol address read/write byte access initial value after system reset tst3="1" tst3="0" or open name interrupt enable register 3 interrupt request register 2 interrupt request register 3 ie2 3ah r/w yes 1h 0h ie3 3bh r/w 0dh 0ch irq2 3eh r/w yes 1h 0h irq3 3fh r/w 0dh 0ch appendixes appendix-1 appendix a package dimensional drawing msm64p155-ngs-bk MSM64P155L-NGS-BK msm64p155-xxxgs-bk msm64p155l-xxxgs-bk figure a-1 100-pin qfp appendix-2 appendix b electrical characteristics (1) for 1.5v specifications in the microcontroller operation mode product name: msm64p155 ? absolute maximum rating parameter symbol condition rating unit power supply voltage 1 vdd1 ta=25 c C0.3~+2.0 v power supply voltage 2 vdd2 ta=25 c C0.3~+4.0 v power supply voltage 3 vdd3 ta=25 c C0.3~+5.5 v input voltage 1 vin1 vdd1 system input, ta=25 c C0.3~vdd1+0.3 v output voltage 1 vout1 vdd1 system output, ta=25 c C0.3~vdd1+0.3 v output voltage 2 vout2 vdd2 system output, ta=25 c C0.3~vdd2+0.3 v output voltage 3 vout3 vdd3 system output, ta=25 c C0.3~vdd3+0.3 v storage temperature tstg C55~+125 c (vss=0v) ? recommended operating conditions parameter symbol condition range unit operating temperature tope 0~65 c operating voltage vdd1 1.35~1.7 v crystal oscillator frequency fxt 30~35 khz (vss=0v) rc osc external resistance ros 1m 10% w appendix-3 ? dc characteristics (unless otherwise specified, vss=0v, vdd1=1.5v, ta=0~65?c). parameter symbol condition measure- ment circuit vdd2 voltage vdd2 3.0 (1/5) unit max. typ. min. 2.8 3.2 v ca, c12=1 f cb=0.1 f vdd3 voltage vdd3 4.5 4.3 4.7 v ca, c12=1 f cb=0.1 f xtosc oscillation beginning voltage vsta v within 5 seconds from the beginning of oscillations after reset xtosc oscillation maintaining voltage vhold v xtosc external capacity cg 10 30 pf crosc oscillation frequency fcr 40 15 75 khz 1 ros=1m w 1.45 1.35 xtosc internal capacity cd 15 10 20 pf note: "xtosc" indicates crystal oscillation circuits at 32.768 khz. "crosc" indicates rc oscillation circuits at 32 khz. appendix-4 ? dc characteristics (32.768 khz crystal oscillation) (unless otherwise specified, vss=0v, vdd1=1.5v, ta=0~65?c). typ. parameter symbol condition measure- ment circuit consumption current 1 idd1 2 (2/5) unit max. min. 10 a cpu is in the halt mode consumption current 2 idd2 75 100 cpu is in the operating mode a 1 ? dc characteristics (rc oscillation) (unless otherwise specified, vss=0v, vdd1=1.5v, ta=0~65?c). typ. parameter symbol condition measure- ment circuit consumption current 1 idd1 3 (3/5) unit max. min. 20 a cpu is in the halt mode consumption current 2 idd2 100 200 cpu is in the operating mode a 1 appendix-5 ? dc characteristics (unless otherwise specified, vss=0v, vdd1=1.5v, vdd2=3.0v, vdd3=4.5v, ta=0~65?c). parameter symbol condition measure- ment circuit output current 1 (p4.0~p4.3) (md0, md0 ) (md1, md1 ) ioh1 C0.6 (4/5) unit max. typ. min. C0.1 ma voh1=vdd1-0.5v C2.0 iol1 0.6 2.0 ma vol1=+0.5v 0.1 output current 2 (seg0~seg59) (com1~com4) ioh2 C4 a voh2=vdd3-0.2v (vdd3 level) iomh2 a vomh2=vdd2+0.2v (vdd2 level) 4 iomh2s C4 a vomh2s=vdd2-0.2v(vdd2 level) ioml2 a voml2=vdd1+0.2v (vdd1 level) 4 ioml2s C4 a voml2s=vdd1-0.2v(vdd1 level) iol2 a vol2=+0.2v (vss level) 4 output leak (p6.0~p6.3) (p7.0~p7.3) iooh 0.3 a voh=vdd1 iool C0.3 a vol=vss 2 output current 3 (p6.0~p6.3) (p7.0~p7.3) ioh3 C0.3 ma voh3=vdd1C0.5v iol3 0.1 ma vol3=+0.5v C5.0 2.0 0.7 C2.1 appendix-6 ? dc characteristics (unless otherwise specified, vss=0v, vdd1=1.5v, vdd2=3.0v, vdd3=4.5v, ta=0~65?c) parameter symbol condition measure- ment circuit input current 1 (p2.0~p2.3) (p3.0~p3.1) (p6.0~p6.3) (p7.0~p7.3) iih1 20 (5/5) unit max. typ. min. 100 a vih=vdd1 (for pull-down) 1 iih1z 1 a vih1=vdd1 (for high impedance) 0 input current 2 (tst1, tst2) iih2 800 a vih2=vdd1 iil2 a vil3=vss C1 iih4 30 a vih4=vdd1 iil4 a vil4=vss C1 vih1 1.5 v vil1 v 0 input voltage 1 (p2.0~p2.3) (p3.0~p3.1) (p6.0~p6.3) (p7.0~p7.3) (tst1, tst2, tst3) (reset) 3 iil1 0 a vil1=vss C1 50 200 0 2 0 input current 4 (reset) 1.2 0.3 4 8 input current 3 (tst3) iih3 5 a vih3=vdd1 iil3 a vil2=vss C1 0.3 1 0 appendix-7 measurement circuit 1 (1) a v v osc1 osc0 c1 c2 crystal c12 cg vss vss vdd1 vdd2 vdd3 ca cb ca, c12 cb crystal cg : 1 m f : 0.1 m f : 32.768 khz : 15 pf measurement circuit 1 (2) a v v osc1 osc0 c1 c2 ros c12 vss vdd1 vdd2 vdd3 ca cb ca cb, c12 ros : 20 m f : 0.1 m f ~ 0.2 m f : 1m w appendix-8 measurement circuit 2 a output pin vss vdd1 vdd2 vdd3 (note 2) input pins (note 1) vih vil measurement circuit 3 a output pin vss vdd1 vdd2 vdd3 (note 3) input pins appendix-9 measurement circuit 4 output pin vss vdd1 vdd2 vdd3 input pins (note 3) vih vil waveform monitoring note 1 input logic for specified mode note 2 repeated on specified output pin note 3 repeated on specified input pin appendix-10 (2) for 3.0v specifications product name: msm64p155l ? absolute maximum ratings parameter symbol condition rating unit power supply voltage 1 vdd1 ta=25 c C0.3~+2.0 v power supply voltage 2 vdd2 ta=25 c C0.3~+4.0 v power supply voltage 3 vdd3 ta=25 c C0.3~+5.5 v input voltage 1 vin1 vdd2 system input, ta=25 c C0.3~vdd2+0.3 v output voltage 1 vout1 vdd2 system output, ta=25 c C0.3~vdd2+0.3 v output voltage 2 vout2 vdd3 system output, ta=25 c C0.3~vdd3+0.3 v storage temperature tstg C55~+125 c (vss=0v) ? recommended operating conditions parameter symbol condition range unit operating temperature tope 0~65 c operating voltage vdd2 2.7~3.5 v crystal oscillator frequency fxt 30~66 khz (vss=0v) rc osc external resistance ros 1m 10% w appendix-11 parameter symbol condition measure- ment circuit vdd1 voltage vdd1 1.5 (1/5) unit max. typ. min. 1.3 1.7 v ca=1 f cb, c12=0.1 f vdd3 voltage vdd3 4.5 4.3 4.7 v ca=1 f cb, c12=0.1 f xtosc oscillation beginning voltage vsta v within 5 seconds from the beginning of oscillations after reset xtosc oscillation maintaining voltage vhold v xtosc external capacitance cg 10 30 pf xtosc internal capacitance cd 15 10 20 pf 2.7 2.7 1 crosc oscilaltion frequency fcr 40 15 75 khz ros=1m w ? dc characteristics (unless otherwise specified, vss=0v, vdd2=3.0v, ta=0~65?c). note: "xtosc" indicates crystal oscillation circuits at 32.768 khz. "crosc" indicates rc oscillation circuits at 32 khz. appendix-12 ? dc characteristics (32.768 khz crystal oscillation) (unless otherwise specified, vss=0v, vdd2=3.0v, ta=0~65?c). parameter symbol condition measure- ment circuit consumption current 1 idd1 1 (2/5) unit max. typ. min. 5 a cpu is in the halt mode consumption current 2 idd2 35 50 cpu is in the operating mode a 1 ? dc characteristics (rc oscillation) (unless otherwise specified, vss=0v, vdd2=3.0v, ta=0~65?c). parameter symbol condition measure- ment circuit consumption current 1 idd1 3 (3/5) unit max. typ. min. 15 a cpu is in the halt mode consumption current 2 idd2 50 100 cpu is in the operating mode a 1 appendix-13 ? dc characteristics (unless otherwise specified, vss=0v, vdd1=1.5v, vdd2=3.0v, vdd3=4.5v, ta=0~65?c). parameter symbol condition measure- ment circuit output current 1 (p4.0~p4.3) (md0, md0 ) (md1, md1 ) ioh1 C1.8 (4/5) unit max. typ. min. C0.7 ma voh1=vdd2C0.5v C6 iol1 1.8 6 ma vol1=+0.5v 0.7 output current 2 (seg0~seg59) (com1~com4) ioh2 C4 voh2=vdd3C0.2v (vdd3 level) iomh2 vomh2=vdd2+0.2v (vdd2 level) 4 iomh2s C4 vomh2s=vdd2C0.2v(vdd2 level) ioml2 voml2=vdd1+0.2v (vdd1 level) 4 ioml2s C4 voml2s=vdd1C0.2v(vdd1 level) iol2 vol2=+0.2v (vss level) 4 output leak (p6.0~p6.3) (p7.0~p7.3) iooh 0.3 voh=vdd2 iool C0.3 vol=vss 2 a a a a a a a a output current 3 (p6.0~p6.3) (p7.0~p7.3) ioh3 C2 voh3=vdd2C0.5v iol3 0.7 vol3=+0.5v ma ma C1.8 6.0 1.6 C6 appendix-14 ? dc characteristics (unless otherwise specified, vss=0v, vdd1=1.5v, vdd2=3.0v, vdd3=4.5v, ta=0~65?c). parameter symbol condition measure- ment circuit input current 1 (p2.0~p2.3), (p3.0~p3.1) (p6.0~p6.3), (p7.0~p7.3) iih1 100 (5/5) unit max. typ. min. 300 a vih1=vdd2 (for pull-down) 50 iih1z 1 a vih1=vdd2 (for high impedance) 0 input current 2 (tst1, tst2) iih2 6 ma vih2=vdd2 iil2 a vil2=vss C1 iih4 300 a vih4=vdd2 iil4 a vil4=vss C1 vih1 3.0 v vil1 v 0 input voltage 1 (p2.0~p2.3) (p3.0~p3.1) (p6.0~p6.3) (p7.0~p7.3) (tst1, tst2, tst3) (reset) 3 iil1 0 a vil1=vss C1 0.4 1.5 0 20 0 input current 4 (reset) 2.4 0.6 4 80 iih3 10 a vih3=vdd2 iil3 a vil3=vss C1 0.5 0 input current 3 (tst3) 3 appendix-15 measurement circuit 1 (1) a v v osc1 osc0 c1 c2 crystal c12 cg vss vss vdd2 vdd1 vdd3 ca cb ca cb, c12 crystal cg : 1 m f : 0.1 m f : 32.768 khz : 15 pf measurement circuit 1 (2) a v v osc1 osc0 c1 c2 ros c12 vss vdd2 vdd1 vdd3 ca cb ca cb, c12 ros : 20 m f : 0.1 m f : 1m w appendix-16 measurement circuit 2 a output pin vss vdd1 vdd2 vdd3 (note 2) input pins (note 1) vih vil measurement circuit 3 a output pin vss vdd1 vdd2 vdd3 (note 3) input pins appendix-17 measurement circuit 4 output pin vss vdd1 vdd2 vdd3 input pins (note 3) vih vil waveform monitoring note 1 input logic for specified mode note 2 repeated on specified output pin note 3 repeated on specified input pin appendix-18 (3) prom operations (common specifications for 1.5v and 3.0v) ? absolute maximum ratings ? recommended operating conditions vcc=vdd1=vdd2 4.75~5.25 parameter symbol condition range unit operating temperature topep 0~65 c vcc power supply voltage vcc 4.75~5.25 v vpp power supply voltage vpp v (vss=0v) vcc=vdd1=vdd2 in read 12.0~13.0 v in write 4~vcc input voltage vih v 0~1 v vil parameter symbol condition rating unit prom power source voltage vcc vcc=vdd1=vdd2 ta=25 c C0.3~+6.7 v (vss=0v) program voltage vpp ta=25 c C0.3~+14.0 v prom input voltage vi vcc system input ta=25 c C0.3~vcc+0.3 v prom output voltage vo vcc system output ta=25 c C0.3~vcc+0.3 v storage temperature tstg C55~+125 c appendix-19 appendix-20 ? timing diagram data output t oe t acc address input c e o e t df t ce appendix-21 appendix-22 ? program timing diagram data input/output address n data input data output t as t ds t dh t vs t ah t oe t dfp t pw t opw t oes address input vpp c e o e msm64p155 user's manual first edition: march 1996 ? ? ? ? ? 1996 oki electric industry co., ltd. |
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