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features ? core ? arm ? cortex ? -m3 revision 2.0 running at up to 48 mhz ?thumb ? -2 instruction ? 24-bit systick counter ? nested vector interrupt controller ? pin-to-pin compatible with sam7s legacy products (48- and 64-pin versions) and sam3s (48-, 64- and 100-pin versions) ? memories ? from 64 to 256 kbytes embedded flash, 128-bit wide access, memory accelerator, single plane ? from 8 to 24 kbytes embedded sram ? 16 kbytes rom with embedded bootload er routines (uart) and iap routines ? system ? embedded voltage regulator for single supply operation ? power-on-reset (por), brown-out det ector (bod) and watchdog for safe operation ? quartz or ceramic resonator oscillators: 3 to 20 mhz main power with failure detection and optional low power 32.768 khz for rtc or device clock ? high precision 8/12 mhz factory trimmed inte rnal rc oscillator with 4 mhz default frequency for device startup. in-appli cation trimming access for frequency adjustment ? slow clock internal rc o scillator as permanent low-power mode device clock ? one pll up to 130 mhz for device clock ? up to 10 peripheral dma (pdc) channels ? low power modes ? sleep and backup modes, down to 3 a in backup mode ? ultra low power rtc ? peripherals ? up to 2 usarts with iso7816, irda ? , rs-485 and spi mode ? two 2-wire uarts ? 2 two wire interface (i2c compatible), 1 spi ? up to 6 three-channel 16-bit timer/coun ter with capture, waveform, compare and pwm mode. quadrature decoder logic and 2-bit gray up/down counter for stepper motor ? 4-channel 16-bit pwm ? 32-bit real-time timer and rtc wi th calendar and alarm features ? up to 16 channels, 384 ksps 10-bit adc ? one 500 ksps 10-bit dac ? i/o ? up to 79 i/o lines with external interrup t capability (edge or level sensitivity), debouncing, glitch filtering and on-die series resistor termination ? three 32-bit parallel input/output controllers ? packages ? 100-lead lqfp, 14 x 14 mm, pitch 0.5 mm / 100-ball lfbga, 9 x 9 mm, pitch 0.8 mm ? 64-lead lqfp, 12 x 12 mm, pitch 0.5 mm / 64-pad qfn 9x9 mm, pitch 0.45 mm ? 48-lead lqfp, 9 x 9 mm, pitch 0.5 mm / 48-pad qf n 7x7 mm, pitch 0.45 mm at91sam arm-based flash mcu atsam3n series 11011a?atarm?04-oct-10
2 11011a?atarm?04-oct-10 sam3n 1. sam3n description atmel's sam3n series is a member of a family of flash microcontrollers based on the high per- formance 32-bit arm cortex-m3 risc processor. it operates at a maximum speed of 48 mhz and features up to 256 kbytes of flash and up to 24 kbytes of sram. the peripheral set includes 2x usarts, 2x uarts, 2x twis, 3x spi, as well as 1 pwm timer, 6x general purpose 16-bit timers, an rtc, a 10-bit adc and a 10-bit dac. the sam3n series is ready for capacitive touch thanks to the qtouch library, offering an easy way to implement buttons, wheels and sliders. the sam3n device is an entry-level general purpose microcontroller. that makes the sam3n the ideal starting point to move from 8- /16-bit to 32-bit microcontrollers. it operates from 1.62v to 3.6v and is avail able in 48-pin, 64-pin and 100-pin qfp, 48-pin and 64-pin qfn, and 100-pin bga packages. the sam3n series is the ideal migration path from the sam3s for applications that require a reduced bom cost. the sam3n series is pin-to-pin compatible with the sam3s series. its aggressive price point and high level of integration pushes its scope of use far into cost-sensi- tive, high-volume applications. 1.1 configuration summary the sam3n4/2/1 differ in memory size, package and features list. table 1-1 summarizes the configurations of the 9 devices. notes: 1. only two tc channels are accessible through the pio. 2. only three tc channels are accessible through the pio. table 1-1. configuration summary device flash sram package number of pios adc timer pdc channels usart dac sam3n4a 256 kbytes 24 kbytes lqfp48 qfn48 34 8 channels 6 (1) 81_ sam3n4b 256 kbytes 24 kbytes lqfp64 qfn64 47 10 channels 6 (2) 10 2 1 sam3n4c 256 kbytes 24 kbytes lqfp100 bga100 79 16 channels 6 10 2 1 sam3n2a 128 kbytes 16 kbytes lqfp48 qfn48 34 8 channels 6 (1) 81 _ sam3n2b 128 kbytes 16 kbytes lqfp64 qfn64 47 10 channels 6( (2) 10 2 1 sam3n2c 128 kbytes 16 kbytes lqfp100 bga100 79 16 channels 6 10 2 1 sam3n1a 64 kbytes 8 kbytes lqfp48 qfn48 34 8 channels 6 (1) 81 _ sam3n1b 64 kbytes 8 kbytes lqfp64 qfn64 47 10 channels 6 (2) 10 2 1 sam3n1c 64 kbytes 8 kbytes lqfp100 bga100 79 16 channels 6 10 2 1
3 11011a?atarm?04-oct-10 sam3n 2. sam3n block diagram figure 2-1. sam3n 100-pin version block diagram t s t pck0-pck2 s y s tem controller xin nr s t pmc xout o s c 3 2k xin 3 2 xout 3 2 s upc r s tc o s c 3 -20 mhz pioa piob por rtc rtt rc 3 2k rc o s c 12/ 8 /4 mhz era s e tdi tdo/trace s wo tm s / s wdio tck/ s wclk jtag s el i/d s vddi n vddout tc[0..2] tclk[0:2] twck0 twd0 twck1 twd1 npc s 0 npc s 1 npc s 2 npc s3 mi s o mo s s pck tclk[ 3 :5] tioa[0:2] tiob[0:2] tioa[ 3 :5] tiob[ 3 :5] pdc pdc pdc pdc pdc pwm in-circ u it em u l a tor pdc jtag & s eri a l wire pwm[0: 3 ] adtrg advref dac0 datrg 10- b it adc 10- b it dac pioc s m vddio pll rxd0 txd0 s ck0 rt s 0 ct s 0 rxd1 txd1 s ck1 rt s 1 ct s 1 u s art0 uart1 uart0 u s art1 cortex-m 3 proce ss or fm a x 4 8 mhz 24- b it s y s tick co u nter rom 16 kbyte s s ram 24 kbyte s 16 kbyte s 8 kbyte s fla s h 256 kbyte s 12 8 kbyte s 64 kbyte s vddcore wdt peripher a l bridge urxd0 utxd0 urxd1 utxd1 timer co u nter a timer co u nter b s pi twi0 twi1 n v i c volt a ge reg u l a tor tc[ 3 ..5] ad[0..15] 3 - l a yer ahb b us m a trix fm a x 4 8 mhz
4 11011a?atarm?04-oct-10 sam3n figure 2-2. sam3n 64-pin version block diagram tc[ 3 ..5] ad[0..9] 3 - l a yer ahb b us m a trix fm a x 4 8 mhz t s t pck0-pck2 s y s tem controller xin nr s t pmc xout o s c 3 2k xin 3 2 xout 3 2 s upc r s tc o s c 3 -20 mhz pioa piob por rtc rtt rc 3 2k rc o s c 12/ 8 /4 mhz era s e tdi tdo/trace s wo tm s / s wdio tck/ s wclk jtag s el i/d s vddi n vddout tc[0..2] tclk[0:2] twck0 twd0 twck1 twd1 npc s 0 npc s 1 npc s 2 npc s3 mi s o mo s s pck tioa[0:2] tiob[0:2] pdc pdc pdc pdc pdc pwm in-circ u it em u l a tor pdc jtag & s eri a l wire pwm[0: 3 ] adtrg advref dac0 datrg 10- b it adc 10- b it dac s m vddio pll rxd0 txd0 s ck0 rt s 0 ct s 0 rxd1 txd1 s ck1 rt s 1 ct s 1 u s art0 uart1 uart0 u s art1 cortex-m 3 proce ss or fm a x 4 8 mhz 24- b it s y s tick co u nter rom 16 kbyte s s ram 24 kbyte s 16 kbyte s 8 kbyte s fla s h 256 kbyte s 12 8 kbyte s 64 kbyte s vddcore wdt peripher a l bridge urxd0 utxd0 urxd1 utxd1 timer co u nter a timer co u nter b s pi twi0 twi1 n v i c volt a ge reg u l a tor 3 -l a yer ahb b us m a trix fm a x 4 8 mhz
5 11011a?atarm?04-oct-10 sam3n figure 2-3. sam3n 48-pin version block diagram tc[ 3 ..5] ad[0..7] 3 - l a yer ahb b us m a trix fm a x 4 8 mhz t s t pck0-pck2 s y s tem controller xin nr s t pmc xout o s c 3 2k xin 3 2 xout 3 2 s upc r s tc o s c 3 -20 mhz pioa piob por rtc rtt rc 3 2k rc o s c 12/ 8 /4 mhz era s e tdi tdo/trace s wo tm s / s wdio tck/ s wclk jtag s el i/d s vddi n vddout tc[0..2] tclk[0:2] twck0 twd0 twck1 twd1 npc s 0 npc s 1 npc s 2 npc s3 mi s o mo s s pck tioa[0:2] tiob[0:2] pdc pdc pdc pdc pwm in-circ u it em u l a tor pdc jtag & s eri a l wire pwm[0: 3 ] adtrg advref 10- b it adc s m vddio pll rxd0 txd0 s ck0 rt s 0 ct s 0 u s art0 uart1 uart0 cortex-m 3 proce ss or fm a x 4 8 mhz 3 -l a yer ahb b us m a trix fm a x 4 8 mhz 24- b it s y s tick co u nter rom 16 kbyte s s ram 24 kbyte s 16 kbyte s 8 kbyte s fla s h 256 kbyte s 12 8 kbyte s 64 kbyte s vddcore wdt peripher a l bridge urxd0 utxd0 urxd1 utxd1 timer co u nter a timer co u nter b s pi twi0 twi1 n v i c volt a ge reg u l a tor
6 11011a?atarm?04-oct-10 sam3n 3. signal description table 3-1 gives details on the signal name classified by peripheral. table 3-1. signal description list signal name function type active level voltage reference comments power supplies vddio peripherals i/o lines power supply power 1.62v to 3.6v vddin voltage regulator, adc and dac power supply power 1.8v to 3.6v (3) vddout voltage regulator output power 1.8v output vddpll oscillator and pll power supply power 1.65 v to 1.95v vddcore power the core, the embedded memories and the peripherals power 1.65v to 1.95v connected externally to vddout gnd ground ground clocks, oscillators and plls xin main oscillator input input vddio reset state: - pio input - internal pull-up disabled - schmitt trigger enabled (1) xout main oscillator output output xin32 slow clock oscillator input input xout32 slow clock oscillator output output pck0 - pck2 programmable clock output output reset state: - pio input - internal pull-up enabled - schmitt trigger enabled (1) ice and jtag tck/swclk test clock/serial wire clock input vddio reset state: - swj-dp mode - internal pull-up disabled - schmitt trigger enabled (1) tdi test data in input tdo/traceswo test data out/trace asynchronous data out output tms/swdio test mode select /serial wire input/output input / i/o jtagsel jtag selection input high permanent internal pull-down
7 11011a?atarm?04-oct-10 sam3n flash memory erase flash and nvm configuration bits erase command input high vddio reset state: - erase input - internal pull-down enabled - schmitt trigger enabled (1) reset/test nrst microcontroller reset i/o low vddio permanent internal pull-up tst test mode select input vddio permanent internal pull-down universal asynchronous receiver transceiver - uartx urxdx uart receive data input utxdx uart transmit data output pio controller - pioa - piob - pioc pa0 - pa31 parallel io controller a i/o vddio reset state: - pio or system ios (2) - internal pull-up enabled - schmitt trigger enabled (1) pb0 - pb14 parallel io controller b i/o pc0 - pc31 parallel io controller c i/o universal synchronous asynchronous receiver transmitter usartx sckx usartx serial clock i/o txdx usartx transmit data i/o rxdx usartx receive data input rtsx usartx request to send output ctsx usartx clear to send input timer/counter - tc tclkx tc channel x external clock input input tioax tc channel x i/o line a i/o tiobx tc channel x i/o line b i/o pulse width modulation controller- pwmc pwmx pwm waveform output for channel x output table 3-1. signal description list (continued) signal name function type active level voltage reference comments
8 11011a?atarm?04-oct-10 sam3n notes: 1. schmitt triggers can be disabled through pio registers. 2. some pio lines are shared with system ios. 3. see section 5.3 ?typical powering schematics? for restriction on voltage range of analog cells. serial peripheral interface - spi miso master in slave out i/o mosi master out slave in i/o spck spi serial clock i/o spi_npcs0 spi peripheral chip select 0 i/o low spi_npcs1 - spi_npcs3 spi peripheral chip select output low two-wire interface- twix twdx twix two-wire serial data i/o twckx twix two-wire serial clock i/o analog advref adc and dac reference analog 10-bit analog-to-digital converter - adc ad0 - ad15 analog inputs analog adtrg adc trigger input vddio digital-to-analo g converter controller- dacc dac0 dacc channel analog output analog datrg dacc trigger input vddio fast flash programming interface pgmen0-pgmen2 programming enabling input vddio pgmm0-pgmm3 programming mode input pgmd0-pgmd15 programming data i/o pgmrdy programming ready output high pgmnvalid data direction output low pgmnoe programming read input low pgmck programming clock input pgmncmd programming command input low table 3-1. signal description list (continued) signal name function type active level voltage reference comments
9 11011a?atarm?04-oct-10 sam3n 4. package and pinout sam3n4/2/1 series is pin-to-pin compatible with sam3s products. furthermore sam3n4/2/1 devices have new functionalitie s referenced in italic in table 4-1 , table 4-3 and table 4-4 . 4.1 sam3n4/2/1c package and pinout 4.1.1 100-lead lqfp package outline figure 4-1. orientation of the 100-lead lqfp package 4.1.2 100-ball lfbga package outline the 100-ball lfbga package has a 0.8 mm ball pitch and respects green standards. its dimen- sions are 9 x 9 x 1.1 mm. figure 4-2. orientation of the 100-ball lfbga package 125 26 50 51 75 76 100 1 3 4 5 6 7 8 9 10 2 abcdefghj k top view ball a1
10 11011a?atarm?04-oct-10 sam3n 4.1.3 100-lead lqfp pinout table 4-1. 100-lead lqfp sam3n4/2/1c pinout 1 advref 26 gnd 51 tdi/pb4 76 tdo/traceswo/pb5 2 gnd 27 vddio 52 pa6/pgmnoe 77 jtagsel 3 pb0/ad4 28 pa16/pgmd4 53 pa5/pgmrdy 78 pc18 4 pc29/ad13 29 pc7 54 pc28 79 tms/swdio/pb6 5 pb1/ad5 30 pa15/pgmd3 55 pa4/pgmncmd 80 pc19 6 pc30/ad14 31 pa14/pgmd2 56 vddcore 81 pa31 7 pb2/ad6 32 pc6 57 pa27 82 pc20 8 pc31/ad15 33 pa13/pgmd1 58 pc8 83 tck/swclk/pb7 9 pb3/ad7 34 pa24 59 pa28 84 pc21 10 vddin 35 pc5 60 nrst 85 vddcore 11 vddout 36 vddcore 61 tst 86 pc22 12 pa17/pgmd5/ad0 37 pc4 62 pc9 87 erase/pb12 13 pc26 38 pa25 63 pa29 88 pb10 14 pa18/pgmd6/ad1 39 pa26 64 pa30 89 pb11 15 pa21/ad8 40 pc3 65 pc10 90 pc23 16 vddcore 41 pa12/pgmd0 66 pa3 91 vddio 17 pc27 42 pa11/pgmm3 67 pa2/pgmen2 92 pc24 18 pa19/pgmd7/ad2 43 pc2 68 pc11 93 pb13/dac0 19 pc15/ad11 44 pa10/pgmm2 69 vddio 94 pc25 20 pa22/ad9 45 gnd 70 gnd 95 gnd 21 pc13/ad10 46 pa9/pgmm1 71 pc14 96 pb8/xout 22 pa23 47 pc1 72 pa1/pgmen1 97 pb9 /pgmck/xin 23 pc12/ad12 48 pa8/xout32/ pgmm0 73 pc16 98 vddio 24 pa20/ad3 49 pa7/xin32/ pgmnvalid 74 pa0/pgmen0 99 pb14 25 pc0 50 vddio 75 pc17 100 vddpll
11 11011a?atarm?04-oct-10 sam3n 4.1.4 100-ball lfbga pinout table 4-2. 100-ball lfbga sam3n4/2/1c pinout a1 pb1/ad5 c6 tck/swclk/pb7 f1 pa 1 8 / p g m d 6 / ad1 h6 pc4 a2 pc29 c7 pc16 f2 pc26 h7 pa11/pgmm3 a3 vddio c8 pa1/pgmen1 f3 vddout h8 pc1 a4 pb9/pgmck/xin c9 pc17 f4 gnd h9 pa6/pgmnoe a5 pb8/xout c10 pa0/pgmen0 f5 vddio h10 tdi/pb4 a6 pb13/dac0 d1 pb3/ad7 f6 pa27 j1 pc15/ad11 a7 ddp/pb11 d2 pb0/ad4 f7 pc8 j2 pc0 a8 ddm/pb10 d3 pc24 f8 pa28 j3 pa16/pgmd4 a9 tms/swdio/pb6 d4 pc22 f9 tst j4 pc6 a10 jtagsel d5 gnd f10 pc9 j5 pa24 b1 pc30 d6 gnd g1 pa21/ad8 j6 pa25 b2 advref d7 vddcore g2 pc27 j7 pa10/pgmm2 b3 gndana d8 pa2/pgmen2 g3 pa15/pgmd3 j8 gnd b4 pb14/dac1 d9 pc11 g4 vddcore j9 vddcore b5 pc21 d10 pc14 g5 vddcore j10 vddio b6 pc20 e1 pa17/pgmd5/ ad0 g 6 pa 2 6 k 1 pa 2 2 / a d 9 b7 pa31 e2 pc31 g7 pa12/pgmd0 k2 pc13/ad10 b8 pc19 e3 vddin g8 pc28 k3 pc12/ad12 b9 pc18 e4 gnd g9 pa4/pgmncmd k4 pa20/ad3 b10 tdo/traceswo/ pb5 e5 gnd g10 pa5/pgmrdy k5 pc5 c1 pb2/ad6 e6 nrst h1 pa 1 9 / p g m d 7 / ad2 k6 pc3 c2 vddpll e7 pa29/ad13 h2 pa23 k7 pc2 c3 pc25 e8 pa30/ad14 h3 pc7 k8 pa9/pgmm1 c4 pc23 e9 pc10 h4 pa14/pgmd2 k9 pa8/xout32/ pgmm0 c5 erase/pb12 e10 pa3 h5 pa13/pgmd1 k10 pa7/xin32/ pgmnvalid
12 11011a?atarm?04-oct-10 sam3n 4.2 sam3n4/2/1b package and pinout figure 4-3. orientation of the 64-pad qfn package figure 4-4. orientation of the 64-lead lqfp package 1 16 17 3 2 33 4 8 49 64 top view 33 49 4 8 3 2 17 16 1 64
13 11011a?atarm?04-oct-10 sam3n 4.2.1 64-lead lqfp and qfn pinout 64-pin version sam3n devices are pin-to-pin compatible with sam3s products. furthermore, sam3n products have new functionalities shown in italic in table 4-3 . note: the bottom pad of the qfn pac kage must be connected to ground. table 4-3. 64-pin sam3n4/2/1b pinout 1 advref 17 gnd 33 tdi/pb4 49 tdo/traceswo/pb5 2 gnd 18 vddio 34 pa6/pgmnoe 50 jtagsel 3 pb0/ad4 19 pa16/pgmd4 35 pa5/pgmrdy 51 tms/swdio/pb6 4 pb1ad5 20 pa15/pgmd3 36 pa4/pgmncmd 52 pa31 5 pb2/ad6 21 pa14/pgmd2 37 pa27/pgmd15 53 tck/swclk/pb7 6 pb3/ad7 22 pa13/pgmd1 38 pa28 54 vddcore 7 vddin 23 pa24/pgmd12 39 nrst 55 erase/pb12 8 vddout 24 vddcore 40 tst 56 pb10 9 pa17/pgmd5/ad0 25 pa25/pgmd13 41 pa29 57 pb11 10 pa18/pgmd6/ad1 26 pa26/pgmd14 42 pa30 58 vddio 11 pa21/pgmd9/ad8 27 pa12/pgmd0 43 pa3 59 pb13/dac0 12 vddcore 28 pa11/pgmm3 44 pa2/pgmen2 60 gnd 13 pa19/pgmd7/ad2 29 pa10/pgmm2 45 vddio 61 xout/pb8 14 pa22/pgmd10/ad9 30 pa9/pgmm1 46 gnd 62 xin/pgmck/pb9 15 pa23/pgmd11 31 pa8/xout32/pgmm 0 47 pa1/pgmen1 63 pb14 16 pa20/pgmd8/ad3 32 pa7/xin32/xout32/ pgmnvalid 48 pa0/pgmen0 64 vddpll
14 11011a?atarm?04-oct-10 sam3n 4.3 sam3n4/2/1a package and pinout figure 4-5. orientation of the 48-pad qfn package figure 4-6. orientation of the 48-lead lqfp package 1 12 1 3 24 25 3 6 3 7 4 8 top view 25 3 7 3 6 24 1 3 12 1 4 8
15 11011a?atarm?04-oct-10 sam3n 4.3.1 48-lead lqfp and qfn pinout note: the bottom pad of the qfn pac kage must be connected to ground. table 4-4. 48-pin sam3n4/2/1a pinout 1 advref 13 vddio 25 tdi/pb4 37 tdo/traceswo/ pb5 2 gnd 14 pa16/pgmd4 26 pa6/pgmnoe 38 jtagsel 3 pb0/ad4 15 pa15/pgmd3 27 pa5/pgmrdy 39 tms/swdio/pb6 4 pb1/ad5 16 pa14/pgmd2 28 pa4/pgmncmd 40 tck/swclk/pb7 5 pb2/ad6 17 pa13/pgmd1 29 nrst 41 vddcore 6 pb3/ad7 18 vddcore 30 tst 42 erase/pb12 7 vddin 19 pa12/pgmd0 31 pa3 43 pb10 8 vddout 20 pa11/pgmm3 32 pa2/pgmen2 44 pb11 9 pa17/pgmd5/ad0 21 pa10/pgmm2 33 vddio 45 xout/pb8 10 pa18/pgmd6/ad1 22 pa9/pgmm1 34 gnd 46 xin/p/pb9/gmck 11 pa19/pgmd7/ad2 23 pa8/xout32/pg mm0 35 pa1/pgmen1 47 vddio 12 pa20/ad3 24 pa7/xin32/pgmn valid 36 pa0/pgmen0 48 vddpll
16 11011a?atarm?04-oct-10 sam3n 5. power considerations 5.1 power supplies the sam3n product has several types of power supply pins: ? vddcore pins: power the core, including the processor, the embedded memories and the peripherals. voltage ranges from 1.62v to 1.95v. ? vddio pins: power the peripherals i/o lines, backup part, 32 khz crystal oscillator and oscillator pads. voltage r anges from 1.62v to 3.6v ? vddin pin: voltage regulator, adc and dac power supply. voltage ranges from 1.8v to 3.6v for the voltage regulator ? vddpll pin: powers the pll, the fast rc a nd the 3 to 20 mhz oscillators. voltage ranges from 1.62v to 1.95v. 5.2 voltage regulator the sam3n embeds a voltage regulator that is managed by the supply controller. this internal regulator is intended to supply the internal core of sam3n. it features two different operating modes: ? in normal mode, the voltage regulator consumes less than 700 a static current and draws 60 ma of output current. internal adaptive biasing adjusts the regulator quiescent current depending on the required load current. in wait mode quiescent current is only 7 a. ? in backup mode, the voltage regulator consumes less than 1 a while its output (vddout) is driven internally to gnd. the default output voltage is 1.80v and the start-up time to reach normal mode is less than100 s. for adequate input and output power supply decoupling/bypassing, refer to ?voltage regulator? in the ?electrical characteristics? section of the datasheet. 5.3 typical powe ring schematics the sam3n supports a 1.62v-3.6v single supply mode. the internal regulator input connected to the source and its output feeds vddcore. figure 5-1 shows the power schematics. as vddin powers the voltage regulator and the adc/dac, when the user does not want to use the embedded voltage regulator, it can be disabled by software via the supc (note that it is dif- ferent from backup mode).
17 11011a?atarm?04-oct-10 sam3n figure 5-1. single supply figure 5-2. core externally supplied note: restrictions with main supply < 3v, adc and dac are not usable. with main supply >= 3v, all peripherals are usable. figure 5-3 below provides an example of the powe ring scheme when using a backup battery. since the pio state is preserved when in backup mode, any free pio line can be used to switch off the external regulator by driving the pio lin e at low level (pio is input, pull-up enabled after backup reset). external wake-up of the system can be from a push button or any signal. see section 5.6 ?wake-up sources? for further details. main supply (1.8v-3.6v) adc, dac i/os. vddin voltage regulator vddout vddcore vddio vddpll main supply (1.62v-3.6v) can be the same supply vddcore supply (1.62v-1.95v) adc, dac supply (3v-3.6v) adc, dac vddin voltage regulator vddout vddcore vddio vddpll i/os.
18 11011a?atarm?04-oct-10 sam3n figure 5-3. core externally supplied (backup battery) 5.4 active mode active mode is the normal runn ing mode with the core clock runn ing from the fast rc oscillator, the main crystal oscillator or the pll. the power management controller can be used to adapt the frequency and to disable the peripheral clocks. 5.5 low power modes the various low-power modes of the sam3n are described below: 5.5.1 backup mode the purpose of backup mode is to achieve the lo west power consumption possible in a system that is performing periodic wakeups to carry out tasks but not requiring fast startup time (<0.1ms). total current consumption is 3 a typical. the supply controller, zero-power power-on reset, rtt, rtc, backup registers and 32 khz oscillator (rc or crystal oscillator selected by so ftware in the supply cont roller) are running. the regulator and the core supply are off. backup mode is based on the cortex-m3 deep sleep mode with the voltage regulator disabled. the sam3n can be awakened from this mode thro ugh wup0-15 pins, the supply monitor (sm), the rtt or rtc wake-up event. backup mode is enter ed by using wfe instructions with the sleepdeep bit in the system con- trol register of the cortex-m3 set to 1. (see the ?power management? description in the arm cortex m3 processor section of the product datasheet). exit from backup mode happens if one of the following enable wake-up events occurs: ? wkupen0-15 pins (level transition, configurable debouncing) adc, dac i/os. vddin voltage regulator 3.3v ldo backup battery + - on/off in out vddout main supply vddcore adc, dac supply (3v-3.6v) vddio vddpll piox (output) wakeupx external wakeup signal note: the two diodes provide a ?switchover circuit? (for illustration purpose) between the backup battery and the main supply when the system is put in backup mode.
19 11011a?atarm?04-oct-10 sam3n ? supply monitor alarm ?rtc alarm ? rtt alarm 5.5.2 wait mode the purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a powered state for a startup ti me of less than 10 s. current consumption in wait mode is typically 15 a (total current consum ption) if the internal voltage regulator is used or 8 a if an external regulator is used. in this mode, the clocks of the core, peripherals and memories are stopped. however, the core, peripherals and memories power supplies are still powered. from this mode, a fast start up is available. this mode is entered via wait for event (wfe) instructions with lpm = 1 (low power mode bit in pmc_fsmr). the cortex-m3 is able to handle exter nal or internal events in order to wake up the core (wfe). by configuring the wup0-15 exter nal lines as fast startup wake-up pins (refer to section 5.7 ?fast start-up? ). rtc or rtt alarm wake-up events can be used to wake up the cpu (exit from wfe). entering wait mode: ? select the 4/8/12 mhz fast rc oscillator as main clock ? set the lpm bit in the pmc fast startup mode register (pmc_fsmr) ? execute the wait-for-event (wfe) instruction of the processor note: internal main cloc k resynchronization cycles are necessa ry between the writing of moscrcen bit and the effective entry in wait mode. depending on the user app lication, waiting for moscrcen bit to be cleared is recommended to en sure that the core will not execute undesired instructions. 5.5.3 sleep mode the purpose of sleep mode is to optimize power consumption of the device versus response time. in this mode, only the core clock is stopped. the peripheral clocks can be enabled. the current consumption in this mode is application dependent. this mode is entered via wait for interrupt (wfi) or wait for event (wfe) instructions with lpm = 0 in pmc_fsmr. the processor can be woke up from an interrupt if wfi instruction of the cortex m3 is used, or from an event if the wfe instruction is used to enter this mode.
20 11011a?atarm?04-oct-10 sam3n 5.5.4 low power mode summary table the modes detailed above are the main low power modes. each part can be set to on or off sep- arately and wake up sources can be individually configured. table 5-1 below shows a summary of the configurations of the low power modes. notes: 1. when considering wake-up time, the time required to start the pll is not taken into accoun t. once started, the device w orks with the 4/8/12 mhz fast rc oscilla tor. the user has to add the pll start-up time if it is nee ded in the system . the wake-up time is defined as the time taken for wake up until the first instruction is fetched. 2. the external loads on pios are not taken into account in the calculation. 3. supply monitor current consumption is not included. 4. total current consumption. 5. 5 a on vddcore, 15 a for total current consumption (using internal voltage regulator), 8 a for total current consumption (without using internal voltage regulator). 6. depends on mck frequency. 7. in this mode the core is supplied and not clocked but some peripherals can be clocked. table 5-1. low power mode conf iguration summary mode supc, 32 khz oscillator rtc rtt backup registers, por (backup region) regulator core memory peripherals mode entry potential wake up sources core at wake up pio state while in low power mode pio state at wake up consumption (2) (3) wake up time (1) backup mode on off off (not powered) wfe +sleepdeep bit = 1 wup0-15 pins bod alarm rtc alarm rtt alarm reset previous state saved pioa & piob & pioc inputs with pull ups 3 a typ (4) < 0.1 ms wait mode on on powered (not clocked) wfe +sleepdeep bit = 0 +lpm bit = 1 any event from: fast startup through wup0-15 pins rtc alarm rtt alarm usb wake-up clocked back previous state saved unchanged 5 a/15 a (5) < 10 s sleep mode on on powered (7) (not clocked) wfe or wfi +sleepdeep bit = 0 +lpm bit = 0 entry mode = wfi interrupt only; entry mode = wfe any enabled interrupt and/or any event from: fast start-up through wup0-15 pins rtc alarm rtt alarm clocked back previous state saved unchanged (6) (6)
21 11011a?atarm?04-oct-10 sam3n 5.6 wake-up sources the wake-up events allow the device to exit backup mode. when a wake-up event is detected, the supply controller performs a sequence which aut omatically reenables the core power sup- ply and the sram power supply, if they are not already enabled. figure 5-4. wake-up source wkup15 wkupen15 wkupt15 wkupen1 wkupen0 debouncer slck wkupdbc wkups rtcen rtc_alarm boden brown_out core supply restart wkupis0 wkupis1 wkupis15 falling/rising edge detector wkupt0 falling/rising edge detector wkupt1 falling/rising edge detector wkup0 wkup1 rtten rtt_alarm
22 11011a?atarm?04-oct-10 sam3n 5.7 fast start-up the sam3n allows the processor to restart in a few microseconds while the processor is in wait mode. a fast start up can occur upon detection of a low level on one of the 19 wake-up inputs (wkup0 to 15 + sm + rtc + rtt). the fast restart circuitry, as shown in figure 5-5 , is fully asynchronous and provides a fast start- up signal to the power management controller. as soon as the fast start-up signal is asserted, the pmc automatically restarts the embedded 4 mhz fast rc oscillator, switches the master clock on this 4 mhz clock and reenables the processor clock. figure 5-5. fast start-up sources rtcen rtc_alarm rtten rtt_alarm fast_restart wkup15 fstt15 wkup0 fstt0 falling/rising edge detector falling/rising edge detector
23 11011a?atarm?04-oct-10 sam3n 6. input/output lines the sam3n has several kinds of input/output (i/o) lines such as general purpose i/os (gpio) and system i/os. gpios can have alternate functionality due to mu ltiplexing capabilities of the pio controllers. the same pio line can be used whether in io mode or by the multiplexed peripheral. system i/os include pins such as test pins, oscillators , erase or analog inputs. 6.1 general purpose i/o lines gpio lines are managed by pio controllers. all i/os have several input or output modes such as pull-up or pull-down, input schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input change interrupt. programming of these modes is performed independently for each i/o line through the pio controller user interface. for more details, refer to the product pio control- ler section. the input output buffers of the pio lines are supplied through vddio power supply rail. the sam3n embeds high speed pads able to h andle up to 45 mhz for spi clock lines and 35 mhz on other lines. see ?ac characteristics? in the ?electrical characteristics? section of the datasheet for more details. typical pull-up and pull-down value is 100 k for all i/os. each i/o line also embeds an odt (on-die termination), (see figure 6-1 ). it consists of an internal series resistor termination scheme for impedance matching between the driver output (sam3n) and the pcb trace impedance preventing si gnal reflection. the series resistor helps to reduce i/o switching current (di/dt) thereby reduc ing in turn, emi. it also decreases overshoot and undershoot (ringing) due to inductance of in terconnect between devices or between boards. in conclusion odt helps dimi nish signal integrity issues. figure 6-1. on-die termination 6.2 system i/o lines system i/o lines are pins used by oscillators, test mode, reset and jtag to name but a few. described below are the sam3n system i/o lines sh ared with pio lines: these pins are software configurable as general purpose i/o or system pins. at startup the default function of these pins is always used. pcb tr a ce z0 ~ 50 ohm s receiver s am 3 driver with rodt zo u t ~ 10 ohm s z0 ~ zo u t + rodt odt 3 6 ohm s ty p.
24 11011a?atarm?04-oct-10 sam3n notes: 1. if pb12 is used as pio input in user applications, a low level must be ensured at start up to prevent flash erase before the user application sets pb12 into pio mode. 2. in the product datasheet refer to: slow clock generator of the supply controller section. 3. in the product datasheet refer to: 3 to 20 mhz crystal oscillator information in the pmc section. 6.2.1 serial wire jtag debug port (swj-dp) pins the swj-dp pins are tck/swclk, tms/sw dio, tdo/swo, tdi and commonly provided on a standard 20-pin jtag connector defined by arm. for more details about voltage reference and reset state, refer to table 3-1 on page 6 . at startup, swj-dp pins are configured in swj-dp mode to allow connection with debugging probe. please refer to the ?debug and test? section of the product datasheet. swj-dp pins can be used as standard i/os to provide users more general input/output pins when the debug port is not needed in the end application. mode selection between swj-dp mode (system io mode) and general io mode is performed through the ahb matrix special function registers (matrix_sfr). configuration of the pad for pull-up, triggers, debouncing and glitch filters is possib le regardless of the mode. the jtagsel pin is used to select the jtag boundary scan when asserted at a high level. it integrates a permanent pull-down resistor of about 15 k to gnd, so that it can be left uncon- nected for normal operations. by default, the jtag debug port is active. if the debugger host wants to switch to the serial wire debug port, it must provide a dedicated jtag sequence on tms/swdio and tck/swclk which disables the jtag-dp and enables the sw-dp. when the serial wire debug port is active, tdo/traceswo can be used for trace. the asynchronous trace output (traceswo) is multiplexed with tdo. so the asynchronous trace can only be used with sw-dp, not jtag-dp. for more information about sw-dp and jtag-dp switching, please refer to the? debug and test? section. table 6-1. system i/o configuration pin list. system_io bit number default function after reset other function constraints for normal start configuration 12 erase pb12 low level at startup (1) in matrix user interface registers (refer to the system i/o configuration register in the bus matrix section of the product datasheet.) 7 tck/swclk pb7 - 6 tms/swdio pb6 - 5 tdo/traceswo pb5 - 4 tdi pb4 - - pa7 xin32 - see footnote (2) below - pa8 xout32 - - pb9 xin - see footnote (3) below - pb8 xout -
25 11011a?atarm?04-oct-10 sam3n 6.3 test pin the tst pin is used for jtag boundary scan manufacturing test or fast flash programming mode of the sam3n series. the tst pin integrates a permanent pull-down resistor of about 15 k to gnd, so that it can be left unconnected for normal operations. to enter fast programming mode, see the ?fast flash programming interface? section of the product datasheet. for more on the manufacturing and test mode, refer to the ?debug and test? section of the product datasheet. 6.4 nrst pin the nrst pin is bidirectional. it is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. it will reset the core and the peripherals except the backup region (rtc, rtt and supply controller). there is no constraint on the length of the reset pulse and the reset con- troller can guarantee a minimum pulse length. the nrst pin integrates a permanent pull-up resistor to vddio of about 100 k . by default, the nrst pin is configured as an input. 6.5 erase pin the erase pin is used to reinitialize the flash content (and some of its nvm bits) to an erased state (all bits read as logic level 1). it integrates a pull-down resistor of about 100 k to gnd, so that it can be left unconnected for normal operations. this pin is debounced by sclk to improve the glitch tolerance. when the erase pin is tied high during less than 100 ms, it is not taken into account. the pin must be tied high during more than 220 ms to perform a flash erase operation. the erase pin is a system i/o pin and can be used as a standard i/o. at startup, the erase pin is not configured as a pio pin. if the erase pin is used as a standa rd i/o, startup level of this pin must be low to prevent unwanted erasing. please refer to section 9.3 ?peripheral signal multiplexing on i/o lines? on page 34 . also, if the erase pin is us ed as a standar d i/o output, asserting the pin to low does not erase the flash.
26 11011a?atarm?04-oct-10 sam3n 7. memories 7.1 product mapping figure 7-1. sam3n4/2/1 product mapping addre ss memory s p a ce code 0x00000000 s ram 0x20000000 peripher a l s 0x40000000 0x60000000 0xa0000000 s y s tem 0xe0000000 0xffffffff offset id peripher a l block code boot memory 0x00000000 intern a l fl as h intern a l rom 0x00400000 0x00800000 0x00c00000 0x1fffffff peripher a l s 0x40000000 0x40004000 s pi 21 0x40008000 0x4000c000 tc0 tc0 0x40010000 23 tc0 tc1 +0x40 24 tc0 tc2 +0x80 25 tc1 tc 3 0x40014000 26 tc1 tc4 +0x40 27 tc1 tc5 +0x80 28 twi0 19 0x40018000 twi1 20 0x4001c000 pwm 31 0x40020000 14 0x40024000 0x40028000 0x4002c000 adc 29 0x40038000 dacc 30 0x4003c000 0x40040000 0x40044000 0x40048000 s y s tem controller 0x400e0000 0x400e2600 0x40100000 s y s tem controller 0x400e0000 matrix 0x400e0200 pmc 5 0x400e0400 uart0 uart1 8 0x400e0600 chipid 0x400e0740 9 0x400e0800 eefc 6 0x400e0a00 0x400e0c00 11 0x400e0e00 piob pioa 12 0x400e1000 pioc 13 0x400e1200 sysc r s tc 0x400e1400 1 sysc s upc +0x10 sysc rtt +0x30 3 sysc wdt +0x50 4 sysc rtc +0x60 2 sysc gpbr +0x90 0x400e1600 0x4007ffff re s erved re s erved re s erved re s erved re s erved re s erved re s erved re s erved re s erved re s erved u s art0 re s erved 0x40200000 re s erved re s erved 3 2 mbyte s b it ba nd a li as 3 2 mbyte s b it ba nd a li as 0x60000000 re s erved re s erved u s art1 15 re s erved re s erved 0x40400000 0x20100000 0x22000000 0x24000000 undefined 1 mbyte b it ba nd region 1 mbyte b it ba nd region
27 11011a?atarm?04-oct-10 sam3n 7.2 embedded memories 7.2.1 internal sram the sam3n4 product embeds a total of 24-kbytes high-speed sram. the sam3n2 product embeds a total of 16-kbytes high-speed sram. the sam3n1 product embeds a total of 8-kbytes high-speed sram. the sram is accessible over system cortex-m3 bus at address 0x2000 0000. the sram is in the bit band region. the bit band alias region is from 0x2200 0000 and 0x23ff ffff. ram size must be configurable by calibration fuses. 7.2.2 internal rom the sam3n product embeds an internal rom, which contains the sam boot assistant (sam-ba), in application programming routines (iap) and fast flash programming interface (ffpi). at any time, the rom is mapped at address 0x0080 0000. 7.2.3 embedded flash 7.2.3.1 flash overview the flash of the sam3n4 (256 kbytes) is organized in one bank of 1024 pages of 256 bytes (single plane). the flash of the sam3n2 (128 kbytes) is organize d in one bank of 512 pages of 256 bytes (sin- gle plane). the flash of the sam3n1 (64 kbytes) is organized in one bank of 256 pages of 256 bytes (sin- gle plane). the flash contains a 128-byte write buffer, accessible through a 32-bit interface. 7.2.3.2 flash power supply the flash is supplied by vddcore. 7.2.3.3 enhanced embedded flash controller the enhanced embedded flash controller (eef c) manages accesses performed by the mas- ters of the system. it enab les reading the flash and writing t he write buffer. it also contains a user interface, mapped on the apb. the enhanced embedded flash controller ensures the interface of the flash block with the 32- bit internal bus. its 128-bit wide memory interface increases performance. the user can choose between high performance or lower current consumption by selecting either 128-bit or 64-bit access. it also manages the programming, erasing, locking and unlocking sequences of the flash using a full set of commands. one of the commands returns the embedded flash descriptor definition that informs the system about the flash organization, thus making the software generic.
28 11011a?atarm?04-oct-10 sam3n 7.2.3.4 flash speed the user needs to set the number of wait states depending on the frequency used. for more details, refer to the ac characteristic s sub section in the ?electrical characteristics? section. 7.2.3.5 lock regions several lock bits used to protect write and er ase operations on lock regions. a lock region is composed of several consecutive pages, and each lock region has its associated lock bit. if a locked-region?s erase or program command occurs, the command is aborted and the eefc triggers an interrupt. the lock bits are software programmable through the eefc user interface. the command ?set lock bit? enables the protection. the command ?clear lock bit? unlocks the lock region. asserting the erase pin clears the lock bits, thus unlocking the entire flash. 7.2.3.6 security bit feature the sam3n features a security bit, based on a specific general purpose nvm bit (gpnvm bit 0). when the security is enabled, any access to the flash, either through the ice interface or through the fast flash programming interface, is forbidden. this ensures the confidentiality of the code programmed in the flash. this security bit can only be enabled, through the command ?set general purpose nvm bit 0? of the eefc user interface. disabling the security bit can only be achieved by asserting the erase pin at 1, after a full flash erase is performed. when the security bit is deactivated, all accesses to the flash are permitted. it is important to note that the assertion of the erase pin should always be longer than 200 ms. as the erase pin integrates a permanent pull-down, it can be left unconnected during normal operation. however, it is safer to connect it directly to gnd fo r the final application. 7.2.3.7 calibration bits nvm bits are used to calibrate the brownout detector and the voltage regulator. these bits are factory configured and cannot be changed by the user. the erase pin has no effect on the cal- ibration bits. 7.2.3.8 unique identifier each device integrates its own 128-bit unique ident ifier. these bits are factory configured and cannot be changed by the user. the erase pin has no e ffect on the unique identifier. table 7-1. lock bit number product number of lock bits lock region size sam3n4 16 16 kbytes (64 pages) sam3n2 8 16 kbytes (64 pages) sam3n1 4 16 kbytes (64 pages)
29 11011a?atarm?04-oct-10 sam3n 7.2.3.9 fast flash programming interface the fast flash programming interface allows programming the device through either a serial jtag interface or through a multiplexed fully-handshaked parallel port. it allows gang program- ming with market-standard industrial programmers. the ffpi supports read, page program, page erase, full erase, lock, unlock and protect commands. the fast flash programming interface is enabled and the fast programming mode is entered when tst and pa0 and pa1are tied low. 7.2.3.10 sam-ba boot the sam-ba boot is a default boot program which provides an easy way to program in-situ the on-chip flash memory. the sam-ba boot assistant supports serial communication via the uart0. the sam-ba boot provides an interface with sam-ba graphic user interface (gui). the sam-ba boot is in rom and is mapped in flash at address 0x0 when gpnvm bit 1 is set to 0. 7.2.3.11 gpnvm bits the sam3n features three gpnvm bits that can be cleared or set respectively through the com- mands ?clear gpnvm bit? and ?set gp nvm bit? of the eefc user interface. 7.2.4 boot strategies the system always boots at address 0x0. to ens ure a maximum boot possibilities the memory layout can be changed via gpnvm. a general purpose nvm (gpnvm) bit is used to boot either on the rom (default) or from the flash. the gpnvm bit can be cleared or set respectively through the commands ?clear general-pur- pose nvm bit? and ?set general-purpose nvm bit? of the eefc user interface. setting the gpnvm bit 1 selects the boot from the flash, clearing it selects the boot from the rom. asserting erase clears the gpnvm bit 1 and thus selects the boot from the rom by default. table 7-2. general-purpose non volatile memory bits gpnvmbit[#] function 0 security bit 1 boot mode selection
30 11011a?atarm?04-oct-10 sam3n 8. system controller the system controller is a set of peripherals, which allow handling of key elements of the sys- tem, such as power, resets, clocks, time, interrupts, watchdog, etc... see the system controller block diagram in figure 8-1 on page 31 .
31 11011a?atarm?04-oct-10 sam3n figure 8-1. system controller block diagram s oftw a re controlled volt a ge reg u l a tor adc pioa/b/c m a trix s ram cortex-m 3 fl as h peripher a l s peripher a l bridge zero-power power-on re s et su pply monitor (b a ck u p) rtc em b edded 3 2 khz rc o s cill a tor xt a l 3 2 khz o s cill a tor su pply controller browno u t detector (core) gener a l p u rpo s e b a ck u p regi s ter s re s et controller b a ck u p power su pply core power su pply vr_on vr_mode b od_on b rown_o u t rtc_ a l a rm s lck rtc_nre s et proc_nre s et periph_nre s et ice_nre s et m as ter clock mck s lck core_nre s et m a in clock mainck s lck nr s t f s tt0 - f s tt15 xin 3 2 xout 3 2 o s c 3 2k_xt a l_en o s c 3 2k_ s el s low clock s lck o s c 3 2k_rc_en core_nre s et vddio vddcore vddout advref adx wkup0 - wkup15 b od_core_on lcore_ b rown_o u t rtt rtt_ a l a rm s lck rtt_nre s et xin xout vddio vddin piox dac dac0 pll f s tt0 - f s tt15 a re po ss i b le f as t s t a rt u p s o u rce s , gener a ted b y wkup0-wkup15 pin s , bu t a re not phy s ic a l pin s . em b edded 12/ 8 /4 mhz rc o s cill a tor xt a l o s cill a tor w a tchdog timer power m a n a gement controller
32 11011a?atarm?04-oct-10 sam3n 8.1 system controller and peripheral mapping please refer to figure 7-1, "sam3n4/2/1 product mapping" on page 26 . all the peripherals are in the bit band region and are mapped in the bit band alias region. 8.2 power-on-reset, brownout and supply monitor the sam3n embeds three features to monitor, warn and/or reset the chip: ? power-on-reset on vddio ? brownout detector on vddcore ? supply monitor on vddio 8.2.1 power-on-reset the power-on-reset monitors vddi o. it is always activated and monitors voltage at start up but also during power down. if vddio goes below the threshold voltage, the entire chip is reset. for more information, refer to the ?electrical characteristics? section of the datasheet. 8.2.2 brownout detector on vddcore the brownout detector monitors v ddcore. it is active by default. it can be deactivated by soft- ware through the supply controller (supc_mr). it is especially recommended to disable it during low-power modes such as wait or sleep modes. if vddcore goes below the thresh old voltage, the reset of the co re is asserted. for more infor- mation, refer to the supply controller (supc) and electrical characteristics sections of the datasheet. 8.2.3 supply monitor on vddio the supply monitor monitors vddio. it is inactive by default. it can be activated by software and is fully programmable with 16 steps for the thres hold (between 1.9v to 3.4v). it is controlled by the supply controller (supc). a samp le mode is possible. it allows to divide the supply monitor power consumption by a factor of up to 2048. for more information, refer to the supply control- ler and electrical characteristics sections of the datasheet.
33 11011a?atarm?04-oct-10 sam3n 9. peripherals 9.1 peripheral identifiers table 9-1 defines the peripheral identifiers of the sam3n4/2/1. a peripheral identifier is required for the control of the peripheral interrupt with the nested vectored interrupt controller and for the control of the peripheral clock with the power management controller. table 9-1. peripheral identifiers instance id instance name nv ic interrupt pmc clock co ntrol instance description 0 supc x supply controller 1 rstc x reset controller 2 rtc x real time clock 3 rtt x real time timer 4 wdt x watchdog timer 5 pmc x power management controller 6 eefc x enhanced flash controller 7 - - reserved 8 uart0 xx uart 0 9 uart1 xx uart 1 10 - -- reserved 11 pioa xx parallel i/o controller a 12 piob xx parallel i/o controller b 13 pioc xx parallel i/o controller c 14 usart0 xx usart 0 15 usart1 xx usart 1 16 - -- reserved 17 - -- reserved 18 - -- reserved 19 twi0 xx two wire interface 0 20 twi1 xx two wire interface 1 21 spi xx serial peripheral interface 22 - -- reserved 23 tc0 xx timer/counter 0 24 tc1 xx timer/counter 1 25 tc2 xx timer/counter 2 26 tc3 xx timer/counter 3 27 tc4 xx timer/counter 4 28 tc5 xx timer/counter 5 29 adc xx analog-to-digital converter 30 dacc xx digital-to-analog converter 31 pwm xx pulse width modulation
34 11011a?atarm?04-oct-10 sam3n 9.2 apb/ahb bridge the sam3n4/2/1 product embeds one peripheral bridge: the peripherals of the bridge are clocked by mck. 9.3 peripheral signal mult iplexing on i/o lines the sam3n product features 2 pio controllers ( 48-pin and 64-pin version) or 3 pio controllers (100-pin version), pioa, piob and pioc, that multiplex the i/o lines of the peripheral set. the sam3n 64-pin and 100-pin pio controller controls up to 32 lines (see table 9-2, ?multiplex- ing on pio controller a (pioa),? on page 35 ). each line can be assigned to one of three peripheral functions: a, b or c. the multiplexing tables in the following paragraphs define how the i/o lines of the peripherals a, b and c are multiplexed on the pio controllers. the column ?comments? has been inserted in this table for the user?s own comments; it may be used to track how pins are defined in an application. note that some peripheral functions which are ou tput only, might be duplicated within the tables.
35 11011a?atarm?04-oct-10 sam3n 9.3.1 pio controller a multiplexing table 9-2. multiplexing on pi o controller a (pioa) i/o line peripheral a peripheral b periphera l c extra function system function comments pa0 pwm0 tioa0 wkup0 high drive pa1 pwm1 tiob0 wkup1 high drive pa2 pwm2 sck0 datrg wkup2 high drive pa 3 t w d 0 n p c s 3 high drive pa4 twck0 tclk0 wkup3 pa5 rxd0 npcs3 wkup4 pa 6 t x d 0 p c k 0 pa 7 rt s 0 p w m 3 x i n 3 2 pa8 cts0 adtrg wkup5 xout32 pa9 urxd0 npcs1 wkup6 pa10 utxd0 npcs2 pa11 npcs0 pwm0 wkup7 pa12 miso pwm1 pa13 mosi pwm2 pa14 spck pwm3 wkup8 pa15 tioa1 wkup14 pa16 tiob1 wkup15 pa17 pck1 ad0 pa18 pck2 ad1 pa19 ad2/wkup9 pa20 ad3/wkup10 pa21 rxd1 pck1 ad8 64/100-pin versions pa22 txd1 npcs3 ad9 64/100-pin versions pa23 sck1 pwm0 64/100-pin versions pa24 rts1 pwm1 64/100-pin versions pa25 cts1 pwm2 64/100-pin versions pa26 tioa2 64/100-pin versions pa27 tiob2 64/100-pin versions pa28 tclk1 64/100-pin versions pa29 tclk2 64/100-pin versions pa30 npcs2 wkup11 64/100-pin versions pa31 npcs1 pck2 64/100-pin versions
36 11011a?atarm?04-oct-10 sam3n 9.3.2 pio controller b multiplexing table 9-3. multiplexing on pi o controller b (piob) i/o line peripheral a peripheral b peripheral c extra function syst em function comments pb0 pwm0 ad4 pb1 pwm1 ad5 pb2 urxd1 npcs2 ad6/wkup12 pb3 utxd1 pck2 ad7 pb4 twd1 pwm2 tdi pb5 twck1 wkup13 tdo/ traceswo pb6 tms/swdio pb7 tck/swclk pb8 xout pb9 xin pb10 pb11 pb12 erase pb13 pck0 dac0 64/100-pin versions pb14 npcs1 pwm3 64/100-pin versions
37 11011a?atarm?04-oct-10 sam3n 9.3.3 pio controller c multiplexing i/o line peripheral a peripheral b periphera l c extra function system function comments pc0 100-pin version pc1 100-pin version pc2 100-pin version pc3 100-pin version pc4 npcs1 100-pin version pc5 100-pin version pc6 100-pin version pc7 npcs2 100-pin version pc8 pwm0 100-pin version pc9 pwm1 100-pin version pc10 pwm2 100-pin version pc11 pwm3 100-pin version pc12 ad12 100-pin version pc13 ad10 100-pin version pc14 pck2 100-pin version pc15 ad11 100-pin version pc16 pck0 100-pin version pc17 pck1 100-pin version pc18 pwm0 100-pin version pc19 pwm1 100-pin version pc20 pwm2 100-pin version pc21 pwm3 100-pin version pc22 pwm0 100-pin version pc23 tioa3 100-pin version pc24 tiob3 100-pin version pc25 tclk3 100-pin version pc26 tioa4 100-pin version pc27 tiob4 100-pin version pc28 tclk4 100-pin version pc29 tioa5 ad13 100-pin version pc30 tiob5 ad14 100-pin version pc31 tclk5 ad15 100-pin version
38 11011a?atarm?04-oct-10 sam3n
39 11011a?atarm?04-oct-10 sam3n 10. arm cortex ? m3 processor 10.1 about this section this section provides the inform ation required for application and system-level software devel- opment. it does not provide information on debug components, features, or operation. this material is for microcontroller software and hardware engineers, including those who have no experience of arm products. note: the information in this section is reproduced from source material provided to atmel by arm ltd. in terms of atmel?s license for the arm cortex ? -m3 processor core. this information is copyright arm ltd., 2008 - 2009. 10.2 embedded characteristics ? version 2.0 ? thumb-2 (isa) subset consisting of all base thumb-2 instructions, 16-bit and 32-bit. ? harvard processor architecture enabling simultaneous instruction fetch with data load/store. ? three-stage pipeline. ? single cycle 32-bit multiply. ? hardware divide. ? thumb and debug states. ? handler and thread modes. ? low latency isr entry and exit. ? systick timer ? 24-bit down counter ? self-reload capability ? flexible system timer ? nested vectored interrupt controller ? thirty two maskable external interrupts ? sixteen priority levels ? processor state automatically saved on interrupt entry, and restored on ? dynamic reprioritization of interrupts ? priority grouping selection of pre-empting interrupt le vels and non pre-empting interrupt levels ? support for tail-chaining and late arrival of interrupts back-to-back interrupt processing without the overhead of state saving and restoration between interrupts. processor state automatically saved on interrupt entry and restored on interrupt exit, with no instruction overhead 10.3 about the cortex-m3 pr ocessor and cor e peripherals ? the cortex-m3 processor is a high performance 32-bit processor designed for the microcontroller market. it offers significant benefits to developers, including: ? outstanding processing performance combined with fast interrupt handling
40 11011a?atarm?04-oct-10 sam3n ? enhanced system debug with extensiv e breakpoint and trace capabilities ? efficient processor core, system and memories ? ultra-low power consumption with integrated sleep modes figure 10-1. typical cortex-m3 implementation the cortex-m3 processor is built on a high-performance processor core, with a 3-stage pipeline harvard architecture, making it ideal for demanding embedded applications. the processor delivers exceptional power efficiency through an efficient instruction set and extensively opti- mized design, providing high-end proce ssing hardware including single-cycle 32x32 multiplication and dedicated hardware division. to facilitate the design of cost-sensitive device s, the cortex-m3 processor implements tightly- coupled system components that reduce processo r area while significantly improving interrupt handling and system debug capabilitie s. the cortex-m3 processor implements a version of the thumb ? instruction set, ensuring high code density and reduced program memory requirements. the cortex-m3 instruction set provides the exceptional performance expected of a modern 32- bit architecture, with the high code densit y of 8-bit and 16-bit microcontrollers. the cortex-m3 processor closely integrates a configurable nested interrupt controlle r (nvic), to deliver industry-leading interrupt performance. the nvic provides up to 16 interrupt priority lev- els. the tight integration of the processor core and nvic provides fast execution of interrupt service routines (isrs), dramatically reducing the interrup t latency. this is achieved through the hardware stacking of registers, and the ability to sus pend load-multiple and store-mu ltiple opera- tions. interrupt handlers do not require any assembler stubs, removing any code overhead from the isrs. tail-chaining optimization also signifi cantly reduces the overhead when switching from one isr to another. to optimize low-power designs, the nvic integrates with the sleep modes, that include a deep sleep function that enables the entire device to be rapidly powered down. processor core nvic debug access port serial wire viewer bus matrix code interface sram and peripheral interface data watchpoints flash patch cortex-m3 processor
41 11011a?atarm?04-oct-10 sam3n 10.3.1 system level interface the cortex-m3 processor provides multiple interfaces using amba ? technology to provide high speed, low latency memory accesses. it su pports unaligned data accesses and implements atomic bit manipulation that enables faster pe ripheral controls, system spinlocks and thread-safe boolean data handling. 10.3.2 integrated configurable debug the cortex-m3 processor implements a complete hardware debug solution. this provides high system visibility of the processor and memory through ei ther a traditional jt ag port or a 2-pin serial wire debug (swd) port that is ideal for microcontrollers and other small package devices. for system trace the proc essor integrates an instrumentation trace macrocell (itm) alongside data watchpoints an d a profiling unit. to enable simple and cost-effective pr ofiling of the system events these generate, a serial wire viewer (swv) can export a stream of software-generated messages, data trace, and profiling informati on through a single pin. 10.3.3 cortex-m3 processor features and benefits summary ? tight integration of system peripherals reduces area and development costs ? thumb instruction set combines high code density with 32-bit performance ? code-patch ability for rom system updates ? power control optimization of system components ? integrated sleep modes for low power consumption ? fast code execution permits slower processor clock or increases sleep mode time ? hardware division and fast multiplier ? deterministic, high-performance interrupt handling for time-critical applications ? extensive debug and trace capabilities: ? serial wire debug and serial wire trace reduce the number of pins required for debugging and tracing. 10.3.4 cortex-m3 core peripherals these are: 10.3.4.1 nested vectored interrupt controller the nested vectored interrupt controller (nvic) is an embedded interrupt controller that sup- ports low latency interrupt processing. 10.3.4.2 system control block the system control block (scb) is the programmers model interface to the processor. it pro- vides system implementation info rmation and system control, in cluding configuration, control, and reporting of system exceptions. 10.3.4.3 system timer the system timer, systick, is a 24 -bit count-down timer. use this as a real time operating sys- tem (rtos) tick timer or as a simple counter.
42 11011a?atarm?04-oct-10 sam3n 10.4 programmers model this section describes the cortex-m3 programmers model. in addition to the individual core reg- ister descriptions, it contains information about the processor modes and privilege levels for software execution and stacks. 10.4.1 processor mode and privilege levels for software execution the processor modes are: 10.4.1.1 thread mode used to execute application software. the processor enters thread mode when it comes out of reset. 10.4.1.2 handler mode used to handle exceptions. the processor returns to thread m ode when it has finished excep- tion processing. the privilege levels for software execution are: 10.4.1.3 unprivileged the software: ? has limited access to the msr and mrs inst ructions, and cannot use the cps instruction ? cannot access the system timer, nvic, or system control block ? might have restricted access to memory or peripherals. unprivileged software executes at the unprivileged level. 10.4.1.4 privileged the software can use all the instructions and has access to all resources. privileged software executes at the privileged level. in thread mode, the control register controls whether software execution is privileged or unprivileged, see ?control register? on page 52 . in handler mode, software execution is always privileged. only privileged software can write to the control register to change the privilege level for software execution in thread mode. unprivileged software can use the svc instruction to make a supervisor call to transfer control to privileged software. 10.4.2 stacks the processor uses a full descend ing stack. this means the st ack pointer indicates the last stacked item on the stack memory. when the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. the proces- sor implements two stacks, the main stack and the process stack , with independent copies of the stack pointer, see ?stack pointer? on page 44 .
43 11011a?atarm?04-oct-10 sam3n in thread mode, the control register controls whether the processor uses the main stack or the process stack, see ?control register? on page 52 . in handler mode, the processor always uses the main stack. the options for processor operations are: 10.4.3 core registers the processor core registers are: table 10-1. summary of processor mode, execution privilege level, and stack use options processor mode used to execute privilege level for software execution stack used thread applications privileged or unprivileged (1) 1. see ?control register? on page 52 . main stack or process stack (1) handler exception handlers always privileged main stack sp (r13) lr (r14) pc (r15) r5 r6 r7 r0 r1 r3 r4 r2 r10 r11 r12 r8 r9 low registers high registers msp ? psp ? psr primask faultmask basepri control general-purpose registers stack pointer link register program counter program status register exception mask registers control register special registers ? banked version of sp
44 11011a?atarm?04-oct-10 sam3n 10.4.3.1 general-purpose registers r0-r12 are 32-bit general-purpose registers for data operations. 10.4.3.2 stack pointer the stack pointer (sp) is register r13. in thread mode, bit[1] of the control register indi- cates the stack pointer to use: ?0 = main stack pointer (msp). this is the reset value. ?1 = process stack pointer (psp). on reset, the processor loads the msp with the value from address 0x00000000 . 10.4.3.3 link register the link register (lr) is register r14. it stores the return information for subroutines, function calls, and exceptions. on reset, the processor loads the lr value 0xffffffff . table 10-2. core register set summary name type (1) 1. describes access type during program execution in thread mode and handler mode. debug access can differ. required privilege (2) 2. an entry of either means privileged and unp rivileged software can access the register. reset value description r0-r12 rw either unknown ?general-purpose registers? on page 44 msp rw privileged see description ?stack pointer? on page 44 psp rw either unknown ?stack pointer? on page 44 lr rw either 0xffffffff ?link register? on page 44 pc rw either see description ?program counter? on page 45 psr rw privileged 0x01000000 ?program status register? on page 46 aspr rw either 0x00000000 ?application program status register? on page 47 ipsr ro privileged 0x00000000 ?interrupt program status register? on page 48 epsr ro privileged 0x01000000 ?execution program status register? on page 49 primask rw privileged 0x00000000 ?priority mask register? on page 50 faultmask rw privileged 0x00000000 ?fault mask register? on page 50 basepri rw privileged 0x00000000 ?base priority mask register? on page 51 control rw privileged 0x00000000 ?control register? on page 52
45 11011a?atarm?04-oct-10 sam3n 10.4.3.4 program counter the program counter (pc) is register r15. it contains the current program address. bit[0] is always 0 because instruction fetches must be halfword aligned. on reset, the processor loads the pc with the value of the reset vector, which is at address 0x00000004 .
46 11011a?atarm?04-oct-10 sam3n 10.4.3.5 program status register the program status register (psr) combines: ? application program status register (apsr) ? interrupt program status register (ipsr) ? execution program status register (epsr). these registers are mutually exclusive bitfields in the 32-bit psr. the bit assignments are: ? apsr: ? ipsr: ? epsr: 31 30 29 28 27 26 25 24 n z c v q reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 76543210 reserved 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved isr_number 76543210 isr_number 31 30 29 28 27 26 25 24 reserved ici/it t 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 ici/it reserved 76543210 reserved
47 11011a?atarm?04-oct-10 sam3n the psr bit assignments are: access these registers individually or as a combination of any tw o or all three registers, using the register name as an argument to the msr or mrs instructions. for example: ? read all of the registers usin g psr with the mrs instruction ? write to the apsr using apsr with the msr instruction. the psr combinations and attributes are: see the instruction descriptions ?mrs? on page 143 and ?msr? on page 144 for more informa- tion about how to access the program status registers. 10.4.3.6 application program status register the apsr contains the current stat e of the condition fl ags from previous in struction executions. see the register summary in table 10-2 on page 44 for its attributes. the bit assignments are: ?n negative or less than flag: 0 = operation result was positive, zero, greater than, or equal 1 = operation result was negative or less than. ?z zero flag: 0 = operation result was not zero 1 = operation result was zero. 31 30 29 28 27 26 25 24 n z c v q ici/it t 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 ici/it reserved isr_number 76543210 isr_number table 10-3. psr register combinations register type combination psr rw (1), (2) 1. the processor ignores writes to the ipsr bits. 2. reads of the epsr bits return zero, and the proces- sor ignores writes to the these bits. apsr, epsr, and ipsr iepsr ro epsr and ipsr iapsr rw (1) apsr and ipsr eapsr rw (2) apsr and epsr
48 11011a?atarm?04-oct-10 sam3n ?c carry or borrow flag: 0 = add operation did not result in a carry bit or subtract operation resulted in a borrow bit 1 = add operation resulted in a carry bit or subtract operation did not result in a borrow bit. ?v overflow flag: 0 = operation did not result in an overflow 1 = operation resulted in an overflow. ?q sticky saturation flag: 0 = indicates that saturation has not occurred since reset or since the bit was last cleared to zero 1 = indicates when an ssat or usat instruction results in saturation. this bit is cleared to zero by software using an mrs instruction. 10.4.3.7 interrupt program status register the ipsr contains the exception type number of the current interrupt service routine (isr). see the register summary in table 10-2 on page 44 for its attributes. the bit assignments are: ?isr_number this is the number of the current exception: 0 = thread mode 1 = reserved 2 = nmi 3 = hard fault 4 = memory management fault 5 = bus fault 6 = usage fault 7-10 = reserved 11 = svcall 12 = reserved for debug 13 = reserved 14 = pendsv 15 = systick 16 = irq0 26 = irq32 see ?exception types? on page 63 for more information.
49 11011a?atarm?04-oct-10 sam3n 10.4.3.8 execution program status register the epsr contains the thumb state bit, and the execution state bits for either the: ? if-then (it) instruction ? interruptible-continuable instruction (ici) field for an interrupted load multiple or store multiple instruction. see the register summary in table 10-2 on page 44 for the epsr attributes. the bit assign- ments are: ?ici interruptible-continuable instruction bits, see ?interruptible-continuable instructions? on page 49 . ?it indicates the execution state bits of the it instruction, see ?it? on page 133 . ?t always set to 1. attempts to read the epsr directly through applicatio n software using the msr instruction always return zero. atte mpts to write the epsr using the ms r instruction in application software are ignored. fault handlers can examine epsr value in the stacked psr to indicate the opera- tion that is at fault. see ?exception entry and return? on page 68 10.4.3.9 interruptible-continuable instructions when an interrupt occurs during the execution of an ldm or stm instruction, the processor: ? stops the load multiple or store multiple instruction operation temporarily ? stores the next register operand in th e multiple operation to epsr bits[15:12]. after servicing the interrupt, the processor: ? returns to the register pointed to by bits[15:12] ? resumes execution of the multiple load or store instruction. when the epsr holds ici execution state, bits[26:25,11:10] are zero. 10.4.3.10 if-then block the if-then block contains up to four instructions following a 16-bit it in struction. each instruc- tion in the block is conditional. the conditions for the instructions are either all the same, or some can be the inverse of others. see ?it? on page 133 for more information. 10.4.3.11 exception mask registers the exception mask registers disable the handling of exceptions by the processor. disable exceptions where they might impact on timing critical tasks. to access the exception mask registers use the msr and mrs instructions, or the cps instruc- tion to change the value of primask or faultmask. see ?mrs? on page 143 , ?msr? on page 144 , and ?cps? on page 139 for more information.
50 11011a?atarm?04-oct-10 sam3n 10.4.3.12 priority mask register the primask register prevents activation of all exceptions with configurable priority. see the register summary in table 10-2 on page 44 for its attributes. the bit assignments are: ?primask 0 = no effect 1 = prevents the activation of all exceptions with configurable priority. 10.4.3.13 fault mask register the faultmask register prevents activation of all exceptions. see the register summary in table 10-2 on page 44 for its attributes. the bit assignments are: ?faultmask 0 = no effect 1 = prevents the activation of all exceptions. the processor clears the faultmask bit to 0 on ex it from any exception handl er except the nmi handler. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 76543210 reserved primask 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 76543210 reserved faultmask
51 11011a?atarm?04-oct-10 sam3n 10.4.3.14 base priority mask register the basepri register defines t he minimum priority for exce ption processing. when basepri is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the basepri value. se e the register summary in table 10-2 on page 44 for its attri- butes. the bit assignments are: ? basepri priority mask bits: 0x0000 = no effect nonzero = defines the base priority for exception processing. the processor does not pr ocess any exception with a priority va lue greater than or equal to basepri. this field is similar to the priority fields in the interrupt pr iority registers. the processor implements only bits[7:4] of th is field, bits[3:0] read as zero and ignore writes. see ?interrupt priority registers? on page 158 for more information. remember that higher priority field values correspond to lower exception priorities. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 76543210 basepri
52 11011a?atarm?04-oct-10 sam3n 10.4.3.15 control register the control register controls the stack used and the privilege level for software execution when the processor is in thread mode. see the register summary in table 10-2 on page 44 for its attributes. the bit assignments are: ? active stack pointer defines the cu rrent stack: 0 = msp is the current stack pointer 1 = psp is the current stack pointer. in handler mode this bit reads as zero and ignores writes. ? thread mode privilege level defines the thread mode privilege level: 0 = privileged 1 = unprivileged. handler mode always uses the msp, so the processor ignores ex plicit writes to the active stack pointer bit of the con- trol register when in handler mode. the exception entry and return mechanisms update the control register. in an os environment, arm recommends that threads running in thread mode use the process stack and the kernel and exception handlers use the main stack. by default, thread mode uses the msp. to switch the stack point er used in thread mode to the psp, use the msr instruc- tion to set the active stack pointer bit to 1, see ?msr? on page 144 . when changing the stack pointer, software must use an isb in struction immediately after the msr instruction. this ensures that instructions after the isb execute using the new stack pointer. see ?isb? on page 142 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 76543210 reserved active stack pointer thread mode privilege level
53 11011a?atarm?04-oct-10 sam3n 10.4.4 exceptions and interrupts the cortex-m3 processor supports interrupts and system exceptions. the processor and the nested vectored interrupt controller (nvic) prioritize and handle all exceptions. an exception changes the normal flow of software control. the processor uses handler mode to handle all exceptions except for reset. see ?exception entry? on page 69 and ?exception return? on page 70 for more information. the nvic registers control interrupt handling. see ?nested vectored interrupt controller? on page 151 for more information. 10.4.5 data types the processor: ? supports the following data types: ? 32-bit words ? 16-bit halfwords ? 8-bit bytes ? supports 64-bit data transfer instructions. ? manages all data memory accesses as little-endian. instruction memory and private peripheral bus (ppb) accesses are alwa ys little-endian. see ?memory regions, types and attributes? on page 55 for more information. ? 10.4.6 the cortex microcontroller software interface standard for a cortex-m3 microcontroller system, the cortex microcontroller software interface standard (cmsis) defines: ? a common way to: ? access peripheral registers ? define exception vectors ? the names of: ? the registers of the core peripherals ? the core exception vectors ? a device-independent interface for rtos kernels, including a debug channel. the cmsis includes address definitions and data structures for the core peripherals in the cor- tex-m3 processor. it also includes optional interfaces for middleware components comprising a tcp/ip stack and a flash file system. cmsis simplifies software development by enabling the reuse of template code and the combi- nation of cmsis-compliant software components from various middleware vendors. software vendors can expand the cmsis to include their peripheral definitions and access functions for those peripherals. this document includes the register names defined by the cmsis, and gives short descriptions of the cmsis functions that address the processor core and the core peripherals. this document uses the register short names defined by the cmsis. in a few cases these differ from the architectural short names that might be used in other documents. the following sections give more information about the cmsis:
54 11011a?atarm?04-oct-10 sam3n ? ?power management programming hints? on page 74 ? ?intrinsic functions? on page 78 ? ?the cmsis mapping of the cortex-m3 nvic registers? on page 151 ? ?nvic programming hints? on page 163 .
55 11011a?atarm?04-oct-10 sam3n 10.5 memory model this section describes the processor memory m ap, the behavior of memory accesses, and the bit-banding features. the processor has a fixe d memory map that provides up to 4gb of addressable memory. the memory map is: the regions for sram and peripherals includ e bit-band regions. bit-banding provides atomic operations to bit data, see ?bit-banding? on page 59 . the processor reserves regions of the private peripheral bus (ppb) address range for core peripheral registers, see ?about the cortex-m3 peripherals? on page 150 . this memory mapping is generic to arm cortex -m3 products. to get the specific memory map- ping of this product, refer to the memories section of the datasheet. 10.5.1 memory regions, types and attributes the memory map split the memory map into regions. each region has a defined memory type, and some regions have additional memory attributes. the memory type and attributes determine the behavior of accesses to the region. the memory types are: vendor-specific memory external device external ram peripheral sram code 0xffffffff private peripheral bus 0xe0100000 0xe00fffff 0x9fffffff 0xa0000000 0x5fffffff 0x60000000 0x3fffffff 0x40000000 0x1fffffff 0x20000000 0x00000000 0x40000000 bit band region bit band alias 32mb 1mb 0x400fffff 0x42000000 0x43ffffff bit band region bit band alias 32mb 1mb 0x20000000 0x200fffff 0x22000000 0x23ffffff 1.0gb 1.0gb 0.5gb 0.5gb 0.5gb 0xdfffffff 0xe0000000 1.0mb 511mb
56 11011a?atarm?04-oct-10 sam3n 10.5.1.1 normal the processor can re-order transactions fo r efficiency, or perform speculative reads. 10.5.1.2 device the processor preserves transaction order relative to other transactions to device or strongly- ordered memory. 10.5.1.3 strongly-ordered the processor preserves transaction order relative to all other transactions. the different ordering requirements for device and strongly-ordered memory mean that the memory system can buffer a write to device memo ry, but must not buffer a write to strongly- ordered memory. the additional memory attributes include. 10.5.1.4 shareable for a shareable memory region, the memory system provides data synchronization between bus masters in a system with multiple bus ma sters, for example, a processor with a dma controller. strongly-ordered memory is always shareable. if multiple bus masters can access a non-shareable memory region, software must ensure data coherency between the bus masters. 10.5.1.5 execute never (xn) means the processor prevents instruction accesses. any attempt to fetch an instruction from an xn region causes a memory management fault exception. 10.5.2 memory system ordering of memory accesses for most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing this does not affect the behavior of the instruction sequence. nor- mally, if correct program execution depends on two memory accesses completing in program order, software must insert a memory barrier instruction between the memory access instruc- tions, see ?software ordering of memory accesses? on page 58 . however, the memory system does guarantee some ordering of accesses to device and strongly-ordered memory. for two memory access instructions a1 and a2, if a1 occurs before a2 in program order, the ordering of the memory accesses caused by two instructions is: where: - means that the memory system does not guarantee the ordering of the accesses. normal access device access, non-shareable device access, shareable strongly-ordered access normal access non-shareable shareable strongly- ordered access device access a1 a2 - - - - - < - < - - < < - < < <
57 11011a?atarm?04-oct-10 sam3n < means that accesses are observed in program or der, that is, a1 is always observed before a2. 10.5.3 behavior of memory accesses the behavior of accesses to each region in the memory map is: the code, sram, and external ram regions can hold programs. however, arm recommends that programs always use the code region. this is because the processor has separate buses that enable instruction fetches and data accesses to occur simultaneously. 10.5.3.1 additional memory access constraints for shared memory when a system includes shared memory, some memory regions have ad ditional access con- straints, and some regions are subdivided, as table 10-5 shows: table 10-4. memory access behavior address range memory region memory type xn description 0x00000000 - 0x1fffffff code normal (1) 1. see ?memory regions, types and attributes? on page 55 for more information. - executable region for program code. you can also put data here. 0x20000000 - 0x3fffffff sram normal (1) - executable region for data. you can also put code here. this region includes bit band and bit band alias areas, see table 10-6 on page 59 . 0x40000000 - 0x5fffffff peripheral device (1) xn this region includes bit band and bit band alias areas, see table 10-6 on page 59 . 0x60000000 - 0x9fffffff external ram normal (1) - executable region for data. 0xa0000000 - 0xdfffffff external device device (1) xn external device memory 0xe0000000 - 0xe00fffff private peripheral bus strongly- ordered (1) xn this region includes the nvic, system timer, and system control block. 0xe0100000 - 0xffffffff reserved device (1) xn reserved table 10-5. memory region s hare ability policies address range memory region memory type shareability 0x00000000 - 0x1fffffff code normal (1) - 0x20000000 - 0x3fffffff sram normal (1) - 0x40000000 - 0x5fffffff peripheral (2) device (1) - 0x60000000 - 0x7fffffff external ram normal (1) - wbwa (2) 0x80000000 - 0x9fffffff wt (2)
58 11011a?atarm?04-oct-10 sam3n 10.5.4 software ordering of memory accesses the order of instructions in the program flow does not always guarantee the order of the corre- sponding memory transactions. this is because: ? the processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence. ? the processor has multiple bus interfaces ? memory or devices in the memory map have different wait states ? some memory accesses are buffered or speculative. ?memory system ordering of memory accesses? on page 56 describes the cases where the memory system guarantees the order of memory accesses. otherwise, if the order of memory accesses is critical, softwa re must include memory barrier instructions to force that ordering. the processor provides the following memory barrier instructions: 10.5.4.1 dmb the data memory barrier (dmb) instruction ensures that outstanding memory transactions com- plete before subsequent memory transactions. see ?dmb? on page 140 . 10.5.4.2 dsb the data synchronization barrier (dsb) instruction ensures that outstanding memory transac- tions complete before subsequent instructions execute. see ?dsb? on page 141 . 10.5.4.3 isb the instruction synchronization barrier (isb) ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. see ?isb? on page 142 . use memory barrier instructions in, for example: ? vector table. if the program changes an entry in the vector table, and then enables the corresponding exception, use a dmb instruction between the operations. this ensures that if the exception is taken immediately after being enabled the processor uses the new exception vector. ? self-modifying code. if a program contains self-modifying code, use an isb instruction immediately after the code modification in the program. this ensures subsequent instruction execution uses the updated program. 0xa0000000 - 0xbfffffff external device device (1) shareable (1) - 0xc0000000 - 0xdfffffff non- shareable (1) 0xe0000000 - 0xe00fffff private peripheral bus strongly- ordered (1) shareable (1) - 0xe0100000 - 0xffffffff vendor-specific device (2) device (1) -- 1. see ?memory regions, types and attributes? on page 55 for more information. 2. the peripheral and vendor-specific device regions have no additional access constraints. table 10-5. memory region share ab ility policies (continued) address range memory region memory type shareability
59 11011a?atarm?04-oct-10 sam3n ? memory map switching. if the system contains a memory map switching mechanism, use a dsb instruction after switching the memory map in the program. this ensures subsequent instruction execution uses the updated memory map. ? dynamic exception priority change. when an exception priority has to change when the exception is pending or active, use dsb instructions after the change. this ensures the change takes effect on completion of the dsb instruction. ? using a semaphore in multi-master system. if the system contains more than one bus master, for example, if another processor is present in the system, each processor must use a dmb instruction after any semaphore instructions, to ensure other bus masters see the memory transactions in the order in which they were executed. memory accesses to strongly-ordered memory, such as the system control block, do not require the use of dmb instructions. 10.5.5 bit-banding a bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region . the bit-band regions occupy the lowest 1mb of the sram and peripheral memory regions. the memory map has two 32mb alias regions that map to two 1mb bit-band regions: ? accesses to the 32mb sram alias region map to the 1mb sram bit-band region, as shown in table 10-6 ? accesses to the 32mb peripheral alias region map to the 1mb peripheral bit-band region, as shown in table 10-7 . a word access to the sram or peripheral bit-band alias regions map to a single bit in the sram or peripheral bit-band region. the following formula shows how the alias region maps onto the bit-band region: bit_word_offset = (byte_offset x 32) + (bit_number x 4) table 10-6. sram memory bit-banding regions address range memory region instruction and data accesses 0x20000000 - 0x200fffff sram bit-band region direct accesses to this memory range behave as sram memory accesses, but this region is also bit addressable through bit-band alias. 0x22000000 - 0x23ffffff sram bit-band alias data accesses to this region are remapped to bit band region. a write operation is pe rformed as read-modify-write. instruction accesses are not remapped. table 10-7. peripheral memory bit-banding regions address range memory region instruction and data accesses 0x40000000- 0x400fffff peripheral bit-band alias direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. 0x42000000- 0x43ffffff peripheral bit-band region data accesses to this region are remapped to bit band region. a write operation is performed as read-modify-write. instruction accesses are not permitted.
60 11011a?atarm?04-oct-10 sam3n bit_word_addr = bit_band_base + bit_word_offset where: ? bit_word_offset is the position of the target bit in the bit-band memory region. ? bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit. ? bit_band_base is the starting address of the alias region. ? byte_offset is the number of the byte in the bit-band region that contains the targeted bit. ? bit_number is the bit position, 0-7, of the targeted bit. figure 10-2 shows examples of bit-band mapping between the sram bit-band alias region and the sram bit-band region: ? the alias word at 0x23ffffe0 maps to bit[0] of the bit-band byte at 0x200fffff : 0x23ffffe0 = 0x22000000 + ( 0xfffff *32) + (0*4). ? the alias word at 0x23fffffc maps to bit[7] of the bit-band byte at 0x200fffff : 0x23fffffc = 0x22000000 + ( 0xfffff *32) + (7*4). ? the alias word at 0x22000000 maps to bit[0] of the bit-band byte at 0x20000000 : 0x22000000 = 0x22000000 + (0*32) + (0 *4). ? the alias word at 0x2200001c maps to bit[7] of the bit-band byte at 0x20000000 : 0x2200001c = 0x22000000 + (0*32) + (7*4). figure 10-2. bit-band mapping 10.5.5.1 directly accessing an alias region writing to a word in the alias region updates a single bit in the bit-band region. bit[0] of the value written to a word in the alias region determines the value written to the tar- geted bit in the bit-band region. writing a value with bit[0] set to 1 writes a 1 to the bit-band bit, and writing a value with bit[0] set to 0 writes a 0 to the bit-band bit. bits[31:1] of the alias word have no effect on the bit-band bit. writing 0x01 has the same effect as writing 0xff . writing 0x00 has the same effect as writing 0x0e . 0x23ffffe4 0x22000004 0x23ffffe0 0x23ffffe8 0x23ffffec 0x23fffff0 0x23fffff4 0x23fffff8 0x23fffffc 0x22000000 0x22000014 0x22000018 0x2200001c 0x22000008 0x22000010 0x2200000c 32mb alias region 0 7 0 0 7 0x20000000 0x20000001 0x20000002 0x20000003 6 5 4 3 2 1 0 7 6 5 4 3 2 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0x200ffffc 0x200ffffd 0x200ffffe 0x200fffff 1mb sram bit-band region
61 11011a?atarm?04-oct-10 sam3n reading a word in the alias region: ? 0x00000000 indicates that the targeted bit in the bit-band region is set to zero ? 0x00000001 indicates that the targeted bit in the bit-band region is set to 1 10.5.5.2 directly accessing a bit-band region ?behavior of memory accesses? on page 57 describes the behavior of direct byte, halfword, or word accesses to the bit-band regions. 10.5.6 memory endianness the processor views memory as a linear collec tion of bytes numbered in ascending order from zero. for example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. or ?little-endian format? describes how words of data are stored in memory. 10.5.6.1 little-endian format in little-endian format, the processor stores the least significant byte of a word at the lowest- numbered byte, and the most significant byte at the highest-numbered byte. for example: 10.5.7 synchronization primitives the cortex-m3 instruction set includes pairs of synchronization primitives . these provide a non- blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. software can use them to perform a guaranteed read-modify-write memory update sequence, or for a semaphore mechanism. a pair of synchronization primitives comprises: 10.5.7.1 a load-exclusive instruction used to read the value of a memory location, requesting exclusive access to that location. 10.5.7.2 a store-exclusive instruction used to attempt to write to the same memory location, returning a status bit to a register. if this bit is: 0: it indicates that the thread or process gained exclusive access to the memory, and the write succeeds, 1: it indicates that the thread or process did not gain exclusive access to the memory, and no write is performed, the pairs of load-exclusive and store-exclusive instructions are: ? the word instructions ldrex and strex memory register address a a+1 lsbyte msbyte a+2 a+3 0 7 b0 b1 b3 b2 31 24 23 16 15 8 7 0 b0 b1 b2 b3
62 11011a?atarm?04-oct-10 sam3n ? the halfword instructions ldrexh and strexh ? the byte instructions ldrexb and strexb. software must use a load-exclusive instruction with the corresponding store-exclusive instruction. to perform a guaranteed read-modify-write of a memory location, software must: ? use a load-exclusive instruction to read the value of the location. ? update the value, as required. ? use a store-exclusive instruction to attempt to write the new value back to the memory location, and tests the returned status bit. if this bit is: 0: the read-modify-write completed successfully, 1: no write was performed. this indicates that the value returned the first step might be out of date. the software must retry the read-modify-write sequence, software can use the synchronization primitiv es to implement a semaphores as follows: ? use a load-exclusive instruction to read from the semaphore address to check whether the semaphore is free. ? if the semaphore is free, use a store-exclusive to write the claim value to the semaphore address. ? if the returned status bit from the second st ep indicates that the store-exclusive succeeded then the software has claimed the semaphore. however, if the store-exclusive failed, another process might have claimed the semaphore after the software performed the first step. the cortex-m3 includes an exclusive access monitor, that tags the fact that the processor has executed a load-exclusive instruction. if the proc essor is part of a multiprocessor system, the system also globally tags the memory loca tions addressed by exclusive accesses by each processor. the processor removes its exclusive access tag if: ? it executes a clrex instruction ? it executes a store-exclusive instruction, regardless of whether the write succeeds. ? an exception occurs. this means the processor can resolve semaphore conflicts between different threads. in a multiprocessor implementation: ? executing a clrex instruction removes only the local exclusive access tag for the processor ? executing a store-exclusive instruction, or an exception. removes the local exclusive access tags, and all global exclusive access tags for the processor. for more information about the synchronization primitive instructions, see ?ldrex and strex? on page 100 and ?clrex? on page 102 .
63 11011a?atarm?04-oct-10 sam3n 10.5.8 programming hints for the synchronization primitives ansi c cannot directly generate the exclusive ac cess instructions. some c compilers provide intrinsic functions for generation of these instructions: the actual exclusive access instruction g enerated depends on the data type of the pointer passed to the intrinsic function. for example, the following c code generates the require ldrexb operation: __ldrex((volatile char *) 0xff); 10.6 exception model this section describes the exception model. 10.6.1 exception states each exception is in one of the following states: 10.6.1.1 inactive the exception is not active and not pending. 10.6.1.2 pending the exception is waiting to be serviced by the processor. an interrupt request from a peripheral or from software can change the state of the correspond- ing interrupt to pending. 10.6.1.3 active an exception that is being serviced by the processor but has not completed. an exception handler can interrupt the execution of another exception handler. in this case both exceptions are in the active state. 10.6.1.4 active and pending the exception is being serviced by the processor and there is a pending exception from the same source. 10.6.2 exception types the exception types are: 10.6.2.1 reset reset is invoked on power up or a warm reset. the exception model treats reset as a special form of exception. when reset is asserted, t he operation of the processor stops, potentially at any point in an instruction. when reset is deasserted, execution restarts from the address pro- table 10-8. c compiler intrinsic functions fo r exclusive access instructions instruction intrinsic function ldrex , ldrexh , or ldrexb unsigned int __ldrex(volatile void *ptr) strex , strexh , or strexb int __strex(unsigned int val, volatile void *ptr) clrex void __clrex(void)
64 11011a?atarm?04-oct-10 sam3n vided by the reset entry in the vector table. ex ecution restarts as privileged execution in thread mode. 10.6.2.2 non maskable interrupt (nmi) a non maskable interrupt (nmi) can be signalled by a peripheral or triggered by software. this is the highest priority exception other than reset. it is permanently enabled and has a fixed priority of -2. nmis cannot be: ? masked or prevented from activation by any other exception. ? preempted by any exception other than reset. 10.6.2.3 hard fault a hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. hard faults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. 10.6.2.4 bus fault a bus fault is an exception that occurs because of a memory related fault for an instruction or data memory transaction. this might be from an error detected on a bus in the memory system. 10.6.2.5 usage fault a usage fault is an exception that occurs because of a fault related to instruction execution. this includes: ? an undefined instruction ? an illegal unaligned access ? invalid state on instruction execution ? an error on exception return. the following can cause a usage fault when the core is configured to report them: ? an unaligned address on word and halfword memory access ? division by zero. 10.6.2.6 svcall a supervisor call (svc) is an exception that is triggered by the svc instruction. in an os envi- ronment, applications can use svc instructions to access os kernel functions and device drivers. 10.6.2.7 pendsv pendsv is an interrupt-driven request for system-level service. in an os environment, use pendsv for context switching when no other exception is active. 10.6.2.8 systick a systick exception is an exception the system timer generates when it reaches zero. software can also generate a systick exception. in an os environment, the processor can use this exception as system tick.
65 11011a?atarm?04-oct-10 sam3n 10.6.2.9 interrupt (irq) a interrupt, or irq, is an exception signalled by a peripheral, or generated by a software request. all interrupts are asynchronous to instruction execution. in the system, peripherals use interrupts to communicate with the processor. for an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. privileged software can disable the exceptions that table 10-9 on page 65 shows as having con- figurable priority, see: ? ?system handler control and state register? on page 179 table 10-9. properties of the different exception types exception number (1) 1. to simplify the software layer, the cmsis only uses irq numbers and therefore uses negative values for exceptions other than interrupts. the ipsr returns the exception number, see ?interrupt program status register? on page 48 . irq number ( 1) exception type priority vector address or offset (2) 2. see ?vector table? on page 67 for more information. activation 1 - reset -3, the highest 0x00000004 asynchronous 2 -14 nmi -2 0x00000008 asynchronous 3 -13 hard fault -1 0x0000000c - 4 -12 memory management fault configurable (3) 3. see ?system handler priority registers? on page 176 . 0x00000010 synchronous 5-11bus fault configurable (3) 0x00000014 synchronous when precise, asynchronous when imprecise 6 -10 usage fault configurable (3) 0x00000018 synchronous 7-10 - - - reserved - 11 -5 svcall configurable (3) 0x0000002c synchronous 12-13 - - - reserved - 14 -2 pendsv configurable (3) 0x00000038 asynchronous 15 -1 systick configurable (3) 0x0000003c asynchronous 16 and above 0 and above (4) 4. see the ?peripheral identifier s? section of the datasheet. interrupt (irq) configurable (5) 5. see ?interrupt priority registers? on page 158 . 0x00000040 and above (6) 6. increasing in steps of 4. asynchronous
66 11011a?atarm?04-oct-10 sam3n ? ?interrupt clear-enable registers? on page 154 . for more information about hard faults, memory management faults, bus faults, and usage faults, see ?fault handling? on page 70 . 10.6.3 exception handlers the processor handles exceptions using: 10.6.3.1 interrupt service routines (isrs) interrupts irq0 to irq32 are the exceptions handled by isrs. 10.6.3.2 fault handlers hard fault, memory management fault, usage fault, bus fault are fault exceptions handled by the fault handlers. 10.6.3.3 system handlers nmi, pendsv, svcall systick, and the fault exceptions are all system exceptions that are han- dled by system handlers. 10.6.4 vector table the vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. figure 10-3 on page 67 shows the order of the exception vectors in the vector table. the least-significant bit of each vector must be 1, indi- cating that the exception handler is thumb code.
67 11011a?atarm?04-oct-10 sam3n figure 10-3. vector table on system reset, the vector table is fixed at address 0x00000000 . privileged software can write to the vtor to relocate the vector table start address to a different memory location, in the range 0x00000080 to 0x3fffff80 , see ?vector table offset register? on page 170 . 10.6.5 exception priorities as table 10-9 on page 65 shows, all exceptions have an associated priority, with: ? a lower priority value indicating a higher priority ? configurable priorities for all exce ptions except reset, hard fault. if software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. for information about configuring exception priorities see ? ?system handler priority registers? on page 176 ? ?interrupt priority registers? on page 158 . initial sp value reset hard fault reserved memory management fault usage fault bus fault 0x0000 0x0004 0x0008 0x000c 0x0010 0x0014 0x0018 reserved svcall pendsv reserved for debug systick irq0 reserved 0x002c 0x0038 0x003c 0x0040 offset exception number 2 3 4 5 6 11 12 14 15 16 18 13 7 10 1 vector . . . 8 9 irq1 irq2 0x0044 irq29 17 0x0048 0x004c 45 . . . . . . 0x00b4 irq number -14 -13 -12 -11 -10 -5 -2 -1 0 2 1 29
68 11011a?atarm?04-oct-10 sam3n configurable priority values are in the range 0-15. this means that the reset, hard fault, and nmi exceptions, with fixed negative priority va lues, always have higher priority than any other exception. for example, assigning a higher priority value to irq[0] and a lower priority value to irq[1] means that irq[1] has higher priority than irq[0]. if both irq[1] and irq[0] are asserted, irq[1] is processed before irq[0]. if multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. for exampl e, if both irq[0] and irq[1] are pending and have the same priority, then irq[0] is processed before irq[1]. when the processor is executing an exception handl er, the exception handler is preempted if a higher priority exception occurs. if an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. however, the status of the new interrupt changes to pending. 10.6.6 interrupt priority grouping to increase priority control in systems with interrupts, the nvic supports priority grouping. this divides each interrupt priority register entry into two fields: ? an upper field that defines the group priority ? a lower field that defines a subpriority within the group. only the group priority determines preemption of interrupt exceptions. when the processor is executing an interrupt exception handler, another in terrupt with the same group priority as the interrupt being handled does not preempt the handler, if multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. if multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest irq number is processed first. for information about splitting the interrupt priority fields into group priority and subpriority, see ?application interrupt and reset control register? on page 171 . 10.6.7 exception entry and return descriptions of exception handling use the following terms: 10.6.7.1 preemption when the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. see ?interrupt pri- ority grouping? on page 68 for more information about preemption by an interrupt. when one exception preempts another, the exceptions are called nested exceptions. see ?exception entry? on page 69 more information. 10.6.7.2 return this occurs when the exception handler is completed, and: ? there is no pending exception with sufficient priority to be serviced ? the completed exception handler was not handling a late-arriving exception. the processor pops the stack and restores the processor state to the state it had before the interrupt occurred. see ?exception return? on page 70 for more information.
69 11011a?atarm?04-oct-10 sam3n 10.6.7.3 tail-chaining this mechanism speeds up exception servicing. on completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. 10.6.7.4 late-arriving this mechanism speeds up preemption. if a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initi- ates the vector fetch for that exception. state saving is not affected by late arrival because the state saved is the same for both exceptions. therefore the state saving continues uninterrupted. the processor can accept a late arriving exception until the first instruction of the exception han- dler of the original exception enters the execute stage of the processor. on return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. 10.6.7.5 exception entry exception entry occurs when there is a pending exception with sufficient priority and either: ? the processor is in thread mode ? the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception. when one exception preempts another, the exceptions are nested. sufficient priority means the exception has more priority than any limits set by the mask regis- ters, see ?exception mask registers? on page 49 . an exception with less priority than this is pending but is not handl ed by the processor. when the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. this operation is referred as stacking and the structure of eight data words is referred as stack frame . the stack frame con- tains the followi ng information: ?r0-r3, r12 ? return address ? psr ?lr. immediately after stacking, the stack pointer indicates the lowest address in the stack frame. unless stack alignment is disabled, the stack frame is aligned to a double-word address. if the stkalign bit of the configuration co ntrol register (ccr) is set to 1, st ack align adjustment is performed during stacking. the stack frame includes the return address. this is the address of the next instruction in the interrupted program. this value is restored to the pc at exception return so that the interrupted program resumes. in parallel to the stacking operation, the processor performs a vector fetch that reads the excep- tion handler start address from the vector table. when stacking is complete, the processor starts executing the exception handler. at the same time, the processor writes an exc_return value to the lr. this indicates which stack pointer corresponds to the stack frame and what operation mode the was processor was in before the entry occurred.
70 11011a?atarm?04-oct-10 sam3n if no higher priority exception o ccurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. if another higher priority exception occurs during exception entry, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. this is t he late arrival case. 10.6.7.6 exception return exception return occurs when the processor is in handler mode and executes one of the follow- ing instructions to load the exc_return value into the pc: ?a pop instruction that includes the pc ?a bx instruction with any register. ?an ldr or ldm instruction with the pc as the destination. exc_return is the value loaded into the lr on exception entry. the exception mechanism relies on this value to detect when the processor has completed an exception handler. the low- est four bits of this value provide information on the return stack and processor mode. table 10- 10 shows the exc_return[3:0] values with a description of the exception return behavior. the processor sets exc_return bits[31:4] to 0xfffffff . when this value is loaded into the pc it indicates to the processor that the except ion is complete, and the processor initiates the exception return sequence. 10.7 fault handling faults are a subset of the exceptions, see ?exception model? on page 63 . the following gener- ate a fault: ? a bus error on: ? an instruction fetch or vector table load ? a data access table 10-10. exception return behavior exc_return[3:0] description bxxx0 reserved. b0001 return to handler mode. exception return gets state from msp. execution uses msp after return. b0011 reserved. b01x1 reserved. b1001 return to thread mode. exception return gets state from msp. execution uses msp after return. b1101 return to thread mode. exception return gets state from psp. execution uses psp after return. b1x11 reserved.
71 11011a?atarm?04-oct-10 sam3n ? an internally-detected error such as an undefined instruction or an attempt to change state with a bx instruction ? attempting to execute an instruction from a memory region marked as non-executable (xn) . 10.7.1 fault types table 10-11 shows the types of fault, the handler used for the fault, the corresponding fault sta- tus register, and the register bit that indicates that the fault has occurred. see ?configurable fault status register? on page 181 for more information about the fault status registers. 10.7.2 fault escalation and hard faults all faults exceptions except for hard fault have configurable exception priority, see ?system han- dler priority registers? on page 176 . software can disable execution of the handlers for these faults, see ?system handler control and state register? on page 179 . usually, the exception priority, together with the values of the exception mask registers, deter- mines whether the processor enters the fault han dler, and whether a fault handler can preempt another fault handler. as described in ?exception model? on page 63 . in some situations, a fault with configurable prio rity is treated as a hard fault. this is called prior- ity escalation , and the fault is described as escalated to hard fault . escalation to hard fault occurs when: ? a fault handler causes the same kind of fault as the one it is servicing. this escalation to hard fault occurs because a fault handler cannot preempt itself because it must have the same priority as the current priority level. table 10-11. faults fault handler bit name fault status register bus error on a vector read hard fault vecttbl ?hard fault status register? on page 187 fault escalated to a hard fault forced bus error: bus fault -- during exception stacking stkerr ?bus fault status register? on page 183 during exception unstacking unstkerr during instruction prefetch ibuserr precise data bus error preciserr imprecise data bus error impreciser r attempt to access a coprocessor usage fault nocp ?usage fault status register? on page 185 undefined instruction undefinstr attempt to enter an invalid instruction set state (1) 1. attempting to use an instruction set other than the thumb instruction set. invstate invalid exc_return value invpc illegal unaligned load or store unaligned divide by 0 divbyzero
72 11011a?atarm?04-oct-10 sam3n ? a fault handler causes a fault with the same or lowe r priority as the fault it is servicing. this is because the handler for the new fault cannot preempt the currently executing fault handler. ? an exception handler causes a fault for which t he priority is the same as or lower than the currently executing exception. ? a fault occurs and the handler for that fault is not enabled. if a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. this means that if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. the fault handler operates but the stack contents are corrupted. only reset and nmi can preempt the fixed priority hard fault. a hard fault can preempt any exception other than reset, nmi, or another hard fault. 10.7.3 fault status registers and fault address registers the fault status registers indicate the cause of a fault. for bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in table 10-12 . 10.7.4 lockup the processor enters a lockup state if a hard fault occurs when executing the hard fault han- dlers. when the processor is in lockup state it does not execute any instructions. the processor remains in lockup state until: ? it is reset 10.8 power management the cortex-m3 processor sleep modes reduce power consumption: ? backup mode ?wait mode ? sleep mode table 10-12. fault status and fault address registers handler status register name address register name register description hard fault hfsr - ?hard fault status register? on page 187 memory management fault mmfsr mmfar ?memory management fault status register? on page 182 ?memory management fault address register? on page 188 bus fault bfsr bfar ?bus fault status register? on page 183 ?bus fault address register? on page 189 usage fault ufsr - ?usage fault status register? on page 185
73 11011a?atarm?04-oct-10 sam3n the sleepdeep bit of the scr select s which sleep mode is used, see ?system control regis- ter? on page 173 . for more information about the behavior of the sleep modes see ?low power modes? in the pmc section of the datasheet. this section describes the mechanisms for ent ering sleep mode, and the conditions for waking up from sleep mode. 10.8.1 entering sleep mode this section describes the mechanisms software can use to put the processor into sleep mode. the system can generate spurious wakeup events, for example a debug operation wakes up the processor. therefore software must be able to put the processor back into sleep mode after such an event. a program might have an idle loop to put the processor back to sleep mode. 10.8.1.1 wait for interrupt the wait for interrupt instruction, wfi, causes immediate entry to sleep mode. when the proces- sor executes a wfi instruction it stops execut ing instructions and enters sleep mode. see ?wfi? on page 149 for more information. 10.8.1.2 wait for event the wait for event instruction, wfe, causes entry to sleep mode conditional on the value of an one-bit event register. when the processor executes a wfe instruction, it checks this register: ? if the register is 0 the processor stops executing instructions and enters sleep mode ? if the register is 1 the processor clears the register to 0 and continues executing instructions without entering sleep mode. see ?wfe? on page 148 for more information. 10.8.1.3 sleep-on-exit if the sleeponexit bit of the s cr is set to 1, when the proc essor completes the execution of an exception handler it returns to thread mode and immediately enters sleep mode. use this mechanism in applications that only require the processor to run when an exception occurs. 10.8.2 wakeup from sleep mode the conditions for the processor to wakeup depend on the mechanism that cause it to enter sleep mode. 10.8.2.1 wakeup from wfi or sleep-on-exit normally, the processor wakes up only when it det ects an exception with sufficient priority to cause exception entry. some embedded systems might have to execute system restore tasks after the processor wakes up, and before it executes an interrupt handler. to achiev e this set the primask bit to 1 and the faultmask bit to 0. if an interrupt arrives that is enabl ed and has a higher priority than current exception priority, the processor wakes up but does not execute the interrupt handler until the processor sets primask to zero. fo r more information about primask and fault- mask see ?exception mask registers? on page 49 . 10.8.2.2 wakeup from wfe the processor wakes up if: ? it detects an exception with sufficient priority to cause exception entry
74 11011a?atarm?04-oct-10 sam3n in addition, if the sevonpend bit in the scr is set to 1, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. for more information about the scr see ?system control register? on page 173 . 10.8.3 power management programming hints ansi c cannot directly generate the wfi and wfe instructions. the cmsis provides the follow- ing intrinsic functions for these instructions: void __wfe(void) // wait for event void __wfe(void) // wait for interrupt
75 11011a?atarm?04-oct-10 sam3n 10.9 instruction set summary the processor implements a version of the thumb instruction set. table 10-13 lists the sup- ported instructions. in table 10-13 : ? angle brackets, <>, enclose alternative forms of the operand ? braces, {}, enclose optional operands ? the operands column is not exhaustive ? op2 is a flexible second operand that can be either a register or a constant ? most instructions can use an optional condition code suffix. for more information on the instructions and operands, see the instruction descriptions. table 10-13. cortex-m3 instructions mnemonic operands brief description flags page adc, adcs {rd,} rn, op2 add with carry n,z,c,v page 105 add, adds {rd,} rn, op2 add n,z,c,v page 105 add, addw {rd,} rn, #imm12 add n,z,c,v page 105 adr rd, label load pc-relative address - page 88 and, ands {rd,} rn, op2 logical and n,z,c page 108 asr, asrs rd, rm, arithmetic shift right n,z,c page 110 b label branch - page 130 bfc rd, #lsb, #width bit field clear - page 126 bfi rd, rn, #lsb, #width bit field insert - page 126 bic, bics {rd,} rn, op2 bit clear n,z,c page 108 bkpt #imm breakpoint - page 138 bl label branch with link - page 130 blx rm branch indirect with link - page 130 bx rm branch indirect - page 130 cbnz rn, label compare and branch if non zero - page 132 cbz rn, label compare and branch if zero - page 132 clrex - clear exclusive - page 102 clz rd, rm count leading zeros - page 112 cmn, cmns rn, op2 compare negative n,z,c,v page 113 cmp, cmps rn, op2 compare n,z,c,v page 113 cpsid iflags change processor state, disable interrupts - page 139 cpsie iflags change processor state, enable interrupts - page 139 dmb - data memory barrier - page 140 dsb - data synchronization barrier - page 141 eor, eors {rd,} rn, op2 exclusive or n,z,c page 108
76 11011a?atarm?04-oct-10 sam3n isb - instruction synchronization barrier - page 142 it - if-then condition block - page 133 ldm rn{!}, reglist load multiple registers, increment after - page 97 ldmdb, ldmea rn{!}, reglist load multiple registers, decrement before - page 97 ldmfd, ldmia rn{!}, reglist load multiple registers, increment after - page 97 ldr rt, [rn, #offset] load register with word - page 92 ldrb, ldrbt rt, [rn, #offset] load register with byte - page 92 ldrd rt, rt2, [rn, #offset] load register with two bytes - page 92 ldrex rt, [rn, #offset] load register exclusive - page 92 ldrexb rt, [rn] load register exclusive with byte - page 92 ldrexh rt, [rn] load register exclusive with halfword - page 92 ldrh, ldrht rt, [rn, #offset] load register with halfword - page 92 ldrsb, ldrsbt rt, [rn, #offset] load register with signed byte - page 92 ldrsh, ldrsht rt, [rn, #offset] load register with signed halfword - page 92 ldrt rt, [rn, #offset] load register with word - page 92 lsl, lsls rd, rm, logical shift left n,z,c page 110 lsr, lsrs rd, rm, logical shift right n,z,c page 110 mla rd, rn, rm, ra multiply with accumulate, 32-bit result - page 120 mls rd, rn, rm, ra multiply and subtract, 32-bit result - page 120 mov, movs rd, op2 move n,z,c page 114 movt rd, #imm16 move top - page 116 movw, mov rd, #imm16 move 16-bit constant n,z,c page 114 mrs rd, spec_reg move from special register to general register - page 143 msr spec_reg, rm move from general register to special register n,z,c,v page 144 mul, muls {rd,} rn, rm multiply, 32-bit result n,z page 120 mvn, mvns rd, op2 move not n,z,c page 114 nop - no operation - page 145 orn, orns {rd,} rn, op2 logical or not n,z,c page 108 orr, orrs {rd,} rn, op2 logical or n,z,c page 108 pop reglist pop registers from stack - page 99 push reglist push registers onto stack - page 99 table 10-13. cortex-m3 instructions (continued) mnemonic operands brief description flags page
77 11011a?atarm?04-oct-10 sam3n rbit rd, rn reverse bits - page 117 rev rd, rn reverse byte order in a word - page 117 rev16 rd, rn reverse byte order in each halfword - page 117 revsh rd, rn reverse byte order in bottom halfword and sign extend - page 117 ror, rors rd, rm, rotate right n,z,c page 110 rrx, rrxs rd, rm rotate right with extend n,z,c page 110 rsb, rsbs {rd,} rn, op2 reverse subtract n,z,c,v page 105 sbc, sbcs {rd,} rn, op2 subtract with carry n,z,c,v page 105 sbfx rd, rn, #lsb, #width signed bit field extract - page 127 sdiv {rd,} rn, rm signed divide - page 122 sev - send event - page 146 smlal rdlo, rdhi, rn, rm signed multiply with accumulate (32 x 32 + 64), 64-bit result - page 121 smull rdlo, rdhi, rn, rm signed multiply (32 x 32), 64-bit result - page 121 ssat rd, #n, rm {,shift #s} signed saturate q page 123 stm rn{!}, reglist store multiple registers, increment after - page 97 stmdb, stmea rn{!}, reglist store multiple registers, decrement before - page 97 stmfd, stmia rn{!}, reglist store multiple registers, increment after - page 97 str rt, [rn, #offset] store register word - page 92 strb, strbt rt, [rn, #offset] sto re register byte - page 92 strd rt, rt2, [rn, #offset] store register two words - page 92 strex rd, rt, [rn, #offset] s tore register exclusive - page 100 strexb rd, rt, [rn] store register exclusive byte - page 100 strexh rd, rt, [rn] store register exclusive halfword - page 100 strh, strht rt, [rn, #offset] store register halfword - page 92 strt rt, [rn, #offset] s tore register word - page 92 sub, subs {rd,} rn, op2 subtract n,z,c,v page 105 sub, subw {rd,} rn, #imm12 subtract n,z,c,v page 105 svc #imm supervisor call - page 147 sxtb {rd,} rm {,ror #n} sign extend a byte - page 128 sxth {rd,} rm {,ror #n} sign extend a halfword - page 128 tbb [rn, rm] table branch byte - page 135 tbh [rn, rm, lsl #1] table branch halfword - page 135 table 10-13. cortex-m3 instructions (continued) mnemonic operands brief description flags page
78 11011a?atarm?04-oct-10 sam3n 10.10 intrinsic functions ansi cannot directly access some cortex-m3 instructions. this se ction describes intrinsic func- tions that can generate these instructions, provid ed by the cmis and that might be provided by a c compiler. if a c compiler does not support an appropriate intrinsic function, you might have to use inline assembler to ac cess some instructions. the cmsis provides the following intrinsic functions to generate instructions that ansi cannot directly access: teq rn, op2 test equivalence n,z,c page 118 tst rn, op2 test n,z,c page 118 ubfx rd, rn, #lsb, #width unsigned bit field extract - page 127 udiv {rd,} rn, rm unsigned divide - page 122 umlal rdlo, rdhi, rn, rm unsigned multiply with accumulate (32 x 32 + 64), 64-bit result - page 121 umull rdlo, rdhi, rn, rm unsigned multiply (32 x 32), 64-bit result - page 121 usat rd, #n, rm {,shift #s} unsigned saturate q page 123 uxtb {rd,} rm {,ror #n} zero extend a byte - page 128 uxth {rd,} rm {,ror #n} zero extend a halfword - page 128 wfe - wait for event - page 148 wfi - wait for interrupt - page 149 table 10-13. cortex-m3 instructions (continued) mnemonic operands brief description flags page table 10-14. cmsis intrinsic functions to generate some cortex-m3 instructions instruction cmsis intrinsic function cpsie i void __enable_irq(void) cpsid i void __disable_irq(void) cpsie f void __enable_fault_irq(void) cpsid f void __disable_fault_irq(void) isb void __isb(void) dsb void __dsb(void) dmb void __dmb(void) rev uint32_t __rev(uint32_t int value) rev16 uint32_t __rev16(uint32_t int value) revsh uint32_t __revsh(uint32_t int value) rbit uint32_t __rbit(uint32_t int value) sev void __sev(void) wfe void __wfe(void) wfi void __wfi(void)
79 11011a?atarm?04-oct-10 sam3n the cmsis also provides a number of functions for accessing the special registers using mrs and msr instructions: 10.11 about the inst ruction descriptions the following sections give more info rmation about using the instructions: ? ?operands? on page 79 ? ?restrictions when using pc or sp? on page 79 ? ?flexible second operand? on page 80 ? ?shift operations? on page 81 ? ?address alignment? on page 83 ? ?pc-relative expressions? on page 84 ? ?conditional execution? on page 84 ? ?instruction width selection? on page 86 . 10.11.1 operands an instruction operand can be an arm register, a constant, or another instruction-specific parameter. instructions act on the operands and often store the result in a destination register. when there is a destination register in the instruction, it is usually specified before the operands. operands in some instructions are flexible in that they can either be a register or a constant. see ?flexible second operand? . 10.11.2 restrictions when using pc or sp many instructions have restrictions on whether you can use the program counter (pc) or stack pointer (sp) for the operands or destination register. see instruction descriptions for more information. table 10-15. cmsis intrinsic functions to access the special registers special register access cmsis function primask read uint32_t __get_primask (void) write void __set_primask (uint32_t value) faultmask read uint32_t __get_faultmask (void) write void __set_faultmask (uint32_t value) basepri read uint32_t __get_basepri (void) write void __set_basepr i (uint32_t value) control read uint32_t __get_control (void) write void __set_control (uint32_t value) msp read uint32_t __get_msp (void) write void __set_msp (uint32_t topofmainstack) psp read uint32_t __get_psp (void) write void __set_psp (uint32_t topofprocstack)
80 11011a?atarm?04-oct-10 sam3n bit[0] of any address you write to the pc with a bx, blx, ldm, ldr, or pop instruction must be 1 for correct execution, because this bit indicates the required instruction set, and the cortex-m3 processor only supports thumb instructions. 10.11.3 flexible second operand many general data processing in structions have a flexible se cond operand. this is shown as operand2 in the descriptions of the syntax of each instruction. operand2 can be a: ? ?constant? ? ?register with optional shift? on page 80 10.11.3.1 constant you specify an operand2 constant in the form: # constant where constant can be: ? any constant that can be produced by shifting an 8-bit value left by any number of bits within a 32-bit word ? any constant of the form 0x00xy00xy ? any constant of the form 0xxy00xy00 ? any constant of the form 0xxyxyxyxy. in the constants shown above, x and y are hexadecimal digits. in addition, in a small number of instructions, constant can take a wider range of values. these are described in the individual instruction descriptions. when an operand2 constant is used with the instructions movs, mvns, ands, orrs, orns, eors, bics, teq or tst, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be produced by shifting an 8-bit value. these instructions do not affect the carry flag if operand2 is any other constant. 10.11.3.2 instruction substitution your assembler might be able to produce an equivalent instruction in cases where you specify a constant that is not permitted. for example, an assembler might assemble the instruction cmp rd , #0xfffffffe as the equivalent instruction cmn rd , #0x2. 10.11.3.3 register with optional shift you specify an operand2 register in the form: rm {, shift } where: rm is the register holding the data for the second operand. shift is an optional shift to be applied to rm . it can be one of: asr # n arithmetic shift right n bits, 1 n 32. lsl # n logical shift left n bits, 1 n 31.
81 11011a?atarm?04-oct-10 sam3n lsr # n logical shift right n bits, 1 n 32. ror # n rotate right n bits, 1 n 31. rrx rotate right one bit, with extend. - if omitted, no shift occurs, equivalent to lsl #0. if you omit the shift, or specify lsl #0, the instruction uses the value in rm . if you specify a shift, the shif t is applied to the value in rm , and the resulting 32-bit value is used by the instruction. however, the contents in the register rm remains unchanged. specifying a register with shift also updates the carry flag when used with certain instructions. for information on the shift operations and how they affect the carry flag, see ?shift operations? 10.11.4 shift operations register shift operations move the bits in a register left or right by a specified number of bits, the shift length . register shift can be performed: ? directly by the instructions asr, lsr, lsl, ro r, and rrx, and the result is written to a destination register ? during the calculation of operand2 by the instructions that specify the second operand as a register with shift, see ?flexible second operand? on page 80 . the result is used by the instruction. the permitted shift lengths depend on the shift type and the instruction, see the individual instruction description or ?flexible second operand? on page 80 . if the shift length is 0, no shift occurs. register shift operations update the carry fl ag except when the specified shift length is 0. the following sub-sections describe the various shift operations and how they affect the carry flag. in these descriptions, rm is the register containing the value to be shifted, and n is the shift length. 10.11.4.1 asr arithmetic shift right by n bits moves the left-hand 32-n bits of the register rm , to the right by n places, into the right-hand 32-n bits of the result. and it copies the original bit[31] of the register into the left-hand n bits of the result. see figure 10-4 on page 81 . you can use the asr #n operation to divide the value in the register rm by 2 n , with the result being rounded towards negative-infinity. when the instruction is asrs or when asr #n is used in operand2 with the instructions movs, mvns, ands, orrs, orns, eors, bics, teq or tst, the carry flag is updated to the last bit shifted out, bit[ n -1], of the register rm . ?if n is 32 or more, then all the bits in the result are set to the value of bit[31] of rm . ?if n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of rm . figure 10-4. asr #3 31 10 carry flag ... 2 3 4 5
82 11011a?atarm?04-oct-10 sam3n 10.11.4.2 lsr logical shift right by n bits moves the left-hand 32-n bits of the register rm, to the right by n places, into the right-hand 32-n bits of the result. and it sets the left-hand n bits of the result to 0. see figure 10-5 . you can use the lsr #n operation to divide the value in the register rm by 2 n , if the value is regarded as an unsigned integer. when the instruction is lsrs or when lsr #n is used in operand2 with the instructions movs, mvns, ands, orrs, orns, eors, bics, teq or tst, the carry flag is updated to the last bit shifted out, bit[n-1], of the register rm. ?if n is 32 or more, then all the bits in the result are cleared to 0. ?if n is 33 or more and the carry flag is updated, it is updated to 0. figure 10-5. lsr #3 10.11.4.3 lsl logical shift left by n bits moves the right-hand 32-n bits of the register rm, to the left by n places, into the left-hand 32-n bits of the result. and it sets the right-hand n bits of the result to 0. see figure 10-6 on page 82 . you can use he lsl #n operation to multiply the value in the register rm by 2 n , if the value is regarded as an unsigned integer or a two?s comp lement signed integer. overflow can occur without warning. when the instruction is lsls or when lsl #n, with non-zero n , is used in operand2 with the instructions movs, mvns, ands, orrs, orns, eors, bics, teq or tst, the carry flag is updated to the last bit shifted out, bit[32- n ], of the register rm . these instructions do not affect the carry flag when used with lsl #0. ?if n is 32 or more, then all the bits in the result are cleared to 0. ?if n is 33 or more and the carry flag is updated, it is updated to 0. figure 10-6. lsl #3 31 10 carry flag ... 0 0 0 2 3 4 5 31 10 carry flag ... 0 0 0 2 3 4 5
83 11011a?atarm?04-oct-10 sam3n 10.11.4.4 ror rotate right by n bits moves the left-hand 32- n bits of the register rm , to the right by n places, into the right-hand 32- n bits of the result. and it moves the right-hand n bits of the register into the left-hand n bits of the result. see figure 10-7 . when the instruction is rors or when ror # n is used in operand2 with the instructions movs, mvns, ands, orrs, orns, eors, bics, teq or tst, the carry flag is updated to the last bit rotation, bit[ n -1], of the register rm . ?if n is 32, then the value of the result is same as the value in rm , and if the carry flag is updated, it is updated to bit[31] of rm . ? ror with shift length, n , more than 32 is the same as ror with shift length n -32. figure 10-7. ror #3 10.11.4.5 rrx rotate right with extend moves the bits of the register rm to the right by one bit. and it copies the carry flag into bit[31] of the result. see figure 10-8 on page 83 . when the instruction is rrxs or when rrx is used in operand2 with the instructions movs, mvns, ands, orrs, orns, eors, bics, teq or ts t, the carry flag is updated to bit[0] of the register rm . figure 10-8. rrx 10.11.5 address alignment an aligned access is an operation where a word-aligned address is used for a word, dual word, or multiple word access, or where a halfwor d-aligned address is used for a halfword access. byte accesses are always aligned. the cortex-m3 processor supports unaligned access only for the following instructions: ? ldr, ldrt ? ldrh, ldrht ? ldrsh, ldrsht ?str, strt ? strh, strht 31 10 carry flag ... 2 3 4 5 31 30 1 0 carry flag ... ...
84 11011a?atarm?04-oct-10 sam3n all other load and store instructions generate a usage fault exception if they perform an unaligned access, and therefore their accesses must be address aligned. for more information about usage faults see ?fault handling? on page 70 . unaligned accesses are usually slower than aligned accesses. in addition, some memory regions might not support unaligned accesses. therefore, arm recommends that programmers ensure that accesses are aligned. to avoid accidental generation of unaligned accesses, use the unalign_trp bit in the configuration and control register to trap all unaligned accesses, see ?configuration and control register? on page 174 . 10.11.6 pc-relative expressions a pc-relative expression or label is a symbol that represents the address of an instruction or lit- eral data. it is represented in the instruction as the pc value plus or minus a numeric offset. the assembler calculates the required offset from the label and the address of the current instruc- tion. if the offset is too big, the assembler produces an error. ? for b, bl, cbnz, and cbz instructions, the value of the pc is the address of the current instruction plus 4 bytes. ? for all other instructions that use labels, the value of the pc is the address of the current instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it word-aligned. ? your assembler might permit other syntaxes for pc-relative expressions, such as a label plus or minus a number, or an expression of the form [pc, #number]. 10.11.7 conditional execution most data processing instructions can opt ionally update the condition flags in the application program status register (apsr) according to the result of the operation, see ?application pro- gram status register? on page 47 . some instructions update all flags, and some only update a subset. if a flag is not updated, the original val ue is preserved. see the instruction descriptions for the flags they affect. you can execute an instruction conditionally, based on the condition flags set in another instruc- tion, either: ? immediately after the instruction that updated the flags ? after any number of intervening instructions that have not updated the flags. conditional execution is avail able by using conditional branc hes or by adding condition code suffixes to instructions. see table 10-16 on page 85 for a list of the suffixes to add to instructions to make them conditional instructions. the condition code suffix enables the processor to test a condition based on the flags. if the condition test of a conditional instruction fails, the instruction: ? does not execute ? does not write any value to its destination register ? does not affect any of the flags ? does not generate any exception. conditional instructions, except for conditional branches, must be inside an if-then instruction block. see ?it? on page 133 for more information and restrictions when using the it instruction. depending on the vendor, the assembler might automatically insert an it instruction if you have conditional instructions outside the it block. use the cbz and cbnz instructions to compare the value of a register against zero and branch on the result.
85 11011a?atarm?04-oct-10 sam3n this section describes: ? ?the condition flags? ? ?condition code suffixes? . 10.11.7.1 the condition flags the apsr contains the following condition flags: n set to 1 when the result of the operation was negative, cleared to 0 otherwise. z set to 1 when the result of the operation was zero, cleared to 0 otherwise. c set to 1 when the operation resulted in a carry, cleared to 0 otherwise. v set to 1 when the operation caused overflow, cleared to 0 otherwise. for more information about the apsr see ?program status register? on page 46 . a carry occurs: ? if the result of an addition is greater than or equal to 2 32 ? if the result of a subtraction is positive or zero ? as the result of an inline barrel shifter operation in a move or logical instruction. overflow occurs if the result of an add, subtract, or compare is greater than or equal to 2 31 , or less than ?2 31 . most instructions update the status flags only if the s suffix is specified. see the instruction descriptions for more information. 10.11.7.2 condition code suffixes the instructions that can be conditional have an optional condition code, shown in syntax descriptions as {cond}. conditional execution requires a preceding it instruction. an instruction with a condition code is only executed if the condi tion code flags in the apsr meet the specified condition. table 10-16 shows the condition codes to use. you can use conditional execution with the it instruction to reduce the number of branch instruc- tions in code. table 10-16 also shows the relationship between condition code suffixes and the n, z, c, and v flags. table 10-16. condition code suffixes suffix flags meaning eq z = 1 equal ne z = 0 not equal cs or hs c = 1 higher or same, unsigned cc or lo c = 0 lower, unsigned < mi n = 1 negative pl n = 0 positive or zero vs v = 1 overflow
86 11011a?atarm?04-oct-10 sam3n 10.11.7.3 absolute value the example below shows the use of a conditional instruction to find the absolute value of a number. r0 = abs(r1). movs r0, r1 ; r0 = r1, setting flags it mi ; it instruction for the negative condition rsbmi r0, r1, #0 ; if negative, r0 = -r1 10.11.7.4 compare and update value the example below shows the use of conditi onal instructions to update the value of r4 if the signed values r0 is greater than r1 and r2 is greater than r3. cmp r0, r1 ; compare r0 and r1, setting flags itt gt ; it instruction for the two gt conditions cmpgt r2, r3 ; if 'greater than', compare r2 and r3, setting flags movgt r4, r5 ; if still 'greater than', do r4 = r5 10.11.8 instruction width selection there are many instructions that can generate either a 16-bit encoding or a 32-bit encoding depending on the operands and destination register s pecified. for some of these instructions, you can force a specific instruction size by using an instruction width suffix. the .w suffix forces a 32-bit instruction encoding. the .n suffix forces a 16-bit instruction encoding. if you specify an instruction width suffix and the assembler cannot generate an instruction encoding of the requested width, it generates an error. in some cases it might be necessary to specify the .w suffix, for example if the operand is the label of an instruction or literal data, as in the case of branch instructions. this is because the assembler might not automatically generate the right size encoding. 10.11.8.1 instruction width selection to use an instruction width suffix, place it immediately after the instruction mnemonic and condition code, if any. the exam- ple below shows instructions wit h the instructio n width suffix. bcs.w label ; creates a 32-bit instruction even for a short branch adds.w r0, r0, r1 ; creates a 32-bit instruction even though the same ; operation can be done by a 16-bit instruction vc v = 0 no overflow hi c = 1 and z = 0 higher, unsigned > ls c = 0 or z = 1 lower or same, unsigned ge n = v greater than or equal, signed lt n ! = v less than, signed < gt z = 0 and n = v greater than, signed > le z = 1 and n != v less than or equal, signed al can have any value always. this is the default when no suffix is specified. table 10-16. condition code suffixes (continued) suffix flags meaning
87 11011a?atarm?04-oct-10 sam3n 10.12 memory acces s instructions table 10-17 shows the memory access instructions: table 10-17. memory access instructions mnemonic brief description see adr load pc-relative address ?adr? on page 88 clrex clear exclusive ?clrex? on page 102 ldm{mode} load multiple registers ?ldm and stm? on page 97 ldr{type} load register using immediate offset ?ldr and str, immediate offset? on page 89 ldr{type} load register using register offset ?ldr and str, register offset? on page 92 ldr{type}t load register with unprivileged access ?ldr and str, unprivileged? on page 94 ldr load register using pc-relative address ?ldr, pc-relative? on page 95 ldrex{type} load register exclusive ?ldrex and strex? on page 100 pop pop registers from stack ?push and pop? on page 99 push push registers onto stack ?push and pop? on page 99 stm{mode} store multiple registers ?ldm and stm? on page 97 str{type} store register using immediate offset ?ldr and str, immediate offset? on page 89 str{type} store register using register offset ?ldr and str, register offset? on page 92 str{type}t store register with unprivileged access ?ldr and str, unprivileged? on page 94 strex{type} store register exclusive ?ldrex and strex? on page 100
88 11011a?atarm?04-oct-10 sam3n 10.12.1 adr load pc-relative address. 10.12.1.1 syntax adr{ cond } rd , label where: cond is an optional condition code, see ?conditional execution? on page 84 . rd is the destination register. label is a pc-relative expression. see ?pc-relative expressions? on page 84 . 10.12.1.2 operation adr determines the address by adding an immediate value to the pc, and writes the result to the destination register. adr produces position-independent code , because the address is pc-relative. if you use adr to generate a target address for a bx or blx instruction, you must ensure that bit[0] of the address you generate is set to1 for correct execution. values of label must be within the range of ? 4095 to +4095 from the address in the pc. you might have to use the .w suffix to get the maximum offset range or to generate addresses that are not word-aligned. see ?instruction width selection? on page 86 . 10.12.1.3 restrictions rd must not be sp and must not be pc. 10.12.1.4 condition flags this instruction does not change the flags. 10.12.1.5 examples adr r1, textmessage ; write address value of a location labelled as ; textmessage to r1
89 11011a?atarm?04-oct-10 sam3n 10.12.2 ldr and str, immediate offset load and store with immediate offset, pre-index ed immediate offset, or post-indexed immediate offset. 10.12.2.1 syntax op { type }{ cond } rt , [ rn {, # offset }] ; immediate offset op { type }{ cond } rt , [ rn , # offset ]! ; pre-indexed op { type }{ cond } rt , [ rn ], # offset ; post-indexed op d{ cond } rt , rt2 , [ rn {, # offset }] ; immediate offset, two words op d{ cond } rt , rt2 , [ rn , # offset ]! ; pre-indexed, two words op d{ cond } rt , rt2 , [ rn ], # offset ; post-indexed, two words where: op is one of: ldr load register. str store register. type is one of: b unsigned byte, zero extend to 32 bits on loads. sb signed byte, sign extend to 32 bits (ldr only). h unsigned halfword, zero extend to 32 bits on loads. sh signed halfword, sign extend to 32 bits (ldr only). - omit, for word. cond is an optional condition code, see ?conditional execution? on page 84 . rt is the register to load or store. rn is the register on which the memory address is based. offset is an offset from rn . if offset is omitted, the address is the contents of rn . rt2 is the additional register to load or store for two-word operations. 10.12.2.2 operation ldr instructions load one or two registers with a value from memory. str instructions store one or two register values to memory. load and store instructions with immediate offset can use the following addressing modes: 10.12.2.3 offset addressing the offset value is added to or subtracted from the address obtained from the register rn . the result is used as the address for the memory access. the register rn is unaltered. the assem- bly language syntax for this mode is: [ rn , # offset ] 10.12.2.4 pre-indexed addressing the offset value is added to or subtracted from the address obtained from the register rn . the result is used as the address for the memory access and written back into the register rn . the assembly language syntax for this mode is:
90 11011a?atarm?04-oct-10 sam3n [ rn , # offset ]! 10.12.2.5 post-indexed addressing the address obtained from the register rn is used as the address for the memory access. the offset value is added to or subtracted from the address, and written back into the register rn . the assembly language syntax for this mode is: [ rn ], # offset the value to load or store can be a byte, halfword, word, or two words. bytes and halfwords can either be signed or unsigned. see ?address alignment? on page 83 . table 10-18 shows the ranges of offset for immediate, pre-indexed and post-indexed forms. 10.12.2.6 restrictions for load instructions: ? rt can be sp or pc for word loads only ? rt must be different from rt2 for two-word loads ? rn must be different from rt and rt2 in the pre-indexed or post-indexed forms. when rt is pc in a word load instruction: ? bit[0] of the loaded value must be 1 for correct execution ? a branch occurs to the address created by changing bit[0] of the loaded value to 0 ? if the instruction is conditi onal, it must be the last instruction in the it block. for store instructions: ? rt can be sp for word stores only ? rt must not be pc ? rn must not be pc ? rn must be different from rt and rt2 in the pre-indexed or post-indexed forms. 10.12.2.7 condition flags these instructions do not change the flags. table 10-18. offset ranges instruction type immediate offset pre-indexed post-indexed word, halfword, signed halfword, byte, or signed byte ? 255 to 4095 ? 255 to 255 ? 255 to 255 tw o w o r d s multiple of 4 in the range ? 1020 to 1020 multiple of 4 in the range ? 1020 to 1020 multiple of 4 in the range ? 1020 to 1020
91 11011a?atarm?04-oct-10 sam3n 10.12.2.8 examples ldr r8, [r10] ; loads r8 from the address in r10. ldrne r2, [r5, #960]! ; loads (conditionally) r2 from a word ; 960 bytes above the address in r5, and ; increments r5 by 960. str r2, [r9,#const-struc] ; const-struc is an expression evaluating ; to a constant in the range 0-4095. strh r3, [r4], #4 ; store r3 as halfword data into address in ; r4, then increment r4 by 4 ldrd r8, r9, [r3, #0x20] ; load r8 from a word 32 bytes above the ; address in r3, and load r9 from a word 36 ; bytes above the address in r3 strd r0, r1, [r8], #-16 ; store r0 to address in r8, and store r1 to ; a word 4 bytes above the address in r8, ; and then decrement r8 by 16.
92 11011a?atarm?04-oct-10 sam3n 10.12.3 ldr and str, register offset load and store with register offset. 10.12.3.1 syntax op { type }{ cond } rt , [ rn , rm {, lsl # n }] where: op is one of: ldr load register. str store register. type is one of: b unsigned byte, zero extend to 32 bits on loads. sb signed byte, sign extend to 32 bits (ldr only). h unsigned halfword, zero extend to 32 bits on loads. sh signed halfword, sign extend to 32 bits (ldr only). - omit, for word. cond is an optional condition code, see ?conditional execution? on page 84 . rt is the register to load or store. rn is the register on which the memory address is based. rm is a register containing a value to be used as the offset. lsl # n is an optional shift, with n in the range 0 to 3. 10.12.3.2 operation ldr instructions load a regist er with a value from memory. str instructions store a register value into memory. the memory address to load from or store to is at an offset from the register rn . the offset is specified by the register rm and can be shifted left by up to 3 bits using lsl. the value to load or store can be a byte, halfword, or word. for load instructions, bytes and half- words can either be signed or unsigned. see ?address alignment? on page 83 . 10.12.3.3 restrictions in these instructions: ? rn must not be pc ? rm must not be sp and must not be pc ? rt can be sp only for word loads and word stores ? rt can be pc only for word loads. when rt is pc in a word load instruction: ? bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address ? if the instruction is conditi onal, it must be the last instruction in the it block.
93 11011a?atarm?04-oct-10 sam3n 10.12.3.4 condition flags these instructions do not change the flags. 10.12.3.5 examples str r0, [r5, r1] ; store value of r0 into an address equal to ; sum of r5 and r1 ldrsb r0, [r5, r1, lsl #1] ; read byte value from an address equal to ; sum of r5 and two times r1, sign extended it ; to a word value and put it in r0 str r0, [r1, r2, lsl #2] ; stores r0 to an address equal to sum of r1 ; and four times r2
94 11011a?atarm?04-oct-10 sam3n 10.12.4 ldr and str, unprivileged load and store with unprivileged access. 10.12.4.1 syntax op { type }t{ cond } rt , [ rn {, # offset }] ; immediate offset where: op is one of: ldr load register. str store register. type is one of: b unsigned byte, zero extend to 32 bits on loads. sb signed byte, sign extend to 32 bits (ldr only). h unsigned halfword, zero extend to 32 bits on loads. sh signed halfword, sign extend to 32 bits (ldr only). - omit, for word. cond is an optional condition code, see ?conditional execution? on page 84 . rt is the register to load or store. rn is the register on which the memory address is based. offset is an offset from rn and can be 0 to 255. if offset is omitted, the address is the value in rn . 10.12.4.2 operation these load and store instructions perform the same function as the memory access instructions with immediate offset, see ?ldr and str, immediate offset? on page 89 . the difference is that these instructions have only unprivileged acce ss even when used in privileged software. when used in unprivileged software, these instru ctions behave in exactly the same way as nor- mal memory access instruct ions with immediate offset. 10.12.4.3 restrictions in these instructions: ? rn must not be pc ? rt must not be sp and must not be pc. 10.12.4.4 condition flags these instructions do not change the flags. 10.12.4.5 examples strbteq r4, [r7] ; conditionally store least significant byte in ; r4 to an address in r7, with unprivileged access ldrht r2, [r2, #8] ; load halfword value from an address equal to ; sum of r2 and 8 into r2, with unprivileged access
95 11011a?atarm?04-oct-10 sam3n 10.12.5 ldr, pc-relative load register from memory. 10.12.5.1 syntax ldr{ type }{ cond } rt , label ldrd{ cond } rt , rt2 , label ; load two words where: type is one of: b unsigned byte, zero extend to 32 bits. sb signed byte, sign extend to 32 bits. h unsigned halfword, zero extend to 32 bits. sh signed halfword, sign extend to 32 bits. - omit, for word. cond is an optional condition code, see ?conditional execution? on page 84 . rt is the register to load or store. rt2 is the second register to load or store. label is a pc-relative expression. see ?pc-relative expressions? on page 84 . 10.12.5.2 operation ldr loads a register with a value from a pc-r elative memory address. the memory address is specified by a label or by an offset from the pc. the value to load or store can be a byte, halfword, or word. for load instructions, bytes and half- words can either be signed or unsigned. see ?address alignment? on page 83 . label must be within a limited range of the current instruction. table 10-19 shows the possible offsets between label and the pc. you might have to use the .w suffix to get the maximum offset range. see ?instruction width selection? on page 86 . 10.12.5.3 restrictions in these instructions: ? rt can be sp or pc only for word loads ? rt2 must not be sp and must not be pc ? rt must be different from rt2. when rt is pc in a word load instruction: table 10-19. offset ranges instruction type offset range word, halfword, signed halfword, byte, signed byte ? 4095 to 4095 tw o w o r d s ? 1020 to 1020
96 11011a?atarm?04-oct-10 sam3n ? bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address ? if the instruction is conditi onal, it must be the last instruction in the it block. 10.12.5.4 condition flags these instructions do not change the flags. 10.12.5.5 examples ldr r0, lookuptable ; load r0 with a word of data from an address ; labelled as lookuptable ldrsb r7, localdata ; load a byte value from an address labelled ; as localdata, sign extend it to a word ; value, and put it in r7
97 11011a?atarm?04-oct-10 sam3n 10.12.6 ldm and stm load and store multiple registers. 10.12.6.1 syntax op { addr_mode }{ cond } rn {!}, reglist where: op is one of: ldm load multiple registers. stm store multiple registers. addr_mode is any one of the following: ia increment address after each access. this is the default. db decrement address be fore each access. cond is an optional condition code, see ?conditional execution? on page 84 . rn is the register on which the memory addresses are based. ! is an optional writeback suffix. if ! is present the final address, that is loaded from or stored to, is written back into rn . reglist is a list of one or more registers to be loaded or stored, enclosed in braces. it can contain register ranges. it must be comma separated if it contains more than one register or reg- ister range, see ?examples? on page 98 . ldm and ldmfd are synonyms for ldmia. ldmfd refers to its use for popping data from full descending stacks. ldmea is a synonym for ldmdb, and refers to its use for popping data from empty ascending stacks. stm and stmea are synonyms for stmia. stmea refers to its use for pushing data onto empty ascending stacks. stmfd is s synonym for stmdb, and refers to its use for pushing data onto full descending stacks 10.12.6.2 operation ldm instructions load the registers in reglist with word values from memory addresses based on rn . stm instructions store the word values in the registers in reglist to memory addresses based on rn . for ldm, ldmia, ldmfd, stm, stmia, and stmea the memory addresses used for the accesses are at 4-byte intervals ranging from rn to rn + 4 * ( n -1), where n is the number of reg- isters in reglist . the accesses happens in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest number register using the highest memory address. if the writeback suffix is specified, the value of rn + 4 * ( n -1) is written back to rn . for ldmdb, ldmea, stmdb, and stmfd the memory addresses used for the accesses are at 4-byte intervals ranging from rn to rn - 4 * ( n -1), where n is the number of registers in reglist .
98 11011a?atarm?04-oct-10 sam3n the accesses happen in order of decreasing register numbers, with the highest numbered regis- ter using the highest memory address and the lowest number register using the lowest memory address. if the writeback suffix is specified, the value of rn - 4 * ( n -1) is written back to rn . the push and pop instructions can be expressed in this form. see ?push and pop? on page 99 for details. 10.12.6.3 restrictions in these instructions: ? rn must not be pc ? reglist must not contain sp ? in any stm instruction, reglist must not contain pc ? in any ldm instruction, reglist must not contain pc if it contains lr ? reglist must not contain rn if you specify the writeback suffix. when pc is in reglist in an ldm instruction: ? bit[0] of the value loaded to the pc must be 1 for correct execution, and a branch occurs to this halfword-aligned address ? if the instruction is conditi onal, it must be the last instruction in the it block. 10.12.6.4 condition flags these instructions do not change the flags. 10.12.6.5 examples ldm r8,{r0,r2,r9} ; ldmia is a synonym for ldm stmdb r1!,{r3-r6,r11,r12} 10.12.6.6 incorrect examples stm r5!,{r5,r4,r9} ; value stored for r5 is unpredictable ldm r2, {} ; there must be at least one register in the list
99 11011a?atarm?04-oct-10 sam3n 10.12.7 push and pop push registers onto, and pop registers off a full-descending stack. 10.12.7.1 syntax push{ cond } reglist pop{ cond } reglist where: cond is an optional condition code, see ?conditional execution? on page 84 . reglist is a non-empty list of registers, enclos ed in braces. it can contain register ranges. it must be comma separated if it contains more than one register or register range. push and pop are synonyms for stmdb and ldm (or ldmia) with the memory addresses for the access based on sp, and with the final address for the access written back to the sp. push and pop are the preferred mnemonics in these cases. 10.12.7.2 operation push stores registers on the stack in order of decreasing the register numbers, with the highest numbered register using the highest memory address and the lowest numbered register using the lowest memory address. pop loads registers from the stack in order of increasing register numbers, with the lowest num- bered register using the lowest memory addres s and the highest numbered register using the highest memory address. see ?ldm and stm? on page 97 for more information. 10.12.7.3 restrictions in these instructions: ? reglist must not contain sp ? for the push instruction, reglist must not contain pc ? for the pop instruction, reglist must not contain pc if it contains lr. when pc is in reglist in a pop instruction: ? bit[0] of the value loaded to the pc must be 1 for correct execution, and a branch occurs to this halfword-aligned address ? if the instruction is conditi onal, it must be the last instruction in the it block. 10.12.7.4 condition flags these instructions do not change the flags. 10.12.7.5 examples push {r0,r4-r7} push {r2,lr} pop {r0,r10,pc}
100 11011a?atarm?04-oct-10 sam3n 10.12.8 ldrex and strex load and store register exclusive. 10.12.8.1 syntax ldrex{ cond } rt , [ rn {, # offset }] strex{ cond } rd , rt , [ rn {, # offset }] ldrexb{ cond } rt , [ rn ] strexb{ cond } rd , rt , [ rn ] ldrexh{ cond } rt , [ rn ] strexh{ cond } rd , rt , [ rn ] where: cond is an optional condition code, see ?conditional execution? on page 84 . rd is the destination register for the returned status. rt is the register to load or store. rn is the register on which the memory address is based. offset is an optional offset applied to the value in rn . if offset is omitted, the address is the value in rn . 10.12.8.2 operation ldrex, ldrexb, and ldrexh load a word, byte , and halfword respectively from a memory address. strex, strexb, and strexh attempt to store a word, byte, and halfword respectively to a memory address. the address used in any store-exclusive instruction must be the same as the address in the most recently executed load-exclusive instruction. the value stored by the store- exclusive instruction must also have the same data size as the value loaded by the preceding load-exclusive instruction. this means software must always use a load-exclusive instruction and a matching store-exclusive instruction to perform a synchronization operation, see ?syn- chronization primitives? on page 61 if an store-exclusive instruction performs the store, it writes 0 to its destination register. if it does not perform the store, it writes 1 to its desti nation register. if the store-exclusive instruction writes 0 to the destination register, it is guar anteed that no other process in the system has accessed the memory location between the load-exclusive and store-exclusive instructions. for reasons of performance, keep the number of instructions between corresponding load- exclusive and store-exclusive instruction to a minimum. the result of executing a store-exclusive instruction to an address that is different from that used in the preceding load-exclusive instruction is unpredictable. 10.12.8.3 restrictions in these instructions: ? do not use pc ? do not use sp for rd and rt ? for strex, rd must be different from both rt and rn ? the value of offset must be a multiple of four in the range 0-1020.
101 11011a?atarm?04-oct-10 sam3n 10.12.8.4 condition flags these instructions do not change the flags. 10.12.8.5 examples mov r1, #0x1 ; initialize the ?lock taken? value try ldrex r0, [lockaddr] ; load the lock value cmp r0, #0 ; is the lock free? itt eq ; it instruction for strexeq and cmpeq strexeq r0, r1, [lockaddr] ; try and claim the lock cmpeq r0, #0 ; did this succeed? bne try ; no ? try again .... ; yes ? we have the lock
102 11011a?atarm?04-oct-10 sam3n 10.12.9 clrex clear exclusive. 10.12.9.1 syntax clrex{ cond } where: cond is an optional condition code, see ?conditional execution? on page 84 . 10.12.9.2 operation use clrex to make the next str ex, strexb, or strexh instruct ion write 1 to its destination register and fail to perform the store. it is useful in exception handler code to force the failure of the store exclusive if the exception occurs between a load exclusive instruction and the match- ing store exclusive instruction in a synchronization operation. see ?synchronization primitives? on page 61 for more information. 10.12.9.3 condition flags these instructions do not change the flags. 10.12.9.4 examples clrex
103 11011a?atarm?04-oct-10 sam3n 10.13 general data pr ocessing instructions table 10-20 shows the data processing instructions: table 10-20. data processing instructions mnemonic brief description see adc add with carry ?add, adc, sub, sbc, and rsb? on page 105 add add ?add, adc, sub, sbc, and rsb? on page 105 addw add ?add, adc, sub, sbc, and rsb? on page 105 and logical and ?and, orr, eor, bic, and orn? on page 108 asr arithmetic shift right ?asr, lsl, lsr, ror, and rrx? on page 110 bic bit clear ?and, orr, eor, bic, and orn? on page 108 clz count leading zeros ?clz? on page 112 cmn compare negative ?cmp and cmn? on page 113 cmp compare ?cmp and cmn? on page 113 eor exclusive or ?and, orr, eor, bic, and orn? on page 108 lsl logical shift left ?asr, lsl, lsr, ror, and rrx? on page 110 lsr logical shift right ?asr, lsl, lsr, ror, and rrx? on page 110 mov move ?mov and mvn? on page 114 movt move top ?movt? on page 116 movw move 16-bit constant ?mov and mvn? on page 114 mvn move not ?mov and mvn? on page 114 orn logical or not ?and, orr, eor, bic, and orn? on page 108 orr logical or ?and, orr, eor, bic, and orn? on page 108 rbit reverse bits ?rev, rev16, revsh, and rbit? on page 117 rev reverse byte order in a word ?rev, rev16, revsh, and rbit? on page 117 rev16 reverse byte order in each halfword ?rev, rev16, revsh, and rbit? on page 117 revsh reverse byte order in bottom halfword and sign extend ?rev, rev16, revsh, and rbit? on page 117 ror rotate right ?asr, lsl, lsr, ror, and rrx? on page 110
104 11011a?atarm?04-oct-10 sam3n rrx rotate right with extend ?asr, lsl, lsr, ror, and rrx? on page 110 rsb reverse subtract ?add, adc, sub, sbc, and rsb? on page 105 sbc subtract with carry ?add, adc, sub, sbc, and rsb? on page 105 sub subtract ?add, adc, sub, sbc, and rsb? on page 105 subw subtract ?add, adc, sub, sbc, and rsb? on page 105 teq test equivalence ?tst and teq? on page 118 tst test ?tst and teq? on page 118 table 10-20. data processing instructions (continued) mnemonic brief description see
105 11011a?atarm?04-oct-10 sam3n 10.13.1 add, adc, sub, sbc, and rsb add, add with carry, subtract, subtract with ca rry, and reverse subtract. 10.13.1.1 syntax op {s}{ cond } { rd ,} rn , operand2 op { cond } { rd ,} rn , # imm12 ; add and sub only where: op is one of: add add. adc add with carry. sub subtract. sbc subtract with carry. rsb reverse subtract. s is an optional suffix. if s is specified, the condition code flags are updated on the result of the operation, see ?conditional execution? on page 84 . cond is an optional condition code, see ?conditional execution? on page 84 . rd is the destination register. if rd is omitted, the destination register is rn . rn is the register holding the first operand. operand2 is a flexible second operand. see ?flexible second operand? on page 80 for details of the options. imm12 is any value in the range 0-4095. 10.13.1.2 operation the add instruction adds the value of operand2 or imm12 to the value in rn . the adc instruction a dds the values in rn and operand2 , together with the carry flag. the sub instruction subtracts the value of operand2 or imm12 from the value in rn . the sbc instruction subtracts the value of operand2 from the value in rn . if the carry flag is clear, the result is reduced by one. the rsb instruction subtracts the value in rn from the value of operand2 . this is useful because of the wide range of options for operand2 . use adc and sbc to synthesize multiword arithmetic, see ?multiword arithmetic examples? on page 107 . see also ?adr? on page 88 . addw is equivalent to the add syntax that uses the imm12 operand. subw is equivalent to the sub syntax that uses the imm12 operand. 10.13.1.3 restrictions in these instructions: ? operand2 must not be sp and must not be pc
106 11011a?atarm?04-oct-10 sam3n ? rd can be sp only in add and sub, and only with the additional restrictions: ? rn must also be sp ? any shift in operand2 must be limited to a maximum of 3 bits using lsl ? rn can be sp only in add and sub ? rd can be pc only in the add{ cond } pc, pc, rm instruction where: ? you must not specify the s suffix ? rm must not be pc and must not be sp ? if the instruction is conditional, it must be the last instruction in the it block ? with the exception of the add{ cond } pc, pc, rm instruction, rn can be pc only in add and sub, and only with the additional restrictions: ? you must not specify the s suffix ? the second operand must be a constant in the range 0 to 4095. ? ? when using the pc for an addition or a subtraction, bits[1:0] of the pc are rounded to b00 before performing the calculation, making the base address for the calculation word-aligned. ? if you want to generate the address of an instruction, you have to adjust the constant based on the value of the pc. arm recommends that you use the adr instruction instead of add or sub with rn equal to the pc, because your assembler automatically calculates the correct constant for the adr instruction. when rd is pc in the add{ cond } pc, pc, rm instruction: ? bit[0] of the value written to the pc is ignored ? a branch occurs to the address created by forcing bit[0] of that value to 0. 10.13.1.4 condition flags if s is specified, these instructions update the n, z, c and v flags according to the result. 10.13.1.5 examples add r2, r1, r3 subs r8, r6, #240 ; sets the flags on the result rsb r4, r4, #1280 ; subtracts contents of r4 from 1280 adchi r11, r0, r3 ; only executed if c flag set and z ; flag clear
107 11011a?atarm?04-oct-10 sam3n 10.13.1.6 multiword arithmetic examples 10.13.1.7 64-bit addition the example below shows two instructions that add a 64-bit integer contained in r2 and r3 to another 64-bit integer con- tained in r0 and r1, and place the result in r4 and r5. adds r4, r0, r2 ; add the least significant words adc r5, r1, r3 ; add the most significant words with carry 10.13.1.8 96-bit subtraction multiword values do not have to use consecutive registers. t he example below shows instruct ions that subtract a 96-bit integer contained in r9, r1, and r11 from another contained in r6, r2, and r8. the example stores the result in r6, r9, and r2. subs r6, r6, r9 ; subtract the least significant words sbcs r9, r2, r1 ; subtract the middle words with carry sbc r2, r8, r11 ; subtract the most significant words with carry
108 11011a?atarm?04-oct-10 sam3n 10.13.2 and, orr, eor, bic, and orn logical and, or, exclusive or, bit clear, and or not. 10.13.2.1 syntax op {s}{ cond } { rd ,} rn , operand2 where: op is one of: and logical and. orr logical or, or bit set. eor logical exclusive or. bic logical and not, or bit clear. orn logical or not. s is an optional suffix. if s is specified, the condition code flags are updated on the result of the operation, see ?conditional execution? on page 84 . cond is an optional condition code, see see ?conditional execution? on page 84. . rd is the destination register. rn is the register holding the first operand. operand2 is a flexible second operand. see ?flexible second operand? on page 80 for details of the options. 10.13.2.2 operation the and, eor, and orr instructions perform bitwise and, exclusiv e or, and or operations on the values in rn and operand2 . the bic instruction performs an and operation on the bits in rn with the complements of the corresponding bits in the value of operand2 . the orn instruction performs an or operation on the bits in rn with the complements of the corresponding bits in the value of operand2 . 10.13.2.3 restrictions do not use sp and do not use pc. 10.13.2.4 condition flags if s is specified, these instructions: ? update the n and z flags according to the result ? can update the c flag during the calculation of operand2 , see ?flexible second operand? on page 80 ? do not affect the v flag.
109 11011a?atarm?04-oct-10 sam3n 10.13.2.5 examples and r9, r2, #0xff00 orreq r2, r0, r5 ands r9, r8, #0x19 eors r7, r11, #0x18181818 bic r0, r1, #0xab orn r7, r11, r14, ror #4 orns r7, r11, r14, asr #32
110 11011a?atarm?04-oct-10 sam3n 10.13.3 asr, lsl, lsr, ror, and rrx arithmetic shift right, logical shift left, logical shift right, rotate right, and rotate right with extend. 10.13.3.1 syntax op {s}{ cond } rd , rm , rs op {s}{ cond } rd , rm , # n rrx{s}{ cond } rd , rm where: op is one of: asr arithmetic shift right. lsl logical shift left. lsr logical shift right. ror rotate right. s is an optional suffix. if s is specified, the condition code flags are updated on the result of the operation, see ?conditional execution? on page 84 . rd is the destination register. rm is the register holding the value to be shifted. rs is the register holding the shift length to apply to the value in rm . only the least significant byte is used and can be in the range 0 to 255. n is the shift length. the range of shift length depends on the instruction: asr shift length from 1 to 32 lsl shift length from 0 to 31 lsr shift length from 1 to 32 ror shift length from 1 to 31. mov{s}{cond} rd, rm is the preferred syntax for lsl{s}{cond} rd, rm, #0. 10.13.3.2 operation asr, lsl, lsr, and ror move the bits in the register rm to the left or right by the number of places specified by constant n or register rs . rrx moves the bits in register rm to the right by 1. in all these instructions, the result is written to rd , but the value in register rm remains unchanged. for details on what result is generated by the different instructions, see ?shift oper- ations? on page 81 . 10.13.3.3 restrictions do not use sp and do not use pc. 10.13.3.4 condition flags if s is specified: ? these instructions update the n and z flags according to the result
111 11011a?atarm?04-oct-10 sam3n ? the c flag is updated to the last bit shifted out, except when the shift length is 0, see ?shift operations? on page 81 . 10.13.3.5 examples asr r7, r8, #9 ; arithmetic shift right by 9 bits lsls r1, r2, #3 ; logical shift left by 3 bits with flag update lsr r4, r5, #6 ; logical shift right by 6 bits ror r4, r5, r6 ; rotate right by the value in the bottom byte of r6 rrx r4, r5 ; rotate right with extend
112 11011a?atarm?04-oct-10 sam3n 10.13.4 clz count leading zeros. 10.13.4.1 syntax clz{ cond } rd , rm where: cond is an optional condition code, see ?conditional execution? on page 84 . rd is the destination register. rm is the operand register. 10.13.4.2 operation the clz instruction counts the number of leading zeros in the value in rm and returns the result in rd . the result value is 32 if no bits are set in the source register, and zero if bit[31] is set. 10.13.4.3 restrictions do not use sp and do not use pc. 10.13.4.4 condition flags this instruction does not change the flags. 10.13.4.5 examples clz r4,r9 clzne r2,r3
113 11011a?atarm?04-oct-10 sam3n 10.13.5 cmp and cmn compare and compare negative. 10.13.5.1 syntax cmp{ cond } rn , operand2 cmn{ cond } rn , operand2 where: cond is an optional condition code, see ?conditional execution? on page 84 . rn is the register holding the first operand. operand2 is a flexible second operand. see ?flexible second operand? on page 80 for details of the options. 10.13.5.2 operation these instructions compare the value in a register with operand2 . they update the condition flags on the result, but do not write the result to a register. the cmp instruction subtracts the value of operand2 from the value in rn . this is the same as a subs instruction, except that the result is discarded. the cmn instruction adds the value of operand2 to the value in rn . this is the same as an adds instruction, except th at the result is discarded. 10.13.5.3 restrictions in these instructions: ? do not use pc ? operand2 must not be sp. 10.13.5.4 condition flags these instructions update the n, z, c and v flags according to the result. 10.13.5.5 examples cmp r2, r9 cmn r0, #6400 cmpgt sp, r7, lsl #2
114 11011a?atarm?04-oct-10 sam3n 10.13.6 mov and mvn move and move not. 10.13.6.1 syntax mov{s}{ cond } rd , operand2 mov{ cond } rd , # imm16 mvn{s}{ cond } rd , operand2 where: s is an optional suffix. if s is specified, the condition code flags are updated on the result of the operation, see ?conditional execution? on page 84 . cond is an optional condition code, see ?conditional execution? on page 84 . rd is the destination register. operand2 is a flexible second operand. see ?flexible second operand? on page 80 for details of the options. imm16 is any value in the range 0-65535. 10.13.6.2 operation the mov instruction copies the value of operand2 into rd . when operand2 in a mov instruction is a register with a shift other than lsl #0, the preferred syntax is the corresponding shift instruction: ? asr{s}{cond} rd, rm, #n is the preferred syntax for mov{s}{cond} rd, rm, asr #n ? lsl{s}{cond} rd, rm, #n is the preferred syntax for mov{s}{cond} rd, rm, lsl #n if n != 0 ? lsr{s}{cond} rd, rm, #n is the preferre d syntax for mov{s}{cond} rd, rm, lsr #n ? ror{s}{cond} rd, rm, #n is the preferred syntax for mov{s}{cond} rd, rm, ror #n ? rrx{s}{cond} rd, rm is the preferred syntax for mov{s}{cond} rd, rm, rrx. also, the mov instruction permits additional forms of operand2 as synonyms for shift instructions: ? mov{s}{cond} rd, rm, asr rs is a synonym for asr{s}{cond} rd, rm, rs ? mov{s}{cond} rd, rm, lsl rs is a synonym for lsl{s}{cond} rd, rm, rs ? mov{s}{cond} rd, rm, lsr rs is a synonym for lsr{s}{cond} rd, rm, rs ? mov{s}{cond} rd, rm, ror rs is a synonym for ror{s}{cond} rd, rm, rs see ?asr, lsl, lsr, ror, and rrx? on page 110 . the mvn instruction takes the value of operand2 , performs a bitwise logical not operation on the value, and places the result into rd . the movw instruction provides the same function as mov, but is restricted to using the imm16 operand. 10.13.6.3 restrictions you can use sp and pc only in the mov instruction, with the following restrictions: ? the second operand must be a register without shift ? you must not specify the s suffix. when rd is pc in a mov instruction:
115 11011a?atarm?04-oct-10 sam3n ? bit[0] of the value written to the pc is ignored ? a branch occurs to the address created by forcing bit[0] of that value to 0. though it is possible to use mov as a branch instruction, arm strongly recommends the use of a bx or blx instruction to branch for softw are portability to the arm instruction set. 10.13.6.4 condition flags if s is specified, these instructions: ? update the n and z flags according to the result ? can update the c flag during the calculation of operand2 , see ?flexible second operand? on page 80 ? do not affect the v flag. 10.13.6.5 example movs r11, #0x000b ; write value of 0x000b to r11, flags get updated mov r1, #0xfa05 ; write value of 0xfa05 to r1, flags are not updated movs r10, r12 ; write value in r12 to r10, flags get updated mov r3, #23 ; write value of 23 to r3 mov r8, sp ; write value of stack pointer to r8 mvns r2, #0xf ; write value of 0xfffffff0 (bitwise inverse of 0xf) ; to the r2 and update flags
116 11011a?atarm?04-oct-10 sam3n 10.13.7 movt move top. 10.13.7.1 syntax movt{ cond } rd , # imm16 where: cond is an optional condition code, see ?conditional execution? on page 84 . rd is the destination register. imm16 is a 16-bit immediate constant. 10.13.7.2 operation movt writes a 16-bit immediate value, imm16 , to the top halfword, rd [31:16], of its destination register. the write does not affect rd [15:0]. the mov, movt instruction pair enables you to generate any 32-bit constant. 10.13.7.3 restrictions rd must not be sp and must not be pc. 10.13.7.4 condition flags this instruction does not change the flags. 10.13.7.5 examples movt r3, #0xf123 ; write 0xf123 to upper halfword of r3, lower halfword ; and apsr are unchanged
117 11011a?atarm?04-oct-10 sam3n 10.13.8 rev, rev16, revsh, and rbit reverse bytes and reverse bits. 10.13.8.1 syntax op { cond } rd , rn where: op is any of: rev reverse byte order in a word. rev16 reverse byte order in each halfword independently. revsh reverse byte order in the bottom halfword, and sign extend to 32 bits. rbit reverse the bit order in a 32-bit word. cond is an optional condition code, see ?conditional execution? on page 84 . rd is the destination register. rn is the register holding the operand. 10.13.8.2 operation use these instructions to change endianness of data: rev converts 32-bit big-endian data into little-endian data or 32-bit little-endian data into big-endian data. rev16 converts 16-bit big-endian data into little-endian data or 16-bit little-endian data into big-endian data. revsh converts either: 16-bit signed big-endian data into 32-bit signed little-endian data 16-bit signed little-endian data into 32-bit signed big-endian data. 10.13.8.3 restrictions do not use sp and do not use pc . 10.13.8.4 condition flags these instructions do not change the flags. 10.13.8.5 examples rev r3, r7 ; reverse byte order of value in r7 and write it to r3 rev16 r0, r0 ; reverse byte order of each 16-bit halfword in r0 revsh r0, r5 ; reverse signed halfword revhs r3, r7 ; reverse with higher or same condition rbit r7, r8 ; reverse bit order of value in r8 and write the result to r7
118 11011a?atarm?04-oct-10 sam3n 10.13.9 tst and teq test bits and test equivalence. 10.13.9.1 syntax tst{ cond } rn , operand2 teq{ cond } rn , operand2 where: cond is an optional condition code, see ?conditional execution? on page 84 . rn is the register holding the first operand. operand2 is a flexible second operand. see ?flexible second operand? on page 80 for details of the options. 10.13.9.2 operation these instructions test the value in a register against operand2 . they update the condition flags based on the result, but do not write the result to a register. the tst instruction performs a bitwise and operation on the value in rn and the value of operand2 . this is the same as the ands instructio n, except that it discards the result. to test whether a bit of rn is 0 or 1, use the tst instruction with an operand2 constant that has that bit set to 1 and all other bits cleared to 0. the teq instruction performs a bitwise exclusive or operation on the value in rn and the value of operand2 . this is the same as the eors instruction, except that it discards the result. use the teq instruction to test if two values are equal without affecting the v or c flags. teq is also useful for testing the sign of a val ue. after the comparison, the n flag is the logical exclusive or of the sign bits of the two operands. 10.13.9.3 restrictions do not use sp and do not use pc . 10.13.9.4 condition flags these instructions: ? update the n and z flags according to the result ? can update the c flag during the calculation of operand2 , see ?flexible second operand? on page 80 ? do not affect the v flag. 10.13.9.5 examples tst r0, #0x3f8 ; perform bitwise and of r0 value to 0x3f8, ; apsr is updated but result is discarded teqeq r10, r9 ; conditionally test if value in r10 is equal to ; value in r9, apsr is updated but result is discarded
119 11011a?atarm?04-oct-10 sam3n 10.14 multiply and divide instructions table 10-21 shows the multiply and divide instructions: table 10-21. multiply and divide instructions mnemonic brief description see mla multiply with accumulate, 32-bit result ?mul, mla, and mls? on page 120 mls multiply and subtract, 32-bit result ?mul, mla, and mls? on page 120 mul multiply, 32-bit result ?mul, mla, and mls? on page 120 sdiv signed divide ?sdiv and udiv? on page 122 smlal signed multiply with accumulate (32x32+64), 64-bit result ?umull, umlal, smull, and smlal? on page 121 smull signed multiply (32x32), 64-bit result ?umull, umlal, smull, and smlal? on page 121 udiv unsigned divide ?sdiv and udiv? on page 122 umlal unsigned multiply with accumulate (32x32+64), 64-bit result ?umull, umlal, smull, and smlal? on page 121 umull unsigned multiply (32x32), 64-bit result ?umull, umlal, smull, and smlal? on page 121
120 11011a?atarm?04-oct-10 sam3n 10.14.1 mul, mla, and mls multiply, multiply with accumulate, and multiply with subtract, using 32-bit operands, and pro- ducing a 32-bit result. 10.14.1.1 syntax mul{s}{ cond } { rd ,} rn , rm ; multiply mla{ cond } rd , rn , rm , ra ; multiply with accumulate mls{ cond } rd , rn , rm , ra ; multiply with subtract where: cond is an optional condition code, see ?conditional execution? on page 84 . s is an optional suffix. if s is specified, the condition code flags are updated on the result of the operation, see ?conditional execution? on page 84 . rd is the destination register. if rd is omitted, the destination register is rn . rn, rm are registers holding the values to be multiplied. ra is a register holding the value to be added or subtracted from. 10.14.1.2 operation the mul instruction mult iplies the values from rn and rm , and places the least significant 32 bits of the result in rd . the mla instruction mult iplies the values from rn and rm , adds the value from ra , and places the least significant 32 bits of the result in rd . the mls instruction mult iplies the values from rn and rm , subtracts the product from the value from ra , and places the least significant 32 bits of the result in rd . the results of these instructions do not depend on whether the operands are signed or unsigned. 10.14.1.3 restrictions in these instructions, do not use sp and do not use pc. if you use the s suffix with the mul instruction: ? rd , rn , and rm must all be in the range r0 to r7 ? rd must be the same as rm ? you must not use the cond suffix. 10.14.1.4 condition flags if s is specified, the mul instruction: ? updates the n and z flags according to the result ? does not affect the c and v flags. 10.14.1.5 examples mul r10, r2, r5 ; multiply, r10 = r2 x r5 mla r10, r2, r1, r5 ; multiply with accumulate, r10 = (r2 x r1) + r5 muls r0, r2, r2 ; multiply with flag update, r0 = r2 x r2 mullt r2, r3, r2 ; conditionally multiply, r2 = r3 x r2 mls r4, r5, r6, r7 ; multiply with subtract, r4 = r7 - (r5 x r6)
121 11011a?atarm?04-oct-10 sam3n 10.14.2 umull, umlal, smull, and smlal signed and unsigned long multiply, with optional accumulate, using 32-bit operands and pro- ducing a 64-bit result. 10.14.2.1 syntax op { cond } rdlo , rdhi , rn , rm where: op is one of: umull unsigned long multiply. umlal unsigned long multiply, with accumulate. smull signed long multiply. smlal signed long multip ly, with accumulate. cond is an optional condition code, see ?conditional execution? on page 84 . rdhi , rdlo are the destination registers. for umlal and smlal they also hold the accumulating value. rn, rm are registers holding the operands. 10.14.2.2 operation the umull instruction interprets the values from rn and rm as unsigned integers. it multiplies these integers and places the least si gnificant 32 bits of the result in rdlo , and the most signifi- cant 32 bits of the result in rdhi . the umlal instruction interprets the values from rn and rm as unsigned integers. it multiplies these integers, adds the 64-bit result to the 64-bit unsigned integer contained in rdhi and rdlo , and writes the result back to rdhi and rdlo . the smull instruction inte rprets the values from rn and rm as two?s complement signed inte- gers. it multiplies these integers and places the least significant 32 bi ts of the result in rdlo , and the most significant 32 bits of the result in rdhi . the smlal instruction interprets the values from rn and rm as two?s complement signed inte- gers. it multiplies these integers, adds the 64- bit result to the 64-bit signed integer contained in rdhi and rdlo , and writes the result back to rdhi and rdlo . 10.14.2.3 restrictions in these instructions: ? do not use sp and do not use pc ? rdhi and rdlo must be different registers. 10.14.2.4 condition flags these instructions do not affect the condition code flags. 10.14.2.5 examples umull r0, r4, r5, r6 ; unsigned (r4,r0) = r5 x r6 smlal r4, r5, r3, r8 ; signed (r5,r4) = (r5,r4) + r3 x r8
122 11011a?atarm?04-oct-10 sam3n 10.14.3 sdiv and udiv signed divide and unsigned divide. 10.14.3.1 syntax sdiv{ cond } { rd ,} rn , rm udiv{ cond } { rd ,} rn, rm where: cond is an optional condition code, see ?conditional execution? on page 84 . rd is the destination register. if rd is omitted, the destination register is rn . rn is the register holding the value to be divided. rm is a register holding the divisor. 10.14.3.2 operation sdiv performs a signed integer division of the value in rn by the value in rm . udiv performs an unsigned integer division of the value in rn by the value in rm . for both instructions, if the value in rn is not divisible by the value in rm , the result is rounded towards zero. 10.14.3.3 restrictions do not use sp and do not use pc . 10.14.3.4 condition flags these instructions do not change the flags. 10.14.3.5 examples sdiv r0, r2, r4 ; signed divide, r0 = r2/r4 udiv r8, r8, r1 ; unsigned divide, r8 = r8/r1
123 11011a?atarm?04-oct-10 sam3n 10.15 saturating instructions this section describes the satura ting instructions, ssat and usat. 10.15.1 ssat and usat signed saturate and unsigned saturate to any bit position, with optional shift before saturating. 10.15.1.1 syntax op { cond } rd , # n , rm {, shift #s} where: op is one of: ssat saturates a signed value to a signed range. usat saturates a signed value to an unsigned range. cond is an optional condition code, see ?conditional execution? on page 84 . rd is the destination register. n specifies the bit position to saturate to: n ranges from 1 to 32 for ssat n ranges from 0 to 31 for usat. rm is the register containing the value to saturate. shift #s is an optional shift applied to rm before saturating. it must be one of the following: asr # s where s is in the range 1 to 31 lsl # s where s is in the range 0 to 31. 10.15.1.2 operation these instructions saturate to a signed or unsigned n -bit value. the ssat instruction applies the specified shift, then saturates to the signed range ? 2 n ?1 x 2 n ?1 ? 1. the usat instruction applies the specified shift, then saturates to the unsigned range 0 x 2 n ? 1. for signed n -bit saturation using ssat, this means that: ? if the value to be saturated is less than ? 2 n ? 1 , the result returned is ? 2 n-1 ? if the value to be saturated is greater than 2 n ? 1 ? 1, the result returned is 2 n-1 ? 1 ? otherwise, the result returned is the same as the value to be saturated. for unsigned n -bit saturation using usat, this means that: ? if the value to be saturated is less than 0, the result returned is 0 ? if the value to be saturated is greater than 2 n ? 1, the result returned is 2 n ? 1 ? otherwise, the result returned is the same as the value to be saturated. if the returned result is different from the value to be saturated, it is called saturation . if satura- tion occurs, the instruction sets the q flag to 1 in the apsr. otherwise, it leaves the q flag unchanged. to clear the q flag to 0, you must use the msr instruction, see ?msr? on page 144 . to read the state of the q flag, use the mrs instruction, see ?mrs? on page 143 .
124 11011a?atarm?04-oct-10 sam3n 10.15.1.3 restrictions do not use sp and do not use pc . 10.15.1.4 condition flags these instructions do not affect the condition code flags. if saturation occurs, these instructions set the q flag to 1. 10.15.1.5 examples ssat r7, #16, r7, lsl #4 ; logical shift left value in r7 by 4, then ; saturate it as a signed 16-bit value and ; write it back to r7 usatne r0, #7, r5 ; conditionally saturate value in r5 as an ; unsigned 7 bit value and write it to r0
125 11011a?atarm?04-oct-10 sam3n 10.16 bitfield instructions table 10-22 shows the instructions that operate on adjacent sets of bits in registers or bitfields: table 10-22. packing and unpacking instructions mnemonic brief description see bfc bit field clear ?bfc and bfi? on page 126 bfi bit field insert ?bfc and bfi? on page 126 sbfx signed bit field extract ?sbfx and ubfx? on page 127 sxtb sign extend a byte ?sxt and uxt? on page 128 sxth sign extend a halfword ?sxt and uxt? on page 128 ubfx unsigned bit field extract ?sbfx and ubfx? on page 127 uxtb zero extend a byte ?sxt and uxt? on page 128 uxth zero extend a halfword ?sxt and uxt? on page 128
126 11011a?atarm?04-oct-10 sam3n 10.16.1 bfc and bfi bit field clear and bit field insert. 10.16.1.1 syntax bfc{ cond } rd , # lsb , # width bfi{ cond } rd , rn , # lsb , # width where: cond is an optional condition code, see ?conditional execution? on page 84 . rd is the destination register. rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32 ? lsb . 10.16.1.2 operation bfc clears a bitfield in a register. it clears width bits in rd , starting at the low bit position lsb . other bits in rd are unchanged. bfi copies a bitfield into one register from another register. it replaces width bits in rd starting at the low bit position lsb , with width bits from rn starting at bit[0]. other bits in rd are unchanged. 10.16.1.3 restrictions do not use sp and do not use pc. 10.16.1.4 condition flags these instructions do not affect the flags. 10.16.1.5 examples bfc r4, #8, #12 ; clear bit 8 to bit 19 (12 bits) of r4 to 0 bfi r9, r2, #8, #12 ; replace bit 8 to bit 19 (12 bits) of r9 with ; bit 0 to bit 11 from r2
127 11011a?atarm?04-oct-10 sam3n 10.16.2 sbfx and ubfx signed bit field extract and unsigned bit field extract. 10.16.2.1 syntax sbfx{ cond } rd , rn , # lsb , # width ubfx{ cond } rd , rn , # lsb , # width where: cond is an optional condition code, see ?conditional execution? on page 84 . rd is the destination register. rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32 ? lsb . 10.16.2.2 operation sbfx extracts a bitfield from one register, sign ex tends it to 32 bits, and writes the result to the destination register. ubfx extracts a bitfield from one register, zero exte nds it to 32 bits, and writes the result to the destination register. 10.16.2.3 restrictions do not use sp and do not use pc . 10.16.2.4 condition flags these instructions do not affect the flags. 10.16.2.5 examples sbfx r0, r1, #20, #4 ; extract bit 20 to bit 23 (4 bits) from r1 and sign ; extend to 32 bits and then write the result to r0. ubfx r8, r11, #9, #10 ; extract bit 9 to bit 18 (10 bits) from r11 and zero ; extend to 32 bits and then write the result to r8
128 11011a?atarm?04-oct-10 sam3n 10.16.3 sxt and uxt sign extend and zero extend. 10.16.3.1 syntax sxt extend { cond } { rd ,} rm {, ror # n } uxt extend { cond } { rd }, rm {, ror # n } where: extend is one of: b extends an 8-bit value to a 32-bit value. h extends a 16-bit value to a 32-bit value. cond is an optional condition code, see ?conditional execution? on page 84 . rd is the destination register. rm is the register holding the value to extend. ror # n is one of: ror #8 value from rm is rotated right 8 bits. ror #16 value from rm is rotated right 16 bits. ror #24 value from rm is rotated right 24 bits. if ror # n is omitted, no rotation is performed. 10.16.3.2 operation these instructions do the following: ? rotate the value from rm right by 0, 8, 16 or 24 bits. ? extract bits from the resulting value: sxtb extracts bits[7:0] and sign extends to 32 bits. uxtb extracts bits[7:0] and zero extends to 32 bits. sxth extracts bits[15:0] and sign extends to 32 bits. uxth extracts bits[15:0] and zero extends to 32 bits. 10.16.3.3 restrictions do not use sp and do not use pc. 10.16.3.4 condition flags these instructions do not affect the flags. 10.16.3.5 examples sxth r4, r6, ror #16 ; rotate r6 right by 16 bits, then obtain the lower ; halfword of the result and then sign extend to ; 32 bits and write the result to r4. uxtb r3, r10 ; extract lowest byte of the value in r10 and zero ; extend it, and write the result to r3
129 11011a?atarm?04-oct-10 sam3n 10.17 branch and contr ol instructions table 10-23 shows the branch and control instructions: table 10-23. branch and control instructions mnemonic brief description see bbranch ?b, bl, bx, and blx? on page 130 bl branch with link ?b, bl, bx, and blx? on page 130 blx branch indirect with link ?b, bl, bx, and blx? on page 130 bx branch indirect ?b, bl, bx, and blx? on page 130 cbnz compare and branch if non zero ?cbz and cbnz? on page 132 cbz compare and branch if non zero ?cbz and cbnz? on page 132 it if-then ?it? on page 133 tbb table branch byte ?tbb and tbh? on page 135 tbh table branch halfword ?tbb and tbh? on page 135
130 11011a?atarm?04-oct-10 sam3n 10.17.1 b, bl, bx, and blx branch instructions. 10.17.1.1 syntax b{ cond } label bl{ cond } label bx{ cond } rm blx{ cond } rm where: b is branch (immediate). bl is branch with link (immediate). bx is branch indirect (register). blx is branch indirect with link (register). cond is an optional condition code, see ?conditional execution? on page 84 . label is a pc-relative expression. see ?pc-relative expressions? on page 84 . rm is a register that indicates an address to branch to. bit[0] of the value in rm must be 1, but the address to branch to is created by changing bit[0] to 0. 10.17.1.2 operation all these instructions cause a branch to label , or to the address indicated in rm . in addition: ? the bl and blx instructions write the address of the next instruction to lr (the link register, r14). ? the bx and blx instructions cause a usagefault exception if bit[0] of rm is 0. b cond label is the only conditional instruction that can be either inside or outside an it block. all other branch instructions must be conditional inside an it block, and must be unconditional out- side the it block, see ?it? on page 133 . table 10-24 shows the ranges for the various branch instructions. you might have to use the .w suffix to get the maximum branch range. see ?instruction width selection? on page 86 . 10.17.1.3 restrictions the restrictions are: table 10-24. branch ranges instruction branch range b label ? 16 mb to +16 mb b cond label (outside it block) ? 1 mb to +1 mb b cond label (inside it block) ? 16 mb to +16 mb bl{ cond } label ? 16 mb to +16 mb bx{ cond } rm any value in register blx{ cond } rm any value in register
131 11011a?atarm?04-oct-10 sam3n ? do not use pc in the blx instruction ? for bx and blx, bit[0] of rm must be 1 for correct execution but a branch occurs to the target address created by changing bit[0] to 0 ? when any of these instructions is inside an it block, it must be the last instruction of the it block. b cond is the only conditional instruct ion that is not required to be inside an it block. however, it has a longer branch range when it is inside an it block. 10.17.1.4 condition flags these instructions do not change the flags. 10.17.1.5 examples b loopa ; branch to loopa ble ng ; conditionally branch to label ng b.w target ; branch to target within 16mb range beq target ; conditionally branch to target beq.w target ; conditionally branch to target within 1mb bl func ; branch with link (call) to function func, return address ; stored in lr bx lr ; return from function call bxne r0 ; conditionally branch to address stored in r0 blx r0 ; branch with link and exchange (call) to a address stored ; in r0
132 11011a?atarm?04-oct-10 sam3n 10.17.2 cbz and cbnz compare and branch on zero, compare and branch on non-zero. 10.17.2.1 syntax cbz rn , label cbnz rn , label where: rn is the register holding the operand. label is the branch destination. 10.17.2.2 operation use the cbz or cbnz instructions to avoid changing the condition code flags and to reduce the number of instructions. cbz rn, label does not change condition flags but is otherwise equivalent to: cmp rn, #0 beq label cbnz rn, label does not change condition flags but is otherwise equivalent to: cmp rn, #0 bne label 10.17.2.3 restrictions the restrictions are: ? rn must be in the range of r0 to r7 ? the branch destination must be within 4 to 130 bytes after the instruction ? these instructions must not be used inside an it block. 10.17.2.4 condition flags these instructions do not change the flags. 10.17.2.5 examples cbz r5, target ; forward branch if r5 is zero cbnz r0, target ; forward branch if r0 is not zero
133 11011a?atarm?04-oct-10 sam3n 10.17.3 it if-then condition instruction. 10.17.3.1 syntax it{ x { y { z }}} cond where: x specifies the condition switch for the second instruction in the it block. y specifies the condition switch for the third instruction in the it block. z specifies the condition switch for the fourth instruction in the it block. cond specifies the condition for the first instruction in the it block. the condition switch for the second, third and fourth instruction in the it block can be either: t then. applies the condition cond to the instruction. e else. applies the inverse condition of cond to the instruction. it is possible to use al (the always condition) for cond in an it instruction. if this is done, all of the instructions in the it block must be unconditional, and each of x , y , and z must be t or omit- ted but not e. 10.17.3.2 operation the it instruction makes up to four following in structions conditional. the conditions can be all the same, or some of them can be the logical inverse of the others. the conditional instructions following the it instruction form the it block . the instructions in the it block, including any branches, must specify the condition in the { cond } part of their syntax. your assembler might be able to generate the required it instructions for conditional instructions automatically, so that you do not need to write them yourself. see your assembler documenta- tion for details. a bkpt instruction in an it block is alwa ys executed, even if its condition fails. exceptions can be taken between an it instruction and the corresponding it block, or within an it block. such an exception results in entry to the appropriate exception handler, with suitable return information in lr and stacked psr. instructions designed for use for exception returns can be used as normal to return from the exception, and execution of the it block resumes correctly. this is the only way that a pc-modi- fying instruction is permitted to branch to an instruction in an it block. 10.17.3.3 restrictions the following instructions are not permitted in an it block: ?it ? cbz and cbnz ? cpsid and cpsie. other restrictions when using an it block are:
134 11011a?atarm?04-oct-10 sam3n ? a branch or any instruction that modifies the pc must either be outside an it block or must be the last instruction inside the it block. these are: ? add pc, pc, rm ? mov pc, rm ? b, bl, bx, blx ? any ldm, ldr, or pop instruction that writes to the pc ? tbb and tbh ? do not branch to any instruction inside an it block, except when returning from an exception handler ? all conditional instructions except b cond must be inside an it block. b cond can be either outside or inside an it block but has a larger branch range if it is inside one ? each instruction inside the it block must specif y a condition code suffix that is either the same or logical inverse as for the other instructions in the block. your assembler might place extra restrictions on the use of it blocks, such as prohibiting the use of assembler directives within them. 10.17.3.4 condition flags this instruction does not change the flags. 10.17.3.5 example itte ne ; next 3 instructions are conditional andne r0, r0, r1 ; andne does not update condition flags addsne r2, r2, #1 ; addsne updates condition flags moveq r2, r3 ; conditional move cmp r0, #9 ; convert r0 hex value (0 to 15) into ascii ; ('0'-'9', 'a'-'f') ite gt ; next 2 instructions are conditional addgt r1, r0, #55 ; convert 0xa -> 'a' addle r1, r0, #48 ; convert 0x0 -> '0' it gt ; it block with only one conditional instruction addgt r1, r1, #1 ; increment r1 conditionally ittee eq ; next 4 instructions are conditional moveq r0, r1 ; conditional move addeq r2, r2, #10 ; conditional add andne r3, r3, #1 ; conditional and bne.w dloop ; branch instruction can only be used in the last ; instruction of an it block it ne ; next instruction is conditional add r0, r0, r1 ; syntax error: no condition code used in it block
135 11011a?atarm?04-oct-10 sam3n 10.17.4 tbb and tbh table branch byte and table branch halfword. 10.17.4.1 syntax tbb [ rn , rm ] tbh [ rn , rm , lsl #1] where: rn is the register containing the address of the table of branch lengths. if rn is pc, then the address of the table is the address of the byte immediately following the tbb or tbh instruction. rm is the index register. this contains an index into the table. for halfword tables, lsl #1 doubles the value in rm to form the right offset into the table. 10.17.4.2 operation these instructions cause a pc-relative forward branch using a table of single byte offsets for tbb, or halfword offsets for tbh. rn provides a pointer to the table, and rm supplies an index into the table. for tbb the branch offset is twice the unsigned value of the byte returned from the table. and for tbh the branch offset is tw ice the unsigned value of the halfword returned from the table. the branch occurs to the address at that offset from the address of the byte immediately after the tbb or tbh instruction. 10.17.4.3 restrictions the restrictions are: ? rn must not be sp ? rm must not be sp and must not be pc ? when any of these instructions is used inside an it block, it must be the last instruction of the it block. 10.17.4.4 condition flags these instructions do not change the flags.
136 11011a?atarm?04-oct-10 sam3n 10.17.4.5 examples adr.w r0, branchtable_byte tbb [r0, r1] ; r1 is the index, r0 is the base address of the ; branch table case1 ; an instruction sequence follows case2 ; an instruction sequence follows case3 ; an instruction sequence follows branchtable_byte dcb 0 ; case1 offset calculation dcb ((case2-case1)/2) ; case2 offset calculation dcb ((case3-case1)/2) ; case3 offset calculation tbh [pc, r1, lsl #1] ; r1 is the index, pc is used as base of the ; branch table branchtable_h dci ((casea - branchtable_h)/2) ; casea offset calculation dci ((caseb - branchtable_h)/2) ; caseb offset calculation dci ((casec - branchtable_h)/2) ; casec offset calculation casea ; an instruction sequence follows caseb ; an instruction sequence follows casec ; an instruction sequence follows
137 11011a?atarm?04-oct-10 sam3n 10.18 miscellaneous instructions table 10-25 shows the remaining cortex-m3 instructions: table 10-25. miscellaneous instructions mnemonic brief description see bkpt breakpoint ?bkpt? on page 138 cpsid change processor state, disable interrupts ?cps? on page 139 cpsie change processor state, enable interrupts ?cps? on page 139 dmb data memory barrier ?dmb? on page 140 dsb data synchronization barrier ?dsb? on page 141 isb instruction synchronization barrier ?isb? on page 142 mrs move from special register to register ?mrs? on page 143 msr move from register to special register ?msr? on page 144 nop no operation ?nop? on page 145 sev send event ?sev? on page 146 svc supervisor call ?svc? on page 147 wfe wait for event ?wfe? on page 148 wfi wait for interrupt ?wfi? on page 149
138 11011a?atarm?04-oct-10 sam3n 10.18.1 bkpt breakpoint. 10.18.1.1 syntax bkpt # imm where: imm is an expression evaluating to an integer in the range 0-255 (8-bit value). 10.18.1.2 operation the bkpt instruction causes the processor to enter debug state. debug tools can use this to investigate system state when the instruct ion at a particular address is reached. imm is ignored by the processor. if required, a debugger can use it to store additional informa- tion about the breakpoint. the bkpt instruction can be placed inside an it block, but it execut es unconditionally, unaf- fected by the condition specified by the it instruction. 10.18.1.3 condition flags this instruction does not change the flags. 10.18.1.4 examples bkpt 0xab ; breakpoint with immediate value set to 0xab (debugger can ; extract the immediate value by locating it using the pc)
139 11011a?atarm?04-oct-10 sam3n 10.18.2 cps change processor state. 10.18.2.1 syntax cps effect iflags where: effect is one of: ie clears the special purpose register. id sets the special purpose register. iflags is a sequence of one or more flags: i set or clear primask. f set or clear faultmask. 10.18.2.2 operation cps changes the primask and faultmask special register values. see ?exception mask registers? on page 49 for more information about these registers. 10.18.2.3 restrictions the restrictions are: ? use cps only from privileged software, it has no effect if used in unprivileged software ? cps cannot be conditional and so must not be used inside an it block. 10.18.2.4 condition flags this instruction does not change the condition flags. 10.18.2.5 examples cpsid i ; disable interrupts and configurable fault handlers (set primask) cpsid f ; disable interrupts and all fault handlers (set faultmask) cpsie i ; enable interrupts and configurable fault handlers (clear primask) cpsie f ; enable interrupts and fault handlers (clear faultmask)
140 11011a?atarm?04-oct-10 sam3n 10.18.3 dmb data memory barrier. 10.18.3.1 syntax dmb{ cond } where: cond is an optional condition code, see ?conditional execution? on page 84 . 10.18.3.2 operation dmb acts as a data memory barrier. it ensures that all explicit memory accesses that appear, in program order, before the dmb instruction are completed before any explicit memory accesses that appear, in program order, after the dmb instruction. dmb does not affect the ordering or execution of instructions that do not access memory. 10.18.3.3 condition flags this instruction does not change the flags. 10.18.3.4 examples dmb ; data memory barrier
141 11011a?atarm?04-oct-10 sam3n 10.18.4 dsb data synchronization barrier. 10.18.4.1 syntax dsb{ cond } where: cond is an optional condition code, see ?conditional execution? on page 84 . 10.18.4.2 operation dsb acts as a special data synchronization memory barrier. instructions that come after the dsb, in program order, do not execute until the dsb instruction completes. the dsb instruction completes when all explicit memory accesses before it complete. 10.18.4.3 condition flags this instruction does not change the flags. 10.18.4.4 examples dsb ; data synchronisation barrier
142 11011a?atarm?04-oct-10 sam3n 10.18.5 isb instruction synchronization barrier. 10.18.5.1 syntax isb{ cond } where: cond is an optional condition code, see ?conditional execution? on page 84 . 10.18.5.2 operation isb acts as an instruction synchronization barrier. it flushes the pipeline of the processor, so that all instructions following the isb are fetched from memory again, after the isb instruction has been completed. 10.18.5.3 condition flags this instruction does not change the flags. 10.18.5.4 examples isb ; instruction synchronisation barrier
143 11011a?atarm?04-oct-10 sam3n 10.18.6 mrs move the contents of a special register to a general-purpose register. 10.18.6.1 syntax mrs{ cond } rd , spec_reg where: cond is an optional condition code, see ?conditional execution? on page 84 . rd is the destination register. spec_reg can be any of: apsr, ipsr, epsr, iepsr, iapsr, eapsr, psr, msp, psp, primask, basepri, basepri_max, faultmask, or control. 10.18.6.2 operation use mrs in combination with msr as part of a read-modify-write sequence for updating a psr, for example to clear the q flag. in process swap code, the programmers model state of the process being swapped out must be saved, including relevant psr contents. similarly, the stat e of the process being swapped in must also be restored. these operations use mrs in the state-saving instruction sequence and msr in the state-restoring instruction sequence. basepri_max is an alias of basepri when used with the mrs instruction. see ?msr? on page 144 . 10.18.6.3 restrictions rd must not be sp and must not be pc. 10.18.6.4 condition flags this instruction does not change the flags. 10.18.6.5 examples mrs r0, primask ; read primask value and write it to r0
144 11011a?atarm?04-oct-10 sam3n 10.18.7 msr move the contents of a general-purpose register into the specified special register. 10.18.7.1 syntax msr{ cond } spec_reg , rn where: cond is an optional condition code, see ?conditional execution? on page 84 . rn is the source register. spec_reg can be any of: apsr, ipsr, epsr, iepsr, iapsr, eapsr, psr, msp, psp, primask, basepri, basepri_max, faultmask, or control. 10.18.7.2 operation the register access operation in msr depends on the privilege level. unprivileged software can only access the apsr, see ?application program status register? on page 47 . privileged soft- ware can access a ll special registers. in unprivileged software writes to unallocated or execution state bits in the psr are ignored. when you write to basepri_m ax, the instruction writes to basepri only if either: ? rn is non-zero and the current basepri value is 0 ? rn is non-zero and less than the current basepri value. see ?mrs? on page 143 . 10.18.7.3 restrictions rn must not be sp and must not be pc. 10.18.7.4 condition flags this instruction updates the flags explicitly based on the value in rn . 10.18.7.5 examples msr control, r1 ; read r1 value and write it to the control register
145 11011a?atarm?04-oct-10 sam3n 10.18.8 nop no operation. 10.18.8.1 syntax nop{ cond } where: cond is an optional condition code, see ?conditional execution? on page 84 . 10.18.8.2 operation nop does nothing. nop is not necessarily a time-consuming nop. the processor might remove it from the pipeline before it reaches the execution stage. use nop for padding, for example to place the following instruction on a 64-bit boundary. 10.18.8.3 condition flags this instruction does not change the flags. 10.18.8.4 examples nop ; no operation
146 11011a?atarm?04-oct-10 sam3n 10.18.9 sev send event. 10.18.9.1 syntax sev{ cond } where: cond is an optional condition code, see ?conditional execution? on page 84 . 10.18.9.2 operation sev is a hint instruction that caus es an event to be signaled to a ll processors within a multipro- cessor system. it also sets the local event register to 1, see ?power management? on page 72 . 10.18.9.3 condition flags this instruction does not change the flags. 10.18.9.4 examples sev ; send event
147 11011a?atarm?04-oct-10 sam3n 10.18.10 svc supervisor call. 10.18.10.1 syntax svc{ cond } # imm where: cond is an optional condition code, see ?conditional execution? on page 84 . imm is an expression evaluating to an integer in the range 0-255 (8-bit value). 10.18.10.2 operation the svc instruction causes the svc exception. imm is ignored by the processor. if required, it can be retrieved by the exception handler to determine what service is being requested. 10.18.10.3 condition flags this instruction does not change the flags. 10.18.10.4 examples svc 0x32 ; supervisor call (svc handler can extract the immediate value ; by locating it via the stacked pc)
148 11011a?atarm?04-oct-10 sam3n 10.18.11 wfe wait for event. 10.18.11.1 syntax wfe{ cond } where: cond is an optional condition code, see ?conditional execution? on page 84 . 10.18.11.2 operation wfe is a hint instruction. if the event register is 0, wfe suspends execution until one of the following events occurs: ? an exception, unless masked by the exception mask registers or the current priority level ? an exception enters the pending state, if sevonpend in the system control register is set ? a debug entry request, if debug is enabled ? an event signaled by a peripheral or another processor in a multiprocessor system using the sev instruction. if the event register is 1, wfe clears it to 0 and returns immediately. for more information see ?power management? on page 72 . 10.18.11.3 condition flags this instruction does not change the flags. 10.18.11.4 examples wfe ; wait for event
149 11011a?atarm?04-oct-10 sam3n 10.18.12 wfi wait for interrupt. 10.18.12.1 syntax wfi{ cond } where: cond is an optional condition code, see ?conditional execution? on page 84 . 10.18.12.2 operation wfi is a hint instruction that suspends execution until one of the following events occurs: ?an exception ? a debug entry request, regardless of whether debug is enabled. 10.18.12.3 condition flags this instruction does not change the flags. 10.18.12.4 examples wfi ; wait for interrupt
150 11011a?atarm?04-oct-10 sam3n 10.19 about the cortex-m3 peripherals the address map of the private peripheral bus (ppb) is: in register descriptions: ? the register type is described as follows: rw read and write. ro read-only. wo write-only. ? the required privilege gives the privilege level required to access the register, as follows: privileged only privileged software can access the register. unprivileged both unprivileged and privileged software can access the register. table 10-26. core peripheral register regions address core peripheral description 0xe000e008 - 0xe000e00f system control block table 10-30 on page 164 0xe000e010 - 0xe000e01f system timer table 10-33 on page 191 0xe000e100 - 0xe000e4ef nested vectored interrupt controller table 10-27 on page 151 0xe000ed00 - 0xe000ed3f system control block table 10-30 on page 164 0xe000ed90 - 0xe000ed93 mpu type register reads as zero, indicating no mpu is implemented (1) 1. software can read the mpu type register at 0xe000ed90 to test for the presence of a memory protection unit (mpu). 0xe000ef00 - 0xe000ef03 nested vectored interrupt controller table 10-27 on page 151
151 11011a?atarm?04-oct-10 sam3n 10.20 nested vectored interrupt controller this section describes the nested vectored interrupt controller (nvic) and the registers it uses. the nvic supports: ? 1 to 33 interrupts. ? a programmable priority level of 0-15 for each interrupt. a higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. ? level and pulse detection of interrupt signals. ? dynamic reprioritization of interrupts. ? grouping of priority values into group priority and subpriority fields. ? interrupt tail-chaining. the processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. this provides low latency exception handling. the hardware implementation of the nvic registers is: 10.20.1 the cmsis mapping of the cortex-m3 nvic registers to improve software efficiency, the cmsis simpli fies the nvic register presentation. in the cmsis: ? the set-enable, clear-enable, set-pending, clear-pending and active bit registers map to arrays of 32-bit integers, so that: ? the array iser[0] corresponds to the registers iser0 ? the array icer[0] corresponds to the registers icer0 ? the array ispr[0] corresponds to the registers ispr0 ? the array icpr[0] corresponds to the registers icpr0 ? the array iabr[0] corresponds to the registers iabr0 table 10-27. nvic register summary address name type required privilege reset value description 0xe000e100 iser0 rw privileged 0x00000000 ?interrupt set-enable registers? on page 153 0xe000e180 icer0 rw privileged 0x00000000 ?interrupt clear-enable registers? on page 154 0xe000e200 ispr0 rw privileged 0x00000000 ?interrupt set-pending registers? on page 155 0xe000e280 icpr0 rw privileged 0x00000000 ?interrupt clear-pending registers? on page 156 0xe000e300 iabr0 ro privileged 0x00000000 ?interrupt active bit registers? on page 157 0xe000e400- 0xe000e41c ipr0- ipr8 rw privileged 0x00000000 ?interrupt priority registers? on page 158 0xe000ef00 stir wo configurable (1) 0x00000000 ?software trigger interru pt register? on page 161 1. see the register description for more information.
152 11011a?atarm?04-oct-10 sam3n ? the 4-bit fields of the interrupt priority registers map to an array of 4-bit integers, so that the array ip[0] to ip[32] corresponds to the registers ipr0-ipr8, and the array entry ip[ n ] holds the interrupt priority for interrupt n . the cmsis provides thread-safe code that gives atomic access to the interrupt priority regis- ters. for more information see the description of the nvic_setpriority function in ?nvic programming hints? on page 163 . table 10-28 shows how the interrupts, or irq numbers, map onto the interrupt registers and corresponding cmsis variables that have one bit per interrupt. table 10-28. mapping of interrupts to the interrupt variables interrupts cmsis array elements (1) 1. each array element corresponds to a single nvic register, for example the element icer[0] corresponds to the icer0 register. set-enable clear-enable set-pen ding clear-pending active bit 0-32 iser[0] icer[0] ispr[0] icpr[0] iabr[0]
153 11011a?atarm?04-oct-10 sam3n 10.20.2 interrupt set-enable registers the iser0 register enables interrupts, and show which interrupts are enabled. see: ? the register summary in table 10-27 on page 151 for the register attributes ? table 10-28 on page 152 for which interrupts are controlled by each register. the bit assignments are: ? setena interrupt set-enable bits. write: 0 = no effect 1 = enable interrupt. read: 0 = interrupt disabled 1 = interrupt enabled. if a pending interrupt is enabled, the nvic activates the interrupt based on its priority. if an interrupt is not enabled, asse rt- ing its interrupt signal changes the interrupt state to pending, but the nvic never activates the interrupt, regardless of its priority. 31 30 29 28 27 26 25 24 setena bits 23 22 21 20 19 18 17 16 setena bits 15 14 13 12 11 10 9 8 setena bits 76543210 setena bits
154 11011a?atarm?04-oct-10 sam3n 10.20.3 interrupt clear-enable registers the icer0 register disables interrupts, and shows which interrupts are enabled. see: ? the register summary in table 10-27 on page 151 for the register attributes ? table 10-28 on page 152 for which interrupts are controlled by each register the bit assignments are: ?clrena interrupt clear-enable bits. write: 0 = no effect 1 = disable interrupt. read: 0 = interrupt disabled 1 = interrupt enabled. 31 30 29 28 27 26 25 24 clrena 23 22 21 20 19 18 17 16 clrena 15 14 13 12 11 10 9 8 clrena 76543210 clrena
155 11011a?atarm?04-oct-10 sam3n 10.20.4 interrupt set-pending registers the ispr0 register forces interrupts into the pending state, and shows which interrupts are pending. see: ? the register summary in table 10-27 on page 151 for the register attributes ? table 10-28 on page 152 for which interrupts are controlled by each register. the bit assignments are: ? setpend interrupt set-pending bits. write: 0 = no effect. 1 = changes interrupt state to pending. read: 0 = interrupt is not pending. 1 = interrupt is pending. writing 1 to the ispr bit corresponding to: ? an interrupt that is pending has no effect ? a disabled interrupt sets the state of that interrupt to pending 31 30 29 28 27 26 25 24 setpend 23 22 21 20 19 18 17 16 setpend 15 14 13 12 11 10 9 8 setpend 76543210 setpend
156 11011a?atarm?04-oct-10 sam3n 10.20.5 interrupt clear-pending registers the icpr0 register removes the pending state from interrupts, and show which interrupts are pending. see: ? the register summary in table 10-27 on page 151 for the register attributes ? table 10-28 on page 152 for which interrupts are controlled by each register. the bit assignments are: ? clrpend interrupt clear-pending bits. write: 0 = no effect. 1 = removes pending state an interrupt. read: 0 = interrupt is not pending. 1 = interrupt is pending. writing 1 to an icpr bit does not affect the active state of the corresponding interrupt. 31 30 29 28 27 26 25 24 clrpend 23 22 21 20 19 18 17 16 clrpend 15 14 13 12 11 10 9 8 clrpend 76543210 clrpend
157 11011a?atarm?04-oct-10 sam3n 10.20.6 interrupt active bit registers the iabr0 register indicates which interrupts are active. see: ? the register summary in table 10-27 on page 151 for the register attributes ? table 10-28 on page 152 for which interrupts are controlled by each register. the bit assignments are: ?active interrupt active flags: 0 = interrupt not active 1 = interrupt active. a bit reads as one if the status of the corresponding interrupt is active or active and pending. 31 30 29 28 27 26 25 24 active 23 22 21 20 19 18 17 16 active 15 14 13 12 11 10 9 8 active 76543210 active
158 11011a?atarm?04-oct-10 sam3n 10.20.7 interrupt priority registers the ipr0-ipr8 registers provide a 4-bit priority field for each interrupt (see the ?peripheral iden- tifiers? section of the datasheet for more details). these registers are byte-accessible. see the register summary in table 10-27 on page 151 for their attributes. each register holds four priority fields, that map up to four elements in the cmsis interrupt priority array ip[0] to ip[32] , as shown: 10.20.7.1 iprm 10.20.7.2 ipr4 10.20.7.3 ipr3 31 30 29 28 27 26 25 24 ip[4m+3] 23 22 21 20 19 18 17 16 ip[4m+2] 15 14 13 12 11 10 9 8 ip[4m+1] 76543210 ip[4m] 31 30 29 28 27 26 25 24 ip[19] 23 22 21 20 19 18 17 16 ip[18] 15 14 13 12 11 10 9 8 76543210 31 30 29 28 27 26 25 24 ip[15] 23 22 21 20 19 18 17 16 ip[14] 15 14 13 12 11 10 9 8 ip[13] 76543210 ip[12]
159 11011a?atarm?04-oct-10 sam3n 10.20.7.4 ipr2 10.20.7.5 ipr1 10.20.7.6 ipr0 ? priority, byte offset 3 ? priority, byte offset 2 ? priority, byte offset 1 ? priority, byte offset 0 each priority field holds a priority value, 0-15. the lower the value, the greater the priority of the corresponding interrupt. the processor implements only bits[7:4] of each fi eld, bits[3:0] read as zero and ignore writes. see ?the cmsis mapping of the cortex-m3 nvic registers? on page 151 for more information about the ip[0] to ip[32] interrupt priority array, that provides the software view of the interrupt priorities. 31 30 29 28 27 26 25 24 ip[11] 23 22 21 20 19 18 17 16 ip[10] 15 14 13 12 11 10 9 8 ip[9] 76543210 ip[8] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ip[6] 15 14 13 12 11 10 9 8 ip[5] 76543210 ip[4] 31 30 29 28 27 26 25 24 ip[3] 23 22 21 20 19 18 17 16 ip[2] 15 14 13 12 11 10 9 8 ip[1] 76543210 ip[0]
160 11011a?atarm?04-oct-10 sam3n find the ipr number and byte offset for interrupt n as follows: ? the corresponding ipr number, m , is given by m = n div 4 ? the byte offset of the required priority field in this register is n mod 4, where: ? byte offset 0 refers to register bits[7:0] ? byte offset 1 refers to register bits[15:8] ? byte offset 2 refers to register bits[23:16] ? byte offset 3 refers to register bits[31:24].
161 11011a?atarm?04-oct-10 sam3n 10.20.8 software trigger interrupt register write to the stir to generate a software generated interrupt (sgi). see the register summary in table 10-27 on page 151 for the stir attributes. when the usersetmpend bit in the scr is set to 1, unprivileged software can access the stir, see ?system control register? on page 173 . only privileged software can enable unprivileged access to the stir. the bit assignments are: ?intid interrupt id of the required sgi, in the range 0-239. for example, a value of b000000011 specifies interrupt irq3. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved intid 76543210 intid
162 11011a?atarm?04-oct-10 sam3n 10.20.9 level-sensitive interrupts the processor supports level-sensitive interrupts. a level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. typ- ically this happens because the isr accesses the peripheral, causing it to clear the interrupt request. when the processor enters the isr, it automatically removes the pending state from the inter- rupt, see ?hardware and software control of interrupts? . for a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the isr, the interrupt becomes pend- ing again, and the processor must execute its isr again. this means that the peripheral can hold the interrupt signal asserted until it no longer needs servicing. 10.20.9.1 hardware and software control of interrupts the cortex-m3 latches all interrupts. a peripheral interrupt becomes pending for one of the fol- lowing reasons: ? the nvic detects that the interrupt signal is high and the interrupt is not active ? the nvic detects a rising edge on the interrupt signal ? software writes to the corresponding interrupt set-pending register bit, see ?interrupt set- pending registers? on page 155 , or to the stir to make an sgi pending, see ?software trigger interrupt register? on page 161 . a pending interrupt remains pending until one of the following: the processor enters the isr for the interrupt. this changes the state of the interrupt from pend- ing to active. then: ? for a level-sensitive interrupt, when the processor returns from the isr, the nvic samples the interrupt signal. if the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the isr. otherwise, the state of the interrupt changes to inactive. ? if the interrupt signal is not pulsed while the processor is in the isr, when the processor returns from the isr the state of the interrupt changes to inactive. ? software writes to the corresponding interrupt clear-pending register bit. for a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. otherwise, the state of the interrupt changes to inactive.
163 11011a?atarm?04-oct-10 sam3n 10.20.10 nvic design hints and tips ensure software uses correctly aligned register accesses. the processor does not support unaligned accesses to nvic registers. see the individual register descriptions for the supported access sizes. a interrupt can enter pending state even it is disabled. before programming vtor to relocate the vector table, ensure the vector table entries of the new vector table are setup for fault handlers and all enabled exception like interrupts. for more information see ?vector table offset register? on page 170 . 10.20.10.1 nvic programming hints software uses the cpsie i and cpsid i instructions to enable and disable interrupts. the cmsis provides the following intrinsi c functions for these instructions: void __disable_irq(void) // disable interrupts void __enable_irq(void) // enable interrupts in addition, the cmsis provides a number of functions for nvic control, including: for more information about these functions see the cmsis documentation. table 10-29. cmsis functions for nvic control cmsis interrupt contro l function description void nvic_setprioritygrouping(uint32_t priority_grouping) set the priority grouping void nvic_enableirq(irqn_t irqn) enable irqn void nvic_disableirq(irqn_t irqn) disable irqn uint32_t nvic_getpendingi rq (irqn_t irqn) return true if irqn is pending void nvic_setpendingirq (irqn_t irqn) set irqn pending void nvic_clearpendingirq (irqn_t irqn) clear irqn pending status uint32_t nvic_getactive (irqn_t irqn) return the irq number of the active interrupt void nvic_setpriority (irqn_t irqn, uint32_t priority) set priority for irqn uint32_t nvic_getpriority (irqn_t irqn) read priority of irqn void nvic_systemreset (void) reset the system
164 11011a?atarm?04-oct-10 sam3n 10.21 system control block the system control block (scb) provides system implementation information, and system con- trol. this includes configuration, control, and reporting of the system exceptions. the system control block registers are: notes: 1. see the register description for more information. 2. a subregister of the cfsr. 10.21.1 the cmsis mapping of the cortex-m3 scb registers to improve software efficiency, the cmsis simp lifies the scb register presentation. in the cmsis, the byte array shp[0] to shp[12] corresponds to the registers shpr1-shpr3. table 10-30. summary of the system control block registers address name type required privilege reset value description 0xe000e008 actlr rw privileged 0x00000000 ?auxiliary control register? on page 165 0xe000ed00 cpuid ro privileged 0x412fc230 ?cpuid base register? on page 166 0xe000ed04 icsr rw (1) privileged 0x00000000 ?interrupt control and st ate register? on page 167 0xe000ed08 vtor rw privileged 0x00000000 ?vector table offset register? on page 170 0xe000ed0c aircr rw (1) privileged 0xfa050000 ?application interrupt and reset control register? on page 171 0xe000ed10 scr rw privileged 0x00000000 ?system control register? on page 173 0xe000ed14 ccr rw privileged 0x00000200 ?configuration and control register? on page 174 0xe000ed18 shpr1 rw privileged 0x00000000 ?system handler priority register 1? on page 177 0xe000ed1c shpr2 rw privileged 0x00000000 ?system handler priority register 2? on page 178 0xe000ed20 shpr3 rw privileged 0x00000000 ?system handler priority register 3? on page 178 0xe000ed24 shcrs rw privileged 0x00000000 ?system handler control and state register? on page 179 0xe000ed28 cfsr rw privileged 0x00000000 ?configurable fault status register? on page 181 0xe000ed28 mmsr (2) rw privileged 0x00 ?memory management fault address register? on page 188 0xe000ed29 bfsr (2) rw privileged 0x00 ?bus fault status register? on page 183 0xe000ed2a ufsr (2) rw privileged 0x0000 ?usage fault status register? on page 185 0xe000ed2c hfsr rw privileged 0x00000000 ?hard fault status register? on page 187 0xe000ed34 mmar rw privileged unknown ?memory management fault address register? on page 188 0xe000ed38 bfar rw privileged unknown ?bus fault address register? on page 189
165 11011a?atarm?04-oct-10 sam3n 10.21.2 auxiliary control register the actlr provides disable bits for the following processor functions: ? it folding ? write buffer use for accesses to the default memory map ? interruption of multi-cycle instructions. see the register summary in table 10-30 on page 164 for the actlr attributes. the bit assign- ments are: ?disfold when set to 1, disables it folding. see ?about it folding? on page 165 for more information. ?disdefwbuf when set to 1, disables write buffer use during default memory map accesses. this causes all bus faults to be precise bus faults but decreases performance because any store to memory must complete before the processor can execute the next instruction. this bit only affects write buffers implemented in the cortex-m3 processor. ? dismcycint when set to 1, disables interruption of load multiple and store multiple instructions. this increases the interrupt latency of the processor because any ldm or stm must complete before the processor can stack the current state and enter the interrupt handler. 10.21.2.1 about it folding in some situations, the processor can start executing the first instruction in an it block while it is still executing the it instruction. this behavio r is called it folding, and improves performance, however, it folding can cause jitte r in looping. if a task must avoid jitter, set the disfold bit to 1 before executing the task, to disable it folding. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 76543210 reserved disfold disdefwbuf dismcycint
166 11011a?atarm?04-oct-10 sam3n 10.21.3 cpuid base register the cpuid register contains the processor part number, version, and implementation informa- tion. see the register summary in table 10-30 on page 164 for its attributes. the bit assignments are: ? implementer implementer code: 0x41 = arm ?variant variant number, the r value in the r n p n product revision identifier: 0x2 = r2p0 ? constant reads as 0xf ?partno part number of the processor: 0xc23 = cortex-m3 ? revision revision number, the p value in the r n p n product revision identifier: 0x0 = r2p0 31 30 29 28 27 26 25 24 implementer 23 22 21 20 19 18 17 16 variant constant 15 14 13 12 11 10 9 8 partno 76543210 partno revision
167 11011a?atarm?04-oct-10 sam3n 10.21.4 interrupt control and state register the icsr: ? provides: ? set-pending and clear-pending bits for the pendsv and systick exceptions ? indicates: ? the exception number of the exception being processed ? whether there are preempted active exceptions ? the exception number of the highest priority pending exception ? whether any interrupts are pending. see the register summary in table 10-30 on page 164 , and the type descriptions in table 10-33 on page 191 , for the icsr attributes. the bit assignments are: ? pendsvset rw pendsv set-pending bit. write: 0 = no effect 1 = changes pendsv exception state to pending. read: 0 = pendsv exception is not pending 1 = pendsv exception is pending. writing 1 to this bit is the only way to set the pendsv exception state to pending. ? pendsvclr wo pendsv clear-pending bit. write: 0 = no effect 1 = removes the pending state from the pendsv exception. 31 30 29 28 27 26 25 24 reserved reserved pendsvset pendsvclr pendstset pendstclr reserved 23 22 21 20 19 18 17 16 reserved for debug isrpending vectpending 15 14 13 12 11 10 9 8 vectpending rettobase reserved vectactive 76543210 vectactive
168 11011a?atarm?04-oct-10 sam3n ? pendstset rw systick exception set-pending bit. write: 0 = no effect 1 = changes systick exception state to pending. read: 0 = systick exception is not pending 1 = systick exception is pending. ? pendstclr wo systick exception clear-pending bit. write: 0 = no effect 1 = removes the pending state from the systick exception. this bit is wo. on a register read its value is unknown. ? reserved for debug use ro this bit is reserved for debug use and reads-as-zero when the processor is not in debug. ? isrpending ro interrupt pending flag, excluding faults: 0 = interrupt not pending 1 = interrupt pending. ? vectpending ro indicates the exception number of the highest priority pending enabled exception: 0 = no pending exceptions nonzero = the exception number of the highest priority pending enabled exception. the value indicated by this field include s the effect of the basepri and faultmask registers, but not any effect of the primask register.
169 11011a?atarm?04-oct-10 sam3n ? rettobase ro indicates whether there are preempted active exceptions: 0 = there are preempted active exceptions to execute 1 = there are no active exceptions, or the currently -executing exception is the only active exception. ? vectactive ro contains the active exception number: 0 = thread mode nonzero = the exception number (1) of the currently active exception. subtract 16 from this value to obtain the irq number required to index into the interrupt clear-enable, set-enable, clear- pending, set-pending, or priority registers, see ?interrupt program status register? on page 48 . when you write to the icsr, the effect is unpredictable if you: ? write 1 to the pendsvset bit and write 1 to the pendsvclr bit ? write 1 to the pendstset bit and write 1 to the pendstclr bit. note: 1. this is the same valu e as ipsr bits [8:0] see ?interrupt program status register? on page 48 .
170 11011a?atarm?04-oct-10 sam3n 10.21.5 vector table offset register the vtor indicates the offset of the vector table base address from memory address 0x00000000. see the register summary in table 10-30 on page 164 for its attributes. the bit assignments are: ?tbloff vector table base offset field. it contains bits[29:7] of th e offset of the table base from the bottom of the memory map. bit[29] determines whether the vector table is in the code or sram memory region: 0 = code 1 = sram. bit[29] is sometimes called the tblbase bit. when setting tbloff, you must align the offset to the number of exception entries in the vector table. the minimum align- ment is 32 words, enough for up to 16 interrupts. for more interrupts, adjust the alignment by rounding up to the next power of two. for example, if you require 21 interrupts, the alignment must be on a 64-word boundary because the required table size is 37 words, and the next power of two is 64. table alignment requirements mean that bits[6:0] of the table offset are always zero. 31 30 29 28 27 26 25 24 reserved tbloff 23 22 21 20 19 18 17 16 tbloff 15 14 13 12 11 10 9 8 tbloff 76543210 tbloff reserved
171 11011a?atarm?04-oct-10 sam3n 10.21.6 application interrupt and reset control register the aircr provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. see the register summary in table 10-30 on page 164 and table 10-33 on page 191 for its attributes. to write to this regi ster, you must write 0x05fa to the vectkey field, otherwise the processor ignores the write. the bit assignments are: ? vectkeystat register key: reads as 0xfa05 ? vectkey register key: on writes, write 0x5fa to vectkey, otherwise the write is ignored. ? endianess ro data endianness bit: 0 = little-endian endianess is set from the bigend configuration signal during reset. ?prigroup r/w interrupt priority grouping field. this field determin es the split of group priority from subpriority, see ?binary point? on page 172 . ? sysresetreq wo system reset request: 0 = no effect 1 = asserts a proc_reset_signal. this is intended to force a large system reset of all major components except for debug. this bit reads as 0. 31 30 29 28 27 26 25 24 on read: vectkeystat, on write: vectkey 23 22 21 20 19 18 17 16 on read: vectkeystat, on write: vectkey 15 14 13 12 11 10 9 8 endianess reserved prigroup 76543210 reserved sysresetreq vectclr- active vectreset
172 11011a?atarm?04-oct-10 sam3n ? vectclractive wo reserved for debug use. this bit reads as 0. when writing to the register you must write 0 to this bit, otherwise behavior is unpredictable. ? vectreset wo reserved for debug use. this bit reads as 0. when writing to the register you must write 0 to this bit, otherwise behavior is unpredictable. 10.21.6.1 binary point the prigroup field indicates the position of the binary point that splits the pri_ n fields in the interrupt priority registers into separate group priority and subpriority fields. table 10-31 shows how the prigroup value controls this split. determining preemption of an exception uses only the group priority field, see ?interrupt priority grouping? on page 68 . table 10-31. priority grouping interrupt priority level value, pri_ n [7:0] number of prigroup binary point (1) 1. pri_ n [7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a sub- priority field bit. group priority bits subpriority bits group priorities subpriorities b011 bxxxx.0000 [7:4] none 16 1 b100 bxxx.y0000 [7:5] [4] 8 2 b101 bxx.yy0000 [7:6] [5:4] 4 4 b110 bx.yyy0000 [7] [6:4] 2 8 b111 b.yyyy0000 none [7:4] 1 16
173 11011a?atarm?04-oct-10 sam3n 10.21.7 system control register the scr controls features of entry to and exit from low power state. see the register summary in table 10-30 on page 164 for its attributes. the bit assignments are: ? sevonpend send event on pending bit: 0 = only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 1 = enabled events and all interrupts, including disabled interrupts, can wakeup the processor. when an event or interrupt enters pending state, the event si gnal wakes up the processor from wfe. if the processor is not waiting for an event, the event is registered and affects the next wfe. the processor also wakes up on execution of an sev instruction or an external event. ? sleepdeep controls whether the processor uses sleep or deep sleep as its low power mode: 0 = sleep 1 = deep sleep. ? sleeponexit indicates sleep-on-exit when returning from handler mode to thread mode: 0 = do not sleep when returning to thread mode. 1 = enter sleep, or deep sleep, on return from an isr. setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 76543210 reserved sevonpend reserved sleepdeep sleeonexit reserved
174 11011a?atarm?04-oct-10 sam3n 10.21.8 configuration and control register the ccr controls entry to thread mode and enables: ? the handlers for hard fault and faults e scalated by faultmask to ignore bus faults ? trapping of divide by zero and unaligned accesses ? access to the stir by unprivileged software, see ?software trigger interrupt register? on page 161 . see the register summary in table 10-30 on page 164 for the ccr attributes. the bit assignments are: ? stkalign indicates stack alignment on exception entry: 0 = 4-byte aligned 1 = 8-byte aligned. on exception entry, the processor uses bit[9] of the stacked psr to indicate the stack alignment. on return from the excep- tion it uses this stacked bit to restore the correct stack alignment. ? bfhfnmign enables handlers with priority -1 or -2 to ignore data bus faul ts caused by load and store instructions. this applies to the hard fault and faultmask escalated handlers: 0 = data bus faults caused by load and store instructions cause a lock-up 1 = handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. set this bit to 1 only when the handler and its data are in absolutely safe memory. the normal use of this bit is to probe sys- tem devices and bridges to detect control path problems and fix them. ? div_0_trp enables faulting or halting when the processor executes an sdiv or udiv instruction with a divisor of 0: 0 = do not trap divide by 0 1 = trap divide by 0. when this bit is set to 0,a divide by zero returns a quotient of 0. ? unalign_trp enables unaligned access traps: 0 = do not trap unaligned halfword and word accesses 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved stkalign bfhfnmign 76543210 reserved div_0_trp unalign_t rp reserved usersetm pend nonbaset hrdena
175 11011a?atarm?04-oct-10 sam3n 1 = trap unaligned halfword and word accesses. if this bit is set to 1, an una ligned access generates a usage fault. unaligned ldm, stm, ldrd, and strd in structions always fault irrespective of whether unalign_trp is set to 1. ? usersetmpend enables unprivileged software access to the stir, see ?software trigger interrupt register? on page 161 : 0 = disable 1 = enable. ? nonebasethrdena indicates how the processor enters thread mode: 0 = processor can enter thread mode on ly when no exception is active. 1 = processor can enter thread mode from any level under the control of an exc_return value, see ?exception return? on page 70 .
176 11011a?atarm?04-oct-10 sam3n 10.21.9 system handler priority registers the shpr1-shpr3 registers set the priority level, 0 to 15 of the exception handlers that have configurable priority. shpr1-shpr3 are byte accessible. see the register summary in table 10-30 on page 164 for their attributes. the system fault handlers and the priority field and register for each handler are: each pri_n field is 8 bits wide, but the proc essor implements only bits[7:4] of each field, and bits[3:0] read as zero and ignore writes. table 10-32. system fault handler priority fields handler field register description memory management fault pri_4 ?system handler priority register 1? on page 177 bus fault pri_5 usage fault pri_6 svcall pri_11 ?system handler priority register 2? on page 178 pendsv pri_14 ?system handler priority register 3? on page 178 systick pri_15
177 11011a?atarm?04-oct-10 sam3n 10.21.9.1 system handler priority register 1 the bit assignments are: ?pri_7 reserved ?pri_6 priority of system handler 6, usage fault ?pri_5 priority of system handler 5, bus fault ?pri_4 priority of system handler 4, memory management fault 31 30 29 28 27 26 25 24 pri_7: reserved 23 22 21 20 19 18 17 16 pri_6 15 14 13 12 11 10 9 8 pri_5 76543210 pri_4
178 11011a?atarm?04-oct-10 sam3n 10.21.9.2 system handler priority register 2 the bit assignments are: ?pri_11 priority of system handler 11, svcall 10.21.9.3 system handler priority register 3 the bit assignments are: ?pri_15 priority of system handler 15, systick exception ?pri_14 priority of system handler 14, pendsv 31 30 29 28 27 26 25 24 pri_11 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 76543210 reserved 31 30 29 28 27 26 25 24 pri_15 23 22 21 20 19 18 17 16 pri_14 15 14 13 12 11 10 9 8 reserved 76543210 reserved
179 11011a?atarm?04-oct-10 sam3n 10.21.10 system handler control and state register the shcsr enables the system handlers, and indicates: ? the pending status of the bus fault, memory management fault, and svc exceptions ? the active status of the system handlers. see the register summary in table 10-30 on page 164 for the shcsr attributes. the bit assign- ments are: ? usgfaultena usage fault enable bit, set to 1 to enable (1) ? busfaultena bus fault enable bit, set to 1 to enable (3) ? memfaultena memory management fault enable bit, set to 1 to enable (3) ? svcallpended svc call pending bit, reads as 1 if exception is pending (2) ? busfaultpended bus fault exception pending bit, reads as 1 if exception is pending (2) ? memfaultpended memory management fault exception pending bit, reads as 1 if exception is pending (2) ? usgfaultpended usage fault exception pending bit, reads as 1 if exception is pending (2) ? systickact systick exception active bit, reads as 1 if exception is active (3) ? pendsvact pendsv exception active bit, reads as 1 if exception is active 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved usgfaultena busfaultena memfaultena 15 14 13 12 11 10 9 8 svcallpende d busfaultpend ed memfaultpen ded usgfaultpend ed systickact pendsvact reserved monitoract 76543210 svcallavct reserved usgfaultact reserved busfaultact memfaultact 1. enable bits, set to 1 to enable the exception, or set to 0 to disable the exception. 2. pending bits, read as 1 if the exception is pending, or as 0 if it is not pending. you can wr ite to these bits to change the pending status of the exceptions. 3. active bits, read as 1 if the exception is active, or as 0 if it is not active. you can write to these bits to change the act ive status of the exceptions, but see the caution in this section.
180 11011a?atarm?04-oct-10 sam3n ? monitoract debug monitor active bit, reads as 1 if debug monitor is active ? svcallact svc call active bit, reads as 1 if svc call is active ?usgfaultact usage fault exception active bit, reads as 1 if exception is active ? busfaultact bus fault exception active bit, reads as 1 if exception is active ? memfaultact memory management fault exception active bit, reads as 1 if exception is active if you disable a system handler and the corresponding fault occurs, the processor treats the fault as a hard fault. you can write to this register to change the pending or active status of system exceptions. an os kernel can write to the active bits to perform a context switch that changes the current exception type. ? software that changes the value of an active bit in this register without correct adjustment to the stacked content can cause the processor to generate a fault exception. ensure software that writes to this register retains and subsequently restores the current active status. ? after you have enabled the system handlers, if you have to change the value of a bit in this register you must use a read- modify-write procedure to ensure that you change only the required bit.
181 11011a?atarm?04-oct-10 sam3n 10.21.11 configurable fault status register the cfsr indicates the cause of a memory management fault, bus fault, or usage fault. see the register summary in table 10-30 on page 164 for its attributes. the bit assignments are: the following subsections describe the subregisters that make up the cfsr: ? ?memory management fault status register? on page 182 ? ?bus fault status register? on page 183 ? ?usage fault status register? on page 185 . the cfsr is byte accessible. you can access the cfsr or its subregisters as follows: ? access the complete cfsr with a word access to 0xe000ed28 ? access the mmfsr with a byte access to 0xe000ed28 ? access the mmfsr and bf sr with a halfword access to 0xe000ed28 ? access the bfsr with a byte access to 0xe000ed29 ? access the ufsr with a half word access to 0xe000ed2a. 31 30 29 28 27 26 25 24 usage fault status register: ufsr 23 22 21 20 19 18 17 16 usage fault status register: ufsr 15 14 13 12 11 10 9 8 bus fault status register: bfsr 76543210 memory management fault status register: mmfsr
182 11011a?atarm?04-oct-10 sam3n 10.21.11.1 memory management fault status register the flags in the mmfsr indicate the cause of memory access faults. the bit assignments are: ?mmarvalid memory management fault address register (mmar) valid flag: 0 = value in mmar is not a valid fault address 1 = mmar holds a valid fault address. if a memory management fault occurs and is escalated to a har d fault because of priority, the hard fault handler must set this bit to 0. this prevents problems on return to a sta cked active memory management fault handler whose mmar value has been overwritten. ? mstkerr memory manager fault on stacking for exception entry: 0 = no stacking fault 1 = stacking for an exception entry has caused one or more access violations. when this bit is 1, the sp is still adjust ed but the values in the context area on the stack might be in correct. the processor has not written a fault address to the mmar. ? munstkerr memory manager fault on unstacking for a return from exception: 0 = no unstacking fault 1 = unstack for an exception return has caused one or more access violations. this fault is chained to the handler. this means that when this bit is 1, the original return sta ck is still present. the proce s- sor has not adjusted the sp from the failing return, and has not performed a new save. the processor has not written a fault address to the mmar. ?daccviol data access violation flag: 0 = no data access violation fault 1 = the processor attempted a load or store at a location that does not permit the operation. when this bit is 1, the pc value stacked for the exception return points to the faulting instruction. the processor has loaded the mmar with the address of the attempted access. ? iaccviol instruction access violation flag: 0 = no instruction access violation fault 1 = the processor attempted an instruction fetch from a location that does not permit execution. when this bit is 1, the pc value stacked for the exception return points to the faulting instruction. the processor has not written a fault address to the mmar. 76543210 mmarvalid reserved mstkerr munstkerr reserved daccviol iaccviol
183 11011a?atarm?04-oct-10 sam3n 10.21.11.2 bus fault status register the flags in the bfsr indicate the cause of a bus access fault. the bit assignments are: ?bfarvalid bus fault address register (bfar) valid flag: 0 = value in bfar is not a valid fault address 1 = bfar holds a valid fault address. the processor sets this bit to 1 after a bus fault where the address is known. other faults can set this bit to 0, such as a memory management fault occurring later. if a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set this bit to 0. this pre- vents problems if returning to a stacked active bus fault handler whose bfar value has been overwritten. ?stkerr bus fault on stacking for exception entry: 0 = no stacking fault 1 = stacking for an exception entry has caused one or more bus faults. when the processor sets this bit to 1, the sp is still adjusted but the values in the context area on the stack might be incor- rect. the processor does not write a fault address to the bfar. ? unstkerr bus fault on unstacking for a return from exception: 0 = no unstacking fault 1 = unstack for an exception return has caused one or more bus faults. this fault is chained to the handler. this means that when the processor sets this bit to 1, the original return stack is still present. the processor does not adjust th e sp from the failing return, does not pe rformed a new save, and does not write a fault address to the bfar. ? impreciserr imprecise data bus error: 0 = no imprecise data bus error 1 = a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. when the processor sets this bit to 1, it does not write a fault address to the bfar. this is an asynchronous fault. therefore, if it is detected when the priority of the current process is higher than the bus fau lt priority, the bus fault becomes pending and becomes active only when the processor returns from all higher priority pro- cesses. if a precise fault occurs before the processor enters the handler for t he imprecise bus faul t, the handler detects both impreciserr set to 1 and one of the precise fault status bits set to 1. 76543210 bfrvalid reserved stkerr unstkerr impreciserr preciserr ibuserr
184 11011a?atarm?04-oct-10 sam3n ? preciserr precise data bus error: 0 = no precise data bus error 1 = a data bus error has occurred, and the pc value stacked for the exception return points to the instruction that caused the fault. when the processor sets this bit is 1, it writes the faulting address to the bfar. ? ibuserr instruction bus error: 0 = no instruction bus error 1 = instruction bus error. the processor detects the instruction bus error on prefetching an instruction, but it sets the ibuserr flag to 1 only if it attempts to issue the faulting instruction. when the processor sets this bit is 1, it does not write a fault address to the bfar.
185 11011a?atarm?04-oct-10 sam3n 10.21.11.3 usage fault status register the ufsr indicates the cause of a usage fault. the bit assignments are: ?divbyzero divide by zero usage fault: 0 = no divide by zero fault, or divide by zero trapping not enabled 1 = the processor has executed an sdiv or udiv instruction with a divisor of 0. when the processor sets this bit to 1, the pc value stacked for the exception return points to the instruction that performed the divide by zero. enable trapping of divide by zero by setti ng the div_0_trp bit in the ccr to 1, see ?configuration and control register? on page 174 . ? unaligned unaligned access usage fault: 0 = no unaligned access fault, or unaligned access trapping not enabled 1 = the processor has made an unaligned memory access. enable trapping of unaligned accesses by setting the unalign_trp bit in the ccr to 1, see ?configuration and control register? on page 174 . unaligned ldm, stm, ldrd, and strd instructions always fault irrespective of the setting of unalign_trp. ?nocp no coprocessor usage fault. the processor does not support coprocessor instructions: 0 = no usage fault caused by attempting to access a coprocessor 1 = the processor has attempted to access a coprocessor. ?invpc invalid pc load usage fault, caused by an invalid pc load by exc_return: 0 = no invalid pc load usage fault 1 = the processor has attempted an illegal load of exc_return to the pc, as a result of an invalid context, or an invalid exc_return value. when this bit is set to 1, the pc value stacked for the exception return points to the instruction that tried to perform the il le- gal load of the pc. ?invstate invalid state usage fault: 0 = no invalid state usage fault 1 = the processor has attempted to execute an instru ction that makes illegal use of the epsr. 15 14 13 12 11 10 9 8 reserved divbyzero unaligned 76543210 reserved nocp invpc invstate undefinstr
186 11011a?atarm?04-oct-10 sam3n when this bit is set to 1, the pc value stacked for the excepti on return points to the instruction that attempted the illegal u se of the epsr. this bit is not set to 1 if an undefined instruct ion uses the epsr. ? undefinstr undefined instruction usage fault: 0 = no undefined instruction usage fault 1 = the processor has attempted to execute an undefined instruction. when this bit is set to 1, the pc value stacked for the exception return points to the undefined instruction. an undefined instruction is an instruction that the processor cannot decode. the ufsr bits are sticky. this means as on e or more fault occurs, the associated bits are set to 1. a bit that is set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset.
187 11011a?atarm?04-oct-10 sam3n 10.21.12 hard fault status register the hfsr gives information about events that activate the hard fault handler. see the register summary in table 10-30 on page 164 for its attributes. this register is read, write to clear. this means t hat bits in the register read normally , but writing 1 to any bit clears that bit to 0. the bit assignments are: ? debugevt reserved for debug use. when writing to the register you must write 0 to this bit, otherwise behavior is unpredictable. ?forced indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either because of priority or because it is disabled: 0 = no forced hard fault 1 = forced hard fault. when this bit is set to 1, the hard fault handler must read the other fault status registers to find the cause of the fault. ? vecttbl indicates a bus fault on a vector table read during exception processing: 0 = no bus fault on vector table read 1 = bus fault on vector table read. this error is always handled by the hard fault handler. when this bit is set to 1, the pc value stacked for the exception return points to the instruction that was preempted by the exception. the hfsr bits are sticky. this means as on e or more fault occurs, the associated bits are set to 1. a bit that is set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset. 31 30 29 28 27 26 25 24 debugevt forced reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 76543210 reserved vecttbl reserved
188 11011a?atarm?04-oct-10 sam3n 10.21.13 memory management fault address register the mmfar contains the address of the location that generated a memory management fault. see the register summary in table 10-30 on page 164 for its attributes. the bit assignments are: ? address when the mmarvalid bit of the mmfsr is set to 1, this field holds the address of the location that generated the memory management fault when an unaligned access faults, the address is the actual address that faulted. because a single read or write instruction can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size. flags in the mmfsr indicate the cause of the fault, and whether the value in the mmfar is valid. see ?memory manage- ment fault status register? on page 182 . 31 30 29 28 27 26 25 24 address 23 22 21 20 19 18 17 16 address 15 14 13 12 11 10 9 8 address 76543210 address
189 11011a?atarm?04-oct-10 sam3n 10.21.14 bus fault address register the bfar contains the address of the location that generated a bus fault. see the register sum- mary in table 10-30 on page 164 for its attributes. the bit assignments are: ? address when the bfarvalid bit of the bfsr is set to 1, this field holds the address of the location that generated the bus fault when an unaligned access faults the address in the bfar is the one requested by the instruction, even if it is not the address of the fault. flags in the bfsr indicate the cause of the fault, and whether the value in the bfar is valid. see ?bus fault status regis- ter? on page 183 . 31 30 29 28 27 26 25 24 address 23 22 21 20 19 18 17 16 address 15 14 13 12 11 10 9 8 address 76543210 address
190 11011a?atarm?04-oct-10 sam3n 10.21.15 system control block design hints and tips ensure software uses aligned accesses of the co rrect size to access the system control block registers: ? except for the cfsr and shpr1-shpr3, it must use aligned word accesses ? for the cfsr and shpr1-shpr3 it can use byte or aligned halfword or word accesses. the processor does not support unaligned accesses to system control block registers. in a fault handler. to determine the true faulting address: ? read and save the mmfar or bfar value. ? read the mmarvalid bit in the mmfsr, or the bfarvalid bit in the bfsr. the mmfar or bfar address is valid only if this bit is 1. software must follow this sequence because another higher priority exception might change the mmfar or bfar value. for example, if a higher priority handler preempts the current fault han- dler, the other fault might change the mmfar or bfar value.
191 11011a?atarm?04-oct-10 sam3n 10.22 system timer, systick the processor has a 24-bit system timer, systic k, that counts down from the reload value to zero, reloads (wraps to) the value in the load register on the next clock edge, then counts down on subsequent clocks. when the processor is halted for debugging the counter does not decrement. the system timer registers are: table 10-33. system timer registers summary address name type required privilege reset value description 0xe000e010 ctrl rw privileged 0x00000004 ?systick control and status register? on page 192 0xe000e014 load rw privileged 0x00000000 ?systick reload value register? on page 193 0xe000e018 val rw privileged 0x00000000 ?systick current value register? on page 194 0xe000e01c calib ro privileged 0x0002904 (1) ?systick calibration value register? on page 195 1. systick calibration value.
192 11011a?atarm?04-oct-10 sam3n 10.22.1 systick control and status register the systick ctrl register enables the systick features. see the register summary in table 10- 33 on page 191 for its attributes. the bit assignments are: ? countflag returns 1 if timer counted to 0 since last time this was read. ? clksource indicates the clock source: 0 = mck/8 1 = mck ?tickint enables systick exception request: 0 = counting down to zero does not assert the systick exception request 1 = counting down to zero to asserts the systick exception request. software can use countflag to determine if systick has ever counted to zero. ? enable enables the counter: 0 = counter disabled 1 = counter enabled. when enable is set to 1, the counter loads the reload value from the load register and then counts down. on reach- ing 0, it sets the countflag to 1 and optionally asserts the systick depending on the value of tickint. it then loads the reload value again, and begins counting. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved countflag 15 14 13 12 11 10 9 8 reserved 76543210 reserved clksource tickint enable
193 11011a?atarm?04-oct-10 sam3n 10.22.2 systick reload value register the load register specifies the start value to load into the val register. see the register sum- mary in table 10-33 on page 191 for its attributes. the bit assignments are: ?reload value to load into the val register when the counter is enabled and when it reaches 0, see ?calculating the reload value? . 10.22.2.1 calculating the reload value the reload value can be any value in the range 0x00000001-0x00ffffff. a start value of 0 is possible, but has no effect because the sy stick exception request and countflag are acti- vated when counting from 1 to 0. the reload value is calculated according to its use: ? to generate a multi-shot timer with a period of n processor clock cycles, use a reload value of n-1. for example, if the systick interrupt is required every 100 clock pulses, set reload to 99. ? to deliver a single systick interrupt after a delay of n processor clock cycles, use a reload of value n. for example, if a systick interrupt is required after 400 clock pulses, set reload to 400. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reload 15 14 13 12 11 10 9 8 reload 76543210 -reload
194 11011a?atarm?04-oct-10 sam3n 10.22.3 systick current value register the val register contains the current value of the systick counter. see the register summary in table 10-33 on page 191 for its attributes. the bit assignments are: ? current reads return the current value of the systick counter. a write of any value clears the field to 0, and also clears the systick ctrl.countflag bit to 0. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 current 15 14 13 12 11 10 9 8 current 76543210 current
195 11011a?atarm?04-oct-10 sam3n 10.22.4 systick calibration value register the calib register indicates the systick calib ration properties. see the register summary in table 10-33 on page 191 for its attributes. the bit assignments are: ?noref reads as zero. ?skew reads as zero ?tenms read as 0x0002904. the systick calibration value is fixed at 0x0002904 (10500), which allows the generation of a time base of 1 ms with systick clock at 6 mhz (48/8 = 6 mhz) 10.22.5 systick design hints and tips the systick counter runs on the processor clock. if this clock signal is stopped for low power mode, the systick counter stops. ensure software uses aligned word acce sses to access the systick registers. 31 30 29 28 27 26 25 24 noref skew reserved 23 22 21 20 19 18 17 16 tenms 15 14 13 12 11 10 9 8 tenms 76543210 tenms
196 11011a?atarm?04-oct-10 sam3n 10.23 glossary this glossary describes some of the terms used in technical documents from arm. abort a mechanism that indicates to a processor that the value associated with a memory access is invalid. an abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction or data memory. aligned a data item stored at an address that is divisible by the number of bytes that defines the data size is said to be aligned. aligned words and halfwords have addresses that are divisible by four and two respectively. the terms word-aligned and halfword-aligned therefore stipulate addresses that are divisible by four and two respectively. banked register a register that has multiple ph ysical copies, where the state of the processor determines which copy is used. the stack pointer, sp (r13) is a banked register. base register in instruction descriptions, a register specified by a load or store instruction that is used to hold the base value for the instruction?s address calculation. depending on the instruction and its addressing mode, an offset can be added to or subtracted from the base register value to form the address that is sent to memory. see also ?index register? ?little-endian (le)? see also ?little-endian memory? .breakpoint a breakpoint is a mechanism provided by debuggers to identify an instruction at which program execution is to be halted. breakpoints are in serted by the programmer to enable inspection of register contents, memory locations, variable values at fixed points in the program execution to test that the program is operating correctly. breakpoints are removed after the program is suc- cessfully tested. . condition field a four-bit field in an instruction that specifies a condition under which the instruction can execute. conditional execution if the condition code flags indicate that the co rresponding condition is true when the instruction starts executing, it executes normally. otherwise, the instruction does nothing. context the environment that each process operates in for a multitasking operating system. in arm pro- cessors, this is limited to mean the physical address range that it can access in memory and the associated memory access permissions. coprocessor a processor that supplements the main pr ocessor. cortex-m3 does not support any coprocessors.
197 11011a?atarm?04-oct-10 sam3n debugger a debugging system that includes a program, used to detect, locate , and correct so ftware faults, together with custom hardware that supports software debugging. direct memory access (dma) an operation that accesses main memory directly, without the processor performing any accesses to the data concerned. doubleword a 64-bit data item. the contents are taken as being an unsigned integer unless otherwise stated. doubleword-aligned a data item having a memory address that is divisible by eight. endianness byte ordering. the scheme that determines the order that successive bytes of a data word are stored in memory. an aspect of the system?s memory mapping. see also ?little-endian (le)? exception an event that interrupts program execution. when an exception occurs, the processor suspends the normal program flow and starts execution at the address indicated by the corresponding exception vector. the indicated address contains the first instruction of the handler for the exception. an exception can be an interrupt request, a fault, or a software-generated system exception. faults include attempting an invalid memory access, attempting to execute an instruction in an invalid processor state, and attempting to execute an undefined instruction. exception service routine see ?interrupt handler? . exception vector see ?interrupt vector? . flat address mapping a system of organizing memory in which each phy sical address in the memory space is the same as the corresponding virtual address. halfword a 16-bit data item. illegal instruction an instruction that is architecturally undefined. implementation-defined the behavior is not architecturally defined, but is defined and documented by individual implementations. implementation-specific
198 11011a?atarm?04-oct-10 sam3n the behavior is not architecturally defined, and does not have to be documented by individual implementations. used when there are a number of implementation options available and the option chosen does not affe ct software compatibility. index register in some load and store instruction descriptions, the value of this register is used as an offset to be added to or subtracted from the base register value to form the address that is sent to mem- ory. some addressing modes optionally enable the index register value to be shifted prior to the addition or subtraction. see also ?base register? instruction cycle count the number of cycles that an instruction oc cupies the execute stage of the pipeline. interrupt handler a program that control of the processor is passed to when an interrupt occurs. interrupt vector one of a number of fixed addresses in low memory, or in high memory if high vectors are config- ured, that contains the first instruction of the corresponding interrupt handler. little-endian (le) byte ordering scheme in which bytes of increas ing significance in a data word are stored at increasing addresses in memory. see also ??little-endian (le)? see also ?little-endian memory? .breakpoint? , ?.? , ?endianness? . little-endian memory memory in which: a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at that address a byte at a halfword-aligned address is the least significant byte within the halfword at that address. . load/store architecture a processor architecture where data-processing operations only operate on register contents, not directly on memory contents. prefetching in pipelined processors, the process of fetching instructions from memory to fill up the pipeline before the preceding instructions have finished executing. prefetching an instruction does not mean that the instruction has to be executed. read reads are defined as memory oper ations that have the semantics of a load. reads include the thumb instructions ldm, ldr, ldrsh, ldrh, ldrsb, ldrb, and pop.
199 11011a?atarm?04-oct-10 sam3n region a partition of memory space. reserved a field in a control register or instruction format is reserved if the field is to be defined by the implementation, or produces unpredictable results if the contents of the field are not zero. these fields are reserved for use in future extensions of the architecture or are implementation-specific. all reserved bits not used by the implement ation must be written as 0 and read as 0. should be one (sbo) write as 1, or all 1s for bit fields, by software. writing as 0 produces unpredictable results. should be zero (sbz) write as 0, or all 0s for bit fields, by software. writing as 1 produces unpredictable results. should be zero or preserved (sbzp) write as 0, or all 0s for bit fields, by software , or preserved by writing the same value back that has been previously read from the same field on the same processor. thread-safe in a multi-tasking environment, thread-safe functions use safeguard mechanisms when access- ing shared resources, to ensure correct operation without the risk of shared access conflicts. thumb instruction one or two halfwords that specify an operation for a processor to perform. thumb instructions must be halfword-aligned. unaligned a data item stored at an address that is not divisible by the number of bytes that defines the data size is said to be unaligned. for example, a word stored at an address that is not divisible by four. undefined indicates an instruction that generates an undefined instruction exception. unpredictable (unp) you cannot rely on the behavior. unpredictable behavior must not represent security holes. unpredictable behavior must not halt or hang the processor, or any parts of the system. warm reset also known as a core reset. initializes the majori ty of the processor excluding the debug control- ler and debug logic. this type of reset is useful if you are using the debugging features of a processor. word a 32-bit data item. write writes are defined as operations that have the semantics of a store. writes include the thumb instructions stm, str, strh, strb, and push.
200 11011a?atarm?04-oct-10 sam3n
201 11011a?atarm?04-oct-10 sam3n 11. debug and test features 11.1 description the sam3 series microcontrollers feature a number of complementary debug and test capabilities. the serial wire/jtag debug port (swj-dp) combining a serial wire debug port (sw-dp) and jtag debug(jtag-dp) port is used for standard debugging functions, such as downloading code and single-stepping through prog rams. it also embeds a serial wire trace. 11.2 embedded characteristics ? debug access to all memory and registers in the system, including cortex-m3 register bank when the core is running, halted, or held in reset. ? serial wire debug port (sw-dp) and serial wire jtag debug port (swj-dp) debug access ? flash patch and breakpoint (fpb) unit for implementing breakpoints and code patches ? data watchpoint and trace (dwt) unit for implementing watchpoints, data tracing, and system profiling ? instrumentation trace macrocell (itm) for support of printf style debugging ? ieee1149.1 jtag boundary-can on all digital pins figure 11-1. debug and test block diagram tst tms tck/swclk tdi jtagsel tdo/traceswo boundary ta p swj-dp reset and test por
202 11011a?atarm?04-oct-10 sam3n 11.3 application examples 11.3.1 debug environment figure 11-2 shows a complete debug environment example. the swj-dp interface is used for standard debugging functions, such as downloading code and single-stepping through the pro- gram and viewing core and peripheral registers. figure 11-2. application debug environment example 11.3.2 test environment figure 11-3 shows a test environment example (jtag boundary scan). test vectors are sent and interpreted by the tester. in this example, the ?board in test? is designed using a number of jtag-compliant devices. these devices can be connected to form a single scan chain. s am 3 ho s t de bu gger pc s am 3 - bas ed applic a tion bo a rd s wj-dp connector s wj-dp em u l a tor/pro b e
203 11011a?atarm?04-oct-10 sam3n figure 11-3. application test environment example 11.4 debug and test pin description chip 2 chip n chip 1 s am 3 s am 3 - bas ed applic a tion bo a rd in te s t jtag connector te s ter te s t ad a ptor jtag pro b e table 11-1. debug and test signal list signal name function type active level reset/test nrst microcontroller reset input/output low tst test select input swd/jtag tck/swclk test clock/serial wire clock input tdi test data in input tdo/traceswo test data out/trace asynchronous data out output tms/swdio test mode select/serial wire input/output input jtagsel jtag selection input high
204 11011a?atarm?04-oct-10 sam3n 11.5 functional description 11.5.1 test pin one dedicated pin, tst, is used to define the device operating mode. when this pin is at low level during power-up, the device is in normal operating mode. when at high level, the device is in test mode or ffpi mode. the tst pin integrates a permanent pull-down resistor of about 15 k , so that it can be left unconnected for normal operation. note that when setting the tst pin to low or high level at power up, it must remain in the same state during the duration of the whole operation. 11.5.2 debug architecture figure 11-4 shows the debug architecture used in the sam3. the cortex-m3 embeds four func- tional units for debug: ? swj-dp (serial wire/jtag debug port) ? fpb (flash patch breakpoint) ? dwt (data watchpoint and trace) ? itm (instrumentation trace macrocell) ? tpiu (trace port interface unit) the debug architecture information that follows is mainly dedicated to developers of swj-dp emulators/probes and debugging tool vendors for cortex m3-based microcontrollers. for further details on swj-dp see the cortex m3 technical reference manual. figure 11-4. debug architecture 11.5.3 serial wire/jtag debug port (swj-dp) the cortex-m3 embeds a swj-dp debug port which is the standard coresight ? debug port. it combines serial wire debug port (sw-dp), from 2 to 3 pins and jtag debug port(jtag-dp), 5 pins. by default, the jtag debug port is active. if the host debugger wants to switch to the serial wire debug port, it must provide a dedicated jtag sequence on tms/swdio and tck/swclk which disables jtag-dp and enables sw-dp. 4 watchpoints pc sampler data address sampler data sampler interrupt trace cpu statistics dwt 6 breakpoints fpb software trace 32 channels time stamping itm swd/jtag swj-dp swo trace tpiu
205 11011a?atarm?04-oct-10 sam3n when the serial wire debug port is active, tdo/traceswo can be used for trace. the asyn- chronous trace output (traceswo) is multiplexed with tdo. so the asynchronous trace can only be used with sw-dp, not jtag-dp. sw-dp or jtag-dp mode is select ed when jtagsel is low. it is not possible to switch directly between swj-dp and jtag boundary scan operations. a chip reset must be performed after jtagsel is changed. 11.5.3.1 sw-dp and jtag-dp selection mechanism debug port selection mechanism is done by sending specific swdiotms sequence. the jtag- dp is selected by default after reset. ? switch from jtag-dp to sw-dp. the sequence is: ? send more than 50 swclktck cycles with swdiotms = 1 ? send the 16-bit sequence on swdiotms = 0111100111100111 (0x79e7 msb first) ? send more than 50 swclktck cycles with swdiotms = 1 ? switch from swd to jtag. the sequence is: ? send more than 50 swclktck cycles with swdiotms = 1 ? send the 16-bit sequence on swdiotms = 0011110011100111 (0x3ce7 msb first) ? send more than 50 swclktck cycles with swdiotms = 1 11.5.4 fpb (flash patch breakpoint) the fpb: ? implements hardware breakpoints ? patches code and data from code space to system space. the fpb unit contains: ? two literal comparators for matching against literal loads from code space, and remapping to a corresponding area in system space. ? six instruction comparators for matching against instruction fetches from code space and remapping to a corresponding area in system space. ? alternatively, comparators can also be configured to generate a breakpoint instruction to the processor core on a match. 11.5.5 dwt (data watchpoint and trace) the dwt contains four comparators which can be configured to generate the following: ? pc sampling packets at set intervals ? pc or data watchpoint packets table 11-2. swj-dp pin list pin name jtag port serial wire debug port tms/swdio tms swdio tck/swclk tck swclk tdi tdi - tdo/traceswo tdo traceswo (optional: trace)
206 11011a?atarm?04-oct-10 sam3n ? watchpoint event to halt core the dwt contains counters for the items that follow: ? clock cycle (cyccnt) ? folded instructions ? load store unit (lsu) operations ? sleep cycles ? cpi (all instruction cycles except for the first cycle) ? interrupt overhead 11.5.6 itm (instrumentation trace macrocell) the itm is an application driven trace source that supports printf style debugging to trace oper- ating system (os) and application events, and emits diagnostic system information. the itm emits trace information as packets which can be generated by three different sources with sev- eral priority levels: ? software trace : software can write directly to itm stimulus registers. this can be done thanks to the ?printf? function. for more information, refer to section 11.5.6.1 ?how to configure the itm? . ? hardware trace : the itm emits packets generated by the dwt. ? time stamping : timestamps are emitted relative to packets. the itm contains a 21-bit counter to generate the timestamp. 11.5.6.1 how to configure the itm the following example describes how to output trace data in asynchronous trace mode. ? configure the tpiu for asynchronous trace mode (refer to section 11.5.6.3 ?5.4.3. how to configure the tpiu? ) ? enable the write accesses into the itm registers by writing ?0xc5acce55? into the lock access register (address: 0xe0000fb0) ? write 0x00010015 into the trace control register: ?enable itm ? enable synchronization packets ? enable swo behavior ? fix the atb id to 1 ? write 0x1 into the trace enable register: ? enable the stimulus port 0 ? write 0x1 into the trace privilege register: ? stimulus port 0 only accessed in privileged mode (clearing a bit in this register will result in the corresponding stimulus port being accessible in user mode.) ? write into the stimulus port 0 register: tpiu (trace port interface unit) the tpiu acts as a bridge between the on-chip trace data and the instruction trace macro- cell (itm). the tpiu formats and transmits trace data off-chip at frequencies asynchronous to the core.
207 11011a?atarm?04-oct-10 sam3n 11.5.6.2 asynchronous mode the tpiu is configured in asynchronous mode, trace data are output using the single trac- eswo pin. the traceswo signal is multiplexed with the tdo signal of the jtag debug port. as a consequence, asynchronous trace mode is only available when the serial wire debug mode is selected since tdo signal is used in jtag debug mode. two encoding formats are avail able for the single pin output: ? manchester encoded stream. this is the reset value. ? nrz_based uart byte structure 11.5.6.3 5.4.3. how to configure the tpiu this example only concerns the asynchronous trace mode. ? set the trcena bit to 1 into the debug exception and monitor register (0xe000edfc) to enable the use of trace and debug blocks. ? write 0x2 into the selected pin protocol register ? select the serial wire output ? nrz ? write 0x100 into the formatter and flush control register ? set the suitable clock prescaler value into the async clock prescaler register to scale the baud rate of the asynchronous output (this can be done automatically by the debugging tool). 11.5.7 ieee ? 1149.1 jtag boundary scan ieee 1149.1 jtag boundary scan allows pin-level access independent of the device packaging technology. ieee 1149.1 jtag boundary scan is enabled when tst, jtagsel are high while fwup and nrstb are tied low during power-up and must be kept in this state during the whole boundary scan operation. vddcore must be externally supplied between 1.8v and 1.95v. the sample, extest and bypass functions are implement ed. in swd/jtag debug mode, the arm pro- cessor responds with a non-jtag chip id that identifies the processor. this is not ieee 1149.1 jtag-compliant. it is not possible to switch directly betw een jtag boundary scan and swj debug port opera- tions. a chip reset must be perf ormed after jtagsel is changed. a boundary-scan descriptor language (bsdl) file is provided on atmel?s web site to set up the test. 11.5.7.1 jtag boundary-scan register the boundary-scan register (bsr) contains a num ber of bits which correspond to active pins and associated control signals. each sam3 input/output pin corresponds to a 3-bit register in the bsr. the output bit con- tains data that can be forced on the pad. the input bit facilitates the observability of data applied to the pad. the control bit selects the direction of the pad. for more information, please refer to bdsl files available for the sam3 series.
208 11011a?atarm?04-oct-10 sam3n 11.5.8 id code register access: read-only ? version[31:28]: product version number set to 0x0. ? part number[27:12]: product part number ? manufacturer identity[11:1] set to 0x01f. ? bit[0] required by ieee std. 1149.1. set to 0x1. 31 30 29 28 27 26 25 24 version part number 23 22 21 20 19 18 17 16 part number 15 14 13 12 11 10 9 8 part number manufacturer identity 76543210 manufacturer identity 1 chip name chip id sam3n 0x05b2e chip name jtag id code sam3n 0x05b2e03f
209 11011a?atarm?04-oct-10 sam3n 12. reset coontroller (rstc) 12.1 description the reset controller (rstc), based on power-on reset cells, handles all the resets of the sys- tem without any external components. it reports which reset occurred last. the reset controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 12.2 embedded characteristics the reset controller is based on a power-on-r eset cell, and a supply monitor on vddcore. the reset controller is capable to return to the software the source of the last reset, either a general reset, a wake-up reset, a software reset, a user reset or a watchdog reset. the reset controller controls the internal resets of the system a nd the nrst pin input/output. it is capable to shape a reset signal for the exter nal devices, simplifying to a minimum connection of a push-button on the nrst pin to implement a manual reset. the configuration of the reset controller is saved as supplied on vddio. 12.3 block diagram figure 12-1. reset controller block diagram nrst proc_nreset wd_fault periph_nreset slck reset state manager reset controller rstc_irq nrst manager exter_nreset nrst_out core_backup_reset wdrproc user_reset vddcore_nreset
210 11011a?atarm?04-oct-10 sam3n 12.4 functional description 12.4.1 reset controller overview the reset controller is made up of an nrst manager and a reset state manager. it runs at slow clock and generates the following reset signals: ? proc_nreset: processor reset line. it also resets the watchdog timer. ? periph_nreset: affects the whole set of embedded peripherals. ? nrst_out: drives the nrst pin. these reset signals are asserted by the reset cont roller, either on external events or on soft- ware action. the reset state manager controls the generation of reset signals and provides a signal to the nrst manager when an assertion of the nrst pin is required. the nrst manager shapes the nrst assertion du ring a programmable ti me, thus controlling external device resets. the reset controller mode register (rstc_mr), allowing the configuration of the reset con- troller, is powered with vddio, so that its configuration is saved as long as vddio is on. 12.4.2 nrst manager after power-up, nrst is an output during the erstl time period defined in the rstc_mr. when erstl has elapsed, the pin behaves as an input and all the system is held in reset if nrst is tied to gnd by an external signal. the nrst manager samples the nrst input pin and drives this pin low when required by the reset state manager. figure 12-2 shows the block diagram of the nrst manager. figure 12-2. nrst manager 12.4.2.1 nrst signal or interrupt the nrst manager samples the nrst pin at slow clock speed. when the line is detected low, a user reset is reported to the reset state manager. however, the nrst manager can be programmed to not trigger a reset when an assertion of nrst occurs. writing the bit ursten at 0 in rstc_mr disables the user reset trigger. the level of the pin nrst can be read at any ti me in the bit nrstl (nrst level) in rstc_sr. as soon as the pin nrst is asserted, the bit ur sts in rstc_sr is set. this bit clears only when rstc_sr is read. external reset timer ursts ursten erstl exter_nreset urstien rstc_mr rstc_mr rstc_mr rstc_sr nrstl nrst_out nrst rstc_irq other interrupt sources user_reset
211 11011a?atarm?04-oct-10 sam3n the reset controller can also be programmed to generate an interrupt instead of generating a reset. to do so, the bit urstien in rstc_mr must be written at 1. 12.4.2.2 nrst external reset control the reset state manager asserts the signal ext_nreset to assert the nrst pin. when this occurs, the ?nrst_out? signal is driven low by the nrst manager for a time programmed by the field erstl in rstc_mr. this assertion duration, named externa l_reset_length, lasts 2 (erstl+1) slow clock cycles. this gives the approximate duration of an assertion between 60 s and 2 seconds. note that erstl at 0 defines a two-cycle duration for the nrst pulse. this feature allows the reset controller to shape the nrst pin level, and thus to guarantee that the nrst line is driven low for a time compliant with potential external devices connected on the system reset. as the erstl field is within rstc_mr register, wh ich is backed-up, it can be used to shape the system power-up reset fo r devices requiring a lo nger startup time than the slow clock oscillator. 12.4.3 brownout manager the brownout manager is embedded within the supply controller, please refer to the product supply controller section for a detailed description. 12.4.4 reset states the reset state manager handles the different reset sources and generates the internal reset signals. it reports the reset status in the field rsttyp of the status register (rstc_sr). the update of the field rsttyp is performed when the processor reset is released. 12.4.4.1 general reset a general reset occurs when a power-on-reset is detected, a brownout or a voltage regulation loss is detected by the supply controller. the vddcore_nreset signal is asserted by the supply controller when a general reset occurs. all the reset signals are released and the field rsttyp in rstc_sr reports a general reset. as the rstc_mr is reset, the nrst line rise s 2 cycles after the v ddcore_nreset, as erstl defaults at value 0x0. figure 12-3 shows how the general reset affects the reset signals.
212 11011a?atarm?04-oct-10 sam3n figure 12-3. general reset state 12.4.4.2 backup reset a backup reset occurs when the chip returns from backup mode. the core_backup_reset signal is asserted by the supply controller when a backup reset occurs. the field rsttyp in rstc_sr is u pdated to report a backup reset. 12.4.4.3 user reset the user reset is entered when a low level is detected on the nrst pin and the bit ursten in rstc_mr is at 1. the nrst inpu t signal is resynchronized with slck to insure proper behav- ior of the system. the user reset is entered as soon as a low level is detected on nrst. the processor reset and the peripheral reset are asserted. the user reset is left when nrst rises, after a two-cycle resynchronization time and a 3-cycle processor startup. the processor clock is re-enabled as soon as nrst is confirmed high. when the processor reset signal is released, the rsttyp field of the status register (rstc_sr) is loaded with the value 0x4, indicating a user reset. the nrst manager guarantees that the nrst line is asserted for external_reset_length slow clock cycles, as programmed in the field erstl. how- ever, if nrst does not rise after extern al_reset_length because it is driven low externally, the internal reset lines remain asserted until nrst actually rises. slck periph_nreset proc_nreset nrst (nrst_out) external reset length = 2 cycles mck processor startup = 2 cycles backup_nreset any freq. rsttyp xxx 0x0 = general reset xxx
213 11011a?atarm?04-oct-10 sam3n figure 12-4. user reset state 12.4.4.4 software reset the reset controller offers several commands used to assert the different reset signals. these commands are performed by writing the control register (rstc_cr) with the following bits at 1: ? procrst: writing procrst at 1 resets the processor and the watchdog timer. ? perrst: writing perrst at 1 resets all the embedded peripherals, including the memory system, and, in particular, the remap command. the peripheral reset is generally used for debug purposes. except for debug purposes , perrst must always be used in conjunction with procrst (perrst and procrst set both at 1 simultaneously). ? extrst: writing extrst at 1 asserts low the nrst pin during a time defined by the field erstl in the mode register (rstc_mr). the software reset is entered if at least one of these bits is set by the software. all these com- mands can be performed independently or simultaneously. the software reset lasts 3 slow clock cycles. the internal reset signals are asserted as soon as the register write is performed. this is detected on the master clock (mck). they are released when the software reset is left, i.e.; syn- chronously to slck. if extrst is set, the nrst_out signal is asserted depending on the programming of the field erstl. however, the result ing falling edge on nrst does not lead to a user reset. if and only if the procrst bit is set, the reset controller reports the software status in the field rsttyp of the status register (rstc_sr). other software resets are not reported in rsttyp. as soon as a software operation is detected, the bit srcmp (software reset command in prog- ress) is set in the status register (rstc_sr). it is cleared as soon as the software reset is left. slck periph_nreset proc_nreset nrst nrst (nrst_out) >= external reset length mck processor startup = 2 cycles any freq. resynch. 2 cycles rsttyp any xxx resynch. 2 cycles 0x4 = user reset
214 11011a?atarm?04-oct-10 sam3n no other software reset can be performed while the srcmp bit is set, and writing any value in rstc_cr has no effect. figure 12-5. software reset 12.4.4.5 watchdog reset the watchdog reset is entered when a watc hdog fault occurs. this state lasts 3 slow clock cycles. when in watchdog reset, assertion of t he reset signals depends on the wdrproc bit in wdt_mr: ? if wdrproc is 0, the processor reset and the peripheral reset are asserted. the nrst line is also asserted, depending on the programming of the field erstl. however, the resulting low level on nrst does not result in a user reset state. ? if wdrproc = 1, only the processor reset is asserted. the watchdog timer is reset by the proc_nreset si gnal. as the watchdog fault always causes a processor reset if wdrsten is set, the watc hdog timer is always reset after a watchdog reset, and the watchdog is enabled by default and with a period set to a maximum. when the wdrsten in wdt_mr bit is reset, the watchdog fault has no impact on the reset controller. slck periph_nreset if perrst=1 proc_nreset if procrst=1 write rstc_cr nrst (nrst_out) if extrst=1 external reset length 8 cycles (erstl=2) mck processor startup = 2 cycles any freq. rsttyp any xxx 0x3 = software reset resynch. 1 cycle srcmp in rstc_sr
215 11011a?atarm?04-oct-10 sam3n figure 12-6. watchdog reset 12.4.5 reset state priorities the reset state manager manages the following priorities between the different reset sources, given in descending order: ? general reset ? backup reset ? watchdog reset ? software reset ? user reset particular cases are listed below: ? when in user reset: ? a watchdog event is impossible because the watchdog timer is being reset by the proc_nreset signal. ? a software reset is impossible, since the processor reset is being activated. ? when in software reset: ? a watchdog event has priority over the current state. ? the nrst has no effect. ? when in watchdog reset: ? the processor reset is active and so a software reset cannot be programmed. ? a user reset cannot be entered. only if wdrproc = 0 slck periph_nreset proc_nreset wd_fault nrst (nrst_out) external reset length 8 cycles (erstl=2) mck processor startup = 2 cycles any freq. rsttyp any xxx 0x2 = watchdog reset
216 11011a?atarm?04-oct-10 sam3n 12.4.6 reset controller status register the reset controller status register (rstc_sr) provides several status fields: ? rsttyp field: this field gives the type of the last reset, as explained in previous sections. ? srcmp bit: this field indicates that a software reset command is in progress and that no further software reset should be performed until the end of the current one. this bit is automatically cleared at the end of the current software reset. ? nrstl bit: the nrstl bit of the status register gives the level of the nrst pin sampled on each mck rising edge. ? ursts bit: a high-to-low transition of the nrst pin sets the ursts bit of the rstc_sr register. this transition is also detected on the master clock (mck) rising edge (see figure 12-7 ). if the user reset is disabled (ursten = 0) and if the interruption is enabled by the urstien bit in the rstc_mr register, the ursts bit triggers an interrupt. reading the rstc_sr status register resets the ursts bit and clears the interrupt. figure 12-7. reset controller status and interrupt mck nrst nrstl 2 cycle resynchronization 2 cycle resynchronization ursts read rstc_sr peripheral access rstc_irq if (ursten = 0) and (urstien = 1)
217 11011a?atarm?04-oct-10 sam3n 12.5 reset controller (rstc) user interface table 12-1. register mapping offset register name access reset 0x00 control register rstc_cr write-only - 0x04 status register rs tc_sr read-only 0x0000_0000 0x08 mode register rstc_mr read-write 0x0000 0001
218 11011a?atarm?04-oct-10 sam3n 12.5.1 reset controller control register name: rstc_cr address: 0x400e1400 access: write-only ? procrst: processor reset 0 = no effect. 1 = if key is correct, resets the processor. ? perrst: peripheral reset 0 = no effect. 1 = if key is correct, resets the peripherals. ? extrst: external reset 0 = no effect. 1 = if key is correct, asserts the nrst pin. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ? 76543210 ????extrstperrst?procrst
219 11011a?atarm?04-oct-10 sam3n 12.5.2 reset controller status register name: rstc_sr address: 0x400e1404 access: read-only ? ursts: user reset status 0 = no high-to-low edge on nrst happened since the last read of rstc_sr. 1 = at least one high-to-low transition of nrst has been detected since the last read of rstc_sr. ? rsttyp: reset type reports the cause of the last processor reset. r eading this rstc_sr does not reset this field. ? nrstl: nrst pin level registers the nrst pin level at master clock (mck). ? srcmp: software reset command in progress 0 = no software command is being performed by the reset controller. the reset controller is ready for a software command. 1 = a software reset command is being performed by the reset controller. the reset controller is busy. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ??????srcmpnrstl 15 14 13 12 11 10 9 8 ????? rsttyp 76543210 ???????ursts rsttyp reset type comments 0 0 0 general reset first power-up reset 0 0 1 backup reset return from backup mode 0 1 0 watchdog reset watchdog fault occurred 0 1 1 software reset processor re set required by the software 1 0 0 user reset nrst pin detected low
220 11011a?atarm?04-oct-10 sam3n 12.5.3 reset controller mode register name: rstc_mr address: 0x400e1408 access: read-write ? ursten: user reset enable 0 = the detection of a low level on the pin nrst does not generate a user reset. 1 = the detection of a low level on the pin nrst triggers a user reset. ? urstien: user reset interrupt enable 0 = usrts bit in rstc_sr at 1 has no effect on rstc_irq. 1 = usrts bit in rstc_sr at 1 asserts rstc_irq if ursten = 0. ? erstl: external reset length this field defines the external reset length. the external reset is asserted during a time of 2 (erstl+1) slow clock cycles. this allows assertion duration to be programmed between 60 s and 2 seconds. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? erstl 76543210 ? ? urstien ? ? ? ursten
221 11011a?atarm?04-oct-10 sam3n 221 11011a?atarm?04-oct-10 sam3n 13. real-time timer (rtt) 13.1 description the real-time timer is built around a 32-bit counter used to count roll-over events of the programmable16-bit prescaler which enables counting elapsed seconds from a 32 khz slow clock source. it generates a periodic interrupt and/or triggers an alarm on a programmed value. 13.2 embedded characteristics ? 32-bit free-running counter on prescaled slow clock ? 16-bit configurable prescaler ? interrupt on alarm 13.3 block diagram figure 13-1. real-time timer slck rtpres rttinc alms 16-bit divider 32-bit counter almv = crtv rtt_mr rtt_vr rtt_ar rtt_sr rttincien rtt_mr 0 10 almien rtt_int rtt_mr set set rtt_sr read rtt_sr reset reset rtt_mr reload rtt_alarm rttrst rtt_mr rttrst
222 11011a?atarm?04-oct-10 sam3n 222 11011a?atarm?04-oct-10 sam3n 13.4 functional description the real-time timer can be used to count elapse d seconds. it is built around a 32-bit counter fed by slow clock divided by a programmable 16-bit value. the value can be programmed in the field rtpres of the real-time mode register (rtt_mr). programming rtpres at 0x00008000 corresponds to feeding the real-time counter with a 1 hz signal (if the slow clock is 32.768 khz). the 32-bit counter can count up to 2 32 seconds, corre- sponding to more than 136 years, then roll over to 0. the real-time timer can also be used as a free -running timer with a lower time-base. the best accuracy is achieved by writing rtpres to 3. programming rtpres to 1 or 2 is possible, but may result in losing status events because the st atus register is clear ed two slow clock cycles after read. thus if the rtt is configured to trigger an interrupt, the interrupt occurs during 2 slow clock cycles after reading rtt_sr. to prevent se veral executions of the interrupt handler, the interrupt must be disabled in the interrupt ha ndler and re-enabled when the status register is clear. the real-time timer value (crtv) can be read at any time in the register rtt_vr (real-time value register). as this value can be updated asynchronously from the master clock, it is advis- able to read this register twice at the same value to improve accuracy of the returned value. the current value of the counter is compared with the value written in the alarm register rtt_ar (real-time alarm register). if the counter value matches the alarm, the bit alms in rtt_sr is set. the alarm register is set to its maximum value, corresponding to 0xffff_ffff, after a reset. the bit rttinc in rtt_sr is set each time the real-time timer counter is incremented. this bit can be used to start a periodic interrupt, the period being one second when the rtpres is pro- grammed with 0x8000 and slow clock equal to 32.768 hz. reading the rtt_sr status register resets the rttinc and alms fields. writing the bit rttrst in rtt_mr immediately re loads and restarts the clock divider with the new programmed value. this also resets the 32-bit counter. note: because of the asynchronism between the slow clock (sclk) and the system clock (mck): 1) the restart of the counter and the reset of the rtt_vr current value register is effective only 2 slow clock cycles after the write of th e rttrst bit in the rtt_mr register. 2) the status register fl ags reset is taken into account only 2 sl ow clock cycles after the read of the rtt_sr (status register).
223 11011a?atarm?04-oct-10 sam3n 223 11011a?atarm?04-oct-10 sam3n figure 13-2. rtt counting pre s c a ler almv almv-1 0 almv+1 0 rtpre s - 1 rtt apb cycle re a d rtt_ s r alm s (rtt_ s r) apb interf a ce s clk rttinc (rtt_ s r) almv+2 almv+ 3 ... apb cycle
224 11011a?atarm?04-oct-10 sam3n 224 11011a?atarm?04-oct-10 sam3n 13.5 real-time timer (rtt) user interface table 13-1. register mapping offset register name access reset 0x00 mode register rtt_mr read-write 0x0000_8000 0x04 alarm register rtt_ar read-write 0xffff_ffff 0x08 value register rtt_vr read-only 0x0000_0000 0x0c status register rtt_sr read-only 0x0000_0000
225 11011a?atarm?04-oct-10 sam3n 225 11011a?atarm?04-oct-10 sam3n 13.5.1 real-time timer mode register register name: rtt_mr address: 0x400e1430 access type: read-write ? rtpres: real-time timer prescaler value defines the number of slck periods required to increment the real-time timer. rtpres is defined as follows: rtpres = 0: the prescaler period is equal to 2 16 * sclk period. rtpres 0: the prescaler period is equal to rtpres * sclk period. ? almien: alarm interrupt enable 0 = the bit alms in rtt_sr has no effect on interrupt. 1 = the bit alms in rtt_sr asserts interrupt. ? rttincien: real-time timer increment interrupt enable 0 = the bit rttinc in rtt_sr has no effect on interrupt. 1 = the bit rttinc in r tt_sr asserts interrupt. ? rttrst: real-time timer restart 0 = no effect. 1 = reloads and restarts the clock divider with the new programmed value. this also resets the 32-bit counter. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????rttrstrttincienalmien 15 14 13 12 11 10 9 8 rtpres 76543210 rtpres
226 11011a?atarm?04-oct-10 sam3n 226 11011a?atarm?04-oct-10 sam3n 13.5.2 real-time timer alarm register register name: rtt_ar address: 0x400e1434 access type: read/write ? almv: alarm value defines the alarm value (almv+1) compared with the real-time timer. 31 30 29 28 27 26 25 24 almv 23 22 21 20 19 18 17 16 almv 15 14 13 12 11 10 9 8 almv 76543210 almv
227 11011a?atarm?04-oct-10 sam3n 227 11011a?atarm?04-oct-10 sam3n 13.5.3 real-time timer value register register name: rtt_vr address: 0x400e1438 access type: read-only ? crtv: current real-time value returns the current value of the real-time timer. 31 30 29 28 27 26 25 24 crtv 23 22 21 20 19 18 17 16 crtv 15 14 13 12 11 10 9 8 crtv 76543210 crtv
228 11011a?atarm?04-oct-10 sam3n 228 11011a?atarm?04-oct-10 sam3n 13.5.4 real-time timer status register register name: rtt_sr address: 0x400e143c access type: read-only ? alms: real-time alarm status 0 = the real-time alarm has not occurred since the last read of rtt_sr. 1 = the real-time alarm occurred since the last read of rtt_sr. ? rttinc: real-time timer increment 0 = the real-time timer has not been incremented since the last read of the rtt_sr. 1 = the real-time timer has been incremented since the last read of the rtt_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????rttincalms
229 11011a?atarm?04-oct-10 sam3n 14. real time clock (rtc) 14.1 description the real-time clock (rtc) peripheral is de signed for very low power consumption. it combines a complete time-of-day clock with alarm and a two-hundred-year gregorian calen- dar, complemented by a programmable periodic interrupt. the alarm and calendar registers are accessed by a 32-bit data bus. the time and calendar values are coded in binary-coded decimal (bcd) format. the time format can be 24-hour mode or 12-hour mode with an am/pm indicator. updating time and calendar fields and configuri ng the alarm fields are performed by a parallel capture on the 32-bit data bus. an entry control is performed to avoid loading registers with incompatible bcd format data or with an incompatible date according to the current month/year/century. 14.2 embedded characteristics ? low power consumption ? full asynchronous design ? two hundred year calendar ? programmable periodic interrupt ? alarm and update parallel load ? control of alarm and update time/calendar data in 14.3 block diagram figure 14-1. rtc block diagram bus interface 32768 divider time slow clock: slck bus interface date rtc interrupt entry control interrupt control
230 11011a?atarm?04-oct-10 sam3n 14.4 product dependencies 14.4.1 power management the real-time clock is cont inuously clocked at 32768 hz. the power management controller has no effect on rtc behavior. 14.4.2 interrupt rtc interrupt line is connected on one of the internal sources of the interrupt controller. rtc interrupt requires the interrupt controller to be programmed first. 14.5 functional description the rtc provides a full binary-coded decimal (b cd) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds. the valid year range is 1900 to 2099 in gregorian mode, a two-hundred-year calendar. the rtc can operate in 24-hour mode or in 12-hour mode with an am/pm indicator. corrections for leap years are included (all years di visible by 4 being leap years). this is correct up to the year 2099. 14.5.1 reference clock the reference clock is slow clock (slck). it can be driven internally or by an external 32.768 khz crystal. during low power modes of the processor, the osc illator runs and power c onsumption is critical. the crystal selection has to take into account the current consumption for power saving and the frequency drift due to temperature effect on the circuit for time accuracy. 14.5.2 timing the rtc is updated in real time at one-second intervals in normal mode for the counters of sec- onds, at one-minute intervals for the counter of minutes and so on. due to the asynchronous operation of the rtc with respect to the rest of the chip, to be certain that the value read in the rtc registers (century, year, month, date, day, hours, minutes, sec- onds) are valid and stable, it is necessary to read these registers twice. if the data is the same both times, then it is valid. therefore, a minimu m of two and a maximum of three accesses are required. 14.5.3 alarm the rtc has five programmable fields: month, date, hours, minutes and seconds. each of these fields can be enabled or disabled to match the alarm condition: ? if all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled) at a given month, date, hour/minute/second. ? if only the ?seconds? field is enabled, then an alarm is generated every minute. depending on the co mbination of fields enabled, a large number of possibilit ies are available to the user ranging from minutes to 365/366 days.
231 11011a?atarm?04-oct-10 sam3n 14.5.4 error checking verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. a chec k is performed on illegal bcd entries such as illegal date of the month with regard to the year and century configured. if one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. the user can not reset this flag. it is reset as soon as an acceptable value is programmed. this avoids any further si de effects in the hardware. the same procedure is done for the alarm. the following checks are performed: 1. century (check if it is in range 19 - 20 ) 2. year (bcd entry check) 3. date (check range 01 - 31) 4. month (check if it is in bcd range 01 - 12, check validity regarding ?date?) 5. day (check range 1 - 7) 6. hour (bcd checks: in 24-hour mode, check range 00 - 23 and check that am/pm flag is not set if rtc is set in 24-hour mode; in 12-hour mode check range 01 - 12) 7. minute (check bcd and range 00 - 59) 8. second (check bcd and range 00 - 59) note: if the 12-hour mode is selected by means of the rtc_mode register, a 12-hour value can be pro- grammed and the returned value on rtc_time will be the corresponding 24-hour value. the entry control checks the value of the am/pm indicato r (bit 22 of rtc_time register) to determine the range to be checked. 14.5.5 updating time/calendar to update any of the time/calendar fields, the user must first stop the rtc by setting the corre- sponding field in the control register. bit updtim must be set to update time fields (hour, minute, second) and bit updcal must be set to update calendar fields (century, year, month, date, day). then the user must poll or wait for the interrupt (if enabled) of bit ackupd in the status regis- ter. once the bit reads 1, it is mandatory to clear this flag by writing the corresponding bit in rtc_sccr. the user can now write to the appropriate time and calendar register. once the update is finished, the user must reset (0) updtim and/or updcal in the control when entering programming mode of the calendar fields, the time fields remain enabled. when entering the programming mode of the time fields, both time and calendar fields are stopped. this is due to the location of the calendar logi c circuity (downstream for low-power consider- ations). it is highly recommended to prepare all the fields to be updated before entering programming mode. in successive update operations, the user must wait at least one second after resetting the updtim/updcal bit in the rtc_cr (control register) before setting these bits again. this is done by waiting for the se c flag in the status register before setting updtim/updcal bit. after resetting updtim/updcal, the sec flag must also be cleared.
232 11011a?atarm?04-oct-10 sam3n figure 14-2. update sequence prep a re time or c a lend a r field s s et updtim a nd/or updcal b it( s ) in rtc_cr re a d rtc_ s r ackupd = 1 ? cle a r ackupd b it in rtc_ s ccr upd a te time a nd/or c a lend a r v a l u e s in rtc_timr/rtc_calr cle a r updtim a nd/or updcal b it in rtc_cr no ye s begin end polling or irq (if en ab led)
233 11011a?atarm?04-oct-10 sam3n 14.6 real time clock (r tc) user interface note: if an offset is not listed in the table it must be considered as reserved. table 14-1. register mapping offset register name access reset 0x00 control register rtc_cr read-write 0x0 0x04 mode register rtc_mr read-write 0x0 0x08 time register rtc_timr read-write 0x0 0x0c calendar register rtc_calr read-write 0x01210720 0x10 time alarm register rtc_timalr read-write 0x0 0x14 calendar alarm register rtc_calalr read-write 0x01010000 0x18 status register rtc_sr read-only 0x0 0x1c status clear command r egister rtc_sccr write-only ? 0x20 interrupt enable register rtc_ier write-only ? 0x24 interrupt disable re gister rtc_idr write-only ? 0x28 interrupt mask register rtc_imr read-only 0x0 0x2c valid entry register rtc_ver read-only 0x0 0x30?0xe0 reserved register ? ? ? 0xe4 write protect mode register rtc_wpmr read-write 0x00000000 0xe8?0xf8 reserved register ? ? ? 0xfc reserved register ? ? ?
234 11011a?atarm?04-oct-10 sam3n 14.6.1 rtc control register name: rtc_cr address: 0x400e1460 access: read-write this register can only be written if the wpen bit is cleared in ?rtc write protect mode register? on page 246 . ? updtim: update request time register 0 = no effect. 1 = stops the rtc time counting. time counting consists of second, minute and hour counters. time counters can be programmed once this bit is set and acknowledged by the bit ackupd of the status register. ? updcal: update request calendar register 0 = no effect. 1 = stops the rtc calendar counting. calendar counting consists of day, date, month, year and century counters. calendar counters can be programmed once this bit is set. ? timevsel: time ev ent selection the event that generates the flag timev in rtc_sr (status register) depends on the value of timevsel. ? calevsel: calendar event selection the event that ge nerates the flag calev in rtc_sr depends on the value of calevsel 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????? cal evsel 15 14 13 12 11 10 9 8 ?????? timevsel 76543210 ??????updcalupdtim value name description 0 minute minute change 1 hour hour change 2 midnight every day at midnight 3 noon every day at noon value name description 0 week week change (every monday at time 00:00:00) 1 month month change (every 01 of each month at time 00:00:00) 2 year year change (every janu ary 1 at time 00:00:00) 3?
235 11011a?atarm?04-oct-10 sam3n 14.6.2 rtc mode register name: rtc_mr address: 0x400e1464 access: read-write ? hrmod: 12-/24-hour mode 0 = 24-hour mode is selected. 1 = 12-hour mode is selected. all non-significant bits read zero. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????hrmod
236 11011a?atarm?04-oct-10 sam3n 14.6.3 rtc time register name: rtc_timr address: 0x400e1468 access: read-write ? sec: current second the range that can be set is 0 - 59 (bcd). the lowest four bits encode the units. the higher bits encode the tens. ? min: current minute the range that can be set is 0 - 59 (bcd). the lowest four bits encode the units. the higher bits encode the tens. ? hour: current hour the range that can be set is 1 - 12 (bcd) in 12-hour mode or 0 - 23 (bcd) in 24-hour mode. ? ampm: ante meridiem post meridiem indicator this bit is the am/pm in dicator in 12-hour mode. 0 = am. 1 = pm. all non-significant bits read zero. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?ampm hour 15 14 13 12 11 10 9 8 ?min 76543210 ?sec
237 11011a?atarm?04-oct-10 sam3n 14.6.4 rtc calendar register name: rtc_calr address: 0x400e146c access: read-write ? cent: current century the range that can be set is 19 - 20 (bcd). the lowest four bits encode the units. the higher bits encode the tens. ? year: current year the range that can be set is 00 - 99 (bcd). the lowest four bits encode the units. the higher bits encode the tens. ? month: current month the range that can be set is 01 - 12 (bcd). the lowest four bits encode the units. the higher bits encode the tens. ? day: current day in current week the range that can be set is 1 - 7 (bcd). the coding of the number (which number represents which day) is user-defined as it has no effect on the date counter. ? date: current day in current month the range that can be set is 01 - 31 (bcd). the lowest four bits encode the units. the higher bits encode the tens. all non-significant bits read zero. 31 30 29 28 27 26 25 24 ?? date 23 22 21 20 19 18 17 16 day month 15 14 13 12 11 10 9 8 year 76543210 ?cent
238 11011a?atarm?04-oct-10 sam3n 14.6.5 rtc time alarm register name: rtc_timalr address: 0x400e1470 access: read-write this register can only be written if the wpen bit is cleared in ?rtc write protect mode register? on page 246 . ? sec: second alarm this field is the alarm field corresponding to the bcd-coded second counter. ? secen: second alarm enable 0 = the second-matching alarm is disabled. 1 = the second-matching alarm is enabled. ? min: minute alarm this field is the alarm field corresponding to the bcd-coded minute counter. ? minen: minute alarm enable 0 = the minute-matching alarm is disabled. 1 = the minute-matching alarm is enabled. ? hour: hour alarm this field is the alarm field corresponding to the bcd-coded hour counter. ? ampm: am/pm indicator this field is the alarm field corresponding to the bcd-coded hour counter. ? houren: hour alarm enable 0 = the hour-matching alarm is disabled. 1 = the hour-matching alarm is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 houren ampm hour 15 14 13 12 11 10 9 8 minen min 76543210 secen sec
239 11011a?atarm?04-oct-10 sam3n 14.6.6 rtc calendar alarm register name: rtc_calalr address: 0x400e1474 access: read-write this register can only be written if the wpen bit is cleared in ?rtc write protect mode register? on page 246 . ? month: month alarm this field is the alarm field corresponding to the bcd-coded month counter. ? mthen: month alarm enable 0 = the month-matching alarm is disabled. 1 = the month-matching alarm is enabled. ?date: date alarm this field is the alarm field corresponding to the bcd-coded date counter. ? dateen: date alarm enable 0 = the date-matching alarm is disabled. 1 = the date-matching alarm is enabled. 31 30 29 28 27 26 25 24 dateen ? date 23 22 21 20 19 18 17 16 mthen ? ? month 15 14 13 12 11 10 9 8 ???????? 76543210 ????????
240 11011a?atarm?04-oct-10 sam3n 14.6.7 rtc status register name: rtc_sr address: 0x400e1478 access: read-only ? ackupd: acknowledge for update 0 = time and calendar registers cannot be updated. 1 = time and calendar registers can be updated. ? alarm: alarm flag 0 = no alarm matching condition occurred. 1 = an alarm matching condition has occurred. ? sec: second event 0 = no second event has occurred since the last clear. 1 = at least one second event has occurred since the last clear. ? timev: time event 0 = no time event has occurred since the last clear. 1 = at least one time event has occurred since the last clear. the time event is selected in the timevsel field in rt c_cr (control register) and can be any one of the following events: minute change, hour change, noon, midnight (day change). ? calev: calendar event 0 = no calendar event has occurred since the last clear. 1 = at least one calendar event has occurred since the last clear. the calendar event is selected in the calevsel field in rtc_cr and can be any one of the following events: week change, month change and year change. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? calev timev sec alarm ackupd
241 11011a?atarm?04-oct-10 sam3n 14.6.8 rtc status clear command register name: rtc_sccr address: 0x400e147c access: write-only ? ackclr: acknowledge clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). ? alrclr: alarm clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). ? secclr: second clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). ? timclr: time clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). ? calclr: calendar clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? calclr timclr secclr alrclr ackclr
242 11011a?atarm?04-oct-10 sam3n 14.6.9 rtc interrupt enable register name: rtc_ier address: 0x400e1480 access: write-only ? acken: acknowledge update interrupt enable 0 = no effect. 1 = the acknowledge for update interrupt is enabled. ? alren: alarm interrupt enable 0 = no effect. 1 = the alarm interrupt is enabled. ? secen: second event interrupt enable 0 = no effect. 1 = the second periodic interrupt is enabled. ? timen: time event interrupt enable 0 = no effect. 1 = the selected time event interrupt is enabled. ? calen: calendar event interrupt enable 0 = no effect. ? 1 = the selected calendar event interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? calen timen secen alren acken
243 11011a?atarm?04-oct-10 sam3n 14.6.10 rtc interrupt disable register name: rtc_idr address: 0x400e1484 access: 2 write-only ? ackdis: acknowledge update interrupt disable 0 = no effect. 1 = the acknowledge for update interrupt is disabled. ? alrdis: alarm interrupt disable 0 = no effect. 1 = the alarm interrupt is disabled. ? secdis: second event interrupt disable 0 = no effect. 1 = the second periodic interrupt is disabled. ? timdis: time event interrupt disable 0 = no effect. 1 = the selected time event interrupt is disabled. ? caldis: calendar event interrupt disable 0 = no effect. 1 = the selected calendar event interrupt is disabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? caldis timdis secdis alrdis ackdis
244 11011a?atarm?04-oct-10 sam3n 14.6.11 rtc interrupt mask register name: rtc_imr address: 0x400e1488 access: read-only ? ack: acknowledge update interrupt mask 0 = the acknowledge for update interrupt is disabled. 1 = the acknowledge for update interrupt is enabled. ? alr: alarm interrupt mask 0 = the alarm interrupt is disabled. 1 = the alarm interrupt is enabled. ? sec: second event interrupt mask 0 = the second periodic interrupt is disabled. 1 = the second periodic interrupt is enabled. ? tim: time event interrupt mask 0 = the selected time event interrupt is disabled. 1 = the selected time event interrupt is enabled. ? cal: calendar event interrupt mask 0 = the selected calendar event interrupt is disabled. 1 = the selected calendar event interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???caltimsecalrack
245 11011a?atarm?04-oct-10 sam3n 14.6.12 rtc valid entry register name: rtc_ver address: 0x400e148c access: read-only ? nvtim: non-valid time 0 = no invalid data has been detected in rtc_timr (time register). 1 = rtc_timr has contained invalid data since it was last programmed. ? nvcal: non-valid calendar 0 = no invalid data has been detected in rtc_calr (calendar register). 1 = rtc_calr has contained invalid data since it was last programmed. ? nvtimalr: non-valid time alarm 0 = no invalid data has been detected in rtc_timalr (time alarm register). 1 = rtc_timalr has contained invalid data since it was last programmed. ? nvcalalr: non-valid calendar alarm 0 = no invalid data has been detected in rtc_calalr (calendar alarm register). 1 = rtc_calalr has contained invalid data since it was last programmed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????nvcalalrnvtimalrnvcalnvtim
246 11011a?atarm?04-oct-10 sam3n 14.6.13 rtc write protect mode register name: rtc_wpmr address: 0x400e1544 access: read-write ? wpen: write protect enable 0 = disables the write protect if wpkey co rresponds to 0x525443 (?rtc? in ascii). 1 = enables the write protect if wpkey corresponds to 0x525443 (?rtc? in ascii). protects the registers: ?rtc mode register? ?rtc mode register? ?rtc time alarm register? ?rtc calendar alarm register? 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 ???????wpen
247 11011a?atarm?04-oct-10 sam3n 15. watchdog timer (wdt) 15.1 description the watchdog timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. it features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 khz). it can generate a general reset or a processor reset only. in addition, it can be stopped while the processor is in debug mode or idle mode. 15.2 embedded characteristics ? 16-bit key-protected only-once-programmable counter ? windowed, prevents the processor to be in a dead-lock on the watchdog access. 15.3 block diagram figure 15-1. watchdog timer block diagram
248 11011a?atarm?04-oct-10 sam3n 15.4 functional description the watchdog timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. it is supplied with vddcore. it re starts with initial values on processor reset. the watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field wdv of the mode register (wdt_m r). the watchdog timer uses the slow clock divided by 128 to establish the maximum watchdo g period to be 16 seconds (with a typical slow clock of 32.768 khz). after a processor reset, the value of wdv is 0xfff, corresponding to the maximum value of the counter with the external reset generation enabled (field wdrsten at 1 after a backup reset). this means that a default watchdog is running at reset, i.e., at power-up. the user must either disable it (by setting the wddis bit in wd t_mr) if he does not expect to use it or must reprogram it to meet the maximum watchdog period the application requires. the watchdog mode register (wdt_mr) can be written only once. only a processor reset resets it. writing the wdt_mr register reloads the timer with the newly programmed mode parameters. in normal operation, the user reloads the watchdog at regular intervals before the timer under- flow occurs, by writing the control register (wdt_cr) with the bit wdrstt to 1. the watchdog counter is then immediately reloaded from wdt_mr and restarted, and the slow clock 128 divider is reset and restarted. the wdt_cr register is write-protected. as a result, writing wdt_cr without the correct hard-coded key has no effect. if an underflow does occur, the ?wdt_fault? signal to the reset controller is asserted if the bit wdrsten is set in the mode register (wdt_mr). moreover, the bit wdunf is set in the watchdog status register (wdt_sr). to prevent a software deadlock that continuously triggers the watchdog, the reload of the watchdog must occur while the watchdog c ounter is within a window between 0 and wdd, wdd is defined in the watchdog mode register wdt_mr. any attempt to restart the watchdog while the watchdog counter is between wdv and wdd results in a watchdog error, even if the watchdog is disabled. the bit wderr is updated in the wdt_sr and the ?wdt_fault? signal to the reset controller is asserted. note that this feature can be disabled by programming a wdd value greater than or equal to the wdv value. in such a configuration, restarti ng the watchdog timer is permitted in the whole range [0; wdv] and does not generate an error. this is the default configuration on reset (the wdd and wdv values are equal). the status bits wdunf (watchdog underflow ) and wderr (watchdog error) trigger an inter- rupt, provided the bit wdfien is set in the mode register. the signal ?wdt_fault? to the reset controller causes a watchdog reset if the wdrsten bit is set as already explained in the reset controller programmer datasheet. in that case, the processor and the watchdog timer are reset, and the wderr and wdunf flags are reset. if a reset is generated or if wdt_sr is read, the status bits are reset, the interrupt is cleared, and the ?wdt_fault? signal to the reset controller is deasserted. writing the wdt_mr reloads and restarts the down counter. while the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits wdidlehlt and wddbghlt in the wdt_mr.
249 11011a?atarm?04-oct-10 sam3n figure 15-2. watchdog behavior
250 11011a?atarm?04-oct-10 sam3n 15.5 watchdog timer (wdt) user interface table 15-1. register mapping offset register name access reset 0x00 control register wdt_cr write-only - 0x04 mode register wdt_mr read-write once 0x3fff_2fff 0x08 status register wdt_sr read-only 0x0000_0000
251 11011a?atarm?04-oct-10 sam3n 15.5.1 watchdog timer control register name: wdt_cr address: 0x400e1450 access: write-only ? wdrstt: watchdog restart 0: no effect. 1: restarts the watchdog. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????wdrstt
252 11011a?atarm?04-oct-10 sam3n 15.5.2 watchdog timer mode register name: wdt_mr address: 0x400e1454 access: read-write once ? wdv: watchdog counter value defines the value loaded in the 12-bit watchdog counter. ? wdfien: watchdog fault interrupt enable 0: a watchdog fault (underflow or error) has no effect on interrupt. 1: a watchdog fault (underflow or error) asserts interrupt. ? wdrsten: watchdog reset enable 0: a watchdog fault (underflow or error) has no effect on the resets. 1: a watchdog fault (underflow or error) triggers a watchdog reset. ? wdrproc: watchdog reset processor 0: if wdrsten is 1, a watchdog fault (underflow or error) activates all resets. 1: if wdrsten is 1, a watchdog fault (underflow or error) activates the processor reset. ? wdd: watchdog delta value defines the permitted range for reloading the watchdog timer. if the watchdog timer value is less than or equal to w dd, writing wdt_cr with wdrs tt = 1 restarts the timer. if the watchdog timer value is greater than wdd, writing wdt_cr with wdrstt = 1 causes a watchdog error. ? wddbghlt: watchdog debug halt 0: the watchdog runs when the processor is in debug state. 1: the watchdog stops when the processor is in debug state. ? wdidlehlt: watchdog idle halt 0: the watchdog runs when the system is in idle mode. 1: the watchdog stops when the system is in idle state. ? wddis: watchdog disable 0: enables the watchdog timer. 1: disables the watchdog timer. 31 30 29 28 27 26 25 24 wdidlehlt wddbghlt wdd 23 22 21 20 19 18 17 16 wdd 15 14 13 12 11 10 9 8 wddis wdrproc wdrsten wdfien wdv 76543210 wdv
253 11011a?atarm?04-oct-10 sam3n 15.5.3 watchdog timer status register name: wdt_sr address: 0x400e1458 access: read-only ? wdunf: watchdog underflow 0: no watchdog underflow occurred since the last read of wdt_sr. 1: at least one watchdog underflow occurred since the last read of wdt_sr. ? wderr: watchdog error 0: no watchdog error occurred since the last read of wdt_sr. 1: at least one watchdog error occurred since the last read of wdt_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????wderrwdunf
254 11011a?atarm?04-oct-10 sam3n
255 11011a?atarm?04-oct-10 sam3n 255 11011a?atarm?04-oct-10 sam3n 16. supply controller (supc) 16.1 description the supply controller (supc) co ntrols the supply voltage of the core of the system and man- ages the backup low power mode. in this mode , the current consumption is reduced to a few microamps for backup power retention. exit from this mode is possible on multiple wake-up sources including events on wkup pins, or a clock alarm. the supc also generates the slow clock by selecting either the low power rc os cillator or the low power crystal oscillator. 16.2 embedded characteristics ? manages the core power supply vddcore and the backup low power mode by controlling the embedde d voltage regulator ? generates the slow clock slck, by selectin g either the 22-42 khz low power rc oscillator or the 32 khz low po wer crystal oscillator ? supports multiple wake up sources, for exit from backup low power mode ? force wake up pin, with programmable debouncing ? 16 wake up inputs, with programmable debouncing ? real time clock alarm ? real time timer alarm ? supply monitor detection on vddio, with programmable scan period and voltage threshold ? a supply monitor detection on vddio or a brownout detection on vddcore can trigger a core reset ? embeds: ? one 22 to 42 khz low power rc oscillator ? one 32 khz low power crystal oscillator ? one zero-power power-on reset cell ? one software programmable supply monitor, on vddio located in backup section ? one brownout detector on vddcore located in the core
256 11011a?atarm?04-oct-10 sam3n 256 11011a?atarm?04-oct-10 sam3n 16.3 block diagram figure 16-1. supply controller block diagram s oftw a re controlled volt a ge reg u l a tor adc pioa/b/c m a trix s ram cortex-m 3 fl as h peripher a l s peripher a l bridge zero-power power-on re s et su pply monitor (b a ck u p) rtc em b edded 3 2 khz rc o s cill a tor xt a l 3 2 khz o s cill a tor su pply controller browno u t detector (core) gener a l p u rpo s e b a ck u p regi s ter s re s et controller b a ck u p power su pply core power su pply vr_on vr_mode b od_on b rown_o u t rtc_ a l a rm s lck rtc_nre s et proc_nre s et periph_nre s et ice_nre s et m as ter clock mck s lck core_nre s et m a in clock mainck s lck nr s t f s tt0 - f s tt15 xin 3 2 xout 3 2 o s c 3 2k_xt a l_en o s c 3 2k_ s el s low clock s lck o s c 3 2k_rc_en core_nre s et vddio vddcore vddout advref adx wkup0 - wkup15 b od_core_on lcore_ b rown_o u t rtt rtt_ a l a rm s lck rtt_nre s et xin xout vddio vddin piox dac dac0x pll f s tt0 - f s tt15 a re po ss i b le f as t s t a rt u p s o u rce s , gener a ted b y wkup0-wkup15 pin s , bu t a re not phy s ic a l pin s . em b edded 12/ 8 /4 mhz rc o s cill a tor xt a l o s cill a tor w a tchdog timer power m a n a gement controller
257 11011a?atarm?04-oct-10 sam3n 257 11011a?atarm?04-oct-10 sam3n 16.4 supply controller functional description 16.4.1 supply controller overview the device can be divided into two power supply areas: ? the vddio power supply: including the supply controller, a part of th e reset controller, the slow clock switch, the general purpose backup registers, the supply monitor and the clock which includes the real time timer and the real time clock ? the core power supply: including the other part of the reset controller, the brownout detector, the processor, the sram memory, the flash memory and the peripherals the supply controller (supc) controls the supply voltage of the core power supply. the supc intervenes when the vddio power supply rises (when the system is starting) or when the backup low power mode is entered. the supc also integrates the sl ow clock generator which is bas ed on a 32 khz crystal oscilla- tor and an embedded 32 khz rc oscillator. the slow clock defaults to the rc oscillator, but the software can enable the cryst al oscillator and select it as the slow clock source. the supply controller and the vddio power su pply have a reset circuitry based on a zero- power power-on reset cell. the zero-power power-on reset allows the supc to start properly as soon as the vddio voltage becomes valid. at startup of the system, once the voltage vddio is valid and the embedded 32 khz rc oscilla- tor is stabilized, the supc starts up the core by sequentially enabling the internal voltage regulator, waiting that the core voltage vddcore is valid, then releasing the reset signal of the core ?vddcore_nreset? signal. once the system has started, the user can program a supply monitor and/or a brownout detec- tor. if the supply monitor detects a voltage on vddio that is too low, the supc can assert the reset signal of the core ?vddcore_nreset? signal until vddio is valid. likewise, if the brownout detector detects a core voltage vddcore that is too low, th e supc can assert the reset signal ?vddcore_nreset? until vddcore is valid. when the backup low power mode is entered, th e supc sequentially asserts the reset signal of the core power supply ?vddcore_nreset? and disables the voltage regulator, in order to supply only the vddio power supply. in this mode the current consumption is reduced to a few micro- amps for backup part retention. exit from this mode is possible on multiple wake-up sources including an event on wkup pins, or a clock alarm. to exit this mode, the supc operates in the same way as system startup.
258 11011a?atarm?04-oct-10 sam3n 258 11011a?atarm?04-oct-10 sam3n 16.4.2 slow clock generator the supply controller embeds a slow clock gene rator that is supplied with the vddio power supply. as soon as the vddio is supplied, both the crystal oscillator and the embedded rc oscillator are powered up, but on ly the embedded rc oscillator is enabled. this allows the slow clock to be valid in a short time (about 100 s). the user can select the crystal oscillator to be t he source of the slow clock, as it provides a more accurate frequency. the command is made by wr iting the supply controller control register (supc_cr) with the xtalsel bit at 1.this results in a sequence which first configures the pio lines multiplexed with xin32 and xout32 to be driven by the oscillator, then enables the crystal oscillator. then waits for 32,768 slow clock cycles, then switches the slow clock on the output of the crystal oscillator and then disables the rc o scillator to save power. the switch of the slow clock source is glitch free. the oscsel bit of the supply controller stat us register (supc_sr) allows knowing when the switch sequence is done. coming back on the rc oscillator is only possibl e by shutting down t he vddio power supply. if the user does not need the crystal oscilla tor, the xin32 and xout32 pins should be left unconnected. the user can also set the crystal oscillator in bypass mode instead of connecting a crystal. in this case, the user has to provide the external cl ock signal on xin32. the input characteristics of the xin32 pin are given in the product electrical characteristics section. in order to set the bypass mode, the oscbypass bit of the supply controller mode regi ster (supc_mr) needs to be set at 1. 16.4.3 voltage regulator control/backup low power mode the supply controller can be used to control the embedded 1.8v voltage regulator. the voltage regulator automatically adapts its quiescent current depending on the required load current. please refer to the electrical characteristics section. the programmer can switch off the voltage regulator, and thus put the device in backup mode, by writing the supply controller control regi ster (supc_cr) with the vroff bit at 1. this can be done also by using wfe (wait for event) cortex-m3 instruction with the deep mode bit set to 1. the backup mode can also be entered by executing the wfi (wait for interrupt) or wfe (wait for event) cortex-m3 instructions. to select the backup mode entry mechanism, two options are available, depending on the sleeponexit bit in the cortex-m3 syst em control register: ? sleep-now: if the sleeponexit bit is cleared, the device enters backup mode as soon as the wfi or wfe instruction is executed. ? sleep-on-exit: if the sleeponexit bit is set when the wfi instruct ion is executed, the device enters backup mode as soon as it exits the lowest priority isr. this asserts the vddcore_nreset signal after the write resynchronization time which lasts, in the worse case, two slow clock cycles. once the vd dcore_nreset signal is asserted, the processor and the peripherals are stopped one slow clock cycle before the core power supply shuts off. when the user does not use the internal voltage regulator and wants to supply vddcore by an external supply, it is possible to disable the volt age regulator. note that it is different from the backup mode. depending on the application, disabl ing the voltage regulator can reduce power consumption as the voltage regulator input (v ddin) is shared with the adc and dac. this is done through onreg bit in supc_mr.
259 11011a?atarm?04-oct-10 sam3n 259 11011a?atarm?04-oct-10 sam3n 16.4.4 supply monitor the supply controller embeds a supply monitor which is located in the vddio power supply and which monitors vddio power supply. the supply monitor can be used to prevent the processor from fa lling into an unpredictable state if the main power supply drops below a certain level. the threshold of the supply monitor is programmable. it can be selected from 1.9v to 3.4v by steps of 100 mv. this threshold is programmed in the smth field of the supply controller sup- ply monitor mode register (supc_smmr). the supply monitor can also be enabled during one slow clock period on every one of either 32, 256 or 2048 slow clock periods, according to the choice of the user. this can be configured by programming the smsmpl field in supc_smmr. enabling the supply monitor for such reduced times allows to divide the typical supply monitor power consumption respectively by factors of 32, 256 or 2048, if the user does not need a con- tinuous monitoring of the vddio power supply. a supply monitor detection can either generate a reset of the core power supply or a wake up of the core power supply. generating a core re set when a supply monitor detection occurs is enabled by writing the smrsten bit to 1 in supc_smmr. waking up the core power supply when a supply monitor detection occurs can be enabled by programming the smen bit to 1 in the supply controller wake up mode register (supc_wumr). the supply controller provides two status bits in the supply controller status register for the supply monitor which allows to determine whether the last wake up was due to the supply monitor: ? the smos bit provides real time information, which is updated at each measurement cycle or updated at each slow clock cycle, if the measurement is continuous. ? the sms bit provides saved information and shows a supply monitor detection has occurred since the last read of supc_sr. the sms bit can generate an interrupt if the smien bit is set to 1 in the supply controller supply monitor mode register (supc_smmr).
260 11011a?atarm?04-oct-10 sam3n 260 11011a?atarm?04-oct-10 sam3n figure 16-2. supply monitor status bit and associated interrupt su pply monitor on 3 . 3 v 0 v thre s hold s m s a nd s upc interr u pt re a d s upc_ s r periodic sa mpling contin u o us sa mpling ( s m s mpl = 1)
261 11011a?atarm?04-oct-10 sam3n 261 11011a?atarm?04-oct-10 sam3n 16.4.5 power supply reset 16.4.5.1 raising the power supply as soon as the voltage vddio rises, the rc oscillator is powered up and the zero-power power-on reset cell ma intains its output low as long as vddio has not reached its target voltage. during this time, the supply co ntroller is entirely reset. when the vddio voltage becomes valid and zero-power power-on reset si gnal is released, a counter is started for 5 slow clock cycles. this is the time it takes for t he 32 khz rc oscillator to stabilize. after this time, the voltage regulator is enabled. the core power supply rises and the brownout detector provides the bodcore_in signal as soon as the core voltage vddcore is valid. this results in releasing the vddcore_nreset signal to the reset controller after the bodcore_in signal has been confirmed as being valid for at least one slow clock cycle. figure 16-3. raising the vddi o power supply zero-power power-on re s et cell o u tp u t 22 - 42 khz rc o s cill a tor o u tp u t f as t rc o s cill a tor o u tp u t b a ck u p power su pply vr_on b odcore_in vddcore_nre s et nr s t proc_nre s et note: after ? proc_nre s et ? ri s ing, the core s t a rt s fecthing in s tr u ction s from fl as h a t 4 mhz. periph_nre s et 7 x s low clock cycle s 3 x s low clock cycle s 3 x s low clock cycle s 6.5 x s low clock cycle s t on volt a ge reg u l a tor zero-power por core power su pply
262 11011a?atarm?04-oct-10 sam3n 262 11011a?atarm?04-oct-10 sam3n 16.4.6 core reset the supply controller manages the vddcore_nreset signal to the reset controller, as described previously in section 16.4.5 ?power supply reset? . the vddcore_nreset signal is normally asserted before shutting down the core power supply and released as soon as the core power supply is correctly regulated. there are two additional sources which can be programmed to activate vddcore_nreset: ? a supply monitor detection ? a brownout detection 16.4.6.1 supply monitor reset the supply monitor is capable of generating a re set of the system. this can be enabled by set- ting the smrsten bit in the supply controller supply monitor mode register (supc_smmr). if smrsten is set and if a supply monitor detection occurs, the vddcore_nreset signal is imme- diately activated for a minimum of 1 slow clock cycle. 16.4.6.2 brownout detector reset the brownout detector provides the bodcore_in si gnal to the supc which indicates that the volt- age regulation is operating as programmed. if th is signal is lost for l onger than 1 slow clock period while the voltage regulator is enabled, the supply controller can assert vddcore_nreset. this feature is enabled by writing the bit, bo drsten (brownout detector reset enable) to 1 in the supply controller m ode register (supc_mr). if bodrsten is set and the voltage regulation is lost (output voltage of the regulator too low), the vddcore_nreset signal is asserted for a minimum of 1 slow clock cycle and then released if bodcore_in has been reactivated. the bodrsts bit is set in the supply controller status reg- ister (supc_sr) so that the user can know the source of the last reset. until bodcore_in is deactivated, the vddcore_nreset signal remains active. 16.4.7 wake up sources the wake up events allow the device to exit backup mode. when a wake up event is detected, the supply controller performs a sequence wh ich automatically reenables the core power supply.
263 11011a?atarm?04-oct-10 sam3n 263 11011a?atarm?04-oct-10 sam3n figure 16-4. wake up sources 16.4.7.1 wake up inputs the wake up inputs, wkup0 to wkup15, can be programmed to perform a wake up of the core power supply. each input can be enabled by writing to 1 the corresponding bit, wkupen0 to wkupen 15, in the wake up inputs regist er (supc_wuir). the wake up level can be selected with the corresponding polarity bit, wkuppl0 to wkuppl15, also located in supc_wuir. all the resulting signals are wired-ored to trigger a debounce counter, which can be pro- grammed with the wkupdbc field in the supply controller wake up mode register (supc_wumr). the wkupdbc field can select a debouncing period of 3, 32, 512, 4,096 or 32,768 slow clock cycles. this corresponds respectively to about 100 s, about 1 ms, about 16 ms, about 128 ms and about 1 second (for a typical slow clock frequency of 32 khz). pro- gramming wkupdbc to 0x0 selects an immediate wake up, i.e., an enabled wkup pin must be active according to its polarity during a minimum of one slow clock period to wake up the core power supply. if an enabled wkup pin is asserted for a time longer than the debouncing period, a wake up of the core power supply is started and th e signals, wkup0 to wkup15 as shown in figure 16-4 , are latched in the supply controller status regist er (supc_sr). this allo ws the user to identify the source of the wake up, however, if a new wake up condition occurs, the primary information is lost. no new wake up can be detected since the primary wake up condition has disappeared. wkup15 wkupen15 wkupt15 wkupen1 wkupen0 de b o u ncer s lck wkupdbc wkup s rtcen rtc_ a l a rm s men s m_o u t core su pply re s t a rt wkupi s 0 wkupi s 1 wkupi s 15 f a lling/ri s ing edge detector wkupt0 f a lling/ri s ing edge detector wkupt1 f a lling/ri s ing edge detector wkup0 wkup1 rtten rtt_ a l a rm
264 11011a?atarm?04-oct-10 sam3n 264 11011a?atarm?04-oct-10 sam3n 16.4.7.2 clock alarms the rtc and the rtt alarms can generate a wake up of the core power supply. this can be enabled by writing respectively, the bits rtce n and rtten to 1 in the supply controller wake up mode register (supc_wumr). the supply controller does not provide any status as the information is available in the user interface of either the real time timer or the real time clock. 16.4.7.3 supply monitor detection the supply monitor can generate a wakeup of the core power supply. see section 16.4.4 ?sup- ply monitor? .
265 11011a?atarm?04-oct-10 sam3n 265 11011a?atarm?04-oct-10 sam3n 16.5 supply controller (supc) user interface the user interface of the supply controller is part of the system controller user interface. 16.5.1 system controller (sysc) user interface 16.5.2 supply controller (supc) user interface table 16-1. system controller registers offset system controller peripheral name 0x00-0x0c reset controller rstc 0x10-0x2c supply controller supc 0x30-0x3c real time timer rtt 0x50-0x5c watchdog wdt 0x60-0x7c real time clock rtc 0x90-0xdc general purpose backup register gpbr table 16-2. register mapping offset register name access reset 0x00 supply controller control register supc_cr write-only n/a 0x04 supply controller supply monitor mode register supc_smmr read-write 0x0000_0000 0x08 supply controller mode register supc_mr read-write 0x0000_5a00 0x0c supply controller wake up mode register supc_wumr read-write 0x0000_0000 0x10 supply controller wake up inputs register supc_wuir read-write 0x0000_0000 0x14 supply controller status register supc_sr read-only 0x0000_0800 0x18 reserved
266 11011a?atarm?04-oct-10 sam3n 266 11011a?atarm?04-oct-10 sam3n 16.5.3 supply controller control register name: supc_cr address: 0x400e1410 access: write-only ? vroff: voltage regulator off 0 (no_effect) = no effect. 1 (stop_vreg) = if key is corr ect, asserts vddcore_ nreset and stops th e voltage regulator. ? xtalsel: crystal oscillator select 0 (no_effect) = no effect. 1 (crystal_sel) = if key is corr ect, switches the slow clock on the crystal oscillator output. ?key: password should be written to value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ? 76543210 ????xtalselvroff??
267 11011a?atarm?04-oct-10 sam3n 267 11011a?atarm?04-oct-10 sam3n 16.5.4 supply controller supply monitor mode register name: supc_smmr address: 0x400e1414 access: read-write ? smth: supply monitor threshold 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? smien smrsten ? smsmpl 76543210 ???? smth value name description 0x0 1_9v 1.9 v 0x1 2_0v 2.0 v 0x2 2_1v 2.1 v 0x3 2_2v 2.2 v 0x4 2_3v 2.3 v 0x5 2_4v 2.4 v 0x6 2_5v 2.5 v 0x7 2_6v 2.6 v 0x8 2_7v 2.7 v 0x9 2_8v 2.8 v 0xa 2_9v 2.9 v 0xb 3_0v 3.0 v 0xc 3_1v 3.1 v 0xd 3_2v 3.2 v 0xe 3_3v 3.3 v 0xf 3_4v 3.4 v
268 11011a?atarm?04-oct-10 sam3n 268 11011a?atarm?04-oct-10 sam3n ? smsmpl: supply monitor sampling period ? smrsten: supply monitor reset enable 0 (not_enable) = the core reset signal ?vddcore_nreset? is not affected when a supply monitor detection occurs. 1 (enable) = the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. ? smien: supply monitor interrupt enable 0 (not_enable) = the supc interrupt signal is no t affected when a supply monitor detection occurs. 1 (enable) = the supc interrupt signal is asserted when a supply monitor detection occurs. value name description 0x0 smd supply monitor disabled 0x1 csm continuous supply monitor 0x2 32slck supply monitor enabled one slck period every 32 slck periods 0x3 256slck supply monitor enabled one slck period every 256 slck periods 0x4 2048slck supply monitor enabled one slck period every 2,048 slck periods 0x5-0x7 reserved reserved
269 11011a?atarm?04-oct-10 sam3n 269 11011a?atarm?04-oct-10 sam3n 16.5.5 supply controller mode register name: supc_mr address: 0x400e1418 access: read-write ? bodrsten: brownout detector reset enable 0 (not_enable) = the core reset signal ?vddcore_nreset? is not affected when a brownout detection occurs. 1 (enable) = the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. ? boddis: brownout detector disable 0 (enable) = the core brownout detector is enabled. 1 (disable) = the core brow nout detector is disabled. ? onreg: voltage regulator enable 0 (onreg_unused) = voltage regulator is not used 1 (onreg_used) = voltage regulator is used ? oscbypass: oscillator bypass 0 (no_effect) = no effect. clock selection depends on xtalsel value. 1 (bypass) = the 32-khz xtal oscillator is selected and is put in bypass mode. ?key: password key should be written to value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???oscbypass???? 15 14 13 12 11 10 9 8 ? onregboddisbodrsten???? 76543210 ????????
270 11011a?atarm?04-oct-10 sam3n 270 11011a?atarm?04-oct-10 sam3n 16.5.6 supply controller wake up mode register name: supc_wumr address: 0x400e141c access: read-write ? smen: supply monitor wake up enable 0 (not_enable) = the supply monitor detection has no wake up effect. 1 (enable) = the supply monitor detection forces the wake up of the core power supply. ? rtten: real time timer wake up enable 0 (not_enable) = the rtt alarm signal has no wake up effect. 1 (enable) = the rtt alarm signal forces the wake up of the core power supply. ? rtcen: real time clock wake up enable 0 (not_enable) = the rtc alarm signal has no wake up effect. 1 (enable) = the rtc alarm signal forces the wake up of the core power supply. ? wkupdbc: wake up inputs debouncer period 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? wkupdbc ???? 76543210 ????rtcenrttensmen? value name description 0 immediate immediate, no debouncing, detected active at least on one slow clock edge. 1 3_sclk wkupx shall be in its active state for at least 3 slck periods 2 32_sclk wkupx shall be in its active state for at least 32 slck periods 3 512_sclk wkupx shall be in its active state for at least 512 slck periods 4 4096_sclk wkupx shall be in its active state for at least 4,096 slck periods 5 32768_sclk wkupx shall be in its active state for at least 32,768 slck periods 6 reserved reserved 7 reserved reserved
271 11011a?atarm?04-oct-10 sam3n 271 11011a?atarm?04-oct-10 sam3n 16.5.7 system controller wake up inputs register name: supc_wuir address: 0x400e1420 access: read-write ? wkupen0 - wkupen15: wake up input enable 0 to 15 0 (not_enable) = the corresponding wake-up input has no wake up effect. 1 (enable) = the corresponding wake-up input forces the wake up of the core power supply. ? wkupt0 - wkupt15: wake up input transition 0 to 15 0 (high_to_low) = a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. 1 (low_to_high) = a low to high level transition on the co rresponding wake-up input forces the wake up of the core power supply. 31 30 29 28 27 26 25 24 wkupt15 wkupt14 wkupt13 wkupt12 wkupt11 wkupt10 wkupt9 wkupt8 23 22 21 20 19 18 17 16 wkupt7 wkupt6 wkupt5 wkupt4 wkupt3 wkupt2 wkupt1 wkupt0 15 14 13 12 11 10 9 8 wkupen15 wkupen14 wkupen13 wkupen12 wkupen11 wkupen10 wkupen9 wkupen8 76543210 wkupen7 wkupen6 wkupen5 wkupen4 wkupen3 wkupen2 wkupen1 wkupen0
272 11011a?atarm?04-oct-10 sam3n 272 11011a?atarm?04-oct-10 sam3n 16.5.8 supply controller status register name: supc_sr address: 0x400e1424 access: read-write note: because of the asynchronism between the slow clock (sclk) and the system clock (mck), the status register flag reset is taken into account only 2 slow clock cycles after the read of the supc_sr. ? wkups: wkup wake up status 0 (no) = no wake up due to the assertion of the wkup pins has occurred since the last read of supc_sr. 1 (present) = at least one wake up due to the assertion of the wkup pins has occurred since the last read of supc_sr. ? smws: supply monitor detection wake up status 0 (no) = no wake up due to a supply monitor detection has occurred since the last read of supc_sr. 1 (present) = at least one wake up d ue to a supply monitor detection has oc curred since t he last read of supc_sr. ? bodrsts: brownout detector reset status 0 (no) = no core brownout rising edge event has been detected since the last read of the supc_sr. 1 (present) = at least one br ownout output rising edge event has been det ected since the last read of the supc_sr. when the voltage remains below the defined threshold, there is no rising edge event at the output of the brownout detec- tion cell. the rising edge event occurs only when there is a voltage transition below the threshold. ? smrsts: supply monitor reset status 0 (no) = no supply monitor detection has generated a core reset since the last read of the supc_sr. 1 (present) = at least one s upply monitor detection has ge nerated a core reset since t he last read of the supc_sr. ? sms: supply monitor status 0 (no) = no supply monitor detection since the last read of supc_sr. 1 (present) = at least one s upply monitor detection sinc e the last read of supc_sr. ? smos: supply monitor output status 0 (high) = the supply monitor detected vddio higher than its threshold at its last measurement. 1 (low) = the supply monitor detected vddio lower than its threshold at its last measurement. 31 30 29 28 27 26 25 24 wkupis15 wkupis14 wkupis13 wkupis12 wkupis11 wkupis10 wkupis9 wkupis8 23 22 21 20 19 18 17 16 wkupis7 wkupis6 wkupis5 wkupis4 wkupis3 wkupis2 wkupis1 wkupis0 15 14 13 12 11 10 9 8 ???????? 76543210 oscsel smos sms smrsts bodrsts smws wkups ?
273 11011a?atarm?04-oct-10 sam3n 273 11011a?atarm?04-oct-10 sam3n 17. general purpose backup registers (gpbr) 17.1 description the system controller embeds eight general-purpose backup registers. 17.2 embedded characteristics eight 32-bit general purpose backup registers 17.3 general purpose backup regist ers (gpbr) user interface table 17-1. register mapping offset register name access reset 0x0 general purpose backup register 0 sys_gpbr0 read-write ? ... ... ... ... ... 0x1c general purpose backup register 7 sys_gpbr7 read-write ?
274 11011a?atarm?04-oct-10 sam3n 274 11011a?atarm?04-oct-10 sam3n 17.3.0.1 general purpose backup register x name: sys_gpbrx addresses: 0x400e1490 [0] .. 0x400e149c [3] access: read-write ? gpbr_valuex: value of gpbr x 31 30 29 28 27 26 25 24 gpbr_valuex 23 22 21 20 19 18 17 16 gpbr_valuex 15 14 13 12 11 10 9 8 gpbr_valuex 76543210 gpbr_valuex
275 11011a?atarm?04-oct-10 sam3n 18. enhanced embedded flash controller (eefc) 18.1 description the enhanced embedded flash controller (eefc) ensures the interface of the flash block with the 32-bit internal bus. its 128-bit or 64-bit wide memory interface increases performance. it also manages the pro- gramming, erasing, locking and unlocking sequences of the flash using a full set of commands. one of the commands returns the embedded flash descriptor definition that informs the system about the flash organization, thus making the software generic. 18.2 product dependencies 18.2.1 power management the enhanced embedded flash controller (eefc) is continuously clocked. the power man- agement controller has no effect on its behavior. 18.2.2 interrupt sources the enhanced embedded flash controller (eefc) interrupt line is connected to the nested vectored interrupt controller (nvic). using the enhanced embedded flash controller (eefc) interrupt requires the nvic to be programmed first. the eefc interrupt is generated only on frdy bit rising. 18.3 functional description 18.3.1 embedded flash organization the embedded flash interfaces directly with the 32-bit internal bus. the embedded flash is composed of: ? one memory plane organized in several pages of the same size. ? two 128-bit or 64-bit read buffers used for code read optimization. ? one 128-bit or 64-bit read buffer used for data read optimization. ? one write buffer that manages page programming. the write buffer size is equal to the page size. this buffer is write-only and accessible all along the 1 mbyte address space, so that each word can be written to its final address. ? several lock bits used to protect write/erase operation on several pages (lock region). a lock bit is associated with a lock region composed of several pages in the memory plane. ? several bits that may be set and cleared through the enhanced embedded flash controller (eefc) interface, called general purpose non volatile memory bits (gpnvm bits). the embedded flash size, the page size, the lock regions organization and gpnvm bits defini- tion are described in the product definition section. the enhanced embedded flash controller (eefc) returns a descriptor of the flash controlled after a get descriptor command issued by the application (see ?getting embedded flash descriptor? on page 280 ). table 18-1. peripheral ids instance id efc 6
276 11011a?atarm?04-oct-10 sam3n figure 18-1. embedded flash organization start address page 0 lock region 0 lock region 1 memory plane page (m-1) lock region (n-1) page (n*m-1) start address + flash size -1 lock bit 0 lock bit 1 lock bit (n-1)
277 11011a?atarm?04-oct-10 sam3n 18.3.2 read operations an optimized controller manages embedded flash reads, thus increasing performance when the processor is running in thumb2 mode by means of the 128- or 64- bit wide memory interface. the flash memory is accessible through 8-, 16- and 32-bit reads. as the flash block size is smaller than the addr ess space reserved for the internal memory area, the embedded flash wraps around the address space and appears to be repeated within it. the read operations can be performed with or without wait states. wait states must be pro- grammed in the field fws (flash read wait state) in the flash mode register (eefc_fmr). defining fws to be 0 enables the single-cycle access of the embedded flash. refer to the elec- trical characteristics for more details. 18.3.2.1 128-bit or 64-bit access mode by default the read accesses of the flash are performed through a 128-bit wide memory inter- face. it enables better system performance especially when 2 or 3 wait state needed. for systems requiring only 1 wait state, or to privilege current consumption rather than perfor- mance, the user can select a 64-bit wide memory access via the fam bit in the flash mode register (eefc_fmr) please refer to the electrical characteristics section of the product datasheet for more details. 18.3.2.2 code read optimization a system of 2 x 128-bit or 2 x 64-bit buffers is added in order to optimize sequential code fetch. note: immediate consecutive code read accesses are not mandatory to benefit from this optimization. figure 18-2. code read optimization for fws = 0 note: when fws is equal to 0, all the accesses are perform ed in a single-cycle access. flash access buffer 0 (128bits) master clock arm request (32-bit) xxx data to arm bytes 0-15 bytes 16-31 bytes 32-47 bytes 0-15 buffer 1 (128bits) bytes 32-47 bytes 0-3 bytes 4-7 bytes 8-11 bytes 12-15 bytes 16-19 bytes 20-23 bytes 24-27 xxx xxx bytes 16-31 @byte 0 @byte 4 @byte 8 @byte 12 @byte 16 @byte 20 @byte 24 @byte 28 @byte 32 bytes 28-31
278 11011a?atarm?04-oct-10 sam3n figure 18-3. code read optimization for fws = 3 note: when fws is included between 1 and 3, in case of sequent ial reads, the first access takes (fws+1) cycles, the other ones o nly 1 cycle. 18.3.2.3 data read optimization the organization of the flash in 128 bits (or 64 bits) is associated with two 128-bit (or 64-bit) prefetch buffers and one 128-bit (or 64-bit) data read buffer, thus providing maximum system performance. this buffer is added in order to store the requested data plus all the data contained in the 128-bit (64-bit) aligned data. this speeds up sequential data reads if, for example, fws is equal to 1 (see figure 18-4 ). note: no consecutive data read accesses are ma ndatory to benefit from this optimization. figure 18-4. data read optimization for fws = 1 flash access buffer 0 (128bits) master clock arm request (32-bit) data to arm buffer 1 (128bits) 0-3 xxx xxx bytes 16-31 @byte 0 @4 @8 bytes 0-15 bytes 16-31 bytes 32-47 bytes 48-63 xxx bytes 0-15 4-7 8-11 12-15 @12 @16 @20 24-27 28-31 32-35 36-39 16-19 20-23 40-43 44-47 @24 @28 @32 @36 @40 @44 @48 @52 bytes 32-47 48-51 flash access buffer (128bits) master clock arm request (32-bit) xxx data to arm bytes 0-15 bytes 16-31 bytes 0-15 bytes 0-3 4-7 8-11 12-15 16-19 20-23 xxx bytes 16-31 @byte 0 @ 4 @ 8 @ 12 @ 16 @ 20 @ 24 @ 28 @ 32 @ 36 xxx bytes 32-47 24-27 28-31 32-35
279 11011a?atarm?04-oct-10 sam3n 18.3.3 flash commands the enhanced embedded flash controller (eefc) offers a set of commands such as program- ming the memory flash, locking and unlocking lock regions, consecutive programming and locking and full flash erasing, etc. commands and read operations can be performed in parallel only on different memory planes. code can be fetched from one memory plane while a write or an erase operation is performed on another. in order to perform one of these commands, the flash command register (eefc_fcr) has to be written with the correct command using the fcmd field. as soon as the eefc_fcr register is written, the frdy flag and the fvalue field in the eefc_frr register are automatically cleared . once the current command is achieved, then the frdy flag is automatically set. if an interrupt has been enabled by setting the frdy bit in eefc_fmr, the corresponding interrupt line of the nvic is activated. (note that this is true for all commands except for the stui com- mand. the frdy flag is not set when the stui command is achieved.) all the commands are protected by the same keyw ord, which has to be written in the 8 highest bits of the eefc_fcr register. writing eefc_fcr with data that does not contain the correct key and/or with an invalid com- mand has no effect on the whole memory plane, but the fcmde flag is set in the eefc_fsr register. this flag is automatically cleared by a read access to the eefc_fsr register. when the current command writes or erases a page in a locked region, the command has no effect on the whole memory plane, but the flocke flag is set in the eefc_fsr register. this flag is automatically cleared by a read access to the eefc_fsr register. table 18-2. set of commands command value mnemonic get flash descriptor 0x00 getd write page 0x01 wp write page and lock 0x02 wpl erase page and write page 0x03 ewp erase page and write page then lock 0x04 ewpl erase all 0x05 ea set lock bit 0x08 slb clear lock bit 0x09 clb get lock bit 0x0a glb set gpnvm bit 0x0b sgpb clear gpnvm bit 0x0c cgpb get gpnvm bit 0x0d ggpb start read unique identifier 0x0e stui stop read unique identifier 0x0f spui get calib bit 0x10 gcalb
280 11011a?atarm?04-oct-10 sam3n figure 18-5. command state chart 18.3.3.1 getting embedded flash descriptor this command allows the system to learn about the flash organization. the system can take full advantage of this information. for instance, a device could be replaced by one with more flash capacity, and so the software is able to adapt itself to the new configuration. to get the embedded flash descriptor, the application writes the getd command in the eefc_fcr register. the first word of the descriptor can be read by the software application in the eefc_frr register as soon as the frdy flag in the eefc_fsr register rises. the next reads of the eefc_frr register provide the following word of the descriptor. if extra read oper- check if frdy flag set no yes read status: mc_fsr write fcmd and pagenb in flash command register check if flocke flag set check if frdy flag set no read status: mc_fsr yes yes locking region violation no check if fcmde flag set yes no bad keyword violation command successfull
281 11011a?atarm?04-oct-10 sam3n ations to the eefc_frr register are done after the last word of the descriptor has been returned, then the eefc_frr register value is 0 until the next valid command. 18.3.3.2 write commands several commands can be used to program the flash. flash technology requires that an erase is done before programming. the full memory plane can be erased at the same time, or several pages can be erased at the same time (refer to section ?the partial programming mode works only with 128-bit (or higher) boundaries. it cannot be used with boundaries lower than 128 bits (8, 16 or 32-bit for example).? ). also, a page erase can be automatically done before a page write using ewp or ewpl commands. after programming, the page (the whole lock region) can be locked to prevent miscellaneous write or erase sequences. the lock bit can be automatically set after page programming using wpl or ewpl commands. data to be written are stored in an internal latch buffer. the size of the latch buffer corresponds to the page size. the latch buffer wraps around within the internal memory area address space and is repeated as many times as the number of pages within this address space. note: writing of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption. write operations are performed in a number of wait states equal to the number of wait states for read operations. data are written to the latch buffer before the programming command is written to the flash command register eefc_fcr. the sequence is as follows: ? write the full page, at any page address, within the internal memory area address space. ? programming starts as soon as the page number and the programming command are written to the flash command register. the frdy bit in the flash programming status register (eefc_fsr) is auto matically cleared. ? when programming is completed, the frdy bit in the flash programming status register (eefc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in eefc_fmr, the corresponding interrupt line of the nvic is activated. table 18-3. flash descriptor definition symbol word index description fl_id 0 flash interface description fl_size 1 flash size in bytes fl_page_size 2 page size in bytes fl_nb_plane 3 number of planes. fl_plane[0] 4 number of bytes in the first plane. ... fl_plane[fl_nb_plane-1] 4 + fl_nb_plane - 1 number of bytes in the last plane. fl_nb_lock 4 + fl_nb_plane number of lock bits. a bit is associated with a lock region. a lock bit is used to prevent write or erase operations in the lock region. fl_lock[0] 4 + fl_nb_plane + 1 number of bytes in the first lock region. ...
282 11011a?atarm?04-oct-10 sam3n two errors can be detected in the eefc_fsr register after a programming sequence: ? a command error: a bad keyword has been written in the eefc_fcr register. ? a lock error: the page to be programmed belongs to a locked region. a command must be previously run to unlock the corresponding region. by using the wp command, a page can be programmed in several steps if it has been erased before (see figure 18-6 ). figure 18-6. example of partial page programming the partial programming mode works only with 128-bit (or higher) boundaries. it cannot be used with boundaries lower than 128 bits (8, 16 or 32-bit for example). 18.3.3.3 erase commands erase commands are allowed only on unlocked regions. the erase sequence is: ? erase starts as soon as one of the erase commands and the farg field are written in the flash command register. ? when the programming completes, the frdy bit in the flash programming status register (eefc_fsr) rises. if an interrupt has been enabled by setting the frdy bit in eefc_fmr, the interrupt line of the nvic is activated. two errors can be detected in the eefc_fsr register after a programming sequence: ? a command error: a bad keyword has been written in the eefc_fcr register. ? a lock error: at least one page to be erased belongs to a locked region. the erase command has been refused, no page has been erased. a command must be run previously to unlock the corresponding region. 18.3.3.4 lock bit protection lock bits are associated with several pages in the embedded flash memory plane. this defines lock regions in the embedded flash memory plane. they prevent writing/erasing protected pages. erase all flash programming of the second part of page y programming of the third part of page y 32-bit wide 32-bit wide 32-bit wide x words ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ... ca fe ca fe ca fe ca fe ca fe ca fe ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ca fe ca fe ca fe ca fe ca fe ca fe de ca de ca de ca de ca de ca de ca ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff step 1. step 2. step 3. ... ... ... ... ... ... ... ... ... ... ... x words x words x words so page y erased
283 11011a?atarm?04-oct-10 sam3n the lock sequence is: ? the set lock command (slb) and a page number to be protected are written in the flash command register. ? when the locking completes, the frdy bit in the flash programming status register (eefc_fsr) rises. if an interrupt has been enabled by setting the frdy bit in eefc_fmr, the interrupt line of the nvic is activated. ? if the lock bit number is greater than the total number of lock bits, then the command has no effect. the result of the slb command can be checked running a glb (get lock bit) command. one error can be detected in the eefc_fsr register after a programming sequence: ? a command error: a bad keyword has been written in the eefc_fcr register. it is possible to clear lock bits previously set. then the locked region can be erased or pro- grammed. the unlock sequence is: ? the clear lock command (clb) and a page number to be unprotected are written in the flash command register. ? when the unlock completes, the frdy bit in the flash programming status register (eefc_fsr) rises. if an interrupt has been enabled by setting the frdy bit in eefc_fmr, the interrupt line of the nvic is activated. ? if the lock bit number is greater than the total number of lock bits, then the command has no effect. one error can be detected in the eefc_fsr register after a programming sequence: ? a command error: a bad keyword has been written in the eefc_fcr register. the status of lock bits can be returned by the enhanced embedded flash controller (eefc). the get lock bit status sequence is: ? the get lock bit command (glb) is written in the flash command register, farg field is meaningless. ? lock bits can be read by the software application in the eefc_frr register. the first word read corresponds to the 32 first lock bits, next reads providing the next 32 lock bits as long as it is meaningful. extra reads to the eefc_frr register return 0. for example, if the third bit of the first word read in the eefc_frr is set, then the third lock region is locked. one error can be detected in the eefc_fsr register after a programming sequence: ? a command error: a bad keyword has been written in the eefc_fcr register. note: access to the flash in read is permitted when a set, clear or get lock bit command is performed. 18.3.3.5 gpnvm bit gpnvm bits do not interfere with the embedded fl ash memory plane. refer to the product defi- nition section for information on the gpnvm bit action. the set gpnvm bit sequence is: ? start the set gpnvm bit command (sgpb) by writing the flash command register with the sgpb command and the number of the gpnvm bit to be set.
284 11011a?atarm?04-oct-10 sam3n ? when the gpvnm bit is set, the bit frdy in the flash programming status register (eefc_fsr) rises. if an interrupt was enabled by setting the frdy bit in eefc_fmr, the interrupt line of the nvic is activated. ? if the gpnvm bit number is greater than the total number of gpnvm bits, then the command has no effect. the result of the sgpb command can be checked by running a ggpb (get gpnvm bit) command. one error can be detected in the eefc_fsr register after a programming sequence: ? a command error: a bad keyword has been written in the eefc_fcr register. it is possible to clear gpnvm bits previo usly set. the clear gpnvm bit sequence is: ? start the clear gpnvm bit command (cgpb) by writing the flash command register with cgpb and the number of the gpnvm bit to be cleared. ? when the clear completes, the frdy bit in the flash programming status register (eefc_fsr) rises. if an interrupt has been enabled by setting the frdy bit in eefc_fmr, the interrupt line of the nvic is activated. ? if the gpnvm bit number is greater than the total number of gpnvm bits, then the command has no effect. one error can be detected in the eefc_fsr register after a programming sequence: ? a command error: a bad keyword has been written in the eefc_fcr register. the status of gpnvm bits can be returned by the enhanced embedded flash controller (eefc). the sequence is: ? start the get gpnvm bit command by writing the flash command register with ggpb. the farg field is meaningless. ? gpnvm bits can be read by the software application in the eefc_frr register. the first word read corresponds to the 32 first gpnvm bits, following reads provide the next 32 gpnvm bits as long as it is meaningful. extr a reads to the eefc_frr register return 0. for example, if the third bit of the first word read in the eefc_frr is set, then the third gpnvm bit is active. one error can be detected in the eefc_fsr register after a programming sequence: ? a command error: a bad keyword has been written in the eefc_fcr register. note: access to the flash in read is permitted w hen a set, clear or get gpnvm bit command is performed. 18.3.3.6 calibration bit calibration bits do not interfere with the embedded flash memory plane. it is impossible to modify the calibration bits. the status of calibration bits can be returned by the enhanced embedded flash controller (eefc). the sequence is: ? issue the get calib bit command by writing the flash command register with gcalb (see table 18-2 ). the farg field is meaningless. ? calibration bits can be read by the software application in the eefc_frr register. the first word read corresponds to the 32 first calibration bits, following reads provide the next 32 calibration bits as long as it is meaningful. extra reads to the eefc_frr register return 0.
285 11011a?atarm?04-oct-10 sam3n the 4/8/12 mhz fast rc oscillato r is calibrated in production. this calibration can be read through the get calib bit command. the table below shows the bit implementation for each frequency: the rc calibration for 4 mhz is set to 1,000,000. 18.3.3.7 security bit protection when the security is enabled, access to the flash, either through the jtag/swd interface or through the fast flash programming interface, is forbidden. this ensures the confidentiality of the code programmed in the flash. the security bit is gpnvm0. disabling the security bit can only be achieved by asserti ng the erase pin at 1, and after a full flash erase is performed. when the security bit is deactivated, all accesses to the flash are permitted. 18.3.3.8 unique identifier each part is programmed with a 128-bit unique identifier. it can be used to generate keys for example. to read the unique identifier the sequence is: ? send the start read unique identifier command (stui) by writing the flash command register with the stui command. ? when the unique identifier is ready to be read, the frdy bit in the flash programming status register (eefc_fsr) falls. ? the unique identifier is located in the first 128 bits of the flash memory mapping. so, at the address 0x80000-0x8000f . ? to stop the unique identifier mode, the user needs to send the stop read unique identifier command (spui) by writing the flash co mmand register with the spui command. ? when the stop read unique identifier command (spui) has been performed, the frdy bit in the flash programming status register (eefc_fsr) rises. if an interrupt was enabled by setting the frdy bit in eefc_fmr, the interrupt line of the nvic is activated. note that during the sequence, the software can not run out of flash (or the second plane in case of dual plane). rc calibration frequency eefc_frr bits 8 mhz output [28 - 22] 12 mhz output [38 - 32]
286 11011a?atarm?04-oct-10 sam3n 18.4 enhanced embedded flash controll er (eefc) user interface the user interface of the enhanced embedded flash controller (eefc) is integrated within the system controller with base address 0x400e0800 . table 18-4. register mapping offset register name access reset state 0x00 eefc flash mode register eefc _fmr read-write 0x0 0x04 eefc flash command register eefc _fcr write-only ? 0x08 eefc flash status register eefc _fsr read-only 0x00000001 0x0c eefc flash result register eefc _frr read-only 0x0 0x10 reserved ? ? ?
287 11011a?atarm?04-oct-10 sam3n 18.4.1 eefc flash mode register name: eefc_fmr address: 0x400e0a00 access: read-write offset :0x00 ? frdy: ready interrupt enable 0: flash ready does not generate an interrupt. 1: flash ready (to accept a new command) generates an interrupt. ? fws: flash wait state this field defines the number of wait states for read and write operations: number of cycles for read/write operations = fws+1 ? fam: flash access mode 0: 128-bit access in read mode only, to enhance access speed. 1: 64-bit access in read mode only, to enhance power consumption. no flash read should be done during change of this register. 31 30 29 28 27 26 25 24 ???????fam 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? fws 76543210 ? ?????frdy
288 11011a?atarm?04-oct-10 sam3n 18.4.2 eefc flash command register name: eefc_fcr address: 0x400e0a04 access: write-only offset :0x04 ? fcmd: flash command this field defines the flash commands. refer to ?flash commands? on page 279 . ? farg: flash command argument ? fkey: flash writing protection key this field should be written with the value 0x5a to enable the command defined by the bits of the register. if the field is wri t- ten with a different value, the write is not performed and no action is started. 31 30 29 28 27 26 25 24 fkey 23 22 21 20 19 18 17 16 farg 15 14 13 12 11 10 9 8 farg 76543210 fcmd erase command for erase all command, this field is meaningless. programming command farg defines the page number to be programmed. lock command farg defines the page number to be locked. gpnvm command farg defines the gpnvm number. get commands field is meaningless. unique identifier commands field is meaningless.
289 11011a?atarm?04-oct-10 sam3n 18.4.3 eefc flash status register name: eefc_fsr address: 0x400e0a08 access: read-only offset :0x08 ? frdy: flash ready status 0: the enhanced embedded flash controller (eefc) is busy. 1: the enhanced embedded flash controller (eefc) is ready to start a new command. when it is set, this flags triggers an interrupt if the frdy flag is set in the eefc_fmr register. this flag is automatically cleared when the en hanced embedded flash controller (eefc) is busy. ? fcmde: flash command error status 0: no invalid commands and no bad keywords were written in the flash mode register eefc_fmr. 1: an invalid command and/or a bad keyword was/were written in the flash mode register eefc_fmr. this flag is automatically cleared when eefc_fsr is read or eefc_fcr is written. ? flocke: flash lock error status 0: no programming/erase of at least one locked region has happened since the last read of eefc_fsr. 1: programming/erase of at least one locked region has happened since the last read of eefc_fsr. this flag is automatically cleared when eefc_fsr is read or eefc_fcr is written. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????flockefcmdefrdy
290 11011a?atarm?04-oct-10 sam3n 18.4.4 eefc flash result register name: eefc_frr address: 0x400e0a0c access: read-only offset :0x0c ? fvalue: flash result value the result of a flash command is returned in this register. if the size of the result is greater than 32 bits, then the next resulting value is accessible at the next register read. 31 30 29 28 27 26 25 24 fvalue 23 22 21 20 19 18 17 16 fvalue 15 14 13 12 11 10 9 8 fvalue 76543210 fvalue
291 11011a?atarm?04-oct-10 sam3n 19. fast flash programming interface (ffpi) 19.1 description the fast flash programming interface provides parallel high-volume programming using a stan- dard gang programmer. the parallel interface is fully handshaked and the device is considered to be a standard eeprom. additionally, the parallel protocol offers an optimized access to all the embedded flash functionalities. although the fast flash programming mode is a dedicated mode for high volume programming, this mode is not designed for in-situ programming. 19.2 parallel fast flash programming 19.2.1 device configuration in fast flash programming mode, the device is in a specific test mode. only a certain set of pins is significant. the rest of the pios are used as inputs with a pull-up. the crystal oscillator is in bypass mode. other pins must be left unconnected. figure 19-1. sam3nxa (48 bits) parallel programming interface figure 19-2. sam3nxb/c (64/100 pins) parallel programming interface ncmd pgmncmd rdy pgmrdy noe pgmnoe nvalid pgmnvalid mode[3:0] pgmm[3:0] data[7:0] pgmd[7:0] xin tst vddio pgmen0 pgmen1 0 - 50mhz vddio vddcore vddio vddpll gnd gnd vddio pgmen2 ncmd pgmncmd rdy pgmrdy noe pgmnoe nvalid pgmnvalid mode[3:0] pgmm[3:0] data[15:0] pgmd[15:0] xin tst vddio pgmen0 pgmen1 0 - 50mhz vddio vddcore vddio vddpll gnd gnd vddio pgmen2
292 11011a?atarm?04-oct-10 sam3n notes: 1. data[7:0] pertains to the sam3nxa (48 bits). 2. pgmd[7:0] pertains to the sam3nxa (48 bits). table 19-1. signal description list signal name function type active level comments power vddio i/o lines power supply power vddcore core power supply power vddpll pll power supply power gnd ground ground clocks xin main clock input. this input can be tied to gnd. in this case, the device is clocked by the internal rc oscillator. input 32khz to 50mhz test tst test mode select input high must be connected to vddio pgmen0 test mode select input high must be connected to vddio pgmen1 test mode select input high must be connected to vddio pgmen2 test mode select input l ow must be connected to gnd pio pgmncmd valid command available input low pulled-up input at reset pgmrdy 0: device is busy 1: device is ready for a new command output high pulled-up input at reset pgmnoe output enable (active high ) input low pulled-up input at reset pgmnvalid 0: data[15:0] or data[7:0] (1) is in input mode 1: data[15:0] or data[7:0] (1) is in output mode output low pulled-up input at reset pgmm[3:0] specifies data type (see table 19-2 ) input pulled-up input at reset pgmd[15:0] or [7:0] (2) bi-directional data bus input/o utput pulled-up input at reset
293 11011a?atarm?04-oct-10 sam3n 19.2.2 signal names depending on the mode settings, data is latched in different internal registers. when mode is equal to cmde, then a new command (strobed on data[15:0] or data[7:0] signals) is stored in the command register. note: data[7:0] pertains to sam3nxa (48 pins). table 19-2. mode coding mode[3:0] symbol data 0000 cmde command register 0001 addr0 address register lsbs 0010 addr1 0011 addr2 0100 addr3 address register msbs 0101 data data register default idle no register table 19-3. command bit coding data[15:0] symbol command executed 0x0011 read read flash 0x0012 wp write page flash 0x0022 wpl write page and lock flash 0x0032 ewp erase page and write page 0x0042 ewpl erase page and write page then lock 0x0013 ea erase all 0x0014 slb set lock bit 0x0024 clb clear lock bit 0x0015 glb get lock bit 0x0034 sgpb set general purpose nvm bit 0x0044 cgpb clear general purpose nvm bit 0x0025 ggpb get general purpose nvm bit 0x0054 sse set security bit 0x0035 gse get security bit 0x001f wram write memory 0x001e gve get version
294 11011a?atarm?04-oct-10 sam3n 19.2.3 entering programming mode the following algorithm puts the devi ce in parallel programming mode: ? apply gnd, vddio, vddcore and vddpll. ? apply xin clock within t por_reset if an external clock is available. ?wait for t por_reset ? start a read or write handshaking. note: after reset, the device is clocked by the internal rc oscillator. before clearing rdy signal, if an external clock ( > 32 khz) is connected to xin, then the device switches on the external clock. else, xin input is not considered. a highe r frequency on xin speeds up the programmer handshake. 19.2.4 programmer handshaking an handshake is defined for read and write operations. when the device is ready to start a new operation (rdy signal set), the programmer star ts the handshake by clearing the ncmd signal. the handshaking is achieved once nc md signal is high and rdy is high. 19.2.4.1 write handshaking for details on the write handshaking sequence, refer to figure 19-3 figure 19-4 and table 19-4 . figure 19-3. sam3nxb/c (64/100 pins) parallel programming timing, write sequence ncmd rdy noe nvalid data[7:0] mode[3:0] 1 2 3 4 5
295 11011a?atarm?04-oct-10 sam3n figure 19-4. sam3nxa (48 pins) parallel programming timing, write sequence 19.2.4.2 read handshaking for details on the read han dshaking sequenc e, refer to figure 19-5 figure 19-6 and table 19-5 . figure 19-5. sam3nxb/c (64/100 pins) parallel programming timing, read sequence ncmd rdy noe nvalid data[15:0] mode[3:0] 1 2 3 4 5 table 19-4. write handshake step programmer action device action data i/o 1 sets mode and data signals waits for ncmd low input 2 clears ncmd signal latches mode and data input 3 waits for rdy low clears rdy signal input 4 releases mode and data signals executes command and polls ncmd high input 5 sets ncmd signal executes command and polls ncmd high input 6 waits for rdy high sets rdy input ncmd rdy noe nvalid data[7:0] mode[3:0] 1 2 3 4 5 6 7 9 8 addr adress in z data out 10 11 xin 12 13
296 11011a?atarm?04-oct-10 sam3n figure 19-6. sam3nxa (48 pins) parallel programming timing, read sequence ncmd rdy noe nvalid data[15:0] mode[3:0] 1 2 3 4 5 6 7 9 8 addr adress in z data out 10 11 xin 12 13 table 19-5. read handshake step programmer action device action data i/o 1 sets mode and data signals waits for ncmd low input 2 clears ncmd signal latch mode and data input 3 waits for rdy low clears rdy signal input 4 sets data signal in tristate waits for noe low input 5 clears noe signal tr i s t a t e 6 waits for nvalid low sets data bus in output mode and outputs the flash contents. output 7 clears nvalid signal output 8 reads value on data bus waits for noe high output 9 sets noe signal output 10 waits for nvalid high sets data bus in input mode x 11 sets data in output mode sets nvalid signal input 12 sets ncmd signal waits for ncmd high input 13 waits for rdy high sets rdy signal input
297 11011a?atarm?04-oct-10 sam3n 19.2.5 device operations several commands on the flash memory are available. these commands are summarized in table 19-3 on page 293 . each command is driven by the programmer through the parallel inter- face running several read/write handshaking sequences. when a new command is executed, the previous one is automatically achieved. thus, chaining a read command after a write automatically flushes the load buffer in the flash. in the following tables, table 19-6 through table 19-17 ? data[15:0] pertains to asam3nxb/c (64/100 pins) ? data[7:0] pertains to sam3bxa (48 pins) 19.2.5.1 flash read command this command is used to read the contents of the flash memory. the read command can start at any valid address in the memory plane and is optimized for consecutive reads. read hand- shaking can be chained; an internal address buffer is automatically increased. table 19-6. read command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde read 2 write handshaking addr0 memory address lsb 3 write handshaking addr1 memory address 4 read handshaking data *memory address++ 5 read handshaking data *memory address++ ... ... ... ... n write handshaking addr0 memory address lsb n+1 write handshaking addr1 memory address n+2 read handshaking data *memory address++ n+3 read handshaking data *memory address++ ... ... ... ... table 19-7. read command step handshake sequence mode[3:0] data[7:0] 1 write handshaking cmde read 2 write handshaking addr0 memory address lsb 3 write handshaking addr1 memory address 4 write handshaking addr2 memory address 5 write handshaking addr3 memory address 6 read handshaking data *memory address++ 7 read handshaking data *memory address++ ... ... ... ... n write handshaking addr0 memory address lsb
298 11011a?atarm?04-oct-10 sam3n 19.2.5.2 flash write command this command is used to write the flash contents. the flash memory plane is organized into several pages. data to be written are stored in a load buffer that corresponds to a flash memory page. the load buffer is automatically flushed to the flash: ? before access to any page other than the current one ? when a new command is validated (mode = cmde) the write page command (wp) is optimized for consecutive writes. write handshaking can be chained; an internal address buffer is automatically increased. n+1 write handshaking addr1 memory address n+2 write handshaking addr2 memory address n+3 write handshaking addr3 memory address n+4 read handshaking data *memory address++ n+5 read handshaking data *memory address++ ... ... ... ... table 19-7. read command (continued) step handshake sequence mode[3:0] data[7:0] table 19-8. write command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde wp or wpl or ewp or ewpl 2 write handshaking addr0 memory address lsb 3 write handshaking addr1 memory address 4 write handshaking data *memory address++ 5 write handshaking data *memory address++ ... ... ... ... n write handshaking addr0 memory address lsb n+1 write handshaking addr1 memory address n+2 write handshaking data *memory address++ n+3 write handshaking data *memory address++ ... ... ... ... table 19-9. write command step handshake sequence mode[3:0] data[7:0] 1 write handshaking cmde wp or wpl or ewp or ewpl 2 write handshaking addr0 memory address lsb 3 write handshaking addr1 memory address 4 write handshaking addr2 memory address
299 11011a?atarm?04-oct-10 sam3n the flash command write page and lock (wpl) is equivalent to the flash write command. however, the lock bit is automatically set at the end of the flash write operation. as a lock region is composed of several pages, the programmer writes to the first pages of the lock region using flash write commands and writes to the last page of the lock region using a flash write and lock command. the flash command erase page and write (ewp) is equivalent to the flash write command. however, before programming the load buffer, the page is erased. the flash command erase page and write the lock (ewpl) combines ewp and wpl commands. 19.2.5.3 flash full erase command this command is used to erase the flash memory planes. all lock regions must be unlocked before the full erase command by using the clb command. otherwise, the erase command is aborted and no page is erased. 19.2.5.4 flash lock commands lock bits can be set using wpl or ewpl co mmands. they can also be set by using the set lock command (slb) . with this command, several lock bits can be activated. a bit mask is pro- vided as argument to the command. when bit 0 of the bit mask is set, then the first lock bit is activated. 5 write handshaking addr3 memory address 6 write handshaking data *memory address++ 7 write handshaking data *memory address++ ... ... ... ... n write handshaking addr0 memory address lsb n+1 write handshaking addr1 memory address n+2 write handshaking addr2 memory address n+3 write handshaking addr3 memory address n+4 write handshaking data *memory address++ n+5 write handshaking data *memory address++ ... ... ... ... table 19-9. write command (continued) step handshake sequence mode[3:0] data[7:0] table 19-10. full erase command step handshake sequence mode[3:0] data[15:0] or data[7:0] 1 write handshaking cmde ea 2 write handshaking data 0
300 11011a?atarm?04-oct-10 sam3n in the same way, the clear lock command (clb) is used to clear lock bits. lock bits can be read using get lock bit command (glb) . the n th lock bit is active when the bit n of the bit mask is set.. 19.2.5.5 flash general-purpose nvm commands general-purpose nvm bits (gp nvm bits) can be set using the set gpnvm command (sgpb) . this command also activates gp nvm bits. a bit mask is provided as argument to the com- mand. when bit 0 of the bit mask is set, then the first gp nvm bit is activated. in the same way, the clear gpnvm command (cgpb) is used to clear general-purpose nvm bits. the general-purpose nvm bit is deactivated when the corresponding bit in the pattern value is set to 1. general-purpose nvm bits can be read using the get gpnvm bit command (ggpb) . the n th gp nvm bit is active when bit n of the bit mask is set.. table 19-11. set and clear lock bit command step handshake sequence mode[3:0] data[15:0] or data[7:0] 1 write handshaking cmde slb or clb 2 write handshaking data bit mask table 19-12. get lock bit command step handshake sequence mode[3:0] data[15:0] or data[7:0] 1 write handshaking cmde glb 2 read handshaking data lock bit mask status 0 = lock bit is cleared 1 = lock bit is set table 19-13. set/clear gp nvm command step handshake sequence mode[3:0] data[15:0] or data[7:0] 1 write handshaking cmde sgpb or cgpb 2 write handshaking data gp nvm bit pattern value table 19-14. get gp nvm bit command step handshake sequence mode[3:0] data[15:0] or data[7:0] 1 write handshaking cmde ggpb 2 read handshaking data gp nvm bit mask status 0 = gp nvm bit is cleared 1 = gp nvm bit is set
301 11011a?atarm?04-oct-10 sam3n 19.2.5.6 flash security bit command a security bit can be set using the set security bit command (sse). once the security bit is active, the fast flash programming is disabled. no other command can be run. an event on the erase pin can erase the security bit once th e contents of the flash have been erased. once the security bit is set, it is not possible to access ffpi. the only way to erase the security bit is to erase the flash. in order to erase the flash, the user must perform the following: ? power-off the chip ? power-on the chip with tst = 0 ? assert erase during a period of more than 220 ms ? power-off the chip then it is possible to return to ffpi mode and check that flash is erased. 19.2.5.7 memory write command this command is used to perform a write access to any memory location. the memory write command (wram) is optimized for consecutive writes. write handshaking can be chained; an internal address buffer is automatically increased. table 19-15. set security bit command step handshake sequence mode[3:0] data[15:0] or data[7:0] 1 write handshaking cmde sse 2 write handshaking data 0 table 19-16. write command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde wram 2 write handshaking addr0 memory address lsb 3 write handshaking addr1 memory address 4 write handshaking data *memory address++ 5 write handshaking data *memory address++ ... ... ... ... n write handshaking addr0 memory address lsb n+1 write handshaking addr1 memory address n+2 write handshaking data *memory address++ n+3 write handshaking data *memory address++ ... ... ... ...
302 11011a?atarm?04-oct-10 sam3n 19.2.5.8 get version command the get version (gve) command retrieves the version of the ffpi interface. table 19-17. write command step handshake sequence mode[3:0] data[7:0] 1 write handshaking cmde wram 2 write handshaking addr0 memory address lsb 3 write handshaking addr1 memory address 4 write handshaking addr2 memory address 5 write handshaking addr3 memory address 6 write handshaking data *memory address++ 7 write handshaking data *memory address++ ... ... ... ... n write handshaking addr0 memory address lsb n+1 write handshaking addr1 memory address n+2 write handshaking addr2 memory address n+3 write handshaking addr3 memory address n+4 write handshaking data *memory address++ n+5 write handshaking data *memory address++ ... ... ... ... table 19-18. get version command step handshake sequence mode[3 :0] data[15:0] or data[7:0] 1 write handshaking cmde gve 2 write handshaking data version
303 11011a?atarm?04-oct-10 sam3n 20. sam3n boot program 20.1 description the sam-ba ? boot program integrates an array of programs permitting download and/or upload into the different memories of the product. 20.2 hardware and software constraints ? sam-ba boot uses the first 2048 bytes of the sram for variables and stacks. the remaining available size can be used for user's code. ? uart0 requirements: none 20.3 flow diagram the boot program implements the algorithm in figure 20-1 . figure 20-1. boot program algorithm flow diagram the sam-ba boot program uses th e internal 12 mhz rc oscillator as source clock for pll. the mck runs from pll divided by 2. the core runs at 48 mhz. 20.4 device initialization initialization follows the steps described below: 1. stack setup 2. setup the embedded flash controller 3. switch on internal 12 mhz rc oscillator 4. configure pll to run at 96 mhz 5. switch mck to run on pll divided by 2 6. configure uart0 7. disable watchdog 8. wait for a character on uart0 9. jump to sam-ba monitor (see section 20.5 ?sam-ba monitor? ) table 20-1. pins driven during boot program execution peripheral pin pio line uart0 urxd0 pa9 uart0 utxd0 pa10 device setup character # received from uart0? run sam-ba monitor ye s no
304 11011a?atarm?04-oct-10 sam3n 20.5 sam-ba monitor the sam-ba boot principle: once the communication interface is identified, to run in an infinite loop waiting for different com- mands as shown in table 20-2 . ? mode commands: ? normal mode configures sam-ba monitor to send/receive data in binary format, ? terminal mode configures sam-ba monitor to send/receive data in ascii format. ? write commands: write a byte ( o ), a halfword ( h ) or a word ( w ) to the target. ? address : address in hexadecimal. ? value : byte, halfword or word to write in hexadecimal. ? output : ?>?. ? read commands: read a byte ( o ), a halfword ( h ) or a word ( w ) from the target. ? address : address in hexadecimal ? output : the byte, halfword or word read in hexadecimal following by ?>? ? send a file ( s ): send a file to a specified address ? address : address in hexadecimal ? output : ?>?. note: there is a time-out on this command which is reached when the prompt ?>? appears before the end of the command execution. ? receive a file ( r ): receive data into a file from a specified address ? address : address in hexadecimal ? nbofbytes : number of bytes in hexadecimal to receive ? output : ?>? ?go ( g ): jump to a specified address and execute the code ? address : address to jump in hexadecimal table 20-2. commands available through the sam-ba boot command action argument(s) example n set normal mode no argument n # t set terminal mode no argument t # o write a byte address, value# o 200001,ca# o read a byte address,# o 200001,# h write a half word address, value# h 200002,cafe# h read a half word address,# h 200002,# w write a word address, value# w 200000,cafedeca# w read a word address,# w 200000,# s send a file address,# s 200000,# r receive a file address, nbofbytes# r 200000,1234# g go address# g 200200# v display version no argument v #
305 11011a?atarm?04-oct-10 sam3n ? output : ?>? ? get version ( v ): return the sam-ba boot version ? output : ?>? 20.5.1 uart0 serial port communication is performed through the uart0 initialized to 115200 baud, 8, n, 1. the send and receive file commands use the xmodem protocol to communicate. any terminal performing this protocol can be used to send th e application file to the target. the size of the binary file to send depends on the sram size embedded in the product. in all cases, the size of the binary file must be lower than the sram si ze because the xmodem protocol requires some sram memory to work. see, section 20.2 ?hardware and software constraints? 20.5.2 xmodem protocol the xmodem protocol supported is the 128-byte l ength block. this protocol uses a two-charac- ter crc-16 to guarantee detection of a maximum bit error. xmodem protocol with crc is accurate provided both sender and receiver report successful transmission. each block of the transfer looks like: <255-blk #><--128 da ta bytes--> in which: ? = 01 hex ? = binary number, starts at 01, increments by 1, and wraps 0ffh to 00h (not to 01) ? <255-blk #> = 1?s complement of the blk#. ? = 2 bytes crc16 figure 20-2 shows a transmission using this protocol. figure 20-2. xmodem transfer example host device soh 01 fe data[128] crc crc c ack soh 02 fd data[128] crc crc ack soh 03 fc data[100] crc crc ack eot ack
306 11011a?atarm?04-oct-10 sam3n 20.5.3 in application programming (iap) feature the iap feature is a function located in rom that can be called by any software application. when called, this function sends the desired flash command to the eefc and waits for the flash to be ready (looping while the frdy bit is not set in the mc_fsr register). since this function is executed from rom, this allows flash programming (such as sector write) to be done by code running in flash. the iap function entry point is retrieved by reading the nmi vector in rom (0x00800008). this function takes one argument in parameter: the command to be sent to the eefc. this function returns the value of the mc_fsr register. iap software code example: (unsigned int) (*iap_function)(unsigned long); void main (void){ unsigned long flashsectornum = 200; // unsigned long flash_cmd = 0; unsigned long flash_status = 0; unsigned long efcindex = 0; // 0:eefc0, 1: eefc1 /* initialize the function pointer (retrieve function address from nmi vector) */ iap_function = ((unsigned long) (*)(unsigned long)) 0x00800008; /* send your data to the sector here */ /* build the command to send to eefc */ flash_cmd = (0x5a << 24) | (flashsectornum << 8) | at91c_mc_fcmd_ewp; /* call the iap function with appropriate command */ flash_status = iap_function (efcindex, flash_cmd); }
307 11011a?atarm?04-oct-10 sam3n 21. bus matrix (matrix) 21.1 description the bus matrix implements a multi-layer ahb that enables parallel access paths between multi- ple ahb masters and slaves in a system, which increases the overall bandwidth. bus matrix interconnects 3 ahb masters to 4 ahb slaves. the normal latency to connect a master to a slave is one cycle except for the default mast er of the accessed slave which is connected directly (zero cycle latency). the bus matrix user interface also provides a ch ip configuration user interface with registers that allow to support application specific features. 21.2 embedded characteristics 21.2.1 matrix masters the bus matrix of the sam3n product manages 3 masters, which means th at each master can perform an access concurrently with others, to an available slave. each master has its own decoder, which is defined specifically for each master. in order to sim- plify the addressing, all the masters have the same decodings. 21.2.2 matrix slaves the bus matrix of the sam3n product manages 4 slaves. each slave has its own arbiter, allow- ing a different arbitration per slave. table 21-1. list of bus matrix masters master 0 cortex-m3 instruction/data master 1 cortex-m3 system master 2 peripheral dma controller (pdc) list of bus matrix slaves slave 0 internal sram slave 1 internal rom slave 2 internal flash slave 3 peripheral bridge
308 11011a?atarm?04-oct-10 sam3n 21.2.3 master to slave access all the masters can normally access all the slaves. however, some paths do not make sense, for example allowing access from the cortex-m3 s bus to the internal rom. thus, these paths are forbidden or simply not wired and shown as ?-? in the following table. 21.3 memory mapping bus matrix provides one decoder for every ahb master interface. the decoder offers each ahb master several memory mappings. in fact, depending on the product, each memory area may be assigned to several slaves. booting at the same address while using different ahb slaves (i.e. internal rom or internal flash) becomes possible. 21.4 special bus granting techniques the bus matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. this mechanism a llows to reduce latency at first accesses of a burst or single transfer. the bus granting mechanism allows to set a default master for every slave. at the end of the current access, if no other re quest is pending, the slave remains connected to its associated default master. a slave can be as sociated with three kinds of default masters: no default master, last access master and fixed default master. 21.4.1 no default master at the end of the current access, if no other request is pending, the slave is disconnected from all masters. no default ma ster suits low power mode. 21.4.2 last access master at the end of the current access, if no other re quest is pending, the slave remains connected to the last master that performed an access request. 21.4.3 fixed default master at the end of the current access, if no other r equest is pending, the slave connects to its fixed default master. unlike last access master, the fixed master doesn?t change unless the user mod- ifies it by a software acti on (field fixed_defmstr of the related matrix_scfg). to change from one kind of default master to another, the bus matrix user interface provides the slave configuration registers, one for each slave, that allow to set a default master for each slave. the slave configuration register contains two fields: defmstr_type and fixed_defmstr. the 2- bit defmstr_type field allows to choose the default master type (no default, last access master, fixed default master) whereas the 4-bit table 21-2. sam3n master to slave access masters 0 1 2 slaves cortex-m3 i/d bus cortex-m3 s bus pdc 0 internal sram - x x 1 internal rom x - x 2 internal flash x - - 3 peripheral bridge - x x
309 11011a?atarm?04-oct-10 sam3n fixed_defmstr field allows to choose a fixed default master provided that defmstr_type is set to fixed default master. please refer to the bus matrix user interface description. 21.5 arbitration the bus matrix provides an arbitration mechani sm that allows to reduce latency when conflict cases occur, basically when two or more masters try to access the same sl ave at the same time. one arbiter per ahb slave is provided, allowing to arbitrate each slave differently. the bus matrix provides to the user the possi bility to choose between 2 arbitration types, and this for each slave: 1. round-robin arbitration (the default) 2. fixed priority arbitration this choice is given through the field arbt of the slave configuration registers (matrix_scfg). each algorithm may be complemented by selecting a default master configuration for each slave. when a re-arbitration has to be done, it is realiz ed only under some spec ific conditions detailed in the following paragraph. 21.5.1 arbitration rules each arbiter has the ability to arbi trate between two or more differ ent master?s requests. in order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitra- tion may only take place during the following cycles: 1. idle cycles: when a slave is not connected to any master or is connected to a master which is not currently accessing it. 2. single cycles: when a slave is currently doing a single access. 3. end of burst cycles: when the current cycle is the last cycle of a burst transfer. for defined length burst, predicted end of burst matches the size of the transfer but is man- aged differently for undefined length burst (see section 21.5.1.1 ?undefined length burst arbitration? on page 309 ?). 4. slot cycle limit: when the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken (see section 21.5.1.2 ?slot cycle limit arbitration? on page 310 ). 21.5.1.1 undefined length burst arbitration in order to avoid too long slave handling durin g undefined length bursts (incr), the bus matrix provides specific logic in order to re-arbitrate before the end of the incr transfer. a predicted end of burst is used as for defined length burst transfer, which is selected between the following: 1. infinite: no predicted end of burst is generated and therefore incr burst transfer will never be broken. 2. four beat bursts: predicted end of burst is generated at the end of each four beat boundary inside incr transfer. 3. eight beat bursts: predicted end of burst is generated at the end of each eight beat boundary inside incr transfer. 4. sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary inside incr transfer.
310 11011a?atarm?04-oct-10 sam3n this selection can be done through the field ulbt of the master configuration registers (matrix_mcfg). 21.5.1.2 slot cycle limit arbitration the bus matrix contains specific logic to break too long accesses such as very long bursts on a very slow slave (e.g. an external low speed memory). at the beginning of the burst access, a counter is loaded with the value previously written in the slot_cycle field of the related slave configuration register (matrix_scfg) and decreased at each clock cycle. when the counter reaches zero, the arbiter has the ab ility to re-arbitrate at the end of the current byte, half word or word transfer. 21.5.2 round-robin arbitration this algorithm allows the bus matrix arbiters to dispatch the requests from different masters to the same slave in a round-robin manner. if two or more master?s requests arise at the same time, the master with the lowest number is first serviced then the others are serviced in a round- robin manner. there are three round-robin algorithm implemented: ? round-robin arbitration without default master ? round-robin arbitration with last access master ? round-robin arbitration with fixed default master 21.5.2.1 round-robin arbitration without default master this is the main algorithm used by bus matrix arbiters. it allows the bus matrix to dispatch requests from different masters to the same slave in a pure round-robin manner. at the end of the current access, if no other request is pending, the slave is disconnected from all masters. this configuration incurs one latency cycle for the first access of a burst. arbitration without default master can be used for masters that perform significant bursts. 21.5.2.2 round-robin arbitration with last access master this is a biased round-robin algorithm used by bus matrix arbiters. it allows the bus matrix to remove the one late ncy cycle for the last master that acce ssed the slave. in fact, at the end of the current transfer, if no other master request is pending, the slave remains connected to the last master that performs t he access. other non privileged ma sters will still get one latency cycle if they want to access the same slave. this technique can be used for masters that mainly per- form single accesses. 21.5.2.3 round-robin arbitration with fixed default master this is another biased round-robin algorithm, it allows the bus matrix arbiters to remove the one latency cycle for the fixed default master per slav e. at the end of the current access, the slave remains connected to its fixed default master. every request attempted by this fixed default mas- ter will not cause any latency whereas other non privileged masters w ill still get one latency cycle. this technique can be used for masters that mainly perform single accesses. 21.5.3 fixed priority arbitration this algorithm allows the bus matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defin ed by the user. if two or more master?s requests are active at the same time, the master with the highest priority number is serviced first. if two or
311 11011a?atarm?04-oct-10 sam3n more master?s requests with the same priority are active at the same time, the master with the highest number is serviced first. for each slave, the priority of each master may be defined through the priority registers for slaves (matrix_pras and matrix_prbs). 21.6 system i/o configuration the system i/o configuration register (ccfg_sysio) allows to configure some i/o lines in system i/o mode (such as jtag, erase, etc. ..) or as general purpose i/o lines. enabling or disabling the corresponding i/o lines in peripheral mode or in pio mode (pio_per or pio_pdr registers) in the pio controller as no effect. however, the direction (input or output), pull-up, pull- down and other mode control is still managed by the pio controller. 21.7 write protect registers to prevent any single software error that may corrupt matrix behavior, the entire matrix address space from address offset 0x000 to 0x1fc can be write-protected by setting the wpen bit in the matrix write protect mode register (matrix_wpmr). if a write access to anywhere in the matrix address space from address offset 0x000 to 0x1fc is detected, then the wpvs flag in the matrix write protect st atus register (matrix_wpsr) is set and the field wpvsrc indicates in which register the write access has been attempted. the wpvs flag is reset by writing the matrix write protect mode register (matrix_wpmr) with the appropriate access key wpkey.
312 11011a?atarm?04-oct-10 sam3n 21.8 bus matrix (matrix) user interface table 21-3. register mapping offset register name access reset 0x0000 master configuration register 0 matrix_mcfg0 read-write 0x00000000 0x0004 master configuration register 1 matrix_mcfg1 read-write 0x00000000 0x0008 master configuration register 2 matrix_mcfg2 read-write 0x00000000 0x000c - 0x003c reserved ? ? ? 0x0040 slave configuration register 0 matrix_scfg0 read-write 0x00010010 0x0044 slave configuration register 1 matrix_scfg1 read-write 0x00050010 0x0048 slave configuration register 2 matrix_scfg2 read-write 0x00000010 0x004c slave configuration register 3 matrix_scfg3 read-write 0x00000010 0x0050 - 0x007c reserved ? ? ? 0x0080 priority register a for slave 0 matrix_pras0 read-write 0x00000000 0x0084 reserved ? ? ? 0x0088 priority register a for slave 1 matrix_pras1 read-write 0x00000000 0x008c reserved ? ? ? 0x0090 priority register a for slave 2 matrix_pras2 read-write 0x00000000 0x0094 reserved ? ? ? 0x0098 priority register a for slave 3 matrix_pras3 read-write 0x00000000 0x009c - 0x0110 reserved ? ? ? 0x0114 system i/o configuration register ccfg_sysio read/write 0x00000000 0x0118- 0x011c reserved ? ? ? 0x0120 - 0x010c reserved ? ? ? 0x1e4 write protect mode register matrix_wpmr read-write 0x0 0x1e8 write protect status register matrix_wpsr read-only 0x0 0x0110 - 0x01fc reserved ? ? ?
313 11011a?atarm?04-oct-10 sam3n 21.8.1 bus matrix master configuration registers name: matrix_mcfg0..matrix_mcfg2 address: 0x400e0200 access: read-write ? ulbt: undefined length burst type 0: infinite length burst no predicted end of burst is generated and therefore incr bursts coming from this master cannot be broken. 1: single access the undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the incr burst. 2: four beat burst the undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end. 3: eight beat burst the undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end. 4: sixteen beat burst the undefined length burst is split into 16-beat burs ts allowing rearbitration at each 16-beat burst end. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????? ulbt
314 11011a?atarm?04-oct-10 sam3n 21.8.2 bus matrix slave configuration registers name: matrix_scfg0..matrix_scfg3 address: 0x400e0240 access: read-write ? slot_cycle: maximum number of allowed cycles for a burst when the slot_cycle limit is reach for a burst it may be broken by another master trying to access this slave. this limit has been placed to avoid locking very slow slaves when very long bursts are used. this limit should not be very small though. an unreasonable sm all value will break every burst and the bus matrix will spend its time to arbitrate without performing any data transfer. 16 cycles is a reasonable value for slot_cycle. ? defmstr_type: default master type 0: no default master at the end of current slave access, if no other master request is pending, the slave is disconnected from all masters. this results in having a one cycle latency for the fi rst access of a burst transf er or for a single access. 1: last default master at the end of current slave access, if no other master request is pending, the slave stays connected to the last master hav- ing accessed it. this results in not having the one cycle latency when the last master re-tries access on the slave again. 2: fixed default master at the end of the current slave access, if no other master r equest is pending, the slave connec ts to the fixed master the number that has been written in the fixed_defmstr field. this results in not having the one cycle latency when the fixed master re-tries access on the slave again. ? fixed_defmstr: fixed default master this is the number of the defa ult master for this slave. only used if defmstr_type is 2. specifying the number of a mas- ter which is not connected to the selected slave is equivalent to setting defmstr_type to 0. ? arbt: arbitration type 0: round-robin arbitration 1: fixed priority arbitration 2: reserved 3: reserved 31 30 29 28 27 26 25 24 ?????? arbt 23 22 21 20 19 18 17 16 ? ? ? fixed_defmstr defmstr_type 15 14 13 12 11 10 9 8 ???????? 76543210 slot_cycle
315 11011a?atarm?04-oct-10 sam3n 21.8.3 bus matrix priority registers for slaves name: matrix_pras0..matrix_pras3 addresses: 0x400e0280 [0], 0x400e0288 [1], 0x400e0290 [2], 0x400e0298 [3] access: read-write ? mxpr: master x priority fixed priority of master x for accessing the selected slave. the higher the number, the higher the priority. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?? m3pr ?? m2pr 76543210 ?? m1pr ?? m0pr
316 11011a?atarm?04-oct-10 sam3n 21.8.4 system i/o configuration register name: ccfg_sysio address: 0x400e0314 access read-write reset: 0x0000_0000 ? sysio4: pb4 or tdi assignment 0 = tdi function selected. 1 = pb4 function selected. ? sysio5: pb5 or tdo/traceswo assignment 0 = tdo/traceswo function selected. 1 = pb5 function selected. ? sysio6: pb6 or tms/swdio assignment 0 = tms/swdio function selected. 1 = pb6 function selected. ? sysio7: pb7 or tck/swclk assignment 0 = tck/swclk function selected. 1 = pb7 function selected. ? sysio12: pb12 or erase assignment 0 = erase function selected. 1 = pb12 function selected. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???sysio12???? 76543210 sysio7 sysio6 sysio5 sysio4 ? ? ? ?
317 11011a?atarm?04-oct-10 sam3n 21.8.5 write protect mode register name: matrix_wpmr address: 0x400e03e4 access: read-write for more details on matrix_wpmr, refer to section 21.7 ?write protect registers? on page 311 . ? wpen: write protect enable 0 = disables the write protect if wpkey corresponds to 0x4d4154 (?mat? in ascii). 1 = enables the write protect if wpkey corresponds to 0x4d4154 (?mat? in ascii). protects the entire matrix address space from address offset 0x000 to 0x1fc. ? wpkey: write protect key (write-only) should be written at value 0x4d4154 (?mat? in ascii). writing any other value in this field aborts the write operation of the wpen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 ???????wpen
318 11011a?atarm?04-oct-10 sam3n 21.8.6 write protect status register name: matrix_wpsr address: 0x400e03e8 access: read-only for more details on matrix_wpsr, refer to section 21.7 ?write protect registers? on page 311 . ? wpvs: write protect violation status 0: no write protect violation has occurr ed since the last write of matrix_wpmr. 1: at least one write protect violation has occurred since the last write of matrix_wpmr. ? wpvsrc: write protect violation source should be written at value 0x4d4154 (?mat? in ascii). writing any other value in this field aborts the write operation of the wpen bit. always reads as 0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 ???????wpvs
319 11011a?atarm?04-oct-10 sam3n 22. peripheral dma controller (pdc) 22.1 description the peripheral dma controller (pdc) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. the link betw een the pdc and a serial peripheral is operated by the ahb to abp bridge. the user interface of each pdc channel is integrat ed into the user interface of the peripheral it serves. the user interface of mono directional channels (receive only or transmit only), contains two 32-bit memory pointers and two 16-bit counters, one set (pointer, counter) for current trans- fer and one set (pointer, counter) for next transfer. the bi-directional channel user interface contains four 32-bit memory pointers and four 16-bit counters. each set (pointer, counter) is used by current transmit, next transmi t, current receive and next receive. using the pdc removes processor overhead by reducing its intervention during the transfer. this significantly reduces the number of clock cycles required for a data transfer, which improves microcontroller performance. to launch a transfer, the peripheral triggers its associated pdc channels by using transmit and receive signals. when the programmed data is transferred, an end of transfer interrupt is gener- ated by the peripheral itself. 22.2 embedded characteristics ? handles data transfer between peripherals and memories ? low bus arbitration overhead ? one master clock cycle needed for a transfer from memory to peripheral ? two master clock cycles needed for a transfer from peripheral to memory ? next pointer management for reducing interrupt latency requirement the peripheral dma controller handles transfer requests from the channel according to the fol- lowing priorities (low to high priorities): table 22-1. peripheral dma controller instance name channel t/r 100 & 64 pins 48 pins twi0 transmit x x uart0 transmit x x usart0 transmit x x dac transmit x n/a spi transmit x x twi0 receive x x uart0 receive x x usart0 receive x x adc receive x x spi receive x x
320 11011a?atarm?04-oct-10 sam3n 22.3 block diagram figure 22-1. block diagram pdc full duplex peripheral thr rhr pdc channel a pdc channel b control status & control control pdc channel c half duplex peripheral thr status & control receive or transmit peripheral rhr or thr control control rhr pdc channel d status & control
321 11011a?atarm?04-oct-10 sam3n 22.4 functional description 22.4.1 configuration the pdc channel user interface enables the user to configure and control data transfers for each channel. the user interface of each pdc channel is integrated into the associated periph- eral user interface. the user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (rpr, rnpr, tpr, tn pr) and four 16-bit counter registers (rcr, rncr, tcr, tncr). however, the transmit and receive parts of each type are programmed differently: the transmit and receive parts of a full duplex peripheral can be programmed at the same time, whereas only one part (transmit or receive) of a half duplex peripheral can be programmed at a time. 32-bit pointers define the access location in memory for current and next transfer, whether it is for read (transmit) or write (receive). 16-bit counters define the size of current and next transfers. it is possible, at any moment, to read the number of transfers left for each channel. the pdc has dedicated status registers which indica te if the transfer is enabled or disabled for each channel. the status for each channel is located in the associated peripheral status register. transfers can be enabled and/or disabled by setting txten/txtdis and rxten/rxtdis in the peripheral?s transfer control register. at the end of a transfer, the pdc channel sends status flags to its associated peripheral. these flags are visible in the peripheral status register (endrx, endtx, rxbuff, and txbufe). refer to section 22.4.3 and to the associated peripheral user interface. 22.4.2 memory pointers each full duplex peripheral is connected to the pdc by a receive channel and a transmit chan- nel. both channels have 32-bit memory pointers that point respectively to a receive area and to a transmit area in on- and/or off-chip memory. each half duplex peripheral is connected to the pdc by a bidirectional channel. this channel has two 32-bit memory pointers, one for current transfer and the other for next transfer. these pointers point to transmit or receive data depending on the operating mode of the peripheral. depending on the type of transfer (byte, half-word or word), the memory pointer is incremented respectively by 1, 2 or 4 bytes. if a memory pointer address changes in the middle of a transfer, the pdc channel continues operating using the new address. 22.4.3 transfer counters each channel has two 16-bit counters, one for current transfer and the other one for next trans- fer. these counters define the size of data to be transferred by the channel. the current transfer counter is decremented first as the data addresse d by current memory pointer starts to be trans- ferred. when the cu rrent transfer counter re aches zero, the channel checks its next transfer counter. if the value of next counter is zero, the channel stops transferring data and sets the appropriate flag. but if the next counter value is greater then zero, the values of the next pointer/next counter are copied into the current pointer/current counter and the channel resumes the transfer whereas next pointer/next counter get zero/zero as values. at the end of this trans- fer the pdc channel sets the appropriate flags in the peripheral status register.
322 11011a?atarm?04-oct-10 sam3n the following list gives an overview of how status register flags behave depending on the coun- ters? values: ? endrx flag is set when the periph_rcr register reaches zero. ? rxbuff flag is set when both per iph_rcr and periph_rncr reach zero. ? endtx flag is set when the periph_tcr register reaches zero. ? txbufe flag is set when both periph_tcr and periph_tncr reach zero. these status flags are described in the peripheral status register. 22.4.4 data transfers the serial peripheral triggers its associated pdc channels? transfers using transmit enable (txen) and receive enable (rxen) flags in the transfer control register integrated in the periph- eral?s user interface. when the peripheral receives an external data, it sends a receive ready signal to its pdc receive channel which then requests access to the matrix. when access is granted, the pdc receive channel starts reading the peripheral receive holding register (rhr). the read data are stored in an internal buffer and then written to memory. when the peripheral is about to send data, it sends a transmit ready to its pdc transmit chan- nel which then requests access to the matrix. when access is granted, the pdc transmit channel reads data from memory and puts them to transmit holding regist er (thr) of its asso- ciated peripheral. the same peripheral sends data according to its mechanism. 22.4.5 pdc flags and peripheral status register each peripheral connected to the pdc sends out receive ready and transmit ready flags and the pdc sends back flags to the peripheral. all these flags are only visible in the peripheral status register. depending on the type of peripheral, half or full duplex, the flags belong to either one single channel or two different channels. 22.4.5.1 receive transfer end this flag is set when periph_rcr register reaches zero and the last data has been transferred to memory. it is reset by writing a non zero value in periph_rcr or periph_rncr. 22.4.5.2 transmit transfer end this flag is set when periph_tcr register reaches zero and the last data has been written into peripheral thr. it is reset by writing a non zero value in periph_tcr or periph_tncr. 22.4.5.3 receive buffer full this flag is set when periph_rcr register reac hes zero with periph_rncr also set to zero and the last data has been transferred to memory. it is reset by writing a non zero value in periph_tcr or periph_tncr.
323 11011a?atarm?04-oct-10 sam3n 22.4.5.4 transmit buffer empty this flag is set when periph_tcr register reac hes zero with periph_tncr also set to zero and the last data has been written into peripheral thr. it is reset by writing a non zero value in periph_tcr or periph_tncr.
324 11011a?atarm?04-oct-10 sam3n 22.5 peripheral dma controll er (pdc) user interface note: 1. periph: ten registers are mapped in the peripheral memory space at the same offset. these can be defined by the user according to the function and the desired peripheral.) table 22-2. register mapping offset register name access reset 0x100 receive pointer register periph (1) _rpr read-write 0 0x104 receive counter register periph_rcr read-write 0 0x108 transmit pointer register periph_tpr read-write 0 0x10c transmit counter register periph_tcr read-write 0 0x110 receive next pointer register periph_rnpr read-write 0 0x114 receive next counter register periph_rncr read-write 0 0x118 transmit next pointer register periph_tnpr read-write 0 0x11c transmit next counter register periph_tncr read-write 0 0x120 transfer control register periph_ptcr write-only 0 0x124 transfer status register periph_ptsr read-only 0
325 11011a?atarm?04-oct-10 sam3n 22.5.1 receive pointer register name: periph_rpr access: read-write ? rxptr: receive pointer register rxptr must be set to receive buffer address. when a half duplex peripheral is connected to the pdc, rxptr = txptr. 31 30 29 28 27 26 25 24 rxptr 23 22 21 20 19 18 17 16 rxptr 15 14 13 12 11 10 9 8 rxptr 76543210 rxptr
326 11011a?atarm?04-oct-10 sam3n 22.5.2 receive counter register name: periph_rcr access: read-write ? rxctr: receive counter register rxctr must be set to receive buffer size. when a half duplex peripheral is connected to the pdc, rxctr = txctr. 0 = stops peripheral data transfer to the receiver 1 - 65535 = starts peripheral data transfer if corresponding channel is active 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rxctr 76543210 rxctr
327 11011a?atarm?04-oct-10 sam3n 22.5.3 transmit pointer register name: periph_tpr access: read-write ? txptr: transmit counter register txptr must be set to transmit buffer address. when a half duplex peripheral is connected to the pdc, rxptr = txptr. 31 30 29 28 27 26 25 24 txptr 23 22 21 20 19 18 17 16 txptr 15 14 13 12 11 10 9 8 txptr 76543210 txptr
328 11011a?atarm?04-oct-10 sam3n 22.5.4 transmit counter register name: periph_tcr access: read-write ? txctr: transmit counter register txctr must be set to transmit buffer size. when a half duplex peripheral is connected to the pdc, rxctr = txctr. 0 = stops peripheral data transfer to the transmitter 1- 65535 = starts peripheral data transfer if corresponding channel is active 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txctr 76543210 txctr
329 11011a?atarm?04-oct-10 sam3n 22.5.5 receive next pointer register name: periph_rnpr access: read-write ? rxnptr: receive next pointer rxnptr contains next receive buffer address. when a half duplex peripheral is connected to the pdc, rxnptr = txnptr. 22.5.6 receive next counter register name: periph_rncr access: read-write ? rxnctr: receive next counter rxnctr contains next receive buffer size. when a half duplex peripheral is connected to the pdc, rxnctr = txnctr. 31 30 29 28 27 26 25 24 rxnptr 23 22 21 20 19 18 17 16 rxnptr 15 14 13 12 11 10 9 8 rxnptr 76543210 rxnptr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rxnctr 76543210 rxnctr
330 11011a?atarm?04-oct-10 sam3n 22.5.7 transmit next pointer register name: periph_tnpr access: read-write ? txnptr: transmit next pointer txnptr contains next transmit buffer address. when a half duplex peripheral is connected to the pdc, rxnptr = txnptr. 22.5.8 transmit next counter register name: periph_tncr access: read-write ? txnctr: transmit counter next txnctr contains next transmit buffer size. when a half duplex peripheral is connected to the pdc, rxnctr = txnctr. 31 30 29 28 27 26 25 24 txnptr 23 22 21 20 19 18 17 16 txnptr 15 14 13 12 11 10 9 8 txnptr 76543210 txnptr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txnctr 76543210 txnctr
331 11011a?atarm?04-oct-10 sam3n 22.5.9 transfer control register name: periph_ptcr access: write-only ? rxten: receiver transfer enable 0 = no effect. 1 = enables pdc receiver channel requests if rxtdis is not set. when a half duplex peripheral is connected to the pdc, en abling the receiver channel requests automatically disables the transmitter channel requests. it is forbidden to set both txten and rxten for a half duplex peripheral. ? rxtdis: receiver transfer disable 0 = no effect. 1 = disables the pdc receiver channel requests. when a half duplex peripheral is connecte d to the pdc, disabling the receiver chann el requests also disables the transmit- ter channel requests. ? txten: transmitter transfer enable 0 = no effect. 1 = enables the pdc transmitter channel requests. when a half duplex peripheral is connected to the pdc, it en ables the transmitter channel requests only if rxten is not set. it is forbidden to set both txten and rxten for a half duplex peripheral. ? txtdis: transmitter transfer disable 0 = no effect. 1 = disables the pdc transmitter channel requests. when a half duplex peripheral is connected to the pdc, dis abling the transmitter channel requests disables the receiver channel requests. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txtdistxten 76543210 ??????rxtdisrxten
332 11011a?atarm?04-oct-10 sam3n 22.5.10 transfer status register name: periph_ptsr access: read-only ? rxten: receiver transfer enable 0 = pdc receiver channel requests are disabled. 1 = pdc receiver channel requests are enabled. ? txten: transmitter transfer enable 0 = pdc transmitter channel requests are disabled. 1 = pdc transmitter channel requests are enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????txten 76543210 ???????rxten
333 11011a?atarm?04-oct-10 sam3n 23. clock generator 23.1 description the clock generator user interface is embedded within the power management controller and is described in section 24.15 ?power management controller (pmc) user interface? . however, the clock generator registers are named ckgr_. 23.2 embedded characteristics the clock generator is made up of: ? a low power 32,768 hz slow clock oscillator with bypass mode ? a low power rc oscillator ? a 3 to 20 mhz crystal or ceramic resonator-based oscillator which can be bypassed ? a factory programmed fast rc oscillator, 3 ou tput frequencies can be selected: 4, 8 or 12 mhz. by default 4 mhz is selected. ? a 60 to 130 mhz programmable pll (input from 3.5 to 20 mhz), capable of providing the clock mck to the processor and to the peripherals. it provides the following clocks: ? slck, the slow clock, which is the only permanent clock within the system ? mainck is the output of the main clock oscilla tor selection: either the crystal or ceramic resonator-based osc illator or 4/8/12 mh z fast rc oscillator ? pllck is the output of the divider and 60 to 130 mhz programmable pll
334 11011a?atarm?04-oct-10 sam3n 23.3 block diagram figure 23-1. clock generator block diagram power management controller main clock mainck pll clock pllck control status moscsel clock generator pll and divider xin xout xin32 xout32 slow clock slck xtalsel (supply controller) 0 1 0 1 3-20 mhz crystal or ceramic resonator oscillator embedded 4/8/12 mhz fast rc oscillator 32768 hz crystal oscillator embedded 32 khz rc oscillator
335 11011a?atarm?04-oct-10 sam3n 23.4 slow clock the supply controller embeds a slow clock genera tor that is supplied with the vddio power- supply. as soon as vddio is supplied, both the crystal oscillator and the embedded rc oscillator are powered up, but on ly the embedded rc oscillator is enabled. this allows the slow clock to be valid in a short time (about 100 s). the slow clock is generated either by the slow clock crystal oscillator or by the slow clock rc oscillator. the selection between the rc or crystal oscillat or is made by writing the xtalsel bit in the supply controller control register (supc_cr). 23.4.1 slow clock rc oscillator by default, the slow clock rc oscillator is enabled and selected. the user has to take into account the possible drifts of th e rc oscillator. more details are given in the section ?dc char- acteristics? of the product datasheet. it can be disabled via the xtalsel bit in the supply controller control register (supc_cr). 23.4.2 slow clock crystal oscillator the clock generator integrat es a 32,768 hz low-powe r oscillator. in order to use this oscillator, the xin32/pa7 and xout32/p8 pins must be connected to a 32,768 hz crystal. two external capacitors must be wired as shown in figure 23-2 . more details are given in the section ?dc characteristics? of the product datasheet. note that the user is not obliged to use the slow clock crystal and can use the rc oscillator instead. figure 23-2. typical slow clock crystal oscillator connection the user can select the crystal oscillator to be t he source of the slow clock, as it provides a more accurate frequency. the command is made by wr iting the supply controller control register (supc_cr) with the xtalsel bit at 1. this results in a sequence which first configures the pio lines multiplexed with xin32 and xout32 to be driven by the oscillator, then enables the crystal oscillator and then disables the rc oscillator to save power. the switch of the slow clock source is glitch free. the oscsel bit of the supply controller status regi ster (supc_sr) allows knowing when the switch sequence is done. coming back on the rc oscillator is only po ssible by shutting down th e vddio power supply. if the user does not need the crystal oscillato r, the xin32 and xout32 pins can be left uncon- nected since by default the xin32 and xout32 system i/o pins are in pio input mode after reset. the user can also set the crystal oscillator in bypass mode instead of connecting a crystal. in this case, the user has to provide the external cl ock signal on xin32. the input characteristics of xin 3 2 xout 3 2 gnd 3 2,76 8 hz cry s t a l
336 11011a?atarm?04-oct-10 sam3n the xin32 pin are given in the product electrical characteristics section. in order to set the bypass mode, the oscbypass bit of the supply controller mode regi ster (supc_mr) needs to be set at 1. the user can set the slow clock crystal oscillator in bypass mode instead of connecting a crys- tal. in this case, the user has to provide the external clock signal on xin32. the input characteristics of the xin32 pin under these condit ions are given in the product electrical char- acteristics section. the programmer has to be sure to set the oscbypass bit in th e supply controller mode reg- ister (supc_mr) and xtalsel bit in the su pply controller control register (supc_cr). 23.5 main clock figure 23-3 shows the main clock block diagram. figure 23-3. main clock block diagram the main clock has two sources: ? 4/8/12 mhz fast rc oscillator which starts very quickly and is used at startup ? 3 to 20 mhz crystal or ceramic resona tor-based oscillator which can be bypassed xin xout moscxten moscxtcnt moscxts main clock frequency counter mainf mainrdy slck slow clock 3-20 mhz crystal or ceramic resonator oscillator 3-20 mhz oscillator counter moscrcen 4/8/12 mhz fast rc oscillator moscrcs moscrcf moscrcen moscxten moscsel moscsel moscsels 1 0 mainck main clock
337 11011a?atarm?04-oct-10 sam3n 23.5.1 4/8/12 mhz fast rc oscillator after reset, the 4/8/12 mhz fast rc oscillator is enabled wit h the 4 mhz frequency selected and it is selected as the source of mainck. mainck is the default clock selected to start up the system. the fast rc oscillator 8 and 12 mhz frequencies are calibrated in production. note that is not the case for the 4 mhz frequency. please refer to the ?dc characteristics? section of the product datasheet. the software can disable or enable the 4/8/12 mhz fast rc oscillator with the moscrcen bit in the clock gene rator main osc illator register (ckgr_mor). the user can also select the output frequency of the fast rc oscillator: either 4 mhz, 8 mhz or 12 mhz are available. it can be done through moscrcf bits in ckgr_mor. when changing this frequency selection, the moscrcs bit in the power management controller status regis- ter (pmc_sr) is automatically cleared and main ck is stopped until the oscillator is stabilized. once the oscillator is stabilized, ma inck restarts and moscrcs is set. when disabling the main clock by clearing the moscrcen bit in ckgr_mor, the moscrcs bit in the power management controller status register (pmc_sr) is automatically cleared, indicating the main clock is off. setting the moscrcs bit in the power management controller interrupt enable register (pmc_ier) can trigger an interrupt to the processor. it is recommended to disable the main clock as soon as the processor no longer uses it and runs out of slck or pllck. the cal4, cal8 and cal12 values in the pmc_ocr registers are the default values set by atmel during production. these values are stored in a specific flash memory area different from the main memory plane. these values cannot be modified by the user and cannot be erased by a flash erase command or by the erase pin. val ues written by the user's application in the pmc_ocr register are reset after each power up or peripheral reset. 23.5.2 4/8/12 mhz fast rc oscillator clock frequency adjustment it is possible for the user to adjust the main rc oscillator frequency th rough pmc_ocr register. by default, sel4/8/12 are low, so the rc oscillator will be driven wit h flash calibration bits which are programmed during chip production. the user can adjust the trimming of the 4/8/12 mhz fast rc oscillator through this register in order to obtain more accurate frequency (to compensate derating factors such as temperature and voltage). in order to calibrate the 4 mhz fast rc oscillator frequency, sel4 must be set to 1 and a valid frequency value must be configured in cal4. likewise, sel8/12 must be set to 1 and a trim value must be configured in cal8/12 in order to adjust the 8/12 mhz frequency oscillator. however, the adjustment can not be done to the frequen cy from which the os cillator is operating. for example, while running from a frequency of 8 mhz, the user can adjust the 4 and 12 mhz frequency but not the 8 mhz.
338 11011a?atarm?04-oct-10 sam3n 23.5.3 3 to 20 mhz crystal or ceramic resonator-based oscillator after reset, the 3 to 20 mhz crystal or cerami c resonator-based oscillator is disabled and it is not selected as the source of mainck. the user can select the 3 to 20 mhz crystal or ceramic resonator-based oscillator to be the source of mainck, as it provides a more accurate frequency. the software enables or disables the main oscillator so as to reduce power cons umption by clearing the moscxten bit in the main oscillator regi ster (ckgr_mor). when disabling the main oscillator by clearing the moscxten bit in ckgr_mor, the moscxts bit in pmc_sr is automatically cl eared, indicating the main clock is off. when enabling the main oscillator, the user must initiate the ma in oscillator coun ter with a value corresponding to the startup time of the oscillat or. this startup time depends on the crystal fre- quency connected to the oscillator. when the moscxten bit and the moscxtcnt are written in ckgr_mor to enable the main oscillator, the moscxts bit in the power mana gement controller status register (pmc_sr) is cleared and the counter starts counting down on the slow clock divided by 8 from the moscx- tcnt value. since the moscxtcnt value is c oded with 8 bits, the maximum startup time is about 62 ms. when the counter reaches 0, the moscxts bit is se t, indicating that the main clock is valid. setting the moscxts bit in pmc_imr can trigger an interrupt to the processor. 23.5.4 main clock oscillator selection the user can select either the 4/8/12 mhz fast rc oscillator or the 3 to 20 mhz crystal or ceramic resonator-based oscillator to be the source of main clock. the advantage of the 4/8/12 mhz fast rc oscillator is that it provides fast startup time, this is why it is selected by default (to start up the system) and when entering wait mode. the advantage of the 3 to 20 mhz crystal or ceramic resonator-based osc illator is that it is very accurate. the selection is made by writing the mosc sel bit in the main oscillator register (ckgr_mor). the switch of the main clock source is glitch free, so there is no need to run out of slck or pllck in order to change the selection. the moscsels bit of the power manage- ment controller status register (pmc_sr) allows knowing when the switch sequence is done. setting the moscsels bit in pmc_imr can trigger an interrupt to the processor. 23.5.5 main clock frequency counter the device features a main clock frequency counter that provides the frequency of the main clock. the main clock frequency counter is reset and starts incrementing at the main clock speed after the next rising edge of the slow clock in the following cases: ? when the 4/8/12 mhz fast rc oscillator clock is selected as the source of main clock and when this oscillator becomes stable (i.e., when the moscrcs bit is set) ? when the 3 to 20 mhz crystal or ceramic resonato r-based oscillator is selected as the source of main clock and when this oscillator becomes stable (i.e., when the moscxts bit is set) ? when the main clock oscilla tor selection is modified
339 11011a?atarm?04-oct-10 sam3n then, at the 16th falling edge of slow clock, the mainfrdy bit in the clock generator main clock frequency register (ckgr_mcfr) is set and the counter stops counting. its value can be read in the mainf field of ckgr_mcfr and gi ves the number of main clock cycles during 16 periods of slow clock, so th at the frequency of the 4/8/12 mhz fast rc oscillator or 3 to 20 mhz crystal or ceramic resonator-based oscillator can be determined.
340 11011a?atarm?04-oct-10 sam3n 23.6 divider and pll block the device features a divider/pll block that permits a wide range of frequencies to be selected on either the master clock, the processor clock or the programmable clock outputs. figure 23-4 shows the block diagram of the divider and pll block. figure 23-4. divider and pll block diagram 23.6.1 divider and phase lock loop programming the divider can be set between 1 and 255 in steps of 1. when the divider field (div) is set to 0, the output of the divider and the pll output is a continuous signal at level 0. on reset, the div field is set to 0, thus the pll input clock is set to 0. the pll allows multiplication of the divider?s output. the pll clock signal has a frequency that depends on the respective source signal frequency and on the div and mul parameters. the factor applied to the source signal frequency is (mul + 1)/div. when mul is written to 0, the pll is disabled and its power consumption is saved. re-enabling the pll can be performed by writing a value higher than 0 in the mul field. whenever the pll is re-enabled or one of its parameters is changed, the lock bit in pmc_sr is automatically cleared. the value written in the pllcount field in ckgr_pllr is loaded in the pll counter. the pll counter then decrements at the speed of the slow clock until it reaches 0. at this time, the lock bit is set in pmc_sr and can trigger an interrupt to the pro- cessor. the user has to load the number of slow clock cycles required to cover the pll transient time into the pllcount field. the pll clock can be divided by 2 by writing the plldiv2 bit in pmc_mckr register. it is forbidden to change 4/8/12 fast rc oscillator frequency or main selection in ckgr_mor register while master clock source is pll and pll reference clock is fast rc oscillator. the user must: ? switch on the main rc os cillator by writing 1 in css field of pmc_mckr. ? change the frequency (moscrcf) or osc illator selection (moscsel) in ckgr_mor. ? wait for moscrcs (if frequency changes) or mo scsels (if oscillator selection changes) in pmc_ier. ? disable and then enable the pll (loc k in pmc_idr and pmc_ier register) ?wait for pllrdy. ? switch back to pll. divider div pll mul pllcount lock out slck mainck pllck pll counter
341 11011a?atarm?04-oct-10 sam3n 24. power management controller (pmc) 24.1 description the power management controller (pmc) optimizes power consumption by controlling all sys- tem and user peripheral clocks. the pmc enables/disables the clock inputs to many of the peripherals and the cortex-m3 processor. the supply controller selects between the 32 khz rc oscillator or the crystal oscillator. the unused oscillator is disabled automatically so that powe r consumption is optimized. by default, at startup th e chip runs out of the master clock usin g the fast rc oscillator running at 4 mhz. the user can trim the 8 and 12 mhz rc oscillato r frequency by software. 24.2 embedded characteristics the power management controller provides the following clocks: ? mck, the master clock, programmable from a few hundred hz to the maximum operating frequency of the device. it is available to the modules running permanently, such as the enhanced embedded flash controller. ? processor clock (hclk), must be switched off when entering the processor in sleep mode. ? free running processor clock (fclk) ? the cortex-m3 systick external clock ? peripheral clocks, typically mck, provided to the embedded peripherals (usart, spi, twi, tc, etc.) and are independently controllable. in order to reduce the number of clock names in a product, the peripheral clocks are named mck in the product datasheet. ? programmable clock outputs can be selected from the clocks provided by the clock generator and driven on the pckx pins.
342 11011a?atarm?04-oct-10 sam3n 24.3 block diagram figure 24-1. general clock block diagram 24.4 master clock controller the master clock controller provides selection and division of the master clock (mck). mck is the clock provided to all the peripherals. the master clock is selected from one of the clocks provided by the clock generator. selecting the slow clock provides a slow clock signal to the whole device. selecting the main clock saves power consumption of the pll. the master clock controller is made up of a clock selector and a prescaler. the master clock selection is made by writi ng the css field (clock source selection) in pmc_mckr (master clock register). the prescaler supports the division by a power of 2 of the selected clock between 1 and 64, and the division by 3. the pres field in pmc_mckr pro- grams the prescaler. each time pmc_mckr is written to define a ne w master clock, the mckr dy bit is cleared in pmc_sr. it reads 0 until the master clock is es tablished. then, the mckrdy bit is set and can trigger an interrupt to the processor. this feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done. power management controller main clock mainck pll clock pllck control status 3-20 mhz crystal or ceramic resonator oscillator moscsel clock generator pll and divider xin xout xin32 xout32 slow clock slck extalsel (supply controller) embedded 32 khz rc oscillator 32768 hz crystal oscillator 0 1 0 1 mck periph_clk[..] int slck mainck pllck prescaler /1,/2,/3,/4,...,/64 hclk processor clock controller sleep mode master clock controller peripherals clock controller on/off prescaler /1,/2,/4,...,/64 pck[..] on/off fclk systick divider /8 slck mainck pllck processor clock free runnning clock master clock embedded 4/8/12 mhz fast rc oscillator programmable clock controller mck
343 11011a?atarm?04-oct-10 sam3n figure 24-2. master clock controller 24.5 processor clock controller the pmc features a processor clock controlle r (hclk) that implements the processor sleep mode. the processor clock can be disabled by executing the wfi (waitforinterrupt) or the wfe (waitforevent) processor instruction while the lpm bit is at 0 in the pmc fast startup mode register (pmc_fsmr). the processor clock hclk is enabled after a reset and is automatically re-enabled by any enabled interrupt. the processor sleep mode is achieved by disabling the processor clock, which is automatically re-enabled by any enabled fa st or normal interrupt, or by the reset of the product. when processor sleep mode is entered, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. 24.6 systick clock the systick calibration value is fixed at 6000 which allows the generation of a time base of 1 ms with systick clock at 6 mhz (max hclk/8). 24.7 peripheral clock controller the power management controller controls the cl ocks of each embedded peripheral by means of the peripheral clock controller. the user can individually enable and disable the clock on the peripherals. the user can also enable and disable these clocks by writing peripheral clock enable (pmc_pcer) and peripheral clock disable (pmc_p cdr) registers. the status of the periph- eral clock activity can be read in the pe ripheral clock status register (pmc_pcsr). when a peripheral clock is disabled, the clock is immediately stopped. the peripheral clocks are automatically disabled after a reset. in order to stop a peri pheral, it is recommended that the syst em software wait until the peripheral has executed its last programmed operation before disabling the clock. this is to avoid data cor- ruption or erroneous behavior of the system. the bit number within the peripheral clock control registers (pmc_pcer, pmc_pcdr and pmc_pcsr) is the peripheral identifier defined at the product level. the bit number corre- sponds to the interrupt source number assigned to the peripheral. slck master clock prescaler mck pres css mainck pllck to the processor clock controller (pck) pmc_mckr pmc_mckr
344 11011a?atarm?04-oct-10 sam3n 24.8 free running processor clock the free running processor clock (fclk) used for sampling interrupts and clocking debug blocks ensures that interrupts can be sampled, and sleep events can be traced, while the pro- cessor is sleeping. it is connected to master clock (mck). 24.9 programmable clock output controller the pmc controls 3 signals to be output on external pins, pckx. each signal can be indepen- dently programmed via the pmc_pckx registers. pckx can be independently selected between the slow clock (slck), the main clock (mainck), the pll clock (pllck) and the master clock (mck) by writing the css field in pmc_pckx. each output signal can also be divide d by a power of 2 between 1 and 64 by writing the pres (prescaler) field in pmc_pckx. each output signal can be enabled and disabled by writing 1 in the corresponding bit, pckx of pmc_scer and pmc_scdr, respectively. status of the active programmable output clocks are given in the pckx bits of pmc_scsr (system clock status register). moreover, like the pck, a status bit in pmc_sr indicates that the programmable clock is actu- ally what has been programmed in the programmable clock registers. as the programmable clock controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the programmable clock before any configuration change and to re-enable it after the change is actually performed.
345 11011a?atarm?04-oct-10 sam3n 24.10 fast startup the sam3n device allows the processor to restar t in less than10 s while the device is in wait mode. the system enters wait mode either by writing the waitmode bit at 1 in the pmc clock generator main oscillator register (ckgr_mor), or by executing the waitforevent (wfe) instruction of the processor while the lpm bit is at 1 in the pmc fast startup mode register (pmc_fsmr). a fast startup is enabled upon the detection of a programmed level on one of the 16 wake-up inputs (wkup) or upon an active alarm from t he rtc and rtt. the polarity of the 16 wake-up inputs is programmable by writing the pmc fast startup polarity register (supc_fspr). the fast restart circuitry, as shown in figure 24-3 , is fully asynchronous and provides a fast startup signal to the power management controller. as soon as the fast startup signal is asserted, this automatically restarts the embedded 4/8/ 12 mhz fast rc oscillator. figure 24-3. fast startup circuitry each wake-up input pin and alarm can be enabled to generate a fast startup event by writing at 1 the corresponding bit in the fast startup mode register supc_fsmr. the user interface does not provide any status for fast startup, but the user can easily recover this information by reading the pio controller, and the status registers of the rtc and rtt. fast_restart wkup15 fstt15 fstp15 wkup1 fstt1 fstp1 wkup0 fstt0 fstp0 rttal rtcal rtt alarm rtc alarm
346 11011a?atarm?04-oct-10 sam3n 24.11 clock failure detector the clock failure detector allows to monitor the 3 to 20 mhz crystal or ceramic resonator- based oscillator and to detect an eventual defect of this oscillator (for example if the crystal is unconnected). the clock failure detector can be enabled or dis abled by means of the cfden bit in the pmc clock generator main oscillator register (ckg r_mor). after reset, the detector is disabled. however, if the 3 to 20 mhz crystal or cera mic resonator-based oscillator is disabled, the clock failure detector is disabled too. a failure is detected by means of a counter incrementing on the 3 to 20 mhzcrystal oscillator or ceramic resonator-ba sed oscillator clock edge and timing logic clocked on the slow clock rc oscillator controlling the co unter. the counter is cl eared when the slow clock rc oscillator signal is low and enabled when the slow clock rc oscillato r is high. thus the failu re detection time is 1 slow clock rc oscillator clock period. if, during th e high level period of slow clock rc oscillator, less than 8 fast crystal clock periods have been counted, then a failure is declared. if a failure of the 3 to 20 mhz crystal or ce ramic resonator-based oscillator clock is detected, the cfdev flag is set in the pmc status register (pmc_sr), and can generate an interrupt if it is not masked. the interrupt remains active until a read operation in the pmc_sr register. the user can know the status of the clock failure detector at any time by reading the cfds bit in the pmc_sr register. if the 3 to 20 mhz crystal or ce ramic resonator-based oscillator cl ock is selected as the source clock of mainck (moscsel = 1), and if the master clock source is pllck (css = 2), then a clock failure detection switches automatically the master clock on mainck. then whatever the pmc configuration is, a clock failure detection switches automatically mainck on the 4/8/12 mhz fast rc oscillator clock. if the fast rc oscillator is disabled when a clock failure detection occurs, it is automatically re-enabled by the clock failure detection mechanism. it takes 2 slow clock rc oscillator cycles to dete ct and switch from the 3 to 20 mhz crystal or ceramic resonator-based oscillat or to the 4/8/12 mhz fast rc oscillator if the master clock source is main clock or 3 slow clock rc oscillator cycles if the master clock source is pll. the user can know the status of the fault output at any time by reading the fos bit in the pmc_sr register.
347 11011a?atarm?04-oct-10 sam3n 24.12 programming sequence 1. enabling the main oscillator: the main oscillator is enabled by setting the moscxt en field in the ckgr_mor reg- ister. the user can define a start-up time. this can be achieved by writing a value in the moscxtst field in the ckgr_mor register. once this register has been correctly configured, the user must wait for moscxts field in the pmc_sr register to be set. this can be done either by polling the status register, or by waiting the interrupt line to be raised if the associated interrupt to moscxts has been enabled in the pmc_ier register. start up time = 8 * moscxtst / slck = 56 slow clock cycles. so, the main oscillator will be enabled (moscxts bit set) after 56 slow clock cycles. 2. checking the main oscilla tor frequency (optional): in some situations the user may need an accurate measure of the main clock frequency. this measure can be accomplished via the ckgr_mcfr register. once the mainfrdy field is set in ckgr_mcfr register, the user may read the mainf field in ckgr_mcfr register. this provides th e number of main clock cycles within sixteen slow clock cycles. 3. setting pll and divider: all parameters needed to configure pll and the divider are located in the ckgr_pllr register. the div field is used to contro l the divider itself. it must be set to 1 when pll is used. by default, div parameter is set to 0 which means that the divider is turned off. the mul field is the pll multiplier factor. this parameter can be programmed between 0 and 2047. if mul is set to 0, pll will be turn ed off, otherwise the pll output frequency is pll input frequency mult iplied by (mul + 1). the pllcount field specifies the number of sl ow clock cycles before lock bit is set in the pmc_sr register after ckgr_pllr register has been written. once the pmc_pll register has been written, the user must wait for the lock bit to be set in the pmc_sr register. this ca n be done either by polling the st atus register or by waiting the interrupt line to be raised if the associated interrupt to lock has been enabled in the pmc_ier register. all parameters in ckgr _pllr can be programmed in a single write operation. if at some stage one of the following parameters, mul, div is modified, lock bit will go low to indicate that pl l is not ready yet. when pll is locked, lock will be set again. the user is constrained to wait for lock bi t to be set before using the pll output clock. 4. selection of master clock and processor clock the master clock and the processor clock are configurable via the pmc_mckr register. the css field is used to select the master clock divider source. by default, the selected clock source is main clock. once the pmc_mckr register has been written, the user must wait for the mckrdy bit to be set in the pmc_sr register. this can be done either by polling the status register or by waiting for the interrupt line to be raised if the associated interrupt to mckrdy has been enabled in the pmc_ier register. the pmc_mckr register must not be programmed in a single write operation. the pre- ferred programming sequence for the pmc_mckr register is as follows:
348 11011a?atarm?04-oct-10 sam3n ? if a new value for css field corresponds to pll clock, ? program the pres field in the pmc_mckr register. ? wait for the mckrdy bit to be set in the pmc_sr register. ? program the css field in the pmc_mckr register. ? wait for the mckrdy bit to be set in the pmc_sr register. ? if a new value for css field corresponds to main clock or slow clock, ? program the css field in the pmc_mckr register. ? wait for the mckrdy bit to be set in the pmc_sr register. ? program the pres field in the pmc_mckr register. ? wait for the mckrdy bit to be set in the pmc_sr register. if at some stage one of the following parameters, css or pres, is modified, the mckrdy bit will go low to indicate that the master clock and the processor clock are not ready yet. the user must wait for mckrdy bit to be set again before using the master and processor clocks. note: if pll clock was selected as the master clock an d the user decides to modify it by writing in ckgr_pllr, the mckrdy flag will go low while pll is unlocked. once pll is locked again, lock goes high and mckrdy is set. while pll is unlocked, the master clock selection is automatically changed to slow clock. for fur- ther information, see section 24.13.2 ?clock switching waveforms? on page 350 . code example: write_register(pmc_mckr,0x00000001) wait (mckrdy=1) write_register(pmc_mckr,0x00000011) wait (mckrdy=1) the master clock is main clock divided by 2. the processor clock is the master clock. 5. selection of programmable clocks programmable clocks are controlled via registers; pmc_scer, pmc_scdr and pmc_scsr. programmable clocks can be enabled and/or disabled via the pmc_scer and pmc_scdr registers. 3 programmable clocks can be enabl ed or disabled. the pmc_scsr provides a clear indication as to which programmable clock is enabled. by default all programmable clocks are disabled. pmc_pckx registers are used to configure programmable clocks. the css field is used to select the programmable clock divider source. three clock options are available: main clock, slow clock, pll. by default, th e clock source selected is slow clock. the pres field is used to control the programmable clock prescaler. it is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). programmable clock output is prescaler input divided by pres parameter. by default, the pres parameter is set to 0 which means that master clock is equal to slow clock.
349 11011a?atarm?04-oct-10 sam3n once the pmc_pckx register has been programmed, the corresponding programmable clock must be enabled and the user is constrai ned to wait for the pckrdyx bit to be set in the pmc_sr register. this can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to pckrdyx has been enabled in the pmc_ier register. all parameters in pmc_ pckx can be programmed in a single write operation. if the css and pres parameters are to be modified, the corresponding programmable clock must be disabled first. the parameters can then be modified. once this has been done, the user must re-enable the programmable clock and wait for the pckrdyx bit to be set. 6. enabling peripheral clocks once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers pmc_ pcer0, pmc_pcer1, pmc_pcdr0 and pmc_pcdr1.
350 11011a?atarm?04-oct-10 sam3n 24.13 clock switching details 24.13.1 master clock switching timings table 24-1 gives the worst case timings required fo r the master clock to switch from one selected clock to another one. this is in the event that the prescaler is de-activated. when the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. 24.13.2 clock switching waveforms figure 24-4. switch master clock from slow clock to pll clock table 24-1. clock switching timings (worst case) from main clock slck pll clock to main clock ? 4 x slck + 2.5 x main clock 3 x pll clock + 4 x slck + 1 x main clock slck 0.5 x main clock + 4.5 x slck ? 3 x pll clock + 5 x slck pll clock 0.5 x main clock + 4 x slck + pllcount x slck + 2.5 x pll clock 2.5 x pll clock + 5 x slck + pllcount x slck 2.5 x pll clock + 4 x slck + pllcount x slck slow clock lock mckrdy master clock write pmc_mckr pll clock
351 11011a?atarm?04-oct-10 sam3n figure 24-5. switch master clock from main clock to slow clock figure 24-6. change pll programming slow clock main clock mckrdy master clock write pmc_mckr slow clock slow clock pll clock lock mckrdy master clock write ckgr_pllr
352 11011a?atarm?04-oct-10 sam3n figure 24-7. programmable clock output programming pll clock pckrdy pckx output write pmc_pckx write pmc_scer write pmc_scdr pckx is disabled pckx is enabled pll clock is selected
353 11011a?atarm?04-oct-10 sam3n 24.14 write protection registers to prevent any single software error that may corrupt pmc behavior, certain address spaces can be write protected by setting the wpen bit in the ?pmc write protect mode register? (pmc_wpmr). if a write access to t he protected registers is detected, then the wpvs flag in the pmc write protect status register (pmc_wpsr) is set and the field wpvsrc indicates in which register the write access has been attempted. the wpvs flag is reset by writ ing the pmc write protect mode register (pmc_wpmr) with the appropriate access key, wpkey. the protected registers are: ?pmc system clock enable register? on page 355 ?pmc system clock disable register? on page 355 ?pmc peripheral clock enable register? on page 357 ?pmc peripheral clock disable register? on page 358 ?pmc clock generator main osc illator register? on page 360 ?pmc clock generator pll register? on page 363 ?pmc master clock register? on page 364 ?pmc programmable clock register? on page 365 ?pmc fast startup mode register? on page 371 ?pmc fast startup polarity register? on page 372 ?pmc oscillator calibration register? on page 376
354 11011a?atarm?04-oct-10 sam3n 24.15 power management contro ller (pmc) user interface note: if an offset is not listed in the table it must be considered as ?reserved?. table 24-2. register mapping offset register name access reset 0x0000 system clock enable register pmc_scer write-only ? 0x0004 system clock disable register pmc_scdr write-only ? 0x0008 system clock status regi ster pmc_scsr read-only 0x0000_0001 0x000c reserved ? ? ? 0x0010 peripheral clock enable register pmc_pcer write-only ? 0x0014 peripheral clock disable register pmc_pcdr write-only ? 0x0018 peripheral clock status register pmc_pcsr read-only 0x0000_0000 0x001c reserved ? ? ? 0x0020 main oscillator register ckgr_mor read-write 0x0000_0001 0x0024 main clock frequency register ckgr_mcfr read-only 0x0000_0000 0x0028 pll register ckgr_pllr read-write 0x0000_3f00 0x002c reserved ? ? ? 0x0030 master clock register pmc_mckr read-write 0x0000_0001 0x0034 - 0x003c reserved ? ? ? 0x0040 programmable clock 0 register pmc_pck0 read-write 0x0000_0000 0x0044 programmable clock 1 register pmc_pck1 read-write 0x0000_0000 0x0048 programmable clock 2 register pmc_pck2 read-write 0x0000_0000 0x004c - 0x005c reserved ? ? ? 0x0060 interrupt enable register pmc_ier write-only ? 0x0064 interrupt disable register pmc_idr write-only ? 0x0068 status register pmc_sr read-only 0x0001_0008 0x006c interrupt mask register pmc_imr read-only 0x0000_0000 0x0070 fast startup mode regist er pmc_fsmr read-write 0x0000_0000 0x0074 fast startup polarity regi ster pmc_fspr read-write 0x0000_0000 0x0078 fault output clear register pmc_focr write-only ? 0x007c- 0x00e0 reserved ? ? ? 0x00e4 write protect mode register pmc_wpmr read-write 0x0 0x00e8 write protect status register pmc_wpsr read-only 0x0 0x00ec-0x010c reserved ? ? ? 0x0110 oscillator calibration register pmc_ocr read-write 0x0040_4040
355 11011a?atarm?04-oct-10 sam3n 24.15.1 pmc system clock enable register name: pmc_scer address: 0x400e0400 access: write-only this register can only be written if the wpen bit is cleared in ?pmc write protect mode register? on page 374 . ? pckx: programmable clock x output enable 0 = no effect. 1 = enables the corresponding programmable clock output. 24.15.2 pmc system clock disable register name: pmc_scdr address: 0x400e0404 access: write-only this register can only be written if the wpen bit is cleared in ?pmc write protect mode register? on page 374 . ? pckx: programmable clock x output disable 0 = no effect. 1 = disables the corresponding programmable clock output. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????pck2pck1pck0 76543210 ???????? 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????pck2pck1pck0 76543210 ????????
356 11011a?atarm?04-oct-10 sam3n 24.15.3 pmc system clock status register name: pmc_scsr address: 0x400e0408 access: read-only ? pckx: programmable clock x output status 0 = the corresponding programmable clock output is disabled. 1 = the corresponding programmable clock output is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????pck2pck1pck0 76543210 ????????
357 11011a?atarm?04-oct-10 sam3n 24.15.4 pmc peripheral clock enable register name: pmc_pcer address: 0x400e0410 access: write-only this register can only be written if the wpen bit is cleared in ?pmc write protect mode register? on page 374 . ? pidx: peripheral clock x enable 0 = no effect. 1 = enables the corresponding peripheral clock. note: pid2 to pid31 refer to identifiers as defined in the section ?peripheral identifiers ? in the product datasheet. note: programming the control bits of the peripheral id that ar e not implemented has no effect on the behavior of the pmc. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 ? ?
358 11011a?atarm?04-oct-10 sam3n 24.15.5 pmc peripheral clock disable register name: pmc_pcdr address: 0x400e0414 access: write-only this register can only be written if the wpen bit is cleared in ?pmc write protect mode register? on page 374 . ? pidx: peripheral clock x disable 0 = no effect. 1 = disables the corresponding peripheral clock. note: pid2 to pid31 refer to identifiers as defined in the section ?peripheral identifiers ? in the product datasheet. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 - -
359 11011a?atarm?04-oct-10 sam3n 24.15.6 pmc peripheral clock status register name: pmc_pcsr address: 0x400e0418 access: read-only ? pidx: peripheral clock x status 0 = the corresponding peripheral clock is disabled. 1 = the corresponding peripheral clock is enabled. note: pid2 to pid31 refer to identifiers as defined in the section ?peripheral identifiers ? in the product datasheet. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 ? ?
360 11011a?atarm?04-oct-10 sam3n 24.15.7 pmc clock generator main oscillator register name: ckgr_mor address: 0x400e0420 access: read-write this register can only be written if the wpen bit is cleared in ?pmc write protect mode register? on page 374 . ?key: password should be written at value 0x37. writing any other value in this field aborts the write operation. ? moscxten: main crystal oscillator enable a crystal must be connected between xin and xout. 0 = the main crystal oscillator is disabled. 1 = the main crystal oscillator is enabled. moscxtby must be set to 0. when moscxten is set, the moscxts flag is set once the main crystal oscillator startup time is achieved. ? moscxtby: main crystal oscillator bypass 0 = no effect. 1 = the main crystal oscillator is bypass ed. moscxten must be set to 0. an ex ternal clock must be connected on xin. when moscxtby is set, the moscxts flag in pmc_sr is automatically set. clearing moscxten and moscxtby bits allows resetting the moscxts flag. ? waitmode: wait mode command 0 = no effect. 1 = enters the device in wait mode. note: the bit waitmode is write-only ? moscrcen: main on-chip rc oscillator enable 0 = the main on-chip rc oscillator is disabled. 1 = the main on-chip rc oscillator is enabled. when moscrcen is set, the mo scrcs flag is set once the main on-chip rc oscillator startup time is achieved. 31 30 29 28 27 26 25 24 ??????cfdenmoscsel 23 22 21 20 19 18 17 16 key 15 14 13 12 11 10 9 8 moscxtst 76543210 ? moscrcf moscrcen waitmode moscxtby moscxten
361 11011a?atarm?04-oct-10 sam3n ? moscrcf: main on-chip rc oscillator frequency selection ? moscxtst: main crystal oscillator start-up time specifies the number of slow clock cycles multiplied by 8 for the main crystal oscillator start-up time. ? moscsel: main oscillator selection 0 = the main on-chip rc oscillator is selected. 1 = the main crystal os cillator is selected. ? cfden: clock failure detector enable 0 = the clock failure de tector is disabled. 1 = the clock failure de tector is enabled. value name description 0x0 4mhz the fast rc oscillator frequ ency is at 4 mhz (default) 0x1 8mhz the fast rc oscillator fr equency is at 8 mhz 0x2 12mhz the fast rc oscillator fr equency is at 12 mhz
362 11011a?atarm?04-oct-10 sam3n 24.15.8 pmc clock generator main clock frequency register name: ckgr_mcfr address: 0x400e0424 access: read-only this register can only be written if the wpen bit is cleared in ?pmc write protect mode register? on page 374 . ? mainf: main clock frequency gives the number of main clock cycles within 16 slow clock periods. ? mainfrdy: main clock ready 0 = mainf value is not valid or the main oscillator is disabled. 1 = the main oscillator has been enabled pr eviously and mainf value is available. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????mainfrdy 15 14 13 12 11 10 9 8 mainf 76543210 mainf
363 11011a?atarm?04-oct-10 sam3n 24.15.9 pmc clock generator pll register name: ckgr_pllr address: 0x400e0428 access: read-write possible limitations on pll input frequencies and multiplier factors should be checked before using the pmc. warning: bit 29 must always be set to 1 when programming the ckgr_pllr register. this register can only be written if the wpen bit is cleared in ?pmc write protect mode register? on page 374 . ?div: divider ? pllcount: pll counter specifies the number of slow clock cycles x8 before t he lock bit is set in pmc_sr after ckgr_pllr is written. ? mul: pll multiplier 0 = the pll is deactivated. 1 up to 2047 = the pll clock frequency is the pll input frequency multiplied by mul + 1. 31 30 29 28 27 26 25 24 ??1?? mul 23 22 21 20 19 18 17 16 mul 15 14 13 12 11 10 9 8 ? ? pllcount 76543210 div div divider selected 0 divider output is 0 1 divider is bypassed (div = 1) 2 - 255 divider output is div
364 11011a?atarm?04-oct-10 sam3n 24.15.10 pmc master clock register name: pmc_mckr address: 0x400e0430 access: read-write this register can only be written if the wpen bit is cleared in ?pmc write protect mode register? on page 374 . ? css: master clock source selection ? pres: processor clock prescaler ? plldiv2: pll divisor by 2 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???plldiv2???? 76543210 ?pres??css value name description 0 slow_clk slow clock is selected 1 main_clk main clock is selected 2 pll_clk pll clock is selected 3? reserved value name description 0 clk selected clock 1 clk_2 selected clock divided by 2 2 clk_4 selected clock divided by 4 3 clk_28 selected clock divided by 8 4 clk_16 selected clock divided by 16 5 clk_32 selected clock divided by 32 6 clk_64 selected clock divided by 64 7 clk_3 selected clock divided by 3 plldiv2 pll clock division 0 pll clock frequency is divided by 1 1 pll clock frequency is divided by 2
365 11011a?atarm?04-oct-10 sam3n 24.15.11 pmc programmable clock register name: pmc_pckx address: 0x400e0440 access: read-write this register can only be written if the wpen bit is cleared in ?pmc write protect mode register? on page 374 . ? css: master clock source selection ? pres: processor clock prescaler 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?pres? css value name description 0 slow_clk slow clock is selected 1 main_clk main clock is selected 2 plla_clk plla clock is selected 3 pllb_clk pllb clock is selected 4 mck master clock is selected value name description 0 clk selected clock 1 clk_2 selected clock divided by 2 2 clk_4 selected clock divided by 4 3 clk_28 selected clock divided by 8 4 clk_16 selected clock divided by 16 5 clk_32 selected clock divided by 32 6 clk_64 selected clock divided by 64
366 11011a?atarm?04-oct-10 sam3n 24.15.12 pmc interrupt enable register name: pmc_ier address: 0x400e0460 access: write-only ? moscxts: main crystal oscillator status interrupt enable ? lock: pll lock interrupt enable ? mckrdy: master clock ready interrupt enable ? pckrdyx: programmable clock ready x interrupt enable ? moscsels: main oscillator selection status interrupt enable ? moscrcs: main on-chip rc status interrupt enable ? cfdev: clock failure detector event interrupt enable 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????cfdevmoscrcsmoscsels 15 14 13 12 11 10 9 8 ?????pckrdy2pckrdy1pckrdy0 76543210 ????mckrdy?lockmoscxts
367 11011a?atarm?04-oct-10 sam3n 24.15.13 pmc interrupt disable register name: pmc_idr address: 0x400e0464 access: write-only ? moscxts: main crystal oscillator status interrupt disable ? lock: pll lock interrupt disable ? mckrdy: master clock ready interrupt disable ? pckrdyx: programmable clock ready x interrupt disable ? moscsels: main oscillator selection status interrupt disable ? moscrcs: main on-chip rc status interrupt disable ? cfdev: clock failure detector event interrupt disable 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????cfdevmoscrcsmoscsels 15 14 13 12 11 10 9 8 ?????pckrdy2pckrdy1pckrdy0 76543210 ????mckrdy?lockmoscxts
368 11011a?atarm?04-oct-10 sam3n 24.15.14 pmc status register name: pmc_sr address: 0x400e0468 access: read-only ? moscxts: main xtal oscillator status 0 = main xtal oscilla tor is not stabilized. 1 = main xtal osc illator is stabilized. ? lock: pll lock status 0 = pll is not locked 1 = pll is locked. ? mckrdy: master clock status 0 = master clock is not ready. 1 = master clock is ready. ? oscsels: slow clock oscillator selection 0 = internal slow clock rc oscillator is selected. 1 = external slow clock 32 khz oscillator is selected. ? pckrdyx: programmable clock ready status 0 = programmable clock x is not ready. 1 = programmable clock x is ready. ? moscsels: main oscillator selection status 0 = selection is in progress 1 = selection is done ? moscrcs: main on-chip rc oscillator status 0 = main on-chip rc osc illator is not stabilized. 1 = main on-chip rc o scillator is stabilized. ? cfdev: clock failure detector event 0 = no clock failure detection of the main on-chip rc oscillator clock has oc curred since the last read of pmc_sr. 1 = at least one clock failure det ection of the main on-chip rc oscillator clock has occurred si nce the last read of pmc_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? fos cfds cfdev moscrcs moscsels 15 14 13 12 11 10 9 8 ?????pckrdy2pckrdy1pckrdy0 76543210 oscsels ? ? ? mckrdy ? lock moscxts
369 11011a?atarm?04-oct-10 sam3n ? cfds: clock failure detector status 0 = a clock failure of the main on-chip rc oscillator clock is not detected. 1 = a clock failure of the main on-chip rc oscillator clock is detected. ? fos: clock failure detector fault output status 0 = the fault output of the clock failure detector is inactive. 1 = the fault output of the clock failure detector is active.
370 11011a?atarm?04-oct-10 sam3n 24.15.15 pmc interrupt mask register name: pmc_imr address: 0x400e046c access: read-only ? moscxts: main crystal oscillator status interrupt mask ? lock: pll lock interrupt mask ? mckrdy: master clock ready interrupt mask ? pckrdyx: programmable clock ready x interrupt mask ? moscsels: main oscillator selection status interrupt mask ? moscrcs: main on-chip rc status interrupt mask ? cfdev: clock failure detector event interrupt mask 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????cfdevmoscrcsmoscsels 15 14 13 12 11 10 9 8 ?????pckrdy2pckrdy1pckrdy0 76543210 ????mckrdy?lockmoscxts
371 11011a?atarm?04-oct-10 sam3n 24.15.16 pmc fast startup mode register name: pmc_fsmr address: 0x400e0470 access: read-write this register can only be written if the wpen bit is cleared in ?pmc write protect mode register? on page 374 . ? fstt0 - fstt15: fast startup input enable 0 to 15 0 = the corresponding wake up input has no effect on the power management controller. 1 = the corresponding wake up input enables a fast restart signal to the power management controller. ? rttal: rtt alarm enable 0 = the rtt alarm has no effect on the power management controller. 1 = the rtt alarm enables a fast restart signal to the power management controller. ? rtcal: rtc alarm enable 0 = the rtc alarm has no effect on the power management controller. 1 = the rtc alarm enables a fast restart signal to the power management controller. ? lpm: low power mode 0 = the waitforinterrupt (wfi) or waitforevent (wfe) instru ction of the processor causes the processor to enter idle mode. 1 = the waitforevent (wfe) instruction of the processor causes the system to enter wait mode. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???lpm??rtcalrttal 15 14 13 12 11 10 9 8 fstt15 fstt14 fstt13 fstt12 fstt11 fstt10 fstt9 fstt8 76543210 fstt7 fstt6 fstt5 fstt4 fstt3 fstt2 fstt1 fstt0
372 11011a?atarm?04-oct-10 sam3n 24.15.17 pmc fast startup polarity register name: pmc_fspr address: 0x400e0474 access: read-write this register can only be written if the wpen bit is cleared in ?pmc write protect mode register? on page 374 . ? fstpx: fast start up input polarityx defines the active polarity of the corresponding wake up inpu t. if the corresponding wake up input is enabled and at the fstp level, it enables a fast restart signal. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 fstp15 fstp14 fstp13 fstp12 fstp11 fstp10 fstp9 fstp8 76543210 fstp7 fstp6 fstp5 fstp4 fstp3 fstp2 fstp1 fstp0
373 11011a?atarm?04-oct-10 sam3n 24.15.18 pmc fault output clear register name: pmc_focr address: 0x400e0478 access: write-only ? foclr: fault output clear clears the clock failure detector fault output. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????foclr
374 11011a?atarm?04-oct-10 sam3n 24.15.19 pmc write protect mode register name: pmc_wpmr address: 0x400e04e4 access: read-write reset: see table 24-2 ? wpen: write protect enable 0 = disables the write protect if wpkey co rresponds to 0x504d43 (?pmc? in ascii). 1 = enables the write protect if wpkey corresponds to 0x504d43 (?pmc? in ascii). protects the registers: ? ?pmc system clock enable register? on page 355 ? ?pmc system clock disable register? on page 355 ? ?pmc peripheral clock enable register? on page 357 ? ?pmc peripheral clock disable register? on page 358 ? ?pmc clock generator main osc illator register? on page 360 ? ?pmc clock generator pll register? on page 363 ? ?pmc master clock register? on page 364 ? ?pmc programmable clock register? on page 365 ? ?pmc fast startup mode register? on page 371 ? ?pmc fast startup polarity register? on page 372 ? ?pmc oscillator calibration register? on page 376 ? wpkey: write protect key should be written at value 0x504d43 (?pmc? in ascii). writing an y other value in this field aborts the write operation of the wpen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 ???????wpen
375 11011a?atarm?04-oct-10 sam3n 24.15.20 pmc write protect status register name: pmc_wpsr address: 0x400e04e8 access: read-only reset: see table 24-2 ? wpvs: write protect violation status 0 = no write protect violation has occurred since the last read of the pmc_wpsr register. 1 = a write protect violation has occurred since the last read of the pmc_wpsr register. if this violation is an unauthor- ized attempt to write a protected register, the associated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. reading pmc_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 ???????wpvs
376 11011a?atarm?04-oct-10 sam3n 24.15.21 pmc oscillator calibration register name: pmc_ocr address: 0x400e0510 access: read-write this register can only be written if the wpen bit is cleared in ?pmc write protect mode register? on page 374 . ? cal4: rc oscillator cali bration bits for 4 mhz calibration bits applied to th e rc oscillator when sel4 is set. ? sel4: selection of rc oscillator calibration bits for 4 mhz 0 = default value stored in flash memory. 1 = value written by user in cal4 field of this register. ? cal8: rc oscillator cali bration bits for 8 mhz calibration bits applied to th e rc oscillator when sel8 is set. ? sel8: selection of rc oscillator calibration bits for 8 mhz 0 = factory determined value stored in flash memory. 1 = value written by user in cal8 field of this register. ? cal12: rc oscillator calibration bits for 12 mhz calibration bits app lied to the rc oscillator when sel12 is set. ? sel12: selection of rc oscillator calibration bits for 12 mhz 0 = factory determined value stored in flash memory. 1 = value written by user in cal12 field of this register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 sel12 cal12 15 14 13 12 11 10 9 8 sel8 cal8 76543210 sel4 cal4
377 11011a?atarm?04-oct-10 sam3n 377 11011a?atarm?04-oct-10 sam3n 25. chip identifier (chipid) 25.1 description chip identifier registers permit recognition of the device and its revision. these registers provide the sizes and types of the on-chip memories, as well as the set of embedded peripherals. two chip identifier registers are embedded: chipid_cidr (chip id register) and chipid_exid (extension id). both registers contain a hard-wired value that is read-only. the first register con- tains the following fields: ? ext - shows the use of the extension identifier register ? nvptyp and nvpsiz - identifies the type of embedded non-volatile memory and its size ? arch - identifies the set of embedded peripherals ? sramsiz - indicates the size of the embedded sram ? eproc - indicates the embedded arm processor ? version - gives the revision of the silicon the second register is device-dependent and reads 0 if the bit ext is 0. table 25-1. atsam3n chip ids register chip name chipi d_cidr chipid_exid atsam3n4c (rev a) 0x29540960 0x0 atsam3n2c (rev a) 0x29590760 0x0 atsam3n1c (rev a) 0x29580560 0x0 atsam3n4b (rev a) 0x29440960 0x0 atsam3n2b (rev a) 0x29490760 0x0 atsam3n1b (rev a) 0x29480560 0x0 atsam3n4a (rev a) 0x29340960 0x0 atsam3n2a (rev a) 0x29390760 0x0 atsam3n1a (rev a) 0x29380560 0x0
378 11011a?atarm?04-oct-10 sam3n 378 11011a?atarm?04-oct-10 sam3n 25.2 chip identifier (chi pid) user interface table 25-2. register mapping offset register name access reset 0x0 chip id register chipid_cidr read-only ? 0x4 chip id extension register chipid_exid read-only ?
379 11011a?atarm?04-oct-10 sam3n 379 11011a?atarm?04-oct-10 sam3n 25.2.1 chip id register name: chipid_cidr address: 0x400e0740 access: read-only ? version: version of the device current version of the device. ? eproc: embedded processor ? nvpsiz: nonvolatile program memory size 31 30 29 28 27 26 25 24 ext nvptyp arch 23 22 21 20 19 18 17 16 arch sramsiz 15 14 13 12 11 10 9 8 nvpsiz2 nvpsiz 76543210 eproc version value name description 1 arm946es arm946es 2 arm7tdmi arm7tdmi 3 cm3 cortex-m3 4 arm920t arm920t 5 arm926ejs arm926ejs 6ca5 cortex-a5 value name description 0none none 18k 8k bytes 2 16k 16k bytes 3 32k 32k bytes 4reserved 5 64k 64k bytes 6reserved 7 128k 128k bytes 8reserved 9 256k 256k bytes 10 512k 512k bytes 11 reserved 12 1024k 1024k bytes
380 11011a?atarm?04-oct-10 sam3n 380 11011a?atarm?04-oct-10 sam3n ? nvpsiz2 second nonvolatile program memory size ? sramsiz: internal sram size 13 reserved 14 2048k 2048k bytes 15 reserved value name description 0 none none 18k 8k bytes 2 16k 16k bytes 3 32k 32k bytes 4 reserved 5 64k 64k bytes 6 reserved 7 128k 128k bytes 8 reserved 9 256k 256k bytes 10 512k 512k bytes 11 reserved 12 1024k 1024k bytes 13 reserved 14 2048k 2048k bytes 15 reserved value name description 0 48k 48k bytes 11k 1k bytes 22k 2k bytes 36k 6k bytes 4 112k 112k bytes 54k 4k bytes 6 80k 80k bytes 7 160k 160k bytes 88k 8k bytes 9 16k 16k bytes 10 32k 32k bytes 11 64k 64k bytes 12 128k 128k bytes value name description
381 11011a?atarm?04-oct-10 sam3n 381 11011a?atarm?04-oct-10 sam3n ? arch: architecture identifier 13 256k 256k bytes 14 96k 96k bytes 15 512k 512k bytes value name description 0x19 at91sam9xx at91sam9xx series 0x29 at91sam9xexx at91sam9xexx series 0x34 at91x34 at91x34 series 0x37 cap7 cap7 series 0x39 cap9 cap9 series 0x3b cap11 cap11 series 0x40 at91x40 at91x40 series 0x42 at91x42 at91x42 series 0x55 at91x55 at91x55 series 0x60 at91sam7axx at91sam7axx series 0x61 at91sam7aqxx at91sam7aqxx series 0x63 at91x63 at91x63 series 0x70 at91sam7sxx at91sam7sxx series 0x71 at91sam7xcxx at91sam7xcxx series 0x72 at91sam7sexx at91sam7sexx series 0x73 at91sam7lxx at91sam7lxx series 0x75 at91sam7xxx at91sam7xxx series 0x76 at91sam7slxx at91sam7slxx series 0x80 atsam3uxc atsam3uxc series (100-pin version) 0x81 atsam3uxe atsam3uxe series (144-pin version) 0x83 atsam3axc atsam3axc series (100-pin version) 0x84 atsam3xxc atsam3xxc series (100-pin version) 0x85 atsam3xxe atsam3xxe series (144-pin version) 0x86 atsam3xxg atsam3xxg series (208/217-pin version) 0x88 atsam3sxa atsam3sxa series (48-pin version) 0x89 atsam3sxb atsam3sxb series (64-pin version) 0x8a atsam3sxc atsam3sxc series (100-pin version) 0x92 at91x92 at91x92 series 0x93 atsam3nxa atsam3nxa series (48-pin version) 0x94 atsam3nxb atsam3nxb series (64-pin version) 0x95 atsam3nxc atsam3nxc series (100-pin version) value name description
382 11011a?atarm?04-oct-10 sam3n 382 11011a?atarm?04-oct-10 sam3n ? nvptyp: nonvolatile program memory type ? ext: extension flag 0 = chip id has a single register definition without extension 1 = an extended chip id exists. 0x98 atsam3sdxa atsam3sdxa series (48-pin version) 0x99 atsam3sdxb atsam3sdxb series (64-pin version) 0x9a atsam3sdxc atsam3sdxc series (100-pin version) 0xa5 atsam5a atsam5a 0xf0 at75cxx at75cxx series value name description 0rom rom 1 romless romless or on-chip flash 4 sram sram emulating rom 2 flash embedded flash memory 3 rom_flash rom and embedded flash memory nvpsiz is rom size nvpsiz2 is flash size value name description
383 11011a?atarm?04-oct-10 sam3n 383 11011a?atarm?04-oct-10 sam3n 25.2.2 chip id extension register name: chipid_exid address: 0x400e0744 access: read-only ? exid: chip id extension reads 0 if the bit ext in chipid_cidr is 0. 31 30 29 28 27 26 25 24 exid 23 22 21 20 19 18 17 16 exid 15 14 13 12 11 10 9 8 exid 76543210 exid
384 11011a?atarm?04-oct-10 sam3n 384 11011a?atarm?04-oct-10 sam3n
385 11011a?atarm?04-oct-10 sam3n 385 11011a?atarm?04-oct-10 sam3n 26. parallel input/outp ut (pio) controller 26.1 description the parallel input/output controller (pio) manages up to 32 fully programmable input/output lines. each i/o line may be dedicated as a general-purpose i/o or be assigned to a function of an embedded peripheral. this assures effective optimization of the pins of a product. each i/o line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface. each i/o line of the pio controller features: ? an input change interrupt enabling level change detection on any i/o line. ? additional interrupt modes enab ling rising edge, falling edge, low level or high level detection on any i/o line. ? a glitch filter providing rejection of glitches lower than one-half of pio clock cycle. ? a debouncing filter providing rejection of unwanted pulses from key or push button operations. ? multi-drive capability similar to an open drain i/o line. ? control of the pull-up and pull-down of the i/o line. ? input visibility a nd output control. the pio controller also features a synchronous output providing up to 32 bits of data output in a single write operation. 26.2 embedded characteristics ? up to 32 programmable i/o lines ? fully programmable through set/clear registers ? multiplexing of four peripheral functions per i/o line ? for each i/o line (whether assigned to a peripheral or used as general purpose i/o) ? input change interrupt ? programmable glitch filter ? programmable debouncing filter ? multi-drive option enables driving in open drain ? programmable pull up on each i/o line ? pin data status re gister, supplies visibility of the level on the pin at any time ? additional interrupt modes on a programmable event: rising edge, falling edge, low level or high level ? lock of the configuration by the connected peripheral ? synchronous output, provides set and clear of several i/o lines in a single write ? write protect registers ? programmable schmitt trigger inputs
386 11011a?atarm?04-oct-10 sam3n 386 11011a?atarm?04-oct-10 sam3n 26.3 block diagram figure 26-1. block diagram figure 26-2. application block diagram em b edded peripher a l em b edded peripher a l pio interr u pt pio controller up to 3 2 pin s pmc up to 3 2 peripher a l io s up to 3 2 peripher a l io s pio clock apb interr u pt controller d a t a , en ab le pin 3 1 pin 1 pin 0 d a t a , en ab le on-chip peripherals pio controller on-chip peripheral drivers control & command driver keyboard driver keyboard driver general purpose i/os external devices
387 11011a?atarm?04-oct-10 sam3n 387 11011a?atarm?04-oct-10 sam3n 26.4 product dependencies 26.4.1 pin multiplexing each pin is configurable, according to product definition as either a general-purpose i/o line only, or as an i/o line multiplexed with one or two peripheral i/os. as the multiplexing is hard- ware defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the pio controllers required by their application. when an i/o line is general-purpose only, i.e. not multiplexed with any peripheral i/o, programming of the pio controller regarding the assignment to a peripheral has no effect and only the pio con- troller can control how the pin is driven by the product. 26.4.2 power management the power management controller controls the pio controller clock in order to save power. writing any of the registers of the user interface does not require the pio controller clock to be enabled. this means that the configuration of the i/o lines does not require the pio controller clock to be enabled. however, when the clock is disabled, not all of t he features of the pio controller are available, including glitch filtering. note that the input change interrupt, interrupt modes on a programma- ble event and the read of the pin level require the clock to be validated. after a hardware reset, the pio clock is disabled by default. the user must configure the power management controller before any access to the input line information. 26.4.3 interrupt generation the pio controller is connected on one of the sources of the nested vectored interrupt control- ler (nvic). using the pio controller requires the nvic to be programmed first. the pio controller interrupt can be generated only if the pio controller clock is enabled.
388 11011a?atarm?04-oct-10 sam3n 388 11011a?atarm?04-oct-10 sam3n 26.5 functional description the pio controller features up to 32 fully-programmable i/o lines. most of the control logic asso- ciated to each i/o is represented in figure 26-3 . in this description each signal shown represents but one of up to 32 possible indexes. figure 26-3. i/o line control logic 1 0 1 0 1 0 1 0 dq dq dff 1 0 1 0 11 00 01 10 programmable glitch or debouncing filter pio_pdsr[0] pio_isr[0] pio_idr[0] pio_imr[0] pio_ier[0] pio interrupt (up to 32 possible inputs) pio_isr[31] pio_idr[31] pio_imr[31] pio_ier[31] pad pio_pudr[0] pio_pusr[0] pio_puer[0] pio_mddr[0] pio_mdsr[0] pio_mder[0] pio_codr[0] pio_odsr[0] pio_sodr[0] pio_pdr[0] pio_psr[0] pio_per[0] pio_abcdsr1[0] pio_odr[0] pio_osr[0] pio_oer[0] resynchronization stage peripheral a input peripheral d output enable peripheral a output enable event detector dff pio_ifdr[0] pio_ifsr[0] pio_ifer[0] system clock clock divider pio_ifscr[0] pio_dcifsr[0] pio_scifsr[0] pio_scdr slow clock peripheral b output enable peripheral c output enable 11 00 01 10 peripheral d output peripheral a output peripheral b output peripheral c output pio_abcdsr2[0] peripheral b input peripheral c input peripheral d input
389 11011a?atarm?04-oct-10 sam3n 389 11011a?atarm?04-oct-10 sam3n 26.5.1 pull-up and pull-down resistor control each i/o line is designed with an embedded pull-up resistor and an embedded pull-down resis- tor. the pull-up resistor can be enabled or disabl ed by writing respectively pio_puer (pull-up enable register) and pio_pudr (pull-up disable resistor). writing in these registers results in setting or clearing the corresponding bit in pio_pusr (pull-up status register). reading a 1 in pio_pusr means the pull-up is disabled and reading a 0 means the pull-up is enabled. the pull-down resistor can be enabled or disabled by writing respectively pio_ppder (pull-down enable register) and pio_ppddr (pull-down disab le resistor). writing in these registers results in setting or clearing the corresponding bit in pio_ppdsr (pull-down status register). reading a 1 in pio_ppdsr means the pull-up is disabled and reading a 0 means the pull-down is enabled. enabling the pull-down resistor while the pull-up resistor is still enabled is not possible. in this case, the write of pio_ppder for the concerned i/o line is discarded. likewise, enabling the pull-up resistor while the pull-down resistor is still enabled is not possible. in this case, the write of pio_puer for the concerned i/o line is discarded. control of the pull-up resistor is possible regardless of the configuration of the i/o line. after reset, all of the pull-ups are enabled, i.e. pio_pusr resets at the value 0x0, and all the pull-downs are disabled, i.e. pio_ppdsr resets at the value 0xffffffff. 26.5.2 i/o line or peripheral function selection when a pin is multiplexed with one or two periph eral functions, the selection is controlled with the registers pio_per (pio enable register) and pio_pdr (pio disable register). the regis- ter pio_psr (pio status register) is the resu lt of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the pio controller. a value of 0 indicates that the pin is controlled by the co rresponding on-chip peripheral selected in the pio_abcdsr1 and pio_abcdsr2 (abcd select regi sters). a value of 1 indicates the pin is controlled by the pio controller. if a pin is used as a general purpose i/o line (not multiplexed with an on-chip peripheral), pio_per and pio_pdr have no effect and pio_psr returns 1 for the corresponding bit. after reset, most generally, the i/o lines are controlled by the pio controller, i.e. pio_psr resets at 1. however, in some events, it is important that pio lines are controlled by the periph- eral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). thus, the reset value of pio_psr is defined at the product level, depending on the multiplexing of the device. 26.5.3 peripheral a or b or c or d selection the pio controller provides multiplexing of up to four peripheral functions on a single pin. the selection is performed by writ ing pio_abcdsr1 and pio_abcdsr2 (abcd select registers). for each pin: ? the corresponding bit at level 0 in pio_abcdsr1 and the corresponding bit at level 0 in pio_abcdsr2 means peripheral a is selected. ? the corresponding bit at level 1 in pio_abcdsr1 and the corresponding bit at level 0 in pio_abcdsr2 means peripheral b is selected. ? the corresponding bit at level 0 in pio_abcdsr1 and the corresponding bit at level 1 in pio_abcdsr2 means periph eral c is selected.
390 11011a?atarm?04-oct-10 sam3n 390 11011a?atarm?04-oct-10 sam3n ? the corresponding bit at level 1 in pio_abcdsr1 and the corresponding bit at level 1 in pio_abcdsr2 means periph eral d is selected. note that multiplexing of peripheral lines a, b, c and d only affects the output line. the periph- eral input lines are always connected to the pin input. after reset, pio_abcdsr1 and pio_abcdsr2 are 0, thus indicating that all the pio lines are configured on peripheral a. however, peripheral a generally does not drive the pin as the pio controller resets in i/o line mode. writing in pio_abcdsr1 and pio_abcdsr2 man ages the multiplexing regardless of the con- figuration of the pin. however, assignment of a pin to a peripheral function requires a write in the peripheral selection registers (pio_abcdsr1 and pio_abcdsr2) in addition to a write in pio_pdr. 26.5.4 output control when the i/0 line is assigned to a peripheral func tion, i.e. the corresponding bit in pio_psr is at 0, the drive of the i/o line is controlled by the peripheral. peripheral a or b or c or d depending on the value in pio_abcdsr1 and pio_abcds r2 (abcd select registers) determines whether the pin is driven or not. when the i/o line is controlled by the pio controller, the pin can be configured to be driven. this is done by writing pio_oer (output enable register) and pio_odr (output disable register). the results of these write operations are detected in pio_osr (output status register). when a bit in this register is at 0, the corresponding i/o line is used as an input only. when the bit is at 1, the corresponding i/o line is driven by the pio controller. the level driven on an i/o line can be determined by writing in pio_sodr (set output data register) and pio_codr (cle ar output data register). these write operations respectively set and clear pio_odsr (output data status register ), which represents the data driven on the i/o lines. writing in pio_oer and pio_odr manage s pio_osr whether the pin is configured to be controlled by the pio controller or assigned to a peripheral function. this enables configura- tion of the i/o line prior to setting it to be managed by the pio controller. similarly, writing in pio_sodr and pio_codr effects pio_odsr. this is important as it defines the first level driven on the i/o line. 26.5.5 synchronous data output clearing one (or more) pio line(s) and setting another one (or more) pio line(s) synchronously cannot be done by using pio_sodr and pio_codr registers. it requires two successive write operations into two different registers. to overco me this, the pio controller offers a direct con- trol of pio outputs by single write access to pio_odsr (output data status register).only bits unmasked by pio_owsr (output write status register) are written. the mask bits in pio_owsr are set by writing to pio_ower (output write enable register) and cleared by writing to pio_owdr (out put write disable register). after reset, the synchronous data output is disabled on all the i/o lines as pio_owsr resets at 0x0. 26.5.6 multi drive control (open drain) each i/o can be independently programmed in open drain by using the multi drive feature. this feature permits several drivers to be connected on the i/o line which is driven low only by each device. an external pull-up resistor (or enabling of the internal one) is generally required to guar- antee a high level on the line.
391 11011a?atarm?04-oct-10 sam3n 391 11011a?atarm?04-oct-10 sam3n the multi drive feature is controlled by pio_mder (multi-driver enable register) and pio_mddr (multi-driver disable register). the multi drive can be selected whether the i/o line is controlled by the pio controller or assigned to a peripheral function. pio_mdsr (multi-driver status register) indicates the pins that are configured to support external drivers. after reset, the multi drive feature is disabled on all pins, i.e. pio_mdsr resets at value 0x0. 26.5.7 output line timings figure 26-4 shows how the outputs are driven either by writing pio_sodr or pio_codr, or by directly writing pio_odsr. this last case is va lid only if the corresponding bit in pio_owsr is set. figure 26-4 also shows when the feedback in pio_pdsr is available. figure 26-4. output line timings 26.5.8 inputs the level on each i/o line can be read through pio_pdsr (pin data status register). this reg- ister indicates the level of the i/o lines regardless of their configuration, whether uniquely as an input or driven by the pio controller or driven by a peripheral. reading the i/o line levels requires the clock of the pio controller to be enabled, otherwise pio_pdsr reads the levels present on the i/o line at the time the clock was disabled. 26.5.9 input glitch and debouncing filters optional input glitch and debouncing filters are independently programmable on each i/o line. the glitch filter can filter a g litch with a duration of less than 1/2 master clock (mck) and the debouncing filter can filter a pulse of less than 1/2 period of a programmable divided slow clock. the selection between glitch filtering or debounce filtering is done by writing in the registers pio_ifscdr (pio input filter slow clock disable register) and pio_ifscer (pio input filter slow clock enable register). writing pio_if scdr and pio_ifscer respectively, sets and clears bits in pio_ifscsr. the current selection status can be checked by reading the register pio_ifscsr (input filter slow clock status register). ? if pio_ifscsr[i] = 0: the glitch filter can filter a glitch with a duration of less than 1/2 period of master clock. 2 cycles apb access 2 cycles apb access mck write pio_sodr write pio_odsr at 1 pio_odsr pio_pdsr write pio_codr write pio_odsr at 0
392 11011a?atarm?04-oct-10 sam3n 392 11011a?atarm?04-oct-10 sam3n ? if pio_ifscsr[i] = 1: the debouncing filter can filter a pulse with a duration of less than 1/2 period of the programmable divided slow clock. for the debouncing filter, the period of the divided slow clock is performed by writing in the div field of the pio_scdr (slow clock divider register) tdiv_slclk = ((div+1)*2).tslow_clock when the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 selected clock cycle (selected clock represents mck or divided slow clock depending on pio_ifscdr and pio_ifscer programming) is autom atically rejected, while a pulse with a duration of 1 selected clock (mck or divided slow clock) cycle or more is accepted. for pulse durations between 1/2 selected clock cycle and 1 selected clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. thus for a pulse to be visible it must exceed 1 selected clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 selected clock cycle. the filters also introduce some la tencies, this is illustrated in figure 26-5 and figure 26-6 . the glitch filters are controlled by the regist er set: pio_ifer (input filter enable register), pio_ifdr (input filter disable register) and pio_ifsr (input filter status register). writing pio_ifer and pio_ifdr respectively sets and clears bits in pio_ifsr. this last register enables the glitch filt er on the i/o lines. when the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the peripherals. it acts only on the value read in pio_pdsr and on the input change interrupt detection. the glitch and debouncing filters require that the pio controller clock is enabled. figure 26-5. input glitch filter timing mck pin level pio_pdsr if pio_ifsr = 0 pio_pdsr if pio_ifsr = 1 1 cycle 1 cycle 1 cycle up to 1.5 cycles 2 cycles up to 2.5 cycles up to 2 cycles 1 cycle 1 cycle pio_ifcsr = 0
393 11011a?atarm?04-oct-10 sam3n 393 11011a?atarm?04-oct-10 sam3n figure 26-6. input debouncing filter timing 26.5.10 input edge/level interrupt the pio controller can be programmed to generate an interrupt when it detects an edge or a level on an i/o line. the input edge/level interrupt is controlled by writing pio_ier (interrupt enable register) and pio_idr (interrupt disable register), which respectively enable and dis- able the input change interrupt by setting and clearing the corresponding bit in pio_imr (interrupt mask register). as input change detection is possible only by comparing two succes- sive samplings of the input of the i/o line, t he pio controller clock must be enabled. the input change interrupt is available, regardless of the configuration of the i/o line, i.e. configured as an input only, controlled by the pio controller or assigned to a peripheral function. by default, the interrupt can be generated at any time an edge is detected on the input. some additional interrupt modes can be enabled/disabled by writing in the pio_aimer (addi- tional interrupt modes enable register) and pio_aimdr (additional interrupt modes disable register). the current state of this sele ction can be read through the pio_aimmr (additional interrupt modes mask register) these additional modes are: ? rising edge detection ? falling edge detection ? low level detection ? high level detection in order to select an additional interrupt mode: ? the type of event detection (edge or level) must be selected by writing in the set of registers; pio_esr (edge select register) and pio_lsr (level select register) which enable respectively, the edge and level detection. the current status of this selection is accessible through the pio_elsr (edge/level status register). ? the polarity of the event detection (rising/fa lling edge or high/low level) must be selected by writing in the set of regist ers; pio_fellsr (falling edge /l ow level select register) and pio_rehlsr (rising edge/high level select register) which allow to select falling or rising edge (if edge is selected in the pio_el sr) edge or high or low level detection (if divided slow clock pin level pio_pdsr if pio_ifsr = 0 pio_pdsr if pio_ifsr = 1 1 cycle tdiv_slclk up to 1.5 cycles tdiv_slclk 1 cycle tdiv_slclk up to 2 cycles tmck up to 2 cycles tmck up to 2 cycles tmck up to 2 cycles tmck up to 1.5 cycles tdiv_slclk pio_ifcsr = 1
394 11011a?atarm?04-oct-10 sam3n 394 11011a?atarm?04-oct-10 sam3n level is selected in the pio_elsr). the current status of this selection is accessible through the pio_frlhsr (fall/rise - low/high status register). when an input edge or level is detected on an i/o line, the corresponding bit in pio_isr (inter- rupt status register) is set. if the correspo nding bit in pio_imr is set, the pio controller interrupt line is asserted. the interrupt signals of the thirty-two channels are ored-wired together to generate a single interrupt signal to the . nested vector interrupt controller (nvic). when the software reads pio_isr, all the interrupts are automatically cleared. this signifies that all the interrupts that are pending when pio_isr is read must be handled. when an interrupt is enabled on a ?level?, the interrupt is generated as long as the interrupt source is not cleared, even if some read accesses in pio_isr are performed. figure 26-7. event detector on input lines (figure represents line 0) 26.5.10.1 example if generating an interrupt is required on the following: ? rising edge on pio line 0 ? falling edge on pio line 1 ? rising edge on pio line 2 ? low level on pio line 3 ? high level on pio line 4 ? high level on pio line 5 ? falling edge on pio line 6 ? rising edge on pio line 7 ? any edge on the other lines the configuration required is described below. event detector 0 1 0 1 1 0 0 1 edge detector falling edge detector rising edge detector pio_fellsr[0] pio_frlhsr[0] pio_rehlsr[0] low level detector high level detector pio_esr[0] pio_elsr[0] pio_lsr[0] pio_aimdr[0] pio_aimmr[0] pio_aimer[0] event detection on line 0 resynchronized input on line 0
395 11011a?atarm?04-oct-10 sam3n 395 11011a?atarm?04-oct-10 sam3n 26.5.10.2 interrupt mode configuration all the interrupt sources are enabled by writing 32?hffff_ffff in pio_ier. then the additional interrupt mode is enabled for line 0 to 7 by writing 32?h0000_00ff in pio_aimer. 26.5.10.3 edge or level detection configuration lines 3, 4 and 5 are configured in level detection by writing 32?h0000_0038 in pio_lsr. the other lines are configured in edge detection by default, if they have not been previously con- figured. otherwise, lines 0, 1, 2, 6 and 7 must be configured in edge detection by writing 32?h0000_00c7 in pio_esr. 26.5.10.4 falling/rising edge or low/ high level detection configuration. lines 0, 2, 4, 5 and 7 are configured in rising edge or high level detection by writing 32?h0000_00b5 in pio_rehlsr. the other lines are configured in falling edge or low level detection by default, if they have not been previously configured. othe rwise, lines 1, 3 and 6 must be configured in falling edge/low level detection by writing 32?h0000_004a in pio_fellsr. figure 26-8. input change interrupt timings if there are no additional interrupt modes 26.5.11 i/o lines lock when an i/o line is controlled by a peripheral (particularly the pulse width modulation controller pwm), it can become locked by the action of th is peripheral via an input of the pio controller. when an i/o line is locked, the write of the corresponding bit in the registers pio_per, pio_pdr, pio_mder, pio_mddr, p io_pudr, pio_puer, pio_abcdsr1 and pio_abcdsr2 is discarded in order to lock its configuration. the user can know at anytime which i/o line is locked by reading the pio lock status register pio_locksr. once an i/o line is locked, the only way to unlock it is to apply a hardware reset to the pio controller. 26.5.12 programmable schmitt trigger it is possible to configure each input for the schmitt trigger. by default the schmitt trigger is active. disabling the schmitt trigger is requested when using the qtouch ? library. mck pin level read pio_isr apb access pio_isr apb access
396 11011a?atarm?04-oct-10 sam3n 396 11011a?atarm?04-oct-10 sam3n 26.5.13 write protection registers to prevent any single software error that may corrupt pio behavior, certain address spaces can be write-protected by setting the wpen bit in the ?pio write protect mode register? (pio_wpmr). if a write access to the protecte d registers is detected, then th e wpvs flag in the pio write pro- tect status register (pio_wpsr) is set and the field wpvsrc indicates in which register the write access has been attempted. the wpvs flag is reset by writ ing the pio write protect mode register (pio_wpmr) with the appropriate access key, wpkey. the protected registers are: ? ?pio enable register? on page 401 ? ?pio disable register? on page 401 ? ?pio output enable register? on page 402 ? ?pio output disable register? on page 403 ? ?pio input filter enable register? on page 404 ? ?pio input filter disable register? on page 404 ? ?pio multi-driver enable register? on page 409 ? ?pio multi-driver disable register? on page 410 ? ?pio pull up disable register? on page 411 ? ?pio pull up enable register? on page 411 ? ?pio peripheral abcd select register 1? on page 413 ? ?pio peripheral abcd select register 2? on page 414 ? ?pio output write enable register? on page 419 ? ?pio output write disable register? on page 419 ? ?pio pad pull down disable register? on page 417 ? ?pio pad pull down status register? on page 418
397 11011a?atarm?04-oct-10 sam3n 397 11011a?atarm?04-oct-10 sam3n 26.6 i/o lines programming example the programing example as shown in table 26-1 below is used to obtain the following configuration. ? 4-bit output port on i/o lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor ? four output signals on i/o lines 4 to 7 (to drive leds for example), driven high and low, no pull-up resistor, no pull-down resistor ? four input signals on i/o lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts ? four input signals on i/o line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter ? i/o lines 16 to 19 assigned to peripheral a functions with pull-up resistor ? i/o lines 20 to 23 assigned to peripheral b functions with pull-down resistor ? i/o line 24 to 27 assigned to peripheral c with input change interrupt, no pull-up resistor and no pull-down resistor ? i/o line 28 to 31 assigned to peripheral d, no pull-up resistor and no pull-down resistor table 26-1. programming example register value to be written pio_per 0x0000_ffff pio_pdr 0xffff_0000 pio_oer 0x0000_00ff pio_odr 0xffff_ff00 pio_ifer 0x0000_0f00 pio_ifdr 0xffff_f0ff pio_sodr 0x0000_0000 pio_codr 0x0fff_ffff pio_ier 0x0f00_0f00 pio_idr 0xf0ff_f0ff pio_mder 0x0000_000f pio_mddr 0xffff_fff0 pio_pudr 0xfff0_00f0 pio_puer 0x000f_ff0f pio_ppddr 0xff0f_ffff pio_ppder 0x00f0_0000 pio_abcdsr1 0xf0f0_0000 pio_abcdsr2 0xff00_0000 pio_ower 0x0000_000f pio_owdr 0x0fff_ fff0
398 11011a?atarm?04-oct-10 sam3n 398 11011a?atarm?04-oct-10 sam3n 26.7 parallel input/output cont roller (pio) user interface each i/o line controlled by the pio controller is associated with a bit in each of the pio control- ler user interface registers. each register is 32 bits wide. if a parallel i/o line is not defined, writing to the corresponding bits has no effect. undefined bits read zero. if the i/o line is not mul- tiplexed with any peripheral, the i/o line is controlled by the pio controller and pio_psr returns 1 systematically. table 26-2. register mapping offset register name access reset 0x0000 pio enable register pio_per write-only ? 0x0004 pio disable register pio_pdr write-only ? 0x0008 pio status register pio_psr read-only (1) 0x000c reserved 0x0010 output enable register pio_oer write-only ? 0x0014 output disable register pio_odr write-only ? 0x0018 output status regist er pio_osr read-only 0x0000 0000 0x001c reserved 0x0020 glitch input filter enab le register pio_ifer write-only ? 0x0024 glitch input filter disab le register pio_ifdr write-only ? 0x0028 glitch input filt er status register pio_ ifsr read-only 0x0000 0000 0x002c reserved 0x0030 set output data r egister pio_sodr write-only ? 0x0034 clear output data register pio_codr write-only 0x0038 output data status register pio_odsr read-only or (2) read-write ? 0x003c pin data status register pio_pdsr read-only (3) 0x0040 interrupt enable register pio_ier write-only ? 0x0044 interrupt disable register pio_idr write-only ? 0x0048 interrupt mask register pio_imr read-only 0x00000000 0x004c interrupt status register (4) pio_isr read-only 0x00000000 0x0050 multi-driver enable register pio_mder write-only ? 0x0054 multi-driver disable register pio_mddr write-only ? 0x0058 multi-driver status r egister pio_mdsr read-only 0x00000000 0x005c reserved ? ? ? 0x0060 pull-up disable register pio_pudr write-only ? 0x0064 pull-up enable register pio_puer write-only ? 0x0068 pad pull-up status register pio_pusr read-only 0x00000000 0x006c reserved ? ? ?
399 11011a?atarm?04-oct-10 sam3n 399 11011a?atarm?04-oct-10 sam3n 0x0070 peripheral select register 1 pio_abcdsr1 read-write 0x00000000 0x0074 peripheral select register 2 pio_abcdsr2 read-write 0x00000000 0x0078 to 0x007c reserved ? ? ? 0x0080 input filter slow clock disa ble register pio_ifscdr write-only ? 0x0084 input filter slow clock enab le register pio_ifscer write-only ? 0x0088 input filter slow clock status register pio_ifscsr read-only 0x00000000 0x008c slow clock divider debouncing register pio_scdr read-write 0x00000000 0x0090 pad pull-down disable register pio_ppddr write-only ? 0x0094 pad pull-down enable register pio_ppder write-only ? 0x0098 pad pull-down status register pio_ppdsr read-only 0xffffffff 0x009c reserved ? ? 0x00a0 output write enab le pio_ower write-only ? 0x00a4 output write disable pio_owdr write-only ? 0x00a8 output write status register pio_owsr read-only 0x00000000 0x00ac reserved ? ? 0x00b0 additional interrupt modes enable register pio_aimer write-only ? 0x00b4 additional interrupt modes disables register pio_aimdr write-only ? 0x00b8 additional interrupt modes mask register pio_aimmr read-only 0x00000000 0x00bc reserved ? ? ? 0x00c0 edge select register pio_esr write-only ? 0x00c4 level select register pio_lsr write-only ? 0x00c8 edge/level status regi ster pio_elsr read-only 0x00000000 0x00cc reserved ? ? ? 0x00d0 falling edge/low level select register pio_fellsr write-only ? 0x00d4 rising edge/ high level select register pio_rehlsr write-only ? 0x00d8 fall/rise - low/high status register pio_frlhsr read-only 0x00000000 0x00dc reserved ? ? ? 0x00e0 lock status pio_locksr read-only 0x00000000 0x00e4 write protect mode r egister pio_wpmr read-write 0x0 0x00e8 write protect status register pio_wpsr read-only 0x0 0x00ec to 0x00f8 reserved ? ? ? 0x0100 schmitt trigger register pio_schmitt read-write 0x00000000 table 26-2. register mapping (continued) offset register name access reset
400 11011a?atarm?04-oct-10 sam3n 400 11011a?atarm?04-oct-10 sam3n notes: 1. reset value of pio_psr depends on the product implementation. 2. pio_odsr is read-only or read/write depending on pio_owsr i/o lines. 3. reset value of pio_pdsr depends on the level of the i/o line s. reading the i/o line levels requires the clock of the pio controller to be enabled, ot herwise pio_pdsr reads the levels present on the i/o line at the time the clock was disabled. 4. pio_isr is reset at 0x0. however, the first read of the register may read a different value as input changes may have occurred. note: if an offset is not listed in the table it must be considered as reserved. 0x0104- 0x010c reserved ? ? ? 0x0110 reserved ? ? ? 0x0114- 0x011c reserved ? ? ? table 26-2. register mapping (continued) offset register name access reset
401 11011a?atarm?04-oct-10 sam3n 401 11011a?atarm?04-oct-10 sam3n 26.7.1 pio enable register name: pio_per addresses: 0x400e0e00 (pioa), 0x400e1000 (piob), 0x400e1200 (pioc) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: pio enable 0 = no effect. 1 = enables the pio to control the corresponding pin (disables peripheral control of the pin). 26.7.2 pio disable register name: pio_pdr addresses: 0x400e0e04 (pioa), 0x400e1004 (piob), 0x400e1204 (pioc) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: pio disable 0 = no effect. 1 = disables the pio from controllin g the corresponding pin (enables peripheral contro l of the pin). 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
402 11011a?atarm?04-oct-10 sam3n 402 11011a?atarm?04-oct-10 sam3n 26.7.3 pio status register name: pio_psr addresses: 0x400e0e08 (pioa), 0x400e1008 (piob), 0x400e1208 (pioc) access: read-only ? p0-p31: pio status 0 = pio is inactive on the corresponding i/o line (peripheral is active). 1 = pio is active on the corresponding i/o line (peripheral is inactive). 26.7.4 pio output enable register name: pio_oer addresses: 0x400e0e10 (pioa), 0x400e1010 (piob), 0x400e1210 (pioc) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: output enable 0 = no effect. 1 = enables the output on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
403 11011a?atarm?04-oct-10 sam3n 403 11011a?atarm?04-oct-10 sam3n 26.7.5 pio output disable register name: pio_odr addresses: 0x400e0e14 (pioa), 0x400e1014 (piob), 0x400e1214 (pioc) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: output disable 0 = no effect. 1 = disables the output on the i/o line. 26.7.6 pio output status register name: pio_osr addresses: 0x400e0e18 (pioa), 0x400e1018 (piob), 0x400e1218 (pioc) access: read-only ? p0-p31: output status 0 = the i/o line is a pure input. 1 = the i/o line is enabled in output. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
404 11011a?atarm?04-oct-10 sam3n 404 11011a?atarm?04-oct-10 sam3n 26.7.7 pio input filter enable register name: pio_ifer addresses: 0x400e0e20 (pioa), 0x400e1020 (piob), 0x400e1220 (pioc) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: input filter enable 0 = no effect. 1 = enables the input glitch filter on the i/o line. 26.7.8 pio input filter disable register name: pio_ifdr addresses: 0x400e0e24 (pioa), 0x400e1024 (piob), 0x400e1224 (pioc) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: input filter disable 0 = no effect. 1 = disables the input glitch filter on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
405 11011a?atarm?04-oct-10 sam3n 405 11011a?atarm?04-oct-10 sam3n 26.7.9 pio input filter status register name: pio_ifsr addresses: 0x400e0e28 (pioa), 0x400e1028 (piob), 0x400e1228 (pioc) access: read-only ? p0-p31: input filer status 0 = the input glitch filter is disabled on the i/o line. 1 = the input glitch filter is enabled on the i/o line. 26.7.10 pio set output data register name: pio_sodr addresses: 0x400e0e30 (pioa), 0x400e1030 (piob), 0x400e1230 (pioc) access: write-only ? p0-p31: set output data 0 = no effect. 1 = sets the data to be driven on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
406 11011a?atarm?04-oct-10 sam3n 406 11011a?atarm?04-oct-10 sam3n 26.7.11 pio clear output data register name: pio_codr addresses: 0x400e0e34 (pioa), 0x400e1034 (piob), 0x400e1234 (pioc) access: write-only ? p0-p31: clear output data 0 = no effect. 1 = clears the data to be driven on the i/o line. 26.7.12 pio output data status register name: pio_odsr addresses: 0x400e0e38 (pioa), 0x400e1038 (piob), 0x400e1238 (pioc) access: read-only or read-write ? p0-p31: output data status 0 = the data to be driven on the i/o line is 0. 1 = the data to be driven on the i/o line is 1. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
407 11011a?atarm?04-oct-10 sam3n 407 11011a?atarm?04-oct-10 sam3n 26.7.13 pio pin data status register name: pio_pdsr addresses: 0x400e0e3c (pioa), 0x400e103c (piob), 0x400e123c (pioc) access: read-only ? p0-p31: output data status 0 = the i/o line is at level 0. 1 = the i/o line is at level 1. 26.7.14 pio interrupt enable register name: pio_ier addresses: 0x400e0e40 (pioa), 0x400e1040 (piob), 0x400e1240 (pioc) access: write-only ? p0-p31: input change interrupt enable 0 = no effect. 1 = enables the input change interrupt on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
408 11011a?atarm?04-oct-10 sam3n 408 11011a?atarm?04-oct-10 sam3n 26.7.15 pio interrupt disable register name: pio_idr addresses: 0x400e0e44 (pioa), 0x400e1044 (piob), 0x400e1244 (pioc) access: write-only ? p0-p31: input change interrupt disable 0 = no effect. 1 = disables the input change interrupt on the i/o line. 26.7.16 pio interrupt mask register name: pio_imr addresses: 0x400e0e48 (pioa), 0x400e1048 (piob), 0x400e1248 (pioc) access: read-only ? p0-p31: input change interrupt mask 0 = input change interrupt is disabled on the i/o line. 1 = input change interrupt is enabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
409 11011a?atarm?04-oct-10 sam3n 409 11011a?atarm?04-oct-10 sam3n 26.7.17 pio interrupt status register name: pio_isr addresses: 0x400e0e4c (pioa), 0x400e104c (piob), 0x400e124c (pioc) access: read-only ? p0-p31: input change interrupt status 0 = no input change has been detected on the i/o line since pio_isr was last read or since reset. 1 = at least one input change has been detected on the i/o line since pio_isr was last read or since reset. 26.7.18 pio multi-driver enable register name: pio_mder addresses: 0x400e0e50 (pioa), 0x400e1050 (piob), 0x400e1250 (pioc) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: multi drive enable. 0 = no effect. 1 = enables multi drive on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
410 11011a?atarm?04-oct-10 sam3n 410 11011a?atarm?04-oct-10 sam3n 26.7.19 pio multi-driver disable register name: pio_mddr addresses: 0x400e0e54 (pioa), 0x400e1054 (piob), 0x400e1254 (pioc) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: multi drive disable. 0 = no effect. 1 = disables multi drive on the i/o line. 26.7.20 pio multi-driver status register name: pio_mdsr addresses: 0x400e0e58 (pioa), 0x400e1058 (piob), 0x400e1258 (pioc) access: read-only ? p0-p31: multi drive status. 0 = the multi drive is disabled on the i/o line. the pin is driven at high and low level. 1 = the multi drive is enabled on the i/o lin e. the pin is driven at low level only. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
411 11011a?atarm?04-oct-10 sam3n 411 11011a?atarm?04-oct-10 sam3n 26.7.21 pio pull up disable register name: pio_pudr addresses: 0x400e0e60 (pioa), 0x400e1060 (piob), 0x400e1260 (pioc) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: pull up disable. 0 = no effect. 1 = disables the pull up resistor on the i/o line. 26.7.22 pio pull up enable register name: pio_puer addresses: 0x400e0e64 (pioa), 0x400e1064 (piob), 0x400e1264 (pioc) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: pull up enable. 0 = no effect. 1 = enables the pull up resistor on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
412 11011a?atarm?04-oct-10 sam3n 412 11011a?atarm?04-oct-10 sam3n 26.7.23 pio pull up status register name: pio_pusr addresses: 0x400e0e68 (pioa), 0x400e1068 (piob), 0x400e1268 (pioc) access: read-only ? p0-p31: pull up status. 0 = pull up resistor is enabled on the i/o line. 1 = pull up resistor is disabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
413 11011a?atarm?04-oct-10 sam3n 413 11011a?atarm?04-oct-10 sam3n 26.7.24 pio peripheral a bcd select register 1 name: pio_abcdsr1 access: read-write this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: peripheral select. if the same bit is set to 0 in pio_abcdsr2: 0 = assigns the i/o line to the peripheral a function. 1 = assigns the i/o line to the peripheral b function. if the same bit is set to 1 in pio_abcdsr2: 0 = assigns the i/o line to the peripheral c function. 1 = assigns the i/o line to the peripheral d function. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
414 11011a?atarm?04-oct-10 sam3n 414 11011a?atarm?04-oct-10 sam3n 26.7.25 pio peripheral a bcd select register 2 name: pio_abcdsr2 access: read-write this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: peripheral select. if the same bit is set to 0 in pio_abcdsr1: 0 = assigns the i/o line to the peripheral a function. 1 = assigns the i/o line to the peripheral c function. if the same bit is set to 1 in pio_abcdsr1: 0 = assigns the i/o line to the peripheral b function. 1 = assigns the i/o line to the peripheral d function. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
415 11011a?atarm?04-oct-10 sam3n 415 11011a?atarm?04-oct-10 sam3n 26.7.26 pio input filter slow clock disable register name: pio_ifscdr addresses: 0x400e0e80 (pioa), 0x400e1080 (piob), 0x400e1280 (pioc) access: write-only ? p0-p31: pio clock glitch filtering select. 0 = no effect. 1 = the glitch filter is able to filter glitches with a duration < tmck/2. 26.7.27 pio input filter slow clock enable register name: pio_ifscer addresses: 0x400e0e84 (pioa), 0x400e1084 (piob), 0x400e1284 (pioc) access: write-only ? p0-p31: debouncing filtering select. 0 = no effect. 1 = the debouncing filter is able to filter pulses with a duration < tdiv_slclk/2. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
416 11011a?atarm?04-oct-10 sam3n 416 11011a?atarm?04-oct-10 sam3n 26.7.28 pio input filter slow clock status register name: pio_ifscsr addresses: 0x400e0e88 (pioa), 0x400e1088 (piob), 0x400e1288 (pioc) access: read-only ? p0-p31: glitch or debouncing filter selection status 0 = the glitch filter is able to f ilter glitches with a duration < tmck2. 1 = the debouncing filter is able to filter pulses with a duration < tdiv_slclk/2. 26.7.29 pio slow clock divider debouncing register name: pio_scdr addresses: 0x400e0e8c (pioa), 0x400e108c (piob), 0x400e128c (pioc) access: read-write ? divx: slow clock divider selection for debouncing tdiv_slclk = 2*(div+1)*tslow_clock. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - div13 div12 div11 div10 div9 div8 76543210 div7 div6 div5 div4 div3 div2 div1 div0
417 11011a?atarm?04-oct-10 sam3n 417 11011a?atarm?04-oct-10 sam3n 26.7.30 pio pad pull down disable register name: pio_ppddr addresses: 0x400e0e90 (pioa), 0x400e1090 (piob), 0x400e1290 (pioc) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: pull down disable. 0 = no effect. 1 = disables the pull down resistor on the i/o line. 26.7.31 pio pad pull down enable register name: pio_ppder addresses: 0x400e0e94 (pioa), 0x400e1094 (piob), 0x400e1294 (pioc) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: pull down enable. 0 = no effect. 1 = enables the pull down resistor on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
418 11011a?atarm?04-oct-10 sam3n 418 11011a?atarm?04-oct-10 sam3n 26.7.32 pio pad pull down status register name: pio_ppdsr addresses: 0x400e0e98 (pioa), 0x400e1098 (piob), 0x400e1298 (pioc) access: read-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: pull down status. 0 = pull down resistor is enabled on the i/o line. 1 = pull down resistor is disabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
419 11011a?atarm?04-oct-10 sam3n 419 11011a?atarm?04-oct-10 sam3n 26.7.33 pio output write enable register name: pio_ower addresses: 0x400e0ea0 (pioa), 0x400e10a0 (piob), 0x400e12a0 (pioc) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: output write enable. 0 = no effect. 1 = enables writing pio_odsr for the i/o line. 26.7.34 pio output write disable register name: pio_owdr addresses: 0x400e0ea4 (pioa), 0x400e10a4 (piob), 0x400e12a4 (pioc) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: output write disable. 0 = no effect. 1 = disables writing pio_odsr for the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
420 11011a?atarm?04-oct-10 sam3n 420 11011a?atarm?04-oct-10 sam3n 26.7.35 pio output write status register name: pio_owsr addresses: 0x400e0ea8 (pioa), 0x400e10a8 (piob), 0x400e12a8 (pioc) access: read-only ? p0-p31: output write status. 0 = writing pio_odsr does not affect the i/o line. 1 = writing pio_odsr affects the i/o line. 26.7.36 pio additional interrupt modes enable register name: pio_aimer addresses: 0x400e0eb0 (pioa), 0x400e10b0 (piob), 0x400e12b0 (pioc) access: write-only ? p0-p31: additional interrupt modes enable. 0 = no effect. 1 = the interrupt source is the event described in pio_elsr and pio_frlhsr. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
421 11011a?atarm?04-oct-10 sam3n 421 11011a?atarm?04-oct-10 sam3n 26.7.37 pio additional interrupt modes disable register name: pio_aimdr addresses: 0x400e0eb4 (pioa), 0x400e10b4 (piob), 0x400e12b4 (pioc) access: write-only ? p0-p31: additional interrupt modes disable. 0 = no effect. 1 = the interrupt mode is set to the default interrupt mode (both edge detection). 26.7.38 pio additional interrupt modes mask register name: pio_aimmr addresses: 0x400e0eb8 (pioa), 0x400e10b8 (piob), 0x400e12b8 (pioc) access: read-only ? p0-p31: peripheral cd status. 0 = the interrupt source is a both edge detection event 1 = the interrupt source is described by the registers pio_elsr and pio_frlhsr 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
422 11011a?atarm?04-oct-10 sam3n 422 11011a?atarm?04-oct-10 sam3n 26.7.39 pio edge select register name: pio_esr addresses: 0x400e0ec0 (pioa), 0x400e10c0 (piob), 0x400e12c0 (pioc) access: write-only ? p0-p31: edge in terrupt selection. 0 = no effect. 1 = the interrupt source is an edge detection event. 26.7.40 pio level select register name: pio_lsr addresses: 0x400e0ec4 (pioa), 0x400e10c4 (piob), 0x400e12c4 (pioc) access: write-only ? p0-p31: level interrupt selection. 0 = no effect. 1 = the interrupt source is a level detection event. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
423 11011a?atarm?04-oct-10 sam3n 423 11011a?atarm?04-oct-10 sam3n 26.7.41 pio edge/level status register name: pio_elsr addresses: 0x400e0ec8 (pioa), 0x400e10c8 (piob), 0x400e12c8 (pioc) access: read-only ? p0-p31: edge/level interrupt source selection. 0 = the interrupt source is an edge detection event. 1 = the interrupt source is a level detection event. 26.7.42 pio falling edge/low level select register name: pio_fellsr addresses: 0x400e0ed0 (pioa), 0x400e10d0 (piob), 0x400e12d0 (pioc) access: write-only ? p0-p31: falling edge/low level interrupt selection. 0 = no effect. 1 = the interrupt source is set to a falling edge detection or low level de tection event, depen ding on pio_elsr. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
424 11011a?atarm?04-oct-10 sam3n 424 11011a?atarm?04-oct-10 sam3n 26.7.43 pio rising edge/high level select register name: pio_rehlsr addresses: 0x400e0ed4 (pioa), 0x400e10d4 (piob), 0x400e12d4 (pioc) access: write-only ? p0-p31: rising edge /high level interrupt selection. 0 = no effect. 1 = the interrupt source is set to a rising edge detection or high level detection event, depending on pio_elsr. 26.7.44 pio fall/rise - low/high status register name: pio_frlhsr addresses: 0x400e0ed8 (pioa), 0x400e10d8 (piob), 0x400e12d8 (pioc) access: read-only ? p0-p31: edge /level interrupt source selection. 0 = the interrupt source is a falling edge detection (if pio_el sr = 0) or low level detect ion event (if pio_elsr = 1). 1 = the interrupt source is a rising edge detection (if pio_elsr = 0) or high level detection event (if pio_elsr = 1). 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
425 11011a?atarm?04-oct-10 sam3n 425 11011a?atarm?04-oct-10 sam3n 26.7.45 pio lock status register name: pio_locksr addresses: 0x400e0ee0 (pioa), 0x400e10e0 (piob), 0x400e12e0 (pioc) access: read-only ? p0-p31: lock status. 0 = the i/o line is not locked. 1 = the i/o line is locked. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
426 11011a?atarm?04-oct-10 sam3n 426 11011a?atarm?04-oct-10 sam3n 26.7.46 pio write protect mode register name: pio_wpmr addresses: 0x400e0ee4 (pioa), 0x400e10e4 (piob), 0x400e12e4 (pioc) access: read-write reset: see table 26-2 for more information on write protection registers, refer to section 26.7 ?parallel input/ output controller (pio) user interface? . ? wpen: write protect enable 0 = disables the write protect if wpkey co rresponds to 0x50494f (?pio? in ascii). 1 = enables the write protect if wpkey corresponds to 0x50494f (?pio? in ascii). protects the registers: ?pio enable register? on page 401 ?pio disable register? on page 401 ?pio output enable register? on page 402 ?pio output disable register? on page 403 ?pio input filter enable register? on page 404 ?pio input filter disable register? on page 404 ?pio multi-driver enable register? on page 409 ?pio multi-driver disable register? on page 410 ?pio pull up disable register? on page 411 ?pio pull up enable register? on page 411 ?pio peripheral abcd select register 1? on page 413 ?pio peripheral abcd select register 2? on page 414 ?pio output write enable register? on page 419 ?pio output write disable register? on page 419 ?pio pad pull down disable register? on page 417 ?pio pad pull down status register? on page 418 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 ???????wpen
427 11011a?atarm?04-oct-10 sam3n 427 11011a?atarm?04-oct-10 sam3n ? wpkey: write protect key should be written at value 0x50494f (?pio? in ascii). writing any other value in this field aborts the write operation of the wpen bit. always reads as 0. 26.7.47 pio write protect status register name: pio_wpsr addresses: 0x400e0ee8 (pioa), 0x400e10e8 (piob), 0x400e12e8 (pioc) access: read-only reset: see table 26-2 ? wpvs: write protect violation status 0 = no write protect violation has occurred since the last read of the pio_wpsr register. 1 = a write protect violation has occurred since the last read of the pio_wpsr register. if this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. note: reading pio_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 ???????wpvs
428 11011a?atarm?04-oct-10 sam3n 428 11011a?atarm?04-oct-10 sam3n 26.7.48 pio schmitt trigger register name: pio_schmitt addresses: 0x400e0f00 (pioa), 0x400e1100 (piob), 0x400e1300 (pioc) access: read-write reset: see figure 26-2 ? schmittx [x=0..31]: 0 = schmitt trigger is enabled. 1= schmitt trigger is disabled. 31 30 29 28 27 26 25 24 schmitt31 schmitt30 schmitt29 schmitt28 schmitt27 schmitt26 schmitt25 schmitt24 23 22 21 20 19 18 17 16 schmitt23 schmitt22 schmitt21 schmitt20 schmitt19 schmitt18 schmitt17 schmitt16 15 14 13 12 11 10 9 8 schmitt15 schmitt14 schmitt13 schmitt12 schmitt11 schmitt10 schmitt9 schmitt8 76543210 schmitt7 schmitt6 schmitt5 schmitt4 schmitt3 schmitt2 schmitt1 schmitt0
429 11011a?atarm?04-oct-10 sam3n 429 11011a?atarm?04-oct-10 sam3n 27. serial peripheral interface (spi) 27.1 description the serial peripheral interface (spi) circuit is a synchronous serial data link that provides com- munication with external devices in master or slave mode. it also enables communication between processors if an external processor is connected to the system. the serial peripheral interface is essentially a shift register that serially transmits data bits to other spis. during a data transfer, one spi syste m acts as the ?master?' which controls the data flow, while the other devices act as ?slaves'' whic h have data shifted into and out by the master. different cpus can take turn being masters (multiple master protocol opposite to single master protocol where one cpu is always the master while all of the others are always slaves) and one master may simultaneously shift da ta into multiple slaves. howeve r, only one slave may drive its output to write data back to the master at any given time. a slave device is selected when the master asse rts its nss signal. if multiple slave devices exist, the master generates a separate slav e select signal for each slave (npcs). the spi system consists of two data lines and two control lines: ? master out slave in (mosi): this data line supplies the output data from the master shifted into the input(s) of the slave(s). ? master in slave out (miso): this data line supplies the output data from a slave to the input of the master. there may be no more than one slave transmitting data during any particular transfer. ? serial clock (spck): this control line is driven by the master and regulates the flow of the data bits. the master may transmit data at a variety of baud rates; the spck line cycles once for each bit that is transmitted. ? slave select (nss): this control line allows slaves to be turned on and off by hardware. 27.2 embedded characteristics ? compatible with an embedded 32-bit microcontroller ? supports communication with serial external devices ? four chip selects with external decoder support allow communication with up to 15 peripherals ? serial memories, such as dataflash and 3-wire eeproms ? serial peripherals, such as adcs, da cs, lcd controllers, can controllers and sensors ? external co-processors ? master or slave serial peripheral bus interface ? 8- to 16-bit programmable da ta length per chip select ? programmable phase and polarity per chip select ? programmable transfer delays between consecutive transfers and between clock and data per chip select ? programmable delay between consecutive transfers ? selectable mode fault detection ? connection to pdc channel capab ilities optimizes data transfers ? one channel for the receiver, one channel for the transmitter ? next buffer support
430 11011a?atarm?04-oct-10 sam3n 430 11011a?atarm?04-oct-10 sam3n 27.3 block diagram figure 27-1. block diagram 27.4 application block diagram figure 27-2. application block diagram: single master/multiple slave implementation s pi interf a ce interr u pt control pio pdc pmc mck s pi interr u pt s pck mi s o mo s i npc s 0/n ss npc s 1 npc s 2 npc s3 apb spi master spck miso mosi npcs0 npcs1 npcs2 spck miso mosi nss slave 0 spck miso mosi nss slave 1 spck miso mosi nss slave 2 nc npcs3
431 11011a?atarm?04-oct-10 sam3n 431 11011a?atarm?04-oct-10 sam3n 27.5 signal description 27.6 product dependencies 27.6.1 i/o lines the pins used for interfacing the compliant ex ternal devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the spi pins to their peripheral functions. 27.6.2 power management the spi may be clocked through the power management controller (pmc), thus the program- mer must first configure the pmc to enable the spi clock. table 27-1. signal description pin name pin description type master slave miso master in slave out input output mosi master out slave in output input spck serial clock output input npcs1-npcs3 peripheral chip selects output unused npcs0/nss peripheral chip select/slave select output input table 27-2. i/o lines instance signal i/o line peripheral spi miso pa12 a spi mosi pa13 a spi npcs0 pa11 a spi npcs1 pa9 b spi npcs1 pa31 a spi npcs1 pb14 a spi npcs1 pc4 b spi npcs2 pa10 b spi npcs2 pa30 b spi npcs2 pb2 b spi npcs2 pc7 b spi npcs3 pa3 b spi npcs3 pa5 b spi npcs3 pa22 b spi spck pa14 a
432 11011a?atarm?04-oct-10 sam3n 432 11011a?atarm?04-oct-10 sam3n 27.6.3 interrupt the spi interface has an interrupt line connected to the nested vector interrupt controller (nvic).handling the spi interrupt requires programming the nvic before configuring the spi. 27.7 functional description 27.7.1 modes of operation the spi operates in master mode or in slave mode. operation in master mode is programmed by writing at 1 the mstr bit in the mode register. the pins npcs0 to npcs3 are all configured as outputs, the spck pin is driven, the miso line is wired on the receiver input and the mosi line driven as an output by the transmitter. if the mstr bit is written at 0, the spi operates in slave mode. the miso line is driven by the transmitter output, the mosi line is wired on the re ceiver input, the spck pin is driven by the transmitter to synchronize the receiver. the npcs0 pin becomes an input, and is used as a slave select signal (nss). the pins npcs1 to npcs3 are not driven and can be used for other purposes. the data transfers are identically programmable for both modes of operations. the baud rate generator is activated only in master mode. 27.7.2 data transfer four combinations of polarity and phase are available for data transfers. the clock polarity is programmed with the cpol bit in the chip select register. the clock phase is programmed with the ncpha bit. these two parameters determine th e edges of the clock signal on which data is driven and sampled. each of the two parameters has two possible states, resulting in four possi- ble combinations that are incompatible with one another. thus, a master/slave pair must use the same parameter pair values to communicate. if multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a dif- ferent slave. table 27-4 shows the four modes and corresponding parameter settings. figure 27-3 and figure 27-4 show examples of data transfers. table 27-3. peripheral ids instance id spi 21 table 27-4. spi bus protocol mode spi mode cpol ncpha shift spck edge capt ure spck edge spck inactive level 0 0 1 falling rising low 1 0 0 rising falling low 2 1 1 rising falling high 3 1 0 falling rising high
433 11011a?atarm?04-oct-10 sam3n 433 11011a?atarm?04-oct-10 sam3n figure 27-3. spi transfer format (ncpha = 1, 8 bits per transfer) figure 27-4. spi transfer format (ncpha = 0, 8 bits per transfer) 6 * spck (cpol = 0) spck (cpol = 1) mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) msb msb lsb lsb 6 6 5 5 4 4 3 3 2 2 1 1 * not defined, but normally msb of previous character received. 1 2345 78 6 * spck (cpol = 0) spck (cpol = 1) 1 2345 7 mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) 8 msb msb lsb lsb 6 6 5 5 4 4 3 3 1 1 * not defined but normally lsb of previous character transmitted. 2 2 6
434 11011a?atarm?04-oct-10 sam3n 434 11011a?atarm?04-oct-10 sam3n 27.7.3 master mode operations when configured in master mode, the spi operates on the clock generated by the internal pro- grammable baud rate generator. it fully controls the data transfers to and from the slave(s) connected to the spi bus. the spi drives the chip select line to the slave and the serial clock signal (spck). the spi features two holding registers, the transmit data register and the receive data regis- ter, and a single shift register. the holding registers maintain the data flow at a constant rate. after enabling the spi, a data transfer begins when the processor writes to the spi_tdr (trans- mit data register). the written data is immediat ely transferred in the shift register and transfer on the spi bus starts. while the data in the shift register is shifted on the mosi line, the miso line is sampled and shifted in the shift register. receiving data cannot occur without transmit- ting data. if receiving mode is not needed, for example when communicating with a slave receiver only (such as an lcd), the receive status flags in the status register can be discarded. before writing the tdr, the pcs field in the spi_mr register must be set in order to select a slave. after enabling the spi, a data transfer begins when the processor writes to the spi_tdr (trans- mit data register). the written data is immediat ely transferred in the shift register and transfer on the spi bus starts. while the data in the shift register is shifted on the mosi line, the miso line is sampled and shifted in the shift register. transmission cannot occur without reception. before writing the tdr, the pcs field must be set in order to select a slave. if new data is written in spi_tdr during the transfer, it stays in it until the current transfer is completed. then, the received data is transferred from the shift register to spi_rdr, the data in spi_tdr is loaded in the shift register and a new transfer starts. the transfer of a data written in spi_tdr in t he shift register is indicated by the tdre bit (transmit data register empty) in the status register (spi_sr). when new data is written in spi_tdr, this bit is cleared. the tdre bit is used to trigger the transmit pdc channel. the end of transfer is indicated by the txempty flag in the spi_sr register. if a transfer delay (dlybct) is greater than 0 for the last transfer, txempty is set after the completion of said delay. the master clock (mck) can be switched off at this time. the transfer of received data from the shift register in spi_rdr is indicated by the rdrf bit (receive data register full) in the status register (spi_sr). when the received data is read, the rdrf bit is cleared. if the spi_rdr (receive data register) has not been read before new data is received, the overrun error bit (ovres) in spi_sr is set. as long as this flag is set, data is loaded in spi_rdr. the user has to read the status register to clear the ovres bit. figure 27-5 , shows a block diagram of the spi when operating in master mode. figure 27-6 on page 436 shows a flow chart describing how transfers are handled.
435 11011a?atarm?04-oct-10 sam3n 435 11011a?atarm?04-oct-10 sam3n 27.7.3.1 master mode block diagram figure 27-5. master mode block diagram shift register spck mosi lsb msb miso spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0..3 cpol ncpha bits mck baud rate generator spi_csr0..3 scbr npcs3 npcs0 npcs2 npcs1 npcs0 0 1 ps spi_mr pcs spi_tdr pcs modf current peripheral spi_rdr pcs spi_csr0..3 csaat pcsdec modfdis mstr
436 11011a?atarm?04-oct-10 sam3n 436 11011a?atarm?04-oct-10 sam3n 27.7.3.2 master mode flow diagram figure 27-6. master mode flow diagram spi enable csaat ? ps ? 1 0 0 1 1 npcs = spi_tdr(pcs) npcs = spi_mr(pcs) delay dlybs serializer = spi_tdr(td) tdre = 1 data transfer spi_rdr(rd) = serializer rdrf = 1 tdre ? npcs = 0xf delay dlybcs fixed peripheral variable peripheral delay dlybct 0 1 csaat ? 0 tdre ? 1 0 ps ? 0 1 spi_tdr(pcs) = npcs ? no yes spi_mr(pcs) = npcs ? no npcs = 0xf delay dlybcs npcs = spi_tdr(pcs) npcs = 0xf delay dlybcs npcs = spi_mr(pcs), spi_tdr(pcs) fixed peripheral variable peripheral - npcs defines the current chip select - csaat, dlybs, dlybct refer to the fields of the chip select register corresponding to the current chip select - when npcs is 0xf, csaat is 0.
437 11011a?atarm?04-oct-10 sam3n 437 11011a?atarm?04-oct-10 sam3n figure 27-7 shows transmit data register empty (t dre), receive data register (rdrf) and transmission register empty (txempty) status flags behavior within the spi_sr (status reg- ister) during an 8-bit data transfer in fixed mode and no peripheral data controller involved. figure 27-7. status register flags behavior figure 27-8 shows transmission register empty (txempty), end of rx buffer (endrx), end of tx buffer (endtx), rx buffer full (rxbuff) and tx buffer empty (txbufe) status flags behavior within the spi_sr (status register) during an 8-bit data transfer in fixed mode with the peripheral data controller involved. the pdc is programmed to transfer and receive three data. the next pointer and counter are not used. the rdrf and tdre are not shown because these flags are managed by the pdc when using the pdc. 6 spck mosi (from master) miso (from slave) npcs0 msb msb lsb lsb 6 6 5 5 4 4 3 3 2 2 1 1 1 2345 78 6 rdrf tdre txempty write in spi_tdr rdr read shift register empty
438 11011a?atarm?04-oct-10 sam3n 438 11011a?atarm?04-oct-10 sam3n figure 27-8. pdc status register flags behavior 27.7.3.3 clock generation the spi baud rate clock is generated by dividing the master clock (mck), by a value between 1 and 255. this allows a maximum operating baud rate at up to master clock and a minimum operating baud rate of mck divided by 255. programming the scbr field at 0 is forbidden. tr iggering a transfer while scbr is at 0 can lead to unpredictable results. at reset, scbr is 0 and the user has to program it at a valid value before performing the first transfer. the divisor can be defined independently for each chip select, as it has to be programmed in the scbr field of the chip select registers. this allows the spi to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 27.7.3.4 transfer delays figure 27-9 shows a chip select transfer change and consecutive transfers on the same chip select. three delays can be programmed to modify the transfer waveforms: ? the delay between chip selects, programmable only once for all the ch ip selects by writing the dlybcs field in the mode register. allows insertion of a delay between release of one chip select and before assertion of a new one. ? the delay before spck, independently programmable for each chip select by writing the field dlybs. allows the start of spck to be delayed after the chip select has been asserted. ? the delay between consecutive transfers, independently programmable for each chip select by writing the dlybct field. allows insertion of a delay between two transfers occurring on the same chip select these delays allow the spi to be adapted to the interfaced peripherals and their speed and bus release time. msb lsb 654321 spck mosi (from master) npcs0 msb lsb 654321 12 3 endtx txempty msb lsb 654321 msb lsb 654321 miso (from slave) msb lsb 654321 msb lsb 654321 endrx txbufe rxbuff
439 11011a?atarm?04-oct-10 sam3n 439 11011a?atarm?04-oct-10 sam3n figure 27-9. programmable delays 27.7.3.5 peripheral selection the serial peripherals are selected through the assertion of the npcs0 to npcs3 signals. by default, all the npcs signals are high before and after each transfer. ? fixed peripheral select: spi exchanges data with only one peripheral fixed peripheral select is activated by writing the ps bit to zero in spi_mr (mode register). in this case, the current peripheral is defined by the pcs field in spi_mr and the pcs field in the spi_tdr has no effect. ? variable peripheral select: data can be exchanged with more than one peripheral without having to reprogram the npcs field in the spi_mr register. variable peripheral select is activated by se tting ps bit to one. the pcs field in spi_tdr is used to select the current peripheral. this means that the peripheral selection can be defined for each new data. the value to write in the spi_tdr register as the following format. [xxxxxxx(7-bit) + lastxfer(1-bit) () + xxxx(4-bit) + pcs (4-bit) + da ta (8 to 16-bit)] with pcs equals to the chip select to assert as defined in section 27.8.4 (spi transmit data register) and lastxfer bit at 0 or 1 depending on csaat bit. note: 1. optional. csaat, lastxfer and csnaat bits are discussed in section 27.7.3.9 ?p eripheral deselec- tion with pdc? . if lastxfer is used, the command must be issued before writing the last character. instead of lastxfer, the user can use the spidis command. after the end of the pdc transfer, wait for the txempty flag, then write spidis into the spi _cr register (this will no t change the configu- ration register values); the np cs will be deactivated after the last character transfer. then, another pdc transfer can be started if the spien was previously written in the spi_cr register. 27.7.3.6 spi peripheral dma controller (pdc) in both fixed and variable mode the peripheral dma controller (pdc) can be used to reduce processor overhead. the fixed peripheral selection allows buffer transfers with a single peripheral. using the pdc is an optimal means, as the size of the data transfer between the memory and the spi is either 8 bits or 16 bits. however, changing the peripheral selection requires the mode register to be reprogrammed. dlybcs dlybs dlybct dlybct chip select 1 chip select 2 spck
440 11011a?atarm?04-oct-10 sam3n 440 11011a?atarm?04-oct-10 sam3n the variable peripheral selection allows buffer transfers with multiple peripherals without repro- gramming the mode register. data written in spi_tdr is 32 bits wide and defines the real data to be transmitted and the peripheral it is desti ned to. using the pdc in this mode requires 32-bit wide buffers, with the data in the lsbs and the pcs and lastxfer fields in the msbs, how- ever the spi still controls the number of bits (8 to16) to be transferre d through miso and mosi lines with the chip select configuration registers. this is not the optimal means in term of mem- ory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. transfer size depending on the data size to transmit, from 8 to 16 bits, the pdc manages automatically the type of pointer's size it has to point to. th e pdc will perform the followin g transfer size depend- ing on the mode and number of bits per data. fixed mode: ?8-bit data: byte transfer, pdc pointer address = address + 1 byte, pdc counter = counter - 1 ? 8-bit to 16-bit data: 2 bytes transfer. n-bit data transfer with don?t care data (msb) filled with 0?s, pdc pointer address = address + 2 bytes, pdc counter = counter - 1 variable mode: in variable mode, pdc pointer address = address +4 bytes and pdc counter = counter - 1 for 8 to 16-bit transfer size. when using the pdc, the tdre and rdrf flags are handled by the pdc, thus the user?s application does not have to check those bits. only end of rx buffer (endrx), end of tx buffer (endtx), buffer fu ll (rxbuff), tx buffer empty (txbufe) are significant. for further details about the periph eral dma controller and user interface, refer to the pdc section of the product datasheet. 27.7.3.7 peripheral chip select decoding the user can program the spi to operate with up to 15 peripherals by decoding the four chip select lines, npcs0 to npcs3 with 1 of up to 16 decoder/demultiplexer. this can be enabled by writing the pcsdec bit at 1 in the mode register (spi_mr). when operating without decoding, the spi makes sure that in any case only one chip select line is activated, i.e., one npcs line driven low at a time. if two bits are defined low in a pcs field, only the lowest numbered ch ip select is driven low. when operating with decoding, the spi directly outputs the value defined by the pcs field on npcs lines of either the mode register or the transmit data register (depending on ps). as the spi sets a default value of 0xf on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. the spi has only four chip select registers, not 15. as a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. as an example, spi_crs0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the pcs values 0x0 to 0x3. thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. figure 27-10 below shows such an implementation.
441 11011a?atarm?04-oct-10 sam3n 441 11011a?atarm?04-oct-10 sam3n if the csaat bit is used, with or without the pdc, the mode fault detection for npcs0 line must be disabled. this is not needed for all other chip select lines since mode fault detection is only on npcs0. figure 27-10. chip select decoding applicati on block diagram: single master/multiple slave implementation 27.7.3.8 peripheral deselection without pdc during a transfer of more than one data on a chip select without the pdc, the spi_tdr is loaded by the processor, the flag tdre rises as soon as the content of the spi_tdr is trans- ferred into the internal shift register. when this flag is detected high, the spi_tdr can be reloaded. if this reload by the processor occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the chip select is not de-asserted between the two transfers. but depending on the application software handling the spi status register flags (by interrupt or polli ng method) or servicing other interrupts or other tasks, the processor may not reload the spi_tdr in time to keep the chip select active (low). a null delay between consecutive transfer (dlybc t) value in the spi_csr register, will give even less time for the processor to reload t he spi_tdr. with some spi slave peripherals, requiring the chip select line to remain active (low) during a full set of transfers might lead to communication errors. to facilitate interfacing with such devices, the chip select register [csr0...csr3] can be pro- grammed with the csaat bit (chip select active af ter transfer) at 1. this allows the chip select lines to remain in their current state (low = active) until transfer to another chip select is required. even if the spi_tdr is not reloa ded the chip select will remain active. to have the chip select line to raise at the end of the transfer the last transfer bit (lastxfer) in the spi_mr register must be set at 1 before writing the last data to transmit into the spi_tdr. spi master spck miso mosi npcs0 npcs1 npcs2 spck 1-of-n decoder/demultiplexer miso mosi nss slave 0 spck miso mosi nss slave 1 spck miso mosi nss slave 14 npcs3
442 11011a?atarm?04-oct-10 sam3n 442 11011a?atarm?04-oct-10 sam3n 27.7.3.9 peripheral deselection with pdc when the peripheral dma controller is used, the chip select line will remain low during the whole transfer since the tdre flag is managed by the pdc itself. the reloading of the spi_tdr by the pdc is done as soon as tdre flag is set to one. in this case t he use of csaat bit might not be needed. however, it may happen that when other pdc channels connected to other peripherals are in use as well, the spi pdc might be delayed by another (pdc with a higher pri- ority on the bus). having pdc buffers in slower memories like flash memory or sdram compared to fast internal sram, may lengthen t he reload time of the spi_tdr by the pdc as well. this means that the spi_t dr might not be reloaded in time to keep the chip select line low. in this case the chip select line may toggle between data transfer and according to some spi slave devices, the communi cation might get lost. the use of the csaat bit might be needed. when the csaat bit is set at 0, the npcs doe s not rise in all cases between two transfers on the same peripheral. during a transfer on a chip select, the flag tdre rises as soon as the con- tent of the spi_tdr is transferred into the internal shifter. when this flag is detected the spi_tdr can be reloaded. if this reload occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the chip select is not de-asserted between the two transfers. this migh t lead to difficulties fo r interfacing with some serial peripherals requiring the chip select to be de-asserted after each transfer. to facilitate interfacing with such de vices, the chip select register ca n be programmed with the csnaat bit (chip select not active after tr ansfer) at 1. this allows to de-assert systematically the chip select lines during a time dlybcs. (the value of the csnaat bit is taken into account only if the csaat bit is set at 0 for the same chip select). figure 27-11 shows different peripheral deselection cases and the effect of the csaat and csnaat bits.
443 11011a?atarm?04-oct-10 sam3n 443 11011a?atarm?04-oct-10 sam3n figure 27-11. peripheral deselection a npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs dlybct pcs=a a dlybcs dlybct a pcs = a a a dlybct aa csaat = 0 and csnaat = 0 dlybct aa csaat = 1 and csnaat= 0 / 1 a dlybcs pcs = a dlybct aa csaat = 0 and csnaat = 1 npcs[0..3] write spi_tdr tdre pcs = a dlybct aa csaat = 0 and csnaat = 0
444 11011a?atarm?04-oct-10 sam3n 444 11011a?atarm?04-oct-10 sam3n 27.7.3.10 mode fault detection a mode fault is detected when the spi is programmed in master mode and a low level is driven by an external master on the npcs0/nss signal. in this case, multi-master configuration, npcs0, mosi, miso and spck pins must be configured in open drain (through the pio control- ler). when a mode fault is detected, the modf bit in the spi_sr is set until the spi_sr is read and the spi is automatically disabled until re-enabled by writing the spien bit in the spi_cr (control register) at 1. by default, the mode fault detection circuitr y is enabled. the user can disable mode fault detection by setting the modfdis bit in the spi mode register (spi_mr). 27.7.4 spi slave mode when operating in slave mode, the spi processes data bits on the clock provided on the spi clock pin (spck). the spi waits for nss to go active before receiving the serial clock from an external master. when nss falls, the clock is validated on the serializer, which processes the number of bits defined by the bits field of the chip select register 0 (spi_csr0). these bits are processed following a phase and a polarity defined respectively by the ncpha and cpol bits of the spi_csr0. note that bits, cpol and ncpha of the other chip select registers have no effect when the spi is programmed in slave mode. the bits are shifted out on the miso line and sampled on the mosi line. (for more information on bits field, see also, the (note:) below the register table; section 27.8.9 ?spi chip select register? on page 458 .) when all the bits are processed, the received data is transferred in the receive data register and the rdrf bit rises. if the spi_rdr (receive data register) has no t been read be fore new data is received, the overrun error bit (ovres) in spi_sr is set. as long as this flag is set, data is loaded in spi_rdr. the user has to read the status register to clear the ovres bit. when a transfer starts, the data shifted out is the data present in the shift register. if no data has been written in the transmit data register (spi_tdr), the la st data received is transferred. if no data has been received since the last reset, all bits are transmitted low, as the shift regis- ter resets at 0. when a first data is written in sp i_tdr, it is transferred immediat ely in the shift register and the tdre bit rises. if new data is wr itten, it remains in spi_tdr unt il a transfer occurs, i.e. nss falls and there is a valid clock on the spck pin. w hen the transfer occurs, the last data written in spi_tdr is transferred in the shift register and the tdre bit rises. this enables frequent updates of critical variables with single transfers. then, a new data is loaded in the shift register from the transmit data register. in case no character is ready to be transmitted, i.e. no character has been written in spi_tdr since the last load from spi_tdr to the shift register, the shift register is not modified and the last received character is retransmitted. in this case the u nderrun error status flag (undes) is set in the spi_sr. figure 27-12 shows a block diagram of the spi when operating in slave mode.
445 11011a?atarm?04-oct-10 sam3n 445 11011a?atarm?04-oct-10 sam3n figure 27-12. slave mode functional bloc diagram shift register spck spiens lsb msb nss mosi spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0 cpol ncpha bits spien spidis miso
446 11011a?atarm?04-oct-10 sam3n 446 11011a?atarm?04-oct-10 sam3n 27.7.5 write protected registers to prevent any single software error that may corrupt spi behavior, the registers listed below can be write-protected by setting the spiwpen bit in the spi write protection mode register (spi_wpmr). if a write access in a write-pr otected register is detected, then the spiwpvs flag in the spi write protection status register (spi_wpsr) is set and the field spiwpvsrc indicates in which register the write access has been attempted. the spiwpvs flag is automatically reset after reading the spi wr ite protection status register (spi_wpsr). list of the write-protected registers: section 27.8.2 ?spi mode register? section 27.8.9 ?spi ch ip select register?
447 11011a?atarm?04-oct-10 sam3n 447 11011a?atarm?04-oct-10 sam3n 27.8 serial peripheral inte rface (spi) user interface table 27-5. register mapping offset register name access reset 0x00 control register spi_cr write-only --- 0x04 mode register spi_mr read-write 0x0 0x08 receive data register spi_rdr read-only 0x0 0x0c transmit data register spi_tdr write-only --- 0x10 status register spi_sr read-only 0x000000f0 0x14 interrupt enable register spi_ier write-only --- 0x18 interrupt disable register spi_idr write-only --- 0x1c interrupt mask register spi_imr read-only 0x0 0x20 - 0x2c reserved 0x30 chip select register 0 spi_csr0 read-write 0x0 0x34 chip select register 1 spi_csr1 read-write 0x0 0x38 chip select register 2 spi_csr2 read-write 0x0 0x3c chip select register 3 spi_csr3 read-write 0x0 0x4c - 0xe0 reserved ? ? ? 0xe4 write protection control register spi_wpmr read-write 0x0 0xe8 write protection status register spi_wpsr read-only 0x0 0x00e8 - 0x00f8 reserved ? ? ? 0x00fc reserved ? ? ? 0x100 - 0x124 reserved for the pdc ? ? ?
448 11011a?atarm?04-oct-10 sam3n 448 11011a?atarm?04-oct-10 sam3n 27.8.1 spi control register name: spi_cr address: 0x40008000 access: write-only ? spien: spi enable 0 = no effect. 1 = enables the spi to transfer and receive data. ? spidis: spi disable 0 = no effect. 1 = disables the spi. as soon as spidis is set, spi finishes its transfer. all pins are set in input mode and no data is received or transmitted. if a transfer is in progress, the transfer is finished before the spi is disabled. if both spien and spidis are equal to one when the control register is written, the spi is disabled. ? swrst: spi software reset 0 = no effect. 1 = reset the spi. a software-triggered hardware reset of the spi interface is performed. the spi is in slave mode after software reset. pdc channels are not affected by software reset. ? lastxfer: last transfer 0 = no effect. 1 = the current npcs will be deasserted afte r the character written in td has been transferred. when csaat is set, this allows to close the communication with the current serial peri pheral by raising the correspo nding npcs line as soon as td transfer has completed. refer to section 27.7.3.5 ?per ipheral selection? for more details. 31 30 29 28 27 26 25 24 ???????lastxfer 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst?????spidisspien
449 11011a?atarm?04-oct-10 sam3n 449 11011a?atarm?04-oct-10 sam3n 27.8.2 spi mode register name: spi_mr address: 0x40008004 access: read-write ? mstr: master/slave mode 0 = spi is in slave mode. 1 = spi is in master mode. ? ps: peripheral select 0 = fixed peripheral select. 1 = variable peripheral select. ? pcsdec: chip select decode 0 = the chip selects are directly connected to a peripheral device. 1 = the four chip select lines are connected to a 4- to 16-bit decoder. when pcsdec equals one, up to 15 chip select signals can be generated with the four lines using an external 4- to 16-bit decoder. the chip select registers define the characteristics of the 15 chip selects according to the following rules: spi_csr0 defines peripheral chip select signals 0 to 3. spi_csr1 defines peripheral chip select signals 4 to 7. spi_csr2 defines peripheral chip select signals 8 to 11. spi_csr3 defines peripheral chip select signals 12 to 14. ? modfdis: mode fault detection 0 = mode fault detection is enabled. 1 = mode fault detection is disabled. ? wdrbt: wait data read before transfer 0 = no effect. in master mode, a transfer can be initiated whatever the state of the receive data register is. 1 = in master mode, a transfer can start only if the receive data register is empty, i.e. does not contain any unread data. this mode prevents overrun error in reception. 31 30 29 28 27 26 25 24 dlybcs 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 ???????? 76543210 llb ? wdrbt modfdis ? pcsdec ps mstr
450 11011a?atarm?04-oct-10 sam3n 450 11011a?atarm?04-oct-10 sam3n ? llb: local loopback enable 0 = local loopback path disabled. 1 = local loopback path enabled llb controls the local loopback on the data serializer for te sting in master mode only. (miso is internally connected on mosi.) ? pcs: peripheral chip select this field is only used if fixed peripheral select is active (ps = 0). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs. ? dlybcs: delay between chip selects this field defines the delay from npcs inactive to the ac tivation of another npcs. the dlybcs time guarantees non-over- lapping chip selects and solves bus contentions in case of peripherals having long data float times. if dlybcs is less than or eq ual to six, six mck periods will be inserted by default. otherwise, the following equat ion determines the delay: delay between chip selects dlybcs mck ---------------------- - =
451 11011a?atarm?04-oct-10 sam3n 451 11011a?atarm?04-oct-10 sam3n 27.8.3 spi receive data register name: spi_rdr address: 0x40008008 access: read-only ? rd: receive data data received by the spi interface is stored in this register right-justified. unused bits read zero. ? pcs: peripheral chip select in master mode only, these bits indicate the value on the npcs pins at the end of a transfer. otherwise, these bits read zero. note: when using variable peripheral select mode (ps = 1 in spi_m r) it is mandatory to also set the wdrbt field to 1 if the spi_rdr pcs field is to be processed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 rd 76543210 rd
452 11011a?atarm?04-oct-10 sam3n 452 11011a?atarm?04-oct-10 sam3n 27.8.4 spi transmit data register name: spi_tdr address: 0x4000800c access: write-only ? td: transmit data data to be transmitted by the spi interface is stored in this register. information to be transmitted must be written to the transmit data register in a right-justified format. ? pcs: peripheral chip select this field is only used if variable peripheral select is active (ps = 1). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs ? lastxfer: last transfer 0 = no effect. 1 = the current npcs will be deasserted afte r the character written in td has been transferred. when csaat is set, this allows to close the communication with the current serial peri pheral by raising the correspo nding npcs line as soon as td transfer has completed. this field is only used if variable peripheral select is active (ps = 1). 31 30 29 28 27 26 25 24 ???????lastxfer 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 td 76543210 td
453 11011a?atarm?04-oct-10 sam3n 453 11011a?atarm?04-oct-10 sam3n 27.8.5 spi status register name: spi_sr address: 0x40008010 access: read-only ? rdrf: receive data register full 0 = no data has been received since the last read of spi_rdr 1 = data has been received and the received data has been transferred from the serializer to spi_rdr since the last read of spi_rdr. ? tdre: transmit data register empty 0 = data has been written to spi_tdr and not yet transferred to the serializer. 1 = the last data written in the transmit data register has been transferred to the serializer. tdre equals zero when the spi is disabled or at reset. the spi enable command sets this bit to one. ? modf: mode fault error 0 = no mode fault has been detected since the last read of spi_sr. 1 = a mode fault occurred since the last read of the spi_sr. ? ovres: overrun error status 0 = no overrun has been detected since the last read of spi_sr. 1 = an overrun has occurred since the last read of spi_sr. an overrun occurs when spi_r dr is loaded at least twice from the serializer since the last read of the spi_rdr. ? endrx: end of rx buffer 0 = the receive counter register has not reached 0 since the last write in spi_rcr (1) or spi_rncr (1) . 1 = the receive counter register has reached 0 since the last write in spi_rcr (1) or spi_rncr (1) . ? endtx: end of tx buffer 0 = the transmit counter register has not reached 0 since the last write in spi_tcr (1) or spi_tncr (1) . 1 = the transmit counter register has reached 0 since the last write in spi_tcr (1) or spi_tncr (1) . ? rxbuff: rx buffer full 0 = spi_rcr (1) or spi_rncr (1) has a value other than 0. 1 = both spi_rcr (1) and spi_rncr (1) have a value of 0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????spiens 15 14 13 12 11 10 9 8 ????? undes txempty nssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
454 11011a?atarm?04-oct-10 sam3n 454 11011a?atarm?04-oct-10 sam3n ? txbufe: tx buffer empty 0 = spi_tcr (1) or spi_tncr (1) has a value other than 0. 1 = both spi_tcr (1) and spi_tncr (1) have a value of 0. ? nssr: nss rising 0 = no rising edge detected on nss pin since last read. 1 = a rising edge occurred on nss pin since last read. ? txempty: transmission registers empty 0 = as soon as data is written in spi_tdr. 1 = spi_tdr and internal shifter are empty. if a transfer delay has been defined, txempty is set after the completion of such delay. ? undes: underrun error status (slave mode only) 0 = no underrun has been detected since the last read of spi_sr. 1 = a transfer begins whereas no data has been loaded in the transmit data register. ? spiens: spi enable status 0 = spi is disabled. 1 = spi is enabled. note: 1. spi_rcr, spi_rncr, spi_tcr, spi_tncr are physica lly located in the pdc.
455 11011a?atarm?04-oct-10 sam3n 455 11011a?atarm?04-oct-10 sam3n 27.8.6 spi interrupt enable register name: spi_ier address: 0x40008014 access: write-only 0 = no effect. 1 = enables the corresponding interrupt. ? rdrf: receive data register full interrupt enable ? tdre: spi transmit data regi ster empty interrupt enable ? modf: mode fault error interrupt enable ? ovres: overrun error interrupt enable ? endrx: end of receive buffer interrupt enable ? endtx: end of transmit buffer interrupt enable ? rxbuff: receive buffer full interrupt enable ? txbufe: transmit buffer empty interrupt enable ? nssr: nss rising interrupt enable ? txempty: transmission registers empty enable ? undes: underrun error interrupt enable 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? undes txempty nssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
456 11011a?atarm?04-oct-10 sam3n 456 11011a?atarm?04-oct-10 sam3n 27.8.7 spi interrupt disable register name: spi_idr address: 0x40008018 access: write-only 0 = no effect. 1 = disables the corresponding interrupt. ? rdrf: receive data register full interrupt disable ? tdre: spi transmit data register empty interrupt disable ? modf: mode fault error interrupt disable ? ovres: overrun error interrupt disable ? endrx: end of receive buffer interrupt disable ? endtx: end of transmit buffer interrupt disable ? rxbuff: receive buffer full interrupt disable ? txbufe: transmit buffer empty interrupt disable ? nssr: nss rising interrupt disable ? txempty: transmission registers empty disable ? undes: underrun error interrupt disable 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? undes txempty nssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
457 11011a?atarm?04-oct-10 sam3n 457 11011a?atarm?04-oct-10 sam3n 27.8.8 spi interrupt mask register name: spi_imr address: 0x4000801c access: read-only 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled. ? rdrf: receive data register full interrupt mask ? tdre: spi transmit data register empty interrupt mask ? modf: mode fault error interrupt mask ? ovres: overrun error interrupt mask ? endrx: end of receive buffer interrupt mask ? endtx: end of transmit buffer interrupt mask ? rxbuff: receive buffer full interrupt mask ? txbufe: transmit buffer empty interrupt mask ? nssr: nss rising interrupt mask ? txempty: transmission registers empty mask ? undes: underrun error interrupt mask 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? undes txempty nssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
458 11011a?atarm?04-oct-10 sam3n 458 11011a?atarm?04-oct-10 sam3n 27.8.9 spi chip select register name: spi_csrx[x=0..3] address: 0x40008030 access: read/write note: spi_csrx registers must be written even if the user wants to use the defaults. the bits field will not be updated with the trans- lated value unless the register is written. ? cpol: clock polarity 0 = the inactive state value of spck is logic level zero. 1 = the inactive state value of spck is logic level one. cpol is used to determine the inactive state value of the serial clock (spck). it is used with ncpha to produce the required clock/data relationship between master and slave devices. ? ncpha: clock phase 0 = data is changed on the leading edge of spck and captured on the following edge of spck. 1 = data is captured on the leading edge of spck and changed on the following edge of spck. ncpha determines which edge of spck causes data to change and which edge causes data to be captured. ncpha is used with cpol to produce the required clock/da ta relationship between master and slave devices. ? csnaat: chip select not active af ter transfer (ignored if csaat = 1) 0 = the peripheral chip select does not rise between two tran sfers if the spi_tdr is reloaded before the end of the first transfer and if the two transfers occur on the same chip select. 1 = the peripheral chip select rises systematically between each transfer performed on the same slave for a minimal dura- tion of: ? (if dlybct field is different from 0) ? (if dlybct field equal 0) ? csaat: chip select active after transfer 0 = the peripheral chip select line rises as soon as the last transfer is achieved. 1 = the peripheral chip select does not rise after the last transfer is achieved. it remains active until a new transfer is requested on a different chip select. 31 30 29 28 27 26 25 24 dlybct 23 22 21 20 19 18 17 16 dlybs 15 14 13 12 11 10 9 8 scbr 76543210 bits csaat csnaat ncpha cpol dlybcs mck ---------------------- - dlybcs 1 + mck -------------------------------- -
459 11011a?atarm?04-oct-10 sam3n 459 11011a?atarm?04-oct-10 sam3n ? bits: bits per transfer (see the (note:) below the register table; section 27.8.9 ?spi chip select register? on page 458 .) the bits field determines the number of data bits transferred. reserved values should not be used. ? scbr: serial clock baud rate in master mode, the spi interface uses a modulus counter to derive the spck baud rate from the master clock mck. the baud rate is selected by writing a value from 1 to 255 in the scbr field. the following equations determine the spck baud rate: programming the scbr field at 0 is forbidden. triggering a trans fer while scbr is at 0 can le ad to unpredictable results. at reset, scbr is 0 and the user has to program it at a valid value before performing the first transfer. note: if one of the scbr fields inspi_csrx is set to 1, the other scbr fields in spi_csrx must be set to 1 as well, if they are required to process transfers. if they are not used to transfer data, they can be set at any value. ? dlybs: delay before spck this field defines the delay from npcs valid to the first valid spck transition. when dlybs equals zero, the npcs valid to spck transition is 1/2 the spck clock period. otherwise, the following equations determine the delay: value name description 0 8_bit 8_bits for transfer 1 9_bit 9_bits for transfer 2 10_bit 8_bits for transfer 3 11_bit 8_bits for transfer 4 12_bit 8_bits for transfer 5 13_bit 8_bits for transfer 6 14_bit 8_bits for transfer 7 15_bit 8_bits for transfer 8 16_bit 8_bits for transfer 10 ? reserved 11 ? reserved 12 ? reserved 13 ? reserved 14 ? reserved 15 ? reserved 16 ? reserved spck baudrate mck scbr -------------- - = delay before spck dlybs mck ------------------ - =
460 11011a?atarm?04-oct-10 sam3n 460 11011a?atarm?04-oct-10 sam3n ? dlybct: delay between consecutive transfers this field defines the delay between two consecutive transfers with the same perip heral without removing the chip select. the delay is always inserted after each transfer and before removing the chip select if needed. when dlybct equals zero, no delay between consecutive transf ers is inserted and the clock keeps its duty cycle over the character transfers. otherwise, the following equat ion determines the delay: delay between consecutive transfers 32 dlybct mck ------------------------------------- =
461 11011a?atarm?04-oct-10 sam3n 461 11011a?atarm?04-oct-10 sam3n 27.8.10 spi write protection mode register name: spi_wpmr address: 0x400080e4 access: read-write ? spiwpen: spi write protection enable 0: the write protection is disabled 1: the write protection is enabled ? spiwpkey: spi write protection key password if a value is written in spiwpen, the value is taken into ac count only if spiwpkey is wri tten with ?spi? (spi written in ascii code, ie 0x535049 in hexadecimal). 31 30 29 28 27 26 25 24 spiwpkey 23 22 21 20 19 18 17 16 spiwpkey 15 14 13 12 11 10 9 8 spiwpkey 76543210 -------spiwpen
462 11011a?atarm?04-oct-10 sam3n 462 11011a?atarm?04-oct-10 sam3n 27.8.11 spi write protection status register name: spi_wpsr address: 0x400080e8 access: read-only ? spiwpvs: spi write prot ection violation status ? spiwpvsrc: spi write prot ection violation source this field indicates the apb offset of the register concerned by the violation (spi _mr or spi_csrx) 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 spiwpvsrc 76543210 ????? spiwpvs spiwpvs value violation type 0x1 the write protection has blocked a write access to a protected register (since the last read). 0x2 software reset has been performed while write protection was enabled (since the last read or since the last write access on spi_m r, spi_ier, spi_i dr or spi_csrx). 0x3 both write protection violation and software re set with write protection enabled have occurred since the last read. 0x4 write accesses have been detected on spi_mr (while a chip select was active) or on spi_csri (while the chip select ?i? was active) since the last read. 0x5 the write protection has blocked a write access to a protected register and write accesses have been detected on spi_mr (while a chip select was active) or on spi_csri (while the chip select ?i? was active) since the last read. 0x6 software reset has been performed while write protection was enabled (since the last read or since the last write access on spi_mr, spi_i er, spi_idr or spi_csrx) and some write accesses have been detected on spi_mr (while a ch ip select was active) or on spi_csri (while the chip select ?i? was active) since the last read. 0x7 - the write protection has blocked a write access to a protected register. and - software reset has been performed while write protection was enabled. and - write accesses have been detected on spi_mr (while a chip select was active) or on spi_csri (while the chip select ?i? was active) since the last read.
463 11011a?atarm?04-oct-10 sam3n 463 11011a?atarm?04-oct-10 sam3n 28. two-wire interface (twi) 28.1 description the atmel two-wire interface (twi) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbits per second, based on a byte-oriented transfer format. it can be used with any atmel two-wire interface bus serial eeprom and i2c compatible device such as real time clock (rtc), dot matrix/graphic lcd controllers and temperature sensor, to name but a few. the twi is programmable as a master or a slave with sequential or single-byte acce ss. multiple master capability is supported. 20 arbitration of the bus is performed internally and puts the twi in slave mode automatically if the bus arbitration is lost. a configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. below, table 28-1 lists the compatibility level of the atme l two-wire interface in master mode and a full i2c compatible device. note: 1. start + b000000001 + ack + sr table 28-1. atmel twi compatibilit y with i2c standard i2c standard atmel twi standard mode speed (100 khz) supported fast mode speed (400 khz) supported 7 or 10 bits slave addressing supported start byte (1) not supported repeated start (sr) condition supported ack and nack management supported slope control and input filtering (fast mode) not supported clock stretching supported multi master capability supported
464 11011a?atarm?04-oct-10 sam3n 464 11011a?atarm?04-oct-10 sam3n 28.2 embedded characteristics ?two twis ? compatible with atmel two-wire interface serial memory and i2c compatible devices (note:) ? one, two or three bytes for slave address ? sequential read-write operations ? master, multi-master and slave mode operation ? bit rate: up to 400 kbits ? general call supported in slave mode ? smbus quick command supported in master mode ? connection to peripheral dma controller (p dc) channel capabilit ies optimizes data transfers in master mode only ? one channel for the receiver, one channel for the transmitter ? next buffer support ? connection to dma controller (d mac) channel capabilities optimizes data transfers in master mode only note: see table 28-1 for details on compat ibility with i2c standard. 28.3 list of abbreviations table 28-2. abbreviations abbreviation description twi two-wire interface a acknowledge na non acknowledge pstop sstart sr repeated start sadr slave address adr any address except sadr r read wwrite
465 11011a?atarm?04-oct-10 sam3n 465 11011a?atarm?04-oct-10 sam3n 28.4 block diagram figure 28-1. block diagram 28.5 application block diagram figure 28-2. application block diagram 28.5.1 i/o lines description apb bridge pmc mck two-wire interface pio nvic twi interrupt twck twd host with twi interface twd twck atmel twi serial eeprom i2c rtc i2c lcd controller slave 1 slave 2 slave 3 vdd i2c temp. sensor slave 4 rp: pull up value as given by the i2c standard rp rp table 28-3. i/o lines description pin name pin description type twd two-wire serial data input/output twck two-wire serial clock input/output
466 11011a?atarm?04-oct-10 sam3n 466 11011a?atarm?04-oct-10 sam3n 28.6 product dependencies 28.6.1 i/o lines both twd and twck are bidirectional lines, connect ed to a positive supply voltage via a current source or pull-up resistor (see figure 28-2 on page 465 ). when the bus is free, both lines are high. the output stages of devices connected to the bus must have an open-drain or open-col- lector to perform the wired-and function. twd and twck pins may be multiplexed with pi o lines. to enable the twi, the programmer must perform the following step: ? program the pio controller to dedicate twd and twck as peripheral lines. the user must not program twd and twck as open-drain. it is already done by the hardware. 28.6.2 power management ? enable the peripheral clock. the twi interface may be clocked through the power management controller (pmc), thus the programmer must first configure the pmc to enable the twi clock. 28.6.3 interrupt the twi interface has an interrupt line connected to the nested vector interrupt controller (nvic). in order to handle interrupts, the nvic must be programmed before configuring the twi. table 28-4. i/o lines instance signal i/o line peripheral twi0 twck0 pa4 a twi0 twd0 pa3 a twi1 twck1 pb5 a twi1 twd1 pb4 a table 28-5. peripheral ids instance id twi0 19 twi1 20
467 11011a?atarm?04-oct-10 sam3n 467 11011a?atarm?04-oct-10 sam3n 28.7 functional description 28.7.1 transfer format the data put on the twd line must be 8 bits long. data is transferred msb first; each byte must be followed by an acknowledgement. the number of bytes per transfer is unlimited (see figure 28-4 ). each transfer begins with a start condition and terminates with a stop condition (see figure 28-3 ). ? a high-to-low transition on the twd line while twck is high defines the start condition. ? a low-to-high transition on the twd line while twck is high defines a stop condition. figure 28-3. start and stop conditions figure 28-4. transfer format 28.7.2 modes of operation the twi has six modes of operations: ? master transmitter mode ? master receiver mode ? multi-master transmitter mode ? multi-master receiver mode ? slave transmitter mode ? slave receiver mode these modes are described in the following chapters. twd twck start stop twd twck start address r/w ack data ack data ack stop
468 11011a?atarm?04-oct-10 sam3n 468 11011a?atarm?04-oct-10 sam3n 28.8 master mode 28.8.1 definition the master is the device that starts a transfer, generates a clock and stops it. 28.8.2 application block diagram figure 28-5. master mode typical application block diagram 28.8.3 programming master mode the following registers have to be programmed before entering master mode: 1. dadr (+ iadrsz + iadr if a 10 bit device is addressed): the device address is used to access slave devices in read or write mode. 2. ckdiv + chdiv + cldiv: clock waveform. 3. svdis: disable the slave mode. 4. msen: enable the master mode. 28.8.4 master transmitter mode after the master initiates a start condition when writing into the tran smit holding register, twi_thr, it sends a 7-bit slave address, configured in the master mode register (dadr in twi_mmr), to notify the slave device. the bit following the slave address indicates the transfer direction, 0 in this case (mread = 0 in twi_mmr). the twi transfers require the slave to acknowledge each received byte. during the acknowl- edge clock pulse (9th pulse), the master releases the data line (high), enabling the slave to pull it down in order to generate the acknowledge. t he master polls the data line during this clock pulse and sets the not acknowledge bit ( nack) in the status register if the slave does not acknowledge the byte. as with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (twi_ier). if the slave acknowledges the byte, the data written in the twi_thr, is then shifted in the internal shifter and transferred. when an acknowledge is detected, the txrdy bit is set until a new write in the twi_thr. while no new data is writ ten in the twi_thr, the serial clock line is tied low. when new data is written in the twi_thr, the scl is released and the data is sent. to generate a stop event, the stop command must be performed by writing in the stop field of twi_cr. host with twi interface twd twck atmel twi serial eeprom i2c rtc i2c lcd controller slave 1 slave 2 slave 3 vdd i2c temp. sensor slave 4 rp: pull up value as given by the i2c standard rp rp
469 11011a?atarm?04-oct-10 sam3n 469 11011a?atarm?04-oct-10 sam3n after a master write transfer, the serial clock line is stretched (tied low) while no new data is written in the twi_thr or until a stop command is performed. see figure 28-6 , figure 28-7 , and figure 28-8 . figure 28-6. master write with one data byte figure 28-7. master write with mu ltiple data bytes txcomp txrdy write thr (data) stop command sent (write in twi_cr) twd a data a s dadr w p a data n a s dadr w data n+1 a p data n+2 a txcomp txrdy write thr (data n) write thr (data n+1) write thr (data n+2) last data sent stop command performed (by writing in the twi_cr) twd twck
470 11011a?atarm?04-oct-10 sam3n 470 11011a?atarm?04-oct-10 sam3n figure 28-8. master write with one byte internal address and multiple data bytes txrdy is used as transmit read y for the pdc transmit channel. 28.8.5 master receiver mode the read sequence begins by setting the start bit. after the start condition has been sent, the master sends a 7-bit slave address to notify th e slave device. the bit following the slave address indicates the transfer direction, 1 in this ca se (mread = 1 in twi_mmr). during the acknowl- edge clock pulse (9th pulse), the master releases the data line (high), enabling the slave to pull it down in order to generate the acknowledge. t he master polls the data line during this clock pulse and sets the nack bit in the status register if the slave does not acknowledge the byte. if an acknowledge is received, the master is then ready to receive data from the slave. after data has been received, the master sends an acknowle dge condition to notify the slave that the data has been received except for the last data, after the stop condition. see figure 28-9 . when the rxrdy bit is set in the status register, a character has been received in the receive-holding reg- ister (twi_rhr). the rxrdy bit is reset when reading the twi_rhr. when a single data byte read is performed, with or without internal address (iadr ), the start and stop bits must be set at the same time. see figure 28-9 . when a multiple data byte read is performed, with or without internal address (iadr ), the stop bit must be set after the next-to- last data received. see figure 28-10 . for internal address usage see section 28.8.6 . figure 28-9. master read with one data byte a data n a s dadr w data n+1 a p data n+2 a txcomp txrdy write thr (data n) write thr (data n+1) write thr (data n+2) last data sent stop command performed (by writing in the twi_cr) twd iadr a twck a s dadr r data n p txcomp write start & stop bit rxrdy read rhr twd
471 11011a?atarm?04-oct-10 sam3n 471 11011a?atarm?04-oct-10 sam3n figure 28-10. master read with mu ltiple data bytes rxrdy is used as receive ready for the pdc receive channel. 28.8.6 internal address the twi interface can perform various transfe r formats: transfers with 7-bit slave address devices and 10-bit slave address devices. 28.8.6.1 7-bit slave addressing when addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page loca- tion in a serial memory, for example. when performing read operations with an internal address, the twi performs a write operation to set the internal address into the slave device, and then switch to master receiver mode. note that the second start condition (after sending the iadr) is sometimes called ?repeated start? (sr) in i2c fully-compatible devices. see figure 28-12 . see figure 28-11 and figure 28-13 for master write operation with internal address. the three internal address bytes are configurable through the master mode register (twi_mmr). if the slave device supports only a 7-bit address, i.e. no internal address, iadrsz must be set to 0. in the figures below the following abbreviations are used: n a s dadr r data n a a data (n+1) a data (n+m) data (n+m)-1 p twd txcomp write start bit rxrdy write stop bit after next-to-last data read read rhr data n read rhr data (n+1) read rhr data (n+m)-1 read rhr data (n+m) ?s start ?sr repeated start ?p stop ?w write ?r read ?a acknowledge ?n not acknowledge ?dadr device address ?iadr internal address
472 11011a?atarm?04-oct-10 sam3n 472 11011a?atarm?04-oct-10 sam3n figure 28-11. master write with one, two or three bytes internal address and one data byte figure 28-12. master read with one, two or three bytes internal address and one data byte 28.8.6.2 10-bit slave addressing for a slave address higher than 7 bits, the user must configure the address size (iadrsz ) and set the other slave address bits in the internal address register (twi_iadr). the two remaining internal address bytes, iadr[15:8] and iadr[23:16] can be used the same as in 7-bit slave addressing. example: address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. program iadrsz = 1, 2. program dadr with 1 1 1 1 0 b1 b2 (b1 is the msb of the 10-bit address, b2, etc.) 3. program twi_iadr with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the lsb of the 10-bit address) figure 28-13 below shows a byte write to an atmel at24lc512 eeprom. this demonstrates the use of internal addresses to access the device. figure 28-13. internal address usage s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a data a p s dadr w a iadr(15:8) a iadr(7:0) a p data a a iadr(7:0) a p data a s dadr w twd three bytes internal address two bytes internal address one byte internal address twd twd s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a s dadr w a iadr(15:8) a iadr(7:0) a a iadr(7:0) a s dadr w data n p sr dadr r a sr dadr r a data n p sr dadr ra data np twd twd twd three bytes internal address two bytes internal address one byte internal address s t a r t m s b device address 0 l s b r / w a c k m s b w r i t e a c k a c k l s b a c k first word address second word address data s t o p
473 11011a?atarm?04-oct-10 sam3n 473 11011a?atarm?04-oct-10 sam3n 28.8.7 using the peripheral dma controller (pdc) the use of the pdc significantly reduces the cpu load. to assure correct implementation, respect the following programming sequences: 28.8.7.1 data transmit with the pdc 1. initialize the transmit pdc (me mory pointers, size, etc.). 2. configure the master mode (dadr, ckdiv, etc.). 3. start the transfer by setting the pdc txten bit. 4. wait for the pdc end tx flag. 5. disable the pdc by setting the pdc txdis bit. 28.8.7.2 data receive with the pdc 1. initialize the receive pdc (memory pointers, size - 1, etc.). 2. configure the master mode (dadr, ckdiv, etc.). 3. start the transfer by setting the pdc rxten bit. 4. wait for the pdc end rx flag. 5. disable the pdc by setting the pdc rxdis bit. 28.8.8 using the dma controller (dmac) the use of the dmac significantlly reduces the cpu load. to assure correct implementation, respect the following programming sequence. 1. initialize the dmac (channels, memory pointers , size, etc.); 1. configure the master mode (dadr, ckdiv, etc.). 1. enable the dmac. 1. wait for the dmac flag. 1. disable the dmac. 28.8.9 smbus quick command (master mode only) the twi interface can perform a quick command: 1. configure the master mode (dadr, ckdiv, etc.). 2. write the mread bit in the twi_mmr register at the value of the one-bit command to be sent. 3. start the transfer by setting the quick bit in the twi_cr. figure 28-14. smbus quick command txcomp txrdy write quick command in twi_cr twd a s dadr r/w p
474 11011a?atarm?04-oct-10 sam3n 474 11011a?atarm?04-oct-10 sam3n 28.8.10 read-write flowcharts the following flowcharts shown in figure 28-16 on page 475 , figure 28-17 on page 476 , figure 28-18 on page 477 , figure 28-19 on page 478 and figure 28-20 on page 479 give examples for read and write operations. a polling or interrupt method can be used to check the status bits. the interrupt method requires that the interrupt enable register (twi_ier) be configured first. figure 28-15. twi write operation with single data byte without internal address set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address (dadr) - transfer direction bit write ==> bit mread = 0 load transmit register twi_thr = data to send read status register txrdy = 1? read status register txcomp = 1? transfer finished ye s ye s begin no no write stop command twi_cr = stop
475 11011a?atarm?04-oct-10 sam3n 475 11011a?atarm?04-oct-10 sam3n figure 28-16. twi write operation with single data byte and internal address begin set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address (dadr) - internal address size (iadrsz) - transfer direction bit write ==> bit mread = 0 load transmit register twi_thr = data to send read status register txrdy = 1? read status register txcomp = 1? transfer finished set the internal address twi_iadr = address yes yes no no write stop command twi_cr = stop
476 11011a?atarm?04-oct-10 sam3n 476 11011a?atarm?04-oct-10 sam3n figure 28-17. twi write operation with multiple data bytes with or without internal address set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - internal address size (if iadr used) - transfer direction bit write ==> bit mread = 0 internal address size = 0? load transmit register twi_thr = data to send read status register txrdy = 1? data to send? read status register txcomp = 1? end begin set the internal address twi_iadr = address ye s twi_thr = data to send ye s ye s ye s no no no write stop command twi_cr = stop set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once)
477 11011a?atarm?04-oct-10 sam3n 477 11011a?atarm?04-oct-10 sam3n figure 28-18. twi read operation with single data byte without internal address set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - transfer direction bit read ==> bit mread = 1 start the transfer twi_cr = start | stop read status register rxrdy = 1? read status register txcomp = 1? end begin ye s ye s set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) read receive holding register no no
478 11011a?atarm?04-oct-10 sam3n 478 11011a?atarm?04-oct-10 sam3n figure 28-19. twi read operation with single data byte and internal address set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - internal address size (iadrsz) - transfer direction bit read ==> bit mread = 1 read status register txcomp = 1? end begin ye s set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) ye s set the internal address twi_iadr = address start the transfer twi_cr = start | stop read status register rxrdy = 1? read receive holding register no no
479 11011a?atarm?04-oct-10 sam3n 479 11011a?atarm?04-oct-10 sam3n figure 28-20. twi read operation with multiple data bytes with or without internal address internal address size = 0? start the transfer twi_cr = start stop the transfer twi_cr = stop read status register rxrdy = 1? last data to read but one? read status register txcomp = 1? end set the internal address twi_iadr = address ye s ye s ye s no ye s read receive holding register (twi_rhr) no set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - internal address size (if iadr used) - transfer direction bit read ==> bit mread = 1 begin set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) no read status register rxrdy = 1? ye s read receive holding register (twi_rhr) no
480 11011a?atarm?04-oct-10 sam3n 480 11011a?atarm?04-oct-10 sam3n 28.9 multi-master mode 28.9.1 definition more than one master may handle the bus at the same time without data corruption by using arbitration. arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. as soon as arbitration is lost by a master, it st ops sending data and listens to the bus in order to detect a stop. when the stop is detected, the master who has lost arbitration may put its data on the bus by respecting arbitration. arbitration is illustrated in figure 28-22 on page 481 . 28.9.2 different multi-master modes two multi-master modes may be distinguished: 1. twi is considered as a master only and will never be addressed. 2. twi may be either a master or a slave and may be addressed. note: in both multi-master modes arbitration is supported. 28.9.2.1 twi as master only in this mode, twi is considered as a master only (msen is always at one) and must be driven like a master with the arblst (arbitration lost) flag in addition. if arbitration is lost (arblst = 1), the programmer must reinitiate the data transfer. if the user starts a transfer (ex.: dadr + start + w + write in thr) and if the bus is busy, the twi automatically waits for a stop conditi on on the bus to initiate the transfer (see figure 28- 21 on page 481 ). note: the state of the bus (busy or free) is not indicated in the user interface. 28.9.2.2 twi as master or slave the automatic reversal from master to slave is not supported in case of a lost arbitration. then, in the case where twi may be either a master or a slave, the programmer must manage the pseudo multi-master mode described in the steps below. 1. program twi in slave mode (sadr + ms dis + sven) and perform slave access (if twi is addressed). 2. if twi has to be set in master mode, wait until txcomp flag is at 1. 3. program master mode (dadr + svdis + msen ) and start the transfer (ex: start + write in thr). 4. as soon as the master mode is enabled, twi scans the bus in order to detect if it is busy or free. when the bus is considered as free, twi initiates the transfer. 5. as soon as the transfer is initiated and until a stop condition is sent, the arbitration becomes relevant and the user must monitor the arblst flag. 6. if the arbitration is lost (arblst is set to 1), the user must program the twi in slave mode in the case where the master that won the arbitration wanted to access the twi. 7. if twi has to be set in slave mode, wait until txcomp flag is at 1 and then program the slave mode.
481 11011a?atarm?04-oct-10 sam3n 481 11011a?atarm?04-oct-10 sam3n note: in the case where the arbitration is lost and tw i is addressed, twi will not acknowledge even if it is programmed in slave mode as soon as arblst is set to 1. then, the master must repeat sadr. figure 28-21. programmer sends data while the bus is busy figure 28-22. arbitration cases the flowchart shown in figure 28-23 on page 482 gives an example of read and write operations in multi-master mode. twck twd data sent by a master stop sent by the master start sent by the twi data sent by the twi bus is busy bus is free a transfer is programmed (dadr + w + start + write thr) transfer is initiated twi data transfer transfer is kept bus is considered as free twck bus is busy bus is free a transfer is programmed (dadr + w + start + write thr) transfer is initiated twi data transfer transfer is kept bus is considered as free data from a master data from twi s 0 s 0 0 1 1 1 arblst s 0 s 0 0 1 1 1 twd s 0 0 1 1 1 1 1 arbitration is lost twi stops sending data p s 0 1 p 0 1 1 1 1 data from the master data from the twi arbitration is lost the master stops sending data transfer is stopped transfer is programmed again (dadr + w + start + write thr) twck twd
482 11011a?atarm?04-oct-10 sam3n 482 11011a?atarm?04-oct-10 sam3n figure 28-23. multi-master flowchart programm the slave mode: sadr + msdis + sven svacc = 1 ? txcomp = 1 ? gacc = 1 ? decoding of the programming sequence prog seq ok ? change sadr svread = 0 ? read status register rxrdy= 0 ? read twi_rhr txrdy= 1 ? eosacc = 1 ? write in twi_thr need to perform a master access ? program the master mode dadr + svdis + msen + clk + r / w read status register arblst = 1 ? mread = 1 ? txrdy= 0 ? write in twi_thr data to send ? rxrdy= 0 ? read twi_rhr data to read? read status register txcomp = 0 ? general call treatment ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s stop transfer twi_cr = stop no no no no no no no no no no no no no no no no start
483 11011a?atarm?04-oct-10 sam3n 483 11011a?atarm?04-oct-10 sam3n 28.10 slave mode 28.10.1 definition the slave mode is defined as a mode where the device receives the clock and the address from another device called the master. in this mode, the device never initiates and never completes the transmission (start, repeated_start and stop conditions are always provided by the master). 28.10.2 application block diagram figure 28-24. slave mode typical application block diagram 28.10.3 programming slave mode the following fields must be programmed before entering slave mode: 1. sadr (twi_smr): the slave device address is used in order to be accessed by mas- ter devices in read or write mode. 2. msdis (twi_cr): disable the master mode. 3. sven (twi_cr): enable the slave mode. as the device receives the clock, values written in twi_cwgr are not taken into account. 28.10.4 receiving data after a start or repeated start condition is detected and if the address sent by the master matches with the slave addre ss programmed in the sadr (slave address) field, svacc (slave access) flag is set and svread (slave read) indicates the direction of the transfer. svacc remains high until a stop condition or a repeated start is detected. when such a condition is detected, eosacc (end of slave access) flag is set. 28.10.4.1 read sequence in the case of a read sequence (svread is high), twi transfers data written in the twi_thr (twi transmit holding register) until a stop condition or a repeated _start + an address different from sadr is detected. note that at the end of the read sequence txcomp (transmis- sion complete) flag is set and svacc reset. as soon as data is written in the twi_t hr, txrdy (transmit holding register ready) flag is reset, and it is set when the shift register is empty and the sent data acknowledged or not. if the data is not acknowledged, the nack flag is set. host with twi interface twd twck lcd controller slave 1 slave 2 slave 3 rr vdd host with twi interface host with twi interface master
484 11011a?atarm?04-oct-10 sam3n 484 11011a?atarm?04-oct-10 sam3n note that a stop or a repeated start always follows a nack. see figure 28-25 on page 485 . 28.10.4.2 write sequence in the case of a write sequence (svread is low), the rxrdy (receive holding register ready) flag is set as soon as a character has been received in the twi_rhr (twi receive holding register). rxrdy is re set when reading the twi_rhr. twi continues receiving data until a stop co ndition or a repeated_start + an address dif- ferent from sadr is detected. note that at the end of the write sequence txcomp flag is set and svacc reset. see figure 28-26 on page 485 . 28.10.4.3 clock synchronization sequence in the case where twi_thr or twi_rhr is not written/read in time, twi performs a clock synchronization. clock stretching information is given by the sclws (clock wait state) bit. see figure 28-28 on page 487 and figure 28-29 on page 488 . 28.10.4.4 general call in the case where a general call is perfor med, gacc (general call access) flag is set. after gacc is set, it is up to the programmer to interpret the meaning of the general call and to decode the new address programming sequence. see figure 28-27 on page 486 . 28.10.4.5 pdc as it is impossible to know the exact number of data to receive/send, the use of pdc is not rec- ommended in slave mode. 28.10.4.6 dmac as it is impossible to know the exact number of data to receive/send, the use of dmac is not recommended in slave mode. 28.10.5 data transfer 28.10.5.1 read operation the read mode is defined as a data requirement from the master. after a start or a repeated start condition is detected, the decoding of the address starts. if the slave address (sadr) is decoded, svacc is set and svread indicates the direc- tion of the transfer. until a stop or repeated start condition is detected, twi continues sending data loaded in the twi_thr register. if a stop condition or a repeated start + an address different from sadr is detected, svacc is reset. figure 28-25 on page 485 describes the write operation.
485 11011a?atarm?04-oct-10 sam3n 485 11011a?atarm?04-oct-10 sam3n figure 28-25. read access ordered by a master notes: 1. when svacc is low, the state of svread becomes irrelevant. 2. txrdy is reset when data has been transmitted from twi_thr to the shift register and set when this data has been acknowledged or non acknowledged. 28.10.5.2 write operation the write mode is defined as a data transmission from the master. after a start or a repeated start, the decodi ng of the address starts . if the slave address is decoded, svacc is set and svread indicates the direction of the transfer (svread is low in this case). until a stop or repeated start condition is detected, twi stores the received data in the twi_rhr register. if a stop condition or a repeated start + an address different from sadr is detected, svacc is reset. figure 28-26 on page 485 describes the write operation. figure 28-26. write access ordered by a master notes: 1. when svacc is low, the state of svread becomes irrelevant. 2. rxrdy is set when data has been transmitted from the shift register to the twi_rhr and reset when this data is read. write thr read rhr svread has to be taken into account only while svacc is active twd txrdy nack svacc svread eosvacc sadr s adr r na r a data a a data na s/sr data na p/s/sr sadr matches, twi answers with an ack sadr does not match, twi answers with a nack ack/nack from the master rxrdy read rhr svread has to be taken into account only while svacc is active twd svacc svread eosvacc sadr does not match, twi answers with a nack sadr s adr w na w a data a a data na s/sr data na p/s/sr sadr matches, twi answers with an ack
486 11011a?atarm?04-oct-10 sam3n 486 11011a?atarm?04-oct-10 sam3n 28.10.5.3 general call the general call is performed in order to change the address of the slave. if a general call is detected, gacc is set. after the detection of general call, it is up to the programmer to decode the commands which come afterwards. in case of a write command, the programmer has to decode the programming sequence and program a new sadr if the programming sequence matches. figure 28-27 on page 486 describes the general call access. figure 28-27. master performs a general call note: this method allows the user to create an own programming sequence by choosing the program- ming bytes and the number of them. the programming sequence has to be provided to the master. 0000000 + w general call p s a general call reset or write dadd a new sadr data 1 a data 2 a a new sadr programming sequence txd gcacc svacc reset command = 00000110x write command = 00000100x reset after read
487 11011a?atarm?04-oct-10 sam3n 487 11011a?atarm?04-oct-10 sam3n 28.10.5.4 clock synchronization in both read and write modes, it may happen that twi_thr/tw i_rhr buffer is not filled /emp- tied before the emission/reception of a new charac ter. in this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. clock synchronization in read mode the clock is tied low if the shif t register is empty and if a stop or repeated start condition was not detected. it is tied low until the shift register is loaded. figure 28-28 on page 487 describes the clock synchronization in read mode. figure 28-28. clock synchronization in read mode notes: 1. txrdy is reset when data has been written in the twi_ thr to the shift register and set when this data has been acknowl- edged or non acknowledged. 2. at the end of the read sequence, txcomp is set after a stop or after a repeated_start + an address different from sadr. 3. sclws is automatically set when the cl ock synchronization mechanism is started. data 1 the clock is stretched after the ack, the state of twd is undefined during clock stretching sclws svacc svread txrdy twck twi_thr txcomp the data is memorized in twi_thr until a new value is written twi_thr is transmitted to the shift register ack or nack from the master data 0 data 0 data 2 1 2 1 clock is tied low by the twi as long as thr is empty s sadr s r data 0 a a data 1 a data 2 na s xxxxxxx 2 write thr as soon as a start is detected
488 11011a?atarm?04-oct-10 sam3n 488 11011a?atarm?04-oct-10 sam3n clock synchronization in write mode the clock is tied low if the shift regi ster and the twi_rhr is full. if a stop or repeated_start condition was not detected , it is tied low until twi_rhr is read. figure 28-29 on page 488 describes the clock synchronization in read mode. figure 28-29. clock synchronization in write mode notes: 1. at the end of the read sequence, txcomp is set after a stop or after a repeated_start + an address different from sadr. 2. sclws is automatically set when the cl ock synchronization mechanism is started and automatically reset when the mecha- nism is finished. rd data0 rd data1 rd data2 svacc svread rxrdy sclws txcomp data 1 data 2 scl is stretched on the last bit of data1 as soon as a start is detected twck twd twi_rhr clock is tied low by the twi as long as rhr is full data0 is not read in the rhr adr s sadr w a data 0 a a data 2 data 1 s na
489 11011a?atarm?04-oct-10 sam3n 489 11011a?atarm?04-oct-10 sam3n 28.10.5.5 reversal after a repeated start reversal of read to write the master initiates the communication by a read command and finishes it by a write command. figure 28-30 on page 489 describes the repeated start + reversal from read to write mode. figure 28-30. repeated start + reversal from read to write mode 1. txcomp is only set at the end of the transmission because after the repeated start, sadr is detected again. reversal of write to read the master initiates the communication by a write command and finishes it by a read com- mand. figure 28-31 on page 489 describes the repeated start + reversal from write to read mode. figure 28-31. repeated start + reversal from write to read mode notes: 1. in this case, if twi_thr has not bee n written at the end of the read command, the clock is automatically stretched befo re the ack. 2. txcomp is only set at the end of the transmission because after the repeated st art, sadr is detected again. s sadr r a data 0 a data 1 sadr sr na w a data 2 a data 3 a p cleared after read data 0 data 1 data 2 data 3 svacc svread twd twi_thr twi_rhr eosacc txrdy rxrdy txcomp as soon as a start is detected s sadr w a data 0 a data 1 sadr sr a r a data 2 a data 3 n a p cleared after read data 0 data 2 data 3 data 1 txcomp txrdy rxrdy as soon as a start is detected read twi_rhr svacc svread twd twi_rhr twi_thr eosacc
490 11011a?atarm?04-oct-10 sam3n 490 11011a?atarm?04-oct-10 sam3n 28.10.6 read write flowcharts the flowchart shown in figure 28-32 on page 490 gives an example of read and write operations in slave mode. a polling or interr upt method can be used to check the status bits. the interrupt method requires that the interrupt enable register (twi_ier) be configured first. figure 28-32. read write flowchart in slave mode set the slave mode: sadr + msdis + sven svacc = 1 ? txcomp = 1 ? gacc = 1 ? decoding of the programming sequence prog seq ok ? change sadr svread = 0 ? read status register rxrdy= 0 ? read twi_rhr txrdy= 1 ? eosacc = 1 ? write in twi_thr end general call treatment no no no no no no no no
491 11011a?atarm?04-oct-10 sam3n 491 11011a?atarm?04-oct-10 sam3n 28.11 two-wire interface (twi) user interface note: 1. all unlisted offset values are conisedered as ?reserved?. table 28-6. register mapping offset register name access reset 0x00 control register twi_cr write-only n / a 0x04 master mode register twi_mmr read-write 0x00000000 0x08 slave mode register twi_smr read-write 0x00000000 0x0c internal address register twi_iadr read-write 0x00000000 0x10 clock waveform generator register twi_cwgr read-write 0x00000000 0x14 - 0x1c reserved ? ? ? 0x20 status register twi_sr read-only 0x0000f009 0x24 interrupt enable regist er twi_ier write-only n / a 0x28 interrupt disable regist er twi_idr write-only n / a 0x2c interrupt mask register twi_imr read-only 0x00000000 0x30 receive holding register twi_rhr read-only 0x00000000 0x34 transmit holding register twi_thr write-only 0x00000000 0xec - 0xfc (1) reserved ? ? ? 0x100 - 0x124 reserved for the pdc ? ? ?
492 11011a?atarm?04-oct-10 sam3n 492 11011a?atarm?04-oct-10 sam3n 28.11.1 twi control register name: twi_cr addresses: 0x40018000 (0), 0x4001c000 (1) access: write-only reset: 0x00000000 ? start: send a start condition 0 = no effect. 1 = a frame beginning with a start bit is transmitted according to the features defined in the mode register. this action is necessary when the twi peripheral wants to read data from a slave. when configured in master mode with a write operation, a frame is sent as soon as the user writes a character in the transmit holding register (twi_thr). ? stop: send a stop condition 0 = no effect. 1 = stop condition is sent just after completing the current byte transmission in master read mode. ? in single data byte master read, the start and stop must both be set. ? in multiple data bytes master read, the stop must be set after the last data received but one. ? in master read mode, if a nack bit is received, the stop is automatically performed. ? in master data write operation, a st op condition will be sent after the tr ansmission of the current data is finished. ? msen: twi master mode enabled 0 = no effect. 1 = if msdis = 0, the master mode is enabled. note: switching from slave to master mo de is only permitted when txcomp = 1. ? msdis: twi master mode disabled 0 = no effect. 1 = the master mode is disabled, all pending data is transmitted. the shifter and holding characters (if it contains data) are transmitted in case of write operation. in read operation, the character being transferred must be completely received before disabling. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst quick svdis sven msdis msen stop start
493 11011a?atarm?04-oct-10 sam3n 493 11011a?atarm?04-oct-10 sam3n ? sven: twi slave mode enabled 0 = no effect. 1 = if svdis = 0, the slave mode is enabled. note: switching from master to slave mode is only permitted when txcomp = 1. ? svdis: twi slave mode disabled 0 = no effect. 1 = the slave mode is disabled. the shifter and holding characte rs (if it contains data) are transmitted in case of read oper- ation. in write operation, the character being transferred must be completely received before disabling. ? quick: smbus quick command 0 = no effect. 1 = if master mode is enabled, a smbus quick command is sent. ? swrst: software reset 0 = no effect. 1 = equivalent to a system reset.
494 11011a?atarm?04-oct-10 sam3n 494 11011a?atarm?04-oct-10 sam3n 28.11.2 twi master mode register name: twi_mmr addresses: 0x40018004 (0), 0x4001c004 (1) access: read-write reset: 0x00000000 ? iadrsz: internal device address size ? mread: master read direction 0 = master write direction. 1 = master read direction. ? dadr: device address the device address is used to access slave devices in read or write mode. those bits are only used in master mode. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?dadr 15 14 13 12 11 10 9 8 ???mread?? iadrsz 76543210 ???????? value name description 0 none no internal device address 1 1_byte one-byte internal device address 2 2_byte two-byte internal device address 3 3_byte three-byte internal device address
495 11011a?atarm?04-oct-10 sam3n 495 11011a?atarm?04-oct-10 sam3n 28.11.3 twi slave mode register name: twi_smr addresses: 0x40018008 (0), 0x4001c008 (1) access: read-write reset: 0x00000000 ? sadr: slave address the slave device address is used in slav e mode in order to be accessed by master devices in read or write mode. sadr must be programmed before enabling the slave mode or after a general call. writes at other times have no effect. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?sadr 15 14 13 12 11 10 9 8 ?????? 76543210 ????????
496 11011a?atarm?04-oct-10 sam3n 496 11011a?atarm?04-oct-10 sam3n 28.11.4 twi internal address register name: twi_iadr addresses: 0x4001800c (0), 0x4001c00c (1) access: read-write reset: 0x00000000 ? iadr: internal address 0, 1, 2 or 3 bytes depending on iadrsz. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 iadr 15 14 13 12 11 10 9 8 iadr 76543210 iadr
497 11011a?atarm?04-oct-10 sam3n 497 11011a?atarm?04-oct-10 sam3n 28.11.5 twi clock waveform generator register name: twi_cwgr addresses: 0x40018010 (0), 0x4001c010 (1) access: read-write reset: 0x00000000 twi_cwgr is only used in master mode. ? cldiv: clock low divider the scl low period is defined as follows: ? chdiv: clock high divider the scl high period is defined as follows: ? ckdiv: clock divider the ckdiv is used to increase both scl high and low periods. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ckdiv 15 14 13 12 11 10 9 8 chdiv 76543210 cldiv t low cldiv ( 2 ckdiv () 4 ) + t mck = t high chdiv ( 2 ckdiv () 4 ) + t mck =
498 11011a?atarm?04-oct-10 sam3n 498 11011a?atarm?04-oct-10 sam3n 28.11.6 twi status register name: twi_sr addresses: 0x40018020 (0), 0x4001c020 (1) access: read-only reset: 0x0000f009 ? txcomp: transmission completed (automatically set / reset) txcomp used in master mode : 0 = during the length of the current frame. 1 = when both holding and shifter registers are empty and stop condition has been sent. txcomp behavior in master mode can be seen in figure 28-8 on page 470 and in figure 28-10 on page 471 . txcomp used in slave mode : 0 = as soon as a start is detected. 1 = after a stop or a repeated start + an address different from sadr is detected. txcomp behavior in slave mode can be seen in figure 28-28 on page 487 , figure 28-29 on page 488 , figure 28-30 on page 489 and figure 28-31 on page 489 . ? rxrdy: receive holding register ready (automatically set / reset) 0 = no character has been received since the last twi_rhr read operation. 1 = a byte has been received in the twi_rhr since the last read. rxrdy behavior in master mode can be seen in figure 28-10 on page 471 . rxrdy behavior in slave mode can be seen in figure 28-26 on page 485 , figure 28-29 on page 488 , figure 28-30 on page 489 and figure 28-31 on page 489 . ? txrdy: transmit holding register ready (automatically set / reset) txrdy used in master mode : 0 = the transmit holding register has not been transferred into shift register. set to 0 when writing into twi_thr register. 1 = as soon as a data byte is transferred from twi_thr to inte rnal shifter or if a nack erro r is detected, txrdy is set at the same time as txcomp and nack. txrdy is also set when msen is set (enable twi). txrdy behavior in master mode can be seen in figure 28-8 on page 470 . 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txbufe rxbuff endtx endrx eosacc sclws arblst nack 76543210 ? ovre gacc svacc svread txrdy rxrdy txcomp
499 11011a?atarm?04-oct-10 sam3n 499 11011a?atarm?04-oct-10 sam3n txrdy used in slave mode : 0 = as soon as data is written in the twi_thr, until this data has been transmitted and acknowledged (ack or nack). 1 = it indicates that the twi_thr is empty and that data has been transmitted and acknowledged. if txrdy is high and if a nack has been detected, the tr ansmission will be stopped. thus when trdy = nack = 1, the programmer must not fill tw i_thr to avoid losing it. txrdy behavior in slave mode can be seen in figure 28-25 on page 485 , figure 28-28 on page 487 , figure 28-30 on page 489 and figure 28-31 on page 489 . ? svread: slave read (automatically set / reset) this bit is only used in slave mode. when svacc is low (no slave access has been detected) svread is irrelevant. 0 = indicates that a write access is performed by a master. 1 = indicates that a read access is performed by a master. svread behavior can be seen in figure 28-25 on page 485 , figure 28-26 on page 485 , figure 28-30 on page 489 and figure 28-31 on page 489 . ? svacc: slave access (automatically set / reset) this bit is only used in slave mode. 0 = twi is not addressed. svacc is automatically cleared af ter a nack or a stop condition is detected. 1 = indicates that the address decoding sequence has matched (a master has sent sadr). svacc remains high until a nack or a stop condition is detected. svacc behavior can be seen in figure 28-25 on page 485 , figure 28-26 on page 485 , figure 28-30 on page 489 and fig- ure 28-31 on page 489 . ? gacc: general call access (clear on read) this bit is only used in slave mode. 0 = no general call has been detected. 1 = a general call has been detected. after the detection of general call, if need be, the programmer may acknowledge this access and decode the following bytes and respond according to the value of the bytes. gacc behavior can be seen in figure 28-27 on page 486 . ? ovre: overrun error (clear on read) this bit is only used in master mode. 0 = twi_rhr has not been loaded while rxrdy was set 1 = twi_rhr has been loaded while rxrdy was set. reset by read in twi_sr when txcomp is set. ? nack: not acknowledged (clear on read) nack used in master mode : 0 = each data byte has been correctly received by the far-end side twi slave component. 1 = a data byte has not been acknowledged by the sl ave component. set at the same time as txcomp. nack used in slave read mode : 0 = each data byte has been correctly received by the master.
500 11011a?atarm?04-oct-10 sam3n 500 11011a?atarm?04-oct-10 sam3n 1 = in read mode, a data byte has not been acknowledged by the master. when nack is set the programmer must not fill twi_thr even if txrdy is set, because it means that the master will stop the data transfer or re initiate it. note that in slave write mode all data are acknowledged by the twi. ? arblst: arbitration lost (clear on read) this bit is only used in master mode. 0: arbitration won. 1: arbitration lost. another master of the twi bus has won the multi-master arbitration. txcomp is set at the same time. ? sclws: clock wait state (automatically set / reset) this bit is only used in slave mode. 0 = the clock is not stretched. 1 = the clock is stretched. twi_thr / tw i_rhr buffer is not filled / emptied bef ore the emission / reception of a new character. sclws behavior can be seen in figure 28-28 on page 487 and figure 28-29 on page 488 . ? eosacc: end of slave access (clear on read) this bit is only used in slave mode. 0 = a slave access is being performing. 1 = the slave access is finished. end of slave access is automatically set as soon as svacc is reset. eosacc behavior can be seen in figure 28-30 on page 489 and figure 28-31 on page 489 ? endrx: end of rx buffer this bit is only used in master mode. 0 = the receive counter register has not reached 0 since the last write in twi_rcr or twi_rncr. 1 = the receive counter register has reached 0 since the last write in twi_rcr or twi_rncr. ? endtx: end of tx buffer this bit is only used in master mode. 0 = the transmit counter register has not reached 0 since the last write in twi_tcr or twi_tncr. 1 = the transmit counter register has reached 0 since the last write in twi_tcr or twi_tncr. ? rxbuff: rx buffer full this bit is only used in master mode. 0 = twi_rcr or twi_rncr have a value other than 0. 1 = both twi_rcr and twi_rncr have a value of 0. ? txbufe: tx buffer empty this bit is only used in master mode. 0 = twi_tcr or twi_tncr have a value other than 0. 1 = both twi_tcr and twi_tncr have a value of 0.
501 11011a?atarm?04-oct-10 sam3n 501 11011a?atarm?04-oct-10 sam3n 28.11.7 twi interrupt enable register name: twi_ier addresses: 0x40018024 (0), 0x4001c024 (1) access: write-only reset: 0x00000000 ? txcomp: transmission completed interrupt enable ? rxrdy: receive holding register ready interrupt enable ? txrdy: transmit holding register ready interrupt enable ? svacc: slave access interrupt enable ? gacc: general call access interrupt enable ? ovre: overrun error interrupt enable ? nack: not acknowledge interrupt enable ? arblst: arbitration lost interrupt enable ? scl_ws: clock wait state interrupt enable ? eosacc: end of slave access interrupt enable ? endrx: end of receive buffer interrupt enable ? endtx: end of transmit buffer interrupt enable ? rxbuff: receive buffer full interrupt enable ? txbufe: transmit buffer empty interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txbufe rxbuff endtx endrx eosacc scl_ws arblst nack 76543210 ? ovre gacc svacc ? txrdy rxrdy txcomp
502 11011a?atarm?04-oct-10 sam3n 502 11011a?atarm?04-oct-10 sam3n 28.11.8 twi interrupt disable register name: twi_idr addresses: 0x40018028 (0), 0x4001c028 (1) access: write-only reset: 0x00000000 ? txcomp: transmission completed interrupt disable ? rxrdy: receive holding regi ster ready interrupt disable ? txrdy: transmit holding register ready interrupt disable ? svacc: slave access interrupt disable ? gacc: general call access interrupt disable ? ovre: overrun error interrupt disable ? nack: not acknowledge interrupt disable ? arblst: arbitration lost interrupt disable ? scl_ws: clock wait state interrupt disable ? eosacc: end of slave access interrupt disable ? endrx: end of receive buffer interrupt disable ? endtx: end of transmit buffer interrupt disable ? rxbuff: receive buffer full interrupt disable ? txbufe: transmit buffer empty interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txbufe rxbuff endtx endrx eosacc scl_ws arblst nack 76543210 ? ovre gacc svacc ? txrdy rxrdy txcomp
503 11011a?atarm?04-oct-10 sam3n 503 11011a?atarm?04-oct-10 sam3n 28.11.9 twi interrupt mask register name: twi_imr addresses: 0x4001802c (0), 0x4001c02c (1) access: read-only reset: 0x00000000 ? txcomp: transmission completed interrupt mask ? rxrdy: receive holding regi ster ready interrupt mask ? txrdy: transmit holding register ready interrupt mask ? svacc: slave access interrupt mask ? gacc: general call access interrupt mask ? ovre: overrun error interrupt mask ? nack: not acknowledge interrupt mask ? arblst: arbitration lost interrupt mask ? scl_ws: clock wait state interrupt mask ? eosacc: end of slave access interrupt mask ? endrx: end of receive buffer interrupt mask ? endtx: end of transmit buffer interrupt mask ? rxbuff: receive buffer full interrupt mask ? txbufe: transmit buffer empty interrupt mask 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txbufe rxbuff endtx endrx eosacc scl_ws arblst nack 76543210 ? ovre gacc svacc ? txrdy rxrdy txcomp
504 11011a?atarm?04-oct-10 sam3n 504 11011a?atarm?04-oct-10 sam3n 28.11.10 twi receive holding register name: twi_rhr addresses: 0x40018030 (0), 0x4001c030 (1) access: read-only reset: 0x00000000 ? rxdata: master or slave receive holding data 28.11.11 twi transmit holding register name: twi_thr addresses: 0x40018034 (0), 0x4001c034 (1) access: read-write reset: 0x00000000 ? txdata: master or slave transmit holding data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rxdata 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txdata
505 11011a?atarm?04-oct-10 sam3n 505 11011a?atarm?04-oct-10 sam3n 29. universal asynchronous receiver transceiver (uart) 29.1 description the universal asynchronous receiver transmitter features a two-pin uart that can be used for communication and trace purposes and offers an ideal medium for in-situ programming solu- tions. moreover, the association with two peripheral dma controller (pdc) channels permits packet handling for these tasks with processor time reduced to a minimum. 29.2 embedded characteristics ?two-pin uart ? implemented features are usart compatible ? independent receiver and transmitter with a common programmable baud rate generator ? even, odd, mark or space parity generation ? parity, framing and overrun error detection ? automatic echo, local loopback and remote loopback channel modes ? interrupt generation ? support for two pdc channels with connection to receiver and transmitter
506 11011a?atarm?04-oct-10 sam3n 506 11011a?atarm?04-oct-10 sam3n 29.3 block diagram figure 29-1. uart functional block diagram 29.4 product dependencies 29.4.1 i/o lines the uart pins are multiplexed with pio lines. the programmer must first configure the corre- sponding pio controller to enable i/o line operations of the uart. 29.4.2 power management the uart clock is controllable through the power management controller. in this case, the pro- grammer must first configure the pmc to enable the uart clock. usually, the peripheral identifier used for this purpose is 1. peripher a l dma controller b au d r a te gener a tor tr a n s mit receive interr u pt control peripher a l bridge p a r a llel inp u t/ o u tp u t utxd urxd power m a n a gement controller mck ua rt_ir q apb uart table 29-1. uart pin description pin name description type urxd uart receive data input utxd uart transmit data output table 29-2. i/o lines instance signal i/o line peripheral uart0 urxd0 pa9 a uart0 utxd0 pa10 a uart1 urxd1 pb2 a uart1 utxd1 pb3 a
507 11011a?atarm?04-oct-10 sam3n 507 11011a?atarm?04-oct-10 sam3n 29.4.3 interrupt source the uart interrupt line is connected to one of the interrupt sources of the nested vectored interrupt controller (nvic). interrupt handling requires programming of the nvic before config- uring the uart. 29.5 uart operations the uart operates in asynchronous mode only and supports only 8-bit character handling (with parity). it has no clock pin. the uart is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. receiver timeout and transmitter time guard are not implemented. how- ever, all the implemented features are compatible with those of a standard usart. 29.5.1 baud rate generator the baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. the baud rate clock is the master clock divided by 16 times the value (cd) written in uart_brgr (baud rate generator register). if ua rt_brgr is set to 0, the baud rate clock is disabled and the uart remains inactive. the maximum allowable baud rate is master clock divided by 16. the minimum allowable baud rate is master clock divided by (16 x 65536). figure 29-2. baud rate generator 29.5.2 receiver 29.5.2.1 receiver rese t, enable and disable after device reset, the uart receiver is disabled and must be enabled before being used. the receiver can be enabled by writing the control re gister uart_cr with the bit rxen at 1. at this command, the receiver starts looking for a start bit. the programmer can disable the receiver by writing uart_cr with the bit rxdis at 1. if the receiver is waiting for a start bit, it is immedi ately stopped. however, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. baud rate mck 16 cd ----------------------- - = mck 16-bit counter 0 baud rate clock cd cd out divide by 16 0 1 >1 receiver sampling clock
508 11011a?atarm?04-oct-10 sam3n 508 11011a?atarm?04-oct-10 sam3n the programmer can also put the receiver in it s reset state by writing uart_cr with the bit rstrx at 1. in doing so, the receiver immediat ely stops its current operations and is disabled, whatever its current state. if rstrx is applied wh en data is being processed, this data is lost. 29.5.2.2 start detection and data sampling the uart only supports asynchronous operations, and this affects only its receiver. the uart receiver detects the start of a received character by sampling th e urxd signal until it detects a valid start bit. a low level (space) on urxd is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. a space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. when a valid start bit has been detected, the receiver samples the urxd at the theoretical mid- point of each bit. it is assumed that each bit last s 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. the first sampling point is therefore 24 cycles (1.5 -bit periods) after t he falling edge of the st art bit was detected. each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. figure 29-3. start bit detection figure 29-4. character reception 29.5.2.3 receiver ready when a complete character is re ceived, it is transferred to the uart_rhr and the rxrdy sta- tus bit in uart_sr (status register) is set. the bit rxrdy is automatically cleared when the receive holding regist er uart_rhr is read. sampling clock urxd true start detection d0 baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 urxd true start detection sampling parity bit stop bit example: 8-bit, parity enabled 1 stop 1 bit period 0.5 bit period
509 11011a?atarm?04-oct-10 sam3n 509 11011a?atarm?04-oct-10 sam3n figure 29-5. receiver ready 29.5.2.4 receiver overrun if uart_rhr has not been read by the software (or the peripheral data controller or dma controller) since the last transf er, the rxrdy bit is still set and a new character is received, the ovre status bit in uart_sr is set. ovre is cl eared when the software writes the control regis- ter uart_cr with the bit rststa (reset status) at 1. figure 29-6. receiver overrun 29.5.2.5 parity error each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field par in uart_mr. it then compares the result with the received parity bit. if different, the parity error bit pare in uart_sr is set at the same time the rxrdy is set. the parity bit is cleared when the control regist er uart_cr is written with the bit rststa (reset status) at 1. if a new character is received before the reset status command is written, the pare bit remains at 1. figure 29-7. parity error 29.5.2.6 receiver framing error when a start bit is detected, it generates a character reception when all the data bits have been sampled. the stop bit is also sampled and when it is detected at 0, the frame (framing error) bit in uart_sr is set at the same time the rx rdy bit is set. the frame bit remains high until the control register uart_cr is wr itten with the bit rststa at 1. d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p urxd read uart_rhr rxrdy d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p urxd rststa rxrdy ovre stop stop stop d0 d1 d2 d3 d4 d5 d6 d7 p s urxd rststa rxrdy pare wrong parity bit
510 11011a?atarm?04-oct-10 sam3n 510 11011a?atarm?04-oct-10 sam3n figure 29-8. receiver framing error 29.5.3 transmitter 29.5.3.1 transmitter reset, enable and disable after device reset, the uart transmitter is disabled and it must be enabled before being used. the transmitter is enabled by writing the control register uart_cr with the bit txen at 1. from this command, the transmitter waits for a character to be written in the transmit holding register (uart_thr) before actually starting the transmission. the programmer can disable the transmitter by writing uart_cr with the bit txdis at 1. if the transmitter is not operating, it is immediately stopped. however, if a character is being pro- cessed into the shift register and/or a character has been written in the transmit holding register, the characters are completed before the transmitter is actually stopped. the programmer can also put the transmitter in its reset state by writing the uart_cr with the bit rsttx at 1. this immediately stops the transmitter, whether or not it is processing characters. 29.5.3.2 transmit format the uart transmitter drives the pin utxd at the baud rate clock speed. the line is driven depending on the format defined in the mode register and the data stored in the shift register. one start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown in the following figure. the field pare in the mode register uart_mr defines whether or not a parity bit is shifted out. when a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. figure 29-9. character transmission 29.5.3.3 transmitter control when the transmitter is enabled, the bit txrdy (transmitter ready) is set in the status register uart_sr. the transmission starts when the prog rammer writes in the tr ansmit holding regis- ter (uart_thr), and after the written character is transferred from uart_thr to the shift d0 d1 d2 d3 d4 d5 d6 d7 p s urxd rststa rxrdy frame stop bit detected at 0 stop d0 d1 d2 d3 d4 d5 d6 d7 utxd start bit parity bit stop bit example: parity enabled baud rate clock
511 11011a?atarm?04-oct-10 sam3n 511 11011a?atarm?04-oct-10 sam3n register. the txrdy bit remains high until a se cond character is written in uart_thr. as soon as the first character is completed, the last character written in uart_thr is transferred into the shift register and txrdy rises again, showing that the holding register is empty. when both the shift register and uart_thr are empty, i.e., all the characters written in uart_thr have been processed, the txempty bit rises after the last stop bit has been completed. figure 29-10. transmitter control 29.5.4 peripheral dma controller both the receiver and the transmitter of the ua rt are connected to a peripheral dma controller (pdc) channel. the peripheral data controller channels are programmed via registers that are mapped within the uart user interface from the offset 0x100. the status bits are reported in the uart status register (uart_sr) and can generate an interrupt. the rxrdy bit triggers the pdc channel data transfer of the receiver. this results in a read of the data in uart_rhr. the txrdy bit triggers the pdc channel data transfer of the transmit- ter. this results in a wr ite of data in uart_thr. 29.5.5 test modes the uart supports three test modes. these modes of operation are programmed by using the field chmode (channel mode) in the mode register (uart_mr). the automatic echo mode allows bit-by-bit retr ansmission. when a bit is received on the urxd line, it is sent to the utxd line. the transm itter operates normally, but has no effect on the utxd line. the local loopback mode allows the transmitted characters to be received. utxd and urxd pins are not used and the output of the transmitter is internally connected to the input of the receiver. the urxd pin level has no effect and th e utxd line is held high , as in idle state. the remote loopback mode directly connects the urxd pin to the utxd line. the transmitter and the receiver are disabled and have no effec t. this mode allows a bit-by-bit retransmission. uart_thr shift register utxd txrdy txempty data 0 data 1 data 0 data 0 data 1 data 1 s s p p write data 0 in uart_thr write data 1 in uart_thr stop stop
512 11011a?atarm?04-oct-10 sam3n 512 11011a?atarm?04-oct-10 sam3n figure 29-11. test modes receiver transmitter disabled rxd txd receiver transmitter disabled rxd txd v dd disabled receiver transmitter disabled rxd txd disabled automatic echo local loopback remote loopback v dd
513 11011a?atarm?04-oct-10 sam3n 513 11011a?atarm?04-oct-10 sam3n 29.6 universal asynchronous receiver transmitter (uart) user interface table 29-3. register mapping offset register name access reset 0x0000 control register uart_cr write-only ? 0x0004 mode register uart_mr read-write 0x0 0x0008 interrupt enable register uart_ier write-only ? 0x000c interrupt disable register uart_idr write-only ? 0x0010 interrupt mask register uart_imr read-only 0x0 0x0014 status register uart_sr read-only ? 0x0018 receive holding register uart_rhr read-only 0x0 0x001c transmit holding register uart_thr write-only ? 0x0020 baud rate generator register uart_brgr read-write 0x0 0x0024 - 0x003c reserved ? ? ? 0x004c - 0x00fc reserved ? ? ? 0x0100 - 0x0124 pdc area ? ? ?
514 11011a?atarm?04-oct-10 sam3n 514 11011a?atarm?04-oct-10 sam3n 29.6.1 uart control register name: uart_cr addresses: 0x400e0600 (0), 0x400e0800 (1) access: write-only ? rstrx: reset receiver 0 = no effect. 1 = the receiver logic is reset and disabled. if a ch aracter is being received, the reception is aborted. ? rsttx: reset transmitter 0 = no effect. 1 = the transmitter logic is reset and disabled. if a character is being transmitted, the transmission is aborted. ? rxen: receiver enable 0 = no effect. 1 = the receiver is enabled if rxdis is 0. ? rxdis: receiver disable 0 = no effect. 1 = the receiver is disabled. if a character is being processe d and rstrx is not set, the character is completed before the receiver is stopped. ? txen: transmitter enable 0 = no effect. 1 = the transmitter is ena bled if txdis is 0. ? txdis: transmitter disable 0 = no effect. 1 = the transmitter is disabled. if a character is being processed and a character has been written in the uart_thr and rsttx is not set, both characters are completed before the transmitter is stopped. ? rststa: reset status bits 0 = no effect. 1 = resets the status bits pare, frame and ovre in the uart_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????? rststa 76543210 txdis txen rxdis rxen rsttx rstrx ??
515 11011a?atarm?04-oct-10 sam3n 515 11011a?atarm?04-oct-10 sam3n 29.6.2 uart mode register name: uart_mr addresses: 0x400e0604 (0), 0x400e0804 (1) access: read-write ? par: parity type ? chmode: channel mode 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 chmode ?? pa r ? 76543210 ???????? value name description 0 even even parity 1 odd odd parity 2 space space: parity forced to 0 3 mark mark: parity forced to 1 4 no no parity value name description 0 normal normal mode 1 automatic automatic echo 2 local_loopback local loopback 3 remote_loopback remote loopback
516 11011a?atarm?04-oct-10 sam3n 516 11011a?atarm?04-oct-10 sam3n 29.6.3 uart interrupt enable register name: uart_ier addresses: 0x400e0608 (0), 0x400e0808 (1) access: write-only ? rxrdy: enable rxrdy interrupt ? txrdy: enable txrdy interrupt ? endrx: enable end of receive transfer interrupt ? endtx: enable end of transmit interrupt ? ovre: enable overrun error interrupt ? frame: enable framing error interrupt ? pare: enable parity error interrupt ? txempty: enable txempty interrupt ? txbufe: enable buffer empty interrupt ? rxbuff: enable buffer full interrupt 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
517 11011a?atarm?04-oct-10 sam3n 517 11011a?atarm?04-oct-10 sam3n 29.6.4 uart interrupt disable register name: uart_idr addresses: 0x400e060c (0), 0x400e080c (1) access: write-only ? rxrdy: disable rxrdy interrupt ? txrdy: disable txrdy interrupt ? endrx: disable end of receive transfer interrupt ? endtx: disable end of transmit interrupt ? ovre: disable overrun error interrupt ? frame: disable framing error interrupt ? pare: disable parity error interrupt ? txempty: disable txempty interrupt ? txbufe: disable buffer empty interrupt ? rxbuff: disable buffer full interrupt 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
518 11011a?atarm?04-oct-10 sam3n 518 11011a?atarm?04-oct-10 sam3n 29.6.5 uart interrupt mask register name: uart_imr addresses: 0x400e0610 (0), 0x400e0810 (1) access: read-only ? rxrdy: mask rxrdy interrupt ? txrdy: disable txrdy interrupt ? endrx: mask end of receive transfer interrupt ? endtx: mask end of transmit interrupt ? ovre: mask overrun error interrupt ? frame: mask framing error interrupt ? pare: mask parity error interrupt ? txempty: mask txempty interrupt ? txbufe: mask txbufe interrupt ? rxbuff: mask rxbuff interrupt 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
519 11011a?atarm?04-oct-10 sam3n 519 11011a?atarm?04-oct-10 sam3n 29.6.6 uart status register name: uart_sr addresses: 0x400e0614 (0), 0x400e0814 (1) access: read-only ? rxrdy: receiver ready 0 = no character has been received since the last re ad of the uart_rhr or the receiver is disabled. 1 = at least one complete character has been received, transferred to uart_rhr and not yet read. ? txrdy: transmitter ready 0 = a character has been written to uart_thr and not yet transferred to the shift register, or the transmitter is disabled. 1 = there is no character written to uart_thr not yet transferred to the shift register. ? endrx: end of receiver transfer 0 = the end of transfer signal from the receiver peripheral data controller channel is inactive. 1 = the end of transfer signal from the receiver peripheral data controller channel is active. ? endtx: end of transmitter transfer 0 = the end of transfer signal from the transmitter peripheral data controller channel is inactive. 1 = the end of transfer signal from the transmitter peripheral data controller channel is active. ? ovre: overrun error 0 = no overrun error has occurred since the last rststa. 1 = at least one overrun error has occurred since the last rststa. ? frame: framing error 0 = no framing error has occurred since the last rststa. 1 = at least one framing error has occurred since the last rststa. ? pare: parity error 0 = no parity error has occurred since the last rststa. 1 = at least one parity error has occurred since the last rststa. ? txempty: transmitter empty 0 = there are characters in uart_thr, or characters being processed by the transmitter, or the transmitter is disabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
520 11011a?atarm?04-oct-10 sam3n 520 11011a?atarm?04-oct-10 sam3n 1 = there are no characters in uart_thr and there ar e no characters being processed by the transmitter. ? txbufe: transmission buffer empty 0 = the buffer empty signal from the transmitter pdc channel is inactive. 1 = the buffer empty signal from the transmitter pdc channel is active. ? rxbuff: receive buffer full 0 = the buffer full signal from the receiver pdc channel is inactive. 1 = the buffer full signal from the receiver pdc channel is active.
521 11011a?atarm?04-oct-10 sam3n 521 11011a?atarm?04-oct-10 sam3n 29.6.7 uart receiver holding register name: uart_rhr addresses: 0x400e0618 (0), 0x400e0818 (1) access: read-only ? rxchr: received character last received character if rxrdy is set. 29.6.8 uart transmit holding register name: uart_thr addresses: 0x400e061c (0), 0x400e081c (1) access: write-only ? txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rxchr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txchr
522 11011a?atarm?04-oct-10 sam3n 522 11011a?atarm?04-oct-10 sam3n 29.6.9 uart baud rate generator register name: uart_brgr addresses: 0x400e0620 (0), 0x400e0820 (1) access: read-write ? cd: clock divisor 0 = baud rate clock is disabled 1 to 65,535 = mck / (cd x 16) 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cd 76543210 cd
523 11011a?atarm?04-oct-10 sam3n 523 11011a?atarm?04-oct-10 sam3n 30. universal synchronous asynchrono us receiver transmitter (usart) 30.1 description the universal synchronous asynchronous rece iver transceiver (usart) provides one full duplex universal synchronous asynchronous serial link. data frame format is widely programma- ble (data length, parity, number of stop bits) to support a maximum of standards. the receiver implements parity error, framing error and overrun error detection. the receiver time-out enables handling variable-length frames and the transmitt er timeguard facilitates communications with slow remote devices. multidrop communications are also supported through address bit han- dling in reception and transmission. the usart features three test modes: remote loopback, local loopback and automatic echo. the usart supports specific operating modes providing interfaces on rs485 and spi buses, with iso7816 t = 0 or t = 1 smart card slots and infrared transceivers. the hardware handshak- ing feature enables an out-of-band flow control by automatic management of the pins rts and cts. the usart supports the connection to the peripheral dma controller, which enables data transfers to the transmitter and from the receiver. the pdc provides chained buffer manage- ment without any intervention of the processor. 30.2 embedded characteristics ? programmable baud rate generator ? 5- to 9-bit full-duplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in asynchronous mode or 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb- or lsb-first ? optional break generation and detection ? by 8 or by 16 over-sampling receiver frequency ? optional hardware handshaking rts-cts ? receiver time-out and transmitter timeguard ? optional multidrop mode with address generation and detection ? rs485 with driver control signal ? iso7816, t = 0 or t = 1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit ? irda modulation and demodulation ? communication at up to 115.2 kbps ? spi mode ?master or slave ? serial clock programmab le phase and polarity ? spi serial clock (sck) frequency up to internal clock frequency mck/6 ? test modes ? remote loopback, local loopback, automatic echo ? supports connection of two peripheral dma controller channels (pdc) ? offers buffer transfer without processor intervention
524 11011a?atarm?04-oct-10 sam3n 524 11011a?atarm?04-oct-10 sam3n 30.3 block diagram figure 30-1. usart block diagram table 30-1. spi operating mode pin usart spi slave spi master rxd rxd mosi miso txd txd miso mosi rts rts ? cs cts cts cs ? (peripheral) dma controller channel channel interrupt controller receiver usart interrupt rxd txd sck usart pio controller cts rts transmitter baud rate generator user interface pmc mck slck div mck/div apb
525 11011a?atarm?04-oct-10 sam3n 525 11011a?atarm?04-oct-10 sam3n 30.4 application block diagram figure 30-2. application block diagram smart card slot usart rs485 drivers differential bus irda transceivers field bus driver emv driver irda driver irlap rs232 drivers serial port serial driver ppp spi driver spi bus
526 11011a?atarm?04-oct-10 sam3n 526 11011a?atarm?04-oct-10 sam3n 30.5 i/o lines description table 30-2. i/o line description name description type active level sck serial clock i/o txd transmit serial data or master out slave in (mosi) in spi master mode or master in slave out (miso) in spi slave mode i/o rxd receive serial data or master in slave out (miso) in spi master mode or master out slave in (mosi) in spi slave mode input cts clear to send or slave select (nss) in spi slave mode input low rts request to send or slave select (nss) in spi master mode output low
527 11011a?atarm?04-oct-10 sam3n 527 11011a?atarm?04-oct-10 sam3n 30.6 product dependencies 30.6.1 i/o lines the pins used for interfacing the usart may be multiplexed with the pio lines. the program- mer must first program the pio controller to assign the desired usart pins to their peripheral function. if i/o lines of the usart are not used by the application, they can be used for other purposes by the pio controller. to prevent the txd line from falling when the usart is di sabled, the use of an internal pull up is mandatory. if the hardware handshaking feature is used, the internal pull up on txd must also be enabled. 30.6.2 power management the usart is not continuously clocked. the pr ogrammer must first enable the usart clock in the power management controller (pmc) before usin g the usart. however, if the application does not require usart operations, the usart clock can be stopped when not needed and be restarted later. in this case, the usart will resume its operations where it left off. configuring the usart does not require the usart clock to be enabled. 30.6.3 interrupt the usart interrupt line is connected on one of the internal sources of the interrupt controller. using the usart interrupt requires the interrupt controller to be programmed first. note that it is not recommended to use the usart interrupt line in edge sensitive mode. table 30-3. i/o lines instance signal i/o line peripheral usart0 cts0 pa8 a usart0 rts0 pa7 a usart0 rxd0 pa5 a usart0 sck0 pa2 b usart0 txd0 pa6 a usart1 cts1 pa25 a usart1 rts1 pa24 a usart1 rxd1 pa21 a usart1 sck1 pa23 a usart1 txd1 pa22 a table 30-4. peripheral ids instance id usart0 14 usart1 15
528 11011a?atarm?04-oct-10 sam3n 528 11011a?atarm?04-oct-10 sam3n 30.7 functional description the usart is capable of managing several ty pes of serial synchronous or asynchronous communications. it supports the following communication modes: ? 5- to 9-bit full-duplex asynchronous serial communication ? msb- or lsb-first ? 1, 1.5 or 2 stop bits ? parity even, odd, marked, space or none ? by 8 or by 16 over-sampling receiver frequency ? optional hardware handshaking ? optional break management ? optional multidrop serial communication ? high-speed 5- to 9-bit full-duplex synchronous serial communication ? msb- or lsb-first ? 1 or 2 stop bits ? parity even, odd, marked, space or none ? by 8 or by 16 over-sampling frequency ? optional hardware handshaking ? optional break management ? optional multidrop serial communication ? rs485 with driver control signal ? iso7816, t0 or t1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit, inverted data. ? infrared irda modulation and demodulation ? spi mode ?master or slave ? serial clock programmab le phase and polarity ? spi serial clock (sck) frequency up to internal clock frequency mck/6 ? test modes ? remote loopback, local loopback, automatic echo
529 11011a?atarm?04-oct-10 sam3n 529 11011a?atarm?04-oct-10 sam3n 30.7.1 baud rate generator the baud rate generator provides the bit period clock named the baud rate clock to both the receiver and the transmitter. the baud rate generator clock source can be selected by setting the usclks field in the mode register (us_mr) between: ? the master clock mck ? a division of the master clock, the divider being product dependent, but generally set to 8 ? the external clock, available on the sck pin the baud rate generator is based upon a 16-bit divider, which is programmed with the cd field of the baud rate generator register (us_brgr). if cd is programmed to 0, the baud rate generator does not generate any clock. if cd is programmed to 1, the divider is bypassed and becomes inactive. if the external sck clock is selected, the duration of the low and high levels of the signal pro- vided on the sck pin must be longer than a master clock (mck) period. the frequency of the signal provided on sck must be at least 3 times lower than mck in usart mode, or 6 in spi mode. figure 30-3. baud rate generator 30.7.1.1 baud rate in asynchronous mode if the usart is programmed to operate in as ynchronous mode, the selected clock is first divided by cd, which is field programmed in the baud rate generator register (us_brgr). the resulting clock is provided to the receiv er as a sampling clock and then divided by 16 or 8, depending on the programming of the over bit in us_mr. if over is set to 1, the receiver sampling is 8 times higher than the baud rate clock. if over is cleared, the sampling is performed at 16 times the baud rate clock. the following formula performs the calculation of the baud rate. this gives a maximum baud rate of mck divided by 8, assuming that mck is the highest possi- ble clock and that over is programmed to 1. mck/div 16-bit counter 0 baud rate clock cd cd sampling divider 0 1 >1 sampling clock reserved mck sck usclks over sck sync sync usclks = 3 1 0 2 3 0 1 0 1 fidi baudrate selectedclock 82 over ? () cd () -------------------------------------------- =
530 11011a?atarm?04-oct-10 sam3n 530 11011a?atarm?04-oct-10 sam3n baud rate calculation example table 30-5 shows calculations of cd to obtain a baud rate at 38400 bauds for different source clock frequencies. this table also shows the actual resulting baud rate and the error. the baud rate is calculated with the following formula: the baud rate error is calculated with the following formula. it is not recommended to work with an error higher than 5%. 30.7.1.2 fractional baud rate in asynchronous mode the baud rate generator previously defined is su bject to the following limitation: the output fre- quency changes by only integer multiples of the reference frequency. an approach to this problem is to integrate a fractional n clock generator that has a high resolution. the generator architecture is modified to obtain baud rate c hanges by a fraction of the reference source clock. this fractional part is programmed with the fp field in the baud rate generator register (us_brgr). if fp is not 0, the fractional part is activated. the resolution is one eighth of the table 30-5. baud rate example (over = 0) source clock expected baud rate calculation result cd actual baud rate error mhz bit/s bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.30 23 38 908.10 1.31% 14 745 600 38 400 24.00 24 38 400.00 0.00% 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.16% 50 000 000 38 400 81.38 81 38 580.25 0.47% baudrate mck cd 16 ? = error 1 expectedbaudrate actualbaudrate -------------------------------------------------- - ?? ?? ? =
531 11011a?atarm?04-oct-10 sam3n 531 11011a?atarm?04-oct-10 sam3n clock divider. this feature is only available when using usart normal mode. the fractional baud rate is calculated using the following formula: the modified architecture is presented below: figure 30-4. fractional baud rate generator 30.7.1.3 baud rate in synchronous mode or spi mode if the usart is programmed to operate in synchronous mode, the selected clock is simply divided by the field cd in us_brgr. in synchronous mode, if the external clock is selected (usclks = 3), the clock is provided directly by the signal on the usart sck pin. no division is active. the value written in us_brgr has no effect. the external clock frequency must be at least 3 times lower than the system clock. in synchronous mode master (usclks = 0 or 1, clk0 set to 1), the receive part limits the sck maximum frequency to mck/3 in usart mode, or mck/6 in spi mode. when either the external clock sck or the inte rnal clock divided (mck/div) is selected, the value programmed in cd must be even if the user has to ensure a 50:50 mark/space ratio on the sck pin. if the internal clock mck is selected, the baud rate generator ensures a 50:50 duty cycle on the sck pin, even if the value programmed in cd is odd. 30.7.1.4 baud rate in iso 7816 mode the iso7816 specification defines the bit rate with the following formula: baudrate selectedclock 82 over ? () cd fp 8 ------- + ?? ?? ?? ?? ---------------------------------------------------------------- - = mck/div 16-bit counter 0 baud rate clock cd cd sampling divider 0 1 >1 sampling clock reserved mck sck usclks over sck sync sync usclks = 3 1 0 2 3 0 1 0 1 fidi glitch-free logic modulus control fp fp baudrate selectedclock cd ------------------------------------- - = b di fi ----- - f =
532 11011a?atarm?04-oct-10 sam3n 532 11011a?atarm?04-oct-10 sam3n where: ? b is the bit rate ? di is the bit-rate adjustment factor ? fi is the clock frequency division factor ? f is the iso7816 clock frequency (hz) di is a binary value encoded on a 4-bit field, named di, as represented in table 30-6 . fi is a binary value encoded on a 4-bi t field, named fi, as represented in table 30-7 . table 30-8 shows the resulting fi/di ratio, which is the ratio between the iso7816 clock and the baud rate clock. if the usart is configured in iso7816 mode, th e clock selected by the usclks field in the mode register (us_mr) is first divided by the value programmed in the field cd in the baud rate generator register (us_brgr). the resulting clock can be provided to the sck pin to feed the smart card clock inputs. this means that the clko bit can be set in us_mr. this clock is then divided by the value progra mmed in the fi_di_ratio field in the fi_di_ratio register (us_fidi). this is performed by the sampling divider, which performs a division by up to 2047 in iso7816 mode. the non-integer values of the fi/di ratio are not supported and the user must program the fi_di_ratio field to a va lue as close as possible to the expected value. the fi_di_ratio field resets to the value 0x174 (372 in decimal) and is the most common divider between the iso7816 clock and the bit rate (fi = 372, di = 1). figure 30-5 shows the relation between the elementary time unit, corresponding to a bit time, and the iso 7816 clock. table 30-6. binary and decimal values for di di field 0001 0010 0011 0100 0101 0110 1000 1001 di (decimal)1 2 4 8 163212 20 table 30-7. binary and decimal values for fi fi field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 fi (decimal) 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 table 30-8. possible values for the fi/di ratio fi/di 372 558 774 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128 32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6 20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4
533 11011a?atarm?04-oct-10 sam3n 533 11011a?atarm?04-oct-10 sam3n figure 30-5. elementary time unit (etu) 30.7.2 receiver and transmitter control after reset, the receiver is disabled. the user must enable the receiver by setting the rxen bit in the control register (us_cr). however, the receiver registers can be programmed before the receiver clock is enabled. after reset, the transmitter is disabled. the user must enable it by setting the txen bit in the control register (us_cr). however, the transmitter registers can be programmed before being enabled. the receiver and the transmitter can be enabled together or independently. at any time, the software can perform a reset on the receiver or the transmitter of the usart by setting the corresponding bit, rstrx and rsttx respectively, in the control register (us_cr). the software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. regard- less of what the receiver or the transmitter is performing, the communi cation is immediately stopped. the user can also independently disable the receiv er or the transmitter by setting rxdis and txdis respectively in us_cr. if the receiver is disabled during a character reception, the usart waits until the end of reception of the current character, then the reception is stopped. if the transmitter is disabled while it is operating, the usart waits the end of transmission of both the current character and character being stored in the transmit holding register (us_thr). if a timeguard is programmed, it is handled normally. 30.7.3 synchronous and asynchronous modes 30.7.3.1 transmitter operations the transmitter performs the same in both synchronous and asynchronous operating modes (sync = 0 or sync = 1). one start bit, up to 9 da ta bits, one optional parity bit and up to two stop bits are successively shifted out on the txd pin at each falling edge of the programmed serial clock. the number of data bits is selected by the chrl field and the mode 9 bit in the mode register (us_mr). nine bits are selected by setting the mode 9 bit regardless of the chrl field. the parity bit is set according to the par field in us_mr. the even, odd, space, marked or none parity bit can be configured. the msbf field in us _mr configures which data bit is sent first. if written to 1, the most significant bit is sent first. if written to 0, the less significant bit is sent first. the number of stop bits is selected by the nbst op field in us_mr. the 1.5 stop bit is sup- ported in asynchronous mode only. 1 etu iso7816 clock on sck iso7816 i/o line on txd fi_di_ratio iso7816 clock cycles
534 11011a?atarm?04-oct-10 sam3n 534 11011a?atarm?04-oct-10 sam3n figure 30-6. character transmit the characters are sent by writing in the tran smit holding register (us_thr). the transmitter reports two status bits in the channel status register (us_csr): txrdy (transmitter ready), which indicates that us_thr is empty and txempty, which indicates that all the characters written in us_thr have been processed. when the current character processing is completed, the last character written in us_thr is transferred into the shift register of the transmitter and us_thr becomes empty, thus txrdy rises. both txrdy and txempty bits are low when the transmitter is disabled. writing a character in us_thr while txrdy is low has no effect and the written character is lost. figure 30-7. transmitter status 30.7.3.2 asynchronous receiver if the usart is programmed in asynchronous operating mode (sync = 0), the receiver over- samples the rxd input line. the oversampling is either 16 or 8 times the baud rate clock, depending on the over bit in the mode register (us_mr). the receiver samples the rxd line. if the line is sampled during one half of a bit time to 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. if the oversampling is 16, (over to 0), a start is detected at the eighth sample to 0. then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. if the oversampling is 8 (over to 1), a start bit is detected at the fourth sample to 0. then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. the number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively chrl , mode9, msbf and par. for the synchronization mechanism only , the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field nbstop, so that resynchronization between the receiver and the d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit example: 8-bit, parity enabled one stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty
535 11011a?atarm?04-oct-10 sam3n 535 11011a?atarm?04-oct-10 sam3n transmitter can occur. moreover, as soon as the st op bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. figure 30-8 and figure 30-9 illustrate start detection and character reception when usart operates in asynchronous mode. figure 30-8. asynchronous start detection figure 30-9. asynchronous character reception 30.7.3.3 synchronous receiver in synchronous mode (sync = 1), the receiver samples the rxd signal on each rising edge of the baud rate clock. if a lo w level is detected, it is considered as a start. all data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. synchronous mode operations provide a high speed transfer capability. configuration fields and bits are the same as in asynchronous mode. figure 30-10 illustrates a character rec eption in synchronous mode. sampling clock (x16) rxd start detection sampling baud rate clock rxd start rejection sampling 12345678 12345670 1234 12345678 9 10111213141516 d0 sampling d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit stop bit example: 8-bit, parity enabled baud rate clock start detection 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples
536 11011a?atarm?04-oct-10 sam3n 536 11011a?atarm?04-oct-10 sam3n figure 30-10. synchronous mode character reception 30.7.3.4 receiver operations when a character reception is completed, it is transferred to the receive holding register (us_rhr) and the rxrdy bit in the status regist er (us_csr) rises. if a character is com- pleted while the rxrdy is set, the ovre (ove rrun error) bit is set. the last character is transferred into us_rhr and overwrites the previous one. the ovre bit is cleared by writing the control register (us_cr) with the rststa (reset status) bit to 1. figure 30-11. receiver status d0 d1 d2 d3 d4 d5 d6 d7 rxd start sampling parity bit stop bit example: 8-bit, parity enabled 1 stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr rxrdy ovre d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit rststa = 1 read us_rhr
537 11011a?atarm?04-oct-10 sam3n 537 11011a?atarm?04-oct-10 sam3n 30.7.3.5 parity the usart supports five parity modes selected by programming the par field in the mode register (us_mr). the par field also enables the multidrop mode, see ?multidrop mode? on page 538 . even and odd parity bit generation and error detection are supported. if even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a num- ber of 1s in the character data bit is even, and to 1 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sam- pled parity bit does not correspond. if odd parity is selected, the parity generator of the transmitter drives the parity bit to 1 if a number of 1s in the character data bit is even, and to 0 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. if the mark parity is used, the parity generator of the transmitter drives the parity bit to 1 for all characters. the receiver parity checker reports an error if the parity bit is sampled to 0. if the space parity is used, the parity generator of the transmitter drives the parity bit to 0 for all characters. the receiver parity checker reports an error if the parity bit is sampled to 1. if parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. table 30-9 shows an example of the parity bit for the character 0x41 (character ascii ?a?) depending on the configuration of the usart. because there are two bits to 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. when the receiver detects a parity error, it sets the pare (parity error) bit in the channel status register (us_csr). the pare bit can be cleared by writing the control register (us_cr) with the rststa bit to 1. figure 30-12 illustrates the parity bit status setting and clearing. table 30-9. parity bit examples character hexa binary parity bit parity mode a 0x41 0100 0001 1 odd a 0x41 0100 0001 0 even a 0x41 0100 0001 1 mark a 0x41 0100 0001 0 space a 0x41 0100 0001 none none
538 11011a?atarm?04-oct-10 sam3n 538 11011a?atarm?04-oct-10 sam3n figure 30-12. parity error 30.7.3.6 multidrop mode if the par field in the mode register (us_mr) is programmed to the value 0x6 or 0x07, the usart runs in multidrop mode. this mode differentiates the data characters and the address characters. data is transmitted with the parity bit to 0 and addresses are transmitted with the parity bit to 1. if the usart is configured in multidrop mode, the receiver sets the pare parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the control register is written with the senda bit to 1. to handle parity error, the pare bit is cleared when the control register is written with the bit rststa to 1. the transmitter sends an address byte (parity bit set) when senda is written to us_cr. in this case, the next byte written to us_thr is trans mitted as an address. any character written in us_thr without having written the command senda is transmitted normally with the parity to 0. 30.7.3.7 transmitter timeguard the timeguard feature enables the usar t interface with slow remote devices. the timeguard function enables the transmitter to insert an idle state on the txd line between two characters. this idle state actually acts as a long stop bit. the duration of the idle state is programmed in the tg field of the transmitter timeguard regis- ter (us_ttgr). when this field is programmed to zero no timeguard is generated. otherwise, the transmitter holds a high level on txd after each transmitted byte during the number of bit periods programmed in tg in addition to the number of stop bits. as illustrated in figure 30-13 , the behavior of txrdy and txempty status bits is modified by the programming of a timeguard. txrdy rises only when the start bit of the next character is sent, and thus remains to 0 during the timeguard transmission if a character has been written in us_thr. txempty remains low until the timeguard transmission is completed as the time- guard is part of the current character being transmitted. d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit bad parity bit stop bit baud rate clock write us_cr pare rxrdy rststa = 1
539 11011a?atarm?04-oct-10 sam3n 539 11011a?atarm?04-oct-10 sam3n figure 30-13. timeguard operations table 30-10 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the baud rate. 30.7.3.8 receiver time-out the receiver time-out provides support in handling variable-length frames. this feature detects an idle condition on the rxd line. when a time-out is detected, the bit timeout in the channel status register (us_csr) rises and can generate an interrupt, thus indicating to the driver an end of frame. the time-out delay period (during which the receiver waits for a new character) is programmed in the to field of the receiver time-out regist er (us_rtor). if the to field is programmed to 0, the receiver time-out is disabled and no time-out is detected. the timeout bit in us_csr remains to 0. otherwise, the receiver loads a 16-bit counter with the value programmed in to. this counter is decremented at each bit per iod and reloaded each time a new character is received. if the counter reaches 0, the timeout bit in the status register rises. then, the user can either: ? stop the counter clock until a new character is received. this is performed by writing the control register (us_cr) with the sttto (start time-out) bit to 1. in this case, the idle state d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit tg = 4 write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty tg = 4 table 30-10. maximum timeguard length depending on baud rate baud rate bit time timeguard bit/sec s ms 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21
540 11011a?atarm?04-oct-10 sam3n 540 11011a?atarm?04-oct-10 sam3n on rxd before a new character is received will not provide a time-out. this prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on rxd after a frame is received. ? obtain an interrupt while no character is rece ived. this is performed by writing us_cr with the retto (reload and start time-out) bit to 1. if retto is performed, the counter starts counting down immediately from the value to. this enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. if sttto is performed, the counter clock is stopped until a first character is received. the idle state on rxd before the start of the frame does not provide a time-out. this prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on rxd is detected. if retto is performed, the counter starts counting down immediately from the value to. this enables generation of a periodic interrupt so t hat a user time-out can be handled, for example when no key is pressed on a keyboard. figure 30-14 shows the block diagram of the receiver time-out feature. figure 30-14. receiver time-out block diagram table 30-11 gives the maximum time-out period for some standard baud rates. table 30-11. maximum time-out period baud rate bit time time-out bit/sec s ms 600 1 667 109 225 1 200 833 54 613 2 400 417 27 306 4 800 208 13 653 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 16-bit time-out counter 0 to timeout baud rate clock = character received retto load clock 16-bit value sttto dq 1 clear
541 11011a?atarm?04-oct-10 sam3n 541 11011a?atarm?04-oct-10 sam3n 30.7.3.9 framing error the receiver is capable of detecting framing errors. a framing error happens when the stop bit of a received character is detected at level 0. this can occur if the receiver and the transmitter are fully desynchronized. a framing error is reported on the frame bit of the channel status register (us_csr). the frame bit is asserted in the middle of the stop bit as soon as the framing error is detected. it is cleared by writing the control register (us_cr) with the rststa bit to 1. figure 30-15. framing error status 30.7.3.10 transmit break the user can request the transmitter to generate a break condition on the txd line. a break con- dition drives the txd line low during at least one complete character. it appears the same as a 0x00 character sent with the parity and the stop bits to 0. however, the transmitter holds the txd line at least during one character until the user requests the break condition to be removed. a break is transmitted by writing the control register (us_cr) with the sttbrk bit to 1. this can be performed at any time, either while the transmitter is empty (no character in either the shift register or in us_thr) or when a character is being transmitted. if a break is requested while a character is being shifted out, the charac ter is first completed before the txd line is held low. once sttbrk command is requested further sttbrk commands are ignored until the end of the break is completed. the break condition is removed by writing us_cr with the stpbrk bit to 1. if the stpbrk is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. 56000 18 1 170 57600 17 1 138 200000 5 328 table 30-11. maximum time-out period (continued) baud rate bit time time-out d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr frame rxrdy rststa = 1
542 11011a?atarm?04-oct-10 sam3n 542 11011a?atarm?04-oct-10 sam3n the transmitter considers the break as though it is a character, i.e. the sttbrk and stpbrk commands are taken into account only if the txrdy bit in us_csr is to 1 and the start of the break condition clears the txrdy and txempty bits as if a character is processed. writing us_cr with both sttbrk and stpbrk bits to 1 can lead to an unpredictable result. all stpbrk commands requested without a previous sttbrk command are ignored. a byte writ- ten into the transmit holding re gister while a break is pending, but not started, is ignored. after the break condition, the transmitter returns the txd line to 1 for a minimum of 12 bit times. thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. if the timeguard is programmed with a value higher than 12, the txd line is held high for the timeguard period. after holding the txd line for this period, the transmitter resumes normal operations. figure 30-16 illustrates the effect of both the start break (sttbrk ) and stop break (stpbrk) commands on the txd line. figure 30-16. break transmission 30.7.3.11 receive break the receiver detects a break condition when all data, parity and stop bits are low. this corre- sponds to detecting a framing error with data to 0x00, but frame remains low. when the low stop bit is detected, the receiver asserts the rxbrk bit in us_csr. this bit may be cleared by writing the control regi ster (us_cr) with the bit rststa to 1. an end of receive break is detected by a high leve l for at least 2/16 of a bit period in asynchro- nous operating mode or one sample at high level in synchronous operating mode. the end of break detection also asserts the rxbrk bit. 30.7.3.12 hardware handshaking the usart features a hardware handshaking out-of-band flow control. the rts and cts pins are used to connect with the remote device, as shown in figure 30-17 . d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock write us_cr txrdy txempty stpbrk = 1 sttbrk = 1 break transmission end of break
543 11011a?atarm?04-oct-10 sam3n 543 11011a?atarm?04-oct-10 sam3n figure 30-17. connection with a remote device for hardware handshaking setting the usart to operate with hardware handshaking is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x2. the usart behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the rts pin as described below and the level on the cts pin modifies the behavior of the transmitter as described below. using this mode requires usin g the pdc channel for reception. the transmitter can handle hardware handshaking in any case. figure 30-18 shows how the receiver operates if hardware handshaking is enabled. the rts pin is driven high if the receiver is disabled and if the status rxbuff (receive buffer full) com- ing from the pdc channel is high. normally, the remote device does not start transmitting while its cts pin (driven by rts) is high. as soon as the receiver is enabled , the rts falls, indicating to the remote device that it can start transmitt ing. defining a new buffer to the pdc clears the status bit rxbuff and, as a result, asserts the pin rts low. figure 30-18. receiver behavior when operating with hardware handshaking figure 30-19 shows how the transmitter operates if hardware handshaking is enabled. the cts pin disables the transmitt er. if a character is being processi ng, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin cts falls. figure 30-19. transmitter behavior when operating with hardware handshaking usart txd cts remote device rxd txd rxd rts rts cts rts rxbuff write us_cr rxen = 1 rxd rxdis = 1 cts txd
544 11011a?atarm?04-oct-10 sam3n 544 11011a?atarm?04-oct-10 sam3n 30.7.4 iso7816 mode the usart features an iso7816-compatible operating mode. this mode permits interfacing with smart cards and security access modules (sam) communicating through an iso7816 link. both t = 0 and t = 1 protocols defined by the iso7816 specification are supported. setting the usart in iso7816 mode is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x4 for protoc ol t = 0 and to the value 0x5 for protocol t = 1. 30.7.4.1 iso7816 mode overview the iso7816 is a half duplex communication on only one bidirectional line. the baud rate is determined by a division of the clo ck provided to the remote device (see ?baud rate generator? on page 529 ). the usart connects to a smart card as shown in figure 30-20 . the txd line becomes bidirec- tional and the baud rate generator feeds the iso7816 clock on the sck pin. as the txd pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is direct ed to the input of the receiver. the usart is con- sidered as the master of the communication as it generates the clock. figure 30-20. connection of a smart card to the usart when operating in iso7816, either in t = 0 or t = 1 modes, the character format is fixed. the configuration is 8 data bits, ev en parity and 1 or 2 stop bits, regardless of the values pro- grammed in the chrl, mode9, par and chmode fields. msbf can be used to transmit lsb or msb first. parity bit (par) can be used to transmit in normal or inverse mode. refer to ?usart mode register? on page 561 and ?par: parity type? on page 562 . the usart cannot operate concurrently in both receiver and transmitter modes as the commu- nication is unidirectional at a time. it has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. enabling both the receiver and the transmitter at the same time in iso7816 mode may lead to unpredictable results. the iso7816 specification defines an inverse transmission format. data bits of the character must be transmitted on the i/o line at their negative value. the usart does not support this for- mat and the user has to perform an exclusive or on the data before writing it in the transmit holding register (us_thr) or after reading it in the receive holding register (us_rhr). 30.7.4.2 protocol t = 0 in t = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. the transmitter shifts out the bits and does not drive the i/o line during the guard time. if no parity error is detected, the i/o line remains to 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in figure 30-21 . smart card sck clk txd i/o usart
545 11011a?atarm?04-oct-10 sam3n 545 11011a?atarm?04-oct-10 sam3n if a parity error is detected by the receiver, it drives the i/o line to 0 during the guard time, as shown in figure 30-22 . this error bit is also named nack, for non acknowledge. in this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. when the usart is the receiver and it detects an error, it does not load the erroneous character in the receive holding register (us_rhr). it appropriately sets the pare bit in the status reg- ister (us_sr) so that the software can handle the error. figure 30-21. t = 0 protocol without parity error figure 30-22. t = 0 protocol with parity error receive error counter the usart receiver also records the total number of errors. this can be read in the number of error (us_ner) register. the nb_errors field can record up to 255 errors. reading us_ner automatically clears the nb_errors field. receive nack inhibit the usart can also be configured to inhibit an error. this can be achieved by setting the inack bit in the mode register (us_mr). if inack is to 1, no error signal is driven on the i/o line even if a parity bit is detected. moreover, if inack is set, the erroneous receiv ed character is stored in the receive holding register, as if no error occurred and the rxrdy bit does rise. transmit character repetition when the usart is transmitting a character and gets a nack, it can automatically repeat the character before moving on to the next one. repetition is enabled by writing the max_iteration field in the mode register (us_mr) at a value higher than 0. each character can be transmitted up to eight times; the first transmission plus seven repetitions. if max_iteration does not equal zero, the u sart repeats the character as many times as the value loaded in max_iteration. d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit baud rate clock start bit guard time 1 next start bit guard time 2 d0 d1 d2 d3 d4 d5 d6 d7 i/o parity bit baud rate clock start bit guard time 1 start bit guard time 2 d0 d1 error repetition
546 11011a?atarm?04-oct-10 sam3n 546 11011a?atarm?04-oct-10 sam3n when the usart repetition number reaches max_iteration, the iteration bit is set in the channel status register (us_csr). if the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. the iteration bit in us_csr can be cleared by writing the control register with the rsit bit to 1. disable successive receive nack the receiver can limit the number of successive nacks sent back to the remote transmitter. this is programmed by setting the bit dsnack in the mode register (us_mr). the maximum number of nack transmitted is programmed in the max_iteration field. as soon as max_iteration is reached, the character is cons idered as correct, an acknowledge is sent on the line and the iteration bit in the channel status register is set. 30.7.4.3 protocol t = 1 when operating in iso7816 protocol t = 1, the transmission is similar to an asynchronous for- mat with only one stop bit. the parity is generated when transmitting and checked when receiving. parity error detection sets the pare bit in the channel status register (us_csr). 30.7.5 irda mode the usart features an irda mode supplying half-duplex point-to-point wireless communica- tion. it embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in figure 30-23 . the modulator and demodulator are compliant with the irda specification version 1.1 and support data transfer speeds ranging from 2.4 kb/s to 115.2 kb/s. the usart irda mode is enabled by setting t he usart_mode field in the mode register (us_mr) to the value 0x8. the irda filter register (us_if) allows configuring the demodulator filter. the usart transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. note that the modulator and the demodulator are activated. figure 30-23. connection to irda transceivers the receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. to receive irda signals, the following needs to be done: ? disable tx and enable rx irda transceivers rxd rx txd tx usart demodulator modulator receiver transmitter
547 11011a?atarm?04-oct-10 sam3n 547 11011a?atarm?04-oct-10 sam3n ? configure the txd pin as pio and set it as an output to 0 (to avoid led emission). disable the internal pull-up (better for power consumption). ? receive data 30.7.5.1 irda modulation for baud rates up to and including 115.2 kbits/sec, the rzi modulation scheme is used. ?0? is represented by a light pulse of 3/16th of a bit time. some examples of signal pulse duration are shown in table 30-12 . figure 30-24 shows an example of character transmission. figure 30-24. irda modulation 30.7.5.2 irda baud rate table 30-13 gives some examples of cd values, baud rate error and pulse duration. note that the requirement on the maximum acceptable error of 1.87% must be met. table 30-12. irda pulse duration baud rate pulse duration (3/16) 2.4 kb/s 78.13 s 9.6 kb/s 19.53 s 19.2 kb/s 9.77 s 38.4 kb/s 4.88 s 57.6 kb/s 3.26 s 115.2 kb/s 1.63 s bit period bit period 3 16 start bit data bits stop bit 0 0 0 0 0 1 1 1 1 1 transmitter output txd table 30-13. irda baud rate error peripheral clock baud rate cd baud rate error pulse time 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.63 32 768 000 115 200 18 1.25% 1.63 40 000 000 115 200 22 1.38% 1.63 3 686 400 57 600 4 0.00% 3.26 20 000 000 57 600 22 1.38% 3.26 32 768 000 57 600 36 1.25% 3.26
548 11011a?atarm?04-oct-10 sam3n 548 11011a?atarm?04-oct-10 sam3n 30.7.5.3 irda demodulator the demodulator is based on the irda receive filter co mprised of an 8-bit down counter which is loaded with the value programmed in us_if. when a falling edge is detected on the rxd pin, the filter counter starts counting down at the master clock (mck) speed. if a rising edge is detected on the rxd pin, the counter stops and is reloaded with us_if. if no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. figure 30-25 illustrates the operations of the irda demodulator. figure 30-25. irda demodulator operations as the irda mode uses the same logic as the iso7816, note that the fi_di_ratio field in us_fidi must be set to a value higher than 0 in order to assure irda communications operate correctly. 40 000 000 57 600 43 0.93% 3.26 3 686 400 38 400 6 0.00% 4.88 20 000 000 38 400 33 1.38% 4.88 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.53 32 768 000 9 600 213 0.16% 19.53 40 000 000 9 600 260 0.16% 19.53 3 686 400 2 400 96 0.00% 78.13 20 000 000 2 400 521 0.03% 78.13 32 768 000 2 400 853 0.04% 78.13 table 30-13. irda baud rate error (continued) peripheral clock baud rate cd baud rate error pulse time mck rxd receiver input pulse rejected 65432 6 1 65432 0 pulse accepted counter value
549 11011a?atarm?04-oct-10 sam3n 549 11011a?atarm?04-oct-10 sam3n 30.7.6 rs485 mode the usart features the rs485 mode to enable li ne driver control. while operating in rs485 mode, the usart behaves as though in asynch ronous or synchronous mode and configuration of all the parameters is possible. the differenc e is that the rts pin is driven high when the transmitter is operating. the behavior of the rts pin is controlled by the txempty bit. a typical connection of the usart to a rs485 bus is shown in figure 30-26 . figure 30-26. typical connection to a rs485 bus the usart is set in rs485 mode by programming the usart_mode field in the mode regis- ter (us_mr) to the value 0x1. the rts pin is at a level inverse to the txempt y bit. significantly, the rts pin remains high when a timeguard is programmed so that the line can remain driven after the last character com- pletion. figure 30-27 gives an example of the rts waveform during a character transmission when the timeguard is enabled. figure 30-27. example of rts drive with timeguard usart rts txd rxd differential bus d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock tg = 4 write us_thr txrdy txempty rts
550 11011a?atarm?04-oct-10 sam3n 550 11011a?atarm?04-oct-10 sam3n 30.7.7 spi mode the serial peripheral interface (spi) mode is a synchronous serial data link that provides com- munication with external devices in master or slave mode. it also enables communication between processors if an external processor is connected to the system. the serial peripheral interface is essentially a shift register that serially transmits data bits to other spis. during a data transfer, one spi system acts as the ?master? which controls the data flow, while the other devices act as ?slaves'' whic h have data shifted into and out by the master. different cpus can take turns being masters and one master may simultaneously shift data into multiple slaves. (multiple master protocol is the opposite of single master protocol, where one cpu is always the master while all of the others are always slaves.) however, only one slave may drive its output to write data back to the master at any given time. a slave device is selected when its nss signal is asserted by the master. the usart in spi master mode can address only one spi slave because it can generate only one nss signal. the spi system consists of two data lines and two control lines: ? master out slave in (mosi): this data line supplies the output data from the master shifted into the input of the slave. ? master in slave out (miso): this data line supplies the output data from a slave to the input of the master. ? serial clock (sck): this control line is driven by the master and regulates the flow of the data bits. the master may transmit data at a variety of baud rates. the sck line cycles once for each bit that is transmitted. ? slave select (nss): this control line allows the master to select or deselect the slave. 30.7.7.1 modes of operation the usart can operate in spi master mode or in spi slave mode. operation in spi master mode is programmed by writing to 0xe the usart_mode field in the mode register. in this case the spi lines must be connected as described below: ? the mosi line is driven by the output pin txd ? the miso line drives the input pin rxd ? the sck line is driven by the output pin sck ? the nss line is driven by the output pin rts operation in spi slave mode is programmed by writing to 0xf the usart_mode field in the mode register. in this case the spi lines must be connected as described below: ? the mosi line drives the input pin rxd ? the miso line is driven by the output pin txd ? the sck line drives the input pin sck ? the nss line drives the input pin cts in order to avoid unpredicted behavior, any change of the spi mode must be followed by a soft- ware reset of the transmitter and of the receiver (except the initial configuration after a hardware reset). (see section 30.7.7.4 ). 30.7.7.2 baud rate in spi mode, the baudrate generator operates in the same way as in usart synchronous mode: see ?baud rate in synchronous mode or spi mode? on page 531. however, there are some restrictions:
551 11011a?atarm?04-oct-10 sam3n 551 11011a?atarm?04-oct-10 sam3n in spi master mode: ? the external clock sck must not be selected (usclks 0x3), and the bit clko must be set to ?1? in the mode register (us_mr), in order to generate correctly the serial clock on the sck pin. ? to obtain correct behavior of the receiver and the transmitter, the value programmed in cd must be superior or equal to 6. ? if the internal clock divided (mck/div) is selected, the value programmed in cd must be even to ensure a 50:50 mark/space ratio on the sck pin, this value can be odd if the internal clock is selected (mck). in spi slave mode: ? the external clock (sck) selection is forced regardless of the value of the usclks field in the mode register (us_mr). likewise, the value written in us_brgr has no effect, because the clock is provided directly by the signal on the usart sck pin. ? to obtain correct behavior of the receiver and the transmitter, the external clock (sck) frequency must be at least 6 times lower than the system clock.
552 11011a?atarm?04-oct-10 sam3n 552 11011a?atarm?04-oct-10 sam3n 30.7.7.3 data transfer up to 9 data bits are successively shifted out on the txd pin at each rising or falling edge (depending of cpol and cpha) of the programmed serial clock. there is no start bit, no parity bit and no stop bit. the number of data bits is selected by the chrl field and the mode 9 bit in the mode register (us_mr). the 9 bits are selected by setting the mode 9 bit regardless of the chrl field. the msb data bit is always sent first in spi mode (master or slave). four combinations of polarity and phase are available for data transfers. the clock polarity is programmed with the cpol bit in the mode regi ster. the clock phase is programmed with the cpha bit. these two parameters determine the edges of the clock signal upon which data is driven and sampled. each of the two parameters has two possible states, resulting in four possi- ble combinations that are incompatible with one another. thus, a master/slave pair must use the same parameter pair values to communicate. if multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a dif- ferent slave. table 30-14. spi bus protocol mode spi bus protocol mode cpol cpha 001 100 211 310
553 11011a?atarm?04-oct-10 sam3n 553 11011a?atarm?04-oct-10 sam3n figure 30-28. spi transfer format (cpha=1, 8 bits per transfer) figure 30-29. spi transfer format (cpha=0, 8 bits per transfer) 30.7.7.4 receiver and transmitter control see ?receiver and transmitter control? on page 533. 6 sck (cpol = 0) sck (cpol = 1) mosi spi master ->txd spi slave -> rxd nss spi master -> rts spi slave -> cts sck cycle (for reference) msb msb lsb lsb 6 6 5 5 4 4 3 3 2 2 1 1 1 2345 78 6 miso spi master ->rxd spi slave -> txd sck (cpol = 0) sck (cpol = 1) 1 2345 7 mosi spi master -> txd spi slave -> rxd miso spi master -> rxd spi slave -> txd nss spi master -> rts spi slave -> cts sck cycle (for reference) 8 msb msb lsb lsb 6 6 5 5 4 4 3 3 1 1 2 2 6
554 11011a?atarm?04-oct-10 sam3n 554 11011a?atarm?04-oct-10 sam3n 30.7.7.5 character transmission the characters are sent by writing in the tran smit holding register (us_thr). an additional condition for transmitting a character can be ad ded when the usart is configured in spi mas- ter mode. in the usart_mr register, the va lue configured on inack field can prevent any character transmission (even if us_thr has been written) while the receiver side is not ready (character not read). when inack equals 0, the c haracter is transmitted whatever the receiver status. if inack is set to 1, the transmitter waits for the receiver holding register to be read before transmitting the character (rxrdy flag cl eared), thus preventing any overflow (character loss) on the receiver side. the transmitter reports two status bits in the channel status register (us_csr): txrdy (transmitter ready), which indicates that us_thr is empty and txempty, which indicates that all the characters written in us_thr have been processed. when the current character pro- cessing is completed, the last ch aracter written in us_thr is transferred into the shift register of the transmitter and us_thr becomes empty, thus txrdy rises. both txrdy and txempty bits are low when the transmitter is disabled. writing a character in us_thr while txrdy is low has no effect and the written character is lost. if the usart is in spi slave mode and if a character must be sent while the transmit holding register (us_thr) is empty, the unre (underru n error) bit is set. the txd transmission line stays at high level during all th is time. the unre bit is cleared by writing the control register (us_cr) with the rststa (reset status) bit to 1. in spi master mode, the slave select line (nss) is asserted at low level 1 tbit (time bit) before the transmission of the msb bit and released at high level 1 tbit after the transmission of the lsb bit. so, the slave select line (nss) is always released between each character transmission and a minimum delay of 3 tbits always inserted . however, in order to address slave devices supporting the csaat mode (chip select active after transfer), the slave select line (nss) can be forced at low level by writing the control register (us_cr) with the rtsen bit to 1. the slave select line (nss) can be released at high level only by writing the control register (us_cr) with the rtsdis bit to 1 (for example, when all data have been transferred to the slave device). in spi slave mode, the transmitter does not require a falling edge of the slave select line (nss) to initiate a character transmission but only a low level. however, this lo w level must be present on the slave select line (nss) at least 1 tbit before the first serial clock cycle corresponding to the msb bit. 30.7.7.6 character reception when a character reception is completed, it is transferred to the receive holding register (us_rhr) and the rxrdy bit in the status regist er (us_csr) rises. if a character is com- pleted while rxrdy is set, the ovre (overrun erro r) bit is set. the last character is transferred into us_rhr and overwrites the pr evious one. the ovre bit is cleared by writing the control register (us_cr) with the rststa (reset status) bit to 1. to ensure correct behavior of the receiver in spi slave mode, the master device sending the frame must ensure a minimum delay of 1 tb it between each character transmission. the receiver does not require a falling edge of the slave select line (nss) to initiate a character reception but only a low level. however, this low level must be present on the slave select line (nss) at least 1 tbit before the first serial clock cycle corresponding to the msb bit.
555 11011a?atarm?04-oct-10 sam3n 555 11011a?atarm?04-oct-10 sam3n 30.7.7.7 receiver timeout because the receiver baudrate clock is active only during data transfers in spi mode, a receiver timeout is impossible in this mode, whatever the time-out value is (field to) in the time-out register (us_rtor). 30.7.8 test modes the usart can be programmed to operate in three different test modes. the internal loopback capability allows on-boar d diagnostics. in the loopback mode the usart interface pins are dis- connected or not and reconfigured for loopback internally or externally. 30.7.8.1 normal mode normal mode connects the rxd pin on the receiver input and the transmitter output on the txd pin. figure 30-30. normal mode configuration 30.7.8.2 automatic echo mode automatic echo mode allows bit-by-bit retransmission. when a bit is received on the rxd pin, it is sent to the txd pin, as shown in figure 30-31 . programming the transmitter has no effect on the txd pin. the rxd pin is still connected to the receiver input, thus the receiver remains active. figure 30-31. automatic echo mode configuration | | | | | | | | data 0 data n rxrdy usart3 lin controller apb bus read buffer nact = subscribe data 0 data n txrdy usart3 lin controller apb bus write buffer (peripheral) dma controller (peripheral) dma controller receiver transmitter rxd txd receiver transmitter rxd txd
556 11011a?atarm?04-oct-10 sam3n 556 11011a?atarm?04-oct-10 sam3n 30.7.8.3 local loopback mode local loopback mode c onnects the output of the transmitter directly to the input of the receiver, as shown in figure 30-32 . the txd and rxd pins are not used. the rxd pin has no effect on the receiver and the txd pin is continuously driven high, as in idle state. figure 30-32. local loopback mode configuration 30.7.8.4 remote loopback mode remote loopback mode directly connects the rxd pin to the txd pin, as shown in figure 30-33 . the transmitter and the receiver are disabled an d have no effect. this mode allows bit-by-bit retransmission. figure 30-33. remote loopback mode configuration 30.7.9 write protection registers to prevent any single software error that may corrupt usart behavior, certain address spaces can be write-protected by setting the wpen bit in the usart write protect mode register (us_wpmr). if a write access to the protected registers is detected, then the wpvs flag in the usart write protect status register (us_wpsr) is set and the field wpvsr c indicates in which r egister the write access has been attempted. the wpvs flag is reset by writing the usart write protec t mode register (us_wpmr) with the appropriate access key, wpkey. the protected registers are: ? ?usart mode register? ? ?usart baud rate generator register? ? ?usart receiver time-out register? ? ?usart transmitter timeguard register? ? ?usart fi di ratio register? ? ?usart irda filter register? receiver transmitter rxd txd 1 receiver transmitter rxd txd 1
557 11011a?atarm?04-oct-10 sam3n 557 11011a?atarm?04-oct-10 sam3n 30.8 universal synchronous async hronous receiver transmitter (usart) user interface table 30-15. register mapping offset register name access reset 0x0000 control register us_cr write-only ? 0x0004 mode register us_mr read-write ? 0x0008 interrupt enable register us_ier write-only ? 0x000c interrupt disable register us_idr write-only ? 0x0010 interrupt mask register us_imr read-only 0x0 0x0014 channel status register us_csr read-only ? 0x0018 receiver holding register us_rhr read-only 0x0 0x001c transmitter holding register us_thr write-only ? 0x0020 baud rate generator register us_brgr read-write 0x0 0x0024 receiver time-out register us_rtor read-write 0x0 0x0028 transmitter timeguard register us_ttgr read-write 0x0 0x2c - 0x3c reserved ? ? ? 0x0040 fi di ratio regist er us_fidi read-write 0x174 0x0044 number of errors register us_ner read-only ? 0x0048 reserved ? ? ? 0x004c irda filter regi ster us_if read-write 0x0 0xe4 write protect mode register us_wpmr read-write 0x0 0xe8 write protect status register us_wpsr read-only 0x0 0x5c - 0xfc reserved ? ? ? 0x100 - 0x128 reserved for pdc registers ? ? ?
558 11011a?atarm?04-oct-10 sam3n 558 11011a?atarm?04-oct-10 sam3n 30.8.1 usart control register name: us_cr addresses: 0x40024000 (0), 0x40028000 (1) access: write-only ? rstrx: reset receiver 0: no effect. 1: resets the receiver. ? rsttx: reset transmitter 0: no effect. 1: resets the transmitter. ? rxen: receiver enable 0: no effect. 1: enables the receiver, if rxdis is 0. ? rxdis: receiver disable 0: no effect. 1: disables the receiver. ? txen: transmitter enable 0: no effect. 1: enables the transmitter if txdis is 0. ? txdis: transmitter disable 0: no effect. 1: disables the transmitter. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rtsdis/rcsrtsen/fcs?? 15 14 13 12 11 10 9 8 retto rstnack rstit senda sttto stpbrk sttbrk rststa 76543210 txdis txen rxdis rxen rsttx rstrx ? ?
559 11011a?atarm?04-oct-10 sam3n 559 11011a?atarm?04-oct-10 sam3n ? rststa: reset status bits 0: no effect. 1: resets the status bits pare, frame, ovre, unre and rxbrk in us_csr. ? sttbrk: start break 0: no effect. 1: starts transmission of a break after the characters present in us_thr and the transmit shi ft register have been trans- mitted. no effect if a break is already being transmitted. ? stpbrk: stop break 0: no effect. 1: stops transmission of the break after a minimum of one char acter length and transmits a high level during 12-bit periods. no effect if no break is being transmitted. ? sttto: start time-out 0: no effect. 1: starts waiting for a character before clocking the time-out counter. resets the status bit timeout in us_csr. ? senda: send address 0: no effect. 1: in multidrop mode only, the next character written to the us_thr is sent with the address bit set. ? rstit: reset iterations 0: no effect. 1: resets iteration in us_csr. no e ffect if the iso7816 is not enabled. ? rstnack: reset non acknowledge 0: no effect 1: resets nack in us_csr. ? retto: rearm time-out 0: no effect 1: restart time-out ? rtsen: request to send enable 0: no effect. 1: drives the pin rts to 0. ? fcs: force spi chip select ? applicable if usart operates in spi master mode (usart_mode = 0xe): fcs = 0: no effect. fcs = 1: forces the slave select line nss (rts pin) to 0, ev en if usart is no transmitting, in order to address spi slave devices supporting the csaat mode (chip select active after transfer).
560 11011a?atarm?04-oct-10 sam3n 560 11011a?atarm?04-oct-10 sam3n ? rtsdis: request to send disable 0: no effect. 1: drives the pin rts to 1. ? rcs: release spi chip select ? applicable if usart operates in spi master mode (usart_mode = 0xe): rcs = 0: no effect. rcs = 1: releases the slave select line nss (rts pin).
561 11011a?atarm?04-oct-10 sam3n 561 11011a?atarm?04-oct-10 sam3n 30.8.2 usart mode register name: us_mr addresses: 0x40024004 (0), 0x40028004 (1) access: read-write this register can only be written if the wpen bit is cleared in ?usart write protect mode register? on page 577 . ? usart_mode ? usclks: clock selection ? chrl: character length. 31 30 29 28 27 26 25 24 ? ? ? filter ? max_iteration 23 22 21 20 19 18 17 16 invdata ? dsnack inack over clko mode9 msbf/cpol 15 14 13 12 11 10 9 8 chmode nbstop par sync/cpha 76543210 chrl usclks usart_mode value name description 0x0 normal normal mode 0x1 rs485 rs485 0x2 hw_handshaking hardware handshaking 0x4 is07816_t_0 is07816 protocol: t = 0 0x6 is07816_t_1 is07816 protocol: t = 1 0x8 irda irda 0xe spi_master spi master 0xf spi_slave spi slave value name description 0 mck master clock mck is selected 1 div internal clock divided mck/div (div= 8 ) is selected 3 sck serial clock slk is selected value name description 0 5_bit character length is 5 bits 1 6_bit character length is 6 bits 2 7_bit character length is 7 bits 3 8_bit character length is 8 bits
562 11011a?atarm?04-oct-10 sam3n 562 11011a?atarm?04-oct-10 sam3n ? sync: synchronous mode select 0: usart operates in asynchronous mode. 1: usart operates in synchronous mode. ? cpha: spi clock phase ? applicable if usart operates in spi mode (usart_mode = 0xe or 0xf): cpha = 0: data is changed on the leading edge of spck and captured on the following edge of spck. cpha = 1: data is captured on the leading edge of spck and changed on the following edge of spck. cpha determines which edge of spck causes data to change and which edge causes data to be captured. cpha is used with cpol to produce the required clock/data relationship between master and slave devices. ? par: parity type ? nbstop: number of stop bits ? chmode: channel mode ? msbf: bit order 0: least significant bit is sent/received first. 1: most significant bit is sent/received first. ? cpol: spi clock polarity ? applicable if usart operates in spi mode (s lave or master, usart_mode = 0xe or 0xf): cpol = 0: the inactive state va lue of spck is logic level zero. cpol = 1: the inactive state value of spck is logic level one. value name description 0 even even parity 1 odd odd parity 2 space parity forced to 0 (space) 3 mark parity forced to 1 (mark) 4 no no parity 6 multidrop multidrop mode value name description 0 1_bit 1 stop bit 1 1_5_bit 1.5 stop bit (sync = 0) or reserved (sync = 1) 2 2_bit 2 stop bits value name description 0 normal normal mode 1 automatic automatic echo. receiver input is connected to the txd pin. 2 local_loopback local loopback. transmitter outp ut is connected to the receiver input. 3 remote_loopback remote loopback. rxd pin is internally connected to the txd pin.
563 11011a?atarm?04-oct-10 sam3n 563 11011a?atarm?04-oct-10 sam3n cpol is used to determine the inactive state value of the se rial clock (spck). it is used with cpha to produce the required clock/data relationship between master and slave devices. ? mode9: 9-bit character length 0: chrl defines character length. 1: 9-bit character length. ? clko: clock output select 0: the usart does not drive the sck pin. 1: the usart drives the sck pin if usclks does not select the external clock sck. ? over: oversampling mode 0: 16x oversampling. 1: 8x oversampling. ? inack: inhibit non acknowledge 0: the nack is generated. 1: the nack is not generated. note: in spi master mode, if inack = 0 the character transmi ssion starts as soon as a character is written into us_thr register (assuming txrdy was set). when inack is 1, an additional condition must be met. the character transmission starts when a character is written and only if rxrdy flag is cleared (receiver holding register has been read). ? dsnack: disable successive nack 0: nack is sent on the iso line as soon as a parity erro r occurs in the received character (unless inack is set). 1: successive parity errors are counted up to the value spec ified in the max_iteration field. these parity errors gener- ate a nack on the iso line. as soon as this value is r eached, no additional nack is sent on the iso line. the flag iteration is asserted. ?invdata: inverted data 0: the data field transmitted on txd line is the same as the one written in us_thr register or the content read in us_rhr is the same as rxd line. normal mode of operation. 1: the data field transmitted on txd line is inverted (voltage polarity only) compared to the value written on us_thr regis- ter or the content read in us_rhr is inverted compared to what is received on rxd line (or iso7816 io line). inverted mode of operation, useful for contactless card application. to be used with configuration bit msbf. ? max_iteration defines the maximum number of iterations in mode iso7816, protocol t= 0. ? filter: infrared receive line filter 0: the usart does not filter the receive line. 1: the usart filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).
564 11011a?atarm?04-oct-10 sam3n 564 11011a?atarm?04-oct-10 sam3n 30.8.3 usart interrupt enable register name: us_ier addresses: 0x40024008 (0), 0x40028008 (1) access: write-only 0: no effect 1: enables the corresponding interrupt. ? rxrdy: rxrdy interrupt enable ? txrdy: txrdy interrupt enable ? rxbrk: receiver break interrupt enable ? endrx: end of receive transfer interrupt enable ? endtx: end of transmit interrupt enable ? ovre: overrun error interrupt enable ? frame: framing error interrupt enable ? pare: parity error interrupt enable ? timeout: time-out interrupt enable ? txempty: txempty interrupt enable ? iter: max number of repetitions reached ? unre: spi underrun error ? txbufe: buffer empty interrupt enable ? rxbuff: buffer full interrupt enable ? nack: non acknowledgeinterrupt enable ? ctsic: clear to send input change interrupt enable 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????ctsic ? ? ? 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iter/unre txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
565 11011a?atarm?04-oct-10 sam3n 565 11011a?atarm?04-oct-10 sam3n 30.8.4 usart interrupt disable register name: us_idr addresses: 0x4002400c (0), 0x4002800c (1) access: write-only 0: no effect 1: disables the corresponding interrupt. ? rxrdy: rxrdy interrupt disable ? txrdy: txrdy interrupt disable ? rxbrk: receiver bre ak interrupt disable ? endrx: end of receive transfer interrupt disable ? endtx: end of transmit interrupt disable ? ovre: overrun error interrupt disable ? frame: framing error interrupt disable ? pare: parity error interrupt disable ? timeout: time-out interrupt disable ? txempty: txempty interrupt disable ? iter: max number of repetitions reached disable ? unre: spi underrun error disable ? txbufe: buffer empty interrupt disable ? rxbuff: buffer full interrupt disable ? nack: non acknowledgeinterrupt disable ? ctsic: clear to send input change interrupt disable 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????ctsic ? ? ? 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iter/unre txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
566 11011a?atarm?04-oct-10 sam3n 566 11011a?atarm?04-oct-10 sam3n 30.8.5 usart interrupt mask register name: us_imr addresses: 0x40024010 (0), 0x40028010 (1) access: read-only 0: the corresponding interrupt is not enabled. 1: the corresponding interrupt is enabled. ? rxrdy: rxrdy interrupt mask ? txrdy: txrdy interrupt mask ? rxbrk: receiver break interrupt mask ? endrx: end of receive transfer interrupt mask ? endtx: end of transmit interrupt mask ? ovre: overrun error interrupt mask ? frame: framing error interrupt mask ? pare: parity error interrupt mask ? timeout: time-out interrupt mask ? txempty: txempty interrupt mask ? iter: max number of repetitions reached mask ? unre: spi underrun error mask ? txbufe: buffer empty interrupt mask ? rxbuff: buffer full interrupt mask ? nack: non acknowledgeinterrupt mask ? ctsic: clear to send input change interrupt mask 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????ctsic ? ? ? 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iter/unre txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
567 11011a?atarm?04-oct-10 sam3n 567 11011a?atarm?04-oct-10 sam3n 30.8.6 usart channel status register name: us_csr addresses: 0x40024014 (0), 0x40028014 (1) access: read-only ? rxrdy: receiver ready 0: no complete character has been received since the last read of us_rhr or the receiver is disabled. if characters were being received when the receiver was disabled, rx rdy changes to 1 when the receiver is enabled. 1: at least one complete char acter has been rece ived and us_rhr has not yet been read. ? txrdy: transmitter ready 0: a character is in the us_thr waiting to be transferred to the transmit shift register, or an sttbrk command has been requested, or the transmitter is disabled. as soon as the transmitter is enabled, txrdy becomes 1. 1: there is no char acter in the us_thr. ? rxbrk: break received/end of break 0: no break received or end of break detected since the last rststa. 1: break received or end of break detected since the last rststa. ? endrx: end of receiver transfer 0: the end of transfer signal from the receive pdc channel is inactive. 1: the end of transfer signal from the receive pdc channel is active. ? endtx: end of transmitter transfer 0: the end of transfer signal from the transmit pdc channel is inactive. 1: the end of transfer signal from the transmit pdc channel is active. ? ovre: overrun error 0: no overrun error has occurred since the last rststa. 1: at least one overrun error has occurred since the last rststa. ? frame: framing error 0: no stop bit has been detected low since the last rststa. 1: at least one stop bit has been detected low since the last rststa. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 cts ? ? ? ctsic ? ? ? 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iter/unre txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
568 11011a?atarm?04-oct-10 sam3n 568 11011a?atarm?04-oct-10 sam3n ? pare: parity error 0: no parity error has been detected since the last rststa. 1: at least one parity error has been detected since the last rststa. ? timeout: receiver time-out 0: there has not been a time-out since t he last start time-out command (sttto in us_cr) or the time-out register is 0. 1: there has been a time-out since the last start time-out command (sttto in us_cr). ? txempty: transmitter empty 0: there are characters in either us_thr or the tr ansmit shift register, or the transmitter is disabled. 1: there are no characters in us_thr, nor in the transmit shift register. ? iter: max number of repetitions reached 0: maximum number of repetitions has not been reached since the last rststa. 1: maximum number of repetitions has been reached since the last rststa. ? unre: spi underrun error ? applicable if usart operates in spi slave mode (usart_mode = 0xf): unre = 0: no spi underrun error has occurred since the last rststa. unre = 1: at least one spi underrun error has occurred since the last rststa. ? txbufe: transmission buffer empty 0: the signal buffer empty from the transmit pdc channel is inactive. 1: the signal buffer empty from the transmit pdc channel is active. ? rxbuff: reception buffer full 0: the signal buffer full from the receive pdc channel is inactive. 1: the signal buffer full from th e receive pdc channel is active. ? nack: non acknowledgeinterrupt 0: non acknowledge has not been detected since the last rstnack. 1: at least one non acknowledge has been detected since the last rstnack. ? ctsic: clear to send input change flag 0: no input change has been detected on the cts pin since the last read of us_csr. 1: at least one input change has been detected on the cts pin since the last read of us_csr. ? cts: image of cts input 0: cts is set to 0. 1: cts is set to 1.
569 11011a?atarm?04-oct-10 sam3n 569 11011a?atarm?04-oct-10 sam3n 30.8.7 usart receive holding register name: us_rhr addresses: 0x40024018 (0), 0x40028018 (1) access: read-only ? rxchr: received character last character received if rxrdy is set. ? rxsynh: received sync 0: last character received is a data. 1: last character received is a command. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rxsynh ??????rxchr 76543210 rxchr
570 11011a?atarm?04-oct-10 sam3n 570 11011a?atarm?04-oct-10 sam3n 30.8.8 usart transmit holding register name: us_thr addresses: 0x4002401c (0), 0x4002801c (1) access: write-only ? txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. ? txsynh: sync field to be transmitted 0: the next character sent is encoded as a data. start frame delimiter is data sync. 1: the next character sent is encoded as a command. start frame delimiter is command sync. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txsynh ??????txchr 76543210 txchr
571 11011a?atarm?04-oct-10 sam3n 571 11011a?atarm?04-oct-10 sam3n 30.8.9 usart baud rate generator register name: us_brgr addresses: 0x40024020 (0), 0x40028020 (1) access: read-write this register can only be written if the wpen bit is cleared in ?usart write protect mode register? on page 577 . ? cd: clock divider ? fp: fractional part 0: fractional divider is disabled. 1 - 7: baudrate resolution, defined by fp x 1/8. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????? fp 15 14 13 12 11 10 9 8 cd 76543210 cd cd usart_mode iso7816 usart_mode = iso7816 sync = 0 sync = 1 or usart_mode = spi (master or slave) over = 0 over = 1 0 baud rate clock disabled 1 to 65535 baud rate = selected clock/(16*cd) baud rate = selected clock/(8*cd) baud rate = selected clock /cd baud rate = selected clock/(fi_di_ratio*cd)
572 11011a?atarm?04-oct-10 sam3n 572 11011a?atarm?04-oct-10 sam3n 30.8.10 usart receiver time-out register name: us_rtor addresses: 0x40024024 (0), 0x40028024 (1) access: read-write this register can only be written if the wpen bit is cleared in ?usart write protect mode register? on page 577 . ? to: time-out value 0: the receiver time-out is disabled. 1 - 65535: the receiver time-out is enabled and the time-out delay is to x bit period. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 to 76543210 to
573 11011a?atarm?04-oct-10 sam3n 573 11011a?atarm?04-oct-10 sam3n 30.8.11 usart transmitter timeguard register name: us_ttgr addresses: 0x40024028 (0), 0x40028028 (1) access: read-write this register can only be written if the wpen bit is cleared in ?usart write protect mode register? on page 577 . ? tg: timeguard value 0: the transmitter timeguard is disabled. 1 - 255: the transmitter timeguard is enabled and the timeguard delay is tg x bit period. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 tg
574 11011a?atarm?04-oct-10 sam3n 574 11011a?atarm?04-oct-10 sam3n 30.8.12 usart fi di ratio register name: us_fidi addresses: 0x40024040 (0), 0x40028040 (1) access: read-write reset value: 0x174 this register can only be written if the wpen bit is cleared in ?usart write protect mode register? on page 577 . ? fi_di_ratio: fi over di ratio value 0: if iso7816 mode is selected, the baud rate generator generates no signal. 1 - 2047: if iso7816 mode is selected, the baud rate is the clock provided on sck divided by fi_di_ratio. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? fi_di_ratio 76543210 fi_di_ratio
575 11011a?atarm?04-oct-10 sam3n 575 11011a?atarm?04-oct-10 sam3n 30.8.13 usart number of errors register name: us_ner addresses: 0x40024044 (0), 0x40028044 (1) access: read-only ? nb_errors: number of errors total number of errors that occurred during an iso7816 transfer. this register automatically clears when read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 nb_errors
576 11011a?atarm?04-oct-10 sam3n 576 11011a?atarm?04-oct-10 sam3n 30.8.14 usart irda filter register name: us_if addresses: 0x4002404c (0), 0x4002804c (1) access: read-write this register can only be written if the wpen bit is cleared in ?usart write protect mode register? on page 577 . ? irda_filter: irda filter sets the filter of the irda demodulator. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 irda_filter
577 11011a?atarm?04-oct-10 sam3n 577 11011a?atarm?04-oct-10 sam3n 30.8.15 usart write protect mode register name: us_wpmr addresses: 0x400240e4 (0), 0x400280e4 (1) access: read-write reset: see table 30-15 ? wpen: write protect enable 0 = disables the write protect if wpkey corresponds to 0x5553 41 (?usa? in ascii). 1 = enables the write protect if wpkey corresponds to 0x555341 (?usa? in ascii). protects the registers: ? ?usart mode register? on page 561 ? ?usart baud rate generator register? on page 571 ? ?usart receiver time-out register? on page 572 ? ?usart transmitter timeguard register? on page 573 ? ?usart fi di ratio register? on page 574 ? ?usart irda filter register? on page 576 ? wpkey: write protect key should be written at value 0x555341 (?usa? in ascii). writing any other value in this field aborts the write operation of the wpen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 ???????wpen
578 11011a?atarm?04-oct-10 sam3n 578 11011a?atarm?04-oct-10 sam3n 30.8.16 usart write protect status register name: us_wpsr addresses: 0x400240e8 (0), 0x400280e8 (1) access: read-only reset: see table 30-15 ? wpvs: write protect violation status 0 = no write protect violation has occurred since the last read of the us_wpsr register. 1 = a write protect violation has occurred since the last read of the us_wpsr register. if this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. note: reading us_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 ???????wpvs
579 11011a?atarm?04-oct-10 sam3n 579 11011a?atarm?04-oct-10 sam3n 31. timeer counter (tc) 31.1 description the timer counter (tc) includes three identical 16-bit timer counter channels. each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. each channel has three external clock inputs, fi ve internal clock inputs and two multi-purpose input/output signals which can be configured by the user. each channel drives an internal inter- rupt signal which can be programmed to generate processor interrupts. the timer counter (tc) embeds a quadrature decoder logic connected in front of the 3 timers and driven by tioa0, tiob0 and tioa1 inputs. when enabled, the quadrature decoder per- forms the input lines filtering, decoding of quadrature signals and connects to the 3 timers/counters in order to read the position and speed of the motor through user interface. the timer counter block has two global registers which act upon all three tc channels. the block control register allows the three channels to be started simultaneously with the same instruction. the block mode register defines the external clock inputs for each channel, allowing them to be chained. table 31-1 gives the assignment of the device timer counter clock inputs common to timer counter 0 to 2. note: 1. when slow clock is selected for master clock (css = 0 in pmc master clock register), timer_clock5 input is master clock, i.e., slow clock modified by pres and mdiv fields. 31.2 embedded characteristics ? three 16-bit timer counter channels ? a wide range of functions including: ? frequency measurement ? event counting ? interval measurement ? pulse generation ?delay timing ? pulse width modulation ? up/down capabilities table 31-1. timer counter clock assignment name definition timer_clock1 mck/2 timer_clock2 mck/8 timer_clock3 mck/32 timer_clock4 mck/128 timer_clock5 (1) slck
580 11011a?atarm?04-oct-10 sam3n 580 11011a?atarm?04-oct-10 sam3n ? quadrature decoder logic ? 2-bit gray up/down count for stepper motor ? each channel is user-configurable and contains: ? three external clock inputs ? five internal clock inputs ? two multi-purpose input/output signals ? internal interrupt signal ? two global registers that act on all three tc channels ? configuration registers can be write protected
581 11011a?atarm?04-oct-10 sam3n 581 11011a?atarm?04-oct-10 sam3n 31.3 block diagram figure 31-1. timer counter block diagram timer/counter channel 0 timer/counter channel 1 timer/counter channel 2 syn c parallel i/o controller tc1xc1s tc0xc0s tc2xc2s int0 int1 int2 tioa0 tioa1 tioa2 tiob0 tiob1 tiob2 xc0 xc1 xc2 xc0 xc1 xc2 xc0 xc1 xc2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tioa1 tioa2 tioa0 tioa2 tioa0 tioa1 interrupt controller tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 timer counter tioa tiob tioa tiob tioa tiob syn c syn c timer_clock2 timer_clock3 timer_clock4 timer_clock5 timer_clock1 table 31-2. signal name description block/channel signal name description channel signal xc0, xc1, xc2 external clock inputs tioa capture mode: timer counter input waveform mode: timer counter output tiob capture mode: timer counter input waveform mode: timer counter input/output int interrupt signal output sync synchronization input signal
582 11011a?atarm?04-oct-10 sam3n 582 11011a?atarm?04-oct-10 sam3n 31.4 pin name list 31.5 product dependencies 31.5.1 i/o lines the pins used for interfacing the compliant ex ternal devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the tc pins to their peripheral functions. 31.5.2 power management the tc is clocked through the power management controller (pmc), thus the programmer must first configure the pmc to enable the timer counter clock. 31.5.3 interrupt the tc has an interrupt line connected to the interrupt controller (ic). handling the tc interrupt requires programming the ic before configuring the tc. pin name description type tclk0-tclk2 external clock input input tioa0-tioa2 i/o line a i/o tiob0-tiob2 i/o line b i/o table 31-3. i/o lines instance signal i/o line peripheral tc0 tclk0 pa4 b tc0 tclk1 pa28 b tc0 tclk2 pa29 b tc0 tioa0 pa0 b tc0 tioa1 pa15 b tc0 tioa2 pa26 b tc0 tiob0 pa1 b tc0 tiob1 pa16 b tc0 tiob2 pa27 b tc1 tclk3 pc25 b tc1 tclk4 pc28 b tc1 tclk5 pc31 b tc1 tioa3 pc23 b tc1 tioa4 pc26 b tc1 tioa5 pc29 b tc1 tiob3 pc24 b tc1 tiob4 pc27 b tc1 tiob5 pc30 b
583 11011a?atarm?04-oct-10 sam3n 583 11011a?atarm?04-oct-10 sam3n 31.6 functional description 31.6.1 tc description the three channels of the timer counter are independent and identical in operation except when quadrature decoder is enabled. the registers for channel programming are listed in table 31-4 on page 603 . 31.6.2 16-bit counter each channel is organized around a 16-bit counter. the value of the counter is incremented at each positive edge of the selected clock. when the counter has reached the value 0xffff and passes to 0x0000, an overflow occurs and the covfs bit in tc_sr (status register) is set. the current value of the counter is accessible in real time by reading the counter value regis- ter, tc_cv. the counter can be reset by a trigger. in this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 31.6.3 clock selection at block level, input clock signals of each channel can either be connected to the external inputs tclk0, tclk1 or tclk2, or be connected to t he internal i/o signals tioa0, tioa1 or tioa2 for chaining by programming the tc_bmr (block mode). see figure 31-2 ?clock chaining selection? . each channel can independently select an internal or external clock source for its counter: ? internal clock signals: timer_cl ock1, timer_clock2, timer_clock3, timer_clock4, timer_clock5 ? external clock signals: xc0, xc1 or xc2 this selection is made by the tcclks bits in the tc channel mode register. the selected clock can be inverted with the clki bit in tc_cmr. this allows counting on the opposite edges of the clock. the burst function allows the clock to be validat ed when an external signal is high. the burst parameter in the mode register defines this signal (none, xc0, xc1, xc2). see figure 31-3 ?clock selection? note: in all cases, if an external clock is used, the du ration of each of its leve ls must be longer than the master clock period. the external clock frequen cy must be at least 2.5 times lower than the mas- ter clock
584 11011a?atarm?04-oct-10 sam3n 584 11011a?atarm?04-oct-10 sam3n figure 31-2. clock chaining selection figure 31-3. clock selection timer/co u nter ch a nnel 0 s ync tc0xc0 s tioa0 tiob0 xc0 xc1 = tclk1 xc2 = tclk2 tclk0 tioa1 tioa2 timer/co u nter ch a nnel 1 s ync tc1xc1 s tioa1 tiob1 xc0 = tclk0 xc1 xc2 = tclk2 tclk1 tioa0 tioa2 timer/co u nter ch a nnel 2 s ync tc2xc2 s tioa2 tiob2 xc0 = tclk0 xc1 = tclk1 xc2 tclk2 tioa0 tioa1 timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki synchronous edge detection burst mck 1 selected clock
585 11011a?atarm?04-oct-10 sam3n 585 11011a?atarm?04-oct-10 sam3n 31.6.4 clock control the clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. see figure 31-4 . ? the clock can be enabled or disabled by the user with the clken and the clkdis commands in the control register. in capture mode it can be disabled by an rb load event if ldbdis is set to 1 in tc_cmr. in waveform mode, it can be disabled by an rc compare event if cpcdis is set to 1 in tc_cmr. when disabled, the start or the stop actions have no effect: only a clken command in the control register can re-enable the clock. when the clock is enabled, the clksta bit is set in the status register. ? the clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. the clock can be stopped by an rb load event in capture mode (ldbstop = 1 in tc_cmr) or a rc compare event in waveform mode (cpcstop = 1 in tc_cmr). the start and the stop commands have effect only if the clock is enabled. figure 31-4. clock control 31.6.5 tc operating modes each channel can independently operate in two different modes: ? capture mode provides measurement on signals. ? waveform mode provides wave generation. the tc operating mode is prog rammed with the wave bit in th e tc channel mode register. in capture mode, tioa and tiob are configured as inputs. in waveform mode, tioa is always configured to be an output and tiob is an output if it is not selected to be the external trigger. 31.6.6 trigger a trigger resets the counter and starts the counter clock. three types of triggers are common to both modes, and a fourth external trigger is available to each mode. qs r s r q clksta clken clkdis stop event disable event counter clock selected clock trigger
586 11011a?atarm?04-oct-10 sam3n 586 11011a?atarm?04-oct-10 sam3n regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. this means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. the following triggers are common to both modes: ? software trigger: each channel has a software trigger, available by setting swtrg in tc_ccr. ? sync: each channel has a synchronization si gnal sync. when asserted, this signal has the same effect as a software trigger. the sync signals of all channels are asserted simultaneously by writing tc_bcr (block control) with sync set. ? compare rc trigger: rc is implemented in each channel and can provide a trigger when the counter value matches the rc val ue if cpctrg is set in tc_cmr. the channel can also be configured to have an external trigger. in capture mode, the external trigger signal can be selected between tioa and tiob. in waveform mode, an external event can be programmed on one of the following signals: tiob, xc0, xc1 or xc2. this external event can then be programmed to perform a trigger by setting enetrg in tc_cmr. if an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. 31.6.7 capture operating mode this mode is entered by clearing the wave parameter in tc_cmr (channel mode register). capture mode allows the tc channel to perform measurements such as pulse timing, fre- quency, period, duty cycle and phase on tioa and tiob sig nals which are considered as inputs. figure 31-5 shows the configuration of the tc channel when programmed in capture mode. 31.6.8 capture registers a and b registers a and b (ra and rb) are used as capture registers. this means that they can be loaded with the counter value when a progr ammable event occurs on the signal tioa. the ldra parameter in tc_cmr defines the tioa edge for the loading of register a, and the ldrb parameter defines the tioa edge for the loading of register b. ra is loaded only if it has not been loaded since the last trigger or if rb has been loaded since the last loading of ra. rb is loaded only if ra has been loaded sinc e the last trigger or t he last loading of rb. loading ra or rb before the read of the last value loaded sets the overrun error flag (lovrs) in tc_sr (status register). in this case, the old value is overwritten. 31.6.9 trigger conditions in addition to the sync signal, the software trigger and the rc compare trigger, an external trig- ger can be defined. the abetrg bit in tc_cmr selects tioa or tiob input signal as an external trigger. the etrgedg parameter defines the ed ge (rising, falling or both) det ected to genera te an external trigger. if etrgedg = 0 (none), the external trigger is disabled.
587 11011a?atarm?04-oct-10 sam3n 587 11011a?atarm?04-oct-10 sam3n figure 31-5. capture mode timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki qs r s r q clksta clken clkdis burst tiob register c capture register a capture register b compare rc = 16-bit counter abetrg swtrg etrgedg cpctrg tc1_imr trig ldrbs ldras etrgs tc1_sr lovrs covfs sync 1 mtiob tioa mtioa ldra ldbstop if ra is not loaded or rb is loaded if ra is loaded ldbdis cpcs int edge detector edge detector ldrb edge detector clk ovf reset timer/counter channel mck synchronous edge detection
588 11011a?atarm?04-oct-10 sam3n 588 11011a?atarm?04-oct-10 sam3n 31.6.10 waveform operating mode waveform operating mode is entered by setting the wave parameter in tc_cmr (channel mode register). in waveform operating mode the tc channel generates 1 or 2 pwm signals with the same fre- quency and independently programmable duty cycles , or generates differe nt types of one-shot or repetitive pulses. in this mode, tioa is configured as an output and tiob is defined as an output if it is not used as an external event ( eevt parameter in tc_cmr). figure 31-6 shows the configuration of the tc channel when programmed in waveform operat- ing mode. 31.6.11 waveform selection depending on the wavsel parameter in tc_c mr (channel mode register), the behavior of tc_cv varies. with any selection, ra, rb and rc can all be used as compare registers. ra compare is used to control the tioa output, rb compare is used to control the tiob output (if correctly configured) and rc compare is used to control tioa and/or tiob outputs.
589 11011a?atarm?04-oct-10 sam3n 589 11011a?atarm?04-oct-10 sam3n figure 31-6. waveform mode tcclks clki qs r s r q clksta clken clkdis cpcdis burst tiob register a register b register c compare ra = compare rb = compare rc = cpcstop 16-bit counter eevt eevtedg sync swtrg enetrg wavsel tc1_imr trig acpc acpa aeevt aswtrg bcpc bcpb beevt bswtrg tioa mtioa tiob mtiob cpas covfs etrgs tc1_sr cpcs cpbs clk ovf reset output controller output controller int 1 edge detector timer/counter channel timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 wavsel mck synchronous edge detection
590 11011a?atarm?04-oct-10 sam3n 590 11011a?atarm?04-oct-10 sam3n 31.6.11.1 wavsel = 00 when wavsel = 00, the value of tc_cv is incr emented from 0 to 0x ffff. once 0xffff has been reached, the value of tc_cv is reset. incrementation of tc_cv starts again and the cycle continues. see figure 31-7 . an external event trigger or a software trigger can reset the value of tc_cv. it is important to note that the trigger may occur at any time. see figure 31-8 . rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1 in tc_cmr) and/or disable the counter clock (cpcdis = 1 in tc_cmr). figure 31-7. wavsel= 00 without trigger time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples
591 11011a?atarm?04-oct-10 sam3n 591 11011a?atarm?04-oct-10 sam3n figure 31-8. wavsel= 00 with trigger 31.6.11.2 wavsel = 10 when wavsel = 10, the value of tc_cv is incremented from 0 to the value of rc, then auto- matically reset on a rc compare. once the value of tc_cv has been reset, it is then incremented and so on. see figure 31-9 . it is important to note that tc_cv can be reset at any time by an external event or a software trigger if both are programmed correctly. see figure 31-10 . in addition, rc compare can stop the counter clock (cpcstop = 1 in tc_cmr) and/or disable the counter clock (cpcdis = 1 in tc_cmr). figure 31-9. wavsel = 10 without trigger time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples counter cleared by trigger time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples
592 11011a?atarm?04-oct-10 sam3n 592 11011a?atarm?04-oct-10 sam3n figure 31-10. wavsel = 10 with trigger 31.6.11.3 wavsel = 01 when wavsel = 01, the value of tc_cv is incremented from 0 to 0xffff. once 0xffff is reached, the value of tc_cv is decremented to 0, then re-incremented to 0xffff and so on. see figure 31-11 . a trigger such as an external event or a software trigger can modify tc_cv at any time. if a trig- ger occurs while tc_cv is incrementing, tc_cv then decrements. if a trigger is received while tc_cv is decrementing, tc_cv then increments. see figure 31-12 . rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpcdis = 1). time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples counter cleared by trigger
593 11011a?atarm?04-oct-10 sam3n 593 11011a?atarm?04-oct-10 sam3n figure 31-11. wavsel = 01 without trigger figure 31-12. wavsel = 01 with trigger 31.6.11.4 wavsel = 11 when wavsel = 11, the value of tc_cv is incremented from 0 to rc. once rc is reached, the value of tc_cv is decremented to 0, then re-incremented to rc and so on. see figure 31-13 . a trigger such as an external event or a software trigger can modify tc_cv at any time. if a trig- ger occurs while tc_cv is incrementing, tc_cv then decrements. if a trigger is received while tc_cv is decrementing, tc_cv then increments. see figure 31-14 . rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpcdis = 1). time counter value r c r b r a tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a
594 11011a?atarm?04-oct-10 sam3n 594 11011a?atarm?04-oct-10 sam3n figure 31-13. wavsel = 11 without trigger figure 31-14. wavsel = 11 with trigger time counter value r c r b r a tiob tioa counter decremented by compare match with rc 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with rc 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a
595 11011a?atarm?04-oct-10 sam3n 595 11011a?atarm?04-oct-10 sam3n 31.6.12 external event/trigger conditions an external event can be programmed to be detected on one of the clock sources (xc0, xc1, xc2) or tiob. the external event selected can then be used as a trigger. the eevt parameter in tc_cmr selects the external tr igger. the eevtedg parameter defines the trigger edge for each of the possible external triggers (ris ing, falling or both). if eevtedg is cleared (none), no external event is defined. if tiob is defined as an external event signal (eevt = 0), tiob is no longer used as an output and the compare register b is not used to generate waveforms and subsequently no irqs. in this case the tc channel can only generate a waveform on tioa. when an external event is defined, it can be used as a trigger by setting bit enetrg in tc_cmr. as in capture mode, the sync signal and the softw are trigger are also available as triggers. rc compare can also be used as a trigger depending on the parameter wavsel. 31.6.13 output controller the output controller defines the output level changes on tioa and tiob following an event. tiob control is used only if tiob is defin ed as output (not as an external event). the following events control tioa and tiob: software trigger, external event and rc compare. ra compare controls tioa and rb compare controls tiob. each of these events can be pro- grammed to set, clear or toggle the output as defined in the corresponding parameter in tc_cmr. 31.6.14 quadrature decoder logic 31.6.14.1 description the quadrature decoder logic is driven by tioa 0, tiob0, tioa1 input pins and drives the timer/counter of channel 0 and 1. channel 2 can be used as a time base in case of speed mea- surement requirements (refer to figure 31.7 ?timer counter (tc) user interface? ). when writing 0 in the qden field of the tc_bmr register, the quadrature decoder logic is totally transparent. tioa0 and tiob0 are to be driven by the 2 dedicated quadrature signals from a rotary sensor mounted on the shaft of the off-chip motor. a third signal from the rotary sensor can be pr ocessed through pin tioa1 and is typically dedi- cated to be driven by an index signal if it is pr ovided by the sensor. this signal is not required to decode the quadrature signals pha, phb. tcclks field of tc_cmr channels must be configured to select xc0 input (i.e. 0x101). tc0xc0s field has no effect as soon as quadrature decoder is enabled. either speed or position/revolution can be measured. position channel 0 accumulates the edges of pha, phb input signals giving a high accura cy on motor position whereas channel 1 accumu- lates the index pulses of the sensor, therefore the number of rotations. concatenation of both values provides a high level of precision on motion system position. in speed mode, position cannot be measured but revolution can be measured. inputs from the rotary sensor can be filtered prior to down-stream processing. accommodation of input polarity, phase definition and other factors are configurable.
596 11011a?atarm?04-oct-10 sam3n 596 11011a?atarm?04-oct-10 sam3n interruptions can be generated on different events. a compare function (using tc_rc register) is available on channel 0 (speed/position) or chan- nel 1 (rotation) and can generate an interrupt by means of the cpcs flag in the tc_sr registers. figure 31-15. predefined connection of the quadrature decoder with timer counters 31.6.14.2 input pre-processing input pre-processing consists of capabilities to take in to account rotary se nsor factors such as polarities and phase definition followed by configurable digital filtering. each input can be negated and swapping pha, phb is also configurable. timer/co u nter ch a nnel 0 1 xc0 tioa tiob timer/co u nter ch a nnel 1 1 xc0 tiob qden timer/co u nter ch a nnel 2 1 tiob0 xc0 1 1 s peeden 1 xc0 q ua dr a t u re decoder (filter + edge detect + qd) pha phb idx tioa0 tiob0 tiob1 tiob1 tioa0 index s peed/po s ition rot a tion s peed time b as e re s et p u l s e direction phedge s qden
597 11011a?atarm?04-oct-10 sam3n 597 11011a?atarm?04-oct-10 sam3n by means of the maxfilt field in tc_bmr, it is possible to configure a minimum duration for which the pulse is stated as valid. when the f ilter is active, pulses with a duration lower than maxfilt+1 * tmck ns are not passed to down-stream logic. filters can be disabled using the filter field in the tc_bmr register. figure 31-16. input stage input filtering can efficiently remove spurious pu lses that might be generated by the presence of particulate contamination on the optical or magnetic disk of the rotary sensor. spurious pulses can also occur in environments wi th high levels of electro-magnetic interfer- ence. or, simply if vibration occurs even when ro tation is fully stopped and the shaft of the motor is in such a position that the beginning of one of the reflective or magnetic bars on the rotary sensor disk is aligned with the light or magnetic (hall) receiver cell of the rotary sensor. any vibration can make the pha, phb signals toggle for a short duration. 1 1 1 maxfilt pha phb idx tioa0 tiob0 tiob1 inva 1 invb 1 invidx s wap 1 idxphb filter filter filter 1 filter direction a nd edge detection idx phedge dir inp u t pre-proce ss ing
598 11011a?atarm?04-oct-10 sam3n 598 11011a?atarm?04-oct-10 sam3n figure 31-17. filtering examples pha,b filter o u t mck maxfilt=2 p a rtic u l a te cont a min a tion pha phb motor s h a ft s topped in su ch a po s ition th a t rot a ry s en s or cell i s a ligned with a n edge of the di s k rot a tion pha phb phb edge a re a d u e to s y s tem vi b r a tion re su lting pha, phb electric a l w a veform s pha optic a l/m a gnetic di s k s trip s s top phb mech a nic a l s hock on s y s tem vi b r a tion s top pha, phb electric a l w a veform s a fter filtering pha phb
599 11011a?atarm?04-oct-10 sam3n 599 11011a?atarm?04-oct-10 sam3n 31.6.14.3 direction status and change detection after filtering, the quadrature signals are analyz ed to extract the rotation direction and edges of the 2 quadrature signals detected in order to be counted by timer/counter logic downstream. the direction status can be directly read at an ytime on tc_qisr register. the polarity of the direction flag status depends on the configurati on written in tc_bmr register. inva, invb, invidx, swap modify the polarity of dir flag. any change in rotation direction is reported on tc_qisr register and can generate an interrupt. the direction change condition is reported as soon as 2 consecutive edges on a phase signal have sampled the same value on the other phas e signal and there is an edge on the other sig- nal. the 2 consecutive edges of 1 phase signal sampling the same value on other phase signal is not sufficient to declare a direction change, fo r the reason that particulate contamination may mask one or more reflective bar on the optical or magnetic disk of the sensor. (refer to figure 31-18 ?rotation change detection? for waveforms.) figure 31-18. rotation change detection the direction change detection is disabled when qdtrans is set to 1 in tc_bmr. in this case the dir flag report must not be used. pha phb direction ch a nge u nder norm a l condition s dir dirchg ch a nge condition report time no direction ch a nge d u e to p a rtic u l a te cont a min a tion m as king a reflective ba r pha phb dir dirchg s p u rio us ch a nge condition (if detected in a s imple w a y) sa me ph as e mi ss ing p u l s e
600 11011a?atarm?04-oct-10 sam3n 600 11011a?atarm?04-oct-10 sam3n a quadrature error is also reported by the quadrature decoder logic. rather than reporting an error only when 2 edges occur at the same time on pha and phb, which is unlikely to occur in real life, there is a report if the time diffe rence between 2 edges on pha, phb is lower than a predefined value. this predefined value is configurable and corresponds to (maxfilt+1) * tmck ns. after being filtered there is no reason to have 2 edges closer than (maxfilt+1) * tmck ns under normal mode of operation. in the instance an anomaly occurs, a quadrature error is reported on qerr flag on tc_qisr register. figure 31-19. quadrature error detection maxfilt must be tuned according to several factors such as the system clock frequency (mck), type of rotary sensor and rotation speed to be achieved. 31.6.14.4 position and rotation measurement when posen is set in tc_bmr register, positi on is processed on channel 0 (by means of the pha,phb edge detections) and motor revolutions are accumulated in channel 1 timer/counter and can be read through tc_cv0 and/or tc_cv1 register if the idx signal is provided on tioa1 input. channel 0 and 1 must be configured in capture mode (wave = 0 in tc_cmr0). mck maxfilt = 2 pha phb a b norm a lly form a tted optic a l di s k s trip s (theoretic a l view) pha phb s trip edge in a cc u r a ry d u e to di s k etching/printing proce ss re su lting pha, phb electric a l w a veform s pha phb even with a n ab norrm a ly form a tted di s k, there i s no occ u rence of pha, phb s witching a t the sa me time. qerr d u r a tion < maxfilt
601 11011a?atarm?04-oct-10 sam3n 601 11011a?atarm?04-oct-10 sam3n in parallel, the number of edges are accumulated on timer/counter channel 0 and can be read on the tc_cv0 register. therefore, the accurate position can be read on both tc_cv registers and concatenated to form a 32-bit word. the timer/counter channel 0 is cleared for each increment of idx count value. depending on the quadrature signals, the direction is decoded and allows to count up or down in timer/counter channels 0 and 1. the direction status is reported on tc_qisr register. 31.6.14.5 speed measurement when speeden is set in tc_bmr register, t he speed measure is e nabled on channel 0. a time base must be defined on channel 2 by writing the tc_rc2 period register. channel 2 must be configured in waveform mode (wave bit field set) in tc_cmr2 register. wavsel bit field must be defined with 0x10 to clear the counter by comparison and matching with tc_rc value. acpc field must be defined at 0x11 to toggle tioa output. this time base is automatically fed back to tioa of channel 0 w hen qden and speeden are set. channel 0 must be configured in capture mode (w ave = 0 in tc_cmr0). abetrg bit field of tc_cmr0 must be configured at 1 to get tioa as a trigger for this channel. edgtrg can be set to 0x01, to clear the counter on a rising edge of the tioa signal and ldra field must be set accordingly to 0x01, to load tc _ra0 at the same time as the counter is cleared (ldrb must be set to 0x01). as a consequence, at the end of each time base period the differ- entiation required for the speed calculation is performed. the process must be started by configurin g the tc_cr register with clken and swtrg. the speed can be read on tc_ra0 register in tc_cmr0. channel 1 can still be used to count the number of revolutions of the motor. 31.6.15 2-bit gray up/down counter for stepper motor each channel can be independently configured to generate a 2-bit gray count waveform on cor- responding tioa,tiob outputs by means of gcen bit in tc_smmrx registers. up or down count can be defined by writing bit down in tc_smmrx registers. it is mandatory to config ure the channel in wave mo de in tc_cmr register. the period of the counters can be programmed on tc_rcx registers.
602 11011a?atarm?04-oct-10 sam3n 602 11011a?atarm?04-oct-10 sam3n figure 31-20. 2-bit gray up/down counter. 31.6.16 write protection system in order to bring security to the timer counter, a write protection system has been implemented. the write protection mode prevent the write of tc_bmr, tc_cmrx, tc_smmrx, tc_rax, tc_rbx, tc_rcx registers. when this mode is enabled and one of the protected registers write, the register write request canceled. due to the nature of the write protection feature, enabling and disabling the write protection mode requires the use of a security code. thus when enabling or disabling the write protection mode the wpkey field of the tc_wpmr register must be f illed with the ?tim? ascii code (cor- responding to 0x54494d) otherwise th e register write will be canceled. tioax tiobx downx tc_rcx wavex = gcenx =1
603 11011a?atarm?04-oct-10 sam3n 603 11011a?atarm?04-oct-10 sam3n 31.7 timer counter (tc) user interface notes: 1. channel index ranges from 0 to 2. 2. read-only if wave = 0 table 31-4. register mapping offset (1) register name access reset 0x00 + channel * 0x40 + 0x00 channel control register tc_ccr write-only ? 0x00 + channel * 0x40 + 0x04 channel mode register tc_cmr read-write 0 0x00 + channel * 0x40 + 0x08 stepper motor mode register tc_smmr read-write 0 0x00 + channel * 0x40 + 0x0c reserved 0x00 + channel * 0x40 + 0x10 counter value tc_cv read-only 0 0x00 + channel * 0x40 + 0x14 register a tc_ra read-write (2) 0 0x00 + channel * 0x40 + 0x18 register b tc_rb read-write (2) 0 0x00 + channel * 0x40 + 0x1c register c tc_rc read-write 0 0x00 + channel * 0x40 + 0x20 status register tc_sr read-only 0 0x00 + channel * 0x40 + 0x24 interrupt enable register tc_ier write-only ? 0x00 + channel * 0x40 + 0x28 interrupt disable register tc_idr write-only ? 0x00 + channel * 0x40 + 0x2c interrupt mask register tc_imr read-only 0 0xc0 block control register tc_bcr write-only ? 0xc4 block mode register tc_bmr read-write 0 0xc8 qdec interrupt enable register tc_qier write-only ? 0xcc qdec interrupt disable register tc_qidr write-only ? 0xd0 qdec interrupt mask register tc_qimr read-only 0 0xd4 qdec interrupt status register tc_qisr read-only 0 0xe4 write protect mode register tc_wpmr read-write 0 0xfc reserved ? ? ?
604 11011a?atarm?04-oct-10 sam3n 604 11011a?atarm?04-oct-10 sam3n 31.7.1 tc block control register name: tc_bcr addresses: 0x400100c0 (0), 0x400140c0 (1) access: write-only ? sync: synchro command 0 = no effect. 1 = asserts the sync signal which generates a software trigger simultaneously for each of the channels. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????sync
605 11011a?atarm?04-oct-10 sam3n 605 11011a?atarm?04-oct-10 sam3n 31.7.2 tc block mode register name: tc_bmr addresses: 0x400100c4 (0), 0x400140c4 (1) access: read-write this register can only be written if the wpen bit is cleared in ?tc write protect mode register? on page 612 . ? tc0xc0s: external clock signal 0 selection ? tc1xc1s: external clock signal 1 selection ? tc2xc2s: external clock signal 2 selection ? qden: quadrature decoder enabled 0 = disabled. 1 = enables the quadrature decoder logic (filter, edge detection and quadrature decoding). quadrature decoding (direction change) can be disabled using qdtrans bit. one of the posen or speeden bits must be also enabled. 31 30 29 28 27 26 25 24 ?????? maxfilt 23 22 21 20 19 18 17 16 maxfilt filter ? idxphb swap 15 14 13 12 11 10 9 8 invidx invb inva edgpha qdtrans speeden posen qden 76543210 ? ? tc2xc2s tc1xc1s tc0xc0s value name description 0 tclk0 signal connected to xc0: tclk0 1? reserved 2 tioa1 signal connected to xc0: tioa1 3 tioa2 signal connected to xc0: tioa2 value name description 0 tclk1 signal connected to xc1: tclk1 1? reserved 2 tioa0 signal connected to xc1: tioa0 3 tioa2 signal connected to xc1: tioa2 value name description 0 tclk2 signal connected to xc2: tclk2 1? reserved 2 tioa1 signal connected to xc2: tioa1 3 tioa2 signal connected to xc2: tioa2
606 11011a?atarm?04-oct-10 sam3n 606 11011a?atarm?04-oct-10 sam3n ? posen: position enabled 0 = disable position. 1 = enables the position measure on channel 0 and 1 ? speeden: speed enabled 0 = disabled. 1 = enables the speed measure on channel 0, the time base being provided by channel 2. ? qdtrans: quadrature decoding transparent 0 = full quadrature decoding logic is active (direction change detected). 1 = quadrature decoding logic is inactive (direction change inactive) but input filtering and edge detection are performed. ? edgpha: edge on pha count mode 0 = edges are detected on both pha and phb. 1 = edges are detected on pha only. ? inva: inverted pha 0 = pha (tioa0) is directly driving quadrature decoder logic. 1 = pha is inverted before driving quadrature decoder logic. ? invb: inverted phb 0 = phb (tiob0) is directly driving quadrature decoder logic. 1 = phb is inverted before driving quadrature decoder logic. ? swap: swap pha and phb 0 = no swap between pha and phb. 1 = swap pha and phb internally, prior to driving quadrature decoder logic. ? invidx: inverted index 0 = idx (tioa1) is directly driving quadrature logic. 1 = idx is inverted before driving quadrature logic. ? idxphb: index pin is phb pin 0 = idx pin of the rotary sensor must drive tioa1. 1 = idx pin of the rotary sensor must drive tiob0. ?filter: 0 = idx,pha, phb input pins are not filtered. 1 = idx,pha, phb input pins are filtered using maxfilt value. ? maxfilt: maximum filter 1.. 63: defines the filtering capabilities pulses with a period shorter than maxfilt+1 mck clock cycles are discarded.
607 11011a?atarm?04-oct-10 sam3n 607 11011a?atarm?04-oct-10 sam3n 31.7.3 tc channel control register name: tc_ccrx [x=0..2] addresses: 0x40010000 (0)[0], 0x40010040 (0)[1], 0x40010080 (0)[2], 0x40014000 (1)[0], 0x40014040 (1)[1], 0x40014080 (1)[2] access: write-only ? clken: counter clock enable command 0 = no effect. 1 = enables the clock if clkdis is not 1. ? clkdis: counter clock disable command 0 = no effect. 1 = disables the clock. ? swtrg: software trigger command 0 = no effect. 1 = a software trigger is performed: the counter is reset and the clock is started. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????swtrgclkdisclken
608 11011a?atarm?04-oct-10 sam3n 608 11011a?atarm?04-oct-10 sam3n 31.7.4 tc qdec interrupt enable register name: tc_qier addresses: 0x400100c8 (0), 0x400140c8 (1) access: write-only ?idx: index 0 = no effect. 1 = enables the interrupt when a rising edge occurs on idx input. ? dirchg: direction change 0 = no effect. 1 = enables the interrupt when a change on rotation direction is detected. ? qerr: quadrature error 0 = no effect. 1 = enables the interrupt when a quadrature error occurs on pha,phb. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? ? ? qerr dirchg idx
609 11011a?atarm?04-oct-10 sam3n 609 11011a?atarm?04-oct-10 sam3n 31.7.5 tc qdec interrupt disable register name: tc_qidr addresses: 0x400100cc (0), 0x400140cc (1) access: write-only ?idx: index 0 = no effect. 1 = disables the interrupt when a rising edge occurs on idx input. ? dirchg: direction change 0 = no effect. 1 = disables the interrupt when a change on rotation direction is detected. ? qerr: quadrature error 0 = no effect. 1 = disables the interrupt when a quadrature error occurs on pha, phb. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? ? ? qerr dirchg idx
610 11011a?atarm?04-oct-10 sam3n 610 11011a?atarm?04-oct-10 sam3n 31.7.6 tc qdec interrupt mask register name: tc_qimr addresses: 0x400100d0 (0), 0x400140d0 (1) access: read-only ?idx: index 0 = the interrupt on idx input is disabled. 1 = the interrupt on idx input is enabled. ? dirchg: direction change 0 = the interrupt on rotation direction change is disabled. 1 = the interrupt on rotation direction change is enabled. ? qerr: quadrature error 0 = the interrupt on quadrature error is disabled. 1 = the interrupt on quadrature error is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? ? ? qerr dirchg idx
611 11011a?atarm?04-oct-10 sam3n 611 11011a?atarm?04-oct-10 sam3n 31.7.7 tc qdec interrupt status register name: tc_qisr addresses: 0x400100d4 (0), 0x400140d4 (1) access: read-only ?idx: index 0 = no index input change since the last read of tc_qisr. 1 = the idx input has change since the last read of tc_qisr. ? dirchg: direction change 0 = no change on rotation direction since the last read of tc_qisr. 1 = the rotation direction changed since the last read of tc_qisr. ? qerr: quadrature error 0 = no quadrature error since the last read of tc_qisr. 1 = a quadrature error occurred since the last read of tc_qisr. ? dir: direction returns an image of the actual rotation direction. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????dir 76543210 ? ? ? ? ? qerr dirchg idx
612 11011a?atarm?04-oct-10 sam3n 612 11011a?atarm?04-oct-10 sam3n 31.7.8 tc write protect mode register name: tc_wpmr addresses: 0x400100e4 (0), 0x400140e4 (1) access: read-write ? wpen: write protect enable 0 = disables the write protect if wpkey co rresponds to 0x54494d (?tim? in ascii). 1 = enables the write protect if wpkey corres ponds to 0x54494d (?tim? in ascii). protects the registers: ?tc block mode register? ?tc channel mode register: capture mode? ?tc channel mode register: waveform mode? ?tc stepper motor mode register? ?tc register a? ?tc register b? ?tc register c? ? wpkey: write protect key this security code is needed to set/reset the wprot bit value (see for details). must be filled wit h ?tim? ascii code. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 ???????wpen
613 11011a?atarm?04-oct-10 sam3n 613 11011a?atarm?04-oct-10 sam3n 31.7.9 tc channel mode register: capture mode name: tc_cmrx [x=0..2] (wave = 0) addresses: 0x40010004 (0)[0], 0x40010044 (0)[1], 0x40010084 (0)[2], 0x40014004 (1)[0], 0x40014044 (1)[1], 0x40014084 (1)[2] access: read-write this register can only be written if the wpen bit is cleared in ?tc write protect mode register? on page 612 ? tcclks: clock selection ? clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. ? burst: burst signal selection ? ldbstop: counter clock stopped with rb loading 0 = counter clock is not stopped when rb loading occurs. 1 = counter clock is stopped when rb loading occurs. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? ? ldrb ldra 15 14 13 12 11 10 9 8 wave cpctrg ? ? ? abetrg etrgedg 76543210 ldbdis ldbstop burst clki tcclks value name description 0 timer_clock1 clock selected: tclk1 1 timer_clock2 clock selected: tclk2 2 timer_clock3 clock selected: tclk3 3 timer_clock4 clock selected: tclk4 4 timer_clock5 clock selected: tclk5 5 xc0 clock selected: xc0 6 xc1 clock selected: xc1 7 xc2 clock selected: xc2 value name description 0 none the clock is not gated by an external signal. 1 xc0 xc0 is anded with the selected clock. 2 xc1 xc1 is anded with the selected clock. 3 xc2 xc2 is anded with the selected clock.
614 11011a?atarm?04-oct-10 sam3n 614 11011a?atarm?04-oct-10 sam3n ? ldbdis: counter clock disable with rb loading 0 = counter clock is not disabled when rb loading occurs. 1 = counter clock is disabled when rb loading occurs. ? etrgedg: external trigger edge selection ? abetrg: tioa or tiob external trigger selection 0 = tiob is used as an external trigger. 1 = tioa is used as an external trigger. ? cpctrg: rc compare trigger enable 0 = rc compare has no effect on the counter and its clock. 1 = rc compare resets the counter and starts the counter clock. ?wave 0 = capture mode is enabled. 1 = capture mode is disabled (waveform mode is enabled). ? ldra: ra loading selection ? ldrb: rb loading selection value name description 0 none the clock is not gated by an external signal. 1 rising rising edge 2 falling falling edge 3 edge each edge value name description 0none none 1 rising rising edge of tioa 2 falling falling edge of tioa 3 edge each edge of tioa value name description 0none none 1 rising rising edge of tioa 2 falling falling edge of tioa 3 edge each edge of tioa
615 11011a?atarm?04-oct-10 sam3n 615 11011a?atarm?04-oct-10 sam3n 31.7.10 tc channel mode register: waveform mode name: tc_cmrx [x=0..2] (wave = 1) addresses: 0x40010004 (0)[0], 0x40010044 (0)[1], 0x40010084 (0)[2], 0x40014004 (1)[0], 0x40014044 (1)[1], 0x40014084 (1)[2] access: read-write this register can only be written if the wpen bit is cleared in ?tc write protect mode register? on page 612 ? tcclks: clock selection ? clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. ? burst: burst signal selection ? cpcstop: counter clock stopped with rc compare 0 = counter clock is not stopped when counter reaches rc. 1 = counter clock is stopped when counter reaches rc. 31 30 29 28 27 26 25 24 bswtrg beevt bcpc bcpb 23 22 21 20 19 18 17 16 aswtrg aeevt acpc acpa 15 14 13 12 11 10 9 8 wave wavsel enetrg eevt eevtedg 76543210 cpcdis cpcstop burst clki tcclks value name description 0 timer_clock1 clock selected: tclk1 1 timer_clock2 clock selected: tclk2 2 timer_clock3 clock selected: tclk3 3 timer_clock4 clock selected: tclk4 4 timer_clock5 clock selected: tclk5 5 xc0 clock selected: xc0 6 xc1 clock selected: xc1 7 xc2 clock selected: xc2 value name description 0 none the clock is not gated by an external signal. 1 xc0 xc0 is anded with the selected clock. 2 xc1 xc1 is anded with the selected clock. 3 xc2 xc2 is anded with the selected clock.
616 11011a?atarm?04-oct-10 sam3n 616 11011a?atarm?04-oct-10 sam3n ? cpcdis: counter clock disable with rc compare 0 = counter clock is not disabl ed when counter reaches rc. 1 = counter clock is disabled when counter reaches rc. ? eevtedg: external ev ent edge selection ? eevt: external event selection signal selected as external event. note: 1. if tiob is chosen as the external event signal, it is conf igured as an input and no longer generates waveforms and subse- quently no irqs . ? enetrg: external event trigger enable 0 = the external event has no effect on the counter and its clock. in this case, the selected external event only controls the tioa output. 1 = the external event resets the counter and starts the counter clock. ? wavsel: waveform selection ?wave 0 = waveform mode is disabled (capture mode is enabled). 1 = waveform mode is enabled. value name description 0none none 1 rising rising edge 2 falling falling edge 3 edge each edge value name description tiob direction 0 tiob tiob (1) input 1 xc0 xc0 output 2 xc1 xc1 output 3 xc2 xc2 output value name description 0 up up mode without automatic trigger on rc compare 1 updown updown mode without automatic trigger on rc compare 2 up_rc up mode with automatic trigger on rc compare 3 updown_rc updown mode with autom atic trigger on rc compare
617 11011a?atarm?04-oct-10 sam3n 617 11011a?atarm?04-oct-10 sam3n ? acpa: ra compare effect on tioa ? acpc: rc compare effect on tioa ? aeevt: external event effect on tioa ? aswtrg: software trigger effect on tioa ? bcpb: rb compare effect on tiob value name description 0none none 1 set set 2 clear clear 3 toggle toggle value name description 0none none 1 set set 2 clear clear 3 toggle toggle value name description 0none none 1 set set 2 clear clear 3 toggle toggle value name description 0none none 1 set set 2 clear clear 3 toggle toggle value name description 0none none 1 set set 2 clear clear 3 toggle toggle
618 11011a?atarm?04-oct-10 sam3n 618 11011a?atarm?04-oct-10 sam3n ? bcpc: rc compare effect on tiob ? beevt: external event effect on tiob ? bswtrg: software trigger effect on tiob value name description 0none none 1 set set 2 clear clear 3 toggle toggle value name description 0none none 1 set set 2 clear clear 3 toggle toggle value name description 0none none 1 set set 2 clear clear 3 toggle toggle
619 11011a?atarm?04-oct-10 sam3n 619 11011a?atarm?04-oct-10 sam3n 31.7.11 tc stepper motor mode register name: tc_smmrx [x=0..2] addresses: 0x40010008 (0)[0], 0x40010048 (0)[1], 0x40010088 (0)[2], 0x40014008 (1)[0], 0x40014048 (1)[1], 0x40014088 (1)[2] access: read-write this register can only be written if the wpen bit is cleared in ?tc write protect mode register? on page 612 ? gcen: gray count enable 0 = tioax [x=0..2] and tiobx [x=0..2] are driven by internal counter of channel x. 1 = tioax [x=0..2] and tiobx [x=0..2] are driven by a 2-bit gray counter. ? down: down count 0 = up counter. 1 = down counter. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????? ? 15 14 13 12 11 10 9 8 ???????? 76543210 ?downgcen
620 11011a?atarm?04-oct-10 sam3n 620 11011a?atarm?04-oct-10 sam3n 31.7.12 tc counter value register name: tc_cvx [x=0..2] addresses: 0x40010010 (0)[0], 0x40010050 (0)[1], 0x40010090 (0)[2], 0x40014010 (1)[0], 0x40014050 (1)[1], 0x40014090 (1)[2] access: read-only ? cv: counter value cv contains the counter value in real time. 31.7.13 tc register a name: tc_rax [x=0..2] addresses: 0x40010014 (0)[0], 0x40010054 (0)[1], 0x40010094 (0)[2], 0x40014014 (1)[0], 0x40014054 (1)[1], 0x40014094 (1)[2] access: read-only if wave = 0, read-write if wave = 1 this register can only be written if the wpen bit is cleared in ?tc write protect mode register? on page 612 ? ra: register a ra contains the register a value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cv 76543210 cv 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ra 76543210 ra
621 11011a?atarm?04-oct-10 sam3n 621 11011a?atarm?04-oct-10 sam3n 31.7.14 tc register b name: tc_rbx [x=0..2] addresses: 0x40010018 (0)[0], 0x40010058 (0)[1], 0x40010098 (0)[2], 0x40014018 (1)[0], 0x40014058 (1)[1], 0x40014098 (1)[2] access: read-only if wave = 0, read-write if wave = 1 this register can only be written if the wpen bit is cleared in ?tc write protect mode register? on page 612 ? rb: register b rb contains the register b value in real time. 31.7.15 tc register c name: tc_rcx [x=0..2] addresses: 0x4001001c (0)[0], 0x4001005c (0)[1], 0x4001009c (0)[2], 0x4001401c (1)[0], 0x4001405c (1)[1], 0x4001409c (1)[2] access: read-write this register can only be written if the wpen bit is cleared in ?tc write protect mode register? on page 612 ? rc: register c rc contains the register c value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rb 76543210 rb 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rc 76543210 rc
622 11011a?atarm?04-oct-10 sam3n 622 11011a?atarm?04-oct-10 sam3n 31.7.16 tc status register name: tc_srx [x=0..2] addresses: 0x40010020 (0)[0], 0x40010060 (0)[1], 0x400100a0 (0)[2], 0x40014020 (1)[0], 0x40014060 (1)[1], 0x400140a0 (1)[2] access: read-only ? covfs: counter overflow status 0 = no counter overflow has occurred since the last read of the status register. 1 = a counter overflow has occurred since the last read of the status register. ? lovrs: load overrun status 0 = load overrun has not occurred since the last read of the status register or wave = 1. 1 = ra or rb have been loaded at least twice without any read of the corresponding register since the last read of the sta- tus register, if wave = 0. ? cpas: ra compare status 0 = ra compare has not occurred since the last read of the status register or wave = 0. 1 = ra compare has occurred since the last read of the status register, if wave = 1. ? cpbs: rb compare status 0 = rb compare has not occurred since the last read of the status register or wave = 0. 1 = rb compare has occurred since the last read of the status register, if wave = 1. ? cpcs: rc compare status 0 = rc compare has not occurred since the last read of the status register. 1 = rc compare has occurred since the last read of the status register. ? ldras: ra loading status 0 = ra load has not occurred si nce the last read of the status register or wave = 1. 1 = ra load has occurred since the last re ad of the status register, if wave = 0. ? ldrbs: rb loading status 0 = rb load has not occurred si nce the last read of the status register or wave = 1. 1 = rb load has occurred since the last re ad of the status register, if wave = 0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????mtiobmtioaclksta 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
623 11011a?atarm?04-oct-10 sam3n 623 11011a?atarm?04-oct-10 sam3n ? etrgs: external trigger status 0 = external trigger has not occurred sinc e the last read of the status register. 1 = external trigger has occurred since the last read of the status register. ? clksta: clock enabling status 0 = clock is disabled. 1 = clock is enabled. ? mtioa: tioa mirror 0 = tioa is low. if wave = 0, this mean s that tioa pin is low. if wave = 1, this means that tioa is driven low. 1 = tioa is high. if wave = 0, this mean s that tioa pin is high. if wave = 1, this means that ti oa is driven high. ? mtiob: tiob mirror 0 = tiob is low. if wave = 0, this mean s that tiob pin is low. if wave = 1, this means that tiob is driven low. 1 = tiob is high. if wave = 0, this mean s that tiob pin is high. if wave = 1, this means that ti ob is driven high.
624 11011a?atarm?04-oct-10 sam3n 624 11011a?atarm?04-oct-10 sam3n 31.7.17 tc interrupt enable register name: tc_ierx [x=0..2] addresses: 0x40010024 (0)[0], 0x40010064 (0)[1], 0x400100a4 (0)[2], 0x40014024 (1)[0], 0x40014064 (1)[1], 0x400140a4 (1)[2] access: write-only ? covfs: counter overflow 0 = no effect. 1 = enables the counter overflow interrupt. ? lovrs: load overrun 0 = no effect. 1 = enables the load overrun interrupt. ? cpas: ra compare 0 = no effect. 1 = enables the ra compare interrupt. ? cpbs: rb compare 0 = no effect. 1 = enables the rb compare interrupt. ? cpcs: rc compare 0 = no effect. 1 = enables the rc compare interrupt. ? ldras: ra loading 0 = no effect. 1 = enables the ra load interrupt. ? ldrbs: rb loading 0 = no effect. 1 = enables the rb load interrupt. ? etrgs: external trigger 0 = no effect. 1 = enables the external trigger interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
625 11011a?atarm?04-oct-10 sam3n 625 11011a?atarm?04-oct-10 sam3n 31.7.18 tc interrupt disable register name: tc_idrx [x=0..2] addresses: 0x40010028 (0)[0], 0x40010068 (0)[1], 0x400100a8 (0)[2], 0x40014028 (1)[0], 0x40014068 (1)[1], 0x400140a8 (1)[2] access: write-only ? covfs: counter overflow 0 = no effect. 1 = disables the counter overflow interrupt. ? lovrs: load overrun 0 = no effect. 1 = disables the load overrun interrupt (if wave = 0). ? cpas: ra compare 0 = no effect. 1 = disables the ra compare interrupt (if wave = 1). ? cpbs: rb compare 0 = no effect. 1 = disables the rb compare interrupt (if wave = 1). ? cpcs: rc compare 0 = no effect. 1 = disables the rc compare interrupt. ? ldras: ra loading 0 = no effect. 1 = disables the ra load interrupt (if wave = 0). ? ldrbs: rb loading 0 = no effect. 1 = disables the rb load interrupt (if wave = 0). ? etrgs: external trigger 0 = no effect. 1 = disables the external trigger interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
626 11011a?atarm?04-oct-10 sam3n 626 11011a?atarm?04-oct-10 sam3n 31.7.19 tc interrupt mask register name: tc_imrx [x=0..2] addresses: 0x4001002c (0)[0], 0x4001006c (0)[1], 0x400100a c (0)[2], 0x4001402c (1)[0], 0x4001406c (1)[1], 0x400140ac (1)[2] access: read-only ? covfs: counter overflow 0 = the counter overflow interrupt is disabled. 1 = the counter overflow interrupt is enabled. ? lovrs: load overrun 0 = the load overrun interrupt is disabled. 1 = the load overrun interrupt is enabled. ? cpas: ra compare 0 = the ra compare interrupt is disabled. 1 = the ra compare interrupt is enabled. ? cpbs: rb compare 0 = the rb compare interrupt is disabled. 1 = the rb compare interrupt is enabled. ? cpcs: rc compare 0 = the rc compare interrupt is disabled. 1 = the rc compare interrupt is enabled. ? ldras: ra loading 0 = the load ra interrupt is disabled. 1 = the load ra interrupt is enabled. ? ldrbs: rb loading 0 = the load rb interrupt is disabled. 1 = the load rb interrupt is enabled. ? etrgs: external trigger 0 = the external trigger interrupt is disabled. 1 = the external trigger interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
627 11011a?atarm?04-oct-10 sam3n 32. pulse width modulation controller (pwm) 32.1 description the pwm macrocell controls several cha nnels independently. each channel controls one square output waveform. characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. each channel selects and uses one of the clocks provided by the clock generator. the cloc k generator provides several clocks resulting from the division of the pwm macrocell master clock. all pwm macrocell accesses are made through apb mapped registers. channels can be synchronized, to generate non overlapped waveforms. all channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle. 32.2 embedded characteristics ? 4 channels ? one 16-bit counter per channel ? common clock generator provid ing thirteen dif ferent clocks ? a modulo n counter providing eleven clocks ? two independent linear dividers working on modulo n counter outputs ? independent channels ? independent enable disable command for each channel ? independent clock selection for each channel ? independent period and duty cycle for each channel ? double buffering of period or duty cycle for each channel ? programmable selection of the output waveform polarity for each channel ? programmable center or left aligned output waveform for each channel
628 11011a?atarm?04-oct-10 sam3n 32.3 block diagram figure 32-1. pulse width modulation controller block diagram 32.4 i/o lines description each channel outputs one waveform on one external i/o line. 32.5 product dependencies 32.5.1 i/o lines the pins used for interfacing the pwm may be multiplexed with pio lines. the programmer must first program the pio controller to assign the desire d pwm pins to their peripheral function. if i/o lines of the pwm are not used by the applicati on, they can be used for other purposes by the pio controller. pwm controller apb pwmx pwmx pwmx channel update duty cycle counter pwm0 channel pio interrupt controller pmc mck clock generator apb interface interrupt generator clock selector period update duty cycle counter clock selector period pwm0 pwm0 comparator comparator table 32-1. i/o line description name description type pwmx pwm waveform output for channel x output
629 11011a?atarm?04-oct-10 sam3n all of the pwm outputs may or may not be enabled. if an application requires only four channels, then only four pio lines will be assigned to pwm outputs. 32.5.2 power management the pwm is not continuously clocked. the programmer must first enable the pwm clock in the power management controller (pmc) before using the pwm. however, if the application does not require pwm operations, the pwm clock can be stopped when not needed and be restarted later. in this case, th e pwm will resume its operat ions where it left off. configuring the pwm does not require the pwm clock to be enabled. table 32-2. i/o lines instance signal i/o line peripheral pwm pwm0 pa0 a pwm pwm0 pa11 b pwm pwm0 pa23 b pwm pwm0 pb0 a pwm pwm0 pc8 b pwm pwm0 pc18 b pwm pwm0 pc22 b pwm pwm1 pa1 a pwm pwm1 pa12 b pwm pwm1 pa24 b pwm pwm1 pb1 a pwm pwm1 pc9 b pwm pwm1 pc19 b pwm pwm2 pa2 a pwm pwm2 pa13 b pwm pwm2 pa25 b pwm pwm2 pb4 b pwm pwm2 pc10 b pwm pwm2 pc20 b pwm pwm3 pa7 b pwm pwm3 pa14 b pwm pwm3 pb14 b pwm pwm3 pc11 b pwm pwm3 pc21 b
630 11011a?atarm?04-oct-10 sam3n 32.5.3 interrupt sources the pwm interrupt line is connected on one of the internal sources of the interrupt controller. using the pwm interrupt requires the interrupt controller to be programmed first. note that it is not recommended to use the pwm interrupt line in edge sensitive mode. 32.6 functional description the pwm macrocell is primarily composed of a clock generator module and 4 channels. ? clocked by the system clock, mck, the clock generator module provides 13 clocks. ? each channel can independently choose one of the clock generator outputs. ? each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. 32.6.1 pwm clock generator figure 32-2. functional view of the clock generator block diagram table 32-3. peripheral ids instance id pwm 31 modulo n counter mck mck/2 mck/4 mck/16 mck/32 mck/64 mck/8 divider a clka diva pwm_mr mck mck/128 mck/256 mck/512 mck/1024 prea divider b clkb divb pwm_mr preb
631 11011a?atarm?04-oct-10 sam3n caution: before using the pwm macrocell, the pr ogrammer must first enable the pwm clock in the power management controller (pmc). the pwm macrocell master clock, mck, is divide d in the clock generator module to provide dif- ferent clocks available for all channels. each channel can independently select one of the divided clocks. the clock generator is divided in three blocks: ? a modulo n counter which provides 11 clocks: f mck , f mck /2, f mck /4, f mck /8, f mck /16, f mck /32, f mck /64, f mck /128, f mck /256, f mck /512, f mck /1024 ? two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clka and clkb each linear divider can independently divide one of the clocks of the modulo n counter. the selection of the clock to be divided is made ac cording to the prea (preb) field of the pwm mode register (pwm_mr). the resulting clock clka (clkb) is the clock selected divided by diva (divb) field value in the pwm mode register (pwm_mr). after a reset of the pwm controller, diva (divb) and prea (preb) in the pwm mode register are set to 0. this implies that after reset clka (clkb) are turned off. at reset, all clocks provided by the modulo n counter are turned off except clock ?clk?. this situa- tion is also true when the pwm master cl ock is turned off through the power management controller. 32.6.2 pwm channel 32.6.2.1 block diagram figure 32-3. functional view of the channel block diagram each of the 4 channels is composed of three blocks: ? a clock selector which selects one of the clocks provided by the clock generator described in section 32.6.1 ?pwm clock generator? on page 630 . ? an internal counter clocked by the output of the clock selector. this internal counter is incremented or decremented according to the channel configuration and comparators events. the size of the internal counter is 16 bits. ? a comparator used to generate events according to the internal counter value. it also computes the pwmx output waveform according to the configuration. comp a r a tor pwmx o u tp u t w a veform intern a l co u nter clock s elector inp u t s from clock gener a tor inp u t s from apb bus ch a nnel
632 11011a?atarm?04-oct-10 sam3n 32.6.2.2 waveform properties the different properties of output waveforms are: ? the internal clock selection . the internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. this channel parameter is defined in the cpre field of the pwm_cmrx register. this field is reset at 0. ? the waveform period . this channel parameter is defined in the cprd field of the pwm_cprdx register. - if the waveform is left aligned, then the output waveform period depends on the counter source clock and can be calculated: by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be: by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or if the waveform is center aligned then the output waveform period depends on the counter source clock and can be calculated: by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024 ). the resulting period formula will be: by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or ? the waveform duty cycle . this channel parameter is defined in the cdty field of the pwm_cdtyx register. if the waveform is left aligned then: if the waveform is center aligned, then: ? the waveform polarity. at the beginning of the period, the signal can be at high or low level. this property is defined in the cpol field of the pwm_cmrx register. by default the signal starts by a low level. xcprd () mck -------------------------------- x * cprd * diva () mck --------------------------------------------- - x * cprd * divb () mck --------------------------------------------- - 2 xcprd () mck ------------------------------------------ - 2* x * cprd * diva () mck --------------------------------------------------- - 2* x * cprd * divb () mck --------------------------------------------------- - duty cycle period 1 fchannel_x_clock cdty ? ? () period ----------------------------------------------------------------------------------------------------------- - = duty cycle period 2 ? () 1 fchannel_x_clock cdty ? ? ()) period 2 ? () ------------------------------------------------------------------------------------------------------------------------------ =
633 11011a?atarm?04-oct-10 sam3n ? the waveform alignment . the output waveform can be left or center aligned. center aligned waveforms can be used to generate non overlapped waveforms. this property is defined in the calg field of the pwm_cmrx register. the default mode is left aligned. figure 32-4. non overlapped center aligned waveforms note: 1. see figure 32-5 on page 634 for a detailed description of center aligned waveforms. when center aligned, the internal channel count er increases up to cprd and.decreases down to 0. this ends the period. when left aligned, the internal channel counter increases up to cprd and is reset. this ends the period. thus, for the same cprd value, the period for a ce nter aligned channel is twice the period for a left aligned channel. waveforms are fixed at 0 when: ? cdty = cprd and cpol = 0 ? cdty = 0 and cpol = 1 waveforms are fixed at 1 (once the channel is enabled) when: ? cdty = 0 and cpol = 0 ? cdty = cprd and cpol = 1 the waveform polarity must be set before enabling the channel. this immediately affects the channel output level. changes on channel polari ty are not taken into account while the channel is enabled. pwm0 pwm1 period no overlap
634 11011a?atarm?04-oct-10 sam3n figure 32-5. waveform properties pwm_mckx chidx(pwm_sr) center aligned cprd(pwm_cprdx) cdty(pwm_cdtyx) pwm_ccntx output waveform pwmx cpol(pwm_cmrx) = 0 output waveform pwmx cpol(pwm_cmrx) = 1 chidx(pwm_isr) left aligned cprd(pwm_cprdx) cdty(pwm_cdtyx) pwm_ccntx output waveform pwmx cpol(pwm_cmrx) = 0 output waveform pwmx cpol(pwm_cmrx) = 1 chidx(pwm_isr) calg(pwm_cmrx) = 0 calg(pwm_cmrx) = 1 period period chidx(pwm_ena) chidx(pwm_dis)
635 11011a?atarm?04-oct-10 sam3n 32.6.3 pwm controller operations 32.6.3.1 initialization before enabling the output channel, this chann el must have been configured by the software application: ? configuration of the clock generator if diva and divb are required ? selection of the clock for each channel (cpre field in the pwm_cmrx register) ? configuration of the waveform alignment for each channel (calg field in the pwm_cmrx register) ? configuration of the period for each channel (cprd in the pwm_cprdx register). writing in pwm_cprdx register is possible while the channel is disabled. after validation of the channel, the user must use pwm_cupdx register to update pwm_cprdx as explained below. ? configuration of the duty cycl e for each channel (cdty in the pwm_cdtyx register). writing in pwm_cdtyx register is possible while the channel is disabled. after validation of the channel, the user must use pwm_cupdx register to update pwm_cdtyx as explained below. ? configuration of the output waveform polarity for each channel (cpol in the pwm_cmrx register) ? enable interrupts (writing chidx in the pwm_ier register) ? enable the pwm channel (writing chidx in the pwm_ena register) it is possible to synchronize different channels by enabling them at the same time by means of writing simultaneously several chidx bits in the pwm_ena register. ? in such a situation, all channels may have the same clock selector configuration and the same period specified. 32.6.3.2 source clock selection criteria the large number of source clocks can make selection difficult. the relationship between the value in the period register (pwm_cprdx) an d the duty cycle regi ster (pwm_cdtyx) can help the user in choosing. the event number written in the period register gives the pwm accu- racy. the duty cycle quantum cannot be lower than 1/pwm_cprdx value. the higher the value of pwm_cprdx, the greater the pwm accuracy. for example, if the user sets 15 (in decimal) in pwm_cprdx, the user is able to set a value between 1 up to 14 in pwm_cdtyx register. the resulting duty cycle quantum cannot be lower than 1/15 of the pwm period. 32.6.3.3 changing the duty cycle or the period it is possible to modulate the output waveform duty cycle or period. to prevent unexpected output waveform, the user must use the update register (pwm_cupdx) to change waveform parameters while the channel is still enabled. the user can write a new period value or duty cycle value in the update re gister (pwm_cupdx). this register holds the new value until the end of the current cycle and updates the value for the next cycle. depending on the cpd field in the pwm_cmrx regist er, pwm_cupdx either updates pwm_cprdx or pwm_cdtyx. note that even if the update register is used, the period must not be smaller than the duty cycle.
636 11011a?atarm?04-oct-10 sam3n figure 32-6. synchronized period or duty cycle update to prevent overwriting the pwm_cupdx by software , the user can use status events in order to synchronize his software. two methods are possibl e. in both, the user must enable the dedi- cated interrupt in pwm_ier at pwm controller level. the first method ( polling method) consists of reading the relevant status bit in pwm_isr regis- ter according to the enabled channel(s). see figure 32-7 . the second method uses an interrupt service routine associated with the pwm channel. note: reading the pwm_isr register automatically clears chidx flags. figure 32-7. polling method note: polarity and alignment can be modified only when the channel is disabled. pwm_cupdx value pwm_cprdx pwm_cdtyx end of cycle pwm_cmrx. cpd user's writing 1 0 writing in pwm_cupdx the last write has been taken into account chidx = 1 writing in cpd field update of the period or duty cycle pwm_isr read acknowledgement and clear previous register state yes
637 11011a?atarm?04-oct-10 sam3n 32.6.3.4 interrupts depending on the interrupt mask in the pwm_imr register, an interrupt is generated at the end of the corresponding channel period. the interrupt remains active until a read operation in the pwm_isr register occurs. a channel interrupt is enabled by setting the corresponding bit in the pwm_ier register. a chan- nel interrupt is disabled by setting the corresponding bit in the pwm_idr register.
638 11011a?atarm?04-oct-10 sam3n 32.7 pulse width modulation cont roller (pwm) user interface 2. some registers are indexed with ?ch_num? index ranging from 0 to 3. table 32-4. register mapping (2) offset register name access reset 0x00 pwm mode register pwm_mr read-write 0 0x04 pwm enable register pwm_ena write-only - 0x08 pwm disable register pwm_dis write-only - 0x0c pwm status register pwm_sr read-only 0 0x10 pwm interrupt enable register pwm_ier write-only - 0x14 pwm interrupt disable register pwm_idr write-only - 0x18 pwm interrupt mask register pwm_imr read-only 0 0x1c pwm interrupt status register pwm_isr read-only 0 0x20 - 0xfc reserved ? ? ? 0x100 - 0x1fc reserved 0x200 + ch_num * 0x20 + 0x00 pwm channel mode register pwm_cmr read-write 0x0 0x200 + ch_num * 0x20 + 0x04 pwm channel duty cycle register pwm_cdty read-write 0x0 0x200 + ch_num * 0x20 + 0x08 pwm channel period register pwm_cprd read-write 0x0 0x200 + ch_num * 0x20 + 0x0c pwm channel counter register pwm_ccnt read-only 0x0 0x200 + ch_num * 0x20 + 0x10 pwm channel update register pwm_cupd write-only -
639 11011a?atarm?04-oct-10 sam3n 32.7.1 pwm mode register name: pwm_mr address: 0x40020000 access: read/write ? diva, divb: clka, clkb divide factor ? prea, preb values which are not listed in the table must be considered as ?reserved?. 31 30 29 28 27 26 25 24 ???? preb 23 22 21 20 19 18 17 16 divb 15 14 13 12 11 10 9 8 ???? prea 76543210 diva value name description 0 clk_off clka, clkb clock is turned off 1 clk_div1 clka, clkb clock is clock selected by prea, preb 2-255 ? clka, clkb clock is clock selected by prea, preb divided by diva, divb factor. value name description 0000 mck master clock 0001 mckdiv2 master clock divided by 2 0010 mckdiv4 master clock divided by 4 0011 mckdiv8 master clock divided by 8 0100 mckdiv16 master clock divided by 16 0101 mckdiv32 master clock divided by 32 0110 mckdiv64 master clock divided by 64 0111 mckdiv128 master clock divided by 128 1000 mckdiv256 master clock divided by 256 1001 mckdiv512 master clock divided by 512 1010 mckdiv1024 master clock divided by 1024
640 11011a?atarm?04-oct-10 sam3n 32.7.2 pwm enable register name: pwm_ena address: 0x40020004 access: write-only ? chidx: channel id 0 = no effect. 1 = enable pwm output for channel x. 32.7.3 pwm disable register name: pwm_dis address: 0x40020008 access: write-only ? chidx: channel id 0 = no effect. 1 = disable pwm output for channel x. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 chid3 chid2 chid1 chid0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 chid3 chid2 chid1 chid0
641 11011a?atarm?04-oct-10 sam3n 32.7.4 pwm status register name: pwm_sr address: 0x4002000c access: read-only ? chidx: channel id 0 = pwm output for channel x is disabled. 1 = pwm output for channel x is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 chid3 chid2 chid1 chid0
642 11011a?atarm?04-oct-10 sam3n 32.7.5 pwm interrupt enable register name: pwm_ier address: 0x40020010 access: write-only ? chidx: channel id. 0 = no effect. 1 = enable interrupt for pwm channel x. 32.7.6 pwm interrupt disable register name: pwm_idr address: 0x40020014 access: write-only ? chidx: channel id. 0 = no effect. 1 = disable interrupt for pwm channel x. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 chid3 chid2 chid1 chid0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 chid3 chid2 chid1 chid0
643 11011a?atarm?04-oct-10 sam3n 32.7.7 pwm interrupt mask register name: pwm_imr address: 0x40020018 access: read-only ? chidx: channel id. 0 = interrupt for pwm channel x is disabled. 1 = interrupt for pwm channel x is enabled. 32.7.8 pwm interrupt status register name: pwm_isr address: 0x4002001c access: read-only ? chidx: channel id 0 = no new channel period has been achieved si nce the last read of the pwm_isr register. 1 = at least one new channel period has been achiev ed since the last read of the pwm_isr register. note: reading pwm_isr automa tically clears chidx flags. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 chid3 chid2 chid1 chid0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 chid3 chid2 chid1 chid0
644 11011a?atarm?04-oct-10 sam3n 32.7.9 pwm channel mode register name: pwm_cmr[0..3] addresses: 0x40020200 [0], 0x40020220 [1], 0x40020240 [2], 0x40020260 [3] access: read/write ? cpre: channel pre-scaler values which are not listed in the table must be considered as ?reserved?. ? calg: channel alignment 0 = the period is left aligned. 1 = the period is center aligned. ? cpol: channel polarity 0 = the output waveform starts at a low level. 1 = the output waveform starts at a high level. ? cpd: channel update period 0 = writing to the pwm_cupdx will modify the duty cycle at the next period start event. 1 = writing to the pwm_cupdx will modify th e period at the next period start event. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????cpdcpolcalg 76543210 ???? cpre value name description 0000 mck master clock 0001 mckdiv2 master clock divided by 2 0010 mckdiv4 master clock divided by 4 0011 mckdiv8 master clock divided by 8 0100 mckdiv16 master clock divided by 16 0101 mckdiv32 master clock divided by 32 0110 mckdiv64 master clock divided by 64 0111 mckdiv128 master clock divided by 128 1000 mckdiv256 master clock divided by 256 1001 mckdiv512 master clock divided by 512 1010 mckdiv1024 master clock divided by 1024 1011 clka clock a 1100 clkb clock b
645 11011a?atarm?04-oct-10 sam3n 32.7.10 pwm channel duty cycle register name: pwm_cdty[0..3] addresses: 0x40020204 [0], 0x40020224 [1], 0x40020244 [2], 0x40020264 [3] access: read/write only the first 16 bits (internal ch annel counter size) are significant. ? cdty: channel duty cycle defines the waveform duty cycle. this value must be defined between 0 and cprd (pwm_cprx). 31 30 29 28 27 26 25 24 cdty 23 22 21 20 19 18 17 16 cdty 15 14 13 12 11 10 9 8 cdty 76543210 cdty
646 11011a?atarm?04-oct-10 sam3n 32.7.11 pwm channel period register name: pwm_cprd[0..3] addresses: 0x40020208 [0], 0x40020228 [1], 0x40020248 [2], 0x40020268 [3] access: read/write only the first 16 bits (internal ch annel counter size) are significant. ? cprd: channel period if the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated: ? by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). the resu lting period formula will be: ? by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or if the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be calculated: ? by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024) . the resulting pe riod formula will be: ? by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or 31 30 29 28 27 26 25 24 cprd 23 22 21 20 19 18 17 16 cprd 15 14 13 12 11 10 9 8 cprd 76543210 cprd xcprd () mck -------------------------------- crpd diva () mck ------------------------------------------- crpd divab () mck ----------------------------------------------- 2 xcprd () mck ------------------------------------------ - 2 cprd diva () mck ----------------------------------------------------- - 2 cprd divb () mck ----------------------------------------------------- -
647 11011a?atarm?04-oct-10 sam3n 32.7.12 pwm channel counter register name: pwm_ccnt[0..3] addresses: 0x4002020c [0], 0x4002022c [1], 0x4002024c [2], 0x4002026c [3] access: read-only ? cnt: channel counter register internal counter value. this register is reset when: ? the channel is enabled (writing chidx in the pwm_ena register). ? the counter reaches cprd value defined in the pwm_ cprdx register if the waveform is left aligned. 31 30 29 28 27 26 25 24 cnt 23 22 21 20 19 18 17 16 cnt 15 14 13 12 11 10 9 8 cnt 76543210 cnt
648 11011a?atarm?04-oct-10 sam3n 32.7.13 pwm channel update register name: pwm_cupd[0..3] addresses: 0x40020210 [0], 0x40020230 [1], 0x40020250 [2], 0x40020270 [3] access: write-only cupd: channel update register this register acts as a double buffer for the period or the duty cycle. this prevents an unexpected waveform when modify- ing the waveform period or duty-cycle. only the first 16 bits (internal ch annel counter size) are significant. when cpd field of pwm_cmrx register = 0, the duty-cycle (cdty of pwm_cdtyx register) is updated with the cupd value at the beginning of the next period. when cpd field of pwm_cmrx register = 1, the period (cpr d of pwm_cprdx register) is updated with the cupd value at the beginning of the next period. 31 30 29 28 27 26 25 24 cupd 23 22 21 20 19 18 17 16 cupd 15 14 13 12 11 10 9 8 cupd 76543210 cupd
649 11011a?atarm?04-oct-10 sam3n 649 11011a?atarm?04-oct-10 sam3n 33. analog-to-digital converter (adc) 33.1 description the adc is based on a 10-bit analog-to-digita l converter (adc) managed by an adc control- ler. refer to the block diagram: figure 33-1 . it also integrates a 16-to-1 analog multiplexer, making possible the analog-to-digital conversions of 16 analog lines. the conversions extend from 0v to advref. the adc supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated reg- ister. software trigger, external trigger on rising edge of the adtrg pin or internal triggers from timer counter output(s) are configurable. the comparison circuitry allows automatic detection of values below a threshold, higher than a threshold, in a given range or outside the range, thresholds and ranges being fully configurable. the adc also integrates a sleep mode and a conversion sequencer and connects with a pdc channel. these features reduce both power consumption and processor intervention. a whole set of reference voltages is generated internally from a single external reference volt- age node that may be equal to the analog supply voltage. an external decoupling capacitance is required for noise filtering. finally, the user can configure adc timings, such as startup time and tracking time. 33.2 embedded characteristics ? 10-bit resolution ? 500 khz conversion rate ? wide range power supply operation ? integrated multiplexer offering up to 16 independent analog inputs ? individual enable and disable of each channel ? hardware or software trigger ? external trigger pin ? timer counter outputs (corresponding tioa tr i g g e r ) ? pdc support ? possibility of adc timings configuration ? two sleep modes and conversion sequencer ? automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels ? possibility of custom ized channel sequence ? standby mode for fast wakeup time response ? power down capability ? automatic window comparison of converted values ? write protect registers
650 11011a?atarm?04-oct-10 sam3n 650 11011a?atarm?04-oct-10 sam3n 33.3 block diagram figure 33-1. analog-to-digital converter block diagram 33.4 signal description table 33-1. adc pin description pin name description advref reference voltage ad0 - ad 15 analog input channels adtrg external trigger adc interrupt adtrg advref gnd trigger selection control logic successive approximation register analog-to-digital converter timer counter channels user interface interrupt controller peripheral bridge apb pdc system bus analog inputs multiplexed with i/o lines pio ad- ad- ad- adc controller pmc mck adc cell chx
651 11011a?atarm?04-oct-10 sam3n 651 11011a?atarm?04-oct-10 sam3n 33.5 product dependencies 33.5.1 power management the adc controller is not continuously clock ed. the programmer must first enable the adc controller mck in the power management cont roller (pmc) before using the adc controller. however, if the application doe s not require adc operations, the adc controller clock can be stopped when not needed and restarted when necessary. configuring the adc controller does not require the adc controller clock to be enabled. 33.5.2 interrupt sources the adc interrupt line is connected on one of the internal sources of the interrupt controller. using the adc interrupt requires the nvic to be programmed first. 33.5.3 analog inputs the analog input pins can be multiplexed with pio lines. in this case, the assignment of the adc input is automatically done as soon as the corresponding channel is enabled by writing the reg- ister adc_cher. by default, after reset, the pio line is configured as input with its pull-up enabled and the adc input is connected to the gnd. 33.5.4 i/o lines the pin adtrg may be shared with other peripheral functions through the pio controller. in this case, the pio controller should be set acco rdingly to assign the pin adtrg to the adc function. table 33-2. peripheral ids instance id adc 29 table 33-3. i/o lines instance signal i/o line peripheral adc adtrg pa8 b adc ad0 pa17 x1 adc ad1 pa18 x1 adc ad2/wkup9 pa19 x1 adc ad3/wkup10 pa20 x1 adc ad4 pb0 x1 adc ad5 pb1 x1 adc ad6/wkup12 pb2 x1 adc ad7 pb3 x1 adc ad8 pa21 x1 adc ad9 pa22 x1 adc ad10 pc13 x1 adc ad11 pc15 x1 adc ad12 pc12 x1
652 11011a?atarm?04-oct-10 sam3n 652 11011a?atarm?04-oct-10 sam3n 33.5.5 timer triggers timer counters may or may not be used as hardware triggers depending on user requirements. thus, some or all of the timer counters may be unconnected. 33.5.6 conversion performances for performance and electrical characteristics of the adc, see the product dc characteristics section. 33.6 functional description 33.6.1 analog-to-digital conversion the adc uses the adc clock to perform conversi ons. converting a single analog value to a 10- bit digital data requires tracki ng clock cycles as defined in the field tracktim of the ?adc mode register? on page 661 and transfer clock cycles as defined in the field transfer of the same register. the adc clock frequency is selected in the prescal field of the mode register (adc_mr). the tracking phase starts during the co nversion of the previous channel. if the track- ing time is longer than the conversion time, the tracking phase is extended to the end of the previous conversion. the adc clock range is between mck/2, if presc al is 0, and mck/512, if prescal is set to 255 (0xff). prescal must be programmed in order to provide an adc clock frequency according to the parameters given in the product electrical characteristics section. adc ad13 pc29 x1 adc ad14 pc30 x1 adc ad15 pc31 x1 table 33-3. i/o lines
653 11011a?atarm?04-oct-10 sam3n 653 11011a?atarm?04-oct-10 sam3n figure 33-2. sequence of adc conversions 33.6.2 conversion reference the conversion is performed on a full range be tween 0v and the reference voltage pin advref. analog inputs between these voltages convert to values based on a linear conversion. 33.6.3 conversion resolution the adc supports 8-bit or 10-bit resolutions. the 8-bit selection is performed by setting the lowres bit in the adc mode r egister (adc_mr). by default, after a reset, the resolution is the highest and the data field in the data registers is fully used. by setting the lowres bit, the adc switches to the lowest resolution and the c onversion results can be read in the lowest sig- nificant bits of the data registers. the two highest bits of the data field in the corresponding adc_cdr register and of the ldata field in the adc_lcdr register read 0. 33.6.4 conversion results when a conversion is completed, the resulting 10-bit digital value is stored in the channel data register (adc_cdrx) of the current channel and in the adc last converted data register (adc_lcdr). by setting the tag option in the adc_emr, the adc_lcdr presents the chan- nel number associated to the last converted data in the chnb field. the channel eoc bit in the status register (adc_sr) is set and the drdy is set. in the case of a connected pdc channel, drdy rising triggers a data transfer request. in any case, either eoc and drdy can trigger an interrupt. reading one of the adc_cdr registers clears the corresponding eoc bit. reading adc_lcdr clears the drdy bit and eoc bit corresponding to the last converted channel. adcclock lcdr adc_on adc_ s el drdy adc_ s t a rt ch0 ch1 ch0 ch2 ch1 s t a rt up time ( a nd tr a cking of ch0) conver s ion of ch0 conver s ion of ch1 tr a cking of ch1 tr a cking of ch2 adc_eoc trigger event (h a rd or s oft) an a log cell io s
654 11011a?atarm?04-oct-10 sam3n 654 11011a?atarm?04-oct-10 sam3n figure 33-3. eocx and drdy flag behavior if the adc_cdr is not read befo re further incoming data is converted, the corresponding over- run error (ovrex) flag is set in the overrun status register (adc_over). likewise, new data converted when drdy is hi gh sets the govre bit (general overrun error) in adc_sr. the ovrex flag is automatically cleared when adc_over is read, and govre flag is auto- matically cleared when adc_sr is read. read the adc_cdrx eocx drdy read the adc_lcdr chx (adc_chsr) (adc_sr) (adc_sr) write the adc_cr with start = 1 write the adc_cr with start = 1
655 11011a?atarm?04-oct-10 sam3n 655 11011a?atarm?04-oct-10 sam3n figure 33-4. govre and ovrex flag behavior warning: if the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and its corresponding eoc and ovre flags in adc_sr are unpredictable. eoc0 govre ch0 (adc_chsr) (adc_sr) (adc_sr) trigger event eoc1 ch1 (adc_chsr) (adc_sr) ovre0 (adc_over) undefined data data a data b adc_lcdr undefined data data a adc_cdr0 undefined data data b adc_cdr1 data c data c conversion c conversion a drdy (adc_sr) read adc_cdr1 read adc_cdr0 conversion b read adc_over read adc_sr ovre1 (adc_over)
656 11011a?atarm?04-oct-10 sam3n 656 11011a?atarm?04-oct-10 sam3n 33.6.5 conversion triggers conversions of the active analog channels are start ed with a software or hardware trigger. the software trigger is provided by writing the control register (adc_ cr) with the start bit at 1. the hardware trigger can be one of the tioa outputs of the timer counter channels or the external trigger input of the adc (adtrg). the hardware trigger is selected with the trgsel field in the mode register (adc_mr). the selected hardware trigger is enabled with the trgen bit in the mode register (adc_mr). the minimum time between 2 consecutive trigger events must be strictly greater than the dura- tion time of the longest conversion sequence according to configuration of registers adc_mr, adc_chsr, adc_seqr1, adc_seqr2. if a hardware trigger is selected, the start of a conversion is triggered after a delay starting at each rising edge of the selected signal. due to asynchronous handling, the delay may vary in a range of 2 mck clock periods to 1 adc clock period. if one of the tioa outputs is selected, the corresponding timer counter channel must be pro- grammed in waveform mode. only one start command is necessary to initiate a conversion sequence on all the channels. the adc hardware logic automatically performs the conversions on the active channels, then waits for a new request. the channel enable (adc_cher) and channel disable (adc_chdr) reg- isters permit the analog channels to be enabled or disabled independently. if the adc is used with a pdc, only the tran sfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly. 33.6.6 sleep mode and conversion sequencer the adc sleep mode maximizes power saving by automatically deactivating the adc when it is not being used for conversions. sleep mode is selected by setting the sleep bit in the mode register adc_mr. the sleep mode is automatically managed by a conversion sequencer, which can automatically process the conversions of all channels at lowest power consumption. this mode can be used when the minimum period of time between 2 successive trigger events is greater than the startup period of analog-digit al converter (see the product adc characteris- tics section). when a start conversion request occurs, the adc is automatically activated. as the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the enabled channels. when all conversions are complete, the adc is deactivated until the next trigger. trig- gers occurring during the sequence are not taken into account. a fast wake-up mode is available in the adc mode register (adc_mr) as a compromise between power saving strategy and responsiveness . setting the fwup bit to ?1? enables the fast wake-up mode. in fast wake-up mo de the adc cell is not fully deac tivated while no conversion is requested, thereby providing less power saving but faster wakeup. the conversion sequencer allows automatic pr ocessing with minimum processor intervention and optimized power consumption. conversion sequences can be performed periodically using trigger start delay
657 11011a?atarm?04-oct-10 sam3n 657 11011a?atarm?04-oct-10 sam3n a timer/counter output. the periodic acquisition of several samples can be processed automat- ically without any intervention of the processor thanks to the pdc. the sequence can be customized by programming the sequence channel registers, adc_seqr1 and adc_seqr2 and setting to 1 the useq bit of the mode register (adc_mr). the user can choose a specific order of channels and can program up to 16 conversions by sequence. the user is totally free to create a personal sequence, by writing channel numbers in adc_seqr1 and adc_seqr2. not only can channel numbers be written in any sequence, channel numbers can be repeated several times. only enabled sequence bitfields are con- verted, consequently to program a 15-conversion sequence, the user can simply put a disable in adc_chsr[15], thus disabling the 16thch field of adc_seqr2. if all adc channels (i.e. 16) are used on an application board, there is no restriction of usage of the user sequence. but as soon as some adc channels are not enabled for conversion but rather used as pure digital inputs, the respecti ve indexes of these channels cannot be used in the user sequence fields (adc_seqr1, adc_seqr2 bitfields). for example, if channel 4 is disabled (adc_csr[4] = 0), adc_seqr1, a dc_seqr2 register bitfields usch1 up to usch16 must not contain the value 4. thus the length of the user sequence may be limited by this behavior. as an example, if only 4 channels over 16 (ch0 up to ch3) are selected for adc conversions, the user sequence length cannot exceed 4 channels. each trigger event may launch up to 4 suc- cessive conversions of any combination of channel s 0 up to 3 but no more (i.e. in this case the sequence ch0, ch0, ch1, ch1, ch1 is impossible). a sequence that repeats several times the same channel requires more enabled channels than channels actually used for conversion. for example, a sequence like ch0, ch0, ch1, ch1 requires 4 enabled channels (4 free channels on application boards) whereas only ch0, ch1 are really converted. note: the reference voltage pins always remain connected in normal mode as in sleep mode. 33.6.7 comparison window the adc controller features automatic comparison functions. it compares converted values to a low threshold or a high threshold or both, according to the cmpmode function chosen in the extended mode register (adc_emr). the comparison can be done on all channels or only on the channel specified in cmpsel field of adc_emr. to compare all channels the cmp_all parameter of adc_emr should be set. the flag can be read on the compe bit of the interrupt status register (adc_isr) and can trig- ger an interrupt. the high threshold and the low threshold can be read/write in the comparison window regis- ter (adc_cwr). 33.6.8 adc timings each adc has its own minimal startup time that is programmed through the field startup in the mode register, adc_mr. a minimal tracking time is necessary for the adc to guarantee the best converted final value between two channel selections. this time has to be programmed through the tracktim bit field in the mode register, adc_mr.
658 11011a?atarm?04-oct-10 sam3n 658 11011a?atarm?04-oct-10 sam3n warning: no input buffer amplifier to isolate the source is included in the adc. this must be taken into consideration to program a precise value in the tracktim field. see the product adc characteristics section. 33.6.9 buffer structure the pdc read channel is triggered each time new data is stored in adc_lcdr register. the same structure of data is repeatedly stored in adc_lcdr register each time a trigger event occurs. depending on user mode of operat ion (adc_mr, adc_chsr, adc_seqr1, adc_seqr2) the structure differs. each data transferred to pdc buffer, carried on a half-word (16-bit), consists of last converted data right aligned and when tag is set in adc_emr register, the 4 most significant bits are carrying the channel number thus allowing an easier post-process- ing in the pdc buffer or better checking the pdc buffer integrity. 33.6.10 write protection registers to prevent any single software error that ma y corrupt adc behavior, certain address spaces can be write-protected by setting the wpen bit in the ?adc write protect mode register? (adc_wpmr). if a write access to the protecte d registers is detected, then th e wpvs flag in the adc write pro- tect status register (adc_wpsr) is set and t he field wpvsrc indicates in which register the write access has been attempted. the wpvs flag is reset by writing the adc wr ite protect mode register (adc_wpmr) with the appropriate access key, wpkey. the protected registers are: ?adc mode register? on page 661 ?adc channel sequence 1 register? on page 663 ?adc channel sequence 2 register? on page 664 ?adc channel enable register? on page 665 ?adc channel disable register? on page 666 ?adc extended mode register? on page 674 ?adc compare window register? on page 675
659 11011a?atarm?04-oct-10 sam3n 659 11011a?atarm?04-oct-10 sam3n 33.7 analog-to-digital conv erter (adc) user interface any offset not listed in table 33-4 must be considered as ?reserved?. note: if an offset is not listed in the table it must be considered as ?reserved?. table 33-4. register mapping offset register name access reset 0x00 control register adc_cr write-only ? 0x04 mode register adc_mr read-write 0x00000000 0x08 channel sequence register 1 adc_seqr1 read-write 0x00000000 0x0c channel sequence register 2 adc_seqr2 read-write 0x00000000 0x10 channel enable register adc_cher write-only ? 0x14 channel disable register adc_chdr write-only ? 0x18 channel status register adc_chsr read-only 0x00000000 0x1c reserved ? ? ? 0x20 last converted data register adc_lcdr read-only 0x00000000 0x24 interrupt enable register adc_ier write-only ? 0x28 interrupt disable register adc_idr write-only ? 0x2c interrupt mask register adc_imr read-only 0x00000000 0x30 interrupt status regist er adc_isr read-only 0x00000000 0x34 reserved ? ? ? 0x38 reserved ? ? ? 0x3c overrun status register adc_over read-only 0x00000000 0x40 extended mode register adc_emr read-write 0x00000000 0x44 compare window register adc_cwr read-write 0x00000000 0x50 channel data register 0 adc_cdr0 read-only 0x00000000 0x54 channel data register 1 adc_cdr1 read-only 0x00000000 ... ... ... ... ... 0x8c channel data register 15 adc_cdr15 read-only 0x00000000 - 0x90 reserved ? ? ? 0x98 - 0xac reserved ? ? ? 0xc4 - 0xe0 reserved ? ? ? 0xe4 write protect mode register adc_wpmr read-write 0x00000000 0xe8 write protect status regi ster adc_wpsr read-only 0x00000000 0xec - 0xf8 reserved ? ? ? 0xfc reserved ? ? ?
660 11011a?atarm?04-oct-10 sam3n 660 11011a?atarm?04-oct-10 sam3n 33.7.1 adc control register name: adc_cr address: 0x40038000 access: write-only ? swrst: software reset 0 = no effect. 1 = resets the adc simulating a hardware reset. ? start: start conversion 0 = no effect. 1 = begins analog-to-digital conversion. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????startswrst
661 11011a?atarm?04-oct-10 sam3n 661 11011a?atarm?04-oct-10 sam3n 33.7.2 adc mode register name: adc_mr address: 0x40038004 access: read-write this register can only be written if the wpen bit is cleared in ?adc write protect mode register? on page 677 . ? trgen: trigger enable ? trgsel: trigger selection ? lowres: resolution ? sleep: sleep mode 31 30 29 28 27 26 25 24 useq ? ? ? tracktim 23 22 21 20 19 18 17 16 ???? startup 15 14 13 12 11 10 9 8 prescal 76543210 freerun fwup sleep lowres trgsel trgen value name description 0 dis hardware triggers are disabled. starting a conversion is only possible by software. 1 en hardware trigger selected by trgsel field is enabled. value name description 0 adc_trig0 external trigger 1 adc_trig1 tio output of the timer counter channel 0 2 adc_trig2 tio output of the timer counter channel 1 3 adc_trig3 tio output of the timer counter channel 2 4 adc_trig4 reserved 5 adc_trig5 reserved 6 adc_trig6 reserved 7?reserved value name description 0 bits_10 10-bit resolution 1 bits_8 8-bit resolution value name description 0 normal normal mode: the adc core and reference vo ltage circuitry are kept on between conversions 1 sleep sleep mode: the adc core and reference voltage circuitry are off between conversions
662 11011a?atarm?04-oct-10 sam3n 662 11011a?atarm?04-oct-10 sam3n ?fwup: fast wake up ? freerun: free run mode ? prescal: prescaler rate selection adcclock = mck / ( (prescal+1) * 2 ) ? startup: start up time ? tracktim: tracking time tracking time = (tracktim + 1) * adcclock periods. ? useq: use sequence enable value name description 0 off normal sleep mode: the sleep mode is defined by the sleep bit 1 on fast wake up sleep mode: the voltage referenc e is on between conversions and adc core is off value name description 0offnormal mode 1 on free run mode: never wait for any trigger. value name description 0 sut0 0 periods of adcclock 1 sut8 8 periods of adcclock 2 sut16 16 periods of adcclock 3 sut24 24 periods of adcclock 4 sut64 64 periods of adcclock 5 sut80 80 periods of adcclock 6 sut96 96 periods of adcclock 7 sut112 112 periods of adcclock 8 sut512 512 periods of adcclock 9 sut576 576 periods of adcclock 10 sut640 640 periods of adcclock 11 sut704 704 periods of adcclock 12 sut768 768 periods of adcclock 13 sut832 832 periods of adcclock 14 sut896 896 periods of adcclock 15 sut960 960 periods of adcclock value name description 0 num_order normal mode: the controller converts channels in a simple numeric order. 1 reg_order user sequence mode: the sequence respects wh at is defined in adc_seqr1 and adc_seqr2 registers.
663 11011a?atarm?04-oct-10 sam3n 663 11011a?atarm?04-oct-10 sam3n 33.7.3 adc channel sequence 1 register name: adc_seqr1 address: 0x40038008 access: read-write this register can only be written if the wpen bit is cleared in ?adc write protect mode register? on page 677 . ? uschx: user sequence number x the sequence number x (uschx) can be programmed by the channel number chy where y is the value written in this field. the allowed range is 0 up to 15. so it is only possible to use the sequencer from ch0 to ch15. this register activates only if adc_mr(useq) field is set to ?1?. any uschx field is taken into account only if adc_chsr(chx) register field reads logical ?1? else any value written in uschx does not add the corresponding channel in the conversion sequence. configuring the same value in different fields leads to multiple samples of the same channel during the conversion sequence. this can be done consecutively, or not, according to user needs. 31 30 29 28 27 26 25 24 usch8 usch7 23 22 21 20 19 18 17 16 usch6 usch5 15 14 13 12 11 10 9 8 usch4 usch3 76543210 usch2 usch1
664 11011a?atarm?04-oct-10 sam3n 664 11011a?atarm?04-oct-10 sam3n 33.7.4 adc channel sequence 2 register name: adc_seqr2 address: 0x4003800c access: read-write this register can only be written if the wpen bit is cleared in ?adc write protect mode register? on page 677 . ? uschx: user sequence number x the sequence number x (uschx) can be programmed by the channel number chy where y is the value written in this field. the allowed range is 0 up to 15. so it is only possible to use the sequencer from ch0 to ch15. this register activates only if adc_mr(useq) field is set to ?1?. any uschx field is taken into account only if adc_chsr(chx) register field reads logical ?1? else any value written in uschx does not add the corresponding channel in the conversion sequence. configuring the same value in different fields leads to multiple samples of the same channel during the conversion sequence. this can be done consecutively, or not, according to user needs. 31 30 29 28 27 26 25 24 usch16 usch15 23 22 21 20 19 18 17 16 usch14 usch13 15 14 13 12 11 10 9 8 usch12 usch11 76543210 usch10 usch9
665 11011a?atarm?04-oct-10 sam3n 665 11011a?atarm?04-oct-10 sam3n 33.7.5 adc channel enable register name: adc_cher address: 0x40038010 access: write-only this register can only be written if the wpen bit is cleared in ?adc write protect mode register? on page 677 . ? chx: channel x enable 0 = no effect. 1 = enables the corresponding channel. note: if useq = 1 in adc_mr register, chx corresponds to the xth channel of the sequence described in adc_seqr1 and adc_seqr2. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0
666 11011a?atarm?04-oct-10 sam3n 666 11011a?atarm?04-oct-10 sam3n 33.7.6 adc channel disable register name: adc_chdr address: 0x40038014 access: write-only this register can only be written if the wpen bit is cleared in ?adc write protect mode register? on page 677 . ? chx: channel x disable 0 = no effect. 1 = disables the corresponding channel. warning: if the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conver- sion, its associated data and its corresponding eoc and ovre flags in adc_sr are unpredictable. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0
667 11011a?atarm?04-oct-10 sam3n 667 11011a?atarm?04-oct-10 sam3n 33.7.7 adc channel status register name: adc_chsr address: 0x40038018 access: read-only ? chx: channel x status 0 = corresponding c hannel is disabled. 1 = corresponding channel is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0
668 11011a?atarm?04-oct-10 sam3n 668 11011a?atarm?04-oct-10 sam3n 33.7.8 adc last conv erted data register name: adc_lcdr address: 0x40038020 access: read-only ? ldata: last data converted the analog-to-digital conversion data is pl aced into this register at the end of a conversion and remains until a new conver- sion is completed. ? chnb: channel number indicates the last converted channel when the tag option is set to 1 in adc_emr register. if tag option is not set, chnb = 0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 chnb ldata 76543210 ldata
669 11011a?atarm?04-oct-10 sam3n 669 11011a?atarm?04-oct-10 sam3n 33.7.9 adc interrupt enable register name: adc_ier address: 0x40038024 access: write-only ? eocx: end of conversion interrupt enable x ? drdy: data ready interrupt enable ? govre: general overrun error interrupt enable ? compe: comparison event interrupt enable ? endrx: end of receive buffer interrupt enable ? rxbuff: receive buffer full interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ? ? ? rxbuff endrx compe govre drdy 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 eoc15 eoc14 eoc13 eoc12 eoc11 eoc10 eoc9 eoc8 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0
670 11011a?atarm?04-oct-10 sam3n 670 11011a?atarm?04-oct-10 sam3n 33.7.10 adc interrupt disable register name: adc_idr address: 0x40038028 access: write-only ? eocx: end of conversion interrupt disable x ? drdy: data ready interrupt disable ? govre: general overrun error interrupt disable ? compe: comparison event interrupt disable ? endrx: end of receive buffer interrupt disable ? rxbuff: receive buffer full interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ? ? ? rxbuff endrx compe govre drdy 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 eoc15 eoc14 eoc13 eoc12 eoc11 eoc10 eoc9 eoc8 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0
671 11011a?atarm?04-oct-10 sam3n 671 11011a?atarm?04-oct-10 sam3n 33.7.11 adc interrupt mask register name: adc_imr address: 0x4003802c access: read-only ? eocx: end of conversion interrupt mask x ? drdy: data ready interrupt mask ? govre: general overrun error interrupt mask ? compe: comparison event interrupt mask ? endrx: end of receive buffer interrupt mask ? rxbuff: receive buffer full interrupt mask 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ? ? ? rxbuff endrx compe govre drdy 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 eoc15 eoc14 eoc13 eoc12 eoc11 eoc10 eoc9 eoc8 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0
672 11011a?atarm?04-oct-10 sam3n 672 11011a?atarm?04-oct-10 sam3n 33.7.12 adc interrupt status register name: adc_isr address: 0x40038030 access: read-only ? eocx: end of conversion x 0 = corresponding analog channel is disabled , or the conversion is not finished. this flag is cleared when reading the cor- responding adc_cdrx registers. 1 = corresponding analog channel is enabled and conversion is complete. ? drdy: data ready 0 = no data has been converted since the last read of adc_lcdr. 1 = at least one data has been conv erted and is ava ilable in adc_lcdr. ? govre: general overrun error 0 = no general overrun error occurred since the last read of adc_isr. 1 = at least one general overrun error has occurred since the last read of adc_isr. ? compe: comparison error 0 = no comparison error since the last read of adc_isr. 1 = at least one comparison error has occurred since the last read of adc_isr. ? endrx: end of rx buffer 0 = the receive counter register has not reach ed 0 since the last write in adc_rcr or adc_rncr. 1 = the receive counter register has reached 0 since the last write in adc_rcr or adc_rncr. ? rxbuff: rx buffer full 0 = adc_rcr or adc_rncr ha ve a value other than 0. 1 = both adc_rcr and adc_rncr have a value of 0. 31 30 29 28 27 26 25 24 ? ? ? rxbuff endrx compe govre drdy 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 eoc15 eoc14 eoc13 eoc12 eoc11 eoc10 eoc9 eoc8 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0
673 11011a?atarm?04-oct-10 sam3n 673 11011a?atarm?04-oct-10 sam3n 33.7.13 adc overrun status register name: adc_over address: 0x4003803c access: read-only ? ovrex: overrun error x 0 = no overrun error on the corresponding channel since the last read of adc_over. 1 = there has been an overrun error on the corres ponding channel since the last read of adc_over. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ovre15 ovre14 ovre13 ovre12 ovre11 ovre10 ovre9 ovre8 76543210 ovre7 ovre6 ovre5 ovre4 ovre3 ovre2 ovre1 ovre0
674 11011a?atarm?04-oct-10 sam3n 674 11011a?atarm?04-oct-10 sam3n 33.7.14 adc extended mode register name: adc_emr address: 0x40038040 access: read-write this register can only be written if the wpen bit is cleared in ?adc write protect mode register? on page 677 . ? cmpmode: comparison mode ? cmpsel: comparison selected channel if cmpall = 0: cmpsel indicates wh ich channel has to be compared. if cmpall = 1: no effect. ? cmpall: compare all channels 0 = only channel indicated in cmpsel field is compared. 1 = all channels are compared. ? tag: tag of adc_ldcr register 0 = set chnb to zero in adc_ldcr. 1 = append the channel number to the conversion result in adc_ldcr register. 31 30 29 28 27 26 25 24 ???????tag 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????cmpall? 76543210 cmpsel ? ? cmpmode value name description 0 low generates an event when the converted data is lower than the low threshold of the window. 1 high generates an event when the converted data is higher than the high threshold of the window. 2 in generates an event when the conver ted data is in the comparison window. 3 out generates an event when the convert ed data is out of the comparison window.
675 11011a?atarm?04-oct-10 sam3n 675 11011a?atarm?04-oct-10 sam3n 33.7.15 adc compare window register name: adc_cwr address: 0x40038044 access: read-write this register can only be written if the wpen bit is cleared in ?adc write protect mode register? on page 677 . ? lowthres: low threshold low threshold associated to compare settings of adc_emr register. ? highthres: high threshold high threshold associated to compare settings of adc_emr register. 31 30 29 28 27 26 25 24 ???? highthres 23 22 21 20 19 18 17 16 highthres 15 14 13 12 11 10 9 8 ???? lowthres 76543210 lowthres
676 11011a?atarm?04-oct-10 sam3n 676 11011a?atarm?04-oct-10 sam3n 33.7.16 adc channel data register name: adc_cdrx [x=0..15] address: 0x40038050 access: read-only ? data: converted data the analog-to-digital conversion data is pl aced into this register at the end of a conversion and remains until a new conver- sion is completed. the convert data re gister (cdr) is only loaded if the corr esponding analog channel is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? data 76543210 data
677 11011a?atarm?04-oct-10 sam3n 677 11011a?atarm?04-oct-10 sam3n 33.7.17 adc write protect mode register name: adc_wpmr address: 0x400380e4 access: read-write ? wpen: write protect enable 0 = disables the write protect if wpkey corresponds to 0x4144 43 (?adc? in ascii). 1 = enables the write protect if wpkey corresponds to 0x414443 (?adc? in ascii). protects the registers: ?adc mode register? on page 661 ?adc channel sequence 1 register? on page 663 ?adc channel sequence 2 register? on page 664 ?adc channel enable register? on page 665 ?adc channel disable register? on page 666 ?adc extended mode register? on page 674 ?adc compare window register? on page 675 ? wpkey: write protect key should be written at value 0x414443 (?adc? in ascii). writing any other value in this field aborts the write operation of the wpen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 ???????wpen
678 11011a?atarm?04-oct-10 sam3n 678 11011a?atarm?04-oct-10 sam3n 33.7.18 adc write protect status register name: adc_wpsr address: 0x400380e8 access: read-only ? wpvs: write protect violation status 0 = no write protect violation has occurred since the last read of the adc_wpsr register. 1 = a write protect violation has occurred since the last read of the adc_wpsr register. if this violation is an unauthor- ized attempt to write a protected register, the associated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. reading adc_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 ???????wpvs
679 11011a?atarm?04-oct-10 sam3n 34. digital to analog converter controller (dacc) 34.1 description the digital-to-analog converter controller (dacc) has one analog output, making it possible for the digital-to-analog conversion to drive one analog line. the dacc supports 10-bit resolution and data to be converted are sent in a common register. external triggers, through the ext_trig pins, or internal triggers are configurable. the dacc controller connects with a pdc channel. this feature reduces processor intervention. finally, the user can configure dacc timings such as startup time and the internal trigger period. 34.2 embedded characteristics ? 1 channel 10-bit dac ? up to 500 ksamples/s conversion rate ? flexible conversion range ? multiple trigger sources ? one pdc channel
680 11011a?atarm?04-oct-10 sam3n 34.3 block diagram figure 34-1. digital-to-analog converter controller block diagram dac controller trigger s election control logic u s er interf a ce dac cell dac core dac0 datrg interr u pt controller dacc interr u pt pdc ahb apb peripher a l bridge
681 11011a?atarm?04-oct-10 sam3n 34.4 signal description 34.5 product dependencies 34.5.1 power management the dac can be enabled and disabled through the dacen bit of the dacc mode register . 34.5.2 interrupt sources the dacc interrupt line is connected on one of the internal sources of the interrupt controller. using the dacc interrupt requires the interrupt controller to be programmed first. 34.5.3 conversion performances for performance and electrical characteristics of the dac, see the product dc characteristics section. table 34-1. dac pin description pin name description dac0 analog output channel datrg external triggers table 34-2. peripheral ids instance id dacc 30
682 11011a?atarm?04-oct-10 sam3n 34.6 functional description 34.6.1 digital-to-analog conversion the dac uses the master clock (mck) to perform conversions. once a conversion has started, the dac will take a setup time to provide the analog result on the analog output. refer to the product electrical characteristics for more information. 34.6.2 conversion results when a conversion is completed, the resulti ng analog value is available at the dac channel output. 34.6.3 conversion triggers in internal trigger mode, conversion starts as soon as the dacc is enabled, data is written in the dacc conversion data register and an internal trigger event occurs (see figure 34-2 ). the internal trigger frequency is configurable through the clkdiv field of the dacc mode register and must not be above the maximum frequency allowed by the dac. in external trigger mode, the conversion waits for a rising edge event on the selected trigger to begin (see figure 34-3 ). warning: disabling the external trigger mode will auto matically set the dacc in internal trigger mode. figure 34-2. internal trigger figure 34-3. external trigger clkdiv/2 clkdiv clkdiv clkdiv txrdy write dacc_cdr intern a l trigger dacc conver s ion d a t a 1d a t a 2d a t a3 d a t a 4 d a t a 1d a t a 2d a t a3 d a t a 4 012 3 4 3 210 n u m b er of b yte s in fifo txrdy write dacc_cdr extern a l trigger dacc conver s ion d a t a 1d a t a 2d a t a3 d a t a 4 d a t a 1d a t a 2d a t a3 d a t a 4 d a t a 5 d a t a 5 01 2 3 2 3 4 3 21 0 n u m b er of b yte s in fifo
683 11011a?atarm?04-oct-10 sam3n 34.6.4 conversion fifo to provide flexibility and high efficiency, a 4 half-word fifo is used to handle the data to be converted. as long as the txrdy flag in the dacc interrupt status register is active the dac controller is ready to accept conversion requ ests by writing data in the dacc conversion data register (dacc_cdr). data which cannot be converted immediately are stored in the dacc fifo. when the fifo is full or the dacc is not ready to accept conversion requests, the txrdy flag is inactive. warning: writing in the dacc_cdr register while txrdy flag is inactive will corrupt fifo data. 34.6.5 conversion width the word field of the dacc mode register allows the user to switch between half-word and word transfer. in half-word transfer mode only one 10-bit data item is sampled (dacc_mr[9:0]) per dacc_cdr register write. in word transfer mode each time the dacc_cdr register is written 2 data items are sampled. first data item sampled for conversion will be dacc_cdr[9:0] and the second dacc_cdr[25:16]. 34.6.6 dac timings the dac startup time must be defined by the user in the startup field of the dacc mode register . the dac maximum clock frequency is 13 mhz, therefore the internal trigger period can be con- figured through the clkdiv field of the dacc mode register . 34.6.7 write protection registers in order to bring security to the dacc, a write protection system has been implemented. the write protection mode prevents the write of the dacc mode register . when this mode is enabled and the protected register is written an error is generated in the dacc write protect status register and the register write request is canceled. when a write protection error occurs, the wproterr flag is set and the address of the corresponding canceled register write is available in the wprotadrr field of the dacc write protect status register . due to the nature of the write protection feature, enabling and disabling the write protection mode requires the use of a security code. thus when enabling or disabling the write protection mode, the wpkey field of the dacc write protect mode register must be filled with the ?dac? ascii code (corresponding to 0x444143) othe rwise the register write will be canceled.
684 11011a?atarm?04-oct-10 sam3n 34.7 digital-to-analog converter c ontroller (dacc) user interface table 34-3. register mapping offset register name access reset 0x00 control register dacc_cr write-only ? 0x04 mode register dacc_mr read-write 0x00000000 0x08 conversion data register dacc_cdr write-only 0x00000000 0x0c interrupt enable register dacc_ier write-only ? 0x10 interrupt disable register dacc_idr write-only ? 0x14 interrupt mask register dacc_imr read-only 0x00000000 0x18 interrupt status register dacc_isr read-only 0x00000000 0xe4 write protect mode register dacc_wpmr read-write 0x00000000 0xe8 write protect status register dacc_wpsr read-only 0x00000000 ... ... ... ... ... 0xec - 0xfc reserved ? ? ?
685 11011a?atarm?04-oct-10 sam3n 34.7.1 dacc control register name: dacc_cr address: 0x4003c000 access: write-only ? swrst: software reset 0 = no effect. 1 = resets the dacc simulating a hardware reset. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????swrst
686 11011a?atarm?04-oct-10 sam3n 34.7.2 dacc mode register name: dacc_mr address: 0x4003c004 access: read-write ? trgen: trigger enable ? trgsel: trigger selection ? dacen: dac enable 0 = dac disabled. 1 = dac enabled. ? word: word transfer 31 30 29 28 27 26 25 24 clkdiv 23 22 21 20 19 18 17 16 clkdiv 15 14 13 12 11 10 9 8 startup 76543210 ? ? word dacen trgsel trgen trgen selected mode 0 external trigger mode disabled. dacc in free running mode. 1 external trigger mode enabled. value name description 0 trgsel0 external trigger 1 trgsel1 tio output of t he timer counter channel 0 2 trgsel2 tio output of t he timer counter channel 1 3 trgsel3 tio output of t he timer counter channel 2 4 trgsel4 reserved 5 trgsel5 reserved 6 trgsel6 reserved 7 reserved word selected resolution 0 half-word transfer 1 word transfer
687 11011a?atarm?04-oct-10 sam3n ? startup: startup time selection startup time = (startup+1) * clock period ? clkdiv: dac clock divider for internal trigger trigger period = clkdiv * clock period
688 11011a?atarm?04-oct-10 sam3n 34.7.3 dacc conversi on data register name: dacc_cdr address: 0x4003c008 access: write-only ? data: data to convert data to convert. can be one half-word or two half -word s depending on word bit in dacc_mr register. 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data
689 11011a?atarm?04-oct-10 sam3n 34.7.4 dacc interrupt enable register name: dacc_ier address: 0x4003c00c access: write-only ? txrdy: transmission ready interrupt enable enables ready for transmission interrupt. ? endtx: end of pdc interrupt enable ? txbufe: buffer empty interrupt enable enables end of conversion it. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????txbufeendtxtxrdy
690 11011a?atarm?04-oct-10 sam3n 34.7.5 dacc interrupt disable register name: dacc_idr address: 0x4003c010 access: write-only ? txrdy: transmission ready interrupt disable disables ready for transmission interrupt. ? endtx: end of pdc interrupt disable ? txbufe: buffer empty interrupt disable 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????txbufeendtxtxrdy
691 11011a?atarm?04-oct-10 sam3n 34.7.6 dacc interrupt mask register name: dacc_imr address: 0x4003c014 access: read-only ? txrdy: transmission ready interrupt mask ? endtx: end of pdc interrupt mask ? txbufe: buffer empty interrupt mask 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????txbufeendtxtxrdy
692 11011a?atarm?04-oct-10 sam3n 34.7.7 dacc interrupt status register name: dacc_isr address: 0x4003c018 access: read-only ? txrdy: transmission ready interrupt flag ? endtx: end of pdc interrupt flag ? txbufe: buffer empty interrupt flag 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????txbufeendtxtxrdy
693 11011a?atarm?04-oct-10 sam3n 34.7.8 dacc write protect mode register name: dacc_wpmr address: 0x4003c0e4 access: read-write ? wpen: write protect enable 0 = disables the write protect if wpkey corresponds to 0x4441 43 (?dac? in ascii). 1 = enables the write protect if wpkey corresponds to 0x444143 (?dac? in ascii). protects the dacc mode register . ? wpkey: write protect key this security code is needed to set/reset the wprot bit value (see section 34.6.7 ?write protection registers? for details). must be filled with ?dac? ascii code. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 ???????wpen
694 11011a?atarm?04-oct-10 sam3n 34.7.9 dacc write protect status register name: dacc_wpsr address: 0x4003c0e8 access: read-only ? wproterr: write protection error indicates a write protection error. ? wprotaddr: write protection error address indicates the address of the register write request which generated the error. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 wprotaddr 76543210 ???????wproterr
695 11011a?atarm?04-oct-10 sam3n 35. electrical characteristics 35.1 absolute maximum ratings table 35-1. absolute maximum ratings* operating temperature (in dustrial) ................-40 c to + 85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indi- cated in the operational sectio ns of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature.....................................-60c to + 150c voltage on input pins with respect to ground...... ..............................-0.3v to + 4.0v maximum operating voltage (vddcore) ................ .............. .............. ........... ........... ....2.0v maximum operating voltage (vddio)............................................................................4.0v total dc output current on all i/o lines 100-lead lqfp............. .............. .............. .............. ........150 ma 100-ball lfbga.............................................................150 ma 64-lead lqfp............ .............. ............ ........... ........... .....100 ma 48-lead lqfp............ .............. ............ ........... ........... .....100 ma 64-pad qfn...... .............. .............. .............. .............. .....100 ma 48-pad qfn...... .............. .............. .............. .............. .....100 ma
696 11011a?atarm?04-oct-10 sam3n 35.2 dc characteristics the following characteristi cs are applicable to the operating temperature range: t a = -40c to 85c, unless otherwise specified table 35-2. dc characteristics symbol parameter conditions min typ max unit s v ddcore dc supply core 1.62 1.8 1.95 v v vddio dc supply i/os (2) (3) 1.62 3.3 3.6 v v vddpll pll and main oscillator supply 1.62 1.95 v v il input low-level voltage pa0-pa3 1, pb0-pb14, pc0-pc31 -0.3 0.3 x v vddio v v ih input high-level voltage pa0-pa31, pb0-pb14, pc0-pc31 0.7 x v vddio v vddio +0.3v v v oh output high-level voltage pa0-pa31, pb0-pb14, pc0-pc31 i oh ~ 0 i oh > 0 (see i oh details below) 0.2 0.4 v v ol output low-level voltage pa0-pa31, pb0-pb14, pc0-pc31 i oh ~ 0 i oh > 0 (see i ol details below) v vddio -0.2v v vddio -0.4v v v hys hysteresis voltage pa0-pa31, pb0-pb14, pc0-pc31 (hysteresis mode enabled) 150 500 mv erase, tst, jtagsel 230 700 mv
697 11011a?atarm?04-oct-10 sam3n note: 1. pa[4-13], pa[15- 28], pb[0-14], pc[0-31] 2. at power-up vddio needs to reac h 0.6v before vddin reaches 1.0v 3. vddio voltage needs to be equal or below to (vddin voltage +0.5v) i o i oh (or i source ) 1.62v < vddio < 1.95v; v oh = v vddio - 0.4 - pa14 (spck), pins - pa 0 - pa 3 - other pins (1) -6 -6 -3 ma 3.0v < vddio < 3.6v; v oh = v vddio - 0.4 - pa14 (spck), pins - pa 0 - pa 3 - other pins (1) -6 -6 -3 1.62v < vddio < 3.6v; v oh = v vddio - 0.4 - nrst -2 relaxed mode: 3.0v < vddio < 3.6v; v oh = 2.2v - pa14 (spck), pins - pa 0 - pa 3 - other pins (1) -14 -16 -8 i ol (or i sink ) 1.62v < vddio < 1.95v; v ol = 0.4v - pa14 (spck), pins - pa 0 - pa 3 - other pins (1) 8 8 4 ma 3.0v < vddio < 3.6v; v ol = 0.4v - pa14 (spck), pins - pa 0 - pa 3 - other pins (1) 9 12 6 1.62v < vddio < 3.6v; v ol = 0.4v - nrst 2 relaxed mode: 3.0v < vddio < 3.6v; v ol = 0.6v - pa14 (spck), pins - pa 0 - pa 3 - other pins (1) 14 18 9 i il input low leakage current no pull-up or pull-down; v in= gnd; v ddio max. (typ: t a = 25c, max: t a = 85c) 530na i ih input high leakage current no pull-up or pull-down; v in= vdd; v ddio max. (typ: t a = 25c, max: t a = 85c) 218na r pullup pull-up resistor pa0-pa31, pb0-pb14, pc0-pc31 50 100 175 k nrst 50 100 175 k r pulldown pull-down resistor pa0-pa31, pb0-pb14, pc0-pc31 tst, jtagsel 50 10 100 175 20 k r odt on-die series termination resistor pa4-pa31, pb0-pb14,pc0-pc31 pa 0 - pa 3 36 18 c in input capacitance digital inputs tbd pf table 35-2. dc characteristics (continued) symbol parameter conditions min typ max unit s
698 11011a?atarm?04-oct-10 sam3n notes: 1. a 10f or higher ceramic capacitor must be connec ted between vddin and the closest gnd pin of the device. this large decoupling capacitor is mandatory to reduce star tup current, improving transient response and noise rejection. 2. to ensure stability, an exte rnal 1f output capacitor, cd out must be connected between the vddout and the closest gnd pin of the device. the esr (equivalent series resistance) of the capacitor must be in the range 0.1 to 10 ohms. solid tantalum, and multilayer ceramic capacitors are all suitable as output capacitor. a 100nf bypass capacitor between vddout and the closest gn d pin of the device helps decreasing output noise and improves the load transient response. 3. at power-up vddio needs to reac h 0.6v before vddin reaches 1.0v 4. vddio voltage needs to be equal or below to (vddin voltage +0.5v) table 35-3. 1.8v voltage regulator characteristics symbol parameter conditions min typ max units v vddin dc input voltage range (3) (4) 1.8 3.3 3.6 v v vddout dc output voltage normal mode standby mode 1.8 0 v v accuracy output voltage accuracy i load = 0.5 ma to 60 ma -3 3 % i load maximum dc output current v vddin > 2v v vddin 2v 60 40 ma d dropout dropout voltage v vddin = 1.8v, i load = 60 ma 100 mv v line v line-tr line regulation transient line regulation v vddin from 2.7v to 3.6v; i load max v vddin from 2.7v to 3.6v; tr = tf = 5s; i load max cd out = 1f 20 50 50 100 mv v load v load-tr load regulation transient load regulation v vddin 2.2v; i load = 10% to 90% max v vddin 2.2v; i load = 10% to 90% max tr = tf = 5 s cd out = 1 f 20 50 50 100 mv i q quiescent current normal mode; @ i load = 0 ma @ i load = 60 ma standby mode; 7 700 10 1200 1 a cd in input decoupling capacitor cf. external capacitor requirements (1) 10 f cd out output decoupling capacitor cf. external capacitor requirements (2) esr 0.75 0.1 1 10 f ohm t on tu r n o n t i m e cd out = 1f, v vddout reaches v th+ (core power brownout detector supply rising threshold) 100 200 s t off turn off time cd out = 1f 40 ms
699 11011a?atarm?04-oct-10 sam3n note: 1. the product is guaranteed to be functional at v th- figure 35-1. core brownout output waveform table 35-4. core power supply brownout detector char acteristics symbol parameter conditions min typ max units v th- supply falling threshold (1) 1.52 1.55 1.58 v v hyst- hysteresis v th- 25 38 mv v th+ supply rising threshold 1.35 1.50 1.59 v v hyst+ hysteresis v th+ 100 170 250 mv i ddon i ddoff current consumption on vddcore brownout detector enabled brownout detector disabled 18 200 a na td- v th- detection propagation time vddcore = v th+ to ( v th- - 100mv) 200 ns t start startup time from disabled state to enabled state 100 200 s t vddcore vth- vth+ bod output t td+ td-
700 11011a?atarm?04-oct-10 sam3n figure 35-2. vddio supply monitor figure 35-3. zero-power-on reset characteristics table 35-5. vddio supply monitor symbol parameter conditions min typ max units v th supply monitor threshold 16 selectable steps of 100mv 1.9 3.4 v t accuracy threshold level accuracy -1.5 +1.5 % v hyst hysteresis 20 30 mv i ddon i ddoff current consumption on vddcore enabled disabled 18 28 1 a t start startup time from disabled state to enabled state 140 s v th v hy s t vddio re s et v th + table 35-6. zero-power-on reset characteristics symbol parameter conditions min typ max units v th+ threshold voltage rising at startup 1.46 1.55 1.60 v v th- threshold voltage falling 1.36 1.45 1.54 v tres reset time-out period 40 90 150 s v th- v th+ vddio re s et
701 11011a?atarm?04-oct-10 sam3n table 35-7. dc flash characteristics symbol parameter conditions typ max units i sb standby current @25c onto vddcore = 1.8v @85c onto vddcore = 1.8v @25c onto vddcore = 1.95v @85c onto vddcore = 1.95v 3.2 6 4 6.5 4 8 1.8 9 a a a a i cc active current 128-bit mode read access: maximum read frequency onto vddcore = 1.8v @ 25 c maximum read frequency onto vddcore = 1.95v @ 25 c 64-bit mode read access: maximum read frequency onto vddcore = 1.8v @ 25 c maximum read frequency onto vddcore = 1.95v @ 25 c 19 25 tbd tbd 22.5 30 tbd tbd ma ma ma ma write onto vddcore = 1.8v @ 25 c write onto vddcore = 1.95v @ 25 c 7.5 5.5 9.5 6.0 ma ma
702 11011a?atarm?04-oct-10 sam3n 35.3 power consumption ? power consumption of the devi ce according to the differen t low power mode capabilities (backup, wait, sleep) and active mode. ? power consumption on power supply in different modes: backup, wait, sleep and active. ? power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. 35.3.1 backup mode current consumption the backup mode configuration and measurements are defined as follow. figure 35-4. measurement setup 35.3.1.1 configuration a ? supply monitor on vddio is disabled ? rtt and rtc not used ? embedded slow clock rc oscillator used ? one wkupx enabled ? current measurement on amp1 (see figure 35-4 ) 35.3.1.2 configuration b ? supply monitor on vddio is disabled ? rtt used ? one wkupx enabled ? current measurement on amp1 (see figure 35-4 ) ? 32 khz crystal oscillator used vddio vddout vddcore vddin volt a ge reg u l a tor vddpll 3 . 3 v amp1
703 11011a?atarm?04-oct-10 sam3n 35.3.2 sleep and wait mode current consumption the wait mode and sleep mode configuration and measurements are defined below. figure 35-5. measurement setup for sleep mode 35.3.2.1 sleep mode ? core clock off ? master clock (mck) running at various freq uencies with pll or the fast rc oscillator. ? fast start-up through wkup0-15 pins ? current measurement as shown in figure figure 35-6 ? all peripheral clocks deactivated table 35-9 gives current consumption in typical conditions. table 35-8. power consumption for backup mode configuration a and b conditions total consumption (amp1) configuration a total consumption (amp1) configuration b unit vddio = 3.3v @25c vddio = 3.0v @25c vddio = 2.5v @25c vddio = 1.8v @25c 2.85 2.55 2.1 1.56 3.25 2.96 2.50 1.89 a vddio = 3.3v @85c vddio = 3.0v @85c vddio = 2.5v @85c vddio = 1.8v @85c tbd tbd tbd tbd tbd tbd tbd tbd a vddio vddout vddcore vddin volt a ge reg u l a tor vddpll 3 . 3 v amp1 table 35-9. typical current consumption for sleep mode conditions vddcore consumption (amp1) total consumption (amp2) unit figure 35-6 @25c mck = 48 mhz there is no activity on the i/os of the device. 6.4 8.4 ma
704 11011a?atarm?04-oct-10 sam3n figure 35-6. current consumption in sleep mode (amp1) versus master clock ranges (conditions from table 35-9 ) table 35-10. sleep mode current consumption versus master clock (mck) variation core clock/mck (mhz) vddcore consumption (amp1) total consumption (amp2) unit 62 8.16 10.7 ma 48 6.4 8.4 32 4.3 5.65 24 3.5 5.5 12 1.68 1.71 81.131.16 40.560.57 20.330.35 10.220.23 0.5 0.16 0.17 0.25 0.14 0.16 0.125 0.12 0.13 0.032 0.01 0.02 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 0 10203040506070 processor and peripheral clocks in mhz iddcore in m a
705 11011a?atarm?04-oct-10 sam3n 35.3.2.2 wait mode figure 35-7. measurement setup for wait mode ? core clock and master clock stopped ? current measurement as shown in the above figure ? all peripheral clocks deactivated table 35-11 gives current consumption in typical conditions. 35.3.3 active mode power consumption the active mode configuration and measurements are defined as follows: ?vddio = vddin = 3.3v ? vddcore = 1.8v (internal voltage regulator used) and 1.62v (external supply) ?t a = 25 c ? recursive fibonacci algorithm or division operation running from flash memory ? all peripheral clocks are deactivated. ? master clock (mck) running at various freq uencies with pll or the fast rc oscillator ? current measurement on amp1 (vddcore) note: 1. recursive fibonacci is a high computation test whereas division operation is a low computa- tion test. table 35-11. typical current consum ption in wait mode conditions vddout consumption (amp1) total consumption (amp2) unit see figure 35-7 on page 705 @25c there is no activity on the i/os of the device. 5.7 14.9 a vddio vddout vddcore vddin volt a ge reg u l a tor vddpll 3 . 3 v amp1 amp2
706 11011a?atarm?04-oct-10 sam3n figure 35-8. active mode measurement setup 35.3.3.1 active power consumption with vddcore @ 1.8v vddio vddout vddcore vddin volt a ge reg u l a tor vddpll 3 . 3 v amp1 table 35-12. master clock (mck) and core clock variation core clock /mck (mhz) amp1 (vddout) consumption unit division fibonacci 128-bit flash access 64-bit flash access 128-bit flash access 64-bit flash access ma 62 30 25.3 31.4 28.55 48 24.45 20.6 26.2 23.15 32 15.6 14.3 20 17.7 24 11.4 10.5 15.6 15 12 6.45 5.7 9.2 8.5 8 4.9 4.2 7.1 6.4 4 4.3 2.9 4.5 2.9 2 2.2 1.5 2.4 1.7 1 1.1 0.84 1.2 0.9
707 11011a?atarm?04-oct-10 sam3n 35.3.3.2 active power consumption with vddcore @ 1.62v 35.3.4 peripheral power consumption in active mode note: 1. note: vddio = 3.3v, v ddcore = 1.80v, t a = 25 c table 35-13. master clock (mck) and core clock variation core clock / mck (mhz) amp1 (vddout) consumption unit division fibonacci 128-bit flash access 64-bit flash access 128-bit flash access 64-bit flash access ma 62 25.7 22.6 27.05 25.2 48 20.8 18 23.2 20.4 32 14.1 12.5 17.2 15.75 24 11.1 9.25 13.65 13.2 12 5.6 5 7.9 7.36 8 4.2 3.6 5.9 5.41 4 3.55 2.4 3.6 5.5 2 1.84 1.3 1.88 1.3 1 1 0.72 1.2 0.72 table 35-14. power consumption on v ddcore (1) peripheral consumption (typ) unit pio controller a (pioa) 10 a/mhz pio controller b (piob) 5.15 pio controller c (pioc) 9.8 uart0 (pdc) 14 uart1 (no pdc) 3.8 usart0 (pdc) 21.2 usart1 (no pdc) 8.2 pwm 10.55 twi0 (pdc) 15.25 twi1 (no pdc) 4.6 spi 12.5 tc0, tc3 9 tc1, tc2, tc4, tc5 5 adc 17.6 dacc 7.75
708 11011a?atarm?04-oct-10 sam3n 35.4 crystal oscillators characteristics 35.4.1 32 khz rc oscillator characteristics 35.4.2 4/8/12 mhz rc oscillators characteristics notes: 1. frequency range can be configured in the supply controller registers 2. not trimmed from factory 3. after trimming from factory table 35-15. 32 khz rc oscillator characteristics symbol parameter conditions min typ max unit rc oscillator frequency 20 32 44 khz frequency supply dependency -3 3 %/v frequency temperature dependency over temperature range (-40c/ +85c) versus 25c -7 7 % duty duty cycle 45 50 55 % t on startup time 100 s i ddon current consumption after startup time temp. range = -40c to +85c typical consumption at 2.2v supply and temp = 25c 540 870 na table 35-16. 4/8/12 mhz rc oscillators characteristics symbol parameter conditions min typ max unit f range rc oscillator frequency range (1) 412mhz acc 4 4 mhz total accuracy -40c 709 11011a?atarm?04-oct-10 sam3n the 4/8/12 mhz fast rc oscillator is ca librated in product ion. this calibration can be read through the get calib bit com- mand (see eefc section) and the frequency can be trimmed by software through the pmc. figure 35-9 and figure 35-10 show the frequency versus trimming for 8 and 12 mhz. figure 35-9. rc 8 mhz trimming figure 35-10. rc 12 mhz trimming
710 11011a?atarm?04-oct-10 sam3n 35.4.3 32.768 khz crystal oscillator characteristics note: 1. r s is the series resistor. c lext = 2x( c crystal ? c para ? c pcb ) where c pcb is the capacitance of the print ed circuit board (pcb) track layout from the crystal to the sam3 pin. 35.4.4 32.768 khz crystal characteristics table 35-17. 32.768 khz crystal oscillator characteristics symbol parameter conditions min typ max unit f req operating frequency normal mode with crystal 32.768 khz supply ripple voltage (on vddio) rms value, 10 khz to 10 mhz 30 mv duty cycle 40 50 60 % startup time rs < 50k rs < 100k (1) c crystal = 12.5pf c crystal = 6pf c crystal = 12.5pf c crystal = 6pf 900 300 1200 500 ms current consumption rs < 50k rs < 100k (1) c crystal = 12.5pf c crystal = 6pf c crystal = 12.5pf c crystal = 6pf 650 450 900 650 1400 1200 1600 1400 na p on drive level 0.1 w r f internal resistor between xin32 and xout32 10 m c lext maximum external capacitor on xin32 and xout32 20 pf c para internal parasitic capacitance 0.8 1 1.2 pf xin 3 2 xout 3 2 c lext c lext s am 3 table 35-18. crystal characteristics symbol parameter conditions min typ max unit esr equivalent series resistor (r s) crystal @ 32.768 khz 50 100 k c m motional capacitance crystal @ 32.768 khz 0.6 3 ff c shunt shunt capacitance crystal @ 32.768 khz 0.6 2 pf
711 11011a?atarm?04-oct-10 sam3n 35.4.5 32.768 khz xin32 clock input characteristics in bypass mode note: 1. these characteristics apply only when the 32768 khz xtal oscillator is in bypass mode (i.e., when oscbypass: = 1 in supc_mr and xtalsel = 1 in the supc_cr registers. table 35-19. xin32 clock electrical characteristics (in bypass mode) symbol parameter conditions min max units 1/(t cpxin32 ) xin32 clock frequency (1) 44 khz t cpxin32 xin32 clock period (1) 22 s t chxin32 xin32 clock high half-period (1) 11 s t clxin32 xin32 clock low half-period (1) 11 s c in xin32 input capacitance 6 pf r in xin32 pull-down resistor 3 5 m v xin32_il v xin32 input low-level voltage -0.3 0.3 x v ddio v v xin32_ih v xin32 input high-level voltage 0.7 x v ddio v ddio +0.3 v t cpxin t cpxin t cpxin t chxin v xin_il v xin_ih
712 11011a?atarm?04-oct-10 sam3n 35.4.6 3 to 20 mhz crystal oscillator characteristics notes: 1. r s is the series resistor 2. rs = 100-200 ohms; cs = 2.0 - 2.5pf; cm = 2 ? 1.5 ff(typ, worst case) using 1 k serial resistor on xout. 3. rs = 50-100 ohms; cs = 2.0 - 2.5p f; cm = 4 - 3 ff(typ, worst case). 4. rs = 25-50 ohms; cs = 2.5 - 3.0p f; cm = 7 - 5 ff (typ, worst case). 5. rs = 20-50 ohms; cs = 3.2 - 4.0pf; cm = 10 - 8 ff(typ, worst case). c lext = 2x( c crystal ? c l ? c pcb ) where c pcb is the capacitance of the print ed circuit board (pcb) track layout from the crystal to the sam3 pin. table 35-20. 3 to 20 mhz crystal oscillator characteristics symbol parameter conditions min typ max unit f req operating frequency normal mode with crystal 3 16 20 mhz f req_bypass operating frequency in bypass mode external clock on xin 50 mhz supply ripple voltage (on vddpll) rms value, 10 khz to 10 mhz 30 mv duty cycle 40 50 60 % t on startup time 3 mhz, c shunt = 3pf 8 mhz, c shunt = 7pf 12 to 16 mhz, c shunt = 7pf 20 mhz, c shunt = 7pf 14.5 4 1.4 1 ms i dd_on current consumption 3 mhz (2) 8 mhz (3) 12 to 16 mhz (4) 20 mhz (5) 150 200 250 350 230 300 350 450 a p on drive level 3 mhz 8 mhz 12 mhz, 16 mhz, 20 mhz 15 30 50 w r f internal resistor between xin and xout 1 m c lext maximum external capacitor on xin and xout 12.5 17.5 pf c l internal equivalent load capacitance integrated load capacitance (xin and xout in series) 7.5 9.5 11.5 pf xin xout c lext c l c lext c cry s t a l s am 3 r=1k if cry s t a l fre qu ency i s lower th a n 8 mhz
713 11011a?atarm?04-oct-10 sam3n 35.4.7 3 to 20 mhz crystal characteristics 35.4.8 3 to 20 mhz xin clock input characteristics in bypass mode note: 1. these characteristics apply only when the 3-20 mhz xtal oscillator is in bypass mode. table 35-21. crystal characteristics symbol parameter conditions min typ max unit esr equivalent series resistor (rs) fundamental @ 3mhz fundamental @ 8mhz fundamental @ 12mhz fundamental @ 16mhz fundamental @ 20mhz 200 100 80 80 50 c m motional capacitance 8ff c shunt shunt capacitance 7pf table 35-22. xin clock electrical characteristics (in bypass mode) symbol parameter conditions min typ max units 1/(t cpxin ) xin clock frequency (1) 50 mhz t cpxin xin clock period (1) 20 ns t chxin xin clock high half-period (1) 8ns t clxin xin clock low half-period (1) 8ns v xin_il v xin input low-level voltage (1) -0.3 0.3 x v vddio v v xin_ih v xin input high-level voltage (1) 0.7 x v vddio v vddio + 0.3 v t cpxin t cpxin t cpxin t chxin v xin_il v xin_ih
714 11011a?atarm?04-oct-10 sam3n 35.4.9 crystal oscillators design consideration information 35.4.9.1 choosing a crystal when choosing a crystal for the 32768 hz slow clock oscillator or for the 3-20 mhz oscillator, several parameters must be taken into account. important parameters between crystal and sam3n specifications are as follows: ? load capacitance ?c crystal is the equivalent capacitor value the oscillator must ?show? to the crystal in order to oscillate at the targ et frequency. the crystal mu st be chosen according to the internal load capacitance (c l ) of the on-chip oscillator. having a mismatch for the load capacitance will result in a frequency drift. ? drive level ? crystal drive level >= oscillator drive level. having a crystal drive level number lower than the oscillator specif ication may damage the crystal. ? equivalent series resistor (esr) ? crystal esr <= oscillator esr max. havi ng a crystal with esr value higher than the oscillator may cause the oscillator to not start. ? shunt capacitance ? max. crystal shunt capacitance <= oscillator shunt capacitance ( c shunt ). having a crystal with esr value higher than the oscilla tor may cause the oscillator to not start. 35.4.9.2 printed circuit board (pcb) sam3n oscillators are low power oscillators requiring particular att ention when designing pcb systems.
715 11011a?atarm?04-oct-10 sam3n 35.5 pll characteristics table 35-23. supply voltage phase lock loop characteristics symbol parameter conditions min typ max unit vddpll supply voltage range 1.6 1.8 1.95 v allowable voltage ripple rms value 10 khz to 10 mhz rms value > 10 mhz 30 10 mv table 35-24. pll characteristics symbol parameter conditions min typ max unit f in input frequency 3.5 20 mhz f out output frequency 60 130 mhz i pll current consumption active mode @ 60 mhz @1.8v active mode @ 96 mhz @1.8v active mode @ 130 mhz @1.8v 1.2 2 2.5 1.7 2.5 3 ma t start settling time 150 s
716 11011a?atarm?04-oct-10 sam3n 35.6 10-bit adc characteristics notes: 1. corresponds to 13 clock cycles at 5 mhz: 3 clock cycles for track and hold ac quisition time and 10 clock cycles for conversion. 2. corresponds to 15 clock cycles at 8 mh z: 5 clock cycles for track and hold acqu isition time and 10 clock cycles for conversion. table 35-25. analog power supply characteristics symbol parameter conditions min typ max units v vddin adc analog supply 3.0 3.6 v i vddin active current consumption on vddin 0.55 1 ma table 35-26. channel conversion time and adc clock parameter conditions min typ max units adc clock frequency 10-bit resolution mode 5 mhz adc clock frequency 8-bit resolution mode 8 mhz startup time return from idle mode 20 s track and hold acquisition time see section 35.6.0.3 ?track and hold time versus source output impedance? for more details 600 ns conversion time adc clock = 5 mhz 2 s conversion time adc clock = 8 mhz 1.25 s throughput rate adc clock = 5 mhz 384 (1) ksps throughput rate adc clock = 8 mhz 533 (2) ksps table 35-27. external voltage reference input parameter conditions min typ max units advref input voltage range 2.6 v ddin v advref input voltage range 8-bit resolution mode 2.5 v ddin v advref average current on 13 samples with adc clock = 5 mhz 200 250 a table 35-28. transfer characteristics parameter conditions min typ max units resolution 10 bit integral non-linearity 2 lsb differential non-linearity no missing code 1 lsb offset error 2 lsb gain error 2 lsb absolute accuracy 4 lsb
717 11011a?atarm?04-oct-10 sam3n . note: 1. input voltage range can be up to vddin without destruction or over-consumption. if vddio < v advref , max input voltage is vddio. 35.6.0.3 track and hold time versus source output impedance the following figure gives a simplified acquisition path. figure 35-11. simplified acquisition path the user can drive adc input with impedance of zsource up to: ? in 8-bit mode: tracktim = 0.1 x zsource + 470 ? in 10-bit mode: tracktim = 0.13 x zsource + 589 with tracktim (track and hold time register) expressed in ns and zsource expressed in ohms. note: csample and ron are taken into account in the formulas 35.6.0.4 adc application information for more information on data converter terminology, please refer to the application note: data converter terminology, atmel lit 6022. http://www.atmel.com/dyn/resources/prod_documents/doc6022.pdf table 35-29. external voltage reference input parameter conditions min typ max units advref input voltage range 2.6 v ddin v advref input voltage range 8-bit resolution mode 2.5 v ddin v advref average current on 13 samples with adc clock = 5 mhz 200 250 a table 35-30. analog inputs parameter min typ max units input voltage range 0v advref input leakage current 1 a input capacitance 12 14 pf sa mple & hold m u x. z s o u rce ron c sa mple adc inp u t 10- b it adc core
718 11011a?atarm?04-oct-10 sam3n 35.7 10-bit dac characteristics external voltage reference for dac is advref. see the adc voltage reference characteristics table 35-29 on page 717 . table 35-31. analog power supply characteristics symbol parameter conditions min typ max units v vddin analog supply 2.4 3.6 v i vddin active current consumption on vddin on advref 485 250 660 300 a a table 35-32. channel conversion time and dac clock symbol parameter conditions min typ max units f dac clock frequency 500 khz t start-up startup time 5s t conv conversion time 1t cp_dac table 35-33. static performance characteristics parameter conditions min typ max units resolution 10 bit integral non-linearity (inl) voltage output range between 0v and (v advref -100 mv). 1 2 lsb differential non-linearity (dnl) no missing error, voltage output range between 0v and (v advref -100 mv). 0.5 -0.9/+1 lsb offset error 15mv gain error 510mv table 35-34. analog outputs parameter conditions min typ max units voltage output range 0v advref v settling/setup time r load = 5k / 0pf < c load < 50pf, 2 s r load output load resistor 5 k c load output load capacitor 50 pf
719 11011a?atarm?04-oct-10 sam3n 35.8 ac characteristics 35.8.1 master clock characteristics 35.8.2 i/o characteristics criteria used to define the maximum frequency of the i/os: ? output duty cycle (40%-60%) ? minimum output swing: 100 mv to vddio - 100 mv ? minimum output swing: 100 mv to vddio - 100 mv ? addition of rising and falling time inferior to 75% of the period notes: 1. pin group 1 = pa14 2. pin group 2 = pa[0-13], pa[15-31], pb[0-14], pc[0-31] table 35-35. master clock waveform parameters symbol parameter conditions min max units 1/(t cpmck ) master clock frequency vddcore @ 1.62v 48 mhz 1/(t cpmck ) master clock frequency vddcore @ 1.80v 62 mhz table 35-36. i/o characteristics symbol parameter conditions min max units freqmax1 pin group 1 (1) maximum output frequency 30 pf v ddio = 1.62v v ddio = 3.0v 45 62 mhz 45 pf v ddio = 1.62v v ddio = 3.0v 34 45 pulseminh 1 pin group 1 (1) high level pulse width 30 pf v ddio = 1.62v v ddio = 3.0v 11 7.7 ns 45 pf v ddio = 1.8v v ddio = 3.0v 14.7 11 pulseminl 1 pin group 1 (1) low level pulse width 30 pf v ddio = 1.62v v ddio = 3.0v 11 7.7 ns 45 pf v ddio = 1.62v v ddio = 3.0v 14.7 11 freqmax2 pin group 2 (2) maximum output frequency load: 25 pf 1.62v < vddio < 3.6v 35 mhz pulseminh 2 pin group 2 (2) high level pulse width load: 25pf 1.62v < vddio < 3.6v 14.5 ns pulseminl 2 pin group 2 (2) low level pulse width load: 25pf 1.62v < vddio < 3.6v 14.5 ns
720 11011a?atarm?04-oct-10 sam3n 35.8.3 spi characteristics figure 35-12. spi master mode with (cpol= ncpha = 0) or (cpol= ncpha= 1) figure 35-13. spi master mode with (cpol = 0 and ncpha=1) or (cpol=1 and ncpha= 0) figure 35-14. spi slave mode with (cpol=0 and ncpha=1) or (cpol=1 and ncpha=0) spck miso mosi spi 2 spi 0 spi 1 spck miso mosi spi 5 spi 3 spi 4 s pck mi s o mo s i s pi 6 s pi 7 s pi 8 npc ss s pi 12 s pi 1 3
721 11011a?atarm?04-oct-10 sam3n figure 35-15. spi slave mode with (cpol = ncpha = 0) or (cpol = ncpha = 1) 35.8.3.1 maximum spi frequency the following formulas give maximum spi frequency in master read and write modes and in slave read and write modes. master write mode the spi is only sending data to a slave device such as an lcd, for example. the limit is given by spi 2 (or spi 5 ) timing. since it gives a maximum frequency above the maximum pad speed (see section 35.8.2 ?i/o characteristics? ), the max spi frequency is the one from the pad. master read mode t valid is the slave time response to output dat a after deleting an spck edge. for atmel spi dataflash (at45db642d), t valid (or t v ) is 12 ns max. in the formula above, f spck max = 38.0 mhz @ vddio = 3.3v. slave read mode in slave mode, spck is the input clock fo r the spi. the max spck frequency is given by setup and hold timings spi 7 /spi 8 (or spi 10 /spi 11 ). since this gives a frequency well above the pad limit, the limit in slave read mode is given by spck pad. slave write mode for 3.3v i/o domain and spi6, f spck max = 32 mhz. t setup is the setup time from the master before sampling data. s pck mi s o mo s i s pi 9 s pi 10 s pi 11 npc s 0 s pi 14 s pi 15 f spck max 1 spi 0 orspi 3 () t valid + -------------------------------------------------------- = f spck max 1 2 xs ( pi 6 orspi 9 () t setup ) + --------------------------------------------------------------------- =
722 11011a?atarm?04-oct-10 sam3n 35.8.3.2 spi timings notes: 1. 3.3v domain: v vddio from 3.0v to 3.6v, maximum external capacitor = 30 pf. 2. 1.8v domain: v vddio from 1.65v to 1.95v, maximum external capacitor = 30 pf. note that in spi master mode the sam3n does not sample the data (miso) on the opposite edge where data clocks out (mosi) but the same edge is used as shown in figure 35-12 and figure 35-13 . table 35-37. spi timings symbol parameter conditions min max units spi 0 miso setup time before spck rises (master) 3.3v domain (1) 14.2 ns 1.8v domain (2) 17 ns spi 1 miso hold time after spck rises (master) 3.3v domain (1) 0ns 1.8v domain (2) 0ns spi 2 spck rising to mosi delay (master) 3.3v domain (1) -2.7 2.6 ns 1.8v domain (2) -3.6 3.4 ns spi 3 miso setup time befo re spck falls (master) 3.3v domain (1) 14.4 ns 1.8v domain (2) 17 ns spi 4 miso hold time afte r spck falls (master) 3.3v domain (1) 0ns 1.8v domain (2) 0ns spi 5 spck falling to mosi delay (master) 3.3v domain (1) -2.4 2.8 ns 1.8v domain (2) -3.4 3.6 ns spi 6 spck falling to miso delay (slave) 3.3v domain (1) 4.4 15.4 ns 1.8v domain (2) 4.6 18.5 ns spi 7 mosi setup time before spck rises (slave) 3.3v domain (1) 0ns 1.8v domain (2) 0ns spi 8 mosi hold time after spck rises (slave) 3.3v domain (1) 1.8 ns 1.8v domain (2) 1.6 ns spi 9 spck rising to miso delay (slave) 3.3v domain (1) 4.9 15.4 ns 1.8v domain (2) 5.2 18.3 ns spi 10 mosi setup time before spck falls (slave) 3.3v domain (1) 0ns 1.8v domain (2) 0 spi 11 mosi hold time after spck falls (slave) 3.3v domain (1) 1.9 ns 1.8v domain (2) 2ns spi 12 npcs setup to spck rising (slave) 3.3v domain (1) 6.3 ns 1.8v domain (2) 6.4 ns spi 13 npcs hold after spck falling (slave) 3.3v domain (1) 0ns 1.8v domain (2) 0ns spi 14 npcs setup to spck falling (slave) 3.3v domain (1) 6.4 ns 1.8v domain (2) 6.4 ns spi 15 npcs hold after spck falling (slave) 3.3v domain (1) 0ns 1.8v domain (2) 0ns
723 11011a?atarm?04-oct-10 sam3n 35.8.4 usart in spi mode timings timings are given with the following conditions. vddio = 1.62v and 3v sck/miso/mosi load = 30 pf figure 35-16. usart spi master mode ? the mosi line is driven by the output pin txd ? the miso line drives the input pin rxd ? the sck line is driven by the output pin sck ? the nss line is driven by the output pin rts figure 35-17. usart spi slave mode: (mode 1 or 2) ? the mosi line drives the input pin rxd ? the miso line is driven by the output pin txd ? the sck line drives the input pin sck ? the nss line drives the input pin cts n ss s pi 0 m s b l s b s pi 1 cpol=1 cpol=0 mi s o mo s i s ck s pi 5 s pi 2 s pi 3 s pi 4 s pi 4 s ck mi s o mo s i s pi 6 s pi 7 s pi 8 n ss s pi 12 s pi 1 3
724 11011a?atarm?04-oct-10 sam3n figure 35-18. usart spi slave mode: (mode 0 or 3) s ck mi s o mo s i s pi 9 s pi 10 s pi 11 n ss s pi 14 s pi 15 table 35-38. usart spi timings symbol parameter conditions min max units master mode spi 0 sck period 1.8v domain 3.3v domain mck/6 ns spi 1 input data setup time 1.8v domain 3.3v domain 0.5 * mck + 2.6 0.5 * mck + 2.4 ns spi 2 input data hold time 1.8v domain 3.3v domain 1.5 * mck -0.3 1.5 * mck -0.3 ns spi 3 chip select active to serial clock 1.8v domain 3.3v domain 1.5 * sck - 0.9 1.5 * sck - 0.6 ns spi 4 output data setup time 1.8v domain 3.3v domain -6 -4.7 3.8 3.6 ns spi 5 serial clock to chip select inactive 1.8v domain 3.3v domain 1 *sck - 6 1 *sck - 4.6 ns slave mode spi 6 sck falling to miso 1.8v domain 3.3v domain 5.7 5.3 22.6 19.8 ns spi 7 mosi setup time before sck rises 1.8v domain 3.3v domain 2 * mck + 1.9 2 * mck + 1.7 ns spi 8 mosi hold time after sck rises 1.8v domain 3.3v domain 0 0 ns spi 9 sck rising to miso 1.8v domain 3.3v domain 5.9 5.6 22 19.4 ns
725 11011a?atarm?04-oct-10 sam3n notes: 1. 1.8v domain: vddio from 1.65v to 1.95v, maximum external capacitor = 25pf 2. 3.3v domain: vddio from 3.0v to 3.6v, maximum external capacitor = 25pf. spi 10 mosi setup time before sck falls 1.8v domain 3.3v domain 2 * mck + 1.8 2 * mck + 1.7 ns spi 11 mosi hold time after sck falls 1.8v domain 3.3v domain 0.5 0.4 ns spi 12 npcs0 setup to sck rising 1.8v domain 3.3v domain 2.5 * mck -0.26 2.5 * mck -0.4 ns spi 13 npcs0 hold after sck falling 1.8v domain 3.3v domain 1.5 * mck + 2.2 1.5 * mck + 2 ns spi 14 npcs0 setup to sck falling 1.8v domain 3.3v domain 2.5 * mck -0.4 2.5 * mck -0.4 ns spi 15 npcs0 hold after sck rising 1.8v domain 3.3v domain 1.5 * mck + 1.8 1.5 * mck + 1.7 ns table 35-38. usart spi timings (continued) symbol parameter conditions min max units
726 11011a?atarm?04-oct-10 sam3n 35.8.5 two-wire serial interface characteristics table 35-39 describes the requirements for devices connected to the two-wire serial bus. for timing symbols refer to fig- ure 35-19 . note: 1. required only for f twck > 100 khz. 2. c b = capacitance of one bus line in pf. per i2c standard, c b max = 400pf 3. the twck low period is defined as follows: 4. the twck high period is defined as follows: 5. t cp_mck = mck bus period. table 35-39. two-wire serial bus requirements symbol parameter condition min max units v il input low-voltage -0.3 0.3 v vddio v v ih input high-voltage 0.7xv vddio v cc + 0.3 v v hys hysteresis of schmitt trigger inputs 0.150 ? v v ol output low-voltage 3 ma sink current - 0.4 v t r rise time for both twd and twck 20 + 0.1c b (1)(2) 300 ns t of output fall time from v ihmin to v ilmax 10 pf < c b < 400 pf figure 35-19 20 + 0.1c b (1)(2) 250 ns c i (1) capacitance for each i/o pin ? 10 pf f twck twck clock frequency 0 400 khz rp value of pull-up resistor f twck 100 khz f twck > 100 khz t low low period of the twck clock f twck 100 khz (3) ?s f twck > 100 khz (3) ?s t high high period of the twck clock f twck 100 khz (4) ?s f twck > 100 khz (4) ?s t hd;sta hold time (repeated) start condition f twck 100 khz t high ?s f twck > 100 khz t high ?s t su;sta set-up time for a repeated start condition f twck 100 khz t high ?s f twck > 100 khz t high ?s t hd;dat data hold time f twck 100 khz 0 3 x t cp_mck (5) s f twck > 100 khz 0 3 x t cp_mck (5) s t su;dat data setup time f twck 100 khz t low - 3 x t cp_mck (5) ?ns f twck > 100 khz t low - 3 x t cp_mck (5) ?ns t su;sto setup time for stop condition f twck 100 khz t high ?s f twck > 100 khz t high ?s t hd;sta hold time (repeated) start condition f twck 100 khz t high ?s f twck > 100 khz t high ?s v vddio 0,4v ? 3ma ------------------------------------- - 1000ns c b ------------------- v vddio 0,4v ? 3ma ------------------------------------- - 300ns c b --------------- - t low cldiv ( 2 ckdiv () 4 ) + t mck = t high chdiv ( 2 ckdiv () 4 ) + t mck =
727 11011a?atarm?04-oct-10 sam3n figure 35-19. two-wire serial bus timing 35.8.6 embedded flash characteristics the maximum operating frequency is given in tables 35-40 and 35-41 below but is limited by the embedded flash access time when the processor is fetching code out of it. the tables 35-40 and 35-41 below give the device maximum operating frequency depending on the field fws of the mc_fmr register. this field defines the number of wait states required to access the embedded flash memory. table 35-40. embedded flash wait state vddcore set at 1.65v fws read operations maximum operating frequency (mhz) 0 1 cycle 21 1 2 cycles 32 2 3 cycles 48 t s u; s ta t low t high t low t of t hd; s ta t hd;dat t s u;dat t s u; s to t buf twck twd t r table 35-41. embedded flash wait state vddcore set at 1.80v fws read operations maximum operating frequency (mhz) 0 1 cycle 24 1 2 cycles 42 2 3 cycles 62 table 35-42. ac flash characteristics parameter conditions min typ max units program cycle time per page including auto-erase 4.6 ms per page without auto-erase 2.3 ms full chip erase 10 11.5 ms data retention not powered or powered 10 years endurance write/erase cycles @ 25c write/erase cycles @ 85c 10k 30k cycles
728 11011a?atarm?04-oct-10 sam3n 36. mechanical characteristics figure 36-1. 100-lead lqfp package mechanical drawing this package respects the recommendations of the nemi user group. table 36-1. device and lqfp package maximum weight sam3n4/2/1 800 mg table 36-2. package reference jedec drawing reference ms-026 jesd97 classification e3 table 36-3. lqfp package characteristics moisture sensitivity level 3 note : 1. this drawing is for general information only. refer to jedec drawing ms-026 for additional information.
729 11011a?atarm?04-oct-10 sam3n figure 36-2. 100-ball lfbga package drawing table 36-4. soldering information (substrate level) ball land tbd soldering mask opening tbd table 36-5. device maximum weight tbd mg table 36-6. 100-ball package characteristics moisture sensitivity level 3 table 36-7. package reference jedec drawing reference tbd jesd97 classification e1
730 11011a?atarm?04-oct-10 sam3n figure 36-3. 64- and 48-lead lqfp package drawing
731 11011a?atarm?04-oct-10 sam3n table 36-8. 48-lead lqfp package dimensions (in mm) symbol millimeter inch min nom max min nom max a ? ?1.60? ?0.063 a1 0.05 ? 0.15 0.002 ? 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 d 9.00 bsc 0.354 bsc d1 7.00 bsc 0.276 bsc e 9.00 bsc 0.354 bsc e1 7.00 bsc 0.276 bsc r2 0.08 ? 0.20 0.003 ? 0.008 r1 0.08 ? ? 0.003 ? ? q 03.57 03.57 1 0??0?? 2 11 12 13 11 12 13 3 11 12 13 11 12 13 c 0.09 ? 0.20 0.004 ? 0.008 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 ref 0.039 ref s 0.20 ? ? 0.008 ? ? b 0.17 0.20 0.27 0.007 0.008 0.011 e 0.50 bsc. 0.020 bsc. d2 5.50 0.217 e2 5.50 0.217 tolerances of form and position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003
732 11011a?atarm?04-oct-10 sam3n this package respects the recommendations of the nemi user group. table 36-9. 64-lead lqfp package dimensions (in mm) symbol millimeter inch min nom max min nom max a ? ?1.60? ?0.063 a1 0.05 ? 0.15 0.002 ? 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 d 12.00 bsc 0.472 bsc d1 10.00 bsc 0.383 bsc e 12.00 bsc 0.472 bsc e1 10.00 bsc 0.383 bsc r2 0.08 ? 0.20 0.003 ? 0.008 r1 0.08 ? ? 0.003 ? ? q 03.57 03.57 1 0??0?? 2 11 12 13 11 12 13 3 11 12 13 11 12 13 c 0.09 ? 0.20 0.004 ? 0.008 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 ref 0.039 ref s 0.20 ? ? 0.008 ? ? b 0.17 0.20 0.27 0.007 0.008 0.011 e 0.50 bsc. 0.020 bsc. d2 7.50 0.285 e2 7.50 0.285 tolerances of form and position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003 table 36-10. device and lqfp package maximum weight sam3n4/2/1 750 mg table 36-11. lqfp package reference jedec drawing reference ms-026 jesd97 classification e3 table 36-12. lqfp and qfn package characteristics moisture sensitivity level 3
733 11011a?atarm?04-oct-10 sam3n figure 36-4. 48-pad qfn package
734 11011a?atarm?04-oct-10 sam3n table 36-13. 48-pad qfn package dimensions (in mm) symbol millimeter inch min nom max min nom max a ? ? 090 ? ? 0.035 a1 ? ? 0.050 ? ? 0.002 a2 ? 0.65 0.70 ? 0.026 0.028 a3 0.20 ref 0.008 ref b 0.18 0.20 0.23 0.007 0.008 0.009 d 7.00 bsc 0.276 bsc d2 5.45 5.60 5.75 0.215 0.220 0.226 e 7.00 bsc 0.276 bsc e2 5.45 5.60 5.75 0.215 0.220 0.226 l 0.35 0.40 0.45 0.014 0.016 0.018 e 0.50 bsc 0.020 bsc r 0.09 ? ? 0.004 ? ? tolerances of form and position aaa 0.10 0.004 bbb 0.10 0.004 ccc 0.05 0.002
735 11011a?atarm?04-oct-10 sam3n figure 36-5. 64-pad qfn package drawing
736 11011a?atarm?04-oct-10 sam3n this package respects the recommendations of the nemi user group. table 36-14. 64-pad qfn package dimensions (in mm) symbol millimeter inch min nom max min nom max a ? ? 090 ? ? 0.035 a1 ? ? 0.05 ? ? 0.001 a2 ? 0.65 0.70 ? 0.026 0.028 a3 0.20 ref 0.008 ref b 0.23 0.25 0.28 0.009 0.010 0.011 d 9.00 bsc 0.354 bsc d2 6.95 7.10 7.25 0.274 0.280 0.285 e 9.00 bsc 0.354 bsc e2 6.95 7.10 7.25 0.274 0.280 0.285 l 0.35 0.40 0.45 0.014 0.016 0.018 e 0.50 bsc 0.020 bsc r 0.125 ? ? 0.0005 ? ? tolerances of form and position aaa 0.10 0.004 bbb 0.10 0.004 ccc 0.05 0.002 table 36-15. device and qfn package maxi mum weight (preliminary) sam3n4/2/1 280 mg table 36-16. qfn package reference jedec drawing reference mo-220 jesd97 classification e3 table 36-17. qfn package characteristics moisture sensitivity level 3
737 11011a?atarm?04-oct-10 sam3n 36.1 soldering profile table 36-18 gives the recommended soldering profile from j-std-020c. note: the package is certified to be backward compatible with pb/sn soldering profile. a maximum of three reflow passes is allowed per component. 36.2 packaging resources land pattern definition. refer to the following ipc standards: ? ipc-7351a and ipc-782 ( generic requirements for surface mount design and land pattern standards ) http://landpatterns.ipc.org/default.asp ? atmel green and rohs policy and package material declaration data sheet http://www.atmel.com/green/ table 36-18. soldering profile profile feature green package average ramp-up rate (217c to peak) 3 c/sec. max. preheat temperature 175c 25c 180 sec. max. temperature maintained above 217c 60 sec. to 150 sec. time within 5 c of actual peak temperature 20 sec. to 40 sec. peak temperature range 260 c ramp-down rate 6 c/sec. max. time 25 c to peak temperature 8 min. max.
738 11011a?atarm?04-oct-10 sam3n 37. ordering information table 37-1. ordering code mrl flash (kbytes) package (kbytes) package type temperature operating range atsam3n4ca-au a 256 qfp100 green industrial -40c to 85c atsam3n4ca-cu a 256 bga100 green industrial -40c to 85c atsam3n4ba-au a 256 qfp64 green industrial -40c to 85c atsam3n4ba-mu a 256 qfn64 green industrial -40c to 85c atsam3n4aa-au a 256 qfp48 green industrial -40c to 85c atsam3n4aa-mu a 256 qfn48 green industrial -40c to 85c atsam3n2ca-au a 128 qfp100 green industrial -40c to 85c atsam3n2ca-cu a 128 bga100 green industrial -40c to 85c ATSAM3N2BA-AU a 128 qfp64 green industrial -40c to 85c atsam3n2ba-mu a 128 qfn64 green industrial -40c to 85c atsam3n2aa-au a 128 qfp48 green industrial -40c to 85c atsam3n2aa-mu a 128 qfn48 green industrial -40c to 85c atsam3n1ca-au a 64 qfp100 green industrial -40c to 85c atsam3n1ca-cu a 64 bga100 green industrial -40c to 85c atsam3n1ba-au a 64 qfp64 green industrial -40c to 85c atsam3n1ba-mu a 64 qfn64 green industrial -40c to 85c atsam3n1aa-au a 64 qfp48 green industrial -40c to 85c atsam3n1aa-mu a 64 qfn48 green industrial -40c to 85c
739 11011a?atarm?04-oct-10 sam3n 38. sam3n series errata 38.1 marking all devices are marked with the atmel logo and the ordering code. additional marking may be in one of the following formats: where ??yy?: manufactory year ? ?ww?: manufactory week ? ?v?: revision ? ?xxxxxxxxx?: lot number yyww v xxxxxxxxx arm
740 11011a?atarm?04-oct-10 sam3n 38.2 flash memory 38.2.1 flash: flash programming when writing data into the flash memory plane (either through the eefc, using the iap function or ffpi), the data may not be correctly written (i.e the data written is not the one expected). problem fix/workaround set the number of wait states (ws) at 6 (fws = 6) during the programming.
741 11011a?atarm?04-oct-10 sam3n revision history doc. rev. 11011a comments change request ref. first issue
742 11011a?atarm?04-oct-10 sam3n
i 11011a?atarm?04-oct-10 sam3n table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 sam3n description ............. .............. ............... .............. .............. ............ 2 1.1 configuration summary .....................................................................................2 2 sam3n block diagram .......... .............. .............. .............. .............. .......... 3 3 signal description .............. .............. ............... .............. .............. ............ 6 4 package and pinout ................. ................ ................. ................ ............... 9 4.1 sam3n4/2/1c package and pinout ..................................................................9 4.2 sam3n4/2/1b package and pinout .................................................................12 4.3 sam3n4/2/1a package and pinout .................................................................14 5 power considerations ........ .............. ............... .............. .............. .......... 16 5.1 power supplies ................................................................................................16 5.2 voltage regulator ............................................................................................16 5.3 typical powering schematics ..........................................................................16 5.4 active mode .....................................................................................................18 5.5 low power modes ...........................................................................................18 5.6 wake-up sources ............................................................................................21 5.7 fast start-up ...................................................................................................22 6 input/output lines .............. .............. ............... .............. .............. .......... 23 6.1 general purpose i/o lines ..............................................................................23 6.2 system i/o lines .............................................................................................23 6.3 test pin ...........................................................................................................25 6.4 nrst pin .........................................................................................................25 6.5 erase pin ......................................................................................................25 7 memories ............... .............. .............. ............... .............. .............. .......... 26 7.1 product mapping .............................................................................................26 7.2 embedded memories ......................................................................................27 8 system controller ............. ................ ............... .............. .............. .......... 30 8.1 system controller and peripheral mapping .....................................................32 8.2 power-on-reset, brownout and supply monitor .............................................32 9 peripherals ............ .............. .............. ............... .............. .............. .......... 33 9.1 peripheral identifiers ........................................................................................33
ii 11011a?atarm?04-oct-10 sam3n 9.2 apb/ahb bridge .... ................ ................ ................ ................ ................ ..........34 9.3 peripheral signal multiplexing on i/o lines .....................................................34 10 arm cortex ? m3 processor ...... ................. ................ ................. .......... 39 10.1 about this section ............................................................................................39 10.2 embedded characteristics ..............................................................................39 10.3 about the cortex-m3 processor and core peripherals .....................................39 10.4 programmers model ........................................................................................42 10.5 memory model .................................................................................................55 10.6 exception model ..............................................................................................63 10.7 fault handling ..................................................................................................70 10.8 power management ........................................................................................72 10.9 instruction set summary ..................................................................................75 10.10 intrinsic functions .............................................................................................78 10.11 about the instruction descriptions ....................................................................79 10.12 memory access instructions ............................................................................87 10.13 general data processing instructions ............................................................103 10.14 multiply and divide instructions ......................................................................119 10.15 saturating instructions ...................................................................................123 10.16 bitfield instructions .........................................................................................125 10.17 branch and control instructions .....................................................................129 10.18 miscellaneous instructions .............................................................................137 10.19 about the cortex-m3 peripherals ...................................................................150 10.20 nested vectored interrupt controller .............................................................151 10.21 system control block .....................................................................................164 10.22 system timer, systick ...................................................................................191 10.23 glossary ........................................................................................................196 11 debug and test featur es ............... .............. .............. .............. ........... 201 11.1 description .....................................................................................................201 11.2 embedded characteristics ............................................................................201 11.3 application examples ....................................................................................202 11.4 debug and test pin description ....................................................................203 11.5 functional description ...................................................................................204 12 reset coontroller (rstc) .. ............. .............. .............. .............. ........... 209 12.1 description .....................................................................................................209 12.2 embedded characteristics ............................................................................209
iii 11011a?atarm?04-oct-10 sam3n 12.3 block diagram ...............................................................................................209 12.4 functional description ...................................................................................210 12.5 reset controller (rstc) user interface ........................................................217 13 real-time timer (rtt) ....... .............. .............. .............. .............. ........... 221 13.1 description .....................................................................................................221 13.2 embedded characteristics ............................................................................221 13.3 block diagram ...............................................................................................221 13.4 functional description ...................................................................................222 13.5 real-time timer (rtt) user interface ...........................................................224 14 real time clock (rtc) ....... .............. ............... .............. .............. ........ 229 14.1 description .....................................................................................................229 14.2 embedded characteristics ............................................................................229 14.3 block diagram ...............................................................................................229 14.4 product dependencies ..................................................................................230 14.5 functional description ...................................................................................230 14.6 real time clock (rtc) user interface ........................................................233 15 watchdog timer (wdt) ......... ................ ................. ................ ............. 247 15.1 description .....................................................................................................247 15.2 embedded characteristics ............................................................................247 15.3 block diagram ...............................................................................................247 15.4 functional description ...................................................................................248 15.5 watchdog timer (wdt) user interface .........................................................250 16 supply controller (supc) .. .............. ............... .............. .............. ........ 255 16.1 description .....................................................................................................255 16.2 embedded characteristics ............................................................................255 16.3 block diagram ...............................................................................................256 16.4 supply controller functional description ......................................................257 16.5 supply controller (supc) user interface ......................................................265 17 general purpose backup regi sters (gpbr) ............ .............. ........... 273 17.1 description .....................................................................................................273 17.2 embedded characteristics ............................................................................273 17.3 general purpose backup registers (gpbr) user interface ........................273 18 enhanced embedded fl ash controller (eefc) ...... ................ ........... 275 18.1 description ...................................................................................................275
iv 11011a?atarm?04-oct-10 sam3n 18.2 product dependencies ..................................................................................275 18.3 functional description ...................................................................................275 18.4 enhanced embedded flash controller (eefc) user interface .....................286 19 fast flash programming in terface (ffpi) ... .............. .............. ........... 291 19.1 description .....................................................................................................291 19.2 parallel fast flash programming ..................................................................291 20 sam3n boot program ........ .............. ............... .............. .............. ........ 303 20.1 description .....................................................................................................303 20.2 hardware and software constraints ..............................................................303 20.3 flow diagram ................................................................................................303 20.4 device initialization ........................................................................................303 20.5 sam-ba monitor ............................................................................................304 21 bus matrix (matrix) ........ .............. .............. .............. .............. ........... 307 21.1 description .....................................................................................................307 21.2 embedded characteristics ............................................................................307 21.3 memory mapping ...........................................................................................308 21.4 special bus granting techniques .................................................................308 21.5 arbitration ......................................................................................................309 21.6 system i/o configuration ..............................................................................311 21.7 write protect registers ..................................................................................311 21.8 bus matrix (matrix) user interface .............................................................312 22 peripheral dma controller (pdc) ................ .............. .............. ........... 319 22.1 description .....................................................................................................319 22.2 embedded characteristics ............................................................................319 22.3 block diagram ...............................................................................................320 22.4 functional description ...................................................................................321 22.5 peripheral dma controller (pdc) user interface ..........................................324 23 clock generator ................ .............. .............. .............. .............. ........... 333 23.1 description .....................................................................................................333 23.2 embedded characteristics ............................................................................333 23.3 block diagram ...............................................................................................334 23.4 slow clock .....................................................................................................335 23.5 main clock .....................................................................................................336 23.6 divider and pll block ...................................................................................340
v 11011a?atarm?04-oct-10 sam3n 24 power management controller (pmc) .... ................. ................ ........... 341 24.1 description .....................................................................................................341 24.2 embedded characteristics ............................................................................341 24.3 block diagram ...............................................................................................342 24.4 master clock controller .................................................................................342 24.5 processor clock controller ............................................................................343 24.6 systick clock ................................................................................................343 24.7 peripheral clock controller ............................................................................343 24.8 free running processor clock ......................................................................344 24.9 programmable clock output controller .........................................................344 24.10 fast startup ...................................................................................................345 24.11 clock failure detector ...................................................................................346 24.12 programming sequence ................................................................................347 24.13 clock switching details .................................................................................350 24.14 write protection registers .............................................................................353 24.15 power management controller (pmc) user interface ..................................354 25 chip identifier (chipid) .. ................ .............. .............. .............. ........... 377 25.1 description .....................................................................................................377 25.2 chip identifier (chipid) user interface ........................................................378 26 parallel input/output (pio) controller .. ................. ................ ............. 385 26.1 description .....................................................................................................385 26.2 embedded characteristics ............................................................................385 26.3 block diagram ...............................................................................................386 26.4 product dependencies ..................................................................................387 26.5 functional description ...................................................................................388 26.6 i/o lines programming example ...................................................................397 26.7 parallel input/output controller (pio) user interface ....................................398 27 serial peripheral interface (spi) ................ ................ .............. ........... 429 27.1 description .....................................................................................................429 27.2 embedded characteristics ............................................................................429 27.3 block diagram ...............................................................................................430 27.4 application block diagram .............................................................................430 27.5 signal description .........................................................................................431 27.6 product dependencies ..................................................................................431 27.7 functional description ...................................................................................432
vi 11011a?atarm?04-oct-10 sam3n 27.8 serial peripheral interface (spi) user interface ............................................447 28 two-wire interface (twi) .... .............. ............... .............. .............. ........ 463 28.1 description .....................................................................................................463 28.2 embedded characteristics ............................................................................464 28.3 list of abbreviations ......................................................................................464 28.4 block diagram ...............................................................................................465 28.5 application block diagram .............................................................................465 28.6 product dependencies ..................................................................................466 28.7 functional description ...................................................................................467 28.8 master mode ..................................................................................................468 28.9 multi-master mode .........................................................................................480 28.10 slave mode ....................................................................................................483 28.11 two-wire interface (twi) user interface .......................................................491 29 universal asynchronous receiver tra nsceiver (uart) ... ............... 505 29.1 description .....................................................................................................505 29.2 embedded characteristics ............................................................................505 29.3 block diagram ...............................................................................................506 29.4 product dependencies ..................................................................................506 29.5 uart operations ..........................................................................................507 29.6 universal asynchronous receiver transmitter (uart) user interface .........513 30 universal synchronous asynchr onous receiver transmitter (usart) ................. ................. ................ ................. ................ ............. 523 30.1 description .....................................................................................................523 30.2 embedded characteristics ............................................................................523 30.3 block diagram ...............................................................................................524 30.4 application block diagram .............................................................................525 30.5 i/o lines description ....................................................................................526 30.6 product dependencies ..................................................................................527 30.7 functional description ...................................................................................528 30.8 universal synchronous asynchro nous receiver transmitter (usart) user interface ................................................................................................557 31 timeer counter (tc) ......... .............. .............. .............. .............. ........... 579 31.1 description .....................................................................................................579 31.2 embedded characteristics ............................................................................579 31.3 block diagram ...............................................................................................581
vii 11011a?atarm?04-oct-10 sam3n 31.4 pin name list ................................................................................................582 31.5 product dependencies ..................................................................................582 31.6 functional description ...................................................................................583 31.7 timer counter (tc) user interface ................................................................603 32 pulse width modulation c ontroller (pwm) . .............. .............. ........... 627 32.1 description .....................................................................................................627 32.2 embedded characteristics ............................................................................627 32.3 block diagram ...............................................................................................628 32.4 i/o lines description .....................................................................................628 32.5 product dependencies ..................................................................................628 32.6 functional description ...................................................................................630 32.7 pulse width modulation controller (pwm) user interface ............................638 33 analog-to-digital converter (adc) .............. .............. .............. ........... 649 33.1 description .....................................................................................................649 33.2 embedded characteristics ............................................................................649 33.3 block diagram ...............................................................................................650 33.4 signal description ..........................................................................................650 33.5 product dependencies ..................................................................................651 33.6 functional description ...................................................................................652 33.7 analog-to-digital converter (adc) user interface .........................................659 34 digital to analog converte r controller (dacc) ...... ................ ........... 679 34.1 description .....................................................................................................679 34.2 embedded characteristics ............................................................................679 34.3 block diagram ...............................................................................................680 34.4 signal description ..........................................................................................681 34.5 product dependencies ..................................................................................681 34.6 functional description ...................................................................................682 34.7 digital-to-analog converter controller (dacc) user interface .....................684 35 electrical characteristics ... .............. ............... .............. .............. ........ 695 35.1 absolute maximum ratings ...........................................................................695 35.2 dc characteristics .........................................................................................696 35.3 power consumption ......................................................................................702 35.4 crystal oscillators characteristics .................................................................708 35.5 pll characteristics .......................................................................................715 35.6 10-bit adc characteristics ............................................................................716
viii 11011a?atarm?04-oct-10 sam3n 35.7 10-bit dac characteristics ............................................................................718 35.8 ac characteristics .........................................................................................719 36 mechanical characteristics ..... ................ ................. ................ ........... 728 36.1 soldering profile ............................................................................................737 36.2 packaging resources ....................................................................................737 37 ordering information .......... .............. ............... .............. .............. ........ 738 38 sam3n series errata ........ .............. .............. .............. .............. ........... 739 38.1 marking ..........................................................................................................739 38.2 flash memory ................................................................................................740 revision history.......... ................ ................. ................ .............. ........... 741 table of contents.......... ................. ................ ................. ................ ........... i
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