uc1841 uc2841 uc3841 programmable, off-line, pwm controller all control, driving, monitoring, and protection functions included low-current, off-line start circuit voltage feed forward or current mode control guaranteed duty cycle clamp pwm latch for single pulse per period pulse-by-pulse current limiting plus shutdown for over-current fault no start-up or shutdown transients slow turn-on both initially and after fault shutdown shutdown upon over- or under-voltage sensing latch off or continuous retry after fault pwm output switch usable to 1a peak current 1% reference accuracy 500khz operation 18 pin dil package the uc1841 family of pwm controllers has been designed to increase the level of versatility while retaining all of the performance features of the earlier uc1840 devices. while still optimized for highly-efficient boot- strapped primary-side operation in forward or flyback power converters, the uc1841 is equally adept in implementing both low and high voltage input dc to dc converters. important performance features include a low-current starting circuit, linear feed-forward for constant volt-second operation, and compatibility with either voltage or current mode topologies. in addition to start-up and normal regulating pwm functions, these de- vices include built in protection from over-voltage, under-voltage, and over-current fault conditions with the option for either latch-off or automat- ic restart. while pin compatible with the uc1840 in all respects except that the po- larity of the external stop has been reversed, the uc1841 offers the fol- lowing improvements: 1. fault latch reset is accomplished with slow start discharge rather than recycling the input voltage to the chip. 2. the external stop input can be used for a fault delay to resist shutdown from short duration transients. 3. the duty-cycle clamping function has been characterized and specified. the uc1841 is characterized for -55c to +125c operation while the uc2841 and uc3841 are designed for -25c to +85c and 0to +70c, respectively. block diagram note: positive true logic, latch outputs high with set, reset has priority. 6/93 description features
parameter test conditions uc1841 / uc2841 uc3841 units min typ max min typ max power inputs start-up current v in = 30v, pin 2 = 2.5v 4.5 6 4.5 6 ma operating current v in = 30v, pin 2 = 3.5v 10 14 10 14 ma supply ov clamp i in = 20ma 33 40 45 33 40 45 v reference section reference voltage t j = 25c 4.95 5.0 5.05 4.9 5.0 5.1 v line regulation v in = 8 to 30v 10 15 10 20 mv load regulation i l = 0 to 10ma 1020 1030mv temperature stability over operating temperature range 4.9 5.1 4.85 5.15 v short circuit current v ref = 0, t j = 25c -80 -100 -80 -100 ma oscillator nominal frequency t j = 25c 47 50 53 45 50 55 khz voltage stability v in = 8 to 30v 0.5 1 0.5 1 % temperature stability over operating temperature range 45 55 43 57 khz maximum frequency r t = 2k w , c t = 330pf 500 500 khz uc1841 uc2841 uc3841 electrical characteristics: unless otherwise stated, these specifications apply for t a = -55c to +125c for the uc1841, -25c to +85c for the uc2841, and 0c to +70c for the uc3841; v in = 20v, r t = 20k w , c t = .001mfd, r r = 10k w , c r = .001mfd, current limit threshold = 200mv, t a = t j. supply voltage, +v in (pin 15) (note 2) voltage driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +32v current driven, 100ma maximum . . . . . . . . . . . . self-limiting pwm output voltage (pin 12) . . . . . . . . . . . . . . . . . . . . . . . 40v pwm output current, steady-state (pin 12) . . . . . . . . . 400ma pwm output peak energy discharge . . . . . . . . . . . . 20 m joules driver bias current (pin 14) . . . . . . . . . . . . . . . . . . . . . -200ma reference output current (pin 16) . . . . . . . . . . . . . . . . -50ma slow-start sink current (pin 8) . . . . . . . . . . . . . . . . . . . . 20ma v in sense current (pin 11). . . . . . . . . . . . . . . . . . . . . . . . 10ma current limit inputs (pins 6 & 7) . . . . . . . . . . . . . -0.5 to +5.5v stop input (pin 4) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +5.5v comparator inputs (pins 1, 7, 9-11, 16) . . . . . . . . . . . . internally clamped at 12v power dissipation at t a = 25c (note 3) . . . . . . . . . . . 1000mw power dissipation at t c = 25c (note 3) . . . . . . . . . . . 2000mw operating junction temperature . . . . . . . . . . -55c to +150c storage temperature range. . . . . . . . . . . . . . -65c to +150c lead temperature (soldering, 10 sec) . . . . . . . . . . . . . +300c note 1: all voltages are with respect to ground, pin 13. currents are positive-into, negative-out of the specified terminal. note 2: all pin numbers are referenced to dil-18 package. note 3: consult packaging section of databook for thermal limitations and considerations of package. connection diagrams plcc-20, lcc-20 (top view) q or l package dil-18, soic-18 (top view) j or n, dw package package pin functions function pin comp 1 start/uv 2 ov sense 3 stop 4 reset 5 cur thresh 7 cur sense 8 slow start 9 r t /c t 10 ramp 11 v in sense 12 pwm out 13 ground 14 drive bias 15 +v in supply 17 5.0v ref 18 inv. input 19 n.i. input 20 absolute maximum ratings 2
parameter test conditions uc1841 / uc2841 uc3841 units min typ max min typ max ramp generator ramp current, minimum i sense = -10 m a -11 -14 -11 -14 m a ramp current, maximum i sense = 1.0ma -0.9 -.95 -0.9 -.95 ma ramp valley 0.3 0.4 0.6 0.3 0.4 0.6 v ramp peak clamping level 3.9 4.2 4.5 3.9 4.2 4.5 v error amplifier input offset voltage v cm = 5.0v 0.5 5 2 10 mv input bias current 0.5 2 1 5 m a input offset current 0.5 0.5 m a open loop gain d v o = 1 to 3v 60 66 60 66 db output swing (max. output ramp peak - 100mv) minimum total range 0.3 3.5 0.3 3.5 v cmrr v cm = 1.5 to 5.5v 70 80 70 80 db psrr v in = 8 to 30v 70 80 70 80 db short circuit current v comp = 0v -4 -10 -4 -10 ma gain bandwidth* t j = 25c, a vol = 0db 1 2 1 2 mhz slew rate* t j = 25c, a vcl = 0db 0.8 0.8 v/ m s pwm section continuous duty cycle range* (other than zero) minimum total continuous range, ramp peak < 4.2v 495495% 50% duty cycle clamp r sense to v ref = 10k 42 47 52 42 47 52 % output saturation i out = 20ma 0.2 0.4 0.2 0.4 v i out = 200ma 1.7 2.2 1.7 2.2 v output leakage v out = 40v 0.1 10 0.1 10 m a comparator delay* pin 8 to pin 12, t j = 25c, r l = 1k w 300 500 300 500 ns sequencing functions comparator thresholds pins 2, 3, 5 2.8 3.0 3.2 2.8 3.0 3.2 v input bias current pins 3, 5 = 0v -1.0 -4.0 -1.0 -4.0 m a input leakage pins 3, 5 = 10v 0.1 2.0 0.1 2.0 m a start/uv hysteresis current pin 2 = 2.5v 170 200 220 170 200 230 m a ext. stop threshold pin 4 0.8 1.6 2.4 0.8 1.6 2.4 v error latch activate current pin 4 = 0v, pin 3 > 3v -120 -200 -120 -200 m a driver bias saturation voltage, v in - v oh i b = -50ma 2 3 2 3 v driver bias leakage v b = 0v -0.1 -10 -0.1 -10 m a slow-start saturation i s = 10ma 0.2 0.5 0.2 0.5 v slow-start leakage v s = 4.5v 0.1 2.0 0.1 2.0 m a current control current limit offset 0 5 0 10 mv current shutdown offset 370 400 430 360 400 440 mv input bias current pin 7 = 0v -2 -5 -2 -5 m a common mode range* -0.4 3.0 -0.4 3.0 v current limit delay* t j = 25c, pin 7 to 12, r l = 1k 200 400 200 400 ns * these parameters are guaranteed by design but not 100% tested in production. uc1841 uc2841 uc3841 electrical characteristics: unless otherwise stated, these specifications apply for t a = -55c to +125c for the uc1841, -25c to +85c for the uc2841, and 0c to +70c for the uc3841; v in = 20v, r t = 20k w , c t = .001mfd, r r = 10k w , c r = .001mfd, current limit threshold = 200mv, t a = t j. 3
pwm control 1. oscillator generates a fixed-freque ncy internal clock from an external r t and c t . frequency = k c r t c t where k c is a first order correction factor ? 0.3 log (c t x 10 12 ). 2. ramp generator develops a linear ramp with a slope defined externally by dv dt = sense voltage r r c r c r is normally selected c t and its value will have some effect upon valley voltage. limiting the minimum value for i sense will establish a maximum duty cycle clamp. c r terminal can be used as an input port for current mode control. 3. error amplifier conventional operational amplifier for closed-loop gain and phase compensation. low output impedance; unity-gain stable. the output is held low by the slow start voltage at turn on in order to minimize overshoot. 4. reference generator precision 5.0v for internal and external usage to 50ma. tracking 3.0v reference for internal usage only with nominal accuracy of 2%. 40v clamp zener for chip ov protection, 100ma maximum current. 5. pwm comparator generates output pulse which starts at termination of clock pulse and ends when the ramp input crosses the lowest of two positive inputs. 6. pwm latch terminates the pwm output pulse when set by inputs from either the pwm comparator, the pulse-by-pulse current limit comparator, or the error latch. resets with each internal clock pulse. 7. pwm output switch transistor capable of sinking current to ground which is off during the pwm on-time and turns on to terminate the power pulse. current capacity is 400ma saturated with peak capacitance discharge in excess of one amp. sequencing functions 1. start/uv sense with an increasing voltage, it generates a turn-on signal and releases the slow-start clamp at a start threshold. with a decreasing voltage, it generates a turn-off command at a lower level separated by a 200 m a hysteresis current. 2. drive switch disables most of the chip to hold internal current consumption low, and driver bias off, until input voltage reaches start threshold. 3. driver bias supplies drive current to external power switch to provide turn-on bias. 4. slow start clamps low to hold pwm off. upon release, rises with rate controlled by r s c s for slow increase of output pulse width. can also be used as an alternate maximum duty cycle clamp with an external voltage divider. protection functions 1. error latch when set by momentary input, this latch insures immediate pwm shutdown and hold off until reset. inputs to error latch are: a. ov > 3.2v (typically 3v) b. stop > 2.4v (typically 1.6v) c. current sense 400mv over threshold (typical). error latch resets when slow start voltage falls to 0.4v if reset pin 5 < 2.8v. with pin 5 > 3.2v, error latch will remain set. 2. current limiting differential input comparator terminates individual output pulses each time sense voltage rises above threshold. when sense voltage rises to 400mv (typical) above threshold, a shutdown signal is sent to error latch. 3. external stop a voltage over 1.2v will set the error latch and hold the output off. a voltage less than 0.8v will defeat the error latch and prevent shutdown. a capacitor here will slow the action of the error latch for transient protection by providing a typical delay of 13ms/ m f. uc1841 uc2841 uc3841 functional description 4
uc1841 uc2841 uc3841 start/uv hysteresis pwm output minimum pulse width oscillator frequency pwm output-saturation voltage shutdown timing error amplifier open loop gain and phase 5
flyback application (a) in this application (see figure a, next page), complete control is maintained on the primary side. control power is provided by r in and c in during start-up, and by a pri- mary-referenced low voltage winding, n2, for efficient op- eration after start. the error amplifier loop is closed to regulate the dc voltage from n2 with other outputs fol- lowing through their magnetic coupling - a task made even easier with the uc1841s feed - forward line regula- tion. an extension to this application for more precise regula- tion would be the use of the uc1901 isolated feedback generator for direct closed-loop control to an output. not shown, are protective snubbers or additional interface circuitry which may be r equired by the choice of the high- voltage switch, qs, or the application; however, one ex- ample of power transistor interfacing is provided on the following page. regulator application (b) with the addition of a level shifting transistor, q1, the uc1841 is an ideal control circuit for dc to dc converters such as the buck regulator shown in figure b opposite. in addition to providing constant current drive pulses to the pic661 power switch, this circuit has full fault protection and high speed dynamic line regulation due to its feed- forward capability. an additional feature is the ability to uc1841 uc2841 uc3841 open-loop test circuit nominal frequency = 1 r t c t = 50 khz start voltage = 3 ? ? r1 + r2 + r3 r2 + r3 ? ? +0.2r1 = 12v uv fault voltage = 3 ? ? r1 + r2 + r3 r2 + r3 ? ? = 8v ov fault voltage = 3 ? ? r1 + r2 + r3 r3 ? ? = 32v current limit = 200mv current fault voltage = 600mv duty cycle clamp = 50% 6
uc1841 uc2841 uc3841 figure a. uc1841 programmable pwm controller in a simplified flyb ack regulator figure b. overall schematic for a 300 watt, off-line power converter using the uc3841 for control 7
since pin 10 is a direct input to the pwm comparator, this point can also serve as a current sense port for current mode control. in this application, current sensing is ground refer- enced through r cs . resistor r1 sets a 400mv offset across r2 (assuming r2 > r cs ) so that both the error amplifier and fault shutdown can force the current completely to zero. r2 is also used along with c f as a small filter to attenuate leading- edge spikes on the load current waveform. in this mode, current limiting can be accomplished by divider r3/r4 which forms a clamp overriding the output of the error amplifier. in this circuit, r1 is used in conjunction with c r (not shown) to establish a minimum ramp charging current such that the ramp voltage reaches 4.2v at the required maximum output pulse width. the purpose of q1 is to provide an increasing ramp current above a threshold established by r2 and r3 such that the duty cycle is further reduced with increasing v in . the minimum ramp current is: l r ( min ) = v ref - v in sense r 1 ? 4 v r 1 the threshold where v in begins to add extra ramp current is: v in ? 5.6v ? ? r2 + r3 r3 ? ? above the threshold, the ramp current will be: l r ( va ria b ) ? 4 r1 + v in - 5.6 r2 - 5.6 r3 uc1841 uc2841 uc3841 error latch internal circuitry programmable soft start and restart delay circuit the error latch consists of q5 and q6 which, when both on, turns off the pwm output and pulls the slow-start pin low. this latch is set by either the over-voltage or current shut down comparators, or by a high signal on pin 4. reset is accom- plished by either the reset comparator or a low signal on pin 4. an activation time delay can be provided with an external capacitor on pin 4 in conjunction with the ? 100 m a collector current from q4. unitrode integrated circuits 7 continental bl vd. merrimack, nh 03054 tel. (603) 424-2410 fax (603) 424-3460 voltage feed-forward combined with maximum duty-cycle clamp current mode control 8
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