document no. 70-0289-05 www.psemi.com page 1 of 10 ?2009-2010 peregrine semiconductor corp. all rights reserved. rf1 rf2 ctrl ls rfc 50 ? 50 ? cmos control driver esd esd the PE42556 rf switch is designed for use in test/ate, cellular and other wireless applications. this broadband general purpose switch maintains excellent rf performance and linearity from 9khz through 13500 mhz. the PE42556 integrates on-board cmos control logic driven by a single-pin, low voltage cmos control input. it also has a logic select pin which enables changing the logic definition of the control pin. additional features include a novel user defined logic table, enabled by the on-board cmos circuitry. the PE42556 also exhibits excellent isolation of 26 db at 13500 mhz, fast settling time, and is offered in a tiny flip chip package. the PE42556 is manufactured on peregrine?s ultracmos? process, a patented variation of silicon-on-insulator (soi) technology on a sapphire substrate, offering the performance of gaas with the economy and integration of conventional cmos. product specification spdt ultracmos? rf switch 9 khz - 13500 mhz product description figure 1. functional diagram PE42556 flip chip features ? harp?-technology-enhanced ? eliminates gate lag ? no insertion loss or phase drift ? fast settling time ? next gen 0.25 m process technology ? single-pin 3.3 v cmos logic control ? high isolation: 26 db@ 13.5 ghz ? low insertion loss: 1.7 db @ 13.5 ghz ? p1db: 33 dbm typical ? return loss: 13 db @ 13.5 ghz (typ) ? iip3: +56 dbm typical ? exceptional esd: 4000 v hbm ? absorptive switch design ? flip chip packaging figure 2. die photo (bumps up) flip chip packaging
product specification PE42556 page 2 of 10 ?2009-2010 peregrine semiconductor corp. all rights reserved. document no. 70-0289-05 ultracmos? rfic solutions table 1. electrical specifications: temp = 25c, v dd = 3.3v parameter conditions min typical max units operation frequency 9 khz 13500 mhz as shown insertion loss 9 khz - 10 mhz 10 - 3000 mhz 3000 - 7500 mhz 7500 - 10000 mhz 10000 - 13500 mhz 0.85 0.92 0.98 1.07 1.74 0.93 1.06 1.23 1.41 2.65 db db db db db isolation ? rf1 to rf2 9 khz - 10 mhz 10 - 3000 mhz 3000 - 7500 mhz 7500 - 10000 mhz 10000 - 13500 mhz 76.5 43.5 30.0 24.0 15.5 88.5 46.0 31.5 25.5 17.5 db db db db db return loss 9 khz - 10 mhz 10 - 3000 mhz 3000 - 7500 mhz 7500 - 10000 mhz 10000 - 13500 mhz 22.5 22.0 17.0 16.0 13.0 db db db db db switching time 50% ctrl to 90% or 10% of final value (-40 to +85 c) 3.3 4.0 s input 1 db compression 1,2 13500 mhz 33 dbm input ip3 1 13500 mhz 56 dbm isolation ? rfc to rf1 9 khz - 10 mhz 10 - 3000 mhz 3000 - 7500 mhz 7500 - 10000 mhz 10000 - 13500 mhz 72.5 39.0 31.5 27.0 21.5 84.0 40.5 33.0 30.5 26.5 db db db db db isolation ? rfc to rf2 9 khz - 10 mhz 10 - 3000 mhz 3000 - 7500 mhz 7500 - 10000 mhz 10000 - 13500 mhz 75.5 39.5 31.5 27.5 21.0 87.0 41.0 33.0 30.5 26.0 db db db db db settling time 50% ctrl to 0.05 db final va lue (-40 to +85 c) rising edge 50% ctrl to 0.05 db final value (-40 to +85 c) falling edge 8.5 9.5 10.0 13.5 s s input ip2 1 13500 mhz 107.5 dbm note: 1. linearity and power performance ar e derated at lower frequencies (< 1 mhz) 2. please refer to maximum operating pin (50 ? ) in table 3
product specification PE42556 page 3 of 10 document no. 70-0289-05 www.psemi.com ?2009-2010 peregrine semiconductor corp. all rights reserved. table 2. bump descriptions table 4. absolute maximum ratings electrostatic discharge (esd) precautions when handling this ultracmos? device, observe the same precautions that you would use with other esd- sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified. latch-up avoidance unlike conventional cmos devices, ultracmos? devices are immune to latch-up. figure 3. bump configuration (bumps up) bump no. bump name description 1 v ss negative supply voltage or gnd connection (note 3) 2, 13, 14 d-gnd digital ground 3, 5, 7, 9 gnd ground 4 rf2 rf port 2 6 rfc rf common 8 rf1 rf port 1 10 ls logic select - used to determine the definition for the ctrl pin (see table 5) 11 v dd nominal 3.3 v supply connection 12 ctrl cmos logic level table 5. control logic truth table exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. table 3. operating ranges note: 5. please consult figures 4 and 5 (low-frequency graphs) for recommended low-frequency operating power level. 6. human body model (hbm, mil_std 883 method 3015.7) logic select (ls) the logic select feature is used to determine the definition for the ctrl pin. note: 3. use vss (bump 1, vss = -vdd) to bypass and disable internal negative voltage generator. connect vss (bump 1) to gnd (vss = 0v) to enable internal negative voltage generator. ls ctrl rfc-rf1 rfc-rf2 0 0 off on 0 1 on off 1 0 on off 1 1 off on symbol parameter/conditions min max units v dd power supply voltage -0.3 4.0 v v i voltage on any input except for ctrl and ls inputs -0.3 v dd + 0.3 v v ctrl voltage on ctrl input 4.0 v v ls voltage on ls input 4.0 v t st storage temperature range -65 150 c t op operating temperature range -40 85 c p in 5 (50 ? ) 9 khz 1 mhz 1 mhz 13.5 ghz fig. 4,5 30 dbm dbm v esd esd voltage (hbm) 6 esd voltage (machine model) 4000 300 v v parameter min typ max units v dd positive power supply voltage 3.0 3.3 3.6 v v dd negative power supply voltage -3.6 -3.3 -3.0 v i dd power supply current (v ss = -3.3v, v dd = 3.0 to 3.6v, -40 to +85 c) 8.0 12.5 a control voltage high 0.7xv dd v control voltage low 0.3xv dd v p in rf power in 4 (50 ? ): 9 khz 1 mhz 1 mhz 13.5 ghz fig. 4,5 30 dbm dbm i dd power supply current (v ss = 0v, v dd = 3.0 to 3.6v, -40 to +85 c) 21.5 29.0 a i ss negative power supply current (v ss = -3.3v, v dd = 3.0 to 3.6v, -40 to +85 c) -18.0 -24.0 a vdd vss gnd ct rl ls rf1 rf2 rf c d- gnd d- gnd dg nd gnd gnd gnd 1 2 3 4 5 11 10 9 8 7 12 13 14 6 flip chip packaging switching frequency the PE42556 has a maximum 25 khz switching rate when the internal negative voltage generator is used (bump1=gnd). the rate at which the PE42556 can be switched is only limited to the switching time (table 1) if an external negativ e supply is provided (bump1=vss). spurious performance the typical spurious performance of the PE42556 is -116 dbm when vss=0v (bump 1 = gnd). if further improvement is desired, the internal negative voltage generator can be disabled by setting vss = -vdd. note: 4. please consult figures 4 and 5 (low-frequency graphs) for recommended low-frequency operating power level.
product specification PE42556 page 4 of 10 ?2009-2010 peregrine semiconductor corp. all rights reserved. document no. 70-0289-05 ultracmos? rfic solutions power handling scaling with frequency 0 5 10 15 20 25 30 1 10 100 1000 freq (khz) operating power offset (db) -12 -10 -8 -6 -4 -2 0 2 4 6 8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) input power (dbm) upper power limit figure 5 shows how the power limit in figure 4 will increase with frequency. as the frequency increases, the contours and maximum power limit curve will increase with the increase in power handling shown on the curve. figure 4. maximum operating power limit vs. vdd and input power @ 9 khz figure 5. operating power offset vs. frequency (normalized to 9khz) figure 4 provides guidelines of how to adjust the vdd and input power to the PE42556 device. the upper limit curve represents the maximum input power vs vdd recommended for this part at low frequencies only. please consult table 3 for the 1 mhz 13.5 ghz range. to allow for sustained operation under any load vswr condition, max power should be kept 6db lower than max power in 50 ohm. power handling examples example 1: maximum power handling at 100 khz, z=50 ohms, vswr 1:1, and vdd=3v ? the power handling offset for 100 khz from fig. 5 is 7 db ? the max power handling at vdd = 3 v is 5.5 db from fig. 4 ? derate power under mismatch conditions ? total maximum power handling for this example is 7 db + 5.5 db = 12.5 dbm low frequency power handling: z l = 50 ?
product specification PE42556 page 5 of 10 document no. 70-0289-05 www.psemi.com ?2009-2010 peregrine semiconductor corp. all rights reserved. evaluation kit figure 6. evaluation board layouts peregrine specification 101/0402 figure 7. evaluation board schematic peregrine specification 102/0478 the spdt switch ek board was designed to ease customer evaluation of peregrine's PE42556 (dual use with pe42554). the rf common port is connected through a 50ohm transmission line via the top sma connector, j1. rf1 and rf2 are connected through 50ohm transmission lines via sma connectors j3, and j2, respectively. a through 50ohm transmission line is available via sma connectors j4 and j5. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. the board is constructed of a four metal layers with a total thickness of 62 mils. the top and bottom layers are rogers ro4003 material with an 8 mil core and er=3.55. the middle layers provide ground for the transmission lines. the rf transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 15 mils, and trace gaps of 10 mils. x general comments -- transmission lines connected to j1, j2, and j3 should have exactly the same electrical length. j4 to j5. notes: 1. use 101-0402-02 pcb should have the same length as j4 and j5 and be in parallel to the path from j2 to j3 including the distance through the part 6 rfc 8 rf1 4 rf2 10 ls 11 vdd 12 ctl 1 vss 2 g0 14 g7 13 g6 9 g5 7 g4 5 g2 3 g1 u1 pe42554 1 ctl 3 ls 5 nc 7 vdd 2 gnd 4 gnd 6 gnd 8 gnd 9 vss 11 gnd 10 gnd 12 gnd j9 header, 12 pin 1 2 j3 1 2 j2 1 2 j5 1 2 j4 1 2 j1
product specification PE42556 page 6 of 10 ?2009-2010 peregrine semiconductor corp. all rights reserved. document no. 70-0289-05 ultracmos? rfic solutions figure 11. isolation: active port to isolated port @ 3.3 v figure 10. insertion loss: rfx @ 25 c figure 8. nominal insertion loss: rf1, rf2 figure 9. insertion loss: rfx @ 3.3 v performance plots: temperature = 25 c, v dd = 3.3 v unless otherwise indicated figure 12. isolation: active port to isolated port @ 25 c figure 13. isolation: rfc to isolated port @ 3.3 v
product specification PE42556 page 7 of 10 document no. 70-0289-05 www.psemi.com ?2009-2010 peregrine semiconductor corp. all rights reserved. iip3: third order distortion from 9khz - 14 ghz 0 10 20 30 40 50 60 70 1.0e+3 10 .0e + 3 100. 0e +3 1. 0e +6 10 . 0e+ 6 100.0e+6 1. 0e +9 10.0e+9 10 0. 0e+ 9 frequency [hz] linearity [dbm] nominal perf ormance figure 17. iip3: third order distortion from 9khz - 14ghz figure 16. return loss at active port @ 25 c figure 14. isolation: rfc to isolated port @ 25 c figure 15. return loss at active port @ 3.3 v performance plots: temperature = 25 c, v dd = 3.3 v unless otherwise indicated
product specification PE42556 page 8 of 10 ?2009-2010 peregrine semiconductor corp. all rights reserved. document no. 70-0289-05 ultracmos? rfic solutions figure 18. pad layout (bumps up) vdd vss gnd ctrl ls rf1 rf2 rfc d-gnd d-gnd dgnd gnd gnd gnd singulated die size: 1.1 x 2.0 mm (400um ball pitch) table 6. mechanical specifications parameter minimum typical maximum units test conditions die size, drawn (x,y) 996 x 1896 m as drawn die size, singulated (x,y) 1080 x 1980 1100 x 2000 1150 x 2050 m including excess sapphire, max. tolerance = -20/+50 m wafer thickness 180 200 220 m wafer size 150 mm ball pitch 400 m ball height 72.25 85 97.75 m ball diameter 110 m typical ubm diameter 85 90 95 m table 7. bump coordinates bump # bump name bump center (m) x y 1 vss 400 850 2 dgnd 400 450 3 gnd4 400 50 4 rf2 400 -350 5 gnd3 400 -750 6 rfc 0 -750 7 gnd1 -400 -750 8 rf1 -400 -350 9 gnd2 -400 50 10 ls -400 450 11 vdd -400 850 12 ctrl 0 850 13 dgnd 0 450 14 dgnd 0 50 1 2 3 4 5 11 10 9 8 7 12 13 14 6 all bump locations originate from the die center and refer to the center of the bump. ball pitch is 400 m. 2000 m -20/+50 m 1100 m -20/+50 m rohs compliant lead-free solder balls ? solder ball composition: 95.5%sn/3.5%ag/ 1.0%cu
product specification PE42556 page 9 of 10 document no. 70-0289-05 www.psemi.com ?2009-2010 peregrine semiconductor corp. all rights reserved. table 8. ordering information logo pin #1 4.00 .05 (.157 .002) 4.00 .05 (.157 .002) 1.50 + .10 (.059 + .004) 2.00 .05 (.079 .002) 3.50 .05 (.138 .002) 8.00 +.30 -.10 (.315 +.012 - .004) 1.75 .10 (.069 .004) bump 1 drawing not drawn to scale, pocket hole diameter 0.60.05mm .229 .02 (.009 .0008) a o 1.2 .05 (.047 .002) .45 .05 (.018 .002) 2.1 .05 (.083 .002) a o = 1.2 b o = 2.1 k o = 0.45 k o b o note: bumped die are oriented active side down maximum cavity angle 5 o tape feed direction figure 19. tape and reel specifications device orientation in tape bump side down bump 1 order code package specification shipping method PE42556di die on cut tape and reel 81-0012 loose or cut tape PE42556di-z die on full tape and reel 81-0012 1,000 dice / reel ek42556-01 evaluation kit 1/ box PE42556dbi die in waffle pack 81-0015 204 dice / waffle pack
product specification PE42556 page 10 of 10 ?2009-2010 peregrine semiconductor corp. all rights reserved. document no. 70-0289-05 ultracmos? rfic solutions sales offices the americas peregrine semiconductor corporation 9380 carroll park drive san diego, ca 92121 tel: 858-731-9400 fax: 858-731-9499 europe peregrine semiconductor europe batiment maine 13-15 rue des quatre vents f-92380 garches, france tel: +33-1-4741-9173 fax : +33-1-4741-9173 for a list of representatives in your area, please refer to our web site at: www.psemi.com data sheet identification advance information the product is in a formative or design stage. the data sheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification the data sheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at an y time without notice in order to supply the best possible product. product specification the data sheet contains final dat a. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a cnf (customer notification form). the information in this data sheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which persona l injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental dam ages, arising out of the use of its products in such applications. the peregrine name, logo, and utsi are registered trademarks and ultracmos, harp, multiswitch and dune are trademarks of peregrine semiconductor corp. high-reliability and defense products americas san diego, ca, usa phone: 858-731-9475 fax: 848-731-9499 europe/asia-pacific aix-en-provence cedex 3, france phone: +33-4-4239-3361 fax: +33-4-4239-7227 peregrine semiconductor, asia pacific (apac) shanghai, 200040, p.r. china tel: +86-21-5836-8276 fax: +86-21-5836-7652 peregrine semiconductor, korea #b-2607, kolon tripolis, 210 geumgok-dong, bundang-gu, seongnam-si gyeonggi-do, 463-943 south korea tel: +82-31-728-3939 fax: +82-31-728-3940 peregrine semiconductor k.k., japan teikoku hotel tower 10b-6 1-1-1 uchisaiwai-cho, chiyoda-ku tokyo 100-0011 japan tel: +81-3-3502-5211 fax: +81-3-3502-5213
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