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| ibm powernp? np4gs3 databook preliminary
0.1 copyright and disclaimer ? copyright international business machines corporation 1999, 2000 all rights reserved us government users restricted rights - use, duplication or disclosure restricted by gsa adp schedule contract with ibm corp. printed in the united states of america september 2000 the following are trademarks of international business machines corporation in the united states, or other countries, or both. ibm ibm logo powerpc other company, product and service names may be trademarks or service marks of others. all information contained in this document is subject to change without notice. the products described in this docu- ment are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. the information contained in this document does not affect or change ibm product specifications or warranties. nothing in this document shall operate as an express or implied license or indemnity under the intellec- tual property rights of ibm or third parties. all information contained in this document was obtained in specific environ- ments, and is presented as an illustration. the results obtained in other operating environments may vary. while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. the information contained in this document is provided on an "as is" basis. in no event will ibm be liable for damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6351 the ibm home page can be found at http://www.ibm.com the ibm microelectronics division home page can be found at http://www.chips.ibm.com np3_dl_title.fm.01 09/25/00 note: this document contains information on products in the design, sampling and/or initial production phases of development. this information is subject to change without notice. verify with your ibm field applications engineer that you have the latest version of this document before finalizing a design. np4gs3 preliminary ibm powernp np3_dltoc.fm 09/25/00 contents page 3 contents list of tables ................................................................................................................. 11 list of figures ............................................................................................................... 17 about this book ........................................................................................................... 19 who should read this manual ........................................................................................................ .. 19 related publications ............................................................................................................ ............... 19 conventions used in this manual .................................................................................................... .19 1. general information ................................................................................................... 21 1.1 features .................................................................................................................... ...................... 21 1.2 ordering information ......................................................................................................... ............ 22 1.3 overview .................................................................................................................... ..................... 23 1.4 np4gs3-based system design .................................................................................................... 23 1.4.1 coprocessors .............................................................................................................. ........... 24 1.4.2 hardware accelerators ...................................................................................................... ..... 24 1.4.3 np4gs3 memory .............................................................................................................. ..... 24 1.4.4 distributed software model .................................................................................................. .. 24 1.5 np4gs3 structure ............................................................................................................. ............. 25 1.6 np4gs3 data flow .............................................................................................................. ........... 26 2. physical description .................................................................................................. 29 2.1 pin information .............................................................................................................. ................. 30 2.1.1 pll filter circuit .......................................................................................................... ........... 65 2.1.2 thermal i/o usage ........................................................................................................... ...... 66 2.1.2.1 temperature calculation ................................................................................................. 6 6 2.1.2.2 measurement calibration ................................................................................................ 66 2.2 mechanical specifications .................................................................................................... ........ 69 2.3 signal pin lists .............................................................................................................. ................ 71 2.4 ieee 1149 (jtag) compliance .................................................................................................... .. 91 2.4.1 statement of jtag compliance ............................................................................................. 91 2.4.2 jtag compliance mode ........................................................................................................ 91 2.4.3 jtag implementation specifics ............................................................................................. 91 2.4.4 brief overview of jtag instructions ....................................................................................... 92 3. pmm overview ............................................................................................................ 93 3.1 ethernet overview ............................................................................................................ .............. 93 3.2 pos overview ................................................................................................................. .............. 102 3.2.1 pos counters ............................................................................................................... ....... 102 3.2.1.1 long frames .............................................................................................................. ... 102 4. ingress enqueuer / dequeuer / scheduler ............................................................. 111 4.1 overview .................................................................................................................... ................... 111 4.2 ingress flow control .......................................................................................................... ........ 112 4.2.1 overview .................................................................................................................. ............. 112 np4gs3 ibm powernp preliminary contents page 4 np3_dltoc.fm 09/25/00 4.2.2 flow control hardware facilities ..........................................................................................112 4.2.3 hardware function .......................................................................................................... ......114 4.2.3.1 exponentially weighted moving average (ewma) .......................................................114 4.2.3.2 flow control hardware actions .....................................................................................114 5. switch interface ........................................................................................................115 5.1 overview .................................................................................................................... ...................115 5.2 ingress switch data mover (i-sdm) ............................................................................................117 5.2.1 cell header ................................................................................................................ ...........117 5.2.2 frame header ............................................................................................................... ........119 5.3 ingress switch cell interface (i-sci) ........................................................................................... 121 5.3.1 idle cell format ............................................................................................................ .........121 5.3.1.1 crc bytes: word 15 .....................................................................................................121 5.3.1.2 i-sci transmit header for an idle cell ..........................................................................122 5.4 switch data cell format - ingress and egress ..........................................................................123 5.5 data-aligned synchronous link (dasl) ....................................................................................124 5.6 egress switch cell interface (e-sci) ..........................................................................................12 4 5.6.1 output queue grant (oqg) reporting .................................................................................124 5.6.2 switch fabric to network processor egress idle cell ...........................................................125 5.6.3 receive header formats for sync cells ...............................................................................127 5.7 egress switch data mover (e-sdm) ...........................................................................................127 6. egress enqueuer / dequeuer / scheduler ..............................................................129 6.1 overview .................................................................................................................... ...................129 6.1.1 egress eds components .....................................................................................................13 0 6.2 operation ................................................................................................................... ...................132 6.3 egress flow control ........................................................................................................... .........136 6.3.1 overview .................................................................................................................. .............136 6.3.2 flow control hardware facilities ..........................................................................................136 6.3.3 remote egress status bus ...................................................................................................13 7 6.3.3.1 overview ................................................................................................................ ........137 6.3.3.2 bus sequence and timing ............................................................................................137 6.3.3.3 configuration ........................................................................................................... ......139 6.3.4 hardware function .......................................................................................................... ......139 6.3.4.1 exponentially weighted moving average (ewma) .......................................................139 6.3.4.2 flow control hardware actions .....................................................................................139 6.4 the egress scheduler .......................................................................................................... ........141 6.4.1 overview .................................................................................................................. .............141 6.4.2 egress scheduler components ............................................................................................143 6.4.2.1 scheduling calendars ...................................................................................................14 3 6.4.2.2 flow queues .............................................................................................................. ...144 6.4.2.3 target port queues .......................................................................................................1 46 6.4.3 configuring flow queues ..................................................................................................... 147 6.4.3.1 additional configuration notes ......................................................................................147 7. embedded processor complex ..............................................................................149 7.1 overview .................................................................................................................... ...................149 7.1.1 thread types ............................................................................................................... .........152 np4gs3 preliminary ibm powernp np3_dltoc.fm 09/25/00 contents page 5 7.2 dyadic protocol processor unit (dppu) .................................................................................... 153 7.2.1 core language processor (clp) ......................................................................................... 154 7.2.1.1 core language processor address map ...................................................................... 156 7.2.2 dppu coprocessors .......................................................................................................... .. 158 7.2.3 the data store coprocessor ................................................................................................ 159 7.2.3.1 data store coprocessor address map .......................................................................... 159 7.2.3.2 data store coprocessor commands ............................................................................ 165 7.2.4 the control access bus (cab) coprocessor ....................................................................... 173 7.2.4.1 cab coprocessor address map ................................................................................... 173 7.2.4.2 cab access to np4gs3 structures .............................................................................. 174 7.2.4.3 cab coprocessor commands ...................................................................................... 175 7.2.5 enqueue coprocessor ........................................................................................................ .. 176 7.2.5.1 enqueue coprocessor address map ............................................................................ 177 7.2.5.2 enqueue coprocessor commands ............................................................................... 183 7.2.6 checksum coprocessor ....................................................................................................... 188 7.2.6.1 checksum coprocessor address map .......................................................................... 188 7.2.6.2 checksum coprocessor commands ............................................................................. 189 7.2.7 string copy coprocessor ..................................................................................................... 192 7.2.7.1 string copy coprocessor address map ........................................................................ 193 7.2.7.2 string copy coprocessor commands ........................................................................... 193 7.2.8 policy coprocessor ......................................................................................................... ...... 194 7.2.8.1 policy coprocessor address map ................................................................................. 194 7.2.8.2 policy coprocessor commands .................................................................................... 194 7.2.9 counter coprocessor ........................................................................................................ ... 195 7.2.9.1 counter coprocessor address map .............................................................................. 195 7.2.9.2 counter coprocessor commands ................................................................................. 195 7.2.10 shared memory pool ......................................................................................................... . 198 7.3 interrupts and timers ......................................................................................................... ......... 199 7.3.1 interrupts ................................................................................................................ .............. 199 7.3.1.1 interrupt vector registers ............................................................................................. 199 7.3.1.2 interrupt mask registers ............................................................................................... 199 7.3.1.3 interrupt target registers ............................................................................................. 199 7.3.1.4 software interrupt registers .......................................................................................... 199 7.3.2 timers .................................................................................................................... ............... 199 7.3.2.1 timer interrupt counters ............................................................................................... 199 7.3.3 port configuration memory ................................................................................................... 200 7.3.3.1 port configuration memory index definition .................................................................. 200 7.3.4 port configuration memory contents definition ................................................................... 201 7.4 hardware classifier .......................................................................................................... ............ 202 7.4.1 ingress classification ..................................................................................................... ....... 202 7.4.1.1 ingress classification input ........................................................................................... 202 7.4.1.2 ingress classification output ......................................................................................... 204 7.4.2 egress classification ...................................................................................................... ...... 206 7.4.2.1 egress classification input ............................................................................................ 206 7.4.2.2 egress classification output ......................................................................................... 207 7.5 policy manager ............................................................................................................... .............. 208 7.6 counter manager .............................................................................................................. ............ 211 7.6.1 counter manager usage ...................................................................................................... 2 13 np4gs3 ibm powernp preliminary contents page 6 np3_dltoc.fm 09/25/00 8. tree search engine ..................................................................................................219 8.1 overview .................................................................................................................... ...................219 8.1.1 addressing control store .................................................................................................... ..219 8.1.2 control store use restrictions ..............................................................................................2 21 8.1.3 object shapes .............................................................................................................. ........221 8.1.4 illegal memory access ....................................................................................................... ...224 8.1.5 memory range checking .....................................................................................................22 5 8.2 trees and tree searches ........................................................................................................ .....225 8.2.1 input key and color register for fm and lpm trees ...........................................................226 8.2.2 input key and color register for smt trees ........................................................................227 8.2.3 direct table ............................................................................................................... ............227 8.2.3.1 pattern search control blocks (pscb) .........................................................................227 8.2.3.2 leaves and compare-at-end operation ........................................................................228 8.2.3.3 cache ................................................................................................................... .........228 8.2.3.4 cache flag and nrpscbs registers .............................................................................228 8.2.3.5 cache management ......................................................................................................228 8.2.3.6 search output ............................................................................................................ ...229 8.2.4 tree search algorithms ...................................................................................................... ..229 8.2.4.1 fm trees ................................................................................................................. ......229 8.2.4.2 lpm trees ................................................................................................................ .....229 8.2.4.3 smt trees ................................................................................................................ .....230 8.2.4.4 compare-at-end operation ...........................................................................................230 8.2.4.5 ropes ................................................................................................................... .........232 8.2.4.6 aging ................................................................................................................... ..........233 8.2.5 tree configuration and initialization .....................................................................................233 8.2.5.1 the ludeftable ........................................................................................................... .233 8.2.5.2 tse free lists (tse_fl) ..............................................................................................235 8.2.6 tse registers and register map .........................................................................................236 8.2.7 tse instructions ........................................................................................................... .........240 8.2.7.1 fm tree search (ts_fm) .............................................................................................240 8.2.7.2 lpm tree search (ts_lpm) .........................................................................................241 8.2.7.3 smt tree search (ts_smt) .........................................................................................242 8.2.7.4 memory read (mrd) ....................................................................................................243 8.2.7.5 memory write (mwr) ....................................................................................................244 8.2.7.6 hash key (hk) ............................................................................................................. ..244 8.2.7.7 read ludeftable (rdludef) .....................................................................................245 8.2.7.8 compare-at-end (compend) ......................................................................................245 8.2.8 gth hardware assist instructions ........................................................................................247 8.2.8.1 hash key gth (hk_gth) ............................................................................................247 8.2.8.2 read ludeftable gth (rdludef gth) ....................................................................248 8.2.8.3 tree search enqueue free list (tsenqfl) ................................................................248 8.2.8.4 tree search dequeue free list (tsdqfl) ...................................................................249 8.2.8.5 read current leaf from rope (rclr) ..........................................................................250 8.2.8.6 advance rope with optional delete leaf (ardl) .........................................................251 8.2.8.7 tree leaf insert rope (tlir) ........................................................................................251 8.2.8.8 clear pscb (clrpscb) ...............................................................................................252 8.2.8.9 read pscb (rdpscb) .................................................................................................252 8.2.8.10 write pscb (wrpscb) ..............................................................................................253 8.2.8.11 push pscb (pushpscb) ..........................................................................................254 8.2.8.12 distinguish (distpos) ................................................................................................254 8.2.8.13 tsr0 pattern (tsr0pat) ...........................................................................................255 np4gs3 preliminary ibm powernp np3_dltoc.fm 09/25/00 contents page 7 8.2.8.14 pattern 2dta (pat2dta) ........................................................................................... 255 8.2.9 hash functions ............................................................................................................. ........ 256 9. serial/parallel manager interface ............................................................................ 263 9.1 spm interface components ...................................................................................................... .. 263 9.2 spm interface data flow ........................................................................................................ ..... 264 9.3 spm interface protocol ........................................................................................................ ........ 265 9.4 spm cab address space .......................................................................................................... .. 267 9.4.1 byte access space ........................................................................................................... .... 267 9.4.2 word access space ........................................................................................................... .. 267 9.4.3 eeprom access space ...................................................................................................... 268 9.4.3.1 eeprom byte access .................................................................................................. 269 9.4.3.2 eeprom 2 byte access ............................................................................................... 270 9.4.3.3 eeprom 3 byte access ............................................................................................... 271 9.4.3.4 eeprom 4 byte access ............................................................................................... 272 10. embedded powerpc? .......................................................................................... 273 10.1 description ................................................................................................................ ................. 273 10.2 processor local bus and device control register buses .................................................... 274 10.3 universal interrupt controller (uic) ......................................................................................... 2 75 10.4 pci/plb macro ............................................................................................................... ............ 276 10.5 plb address map .............................................................................................................. ........ 278 10.6 cab address map .............................................................................................................. ........ 280 10.7 cab interface macro .......................................................................................................... ........ 281 10.7.1 powerpc cab address (pwrpc_cab_addr) register ...................................................... 283 10.7.2 powerpc cab data (pwrpc_cab_data) register ........................................................... 284 10.7.3 powerpc cab control (pwrpc_cab_cntl) register ......................................................... 285 10.7.4 powerpc cab status (pwrpc_cab_status) register ...................................................... 286 10.7.5 pci host cab address (host_cab_addr) register .......................................................... 287 10.7.6 pci host cab data (host_cab_data) register ................................................................ 288 10.7.7 pci host cab control (host_cab_cntl) register ............................................................. 289 10.7.8 pci host cab status (host_cab_status) register ........................................................... 290 10.8 mailbox communications and dram interface macro ........................................................... 291 10.8.1 mailbox communications between pci host and powerpc .............................................. 291 10.8.2 pci interrupt status (pci_interr_status) register .............................................................. 293 10.8.3 pci interrupt enable (pci_interr_ena) register ................................................................ 294 10.8.4 powerpc to pci host message resource (p2h_msg_resource) register ...................... 295 10.8.5 powerpc to host message address (p2h_msg_addr) register ....................................... 296 10.8.6 powerpc to host doorbell (p2h_doorbell) register ......................................................... 297 10.8.7 host to powerpc message address (h2p_msg_addr) register ....................................... 298 10.8.8 host to powerpc doorbell (h2p_doorbell) register ......................................................... 299 10.8.9 mailbox communications between powerpc and epc ..................................................... 300 10.8.10 epc to powerpc resource (e2p_msg_resource) register ........................................... 301 10.8.11 epc to powerpc message address (e2p_msg_addr) register ..................................... 302 10.8.12 epc to powerpc doorbell (e2p_doorbell) register ........................................................ 303 10.8.13 epc interrupt vector register .......................................................................................... 305 10.8.14 epc interrupt mask register ............................................................................................ 305 10.8.15 powerpc to epc message address (p2e_msg_addr) register ..................................... 306 10.8.16 powerpc to epc doorbell (p2e_doorbell) register ........................................................ 307 10.8.17 mailbox communications between pci host and epc .................................................... 309 np4gs3 ibm powernp preliminary contents page 8 np3_dltoc.fm 09/25/00 10.8.18 epc to pci host resource (e2h_msg_resource) register ............................................310 10.8.19 epc to pci host message address (e2h_msg_addr) register ......................................311 10.8.20 epc to pci host doorbell (e2h_doorbell) register .........................................................312 10.8.21 pci host to epc message address (h2e_msg_addr) register ......................................314 10.8.22 pci host to epc doorbell (h2e_doorbell) register .........................................................315 10.8.23 message status (msg_status) register ...........................................................................317 10.8.24 slave error address register (sear) ..............................................................................319 10.8.25 slave error status register (sesr) .................................................................................320 10.8.26 parity error counter (perr_count) register ......................................................................321 10.9 system start-up and initialization ............................................................................................ 322 10.9.1 np4gs3 resets ............................................................................................................. .....322 10.9.2 systems initialized by external pci host processors .........................................................323 10.9.3 systems with pci host processors and initialized by powerpc ........................................324 10.9.4 systems without pci host processors and initialized by powerpc ...................................325 10.9.5 systems without pci interface hardware and initialized by epc ......................................326 11. reset and initialization ...........................................................................................327 11.1 overview ................................................................................................................... ..................327 11.2 step 1: set i/os .............................................................................................................. .............328 11.3 step 2: reset the np4gs3 ....................................................................................................... ..329 11.4 step 3: boot ................................................................................................................. ...............329 11.4.1 boot the embedded processor complex (epc) .................................................................329 11.4.2 boot the powerpc ........................................................................................................... ...330 11.4.3 boot summary .............................................................................................................. ......330 11.5 step 4: setup 1 ............................................................................................................... ............330 11.6 step 5: diagnostics 1 ......................................................................................................... ........331 11.7 step 6: setup 2 ............................................................................................................... ............332 11.8 step 7: hardware initialization ............................................................................................... ...332 11.9 step 8: diagnostics 2 ......................................................................................................... ........333 11.10 step 9: operational ......................................................................................................... .........334 11.11 step 10: configure .......................................................................................................... .........334 11.12 step 11: initialization complete ............................................................................................. .335 12. debug facilities ......................................................................................................337 12.1 debugging picoprocessors .................................................................................................... ...337 12.1.1 single step ............................................................................................................... ...........337 12.1.2 break points .............................................................................................................. ..........337 12.1.3 cab accessible registers ..................................................................................................3 37 12.2 riscwatch .................................................................................................................. ................338 13. ibm powernp configuration ..................................................................................339 13.1 memory configuration ........................................................................................................ .......339 13.1.1 memory configuration register (memory_config) .............................................................340 13.1.2 dram parameter register (dram_parm) ........................................................................342 13.2 master grant mode register (mg_mode) .................................................................................344 13.3 tb mode register (tb_mode) ...................................................................................................3 45 13.4 egress reassembly sequence check register (e_reassembly_seq_ck) ..........................346 13.5 aborted frame reassembly action control register (afrac) ...........................................347 np4gs3 preliminary ibm powernp np3_dltoc.fm 09/25/00 contents page 9 13.6 packing control register (pack_ctrl) ...................................................................................... 348 13.7 initialization control registers ............................................................................................. .... 349 13.7.1 initialization register (init) ............................................................................................. .... 349 13.7.2 initialization done register (init_done) ............................................................................. 350 13.8 network processor ready register (npr_ready) ................................................................ 351 13.9 phase locked loop fail register (pll_lock_fail) ............................................................... 352 13.10 software controlled reset register (soft_reset) ................................................................ 353 13.11 ingress free queue threshold configuration ....................................................................... 354 13.11.1 bcb_fq threshold registers .......................................................................................... 354 13.11.2 bcb_fq threshold for guided traffic (bcb_fq_th_gt) ............................................. 354 13.11.3 bcb_fq_threshold_0 / _1 / _2 registers (bcb_fq_th_0/_1/_2) ................................. 355 13.12 ingress target dmu data storage map register (i_tdmu_dsu) ....................................... 356 13.13 embedded processor complex configuration ..................................................................... 357 13.13.1 powerpc core reset register (powerpc_reset) ........................................................... 357 13.13.2 powerpc boot redirection instruction registers (boot_redir_inst) ................................ 358 13.13.3 watch dog reset enable register (wd_reset_ena) ...................................................... 359 13.13.4 boot override register (boot_override) .......................................................................... 360 13.13.5 thread enable register (thread_enable) ....................................................................... 361 13.13.6 gfh data disable register (gfh_data_dis) .................................................................. 362 13.13.7 ingress maximum dcb entries (i_max_dcb) .................................................................. 363 13.13.8 egress maximum dcb entries (e_max_dcb) ................................................................. 364 13.13.9 my target blade address register (my_tb) .................................................................... 365 13.13.10 local target blade vector register (local_tb_vector) ................................................. 366 13.13.11 local mctarget blade vector register (local_mc_tb_max) ....................................... 367 13.14 flow control structures ..................................................................................................... ..... 368 13.14.1 ingress flow control hardware structures ....................................................................... 368 13.14.1.1 ingress transmit probability memory register (i_tx_prob_mem) ........................... 368 13.14.1.2 ingress pseudo-random number register (i_rand_num) ...................................... 369 13.14.1.3 free queue thresholds register (fq_th) ............................................................... 370 13.14.2 egress flow control structures ........................................................................................ 371 13.14.2.1 egress transmit probability memory (e_tx_prob_mem) register ........................... 371 13.14.2.2 egress pseudo-random number (e_rand_num) ................................................... 372 13.14.2.3 p0 twin count threshold (p0_twin_th) .................................................................. 373 13.14.2.4 p1 twin count threshold (p1_twin_th) .................................................................. 374 13.14.2.5 egress p0 twin count ewma threshold register (e_p0_twin_ewma_th) .......... 375 13.14.2.6 egress p1 twin count ewma threshold register (e_p1_twin_ewma_th) .......... 376 13.14.3 exponentially weighted moving average constant (k) register (ewma_k) .................. 377 13.14.4 exponentially weighted moving average sample period (t) register (ewma_t) .......... 378 13.14.5 remote egress status bus configuration enables (res_data_cnf) .............................. 379 13.15 target port data storage map (tp_ds_map) register ....................................................... 380 13.16 egress sdm stack threshold register (e_sdm_stack_th) ............................................... 383 13.17 free queue extended stack maximum size (fq_es_max) register ................................. 384 13.18 egress free queue thresholds .............................................................................................. 385 13.18.1 fq_es_threshold_0 register (fq_es_th_0) ............................................................... 385 13.18.2 fq_es_threshold_1 register (fq_es_th_1) ............................................................... 386 13.18.3 fq_es_threshold_2 register (fq_es_th_2) ............................................................... 387 13.19 discard flow qcb register (discard_qcb) .......................................................................... 388 13.20 frame control block fq size register (fcb_fq_max) ...................................................... 389 13.21 data mover unit (dmu) configuration .................................................................................... 390 13.22 qd accuracy register (qd_acc) ............................................................................................ 394 np4gs3 ibm powernp preliminary contents page 10 np3_dltoc.fm 09/25/00 13.23 packet over sonet control register (pos_ctrl) .................................................................395 13.24 packet over sonet maximum frame size (pos_max_fs) .................................................396 13.25 ethernet encapsulation type register for control (e_type_c) ..........................................397 13.26 ethernet encapsulation type register for data (e_type_d) ...............................................398 13.27 source address array (sa_array) .........................................................................................399 13.28 dasl initialization and configuration ....................................................................................400 13.28.1 dasl configuration register (dasl_config) ..................................................................400 13.28.2 dasl bypass and wrap register (dasl_bypass_wrap) ................................................402 13.28.3 dasl start register (dasl_start) ..................................................................................403 14. electrical and thermal specifications ..................................................................405 14.1 driver specifications ....................................................................................................... ...........426 14.2 receiver specifications ..................................................................................................... ........428 14.3 other driver and receiver specifications ................................................................................430 15. glossary of terms and abbreviations ..................................................................433 revision log .................................................................................................................443 np4gs3 preliminary ibm powernp np3_dllot.fm 09/25/00 list of tables page 11 list of tables table 1: i/o signal pin summary ..................................................................................................... ............ 31 table 2: ibm 28.4 gbps packet routing switch interface pins .................................................................... 32 table 3: flow control pins ......................................................................................................... .................. 33 table 4: z0 zbt sram interface pins .................................................................................................. ....... 33 table 5: z1 zbt sram interface pins .................................................................................................. ....... 34 table 6: zbt sram timing diagram legend .............................................................................................. 36 table 7: d3, d2, and d1 memory pins ................................................................................................... ...... 36 table 8: d0 memory pins ............................................................................................................ ................. 37 table 9: d4_0 / d4_1 memory pins ..................................................................................................... ........ 38 table 10: d6_5 / d6_4 / d6_3 / d6_2 / d6_1 / d6_0 memory pins ............................................................. 39 table 11: ds1 and ds0 pins .......................................................................................................... .............. 40 table 12: ddr timing diagrams legend ................................................................................................ ..... 43 table 13: pmm interface pins ....................................................................................................... ............... 43 table 14: pmm interface pin multiplexing ............................................................................................ ........ 44 table 15: parallel data bit to 8b/10b position mapping (tbi interface) ...................................................... 44 table 16: pmm interface pins pos32 mode .............................................................................................. .. 45 table 17: pmm interface signals: gmii mode ........................................................................................... ... 48 table 18: gmii timing diagram legend ................................................................................................ ...... 50 table 19: pmm interface pins: tbi mode ............................................................................................... ...... 50 table 20: tbi timing diagram legend ................................................................................................. ........ 53 table 21: pmm interface pins: smii mode .............................................................................................. ..... 53 table 22: smii timing diagram legend ................................................................................................ ....... 55 table 23: pos signals ............................................................................................................. .................... 55 table 24: pos timing diagram legend ................................................................................................. ...... 58 table 25: pci interface pins ....................................................................................................... .................. 59 table 26: pci timing diagram legend ................................................................................................. ....... 61 table 27: management bus pins ...................................................................................................... ........... 61 table 28: management bus timing diagram legend .................................................................................. 62 table 29: miscellaneous pins ...................................................................................................... ................. 63 table 30: signals requiring pull-up or pull-down ..................................................................................... .. 65 table 31: mechanical specifications ............................................................................................... ............. 70 table 32: complete signal pin listing by signal name ............................................................................... 71 table 33: complete signal pin listing by grid position ............................................................................... 81 table 34: jtag compliance-enable inputs ............................................................................................ ..... 91 table 35: implemented jtag public instructions ...................................................................................... .. 91 table 36: ingress ethernet counters ................................................................................................ ............ 97 table 37: egress ethernet counters ................................................................................................. ........... 99 table 38: ethernet support ........................................................................................................ ................ 101 table 39: receive counter ram addresses for ingress pos mac ......................................................... 102 table 40: transmit counter ram addresses for egress pos mac ......................................................... 104 table 41: pos support ............................................................................................................. ................. 109 table 42: list of flow control hardware facilities .................................................................................... . 113 table 43: cell header fields ....................................................................................................... ............... 118 table 44: frame header fields ...................................................................................................... ............ 119 table 45: idle cell format transmitted to the switch interface .................................................................. 121 table 46: switch data cell format ................................................................................................... .......... 123 table 47: receive cell header byte h0 for an idle cell ............................................................................. 126 table 48: idle cell format received from the switch interface - 16-blade mode ..................................... 126 table 49: idle cell format received from the switch interface - 64-blade mode ..................................... 127 table 50: list of flow control hardware facilities .................................................................................... . 136 np4gs3 ibm powernp preliminary list of tables page 12 np3_dllot.fm 09/25/00 table 51: flow queue parameters .................................................................................................... .........141 table 52: valid combinations of scheduler parameters ............................................................................143 table 53: configure a flow qcb ...................................................................................................... ..........147 table 54: core language processor address map ....................................................................................156 table 55: coprocessor instruction format ........................................................................................... .......158 table 56: data store coprocessor address map .......................................................................................15 9 table 57: ingress datapool byte address definitions ................................................................................16 1 table 58: egress frames datapool quadword addresses ........................................................................164 table 59: datapool byte addressing with cell header skip .......................................................................164 table 60: number of frame-bytes in the datapool ....................................................................................165 table 61: data store coprocessor commands summary .........................................................................167 table 62: wreds input ............................................................................................................. .................167 table 63: wreds output ............................................................................................................ ...............168 table 64: rdeds input ............................................................................................................. .................168 table 65: rdeds output ............................................................................................................ ................168 table 66: wrids input ............................................................................................................. ..................169 table 67: wrids output ............................................................................................................ ................169 table 68: rdids input ............................................................................................................. ...................169 table 69: rdids output ............................................................................................................ .................170 table 70: rdmorei input ........................................................................................................... ...............170 table 71: rdmorei output .......................................................................................................... .............170 table 72: rdmoree input ........................................................................................................... ..............171 table 73: rdmoree output .......................................................................................................... ............171 table 74: edirty output ........................................................................................................... ................172 table 75: idirty inputs ........................................................................................................... ..................172 table 76: idirty output ........................................................................................................... .................173 table 77: leasetwin output ........................................................................................................ ...........173 table 78: cab coprocessor address map ............................................................................................... ..173 table 79: cab address field definitions ............................................................................................. .......174 table 80: cab address, functional island encoding .................................................................................174 table 81: cab coprocessor commands summary ...................................................................................175 table 82: cabarb input ............................................................................................................ ................175 table 83: cabaccess input ......................................................................................................... ............176 table 84: cabaccess output ........................................................................................................ ..........176 table 85: enqueue coprocessor address map ..........................................................................................1 77 table 86: ingress fcbpage description .............................................................................................. .......178 table 87: egress fcbpage description ............................................................................................... ......180 table 88: enqueue coprocessor commands summary ............................................................................183 table 89: enqe target queues ....................................................................................................... ..........183 table 90: egress target queue selection coding .....................................................................................18 3 table 91: egress target queue parameters ............................................................................................ ..184 table 92: type field for discard queue ............................................................................................... ......184 table 93: enqe command input ....................................................................................................... ........184 table 94: egress queue class definitions ............................................................................................ .....185 table 95: enqi target queues ....................................................................................................... ...........186 table 96: ingress target queue selection coding .....................................................................................1 86 table 97: ingress target queue fcbpage parameters .............................................................................186 table 98: enqi command input ....................................................................................................... ..........187 table 99: ingress-queue class definition ........................................................................................... .......187 table 100: enqclr command input .................................................................................................... ....188 table 101: enqclr output .......................................................................................................... .............188 table 102: checksum coprocessor address map .....................................................................................188 np4gs3 preliminary ibm powernp np3_dllot.fm 09/25/00 list of tables page 13 table 103: checksum coprocessor commands summary ....................................................................... 189 table 104: gengen/gengenx command inputs ................................................................................... 190 table 105: gengen/gengenx/genip/genipx command outputs ..................................................... 190 table 106: genip/genipx command inputs ........................................................................................... 19 1 table 107: chkgen/chkgenx command inputs ................................................................................... 191 table 108: chkgen/chkgenx/chkip/chkipx command outputs ...................................................... 192 table 109: chkip/chkipx command inputs ............................................................................................ 1 92 table 110: string copy coprocessor address map ................................................................................... 193 table 111: string copy coprocessor commands summary ...................................................................... 193 table 112: strcopy command input ................................................................................................... ....... 193 table 113: strcopy command output .................................................................................................. ..... 194 table 114: policy coprocessor address map ........................................................................................... . 194 table 115: policy coprocessor commands summary ............................................................................... 194 table 116: polaccess input ........................................................................................................ ................ 195 table 117: polaccess output ....................................................................................................... .............. 195 table 118: counter coprocessor address map ......................................................................................... 1 95 table 119: counter coprocessor commands summary ............................................................................ 196 table 120: ctrinc input ........................................................................................................... .................... 196 table 121: ctradd input ........................................................................................................... .................. 197 table 122: ctrrd/ctrrdclr input ................................................................................................... ............. 197 table 123: ctrrd/ctrrdclr output .................................................................................................. ........... 197 table 124: ctrwr15_0/ctrwr31_16 input ............................................................................................. ...... 198 table 125: shared memory pool ...................................................................................................... .......... 198 table 126: port configuration memory index .......................................................................................... ... 200 table 127: relationship between sp field, queue, and port configuration memory index ...................... 201 table 128: port configuration memory content ........................................................................................ . 201 table 129: protocol identifiers ................................................................................................... ................. 203 table 130: hccia table ............................................................................................................ ................ 204 table 131: protocol identifiers for frame encapsulation types ................................................................. 205 table 132: general purpose register bit definitions for ingress classification flags ............................... 205 table 133: flow control information values .......................................................................................... .... 206 table 134: hccia index definition .................................................................................................. ........... 207 table 135: polcb field definitions ................................................................................................. ............ 209 table 136: counter manager components .............................................................................................. .. 213 table 137: counter types .......................................................................................................... ................ 213 table 138: counter actions ........................................................................................................ ................ 213 table 139: counter definition entry format .......................................................................................... ..... 214 table 140: counter manager passed parameters ..................................................................................... 216 table 141: control store address mapping for tse references ............................................................... 219 table 142: cs address map and use .................................................................................................... .... 220 table 143: dtentry, pscb, and leaf shaping .......................................................................................... 2 21 table 144: height, width, and offset restrictions for tse objects ........................................................... 224 table 145: fm and lpm tree fixed leaf formats ..................................................................................... 225 table 146: smt tree fixed leaf formats ............................................................................................... ... 226 table 147: search input parameters ................................................................................................. ......... 226 table 148: cache status registers .................................................................................................. .......... 228 table 149: search output parameters ................................................................................................ ....... 229 table 150: dtentry and pscbline formats ............................................................................................. . 229 table 151: lpm dtentry and pscbline formats ..................................................................................... 230 table 152: nlasmt field format ..................................................................................................... ......... 230 table 153: compdeftable entry format ............................................................................................... ..... 231 table 154: ludeftable rope parameters .............................................................................................. ... 232 np4gs3 ibm powernp preliminary list of tables page 14 np3_dllot.fm 09/25/00 table 155: nlarope field format .................................................................................................... .........233 table 156: ludeftable entry definitions ............................................................................................ ........233 table 157: free list entry definition ............................................................................................... ............235 table 158: tse scalar registers for gth only .........................................................................................2 36 table 159: tse array registers for all gxh ............................................................................................ ...237 table 160: tse registers for gth (tree management) ............................................................................237 table 161: tse scalar registers for gdh and gth ..................................................................................237 table 162: pscb register format .................................................................................................... .........238 table 163: tse gth indirect registers ............................................................................................... ......238 table 164: address map for pscb0-2 registers in gth ...........................................................................239 table 165: general tse instructions ................................................................................................ ..........240 table 166: fm tree search input operands ............................................................................................. .240 table 167: fm tree search results (tsr) output .....................................................................................241 table 168: lpm tree search input operands ............................................................................................ 241 table 169: lpm tree search results (tsr) output ..................................................................................242 table 170: smt tree search input operands ............................................................................................ 242 table 171: smt tree search results (tsr) output ..................................................................................243 table 172: memory read input operands ............................................................................................... ...243 table 173: memory read output results ............................................................................................... ....243 table 174: memory write input operands .............................................................................................. ....244 table 175: hash key input operands .................................................................................................. .......244 table 176: hash key output results .................................................................................................. ........245 table 177: rdludef input operands .................................................................................................. .....245 table 178: rdludef output results .................................................................................................. ......245 table 179: compend input operands .................................................................................................. ....246 table 180: compend output results .................................................................................................. .....246 table 181: general gth instructions ................................................................................................ .........247 table 182: hash key gth input operands ............................................................................................... .247 table 183: hash key gth output results ............................................................................................... ..248 table 184: rdludef_gth input operands .............................................................................................. 248 table 185: rdludef_gth output results .............................................................................................. .248 table 186: tsenqfl input operands .................................................................................................. ......249 table 187: tsenqfl output results .................................................................................................. .......249 table 188: tsdqfl input operands ................................................................................................... .......249 table 189: tsdqfl output results ................................................................................................... ........250 table 190: rclr input operands ..................................................................................................... .........250 table 191: rclr output results ..................................................................................................... ..........250 table 192: ardl input operands ..................................................................................................... ..........251 table 193: ardl output results ..................................................................................................... ...........251 table 194: tlir input operands ..................................................................................................... ...........252 table 195: tlir output results ..................................................................................................... ............252 table 196: clrpscb input operands .................................................................................................. .....252 table 197: clrpscb output results .................................................................................................. ......252 table 198: rdpscb input operands ................................................................................................... ......253 table 199: rdpscb output results ................................................................................................... .......253 table 200: wrpscb input operands ................................................................................................... .....253 table 201: pushpscb input operands ................................................................................................. ...254 table 202: pushpscb output results ................................................................................................. ....254 table 203: distpos input operands .................................................................................................. ......254 table 204: distpos output results .................................................................................................. .......254 table 205: tsr0pat input operands .................................................................................................. ......255 table 206: tsr0pat output results .................................................................................................. .......255 np4gs3 preliminary ibm powernp np3_dllot.fm 09/25/00 list of tables page 15 table 207: pat2dta input operands .................................................................................................. ...... 255 table 208: pat2dta output results .................................................................................................. ....... 255 table 209: general hash functions .................................................................................................. ......... 256 table 210: field definitions for cab addresses ....................................................................................... . 268 table 211: plb master connections .................................................................................................. ........ 274 table 212: uic interrupt assignments ............................................................................................... ........ 275 table 213: plb address map for pci/plb macro ...................................................................................... 276 table 214: reset domains .......................................................................................................... ............... 322 table 215: reset and initialization sequence ........................................................................................ .... 327 table 216: set i/os checklist ...................................................................................................... ............... 328 table 217: setup 1 checklist ....................................................................................................... ............... 330 table 218: diagnostics 1 checklist ................................................................................................. ........... 331 table 219: setup 2 checklist ....................................................................................................... ............... 332 table 220: hardware initialization checklist ....................................................................................... ........ 333 table 221: diagnostic 2 checklist .................................................................................................. ............ 333 table 222: configure checklist .................................................................................................... .............. 334 table 223: absolute maximum ratings ................................................................................................ ...... 405 table 224: input capacitance (pf) .................................................................................................. ........... 405 table 225: operating supply voltages ............................................................................................... ........ 426 table 226: thermal characteristics ................................................................................................ ............ 426 table 227: definition of terms ..................................................................................................... .............. 426 table 228: 1.8 v cmos driver dc voltage specifications ........................................................................ 427 table 229: 1.8 v cmos driver minimum dc currents at rated voltage .................................................. 427 table 230: 2.5 v cmos driver dc voltage specifications ........................................................................ 427 table 231: 2.5 v cmos driver minimum dc currents at rated voltage .................................................. 427 table 232: 3.3 v-tolerant 2.5 v cmos driver dc voltage specifications ................................................ 427 table 233: 3.3 v lvttl driver dc voltage specifications ........................................................................ 428 table 234: 3.3 v lvttl/5.0 v-tolerant driver dc voltage specifications ................................................ 428 table 235: 3.3 v lvttl driver minimum dc currents at rated voltage .................................................. 428 table 236: 1.8 v cmos receiver dc voltage specifications .................................................................... 428 table 237: 2.5 v cmos receiver dc voltage specifications .................................................................... 428 table 238: 3.3 v lvttl receiver dc voltage specifications .................................................................... 429 table 239: 3.3 v lvttl/5v-tolerant receiver dc voltage specifications ................................................ 429 table 240: receiver maximum input leakage dc current input specifications ........................................ 429 table 241: lvds receiver dc specifications .......................................................................................... .. 430 table 242: sstl2 dc specifications ................................................................................................. ........ 430 np4gs3 ibm powernp preliminary list of tables page 16 np3_dllot.fm 09/25/00 np4gs3 preliminary ibm powernp np3_dllof.fm 09/25/00 - ibm confidential list of figures page 17 list of figures figure 1: function placement in an np4gs3-based system ..................................................................... 25 figure 2: np4gs3 major sections .................................................................................................... .......... 26 figure 3: embedded processor complex block diagram ........................................................................... 27 figure 4: devices interfaces ...................................................................................................... ................... 29 figure 5: zbt sram timing diagram ................................................................................................... ...... 35 figure 6: ddr timing diagram ....................................................................................................... ............ 41 figure 7: ddr read input timing diagram .............................................................................................. .. 41 figure 8: ddr write output timing diagram ............................................................................................ .. 42 figure 9: np4gs3 dmu bus clock connections ........................................................................................ 46 figure 10: np4gs3 dmu bus clock connections (pos overview) ........................................................... 47 figure 11: gmii timing diagram ..................................................................................................... ............ 49 figure 12: tbi timing diagram ...................................................................................................... ............. 52 figure 13: smii timing diagram ..................................................................................................... ............. 54 figure 14: pos timing diagram ...................................................................................................... ........... 57 figure 15: pci timing diagram ...................................................................................................... ............. 60 figure 16: management bus timing diagram ............................................................................................ .62 figure 17: pll filter circuit diagram ............................................................................................... ........... 66 figure 18: thermal monitor ........................................................................................................ ................. 66 figure 19: pins diagram ........................................................................................................... ................... 68 figure 20: mechanical diagram ..................................................................................................... .............. 69 figure 21: pmm overview ........................................................................................................... ................ 93 figure 22: smii timing diagram ..................................................................................................... ............. 94 figure 23: gmii timing diagrams .................................................................................................... ........... 94 figure 24: tbi timing diagrams ..................................................................................................... ............. 95 figure 25: ethernet mode .......................................................................................................... .................. 95 figure 26: gmii pos mode timing diagram .............................................................................................. .96 figure 27: receive pos8 interface timing for 8-bit data bus (oc-3c, oc-12, oc-12c, and oc-48). ...... 105 figure 28: receive pos32 interface timing for 32-bit data bus (oc-48c). .............................................. 106 figure 29: transmit pos8 interface timing for 8-bit data bus (oc-3c, oc-12) ........................................ 106 figure 30: transmit pos8 interface timing for 8-bit data bus (oc-12c, oc-48) ...................................... 107 figure 31: transmit pos32 interface timing for 32-bit data bus (oc-48c). ............................................. 107 figure 32: oc-3c/12/12c configuration ............................................................................................. ........ 108 figure 33: oc-48 configuration .................................................................................................... ........... 108 figure 34: oc-48c configuration ................................................................................................... ............ 109 figure 35: logical organization of the data flow managed by the ingress eds ..................................... 111 figure 36: switch interface functional units ........................................................................................ ..... 116 figure 37: cell header format ...................................................................................................... ............ 117 figure 38: frame header format ..................................................................................................... ......... 119 figure 39: crc calculation example ................................................................................................. ....... 122 figure 40: egress eds block diagram ................................................................................................. .... 130 figure 41: cell formats and storage in egress data store ...................................................................... 133 figure 42: tpq, fcb, and egress frame example .................................................................................. 134 figure 43: res bus timing .......................................................................................................... ............. 138 figure 44: the egress scheduler .................................................................................................... .......... 142 figure 45: embedded processor complex block diagram ....................................................................... 151 figure 46: dyadic protocol processor unit block diagram ....................................................................... 153 figure 47: core language processor ................................................................................................. ...... 155 figure 48: a frame in the ingress data store ........................................................................................... 162 figure 49: a frame in the egress data store .......................................................................................... 16 3 figure 50: ingress fcbpage format .................................................................................................. ....... 177 np4gs3 ibm powernp preliminary list of figures page 18 np3_dllof.fm 09/25/00 - ibm confidential figure 51: egress fcbpage format ................................................................................................... ....... 180 figure 52: split between picocode and hardware for the policy manager ................................................ 208 figure 53: counter manager block diagram ............................................................................................ . 212 figure 54: counter definition entry ................................................................................................ ............ 214 figure 55: counter blocks and sets .................................................................................................. ........ 215 figure 56: example shaping dimensions .............................................................................................. .... 223 figure 57: effects of using a direct table ............................................................................................ ..... 227 figure 58: example input key and leaf pattern fields ............................................................................. 231 figure 59: rope structure ......................................................................................................... ................. 232 figure 60: no-hash function ....................................................................................................... .............. 256 figure 61: 192-bit ip hash function ................................................................................................. ......... 257 figure 62: mac hash function ....................................................................................................... ........... 258 figure 63: network dispatcher hash function ......................................................................................... . 259 figure 64: 48-bit mac hash function ................................................................................................. ...... 260 figure 65: 60-bit mac hash function ................................................................................................. ...... 261 figure 66: spm interface block diagram .............................................................................................. ..... 263 figure 67: epc boot image in external eeprom .................................................................................... 264 figure 68: spm bit timing .......................................................................................................... ............... 266 figure 69: spm interface read protocol .............................................................................................. ..... 266 figure 70: spm interface write protocol ............................................................................................. ...... 266 figure 71: powerpc block diagram ................................................................................................... ....... 273 figure 72: polled access flow diagram ............................................................................................... ..... 282 figure 73: system environments .................................................................................................... ........... 328 figure 74: np4gs3 memory subsystems ................................................................................................ . 339 figure 75: 3.3v lvttl/5v tolerant bp33 and ip33 receiver input current/voltage curve ..................... 429 np4gs3 preliminary ibm powernp np3_dl_preface.fm.01 09/25/00 about this book page 19 of 444 about this book this databook describes the ibm powernp np4gs3 and explains the basics of building a system using it. a list of terms and abbreviations is provided in section 15. glossary of terms and abbreviations on page 433. who should read this manual this document is intended to provide information to programmers and engineers using the np4gs3 for development of interconnect solutions for internet or enterprise network providers. technology information to enable development of cards and boards includes electrical specifications and interface protocol and timings. programmer information includes descriptions of the dyadic protocol processors and the available command set. additional information on configuring the network processor features for operation such as the egress scheduler and the flow control hardware is provided. related publications ppc405gp embedded controller user?s manual ( http://www.chips.ibm.com/techlib/products/powerpc/ datasheets.html ) pci specification, version 2.2. ( http://www.pcisig.com ) conventions used in this manual the following conventions are used in this manual. 1. the bit notation for physical description, physical mac multiplexer, enqueuer / dequeuer / scheduler, switch interface, embedded processor complex, control access bus, and the serial/parallel manager interface, is non-ibm, meaning that bit zero is the least significant bit and bit 31 is the most significant bit in a 4-byte word. the bit notation for tree search engine and embedded powerpc is ibm-standard, meaning that bit 31 is the least significant bit and bit zero is the most significant bit in a 4-byte word. 2. nibble numbering is the same as byte numbering. the left-most nibble is most significant and starts at zero. 3. overbars, e.g. txenb , designate signals that are asserted ?low?. 4. numeric notation is as follows: hexadecimal values are preceded by x or x. for example: x?0b00?. binary values in text are either spelled out (zero and one) or appear in quotation marks. for example: ?10101?. np4gs3 ibm powernp preliminary about this book page 20 of 444 np3_dl_preface.fm.01 09/25/00 binary values in the default and description columns of the register sections are often isolated from text as in this example: 0: no action on read access 1: auto-reset interrupt request register upon read access 5. field length conventions are as follows: 1 byte = 8 bits 1word=4bytes 1 double word (dw) = 2 words = 8 bytes 1 quadword (qw) = 4 words = 16 bytes 6. for signal and field definitions, when a field is designated as reserved ('r'): as an input to the np4gs3 it must be sent as zero. as an output from the np4gs3 it must not be checked or modified. its use as code point results in unpredictable behavior. np3_dl_sec01_over.fm.01 09/25/00 np4gs3 preliminary ibm powernp general information page 21 of 444 1. general information 1.1 features 4.5 million packets per second (mpps) layer 2 and layer 3 switching. 40 fast ethernet / 4 gb macs accessed through smii, gmii, and tbi interfaces supporting indus- try standard phy components. the ethernet mac provides 36 ethernet statistics counters. software can define an additional one million counters. once these counts are defined, the hardware assists in updating them. with this hardware support, many standard mibs can be supported at wire speed. - supports ieee 802.3 ad link aggregation and vlan detection (frame type 8100). - 16xoc-3c / 4xoc-12 / 4xoc-12c / 1xoc-48 / 1xoc-48c integrated packet over sonet (pos) interfaces support industry standard pos framers. two data-aligned synchronous link (dasl) ports, rated 3.25 to 4 gbps, for attachment to the packet routing switch, another ibm pow- ernp np4gs3, or to itself through a wrap path for a stand-alone solution. (dasls are electri- cally i/o compliant with the eia/jedec jesd8- 6 standard for differential hstl.) addressing capability of 64 target network pro- cessors, allowing the design of a network inter- connect solution supporting 1024 ports. advanced flow control mechanisms which toler- ate high rates of temporary oversubscription without tcp collapse. geometric hash functions yield lower collision rates than conventional bit scrambling methods, providing faster lookups and more powerful search engines. hardware support for port mirroring 1 . depend- ing on the application, mirrored traffic can either share bandwidth with user traffic or use a sepa- rate switch data path, eliminating the penalty normally associated with port mirroring. support for jumbo frames (9018 without vlan, 9022 with vlan). hardware managed and software configured bandwidth allocation control of 2048 concurrent communication flows. embedded powerpc and external 33/66 mhz 32-bit pci bus for enhanced design flexibility. - supports riscwatch through the jtag interface eight dyadic protocol processor units (dppu) - two picocode engines per dppu - eight coprocessor units per dppu to reduce picocode path lengths for common tasks - multi-thread support of four threads per dppu (two per picocode engine) - zero context switching overhead between threads serial management interface to support physical layer devices, board and box functions ibm sa-27e, 0.18 m technology. voltage ratings. - 1.8 v supply voltage - 2.5 v and 3.3 v compatibility with drivers and receivers - 1.25 v reference voltage for sstl drivers - 1.5 v compatibility for dasl interfaces 1088-pin bottom surface metallurgy - ceramic column grid array (bsm-ccga) package with 815 signal i/o. ieee 1149.1a jtag compliant. 1. oc48c ports are not supported by port mirroring functions. . np4gs3 ibm powernp preliminary general information page 22 of 444 np3_dl_sec01_over.fm.01 09/25/00 1.2 ordering information part number description IBM32NPR161EPXCAC133 ibm powernp np4gs3 np4gs3 preliminary ibm powernp np3_dl_sec01_over.fm.01 09/25/00 general information page 23 of 444 1.3 overview the ibm powernp? np4gs3 is ibm?s latest technology for supporting media-rate, multi-layer ethernet switching. it also supports the ip over sonet (pos) and ppp protocol. the np4gs3 provides a highly cus- tomizable, scalable technology for the development of interconnect solutions for internet or enterprise net- work providers. a single device can be used in desktop solution or be a component in a large multi-rack solution with up to 1024 ports. when used with the ibm packet routing switch, addressing is limited to 640 ports. scaling of this nature is accomplished through the use of ibm?s high performance, non-blocking, packet switching technology and ibm?s data-aligned synchronous link (dasl) interface which can be adapted to other industry switch technologies. the np4gs3 integrates switching engine, search engine, and security functions on one device to support the needs of customers who require high capacity, media rate switching of layer 2 and 3 frames. three switch priority levels are supported for port mirroring, high priority user frames, and low priority frames. the device?s ability to enforce hundreds of rules with complex range and action specifications, a new industry benchmark for filtering capabilities, makes an np4gs3-based system uniquely suited for server farm applications. the np4gs3 contains dyadic protocol processor units that work with hardware accelerators to support high speed pattern search, data manipulation, internal chip management functions, frame parsing, and data prefetching. systems developed with the np4gs3 use a distributed software model. a rich instruction set includes condi- tional execution, packing (for input hash keys), conditional branching, signed and unsigned operations, counts of leading zeros, and more. to support this model, the device hardware and code development suite include on-chip debugger facilities, a picocode assembler, and a picocode and system simulator which decrease the time to market for new applications. the np4gs3?s scalability allows the design of multiple system configurations: low-end systems with only one device which can use the device?s switch interface to wrap traffic from the ingress side to the egress side. medium-end systems with two devices which are directly interconnected through their switch interfaces. high-end systems with up to 64 np4gs3s which are interconnected through a single or redundant switch. the ibm packet routing switch is limited to addressing up to 16 np4gs3s. 1.4 np4gs3-based system design the np4gs3 contains eight dyadic protocol processor units (dppus) with 16 k words of internal picocode instruction store, providing 2128 mips of processing power. each dppu contains two processors (clps) which share eight dedicated coprocessors. all eight dppus share three hardware accelerators. each clp can run two threads; each dppu can therefore run four threads. context switching occurs when the clp is waiting for a shared resource (for example, waiting for one of the coprocessors to complete an operation, return the results of a search, or access dram). context switching is accomplished by hardware assists that maintain separate sets of general purpose registers (gpr). coprocessors can run in parallel with the proto- col processors. the control store for the protocol processors is provided by both internal and external memories: internal sram for immediate access, external zbt sram for fast access, and external ddr sdram for large stor- age requirements. the internal control access bus (cab) allows access to internal registers, counters, and memory. the cab also includes an external interface to control instruction step and interrupt control for debugging and diagnostics. np4gs3 ibm powernp preliminary general information page 24 of 444 np3_dl_sec01_over.fm.01 09/25/00 1.4.1 coprocessors the data store coprocessor interfaces frame buffer memory (ingress and egress directions) providing a 320-byte working area. the checksum coprocessor calculates and verifies header checksums. the enqueue coprocessor manages control blocks containing key frame parameters. this coprocessor interfaces with the completion unit hardware assist, to enqueue frames to the switch and target port out- put queues. the cab interface coprocessor controls thread access to the cab through the cab arbiter. the string copy coprocessor accelerates data movement between coprocessors. the counter coprocessor manages counter updates for the picocode engines. the policy coprocessor determines if the incoming data stream complies with configured profiles. the tree search engine performs pattern analysis through tree searches, along with regular read and write accesses, all protected by memory range checking. 1.4.2 hardware accelerators the completion unit assures frame order. the dispatch unit parses the work out among the dyadic processors. the control store arbiter is a shared memory interface. 1.4.3np4gs3memory the np4gs3 utilizes: a common instruction memory which holds 16 k instruction words for normal processing and control functions a 128 k byte internal sram for input frame buffering 113 k bytes of internal sram control store high capacity external ddr dram for egress frame buffering and to support large forwarding tables external zbt sram for fast table access 1.4.4 distributed software model systems developed with the np4gs3 use a distributed software model. the system relies on a control point function to provide support for layer 2 and layer 3 routing protocols, layer 4 and layer 5 network applica- tions, and systems management. the control point function may be provided by an external microprocessor connected through industry standard full duplex ethernet links using either fast or gigabit ethernet. how- ever, control point functions in a smaller system configuration can be performed by the device?s embedded powerpc processor. forwarding and filtering tables created by the control point function are downloaded to the control store using guided frames. guided frames are the in-band control path between the control np4gs3 preliminary ibm powernp np3_dl_sec01_over.fm.01 09/25/00 general information page 25 of 444 point function and all network processor devices in a the system. other functions, such as forwarding, filtering and classification, are performed at wire speed in a distributed way by the hardware and resident picocode of each device in the system. 1.5 np4gs3 structure the np4gs3 has eight major functional blocks: embedded processor complex (epc) embedded 405 powerpc core. the control store interface provides for 64 mb program space for the power pc enqueuer / dequeuer / scheduler logic for frames traveling from the physical layer devices to the switch fabric (ingress-eds) enqueuer / dequeuer / scheduler logic for frames traveling from the switch fabric to the physical layer devices (egress-eds) ingress switch interface (ingress-switch) egress switch interface (egress-switch) physical mac multiplexer (ingress-pmm) receiving frames from the physical layer devices (ethernet, pos framers, etc.) figure 1: function placement in an np4gs3-based system packet routing switch ibm powernp cp 3.25 to 4 gbps control point ibm powernp control store l2 support (spanning tree...) networking management agent (rmon...) box services l2 forwarding filtering learning l3 forwarding filtering l4 flow classification priority shaping network management counters l3 support (ospf...) frame repository queueing flow control frame alteration multicast handling data store data store data store control store control store fdx ibm powernp ibm powernp np4gs3 ibm powernp preliminary general information page 26 of 444 np3_dl_sec01_over.fm.01 09/25/00 physical mac multiplexer (egress-pmm) transmitting frames to the physical layer devices 1.6 np4gs3 data flow the ingress eds places frames received from a physical layer device into the ingress data store. these frames are then identified as either normal data frames or system control guided frames and enqueued to the epc. the epc contains eight dyadic protocol processor units capable of operating on up to 32 frames in parallel. three of the threads within the eight dyadic protocol processors are enhanced: one for handling guided frames (the guided frame handler or gfh), one for building table data in control memory (the gen- eral table handler or gth), and one for handling communication with the embedded powerpc. the epc also contains the following: a dispatch unit to dispatch new frames to idle threads a completion unit to maintain frame sequence common instruction memory hardware classifier to parse the frame on-the-fly, preparing its processing by picocode ingress and egress data store interfaces to control read and write operations of data buffers control store arbiter to allow the processors to share access to the control memory cab control, cab arbiter, and cab interface to allow debug access to np4gs3 data structures figure 2: np4gs3 major sections embedded processor complex ingress eds egress eds enqueuer dequeuer scheduler enqueuer dequeuer data store ingress switch interface egress switch interface ddr sdram (10 to 13) zbt sram (2) internal srams data store ddr sdram ingress - pmm multiplexed macs egress - pmm multiplexed macs a b c d e physical layer devices scheduler dmu bus dmu bus 405 powerpc core spm interface np4gs3 preliminary ibm powernp np3_dl_sec01_over.fm.01 09/25/00 general information page 27 of 444 data frames are dispatched by the dispatch unit to the next available protocol processor for performing frame lookups, filtering, etc. frame data is passed to the protocol processor along with results from the hard- ware classifier (hc). the hc parses bridged, ip, and ipx frame formats and passes the results to the proto- figure 3: embedded processor complex block diagram control store arbiter h0 h1 z0 d1 d2 d6 on-chip memories off-chip memories dispatch unit ingress ds egress ds interface instruction memory cab arbiter debug, single step control & ingress eds queue egress eds queue ingress data ingress data store interface (rd) egress data egress data store interface (rd) cab internal epc cab ludeftable comptable freeqs interrupts freezeepc exception d0 completion unit counter manager policy manager hardware classifier d3 405 powerpc core interrupt dppu 1 dppu 8 tree search engine store and arbiter (rd+wr) and arbiter (rd+wr) store interface interface interrupts & timers np4gs3 ibm powernp preliminary general information page 28 of 444 np3_dl_sec01_over.fm.01 09/25/00 col processor. the results determine the tree search algorithm and the starting common instruction address (cia). tree search algorithms supported are: full match trees (fixed size patterns requiring exact match, such as layer 2 ethernet mac tables) longest prefix match trees (patterns requiring variable length matches, such as subnet ip forwarding) software managed trees (patterns defining a range or a bit mask set, such as those used for filter rules) the tree search engine (tse) performs table searches. the tse performs control store accesses indepen- dently, freeing the protocol processor for parallel execution. the control store contains all tables, counters, and any other data needed by the picocode. the control store arbiter manages all control store operations, allocating memory bandwidth among the threads of the protocol processors. frame data is accessed through the data store coprocessor, which manages a 320-byte data buffer and con- trol blocks for data store operations. ingress frame alterations, such as vlan header insertion or overlay, are defined once the forwarding requirements are found. these alterations are not performed by the embed- ded processor complex. instead, hardware flags are associated with the frame and ingress switch interface hardware performs alterations while moving data. other frame alterations can be accomplished by the pico- code and the data store coprocessor by directly modifying frame contents held in the ingress data store. control data is gathered and used to build switch headers and frame headers prior to sending frames to the switch fabric. control data includes switch information, such as the destination switch port of the frame, and information for the egress side of the target device to help the device expedite frame lookup of destination ports and multicast or unicast operations, and determine necessary egress frame alterations. upon completion, the enqueue coprocessor builds the necessary information to enqueue the frame to the switch interface and provides it to the completion unit (cu). the cu guarantees the frame order from the 32 threads to the switch interface queues. frames from the switch interface queues are segmented into 64-byte cells with cell header and frame header bytes inserted as they are transmitted to the switch interface. frames received from the switch interface are placed in egress data store (e-ds) buffers by the egress eds and presented to the epc. the dispatch unit fetches a portion of the frame and delivers it to an available dyadic protocol processor to perform frame forwarding. frame data is dispatched to the dyadic protocol pro- cessor along with data from the hc. the hc uses frame control data created by the ingress device to help determine the beginning cia. egress table searches support the same algorithms as those supported for ingress searches. the tse per- forms table searches, freeing the protocol processor to continue parallel execution. all control store opera- tions are managed by the control store arbiter, which allocates memory bandwidth among the threads of all the dyadic protocol processors. egress frame data is accessed through the data store coprocessor. the result of a successful lookup con- tains forwarding information and, if needed, frame alteration information. egress frame alterations can include vlan header deletion, time to live increment (ipx) or decrement (ip), ip header checksum recalculation, ethernet frame crc overlay, and mac da/sa overlay or insertion. these alterations are not performed by the embedded processor complex. rather, hardware flags are associated with the frame, and egress pmm hardware performs the alterations while moving data. upon completion, the enqueue coprocessor is used to build the necessary information for enqueueing the frame in the egress eds queues and provides it to the completion unit. the completion unit guarantees frame order for the eight dyadic protocol processor units? 32 threads to the egress eds queues feeding the egress ports. the completed frames are then sent by egress pmm hardware to the attached physical layer devices. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 29 of 444 2. physical description figure 4: devices interfaces data stores: sdram sram packet clk, test, reset, etc. b smll gmll tbi eeprom interface eeprom ibm powernp a smll gmll tbi pos c smll gmll tbi d pci interface switch a routing packet switch b routing note: thememoryarrayconsistsof the following ddr sdrams: drams 0 and 4 2 devices each drams 1, 2, and 3 1deviceeach dram 6 6devices ddr sdram ddr control store control store ddr sdram for d0/1/2/3 interface control store ddr sdram for d4 interface control store ddr sdram for d6 interface pos pos pos smll gmll tbi IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 30 of 444 np3_dl_sec02_phys.fm.01 09/25/00 2.1 pin information the tables listed below (found on pages 32?63) describe the device pins arranged by functionality: ibm 28.4 gbps packet routing switch interface pins interface between the np4gs3 and the packet routingswitchfabric. flow control pins z0 zbt sram interface pins interface to the z0 zero bus turnaround (zbt) sram for lookup. z1 zbt sram interface pins d3, d2, and d1 memory pins and d0 memory pins interface to the double-data rate (ddr) sdram used to implement the d3, d2, d1, and d0 memories. d6_5 / d6_4 / d6_3 / d6_2 / d6_1 / d6_0 memory pins interface to the double-data rate (ddr) sdram used to implement the powerpc store. d4_0 / d4_1 memory pins interface to the double-data rate (ddr) dram to implement the d4 memo- ries. ds1 and ds0 pins interface to the double-data rate (ddr) dram used to implement the ds1 and ds0 memories. pmm interface pins interface to the phy (tbi bus, smii bus, gmii bus, pos bus pci interface pins interface to the pci bus management bus pins are translated into various ?host? buses by an external fpga (spm). miscellaneous pins for information on signal pin locations, see table 32: complete signal pin listing by signal name on page 71 and table 33: complete signal pin listing by grid position on page 81. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 31 of 444 table 1: i/o signal pin summary interface quantity interface quantity dasl-a 32 dmu-a 31 dasl-b 32 dmu-b 31 master grant (master_grant) a and b 4 dmu-c 31 multicast grant (mc_grant) a and b 4 dmu-d 31 send grant (send_grant) a and b 2 rx_byte(1:0) 2 ingress free queue threshold (i_freeq_th) 1 pci 52 flow control pins [res_sync, res_data] 2 management bus 3 zbt0 57 2x switch clock differential 4 zbt1 39 dasl a/b select (switch_bna) 1 d1 / d2 / d3 shared (shared among five ddr sdrams) 6 core_clock (53.3 mhz) 1 d3_0 33 125 mhz clock 1 d2_0 33 reset 1 d1_0 33 not operational 1 d0 shared (clk, clk , ras, cas, ba(1:0)) 6testmode 2 d0_0/0_1 51 riscwatch/jtag 6 d4_0/d4_1 (clk, clk , ras, cas, ba(1:0)) (shared among two ddr sdrams) 6 pll_analog v dd 3 d4_0/d4_1 51 pll_analog gnd 3 d6 (clk, clk , ras, cas, ba(1:0)) (shared among six ddr sdrams) 6 thermal (_in/_out) 2 d6_0/d6_1/d6_2/d6_3/d6_4/d6_5 41 vref 12 ds0_0/0_1/ds1_0/1_1 shared (clk, clk , ras, cas, ba(1:0)) (shared among four ddr sdrams) 6 code boot strapping (boot_picocode, boot_ppc) 2 ds1_0/_1 51 spare test receivers 10 ds0_0/1 51 total used 777 unused 1 38 1. all unused pins should be left unconnected on the card. IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 32 of 444 np3_dl_sec02_phys.fm.01 09/25/00 table 2: ibm 28.4 gbps packet routing switch interface pins signal (clock domain) description type dasl_out_a(7:0) (switch clk * 8) the positive half of an output bus of eight custom low power differential drivers. runs at frequency switch_clock_a * 8. output dasl 1.5 v dasl_out_a(7:0) (switch clk * 8) the negative half of the 8-bit differential bus described above. runs at frequency switch_clock_a * 8. output dasl 1.5 v dasl_in_a(7:0) (switch clk * 8) the positive half of an input bus of eight custom low power differential receivers. runs at frequency switch_clock_a * 8. input dasl 1.5 v dasl_in_a(7:0) (switch clk * 8) the negative half of the 8-bit differential bus described above. runs at frequency switch_clock_a * 8. input dasl 1.5 v dasl_out_b(7:0) (switch clk * 8) the positive half of an output bus of eight custom low power differential drivers. runs at frequency switch_clock_b * 8. output dasl 1.5 v dasl_out_b(7:0) (switch clk * 8) the negative half of the 8-bit differential bus described above. runs at frequency switch_clock_b * 8. output dasl 1.5 v dasl_in_b(7:0) (switch clk * 8) the positive half of an input bus of eight custom low power differential receivers. runs at frequency switch_clock_b * 8. input dasl 1.5 v dasl_in_b(7:0) (switch clk * 8) the negative half of the 8-bit differential bus described above. runs at frequency switch_clock_b * 8. input dasl 1.5 v master_grant_a(1:0) (switch clk * 2) master grant a indicates whether the ?a? connection of the switch fabric is able to receive cells from the np4gs3. the definitions of these i/os are configured by the master grand mode configuration registers. see section 13.2 on page 344. input 5.0 v-tolerant 3.3 v lvttl 3.3 v master_grant_b(1:0) (switch clk * 2) master grant b indicates whether the ?b? connection of the switch fabric is able to receive cells from the np4gs3. the definitions of these i/os are configured by the master grand mode configuration registers. see section 13.2 on page 344. input 5.0 v-tolerant 3.3 v lvttl 3.3 v multicast_grant_a(1:0) multicast grant a indicates whether the ?a? connection of the switch fabric is able to receive multicast cells. 0 unable 1able bit 0 of this bus serves as the master grant for the high priority channel, and bit 1 for the low priority channel. this signal runs at frequency switch clock * 2. input 5.0 v-tolerant 3.3 v lvttl 3.3 v multicast_grant_b(1:0) multicast grant b indicates whether the ?b? connection of the switch fabric is able to receive multicast cells from the np4gs3. 0 unable 1able bit 0 of this bus serves as the master grant for the high priority channel, and bit 1 for the low priority channel. this signal runs at frequency switch clock * 2. input 5.0 v-tolerant 3.3 v lvttl 3.3 v send_grant_a (switch clk * 2) send grant a indicates whether the ?a? connection of the np4gs3 is able to receive cells from the switch fabric. 0 unable (the packet routing switch should send only idle cells) 1able the np4gs3 changes the state of this signal. output 5.0 v-tolerant 3.3 v lvttl 3.3 v IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 33 of 444 send_grant_b (switch clk * 2) send grant b indicates whether the ?b? connection of the np4gs3 is able to receive cells from the switch fabric. 0 unable (the packet routing switch should send only idle cells) 1able the np4gs3 changes the state of this signal. output 5.0 v-tolerant 3.3 v lvttl 3.3 v table 3: flow control pins signal description type i_freeq_th ingress free queue threshold 0 threshold not exceeded 1 threshold exceeded output 5.0 v-tolerant 3.3 v lvttl 3.3 v res_sync remote egress status synchronization (sync) is driven by the network processor that is con- figured to provide this signal. it is received by all other network processors. 1 shared data bus sync pulse. indicates start of time division multiplex cycle. input/output 5.0 v-tolerant 3.3 v lvttl 3.3 v res_data remote egress status data is driven by a single network processor during its designated time slot. 0 not exceeded 1 network processor?s exponentially weighted moving average (ewma) of the egress offered rate exceeds the configured threshold. input/output 5.0 v-tolerant 3.3 v lvttl 3.3 v table 4: z0 zbt sram interface pins signal description type lu_clk look-up clock. 7.5 ns period (133 mhz). output cmos 2.5 v lu_addr(18:0) look-up address signals are sampled by the rising edge of lu_clk. output cmos 2.5 v lu_data(35:0) look-up data. when used as sram inputs, the rising edge of lu_clk samples these sig- nals. input/output cmos 2.5 v lu_r_wrt look-up read/write control signal is sampled by the rising edge of lu_clk. 0write 1read output cmos 2.5 v table 2: ibm 28.4 gbps packet routing switch interface pins (continued) signal (clock domain) description type IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 34 of 444 np3_dl_sec02_phys.fm.01 09/25/00 table 5: z1 zbt sram interface pins signal description type sch_clk sram clock input. 7.5 ns period (133 mhz). output cmos 2.5 v sch_addr(18:0) sram address signals are sampled by the rising edge of lu_clk. output cmos 2.5 v sch_data(17:0) databus. when used as an sram input, the rising edge of sch_clk samples these signals. input/output cmos 2.5 v sch_r_wrt read/write control signal is sampled by the rising edge of sch_clk. 0write 1read output cmos 2.5 v IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 35 of 444 figure 5: zbt sram timing diagram tcy tdd tds tdh tdckoff tdckon xx_clk xx_addr / xx_r_wrt out xx_data in / out xx_data 30 pf ts +vdd/2 tda/tdwe 50 ? notes: out 1) xx = lu or sch 2) data unstable IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 36 of 444 np3_dl_sec02_phys.fm.01 09/25/00 table 6: zbt sram timing diagram legend symbol symbol description minimum delay (ns) maximum delay (ns) tcy zbt cycle time 7.5 tda address output delay 1 2.28 4.25 tdwe read/write output delay 1 2.92 5.22 tdd data output delay 1 1.75 4.98 tdckon data output turn on 2 3.28 tdckoff data output turn off 5.65 tds input data setup time 2.44 tdh input data hold time 0 1. to determine delay from np4gs3 internal clock, add 9.14 ns to minimum delay and 8.38 ns to maximum delay. 2. to determine delay from np4gs3 internal clock, add 3.33 ns to minimum delay. 3. blank space indicates no limit. 4. all delays are measured with 1 ns slew time measured from 10-90% of input voltage. table 7: d3, d2, and d1 memory pins signal description type shared signals db_clk the positive pin of an output differential pair. 133 mhz. common to the d3, d2, and d1 memory devices. output sstl2 2.5 v db_clk the negative pin of an output differential pair. 133 mhz. common to the d3, d2, and d1 memory devices. output sstl2 2.5 v db_ras common row address strobe (common to d3, d2, and d1 output sstl2 2.5 v db_cas common column address strobe (common to d3, d2, and d1 output sstl2 2.5 v db_ba(1:0) common bank address (common to d3, d2, and d1 output sstl2 2.5 v d3 signals d3_addr(12:0) d3 address output cmos 2.5 v d3_dqs(1:0) d3 data strobes input/output sstl2 2.5 v d3_data(15:0) d3 data bus input/output sstl2 2.5 v d3_we d3 write enable output cmos 2.5 v IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 37 of 444 d3_cs d3 chip select output cmos 2.5 v d2 signals d2_addr(12:0) d2 address output cmos 2.5 v d2_dqs(1:0) d2 data strobes input/output sstl2 2.5 v d2_data(15:0) d2 data bus input/output sstl2 2.5 v d2_we d2 write enable output cmos 2.5 v d2_cs d2 chip select output cmos 2.5 v d1 signals d1_addr(12:0) d1 address output cmos 2.5 v d1_dqs(1:0) d1 data strobes input/output sstl2 2.5 v d1_data(15:0) d1 data bus input/output sstl2 2.5 v d1_we d1 write enable output cmos 2.5 v d1_cs d1 chip select output cmos 2.5 v table 8: d0 memory pins signal description type d0_0 and d0_1 shared signals de_clk the positive pin of an output differential pair. 133 mhz. common to the d0_0/1 memory devices. output sstl2 2.5 v de_clk the negative pin of an output differential pair. 133 mhz. common to the d0_0/1 devices. output sstl2 2.5 v de_ras common row address strobe output cmos 2.5 v table 7: d3, d2, and d1 memory pins (continued) signal description type IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 38 of 444 np3_dl_sec02_phys.fm.01 09/25/00 de_cas common column address strobe output cmos 2.5 v de_ba(1:0) common bank address output cmos 2.5 v d0_addr(12:0) d0 address output cmos 2.5 v d0_dqs(3:0) d0 data strobes input/output sstl2 2.5 v d0_data(31:0) d0 data bus input/output sstl2 2.5 v d0_we d0 write enable output cmos 2.5 v d0_cs d0 chip select output cmos 2.5 v table 9: d4_0 / d4_1 memory pins signal description type dd_clk the positive pin of an output differential pair. 133 mhz. common to the d4_0/1 memory devices. output sstl2 2.5 v dd_clk the negative pin of an output differential pair. 133 mhz. common to the d4_0/1 memory devices. output sstl2 2.5 v dd_ras common row address strobe output cmos 2.5 v dd_cas common column address strobe output cmos 2.5 v dd_ba(1:0) common bank address output cmos 2.5 v d4_addr(12:0) d4 address output cmos 2.5 v d4_dqs(3:0) d4 data strobes input/output sstl2 2.5 v d4_data(31:0) d4 data bus input/output sstl2 2.5 v table 8: d0 memory pins signal description type IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 39 of 444 d4_we d4 write enable output cmos 2.5 v d4_cs d4 chip select output cmos 2.5 v table 10: d6_5 / d6_4 / d6_3 / d6_2 / d6_1 / d6_0 memory pins signal description type da_clk the positive pin of an output differential pair. 133 mhz. common to the d6 memory chips. output sstl2 2.5 v da_clk the negative pin of an output differential pair. 133 mhz. common to the d6 memory devices. output sstl2 2.5 v da_ras common row address strobe (common to d6) output sstl2 2.5 v da_cas commoncolumnaddressstrobe(commontod6) output sstl2 2.5 v da_ba(1:0) common bank address (common to d6) output sstl2 2.5 v d6_we commonwriteenable(commontod6) output sstl2 2.5 v d6_addr(12:0) d6 address output sstl2 2.5 v d6_cs d6 chip select output sstl2 2.5 v d6_dqs(3:0) d6 data strobes input/output sstl2 2.5 v d6_data(15:0) d6 data bus input/output sstl2 2.5 v d6_byteen(1:0) d6 byte enables byte masking write to d6. input/output sstl2 2.5 v d6_parity(1:0) d6 parity signals, one per byte. must go to separate chips to allow for byte write capability. input/output sstl2 2.5 v d6_dqs_par(1:0) d6 data strobe for the parity signals input/output sstl2 2.5 v table 9: d4_0 / d4_1 memory pins signal description type IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 40 of 444 np3_dl_sec02_phys.fm.01 09/25/00 table 11: ds1 and ds0 pins signal description type shared signals dc_clk the positive pin of an output differential pair. 133 mhz. common to the ds1 and ds0 memory devices. output sstl2 2.5 v dc_clk the negative pin of an output differential pair. 133 mhz. common to the ds1 and ds0 memory devices. output sstl2 2.5 v dc_ras common row address strobe (common to ds1 and ds0) output sstl2 2.5 v dc_cas commoncolumnaddressstrobe(commontods1andds0) output sstl2 2.5 v dc_ba(1:0) common bank address (common to ds1 and ds0) output sstl2 2.5 v ds1 signals ds1_addr(12:0) ds1 address output cmos 2.5 v ds1_dqs(3:0) ds1 data strobes input/output sstl2 2.5 v ds1_data(31:0) ds1 data bus input/output sstl2 2.5 v ds1_we ds1 write enable output cmos 2.5 v ds1_cs ds1 chip select output cmos 2.5 v ds0 signals ds0_addr(12:0) ds0 address output cmos 2.5 v ds0_dqs(3:0) ds0 data strobes input/output sstl2 2.5 v ds0_data(31:0) ds0 data bus input/output sstl2 2.5 v ds0_we ds0 write enable output cmos 2.5 v ds0_cs ds0 chip select output cmos 2.5 v IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 41 of 444 figure 6: ddr timing diagram figure 7: ddr read input timing diagram tcy tzon tzoff dy_ clk /dy _cl k dx_dq/dx_dqs z notes: 1) the shaded area stands for data or strobe in transition. 2) dx: d0, d1, d2, d3, d4, d6, ds0, ds1 3) dy: da, db, dc, dd, de indicates unstable data 4) dx_dqs dx_dq tdqs tdqh tdqh tdqs notes: 1) this diagram shows data coming into the np4gs3. 2) dx: d0, d1, d2, d3, d4, d6, ds0, ds1 3) dy: da, db, dc, dd, de indicates unstable data 4) IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 42 of 444 np3_dl_sec02_phys.fm.01 09/25/00 figure 8: ddr write output timing diagram tcy tddq (max) tda tdw tdcs tdba tdras tdcas dy_cl k /dy_ clk dx_dqs dx_dq dx_addr dx_we dx_cs dx_ba dx_ras dx_cas tddqs tddq (min) notes: 1) this diagram shows data leaving the np4gs3. 2) dx: d0, d1, d2, d3, d4, d6, ds0, ds1 3) dy: da, db, dc, dd, de indicates unstable data 4) IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 43 of 444 table 12: ddr timing diagrams legend symbol symbol description minimum delay (ns) maximum delay (ns) tcy ddr clock cycle time 7.5 tddqs dqs output strobe to clock output delay -0.9 1.29 tddq dq data to dqs skew -2.2 2.45 tda address output delay 1 0.79 4.85 tdw write enable output delay 1 1.00 4.88 tdcs chip select output delay 1 0.93 5.62 tdba bank address output delay 1 0.88 4.78 tdras ras output delay 1 0.79 5.08 tdcas cas output delay 1 0.62 4.80 tdqs strobe to data setup time -1.8 tdqh strobe to data hold time 2.42 tzon dq/dqs turn on time from clk/clk tbd tzoff dq/dqs turn off time from clk/clk tbd 1. to determine delay from np4gs3 internal clock, add 7.28 ns to minimum delay and 11.34 ns to maximum delay. 2. blank space indicates no limit. 3. all delays are measured with 1 ns slew time measured from 10-90% of input voltage. table 13: pmm interface pins signal description type dmu_a(30:0) define the first of the four pmm interfaces and can be configured for tbi, smii, gmii, or pos. see table 14: pmm interface pin multiplexing on page 44 for pin directions and defini- tions. 5.0 v-tolerant 3.3 v lvttl 3.3 v dmu_b(30:0) define the second of the four pmm interfaces and can be configured for tbi, smii, gmii, or pos. see table 14: pmm interface pin multiplexing on page 44 for pin directions and defini- tions. 5.0 v-tolerant 3.3 v lvttl 3.3 v dmu_c(30:0) define the third of the four pmm interfaces and can be configured for tbi, smii, gmii, or pos. see table 14: pmm interface pin multiplexing on page 44 for pin directions and defini- tions. 5.0 v-tolerant 3.3 v lvttl 3.3 v dmu_d(30:0) define the fourth of the four pmm interfaces and can be configured for tbi, smii, gmii, debug, or pos. see table 14: pmm interface pin multiplexing on page 44 for pin directions and definitions. 5.0 v-tolerant 3.3 v lvttl 3.3 v rx_lbyte(1:0) receive last byte position (valid for 32-bit pos only) provides the position of the last byte within the final word of the packet transfer. this signal is valid only when rx_eof is high. input 5.0 v-tolerant 3.3 v lvttl 3.3 v IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 44 of 444 np3_dl_sec02_phys.fm.01 09/25/00 table 14: pmm interface pin multiplexing pin(s) pin mode interface type dmu_a, dmu_b, dmu_c dmu_d gmii tbi smii debug (dmu_d only) 8-bit pos 30 o o rxaddr(1) o 29 o o rxaddr(0) o 28 o o txaddr(1) o 27 o o txaddr(0) o 26 o o txsof o 25 o o tx_valid_byte o txeof o (24:17) o i/o tx_data(7:0) o tx_data(0:7) o tx_data(9:2) o debug(23:16) i/o txdata(7:0) o (16:9) i i/o rx_data(7:0) i rx_data(0:7) i rx_data(9:2) i debug(15:8) i/o rxdata(7:0) i 8oo tx_clk 8ns tx_clk 8ns ??? 7 o i/o tx_en o tx_data(8) o tx_data(1) o debug(7) i/o txen o 6 i/o i/o tx_er o tx_data(9) o tx_data(0) o debug(6) i/o txpfa i 5 i i/o rx_valid_byte i rx_data(8) i rx_data(1) i debug(5) i/o rxpfa i 4 i i/o tx_byte_credit i rx_data(9) i rx_data(0) i debug(4) i/o rxval i 3 i i/o rx_clk i 8ns rx_clk1 i 16 ns clk i 8ns debug(3) o clk i 10 ns 2 i/o i/o rx_dv i rx_clk0 i 16 ns sync o debug(2) i/o rxeof i 1 i/o i/o rx_er i sig_det i sync2 o debug(1) i/o rxerr i 0 i/o i/o cpdetect (0 = cpf) - input cpdetect (0 = cpf) - input activity - output cpdetect (0 = cpf) - input debug(0) i/o rxenb o table 15: parallel data bit to 8b/10b position mapping (tbi interface) parallel data bit 0123456789 8b/10b bit position abcde f gh i j IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 45 of 444 table 16: pmm interface pins pos32 mode pin(s) dmu_a dmu_b dmu_c dmu_d 28 txpadl(1) o 27 txpadl(0) o 26 txsof o 25 txeof o (24:17) txdata(31:24) o txdata(23:16) o txdata(15:8) o txdata(7:0) o (16:9) rxdata(31:24) i rxdata(23:16) i rxdata(15:8) i rxdata(7:0) i 8 ? 7 txen o 6 txpfa i 5 rxpfa i 4 rxval i 3 clk i 10 ns clk i 10 ns clk i 10 ns clk i 10 ns 2 rxeof i 1 rxerr i 0 rxenb o single pins (not associated with a dmu) pin rx_lbyte 1 rx_lbyte(1) i 0 rx_lbyte(0) i IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 46 of 444 np3_dl_sec02_phys.fm.01 09/25/00 figure 9: np4gs3 dmu bus clock connections gmii phy dmu_*(8) dmu_*(3) clock125 tx_clk rx_clk dmu_*(8) dmu_*(3) (1 port) note: trace lengths to all inputs will be matchedonthecard. nc ibm powernp tbi phy (10 ports) dmu_*(8) dmu_*(3) dmu_*(2) tx_clk rx_clk1 rx_clk0 clock125 53.3 mhz oscillator pll 266 mhz 62.5 mhz 62.5 mhz clock_core 125 mhz oscillator x5 notes: each figure above illustrates a single dmu bus and applies to any of the four dmu busses. the ?dmu_*? labels represent any of the four dmu busses (dmu_a, dmu_b, dmu_c, or dmu_d). smii phy (6 ports) smii phy (4 ports) gmii interface smii interface tbi interface 125 mhz oscillator 125 mhz oscillator asynchronous interface ibm powernp ibm powernp IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 47 of 444 figure 10: np4gs3 dmu bus clock connections (pos overview) dmu_a(8) dmu_a(3) note: trace lengths to all inputs will be matched on the card. 100 mhz oscillator rxclk txclk nc at m fra m e r dmu_*(8) dmu_*(3) note: trace lengths to all inputs will be matchedonthecard. 100 mhz oscillator rxclk txclk nc (except oc48) (oc48) dmu_b(8) dmu_b(3) nc dmu_c(8) dmu_c(3) nc dmu_d(8) dmu_d(3) nc single dmu bus (applies to dmu a-d) at m fr a m e r ibm powernp ibm powernp IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 48 of 444 np3_dl_sec02_phys.fm.01 09/25/00 table 17: pmm interface signals: gmii mode (refer to notes) signal description type tx_data(7:0) transmit data. data bus to the phy, synchronous to tx_clk. output 5.0 v-tolerant 3.3 v lvttl 3.3 v rx_data(7:0) received data. data bus from the phy, synchronous to rx_clk. input 5.0 v-tolerant 3.3 v lvttl 3.3 v tx_en transmit data enabled to the phy, synchronous to tx_clk. 0 end of frame transmission 1 active frame transmission output 5.0 v-tolerant 3.3 v lvttl 3.3 v tx_er transmit error, synchronous to the tx_clk. 0 no error detected 1 informs the phy that mac detected an error output 5.0 v-tolerant 3.3 v lvttl 3.3 v rx_valid_byte receive valid data, synchronous to the rx_clk. 0 data invalid 1 byteofdata(fromthephy)onrx_dataisvalid. for a standard gmii connection, this signal can be tied to ?1? on the card. input 5.0 v-tolerant 3.3 v lvttl 3.3 v tx_byte_credit transmit next data value, asynchronous. 0 do not send next data byte 1 asserted. phy indicates that the next tx_data value may be sent. for a standard gmii connection, this signal can be tied to ?1? on the card. input 5.0 v-tolerant 3.3 v lvttl 3.3 v tx_valid_byte transmit valid data, synchronous to tx_clock 0 data invalid 1 byte of data (from the network processor) on tx_data is valid. output 5.0 v-tolerant 3.3 v lvttl 3.3 v rx_clk 125 mhz receive medium clock generated by the phy. input 5.0 v-tolerant 3.3 v lvttl 3.3 v rx_dv receive data valid (from the phy), synchronous to rx_clk. 0 end of frame transmission. 1 active frame transmission. input 5.0 v-tolerant 3.3 v lvttl 3.3 v rx_er receive error, synchronous to rx_clk. 0 no error detected 1 informs the mac that phy detected an error input 5.0 v-tolerant 3.3 v lvttl 3.3 v tx_clk 125 mhz transmit clock to the phy. during operation, the network processor drives this sig- nal to indicate that a transmit is in progress for this interface. output 5.0 v-tolerant 3.3 v lvttl 3.3 v cpdetect the control point card drives this signal active low to indicate its presence. when a non- control point card is plugged in, or this device pin is not connected, this signal should be pulled to a ?1? on the card. input 5.0 v-tolerant 3.3 v lvttl 3.3 v 1. the np4gs3 supports gmii in full-duplex mode only. 2. see table 14: pmm interface pin multiplexing on page 44 for pin directions (i/o) and definitions. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 49 of 444 figure 11: gmii timing diagram tcy tden/tder/tdvb tx_clk tx_data 30 pf ts +vdd/2 tdd 50 ? tx_en/tx_er/t x_valid_byte rx_clk rx_data trdh trds rx_valid byte/ rx_er/ rx_dv/ tx_byte_credit trvh/treh/trdvh/tbch trvs/tres/trdvs/tbcs IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 50 of 444 np3_dl_sec02_phys.fm.01 09/25/00 table 18: gmii timing diagram legend symbol symbol description minimum delay (ns) maximum delay (ns) tcy gmii cycle time 8 tdd tx_data output delay 1 3.67 4.71 tder tx_er output delay 3 3.82 4.65 tdvb tx_valid_byte output delay 2 3.77 4.77 tden tx_en output delay 3.78 4.67 trds rx_data setup time 1.78 trdh rx_data hold time 0 trvs rx_valid_byte setup time 1.78 trvh rx_valid_byte hold time 0 tres rx_er setup time 1.86 treh rx_er hold time 0 trdvs rx_dv setup time 1.56 trdvh rx_dv hold time 0 tbcs tx_byte_credit setup time 1.71 tbch tx_byte_credit hold time 0 1. to determine delay from np4gs3 internal clock, add -0.58 ns to minimum delay and 1.26 ns to maximum delay. 2. to determine delay from np4gs3 internal clock, add -0.73 ns to minimum delay and 1.35 ns to maximum delay. 3. to determine delay from np4gs3 internal clock, add 1.49 ns to minimum delay and 1.49 ns to maximum delay. 4. blank space indicates no limit. 5. all delays are measured with 1 ns slew time measured from 10-90% of input voltage. table 19: pmm interface pins: tbi mode signal description type tx_data(9:0) transmit data. data bus to the phy, synchronous to tx_clk. output 5.0 v-tolerant 3.3 v lvttl 3.3 v rx_data(9:0) receive data. data bus from the phy, synchronous to rx_clk1 and rx_clk0. (data switches at double the frequency of rx_clk1 or rx_clk0.) input 5.0 v-tolerant 3.3 v lvttl 3.3 v rx_clk1 receiveclock,62.5mhz.rx_dataisvalidontherisingedgeofthisclock. input 5.0 v-tolerant 3.3 v lvttl 3.3 v rx_clk0 receive clock, 62.5 mhz. this signal is 180 degrees out of phase with rx_clk1. rx_data is valid on the rising edge of this clock. input 5.0 v-tolerant 3.3 v lvttl 3.3 v note: see table 14: pmm interface pin multiplexing on page 44 table for pin directions (i/o) and definitions. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 51 of 444 sig_det signal detect. signal asserted by the phy to indicate that the physical media is valid. input 5.0 v-tolerant 3.3 v lvttl 3.3 v cpdetect the control point card drives this signal active low to indicate its presence. when a non- control point card is plugged in, or this device pin is not connected, this signal should be pulledtoa?1?onthecard. during operation, this signal is driven by the network processor to indicate the status of the interface. 0 tbi interface is not in the data pass state (link down) 1 tbi interface is in the data pass state (occurs when auto-negotiation is complete, or when idles are detected (if an is disabled)) pulse tbi interface is in a data pass state and is either receiving or transmitting. the line pulses once per frame transmitted or received at a maximum rate of 8hz. input/output 5.0 v-tolerant 3.3 v lvttl 3.3 v tx_clk 125 mhz clock transmit clock to the phy. during operation, the network processor drives this signal to indicate that a transmit or receive is in progress for this interface. output 5.0 v-tolerant 3.3 v lvttl 3.3 v table 19: pmm interface pins: tbi mode signal description type note: see table 14: pmm interface pin multiplexing on page 44 table for pin directions (i/o) and definitions. IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 52 of 444 np3_dl_sec02_phys.fm.01 09/25/00 figure 12: tbi timing diagram tcy tx_clk tx_data_(9:0) 30 pf ts +vdd/2 tdd1/tdd2 50 w rx_clk0/rx_clk1 rx_data_(9:0) trt0h/trt08h/trt1h/trt18h/trs0h/trs1h trt0s/trt08s/trt1s/trt18s trs0s/trs1s IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 53 of 444 table 20: tbi timing diagram legend symbol symbol description minimum delay (ns) maximum delay (ns) tcy tbi cycle time 16 tdd1 tx_data_(7:0) output delay 1 3.67 4.71 tdd2 tx_data_(9:8) output delay 1 3.67 4.71 trt0s rx_data_(7:0) set up time clk0 0.66 trt0h rx_data_(7:0) hold time clk0 0.72 trt08s rx_data_(9:8) set up time clk0 0.66 trt08h rx_data_(9:8) hold up time clk0 0.72 trs0s sig_det setup time clk0 0.66 trs0h sig_det hold time clk0 0.72 trt1s rx_data_(7:0) set up time clk1 0.80 trt1h rx_data_(7:0) hold time clk1 0.12 trt18s rx_data_(9:8) set up time clk1 0.80 trt18h rx_data_(9:8) hold up time clk1 0.12 trs1s sig_det setup time clk1 0.80 trs1h sig_det hold time clk1 0.12 1. to determine delay from np4gs3 internal clock, add -0.58 ns to minimum delay and 1.26 ns to maximum delay. 2. blank space indicates no limit. 3. all delays are measured with 1 ns slew time measured from 10-90% of input voltage. table 21: pmm interface pins: smii mode signal description type tx_data(9:0) transmit data. data bus to the phy - contains ten streams of serial transmit data. each serial stream is connected to a unique port. synchronous to the common clock (clk). output 5.0 v-tolerant 3.3 v lvttl 3.3 v rx_data(9:0) received data. data bus from the phy - contains ten streams of serial receive data. each serial stream is connected to a unique port. synchronous to the common clock (clk). input 5.0 v-tolerant 3.3 v lvttl 3.3 v sync asserted for one tx_clk cycle once every ten tx_clk cycles. assertion indicates the begin- ning of a 10-bit segment on both tx_data and rx_data. output 5.0 v-tolerant 3.3 v lvttl 3.3 v sync2 logically identical to sync and provided for fanout purposes. output 5.0 v-tolerant 3.3 v lvttl 3.3 v cpdetect the control point card drives this signal active low to indicate its presence. when a non- control point card is plugged in, or this device pin is not connected, this signal should be pulledtoa?1?onthecard. input 5.0 v-tolerant 3.3 v lvttl 3.3 v note: the transmit and receive clocks the np4gs3 uses for this mode are derived from the clock 125 input. see figure 9 on page 46. see table 14: pmm interface pin multiplexing on page 44 table for pin directions (i/o) and definitions. IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 54 of 444 np3_dl_sec02_phys.fm.01 09/25/00 figure 13: smii timing diagram tcy tdd1/tdd2 tds/tds2 tx_clk tx_data_(9:0) 30 pf ts +vdd/2 50 ? sync/sync2 rx_clk rx_data_(9:0) trh1/trh2 trs1/trs2 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 55 of 444 table 22: smii timing diagram legend symbol symbol description minimum delay (ns) maximum delay (ns) tcy smii cycle time 8 tdd1 tx_data_(9:2) output delay 1 2.07 4.29 tdd2 tx_data_(1:0) output delay 1 2.13 4.31 tds sync output delay 1 2.12 4.23 tds2 sync2 output delay 1 2.10 4.48 trs1 rx_data_(9:2) set up time 0.37 trh1 rx_data_(9:2) hold time 1.22 trs2 rx_data_(1:0) set up time 0.19 trh2 rx_data_(1:0) hold time 1.19 1. to determine delay from np4gs3 internal clock, add 0 ns to minimum delay and 0 ns to maximum delay. 2. blank space indicates no limit. 3. all delays are measured with 1 ns slew time measured from 10-90% of input voltage. table 23: pos signals signal description type rxaddr(1:0) receive address bus selects a particular port in the framer for a data transfer. valid on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl 3.3 v rxdata (7:0) 8-bit mode (31:0) 32-bit mode receive pos data bus carries the frame word that is read from the framer?s fifo. rxdata transports the frame data in an 8-bit format. rxdata[7:0] and [31:0] are updated on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl 3.3 v clk pos clock provides timing for the pos framer interface. clk must cycle at a 100 mhz or lower instantaneous rate. 5.0 v-tolerant 3.3 v lvttl 3.3 v rxenb receive read enable controls read access from the framer?s receive interface. the framer?s addressed fifo is selected on the falling edge of rxenb. generated on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl 3.3 v rxeof receiveend-of-framemarksthelastwordofaframeinrxdata.updatedontherising edge of clk. 5.0 v-tolerant 3.3 v lvttl 3.3 v rxerr receive packet error indicates that the received packet contains an error and must be dis- carded. only asserted on the last word of a packet (when rxeof is also asserted). updated on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl 3.3 v rxval receive valid data output indicates the receive signals rxdata, rxsof, rxeof, rxerr, and rxpadl are valid from the framer. updated on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl 3.3 v rxpadl(1:0) receive padding length indicates the number of padding bytes included in the last word of the packet transferred in rxdata. only used when the network processor is configured in 32-bit pos mode. updated on the rising edge of clk. rxpadl(1:0) (32-bit mode) 00 packet ends on rxdata(7:0) (rxdata = dddd) 01 packet ends on rxdata(15:8) (rxdata = dddp) 10 packet ends on rxdata(23:16) (rxdata = ddpp) 11 packet ends on rxdata(31:24) (rxdata = dppp) 5.0 v-tolerant 3.3 v lvttl 3.3 v IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 56 of 444 np3_dl_sec02_phys.fm.01 09/25/00 rxpfa receive polled frame-available input indicates that the framers polled receive fifo con- tains data. updated on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl 3.3 v txdata (7:0) 8-bit mode (31:0) 32-bit mode transmit utopia data bus carries the frame word that is written to the framer?s transmit fifo. considered valid and written to a framer?s transmit fifo only when the transmit interface is selected by using txenb. sampled on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl 3.3 v txen transmit write enable controls write access to the transmit interface. a framer port is selected on the falling edge of txenb. sampled on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl 3.3 v txaddr(1:0) transmit address bus uses txenb to select a particular fifo within the framer for a data transfer. sampled on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl 3.3 v txsof transmit start-of-frame marks the first word of a frame in txdata. sampled on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl 3.3 v txeof transmit end-of-frame marks the last word of a frame in txdata. sampled on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl 3.3 v txpadl (1:0) transmit padding length indicates the number of padding bytes included in the last word of the packet transferred in txdata. sampled on the rising edge of clk. when configured in 32-bit mode the last word may contain zero, one, two or three padding bytes and only txpadl[1:0] is used. in 8-bit mode txpadl[1:0] is not used. txpadl[1:0] (32-bit mode) 00 packet ends on txdata[7:0] (txdata = dddd) 01 packet ends on txdata[15:8] (txdata = dddp) 10 packet ends on txdata[23:16] (txdata = ddpp) 11 packet ends on txdata[31:24] (txdata = dppp) 5.0 v-tolerant 3.3 v lvttl 3.3 v txpfa transmit polled frame-available output - indicates that the polled framer?s transmit fifo hasfreeavailablespaceandthenp4gs3canwritedataintotheframer?sfifo.updated on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl 3.3 v table 23: pos signals (continued) signal description type IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 57 of 444 figure 14: pos timing diagram tcy tx_clk tx_data_(31:0) 30 pf ts +vdd/2 tdd 50 ? txaddr/rxaddr/txsof/txeof/txen/txpadl rx_clk rx_data_(31:0) trxh trxs trpfs/ttpfs/trers/trvs/treofs tda/tda1/tdsof/tdeof/tden/tdpadl/tdren trpfh/ttpfh/trerh/trvh/treofh rxpfa/rxerr/rxval/rxeof/txpfa IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 58 of 444 np3_dl_sec02_phys.fm.01 09/25/00 table 24: pos timing diagram legend symbol symbol description minimum delay (ns) maximum delay (ns) tcy pos cycle time 10 tdd tx_data_(31:0) output delay 1 2.07 4.29 tda tx_addr_(1:0) output delay 1 2.12 4.34 tda1 rx_addr_(1:0) output delay 1 1.87 3.9 tdsof txsof output delay 1 2.13 4.22 tdeof txeof output delay 1 2.15 4.40 tden txen output delay 1 1.79 4.31 tdpadl txpadl_(1:0) output delay 1 2.12 4.34 tdren rxenb output delay 1 1.79 3.85 trxs rx_data_(31:0) set up time 1.3 trxh rx_data_(31:0) hold time 0.25 trvs rxval set up time 1.09 trvh rxval hold time 0.35 trers rxerr set up time 1.2 trerh rxerr hold time 0 treofs rxeof set up time 1.00 treofh rxeof hold time 0 trpfs rxpfa setup time 1.19 trpfh rxpfa hold time 0 ttpfs txpfa setup time 1.09 ttpfh txpfa hold time 0 1. to determine delay from np4gs3 internal clock, add 0 ns to minimum delay and 0 ns to maximum delay. 2. blank space indicates no limit. 3. all delays are measured with 1 ns slew time measured from 10-90% of input voltage. 4. tx_clk is not an external pin. it is an internal clock derived from the 100 mhz clock IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 59 of 444 table 25: pci interface pins signal description type pci_clk pci clock signal (see pci_speed field below) input pci 3.3 v pci_ad(31:0) pci multiplexed address and data signals input/output pci 3.3 v pci_cbe (3:0) pci command/byte enable signals input/output pci 3.3 v pci_frame pci frame signal input/output pci 3.3 v pci_irdy pci initiator (master) ready signal input/output pci 3.3 v pci_trdy pci target (slave) ready signal input/output pci 3.3 v pci_devsel pci device select signal input/output pci 3.3 v pci_stop pci stop signal input/output pci 3.3 v pci _ request pci bus request signal output pci 3.3 v pci_grant pci bus grant signal input pci 3.3 v pci_idsel pci initialization device select signal input pci 3.3 v pci_perr pci parity error signal input/output pci 3.3 v pci_serr pci system error signal input/output pci 3.3 v pci_inta pci level sensitive interrupt output pci 3.3 v pci_par pci parity signal. covers all the data/address and the four command/be signals. input/output pci 3.3 v pci_speed pci speed. frequency of attached pci bus. 066mhz 133mhz input 3.3 v-tolerant 2.5 v 2.5 v pci_bus_nm_int external non-maskable interrupt - the active polarity of the interrupt is programmable by the powerpc. input pci 3.3 v note: pci i/o are all configured for multi-point operation. IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 60 of 444 np3_dl_sec02_phys.fm.01 09/25/00 pci_bus_m_int external maskable interrupt - the active polarity of the interrupt is programmable by the powerpc. input pci 3.3 v figure 15: pci timing diagram table 25: pci interface pins (continued) signal description type note: pci i/o are all configured for multi-point operation. tcy pci_clk 30 pf ts tval 50 ? outputs inputs t_off t_on t_h t_su vdd/2 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 61 of 444 table 26: pci timing diagram legend symbol symbol description minimum delay (ns) maximum delay (ns) tcy pci cycle time 15 tval worst case output delay 2.79 5.7 t_on pci bus turn on output delay 2 t_off pci bus turn off output delay 14 t_su input set up time 2.12 t_h input hold time 0 1. blank space indicates no limit. 2. all delays are measured with 1 ns slew time measured from 10-90% of input voltage. table 27: management bus pins signal description type mg_data serial data. supports address/control/data protocol. input/output 3.3 v-tolerant 2.5 v 2.5 v mg_clk 33.33 mhz clock output 3.3 v-tolerant 2.5 v 2.5 v mg_nintr rising-edge sensitive interrupt input input 3.3 v-tolerant 2.5 v 2.5 v IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 62 of 444 np3_dl_sec02_phys.fm.01 09/25/00 figure 16: management bus timing diagram table 28: management bus timing diagram legend symbol symbol description minimum delay (ns) maximum delay (ns) tcy spm cycle time 30 tdd worst case data output delay 1 0.5 0.82 tds data setup time 1.6 tdh data hold time 0 1. to determine delay from np4gs3 internal clock, add 6.59 ns to minimum delay and 7.09 ns to maximum delay. 2. mg_nintr is an asynchronous input and is not timed. 3. blank space indicates no limit. 4. all delays are measured with 1 ns slew time measured from 10-90% of input voltage. tcy mg_clk 30 pf ts 50 ? mg_data outputs vdd/2 tdd tds tdh IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 63 of 444 table 29: miscellaneous pins signal description type switch_clock_a the positive pin of an input differential pair. 50.6875 to 62.5 mhz. generates packet routing switch clock domains. required to have cycle-to-cycle jitter 150ps. duty cycle tolerance must be 10%. input lvds 1.5 v switch_clock_a the negative pin of an input differential pair. 50.6875 to 62.5 mhz. input lvds 1.5 v switch_clock_b the positive pin of an input differential pair. 50.6875 to 62.5 mhz. generates packet routing switch clock domains. required to have cycle-to-cycle jitter 150ps. duty cycle tolerance must be 10%. input lvds 1.5 v switch_clock_b the negative pin of an input differential pair. 50.6875 to 62.5 mhz. input lvds 1.5 v switch_bna selects which of the two dasl ports (a or b) carries network traffic. 0 port a carries the network traffic 1 port b carries the network traffic input 5.0 v-tolerant 3.3 v lvttl 3.3 v core_clock 53.33 mhz oscillator - generates 266 /133 clock domains. required to have cycle-to-cycle jitter 150ps. duty cycle tolerance must be 5%. input 5.0 v-tolerant 3.3 v lvttl 3.3 v clock125 125 mhz oscillator. required to have cycle-to-cycle jitter 60ps. duty cycle tolerance must be 5%. input 5.0 v-tolerant 3.3 v lvttl 3.3 v blade_reset reset np4gs3 - signal must be driven active low for a minimum of 1 s to ensure a proper reset of the np4gs3. all input clocks (switch_clock_a, switch_clock_a , switch_clock_b, switch_clock_b , core_clock, clock125, and pci_clk) must be running prior to the activa- tion of this signal. input 5.0 v-tolerant 3.3 v lvttl 3.3 v operational np4gs3 operational - pin is driven active low when both the np4gs3 ingress and egress macros have completed their initialization. it remains active until a subsequent blade_reset is issued. output 5.0 v-tolerant 3.3 v lvttl 3.3 v testmode(1:0) 00 functional mode, including concurrent use of the jtag interface for riscwatch or cabwatch operations. 01 debug mode - debug mode must be indicated by the testmode i/o for the debug bus (dmu_d) output to be gated from the probe. 10 jtag test mode 11 lssd test mode input cmos 1.8 v jtag_trst jtag test reset. for normal functional operation, this pin must be connected to the same card source that is connected to the blade_reset input. when the jtag interface is used for jtag test functions, this pin is controlled by the jtag interface logic on the card. input 5.0 v-tolerant 3.3 v lvttl 3.3 v jtag_tms jtag test mode select. for normal functional operation, this pin should be tied either low or high. input 5.0 v-tolerant 3.3 v lvttl 3.3 v jtag_tdo jtag test data out. for normal functional operation, this pin should be tied either low or high. output 5.0 v-tolerant 3.3 v lvttl 3.3 v IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 64 of 444 np3_dl_sec02_phys.fm.01 09/25/00 jtag_tdi jtag test data in. for normal functional operation, this pin should be tied either low or high. input 5.0 v-tolerant 3.3 v lvttl 3.3 v jtag_tck jtag test clock. for normal functional operation, this pin should be tied either low or high. input 5.0 v-tolerant 3.3 v lvttl 3.3 v plla_v dd pllb_v dd pllc_v dd these pins serve as the +1.8 volt supply for a critical noise sensitive portion of the phased locked loop (pll) circuits. one pin serves as the analog v dd for each pll circuit. to pre- vent noise on these pins from introducing phase jitter in the pll outputs, place filters at the board level to isolate these pins from the noisy digital v dd pins. place separate filters on each analog v dd pin to prevent noise from one pll being introduced into another. see section 2.1.1 pll filter circuit on page 65 for filter circuit details. input pll_v dd 1.8 v plla_gnd pllb_gnd pllc_gnd these pins serve as the ground connection for the critical noise portion of the phase lock loop (pll). one pin serves as the analog gnd for each pll circuit. each should be con- nected to the digital ground plane at the v dda node of the pll filter capacitor shown in fig- ure 17: pll filter circuit diagram on page 66. input pll_gnd 0.0 v thermal_in input pad of the thermal monitor (resistor). see 2.1.2 thermal i/o usage on page 66 for details on thermal monitor usage. thermal thermal_out output pad of the thermal monitor (resistor). thermal vref1(2), vref2(8,7,6) voltage reference for sstl2 i/os for d1, d2, and d3 (approximately four pins per side of the device that contains sstl2 i/o). input vref 1.25 v vref1(1), vref2(5,4,3) voltage reference for sstl2 i/os for d4 and d6 (approximately four pins per side of the device that contains sstl2 i/o). input vref 1.25 v vref1(0), vref2(2,1,0) voltage reference for sstl2 i/os for ds0 and ds1 (approximately four pins per side of the device that contains sstl2 i/o). input vref 1.25 v boot_picocode determines location of network processor picocode load location. 0 load from spm 1 load from external source (typically power pc or pci bus) input 3.3 v-tolerant 2.5 v 2.5 v boot_ppc determines location of power pc code start location. 0 start from d6 1 start from pci input 3.3 v-tolerant 2.5 v 2.5 v spare_tst_rcvr(9:0) unused signals needed for manufacturing test. spare_tst_rcvr (9:5,1) should be tied to 0 on the card. spare_tst_rcvr (4:2,0) should be tied to 1 on the card. input cmos 1.8 v c405_debug_halt this signal, when asserted low, forces the embedded powerpc 405 processor to stop pro- cessing all instructions. for normal functional operation, this signal should be tied inactive high. input 5.0 v-tolerant 3.3 v lvttl 3.3v table 29: miscellaneous pins (continued) signal description type IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 65 of 444 2.1.1 pll filter circuit v dda is the voltage supply pin to the analog circuits in the pll. noise on v dda causes phase jitter at the out- put of the pll. v dda is brought to a package pin to isolate it from the noisy internal digital v dd signal. if little noise is expected at the board level, then v dda can be connected directly to the digital v dd plane. in most cir- cumstances, however, it is prudent to place a filter circuit on the v dda as shown below. note: all wire lengths should be kept as short as possible to minimize coupling from other signals. the impedance of the ferrite bead should be much greater than that of the capacitor at frequencies where noise is expected. many applications have found that a resistor does a better job of reducing jitter than a fer- rite bead does. the resistor should be kept to a value lower than 2 ? . experimentation is the best way to determine the optimal filter design for a specific application. table 30: signals requiring pull-up or pull-down signal name function value signals requiring a dc connection that is the same value for all applications testmode(1:0) pull-down jtag_tdi pull-up jtag_tms pull-up jtag_tck pull-up c405_debug_halt pull-up spare_tst_rcvr (9:5, 1) pull-down spare_tst_rcvr (4:2, 0) pull-up signals requiring a dc connection that varies across different applications multicast_grant_a, multicast_grant_b pull-up if no system device drives this signal res_data pull-down if no other system device drives this signal pci_speed choose up or down based on system pci bus speed mg_nintr pull-down if no system device drives this signal boot_picocode choose up or down based on picocode load location boot_ppc choose up or down based on ppc code load location switch_bna pull-up if no system device drives this signal signals which have an ac connection, but also require pull-up or pull-down operational pull-up dmu_a(0), dmu_b(0), dmu_c(0), dmu_d(0) cpdetect if control point blade then pull-down, otherwise pull-up dmu_a(30:29), dmu_b(30:29), dmu_c(30:29), dmu_d(30:29) dmu in 8-bit pos mode. rxaddr (1:0) pull-down dmu_a(4), dmu_b(4), dmu_c(4), dmu_d(4) dmu in any pos mode. rxval pull-down d3_dqs(1:0), d2_dqs(1:0), d1_dqs(1:0) pull-down d0_dqs(3:0), d4_dqs(3:0), d6_dqs(3:0) pull-down ds0_dqs(3:0), ds1_dqs(3:0) pull-down IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 66 of 444 np3_dl_sec02_phys.fm.01 09/25/00 note: one filter circuit may be used for plla and pllb, and a second filter circuit should be used for pllc. 2.1.2 thermal i/o usage the thermal monitor consists of a resistor connected between pins pada and padb. at 2 5 c this resistance is estimated at 1290 + 350 ohms. the published temperature coefficient of the resistance for this technology is 0.33% per c. to determine the actual temperature coefficient, see measurement calibration on page 66. note: there is an electrostatic discharge (esd) diode at pada and padb. 2.1.2.1 temperature calculation thechiptemperaturecanbecalculatedfrom where: r measured = resistance measured between pada and padb at test temperature. r calibrated = resistance measured between pada and padb (v r /i dc ) at known temperature. t calibrated = known temperature used to measure r calibrated. 2.1.2.2 measurement calibration to use this thermal monitor accurately, it must first be calibrated. to calibrate, measure the voltage drop at figure 17: pll filter circuit diagram figure 18: thermal monitor gnd digital v dd (via at board) v dda (to pll) ferrite bead c=0.1 f thermal pada padb t c (r measured -r calibrated ) t chip = 1 +t calibrated c IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 67 of 444 two different known temperatures at the package while the chip is dissipating little (less than 100 mw) or no power. apply i dc and wait for a fixed time t m ,wheret m = approx. 1 ms. keep t m short to minimize heating effects on the thermal monitor resistance. then measure v r . next, turn off i dc and change the package temperature. reapply i dc ,waitt m again and measure v r . the temperature coefficient is, , where: t = temperature change, c v r = voltage drop, v i dc = applied current, a tc ? vr idc ? t --------------------- - ? c ------ = padb pada v r measure voltage drop v supply =v dd maximum i dc = 200 a maximum thermal IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 68 of 444 np3_dl_sec02_phys.fm.01 09/25/00 figure 19: pins diagram wvutrp nml kj hgfedcb a 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 ad ac ab aa y 20 21 22 23 24 25 corner ae af ag ah aj ak al am an signal = 815 test i/o ground = 137 v dd =72 v dd2 (3.3 v) = 16 1 2 v dd3 (2.5 v) = 16 v dd4 (2.5 v) = 16 3 4 v dd5 (2.5 v) = 16 5 dc test i/o 1 4 1 4 1 4 1 4 1 4 1 1 3 4 1 4 1 4 5 4 1 4 1 1 5 4 1 1 1 4 3 1 5 1 1 4 4 1 1 3 1 4 1 5 4 3 1 3 1 1 5 1 1 5 1 3 1 3 5 1 5 1 1 1 3 1 1 1 1 2 1 2 1 2 1 2 1 2 1 2 5 1 1 2 1 2 1 1 1 2 1 2 3 1 1 2 5 2 1 1 3 1 5 2 1 1 2 3 1 5 2 5 1 2 1 3 1 1 1 1 5 1 5 1 3 3 1 1 1 1 5 1 3 1 3 1 26 27 28 29 30 31 32 33 note: for illustrative purposes only. see the ibm asic viewed through top of package sa-12e databook available from your ibm representative. a01 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 69 of 444 2.2 mechanical specifications figure 20: mechanical diagram notes: 1. refer to table 31 on page 70 for mechanical dimensions. 2. mechanical drawing is not to scale. see your ibm representative for more information. 3. ibm square outline conforms to jedec mo-158. a a1 dla lidless dla chip aaa d e e1 d1 e ccc ccc b note: no i/o at a01 location yddd m yeee m z z xy a a1 aaa z y x terminal a01 identifier to p v iew bottom view z IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 70 of 444 np3_dl_sec02_phys.fm.01 09/25/00 table 31: mechanical specifications mechanical dimensions value 1 a(dla) min 2 6.23 max 3 6.83 a (lidless) min 2 4.23 max 3 4.83 a1 nom 2.21 b min 0.48 max 0.52 e basic 1.27 aaa 0.15 ccc 0.20 ddd 0.30 eee 0.10 d 42.50 d1 40.64 e 42.50 e1 40.64 m 4 33 x 33 n 5 1088 5 weight (g) tbd 1. all dimensions are in millimeters, except where noted. 2. minimum package thickness is calculated using the nominal thickness of all parts. the nominal thickness of an 8-layer package was used for the package thickness. 3. maximum package thickness is calculated using the nominal thickness of all parts. the nominal thickness of a 12-layer package was used for the package thickness. 4. m = the i/o matrix size. 5. n = the maximum number of i/os. the number of i/os shown in the table is the amount after depopulation. product with 1.27 mm pitch is depopulated by 1 i/o at the a01 corner of the array. 6. ibm square outline conforms to jedec mo-158. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 71 of 444 2.3 signal pin lists note: all unused pins should be left unconnected on the card. table 32: complete signal pin listing by signal name (page 1 of 10) signal name grid position signal name grid position signal name grid position blade_reset e29 d0_data(16) aj07 d1_data(01) an11 boot_picocode k07 d0_data(17) an04 d1_data(02) al12 boot_ppc l04 d0_data(18) an07 d1_data(03) aj10 c405_debug_halt ab23 d0_data(19) al07 d1_data(04) ak09 clock125 b33 d0_data(20) af09 d1_data(05) y15 core_clock c33 d0_data(21) ag08 d1_data(06) aa15 d0_addr(00) al10 d0_data(22) ae10 d1_data(07) aj11 d0_addr(01) an10 d0_data(23) ad11 d1_data(08) ak11 d0_addr(02) aj09 d0_data(24) an08 d1_data(09) al13 d0_addr(03) an06 d0_data(25) al09 d1_data(10) an12 d0_addr(04) aa14 d0_data(26) al06 d1_data(11) ah11 d0_addr(05) ab15 d0_data(27) am05 d1_data(12) am13 d0_addr(06) am07 d0_data(28) ab13 d1_data(13) an13 d0_addr(07) al08 d0_data(29) ac15 d1_data(14) ah13 d0_addr(08) am11 d0_data(30) ak07 d1_data(15) ac16 d0_addr(09) al11 d0_data(31) aj08 d1_dqs(0) aj14 d0_addr(10) ac14 d0_dqs(0) ag09 d1_dqs(1) an16 d0_addr(11) ag10 d0_dqs(1) ac12 d1_we al16 d0_addr(12) af11 d0_dqs(2) ae11 d2_addr(00) aj22 d0_cs an09 d0_dqs(3) ah09 d2_addr(01) ah21 d0_data(00) aa12 d0_we am09 d2_addr(02) an21 d0_data(01) ad09 d1_addr(00) ab17 d2_addr(03) am21 d0_data(02) ag07 d1_addr(01) aj13 d2_addr(04) ah23 d0_data(03) ab11 d1_addr(02) ak13 d2_addr(05) ac20 d0_data(04) an02 d1_addr(03) am15 d2_addr(06) ad21 d0_data(05) am03 d1_addr(04) an14 d2_addr(07) ag23 d0_data(06) an01 d1_addr(05) ag12 d2_addr(08) an22 d0_data(07) an03 d1_addr(06) af13 d2_addr(09) al21 d0_data(08) al04 d1_addr(07) ae14 d2_addr(10) ak23 d0_data(09) ag03 d1_addr(08) an15 d2_addr(11) aj23 d0_data(10) ah07 d1_addr(09) al14 d2_addr(12) aa19 d0_data(11) ae09 d1_addr(10) w16 d2_cs al22 d0_data(12) al03 d1_addr(11) ah15 d2_data(00) an18 d0_data(13) ac11 d1_addr(12) aj15 d2_data(01) aj19 d0_data(14) aj06 d1_cs ad15 d2_data(02) w18 d0_data(15) ak05 d1_data(00) ae12 d2_data(03) aa18 IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 72 of 444 np3_dl_sec02_phys.fm.01 09/25/00 d2_data(04) aj20 d3_data(10) ag16 d4_data(16) e14 d2_data(05) al20 d3_data(11) ah17 d4_data(17) c14 d2_data(06) an19 d3_data(12) ag17 d4_data(18) e09 d2_data(07) ae20 d3_data(13) ag15 d4_data(19) a15 d2_data(08) ae17 d3_data(14) af15 d4_data(20) l15 d2_data(09) ae21 d3_data(15) af19 d4_data(21) j14 d2_data(10) ag22 d3_dqs(0) ag20 d4_data(22) g12 d2_data(11) an20 d3_dqs(1) ac17 d4_data(23) h13 d2_data(12) am19 d3_we ad19 d4_data(24) a14 d2_data(13) ak21 d4_addr(00) c12 d4_data(25) b15 d2_data(14) aj21 d4_addr(01) a11 d4_data(26) d13 d2_data(15) y19 d4_addr(02) j12 d4_data(27) e13 d2_dqs(0) ab19 d4_addr(03) h11 d4_data(28) p15 d2_dqs(1) ak25 d4_addr(04) g10 d4_data(29) e12 d2_we aj24 d4_addr(05) l13 d4_data(30) f13 d3_addr(00) ag19 d4_addr(06) c11 d4_data(31) a13 d3_addr(01) aj16 d4_addr(07) b11 d4_dqs(0) d11 d3_addr(02) af17 d4_addr(08) d09 d4_dqs(1) e11 d3_addr(03) aj17 d4_addr(09) c08 d4_dqs(2) n15 d3_addr(04) ag18 d4_addr(10) m13 d4_dqs(3) m15 d3_addr(05) ae18 d4_addr(11) n14 d4_we f11 d3_addr(06) aa17 d4_addr(12) b07 d6_addr(00) al28 d3_addr(07) ac18 d4_cs e10 d6_addr(01) an26 d3_addr(08) ak19 d4_data(00) m17 d6_addr(02) ae24 d3_addr(09) al19 d4_data(01) l16 d6_addr(03) ag26 d3_addr(10) an17 d4_data(02) d15 d6_addr(04) af25 d3_addr(11) ak17 d4_data(03) c15 d6_addr(05) al27 d3_addr(12) ae19 d4_data(04) a17 d6_addr(06) an30 d3_cs al18 d4_data(05) d17 d6_addr(07) aj27 d3_data(00) ag13 d4_data(06) h09 d6_addr(08) ak29 d3_data(01) aa16 d4_data(07) g14 d6_addr(09) aj28 d3_data(02) ag14 d4_data(08) g13 d6_addr(10) al29 d3_data(03) ae15 d4_data(09) k15 d6_addr(11) ag21 d3_data(04) al17 d4_data(10) c16 d6_addr(12) ah27 d3_data(05) am17 d4_data(11) a16 d6_byteen(0) ag24 d3_data(06) al15 d4_data(12) e15 d6_byteen(1) af23 d3_data(07) ak15 d4_data(13) f15 d6_cs al31 d3_data(08) w17 d4_data(14) r17 d6_data(00) al23 d3_data(09) ae16 d4_data(15) n16 d6_data(01) am23 table 32: complete signal pin listing by signal name (page 2 of 10) signal name grid position signal name grid position signal name grid position IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 73 of 444 d6_data(02) al26 dasl_in_b(0) e02 dasl_out_b(3) n03 d6_data(03) am27 dasl_in_b(0) d01 dasl_out_b(4) l05 d6_data(04) ab21 dasl_in_b(1) j02 dasl_out_b(4) l06 d6_data(05) an28 dasl_in_b(1) h01 dasl_out_b(5) k05 d6_data(06) an24 dasl_in_b(2) f03 dasl_out_b(5) l07 d6_data(07) al24 dasl_in_b(2) f01 dasl_out_b(6) j05 d6_data(08) ah25 dasl_in_b(3) g02 dasl_out_b(6) j04 d6_data(09) ae23 dasl_in_b(3) g04 dasl_out_b(7) h05 d6_data(10) ac21 dasl_in_b(4) j03 dasl_out_b(7) h03 d6_data(11) an25 dasl_in_b(4) j01 da_ba(0) an29 d6_data(12) aj26 dasl_in_b(5) k01 da_ba(1) aa20 d6_data(13) ak27 dasl_in_b(5) k03 da_cas an27 d6_data(14) ae22 dasl_in_b(6) l03 da_clk am25 d6_data(15) ac22 dasl_in_b(6) l02 da_clk al25 d6_dqs(0) al30 dasl_in_b(7) n04 da_ras ag25 d6_dqs(1) an31 dasl_in_b(7) m03 db_ba(0) ag11 d6_dqs(2) an33 dasl_out_a(0) y01 db_ba(1) ad13 d6_dqs(3) am31 dasl_out_a(0) w02 db_cas aj12 d6_dqs_par(00) an32 dasl_out_a(1) w03 db_clk ah19 d6_dqs_par(01) af21 dasl_out_a(1) aa01 db_clk aj18 d6_parity(00) am29 dasl_out_a(2) ab01 db_ras ae13 d6_parity(01) an23 dasl_out_a(2) aa02 dc_ba(0) d25 d6_we aj25 dasl_out_a(3) ac06 dc_ba(1) j17 dasl_in_a(0) ak01 dasl_out_a(3) ac05 dc_cas n19 dasl_in_a(0) aj02 dasl_out_a(4) ac07 dc_clk e23 dasl_in_a(1) af01 dasl_out_a(4) ad05 dc_clk d23 dasl_in_a(1) ae02 dasl_out_a(5) ae04 dc_ras c21 dasl_in_a(2) ah01 dasl_out_a(5) ae05 dd_ba(0) a12 dasl_in_a(2) ah03 dasl_out_a(6) af03 dd_ba(1) j13 dasl_in_a(3) ae01 dasl_out_a(6) af05 dd_cas g11 dasl_in_a(3) ae03 dasl_out_a(7) ag04 dd_clk c13 dasl_in_a(4) ad03 dasl_out_a(7) ag02 dd_clk b13 dasl_in_a(4) ad01 dasl_out_b(0) r02 dd_ras k13 dasl_in_a(5) ac02 dasl_out_b(0) p01 de_ba(0) am01 dasl_in_a(5) ac03 dasl_out_b(1) n01 de_ba(1) ah05 dasl_in_a(6) ab03 dasl_out_b(1) r03 de_cas al02 dasl_in_a(6) aa04 dasl_out_b(2) n02 de_clk aj04 dasl_in_a(7) aa03 dasl_out_b(2) m01 de_clk aj05 dasl_in_a(7) y03 dasl_out_b(3) p03 dd_ras k13 table 32: complete signal pin listing by signal name (page 3 of 10) signal name grid position signal name grid position signal name grid position IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 74 of 444 np3_dl_sec02_phys.fm.01 09/25/00 dmu_a(00) v31 dmu_b(08) r28 dmu_c(16) m23 dmu_a(01) v29 dmu_b(09) r27 dmu_c(17) n33 dmu_a(02) v27 dmu_b(10) r26 dmu_c(18) n32 dmu_a(03) w33 dmu_b(11) r25 dmu_c(19) n31 dmu_a(04) w32 dmu_b(12) r24 dmu_c(20) n30 dmu_a(05) w31 dmu_b(13) r23 dmu_c(21) n29 dmu_a(06) w30 dmu_b(14) t33 dmu_c(22) n28 dmu_a(07) w29 dmu_b(15) t31 dmu_c(23) n27 dmu_a(08) w28 dmu_b(16) t29 dmu_c(24) n26 dmu_a(09) w27 dmu_b(17) t27 dmu_c(25) n25 dmu_a(10) w26 dmu_b(18) r22 dmu_c(26) n24 dmu_a(11) w25 dmu_b(19) t23 dmu_c(27) n23 dmu_a(12) w24 dmu_b(20) v25 dmu_c(28) p33 dmu_a(13) w23 dmu_b(21) u32 dmu_c(29) p31 dmu_a(14) y33 dmu_b(22) u31 dmu_c(30) p29 dmu_a(15) y31 dmu_b(23) u30 dmu_d(00) d33 dmu_a(16) y29 dmu_b(24) u29 dmu_d(01) d31 dmu_a(17) y27 dmu_b(25) u28 dmu_d(02) g28 dmu_a(18) y25 dmu_b(26) u27 dmu_d(03) j29 dmu_a(19) y23 dmu_b(27) u26 dmu_d(04) e30 dmu_a(20) aa33 dmu_b(28) u25 dmu_d(05) f33 dmu_a(21) aa32 dmu_b(29) u24 dmu_d(06) f31 dmu_a(22) aa31 dmu_b(30) v33 dmu_d(07) f29 dmu_a(23) aa30 dmu_c(00) l33 dmu_d(08) g32 dmu_a(24) aa29 dmu_c(01) l32 dmu_d(09) k25 dmu_a(25) aa28 dmu_c(02) l31 dmu_d(10) g30 dmu_a(26) aa27 dmu_c(03) l30 dmu_d(11) g29 dmu_a(27) aa26 dmu_c(04) l29 dmu_d(12) e32 dmu_a(28) aa25 dmu_c(05) l28 dmu_d(13) h33 dmu_a(29) ab33 dmu_c(06) l27 dmu_d(14) h31 dmu_a(30) ab31 dmu_c(07) l26 dmu_d(15) h29 dmu_b(00) p27 dmu_c(08) l25 dmu_d(16) h27 dmu_b(01) p25 dmu_c(09) l24 dmu_d(17) j33 dmu_b(02) p23 dmu_c(10) l23 dmu_d(18) j32 dmu_b(03) r33 dmu_c(11) m33 dmu_d(19) j31 dmu_b(04) r32 dmu_c(12) m31 dmu_d(20) j30 dmu_b(05) r31 dmu_c(13) m29 dmu_d(21) k27 dmu_b(06) r30 dmu_c(14) m27 dmu_d(22) j28 dmu_b(07) r29 dmu_c(15) m25 dmu_d(23) j27 table 32: complete signal pin listing by signal name (page 4 of 10) signal name grid position signal name grid position signal name grid position IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 75 of 444 dmu_d(24) j26 ds0_data(18) j24 ds1_data(06) a21 dmu_d(25) j25 ds0_data(19) k23 ds1_data(07) f21 dmu_d(26) k33 ds0_data(20) a26 ds1_data(08) e22 dmu_d(27) k31 ds0_data(21) c25 ds1_data(09) l18 dmu_d(28) k29 ds0_data(22) c28 ds1_data(10) l17 dmu_d(29) e31 ds0_data(23) b29 ds1_data(11) e21 dmu_d(30) g31 ds0_data(24) m21 ds1_data(12) d21 ds0_addr(00) a28 ds0_data(25) l19 ds1_data(13) b19 ds0_addr(01) n20 ds0_data(26) d27 ds1_data(14) a20 ds0_addr(02) m19 ds0_data(27) e26 ds1_data(15) g22 ds0_addr(03) b27 ds0_data(28) a25 ds1_data(16) j21 ds0_addr(04) c26 ds0_data(29) b25 ds1_data(17) j15 ds0_addr(05) b23 ds0_data(30) g25 ds1_data(18) j20 ds0_addr(06) c23 ds0_data(31) l22 ds1_data(19) a19 ds0_addr(07) g24 ds0_dqs(0) f25 ds1_data(20) e18 ds0_addr(08) h23 ds0_dqs(1) c24 ds1_data(21) c20 ds0_addr(09) j22 ds0_dqs(2) a24 ds1_data(22) e20 ds0_addr(10) a23 ds0_dqs(3) e25 ds1_data(23) n18 ds0_addr(11) c22 ds0_we j23 ds1_data(24) f19 ds0_addr(12) e24 ds1_addr(00) n17 ds1_data(25) e19 ds0_cs a31 ds1_addr(01) j18 ds1_data(26) a18 ds0_data(00) p19 ds1_addr(02) g18 ds1_data(27) c18 ds0_data(01) a32 ds1_addr(03) e17 ds1_data(28) k19 ds0_data(02) b31 ds1_addr(04) h17 ds1_data(29) g21 ds0_data(03) a33 ds1_addr(05) g19 ds1_data(30) g20 ds0_data(04) c30 ds1_addr(06) h19 ds1_data(31) j19 ds0_data(05) c31 ds1_addr(07) h15 ds1_dqs(0) b17 ds0_data(06) f27 ds1_addr(08) g15 ds1_dqs(1) c19 ds0_data(07) h21 ds1_addr(09) g17 ds1_dqs(2) d19 ds0_data(08) c29 ds1_addr(10) f17 ds1_dqs(3) r18 ds0_data(09) a29 ds1_addr(11) g16 ds1_we c17 ds0_data(10) e28 ds1_addr(12) j16 dum a01 ds0_data(11) d29 ds1_cs e16 gnd b10 ds0_data(12) e27 ds1_data(00) a22 gnd ah32 ds0_data(13) a30 ds1_data(01) g23 gnd ak04 ds0_data(14) a27 ds1_data(02) k21 gnd b24 ds0_data(15) c27 ds1_data(03) l20 gnd ah24 ds0_data(16) h25 ds1_data(04) f23 gnd ah28 ds0_data(17) g26 ds1_data(05) b21 gnd af30 table 32: complete signal pin listing by signal name (page 5 of 10) signal name grid position signal name grid position signal name grid position IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 76 of 444 np3_dl_sec02_phys.fm.01 09/25/00 gnd af18 gnd am02 gnd k24 gnd b32 gnd f06 gnd ab04 gnd af12 gnd ak18 gnd m26 gnd b28 gnd am10 gnd k06 gnd af16 gnd f20 gnd ab26 gnd ah20 gnd am14 gnd k02 gnd b20 gnd ad06 gnd t12 gnd y17 gnd ak22 gnd m22 gnd w19 gnd ad24 gnd r15 gnd y20 gnd f10 gnd r19 gnd k20 gnd ad14 gnd d04 gnd f32 gnd t30 gnd h12 gnd w15 gnd f28 gnd af08 gnd y02 gnd ah06 gnd d08 gnd v30 gnd m08 gnd v12 gnd am20 gnd d12 gnd af04 gnd ah10 gnd h18 gnd t16 gnd af26 gnd p14 gnd v26 gnd af22 gnd p24 gnd d22 gnd f02 gnd m30 gnd y10 gnd ah02 gnd p17 gnd p06 gnd b06 gnd t04 gnd v22 gnd ah14 gnd m12 gnd d26 gnd b02 gnd ab30 gnd y14 gnd b14 gnd h16 gnd am24 gnd ad20 gnd k10 gnd v04 gnd d16 gnd h04 gnd am28 gnd ak26 gnd ab12 gnd v08 gnd u20 gnd h26 gnd v16 gnd ak30 gnd p20 gnd am32 gnd ad28 gnd ab16 gnd h30 gnd ad10 gnd ab18 gnd k32 gnd y24 gnd p10 gnd k28 gnd ad32 gnd m04 gnd h08 gnd t18 gnd d18 gnd p02 gnd ad02 gnd ab08 gnd p32 gnd y32 gnd y17 gnd d30 gnd ak08 gnd t22 gnd ak16 gnd ak12 gnd am06 gnd t26 table 32: complete signal pin listing by signal name (page 6 of 10) signal name grid position signal name grid position signal name grid position IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 77 of 444 gnd u14 lu_clk aj03 mc_grant_a(1) w21 gnd y28 lu_data(00) u15 mc_grant_b(0) r20 gnd f14 lu_data(01) u13 mc_grant_b(1) p21 gnd v18 lu_data(02) t09 mgrant_a(0) v19 gnd ab22 lu_data(03) t07 mgrant_a(1) u19 gnd y06 lu_data(04) r07 mgrant_b(0) ag27 gnd k14 lu_data(05) r08 mgrant_b(1) ae25 gnd f24 lu_data(06) w06 mg_clk j07 gnd h22 lu_data(07) w05 mg_data j06 gnd t08 lu_data(08) u08 mg_nintr j08 gnd m18 lu_data(09) v07 operational c32 gnd m16 lu_data(10) v09 pci_ad(00) ab29 gnd u17 lu_data(11) u12 pci_ad(01) ab27 gnd p28 lu_data(12) v15 pci_ad(02) ab25 i_freeq_th v21 lu_data(13) w04 pci_ad(03) ac33 jtag_tck aa22 lu_data(14) v11 pci_ad(04) ac32 jtag_tdi w22 lu_data(15) w07 pci_ad(05) ac31 jtag_tdo aa23 lu_data(16) w08 pci_ad(06) ac30 jtag_tms u22 lu_data(17) y07 pci_ad(07) ac29 jtag_trst t25 lu_data(18) v13 pci_ad(08) ac27 lu_addr(00) aa09 lu_data(19) w13 pci_ad(09) ac26 lu_addr(01) y11 lu_data(20) w01 pci_ad(10) ac25 lu_addr(02) aa10 lu_data(21) w09 pci_ad(11) ac24 lu_addr(03) ab07 lu_data(22) y09 pci_ad(12) ad33 lu_addr(04) ac09 lu_data(23) aa06 pci_ad(13) ad31 lu_addr(05) ae06 lu_data(24) t15 pci_ad(14) ad29 lu_addr(06) ae07 lu_data(25) w10 pci_ad(15) ad27 lu_addr(07) ac01 lu_data(26) w12 pci_ad(16) af29 lu_addr(08) r04 lu_data(27) w14 pci_ad(17) af27 lu_addr(09) ag05 lu_data(28) aa07 pci_ad(18) ag33 lu_addr(10) ag06 lu_data(29) aa08 pci_ad(19) ag32 lu_addr(11) ac04 lu_data(30) u01 pci_ad(20) ag31 lu_addr(12) ad07 lu_data(31) w11 pci_ad(21) ag30 lu_addr(13) af07 lu_data(32) y05 pci_ad(22) ag29 lu_addr(14) ab05 lu_data(33) r05 pci_ad(23) ag28 lu_addr(15) ae08 lu_data(34) u10 pci_ad(24) ah29 lu_addr(16) ab09 lu_data(35) u03 pci_ad(25) aj33 lu_addr(17) aa05 lu_r_wrt ac08 pci_ad(26) aj32 lu_addr(18) aa11 mc_grant_a(0) y21 pci_ad(27) aj31 table 32: complete signal pin listing by signal name (page 7 of 10) signal name grid position signal name grid position signal name grid position IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 78 of 444 np3_dl_sec02_phys.fm.01 09/25/00 pci_ad(28) aj30 sch_addr(05) e04 spare_tst_rcvr(3) t01 pci_ad(29) aj29 sch_addr(06) h07 spare_tst_rcvr(4) al01 pci_ad(30) ak33 sch_addr(07) f05 spare_tst_rcvr(5) g03 pci_ad(31) ak31 sch_addr(08) f07 spare_tst_rcvr(6) v01 pci_bus_m_int ac23 sch_addr(09) c03 spare_tst_rcvr(7) v03 pci_bus_nm_int g27 sch_addr(10) d05 spare_tst_rcvr(8) t03 pci_cbe(0) ac28 sch_addr(11) a02 spare_tst_rcvr(9) u33 pci_cbe(1) ad25 sch_addr(12) c04 switch_bna r21 pci_cbe(2) af31 sch_addr(13) b03 switch_clk_a an05 pci_cbe(3) ah31 sch_addr(14) c02 switch_clk_a al05 pci_clk af33 sch_addr(15) d03 switch_clk_b c05 pci_devsel ae29 sch_addr(16) b01 switch_clk_b a05 pci_frame ae26 sch_addr(17) c01 testmode(0) v05 pci_grant al32 sch_addr(18) e05 testmode(1) u06 pci_idsel ah33 sch_clk c07 thermal_in u04 pci_inta am33 sch_data(00) a10 thermal_out u02 pci_irdy ae27 sch_data(01) c10 unused u07 pci_par ae33 sch_data(02) f09 unused n05 pci_perr ae31 sch_data(03) j11 unused t11 pci_request al33 sch_data(04) l12 unused n10 pci_serr ae32 sch_data(05) g09 unused n09 pci_speed m07 sch_data(06) b09 unused t13 pci_stop ae30 sch_data(07) a09 unused j09 pci_trdy ae28 sch_data(08) a06 unused n12 plla_gnd ag01 sch_data(09) e08 unused r16 plla_v dd aj01 sch_data(10) g06 unused n07 pllb_gnd g01 sch_data(11) g07 unused m11 pllb_v dd e01 sch_data(12) c06 unused r12 pllc_gnd g33 sch_data(13) d07 unused r11 pllc_v dd e33 sch_data(14) c09 unused n06 res_data t21 sch_data(15) a08 unused r09 res_sync u21 sch_data(16) j10 unused u11 rx_lbyte(0) u23 sch_data(17) g08 unused r13 rx_lbyte(1) v23 sch_r_wrt g05 unused u09 sch_addr(00) a07 send_grant_a w20 unused t05 sch_addr(01) b05 send_grant_b t19 unused k09 sch_addr(02) a04 spare_tst_rcvr(0) u05 unused p07 sch_addr(03) e06 spare_tst_rcvr(1) e03 unused l08 sch_addr(04) e07 spare_tst_rcvr(2) a03 unused l09 table 32: complete signal pin listing by signal name (page 8 of 10) signal name grid position signal name grid position signal name grid position IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 79 of 444 unused r01 v dd f04 v dd v14 unused p13 v dd b12 v dd v06 unused m09 v dd ab10 v dd ad16 unused n08 v dd ah26 v dd d28 unused l01 v dd ak06 v dd b18 unused n22 v dd ak02 v dd b26 unused m05 v dd m32 v dd af10 unused aa24 v dd y18 v dd am16 unused r14 v dd k30 v dd u18 unused l11 v dd v32 vref1(0) ad23 unused r10 v dd v24 vref1(1) k11 unused p05 v dd t10 vref1(2) ac10 unused r06 v dd am22 vref2(0) ac19 unused p11 v dd af20 vref2(1) ad17 unused p09 v dd d32 vref2(2) ac13 v dd ad04 v dd p16 vref2(3) l14 v dd t20 v dd y16 vref2(4) k17 v dd af06 v dd ad26 vref2(5) l21 v dd ab28 v dd b04 vref2(6) y13 v dd aa13 v dd am30 vref2(7) n11 v dd k12 v dd y30 vref2(8) l10 v dd t17 v dd ah30 2.5 v p12 v dd h02 v dd y08 2.5 v d02 v dd n21 v dd f08 2.5 v ak10 v dd k08 v dd p04 2.5 v f26 v dd t14 v dd ak24 2.5 v h10 v dd t02 v dd p18 2.5 v d06 v dd t28 v dd ah18 2.5 v am18 v dd k18 v dd m24 2.5 v d14 v dd h28 v dd af32 2.5 v am12 v dd f22 v dd am08 2.5 v af02 v dd v17 v dd ak14 2.5 v f18 v dd v20 v dd ah12 2.5 v k04 v dd h24 v dd m06 2.5 v ab20 v dd p26 v dd h14 2.5 v y04 v dd u16 v dd f16 2.5 v ah22 v dd d10 v dd n13 2.5 v ah04 v dd d20 v dd ab02 2.5 v v10 v dd aa21 v dd ad22 2.5 v y12 table 32: complete signal pin listing by signal name (page 9 of 10) signal name grid position signal name grid position signal name grid position IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 80 of 444 np3_dl_sec02_phys.fm.01 09/25/00 note: all unused pins should be left unused on the card. 2.5 v m10 2.5 v m02 3.3 v y22 2.5 v ah08 2.5 v b22 3.3 v m28 2.5 v ad18 2.5 v ah16 3.3 v y26 2.5 v v02 2.5 v am26 3.3 v p30 2.5 v d24 2.5 v af24 3.3 v t24 2.5 v t06 2.5 v ab06 3.3 v p22 2.5 v b16 2.5 v am04 3.3 v af28 2.5 v h06 2.5 v f12 3.3 v ab24 2.5 v af14 2.5 v b08 3.3 v f30 2.5 v m14 2.5 v ak20 3.3 v ab32 2.5 v ab14 2.5 v k16 3.3 v v28 2.5 v b30 2.5 v ak28 3.3 v h32 2.5 v h20 2.5 v p08 3.3 v k26 2.5 v k22 2.5 v m20 3.3 v ak32 2.5 v ad08 2.5 v ad12 3.3 v t32 3.3 v ad30 table 32: complete signal pin listing by signal name (page 10 of 10) signal name grid position signal name grid position signal name grid position IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 81 of 444 table 33: complete signal pin listing by grid position (page1of10) grid position signal name grid position signal name grid position signal name a01 dum aa04 dasl_in_a (6) ab07 lu_addr(03) a02 sch_addr(11) aa05 lu_addr(17) ab08 gnd a03 spare_tst_rcvr(2) aa06 lu_data(23) ab09 lu_addr(16) a04 sch_addr(02) aa07 lu_data(28) ab10 v dd a05 switch_clk_b aa08 lu_data(29) ab11 d0_data(03) a06 sch_data(08) aa09 lu_addr(00) ab12 gnd a07 sch_addr(00) aa10 lu_addr(02) ab13 d0_data(28) a08 sch_data(15) aa11 lu_addr(18) ab14 2.5v a09 sch_data(07) aa12 d0_data(00) ab15 d0_addr(05) a10 sch_data(00) aa13 v dd ab16 gnd a11 d4_addr(01) aa14 d0_addr(04) ab17 d1_addr(00) a12 dd_ba(0) aa15 d1_data(06) ab18 gnd a13 d4_data(31) aa16 d3_data(01) ab19 d2_dqs(0) a14 d4_data(24) aa17 d3_addr(06) ab20 2.5v a15 d4_data(19) aa18 d2_data(03) ab21 d6_data(04) a16 d4_data(11) aa19 d2_addr(12) ab22 gnd a17 d4_data(04) aa20 da_ba(1) ab23 c405_debug_halt a18 ds1_data(26) aa21 v dd ab24 3.3v a19 ds1_data(19) aa22 jtag_tck ab25 pci_ad(02) a20 ds1_data(14) aa23 jtag_tdo ab26 gnd a21 ds1_data(06) aa24 unused ab27 pci_ad(01) a22 ds1_data(00) aa25 dmu_a(28) ab28 v dd a23 ds0_addr(10) aa26 dmu_a(27) ab29 pci_ad(00) a24 ds0_dqs(2) aa27 dmu_a(26) ab30 gnd a25 ds0_data(28) aa28 dmu_a(25) ab31 dmu_a(30) a26 ds0_data(20) aa29 dmu_a(24) ab32 3.3v a27 ds0_data(14) aa30 dmu_a(23) ab33 dmu_a(29) a28 ds0_addr(00) aa31 dmu_a(22) ac01 lu_addr(07) a29 ds0_data(09) aa32 dmu_a(21) ac02 dasl_in_a(5) a30 ds0_data(13) aa33 dmu_a(20) ac03 dasl_in_a (5) a31 ds0_cs ab01 dasl_out_a(2) ac04 lu_addr(11) a32 ds0_data(01) ab02 v dd ac05 dasl_out_a (3) a33 ds0_data(03) ab03 dasl_in_a(6) ac06 dasl_out_a(3) aa01 dasl_out_a(1) ab04 gnd ac07 dasl_out_a(4) aa02 dasl_out_a(2) ab05 lu_addr(14) ac08 lu_r_wrt aa03 dasl_in_a(7) ab06 2.5v ac09 lu_addr(04) IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 82 of 444 np3_dl_sec02_phys.fm.01 09/25/00 ac10 vref1(2) ad13 db_ba(1) ae16 d3_data(09) ac11 d0_data(13) ad14 gnd ae17 d2_data(08) ac12 d0_dqs(1) ad15 d1_cs ae18 d3_addr(05) ac13 vref2(2) ad16 v dd ae19 d3_addr(12) ac14 d0_addr(10) ad17 vref2(1) ae20 d2_data(07) ac15 d0_data(29) ad18 2.5v ae21 d2_data(09) ac16 d1_data(15) ad19 d3_we ae22 d6_data(14) ac17 d3_dqs(1) ad20 gnd ae23 d6_data(09) ac18 d3_addr(07) ad21 d2_addr(06) ae24 d6_addr(02) ac19 vref2(0) ad22 v dd ae25 mgrant_b(1) ac20 d2_addr(05) ad23 vref1(0) ae26 pci_frame ac21 d6_data(10) ad24 gnd ae27 pci_irdy ac22 d6_data(15) ad25 pci_cbe(1) ae28 pci_trdy ac23 pci_bus_m_int ad26 v dd ae29 pci_devsel ac24 pci_ad(11) ad27 pci_ad(15) ae30 pci_stop ac25 pci_ad(10) ad28 gnd ae31 pci_perr ac26 pci_ad(09) ad29 pci_ad(14) ae32 pci_serr ac27 pci_ad(08) ad30 3.3v ae33 pci_par ac28 pci_cbe(0) ad31 pci_ad(13) af01 dasl_in_a(1) ac29 pci_ad(07) ad32 gnd af02 2.5v ac30 pci_ad(06) ad33 pci_ad(12) af03 dasl_out_a(6) ac31 pci_ad(05) ae01 dasl_in_a(3) af04 gnd ac32 pci_ad(04) ae02 dasl_in_a (1) af05 dasl_out_a (6) ac33 pci_ad(03) ae03 dasl_in_a (3) af06 v dd ad01 dasl_in_a (4) ae04 dasl_out_a(5) af07 lu_addr(13) ad02 gnd ae05 dasl_out_a (5) af08 gnd ad03 dasl_in_a(4) ae06 lu_addr(05) af09 d0_data(20) ad04 v dd ae07 lu_addr(06) af10 v dd ad05 dasl_out_a(4) ae08 lu_addr(15) af11 d0_addr(12) ad06 gnd ae09 d0_data(11) af12 gnd ad07 lu_addr(12) ae10 d0_data(22) af13 d1_addr(06) ad08 2.5v ae11 d0_dqs(2) af14 2.5v ad09 d0_data(01) ae12 d1_data(00) af15 d3_data(14) ad10 gnd ae13 db_ras af16 gnd ad11 d0_data(23) ae14 d1_addr(07) af17 d3_addr(02) ad12 2.5v ae15 d3_data(03) af18 gnd af19 d3_data(15) ag22 d2_data(10) ah25 d6_data(08) table 33: complete signal pin listing by grid position (page2of10) grid position signal name grid position signal name grid position signal name IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 83 of 444 af20 v dd ag23 d2_addr(07) ah26 v dd af21 d6_dqs_par(01) ag24 d6_byteen(0) ah27 d6_addr(12) af22 gnd ag25 da_ras ah28 gnd af23 d6_byteen(1) ag26 d6_addr(03) ah29 pci_ad(24) af24 2.5v ag27 mgrant_b(0) ah30 v dd af25 d6_addr(04) ag28 pci_ad(23) ah31 pci_cbe(3) af26 gnd ag29 pci_ad(22) ah32 gnd af27 pci_ad(17) ag30 pci_ad(21) ah33 pci_idsel af28 3.3v ag31 pci_ad(20) aj01 plla_v dd af29 pci_ad(16) ag32 pci_ad(19) aj02 dasl_in_a (0) af30 gnd ag33 pci_ad(18) aj03 lu_clk af31 pci_cbe(2) ah01 dasl_in_a(2) aj04 de_clk af32 v dd ah02 gnd aj05 de_clk af33 pci_clk ah03 dasl_in_a (2) aj06 d0_data(14) ag01 plla_gnd ah04 2.5v aj07 d0_data(16) ag02 dasl_out_a(7) ah05 de_ba(1) aj08 d0_data(31) ag03 d0_data(09) ah06 gnd aj09 d0_addr(02) ag04 dasl_out_a(7) ah07 d0_data(10) aj10 d1_data(03) ag05 lu_addr(09) ah08 2.5v aj11 d1_data(07) ag06 lu_addr(10) ah09 d0_dqs(3) aj12 db_cas ag07 d0_data(02) ah10 gnd aj13 d1_addr(01) ag08 d0_data(21) ah11 d1_data(11) aj14 d1_dqs(0) ag09 d0_dqs(0) ah12 v dd aj15 d1_addr(12) ag10 d0_addr(11) ah13 d1_data(14) aj16 d3_addr(01) ag11 db_ba(0) ah14 gnd aj17 d3_addr(03) ag12 d1_addr(05) ah15 d1_addr(11) aj18 db_clk ag13 d3_data(00) ah16 2.5v aj19 d2_data(01) ag14 d3_data(02) ah17 d3_data(11) aj20 d2_data(04) ag15 d3_data(13) ah18 v dd aj21 d2_data(14) ag16 d3_data(10) ah19 db_clk aj22 d2_addr(00) ag17 d3_data(12) ah20 gnd aj23 d2_addr(11) ag18 d3_addr(04) ah21 d2_addr(01) aj24 d2_we ag19 d3_addr(00) ah22 2.5v aj25 d6_we ag20 d3_dqs(0) ah23 d2_addr(04) aj26 d6_data(12) ag21 d6_addr(11) ah24 gnd aj27 d6_addr(07) aj28 d6_addr(09) ak31 pci_ad(31) am01 de_ba(0) aj29 pci_ad(29) ak32 3.3v am02 gnd table 33: complete signal pin listing by grid position (page3of10) grid position signal name grid position signal name grid position signal name IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 84 of 444 np3_dl_sec02_phys.fm.01 09/25/00 aj30 pci_ad(28) ak33 pci_ad(30) am03 d0_data(05) aj31 pci_ad(27) al01 spare_tst_rcvr(4) am04 2.5v aj32 pci_ad(26) al02 de_cas am05 d0_data(27) aj33 pci_ad(25) al03 d0_data(12) am06 gnd ak01 dasl_in_a(0) al04 d0_data(08) am07 d0_addr(06) ak02 v dd al05 switch_clk_a am08 v dd ak03 de_ras al06 d0_data(26) am09 d0_we ak04 gnd al07 d0_data(19) am10 gnd ak05 d0_data(15) al08 d0_addr(07) am11 d0_addr(08) ak06 v dd al09 d0_data(25) am12 2.5v ak07 d0_data(30) al10 d0_addr(00) am13 d1_data(12) ak08 gnd al11 d0_addr(09) am14 gnd ak09 d1_data(04) al12 d1_data(02) am15 d1_addr(03) ak10 2.5v al13 d1_data(09) am16 v dd ak11 d1_data(08) al14 d1_addr(09) am17 d3_data(05) ak12 gnd al15 d3_data(06) am18 2.5v ak13 d1_addr(02) al16 d1_we am19 d2_data(12) ak14 v dd al17 d3_data(04) am20 gnd ak15 d3_data(07) al18 d3_cs am21 d2_addr(03) ak16 gnd al19 d3_addr(09) am22 v dd ak17 d3_addr(11) al20 d2_data(05) am23 d6_data(01) ak18 gnd al21 d2_addr(09) am24 gnd ak19 d3_addr(08) al22 d2_cs am25 da_clk ak20 2.5v al23 d6_data(00) am26 2.5v ak21 d2_data(13) al24 d6_data(07) am27 d6_data(03) ak22 gnd al25 da_clk am28 gnd ak23 d2_addr(10) al26 d6_data(02) am29 d6_parity(00) ak24 v dd al27 d6_addr(05) am30 v dd ak25 d2_dqs(1) al28 d6_addr(00) am31 d6_dqs(3) ak26 gnd al29 d6_addr(10) am32 gnd ak27 d6_data(13) al30 d6_dqs(0) am33 pci_inta ak28 2.5v al31 d6_cs an01 d0_data(06) ak29 d6_addr(08) al32 pci_grant an02 d0_data(04) ak30 gnd al33 pci_request an03 d0_data(07) an04 d0_data(17) b07 d4_addr(12) c10 sch_data(01) an05 switch_clk_a b08 2.5v c11 d4_addr(06) an06 d0_addr(03) b09 sch_data(06) c12 d4_addr(00) table 33: complete signal pin listing by grid position (page4of10) grid position signal name grid position signal name grid position signal name IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 85 of 444 an07 d0_data(18) b10 gnd c13 dd_clk an08 d0_data(24) b11 d4_addr(07) c14 d4_data(17) an09 d0_cs b12 v dd c15 d4_data(03) an10 d0_addr(01) b13 dd_clk c16 d4_data(10) an11 d1_data(01) b14 gnd c17 ds1_we an12 d1_data(10) b15 d4_data(25) c18 ds1_data(27) an13 d1_data(13) b16 2.5v c19 ds1_dqs(1) an14 d1_addr(04) b17 ds1_dqs(0) c20 ds1_data(21) an15 d1_addr(08) b18 v dd c21 dc_ras an16 d1_dqs(1) b19 ds1_data(13) c22 ds0_addr(11) an17 d3_addr(10) b20 gnd c23 ds0_addr(06) an18 d2_data(00) b21 ds1_data(05) c24 ds0_dqs(1) an19 d2_data(06) b22 2.5v c25 ds0_data(21) an20 d2_data(11) b23 ds0_addr(05) c26 ds0_addr(04) an21 d2_addr(02) b24 gnd c27 ds0_data(15) an22 d2_addr(08) b25 ds0_data(29) c28 ds0_data(22) an23 d6_parity(01) b26 v dd c29 ds0_data(08) an24 d6_data(06) b27 ds0_addr(03) c30 ds0_data(04) an25 d6_data(11) b28 gnd c31 ds0_data(05) an26 d6_addr(01) b29 ds0_data(23) c32 operational an27 da_cas b30 2.5v c33 core_clock an28 d6_data(05) b31 ds0_data(02) d01 dasl_in_b (0) an29 da_ba(0) b32 gnd d02 2.5v an30 d6_addr(06) b33 clock125 d03 sch_addr(15) an31 d6_dqs(1) c01 sch_addr(17) d04 gnd an32 d6_dqs_par(00) c02 sch_addr(14) d05 sch_addr(10) an33 d6_dqs(2) c03 sch_addr(09) d06 2.5v b01 sch_addr(16) c04 sch_addr(12) d07 sch_data(13) b02 gnd c05 switch_clk_b d08 gnd b03 sch_addr(13) c06 sch_data(12) d09 d4_addr(08) b04 v dd c07 sch_clk d10 v dd b05 sch_addr(01) c08 d4_addr(09) d11 d4_dqs(0) b06 gnd c09 sch_data(14) d12 gnd d13 d4_data(26) e16 ds1_cs f19 ds1_data(24) d14 2.5v e17 ds1_addr(03) f20 gnd d15 d4_data(02) e18 ds1_data(20) f21 ds1_data(07) d16 gnd e19 ds1_data(25) f22 v dd table 33: complete signal pin listing by grid position (page5of10) grid position signal name grid position signal name grid position signal name IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 86 of 444 np3_dl_sec02_phys.fm.01 09/25/00 d17 d4_data(05) e20 ds1_data(22) f23 ds1_data(04) d18 gnd e21 ds1_data(11) f24 gnd d19 ds1_dqs(2) e22 ds1_data(08) f25 ds0_dqs(0) d20 v dd e23 dc_clk f26 2.5v d21 ds1_data(12) e24 ds0_addr(12) f27 ds0_data(06) d22 gnd e25 ds0_dqs(3) f28 gnd d23 dc_clk e26 ds0_data(27) f29 dmu_d(07) d24 2.5v e27 ds0_data(12) f30 3.3v d25 dc_ba(0) e28 ds0_data(10) f31 dmu_d(06) d26 gnd e29 blade_reset f32 gnd d27 ds0_data(26) e30 dmu_d(04) f33 dmu_d(05) d28 v dd e31 dmu_d(29) g01 pllb_gnd d29 ds0_data(11) e32 dmu_d(12) g02 dasl_in_b(3) d30 gnd e33 pllc_v dd g03 spare_tst_rcvr(5) d31 dmu_d(01) f01 dasl_in_b (2) g04 dasl_in_b (3) d32 v dd f02 gnd g05 sch_r_wrt d33 dmu_d(00) f03 dasl_in_b(2) g06 sch_data(10) e01 pllb_v dd f04 v dd g07 sch_data(11) e02 dasl_in_b(0) f05 sch_addr(07) g08 sch_data(17) e03 spare_tst_rcvr(1) f06 gnd g09 sch_data(05) e04 sch_addr(05) f07 sch_addr(08) g10 d4_addr(04) e05sch_addr(18) f08v dd g11 dd_cas e06 sch_addr(03) f09 sch_data(02) g12 d4_data(22) e07 sch_addr(04) f10 gnd g13 d4_data(08) e08 sch_data(09) f11 d4_we g14 d4_data(07) e09 d4_data(18) f12 2.5v g15 ds1_addr(08) e10 d4_cs f13 d4_data(30) g16 ds1_addr(11) e11 d4_dqs(1) f14 gnd g17 ds1_addr(09) e12 d4_data(29) f15 d4_data(13) g18 ds1_addr(02) e13 d4_data(27) f16 v dd g19 ds1_addr(05) e14 d4_data(16) f17 ds1_addr(10) g20 ds1_data(30) e15 d4_data(12) f18 2.5v g21 ds1_data(29) g22 ds1_data(15) h25 ds0_data(16) j28 dmu_d(22) g23 ds1_data(01) h26 gnd j29 dmu_d(03) g24 ds0_addr(07) h27 dmu_d(16) j30 dmu_d(20) g25 ds0_data(30) h28 v dd j31 dmu_d(19) g26 ds0_data(17) h29 dmu_d(15) j32 dmu_d(18) table 33: complete signal pin listing by grid position (page6of10) grid position signal name grid position signal name grid position signal name IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 87 of 444 g27 pci_bus_nm_int h30 gnd j33 dmu_d(17) g28 dmu_d(02) h31 dmu_d(14) k01 dasl_in_b(5) g29dmu_d(11) h323.3v k02gnd g30 dmu_d(10) h33 dmu_d(13) k03 dasl_in_b(5) g31 dmu_d(30) j01 dasl_in_b (4) k04 2.5v g32 dmu_d(08) j02 dasl_in_b(1) k05 dasl_out_b(5) g33 pllc_gnd j03 dasl_in_b(4) k06 gnd h01 dasl_in_b (1) j04 dasl_out_b (6) k07 boot_picocode h02 v dd j05 dasl_out_b(6) k08 v dd h03 dasl_out_b (7) j06 mg_data k09 unused h04 gnd j07 mg_clk k10 gnd h05 dasl_out_b(7) j08 mg_nintr k11 vref1(1) h06 2.5v j09 unused k12 v dd h07 sch_addr(06) j10 sch_data(16) k13 dd_ras h08 gnd j11 sch_data(03) k14 gnd h09 d4_data(06) j12 d4_addr(02) k15 d4_data(09) h10 2.5v j13 dd_ba(1) k16 2.5v h11 d4_addr(03) j14 d4_data(21) k17 vref2(4) h12 gnd j15 ds1_data(17) k18 v dd h13 d4_data(23) j16 ds1_addr(12) k19 ds1_data(28) h14 v dd j17 dc_ba(1) k20 gnd h15 ds1_addr(07) j18 ds1_addr(01) k21 ds1_data(02) h16 gnd j19 ds1_data(31) k22 2.5v h17 ds1_addr(04) j20 ds1_data(18) k23 ds0_data(19) h18 gnd j21 ds1_data(16) k24 gnd h19 ds1_addr(06) j22 ds0_addr(09) k25 dmu_d(09) h20 2.5v j23 ds0_we k26 3.3v h21 ds0_data(07) j24 ds0_data(18) k27 dmu_d(21) h22 gnd j25 dmu_d(25) k28 gnd h23 ds0_addr(08) j26 dmu_d(24) k29 dmu_d(28) h24 v dd j27 dmu_d(23) k30 v dd k31 dmu_d(27) m01 dasl_out_b (2) n04 dasl_in_b(7) k32 gnd m02 2.5v n05 unused k33 dmu_d(26) m03 dasl_in_b (7) n06 unused l01 unused m04 gnd n07 unused l02 dasl_in_b(6) m05 unused n08 unused l03 dasl_in_b(6) m06 v dd n09 unused table 33: complete signal pin listing by grid position (page7of10) grid position signal name grid position signal name grid position signal name IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 88 of 444 np3_dl_sec02_phys.fm.01 09/25/00 l04 boot_ppc m07 pci_speed n10 unused l05 dasl_out_b(4) m08 gnd n11 vref2(7) l06 dasl_out_b (4) m09 unused n12 unused l07 dasl_out_b (5) m10 2.5v n13 v dd l08 unused m11 unused n14 d4_addr(11) l09 unused m12 gnd n15 d4_dqs(2) l10 vref2(8) m13 d4_addr(10) n16 d4_data(15) l11 unused m14 2.5v n17 ds1_addr(00) l12 sch_data(04) m15 d4_dqs(3) n18 ds1_data(23) l13 d4_addr(05) m16 gnd n19 dc_cas l14 vref2(3) m17 d4_data(00) n20 ds0_addr(01) l15 d4_data(20) m18 gnd n21 v dd l16 d4_data(01) m19 ds0_addr(02) n22 unused l17 ds1_data(10) m20 2.5v n23 dmu_c(27) l18 ds1_data(09) m21 ds0_data(24) n24 dmu_c(26) l19 ds0_data(25) m22 gnd n25 dmu_c(25) l20 ds1_data(03) m23 dmu_c(16) n26 dmu_c(24) l21 vref2(5) m24 v dd n27 dmu_c(23) l22 ds0_data(31) m25 dmu_c(15) n28 dmu_c(22) l23 dmu_c(10) m26 gnd n29 dmu_c(21) l24 dmu_c(09) m27 dmu_c(14) n30 dmu_c(20) l25 dmu_c(08) m28 3.3v n31 dmu_c(19) l26 dmu_c(07) m29 dmu_c(13) n32 dmu_c(18) l27 dmu_c(06) m30 gnd n33 dmu_c(17) l28 dmu_c(05) m31 dmu_c(12) p01 dasl_out_b (0) l29 dmu_c(04) m32 v dd p02 gnd l30 dmu_c(03) m33 dmu_c(11) p03 dasl_out_b(3) l31 dmu_c(02) n01 dasl_out_b(1) p04 v dd l32 dmu_c(01) n02 dasl_out_b(2) p05 unused l33 dmu_c(00) n03 dasl_out_b (3) p06 gnd p07 unused r10 unused t13 unused p08 2.5v r11 unused t14 v dd p09 unused r12 unused t15 lu_data(24) p10 gnd r13 unused t16 gnd p11 unused r14 unused t17 v dd p12 2.5v r15 gnd t18 gnd p13 unused r16 unused t19 send_grant_b table 33: complete signal pin listing by grid position (page8of10) grid position signal name grid position signal name grid position signal name IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 89 of 444 p14 gnd r17 d4_data(14) t20 v dd p15 d4_data(28) r18 ds1_dqs(3) t21 res_data p16 v dd r19 gnd t22 gnd p17 gnd r20 mc_grant_b(0) t23 dmu_b(19) p18 v dd r21 switch_bna t24 3.3v p19 ds0_data(00) r22 dmu_b(18) t25 jtag_trst p20 gnd r23 dmu_b(13) t26 gnd p21 mc_grant_b(1) r24 dmu_b(12) t27 dmu_b(17) p22 3.3v r25 dmu_b(11) t28 v dd p23 dmu_b(02) r26 dmu_b(10) t29 dmu_b(16) p24 gnd r27 dmu_b(09) t30 gnd p25 dmu_b(01) r28 dmu_b(08) t31 dmu_b(15) p26 v dd r29 dmu_b(07) t32 3.3v p27 dmu_b(00) r30 dmu_b(06) t33 dmu_b(14) p28 gnd r31 dmu_b(05) u01 lu_data(30) p29 dmu_c(30) r32 dmu_b(04) u02 thermal_out p30 3.3v r33 dmu_b(03) u03 lu_data(35) p31 dmu_c(29) t01 spare_tst_rcvr(3) u04 thermal_in p32gnd t02v dd u05 spare_tst_rcvr(0) p33 dmu_c(28) t03 spare_tst_rcvr(8) u06 testmode(1) r01 unused t04 gnd u07 unused r02 dasl_out_b(0) t05 unused u08 lu_data(08) r03 dasl_out_b (1) t06 2.5v u09 unused r04 lu_addr(08) t07 lu_data(03) u10 lu_data(34) r05 lu_data(33) t08 gnd u11 unused r06 unused t09 lu_data(02) u12 lu_data(11) r07 lu_data(04) t10 v dd u13 lu_data(01) r08 lu_data(05) t11 unused u14 gnd r09 unused t12 gnd u15 lu_data(00) u16 v dd v19 mgrant_a(0) w22 jtag_tdi u17 gnd v20 v dd w23 dmu_a(13) u18 v dd v21 i_freeq_th w24 dmu_a(12) u19 mgrant_a(1) v22 gnd w25 dmu_a(11) u20 gnd v23 rx_lbyte(1) w26 dmu_a(10) u21 res_sync v24 v dd w27 dmu_a(09) u22 jtag_tms v25 dmu_b(20) w28 dmu_a(08) u23 rx_lbyte(0) v26 gnd w29 dmu_a(07) table 33: complete signal pin listing by grid position (page9of10) grid position signal name grid position signal name grid position signal name IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 90 of 444 np3_dl_sec02_phys.fm.01 09/25/00 u24 dmu_b(29) v27 dmu_a(02) w30 dmu_a(06) u25 dmu_b(28) v28 3.3v w31 dmu_a(05) u26 dmu_b(27) v29 dmu_a(01) w32 dmu_a(04) u27dmu_b(26) v30gnd w33dmu_a(03) u28 dmu_b(25) v31 dmu_a(00) y01 dasl_out_a(0) u29dmu_b(24) v32v dd y02 gnd u30 dmu_b(23) v33 dmu_b(30) y03 dasl_in_a (7) u31 dmu_b(22) w01 lu_data(20) y04 2.5v u32 dmu_b(21) w02 dasl_out_a (0) y05 lu_data(32) u33 spare_tst_rcvr(9) w03 dasl_out_a(1) y06 gnd v01 spare_tst_rcvr(6) w04 lu_data(13) y07 lu_data(17) v02 2.5v w05 lu_data(07) y08 v dd v03 spare_tst_rcvr(7) w06 lu_data(06) y09 lu_data(22) v04 gnd w07 lu_data(15) y10 gnd v05 testmode(0) w08 lu_data(16) y11 lu_addr(01) v06 v dd w09 lu_data(21) y12 2.5v v07 lu_data(09) w10 lu_data(25) y13 vref2(6) v08 gnd w11 lu_data(31) y14 gnd v09 lu_data(10) w12 lu_data(26) y15 d1_data(05) v10 2.5v w13 lu_data(19) y16 v dd v11 lu_data(14) w14 lu_data(27) y17 gnd v12 gnd w15 gnd y18 v dd v13 lu_data(18) w16 d1_addr(10) y19 d2_data(15) v14 v dd w17 d3_data(08) y20 gnd v15 lu_data(12) w18 d2_data(02) y21 mc_grant_a(0) v16 gnd w19 gnd y22 3.3v v17 v dd w20 send_grant_a y23 dmu_a(19) v18 gnd w21 mc_grant_a(1) y24 gnd y25 dmu_a(18) y28 gnd y31 dmu_a(15) y26 3.3v y29 dmu_a(16) y32 gnd y27 dmu_a(17) y30 v dd y33 dmu_a(14) table 33: complete signal pin listing by grid position (page 10 of 10) grid position signal name grid position signal name grid position signal name IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec02_phys.fm.01 09/25/00 physical description page 91 of 444 2.4ieee1149(jtag)compliance 2.4.1 statement of jtag compliance the np4gs3 is compliant with ieee standard 1149.1a. 2.4.2 jtag compliance mode compliance with ieee 1149.1a is enabled by applying a compliance-enable pattern to the compliance-enable inputs as shown in table 34 . 2.4.3 jtag implementation specifics all mandatory jtag public instructions are implemented in the np4gs3?s design. table 35 documents all implemented public instructions. table 34: jtag compliance-enable inputs compliance-enable inputs compliance-enable pattern testmode(1:0) ?10? spare_tst_rcvr(9) 1 spare_tst_rcvr(4) 1 spare_tst_rcvr(3) 1 spare_tst_rcvr(2) 1 note: to achieve reset of the jtag test logic, the jtag_trst input must be driven low when the compliance-enable pattern is applied. table 35: implemented jtag public instructions instruction name binary code 1 serial data reg connected to tdi/tdo i/o control source (driver data and driver enable) bypass 111 1111 bypass system, functional values clamp 111 1101 bypass jtag extest 111 1000 boundaryscan jtag highz 111 1010 bypass jtag, all drivers disabled sample/preload 111 1001 boundaryscan system, functional values 1. chip tdo output driver is only enabled during tap controller states shift_ir and shift_dr. IBM32NPR161EPXCAC133 ibm powernp preliminary physical description page 92 of 444 np3_dl_sec02_phys.fm.01 09/25/00 2.4.4 brief overview of jtag instructions instruction description bypass connects the bypass data register between the tdi and tdo pins. the bypass data register is a single shift-register stage that provides a minimum-length serial path between the tdi and tdo pins when no test operation of the device is required. bypass does not disturb the normal functional connection and control of the i/o pins. clamp causes all output pins to be driven from the corresponding jtag parallel boundary scan register. the sample/preload instruction is typically used to load the desired values into the parallel boundary scan register. since the clamp instruction causes the serial tdi/tdo path to be connected to the bypass data registers, scanning through the device is very fast when the clamp instruction is loaded. extest allows the jtag logic to control output pin values by connecting each output data and enable signal to its corresponding parallel boundary scan register. the desired controlling values for the output data and enable signals are shifted into the scan boundary scan register during the shiftdr state. the paral- lel boundary scan register is loaded from the scan boundary scan register during the updatedr state. the extest instruction also allows the jtag logic to sample input receiver and output enable values. the values are loaded into the scan boundary scan register during capturedr state. highz causes the jtag logic to tri-state all output drivers while connecting the bypass register in the serial tdi/tdo path. sample/preload allows the jtag logic to sample input pin values and load the parallel boundary scan register without disturbing the normal functional connection and control of the i/o pins. the sample phase of the instruction occurs in capturedr state, at which time the scan boundary scan register is loaded with the corresponding input receiver and output enable values. (note that for input pins that are connected to a common i/o, the scan boundary scan register only updates with a input receiver sample if the corre- sponding output driver of the common i/o is disabled; otherwise the scan register is updated with the output data signal. the desired controlling values for the output pins are shifted into the scan boundary scan register dur- ing the shiftdr state and loaded from the scan boundary scan register to the parallel boundary scan register during the updatedr state. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec03_pmm.fm.01 09/25/00 pmm overview page 93 of 444 3. pmm overview the physical mac multiplexer (pmm) unit interfaces with the network processor?s external ports in the ingress (i-pmm) and egress (e-pmm) directions. the pmm includes five data mover units (dmus a, b, c, d, and the wrap dmu). four dmus (a, b, c, and d) can each be independently configured as an ethernet mac or a pos mac. a complete set of performance statistics is kept on a per port basis in either mode. each dmu?s data throughput capability is 1 gbps in both the ingress and the egress directions. the wrap dmu is used as a wrap path to enable traffic generated by the np4gs3?s egress side to be sent up through the switch fabric through the ingress side. 3.1 ethernet overview a dmu configured in ethernet mode can support either one port of gigabit ethernet or ten ports of 10/100 ethernet. figure 25: ethernet mode on page 95 shows an np4gs3 with dmu-a and dmu-b configured as gigabit ethernet macs. when in gigabit mode, each dmu can be configured with either a gigabit media independent interface (gmii) or a tbi interface. dmu-c and dmu-d are shown configured in 10/100 megabit ethernet serial media independent interface (smii) mode. when in the smii mode, the single dmu mac time division multiplexes the ten ports. each of these four dmus can be configured in any of the ethernet opera- tion modes. timing diagrams for the smii, gmii, and tbi ethernet interfaces are shown below. figure 21: pmm overview w d c b ibm powernp ingress eds dmu a b c d pmm w egress eds dmu a IBM32NPR161EPXCAC133 ibm powernp preliminary pmm overview page 94 of 444 np3_dl_sec03_pmm.fm.01 09/25/00 figure 22: smii timing diagram figure 23: gmii timing diagrams clock sync rx crs rx_dv rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 crs tx_er tx_en txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 tx_er tx rx_clk rx_dv rxd<7:0> rx_er fcs preamble sfd receive tx_clk tx_en txd<7:0> tx_er fcs preamble transmit IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec03_pmm.fm.01 09/25/00 pmm overview page 95 of 444 figure 24: tbi timing diagrams figure 25: ethernet mode tr i tx_clk tx_en txd[7:0] tx_er fcs preamble tx code group i=idle s=startofpacket d=data t = end of packet (part 1) r=endofpacket(part2or3) isd d dd ddddd dd ddd rx_clk1 2.0 v rx_code_group[9:0] 1.4 v 0.8 v rx_clk0 t hold comma code-group valid data t setup t hold t setup receive clocks and receive data transmit data dmu - a ibm powernp phy gmii or tbi 1 gigabit ethernet port dmu - b phy 1 gigabit ethernet port dmu - c phy dmu - d phy smii smii up to ten 10/100 ports up to ten 10/100 ports gmii or tbi IBM32NPR161EPXCAC133 ibm powernp preliminary pmm overview page 96 of 444 np3_dl_sec03_pmm.fm.01 09/25/00 figure 25: ethernet mode on page 95 shows an example of ethernet configuration of the dmus. any of the four dmus can be configured in gigabit ethernet or ten 10/100 ports. table 36: ingress ethernet counters on page 97 and table 37: egress ethernet counters on page 99 show the statistics counters kept in each dmu when it operates in ethernet mode. these counters are accessible through the cab interface. (for information on cab addresses, refer to the ibm powernp np4gs3 hard- ware reference manual, sections 3 and 6.) figure 26: gmii pos mode timing diagram rx_data receive valid byte tx_data transmit byte credit valid skip byte do not send ok to send valid valid valid do not send ok to send ok to send transmit valid byte IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec03_pmm.fm.01 09/25/00 pmm overview page 97 of 444 table 36: ingress ethernet counters name / group counter no. group description notes short frames x?00? 4 total number of frames received that were less than 64 octets long and were otherwise well formed (had a good crc). 1, 2 fragments x?01? total number of frames received that were less than 64 octets long and had a bad crc. 1, 2 frames received (64 octets) x?02? total number of frames (including bad frames) received that were 64 octets in length. 1, 2 frames received (65to127octets) x?03? total number of frames (including bad frames) received that were between 65 and 127 octets in length inclusive. 1, 2 frames received (128 to 255 octets) x?04? total number of frames (including bad frames) received that were between 128 and 255 octets in length inclusive. 1, 2 frames received (256 to 511 octets) x?05? total number of frames (including bad frames) received that were between 256 and 511 octets in length inclusive. 1, 2 frames received (512 to 1023 octets) x?06? total number of frames (including bad frames) received that were between 512 and 1023 octets in length inclusive. 1, 2 frames received (1024to1518octets) x?07? total number of frames (including bad frames) received that were between 1024 and 1518 octets in length inclusive. 1, 2 jumbo frames x?14? total number of frames (including bad frames) received with a length between 1519 and 9018 octets, or between 1519 and 9022 octets if vlan is asserted. if jumbo is not asserted the frame is a long frame. long frames received x?08? total number of long frames received with a good crc that were either: 1) longer than 1518 octets (excluding framing bits, but including crc octets), and were otherwise well formed (good crc), vlan and jumbo deasserted. 2) vlan frames that were longer than 1522 octets, with jumbo deasserted, 3) jumbo frames that were longer than 9018 octets, with vlan deasserted 4) jumbo vlan frames that were longer than 9022 octets. 3 jabber x?09? total number of long frames received with bad crc that were either: 1) longer than 1518 octets (excluding framing bits, but including crc octets), and were not well formed (bad crc), vlan and jumbo not asserted, 2) vlan frames that were longer than 1522 octets, with jumbo deasserted, 3) jumbo frames that were longer than 9018 octets, with vlan deasserted 4) jumbo vlan frames that were longer than 9022 octets. 3 frames with bad crc x?0a? 3 total number of frames received that were not long frames, but had bad crc. 2 unicast frames received x?0b? total number of good frames received that were directed to the unicast address (excluding multicast frames, broadcast frames, or long frames). broadcast frames received x?0c? total number of good frames received that were directed to the broadcast address (excluding multicast frames or long frames). multicast frames received x?0d? total number of good frames received that were directed to the multicast address (excluding broadcast frames, or long frames). 1. the states of vlan or jumbo have no effect on this count. 2. excluding framing bits but including crc octets 3. reception of frames meeting the criteria for this counter are aborted by the hardware. abort is indicated in the ingress port control block and in the ingress frame control block. if the frame has not been forwarded by the picocode, the picocode must enqueue the frame to the ingress discard queue. if the frame has been forwarded, then the egress hardware will discard the frame. at the mac further reception is inhibited until the next frame starts. IBM32NPR161EPXCAC133 ibm powernp preliminary pmm overview page 98 of 444 np3_dl_sec03_pmm.fm.01 09/25/00 total frames received x?0e? 2 total number of frames (including bad frames, broadcast frames, multicast frames, unicast frames, and long frames) received. receive errors x?0f? total number of frames received in which the phy detected an error and asserted the rx_err signal. overruns x?13? total number of frames received when the pmm internal buffer was full and the frame couldn?t be stored. includes frames in the process of being received when the pmm internal buffer becomes full. pause frames x?10? total number of mac pause frames received that were well formed and had a good crc. total pause time x?11? 1 total amount of time spent in a pause condition as a result of receiving a good pause mac frame. total octets received x?12? 0 total number of octets of data (including those in bad frames) received on the network. 2 table 36: ingress ethernet counters (continued) name / group counter no. group description notes 1. the states of vlan or jumbo have no effect on this count. 2. excluding framing bits but including crc octets 3. reception of frames meeting the criteria for this counter are aborted by the hardware. abort is indicated in the ingress port control block and in the ingress frame control block. if the frame has not been forwarded by the picocode, the picocode must enqueue the frame to the ingress discard queue. if the frame has been forwarded, then the egress hardware will discard the frame. at the mac further reception is inhibited until the next frame starts. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec03_pmm.fm.01 09/25/00 pmm overview page 99 of 444 table 37: egress ethernet counters name counter no. group description cnt short frames x?00? 4 total number of frames transmitted with less than 64 octets that had good crc. 1, 2 runt frames (bad crc) x?01? total number of frames transmitted with less than 64 octets that had bad crc. 1, 2 frames transmitted (64 octets) x?02? total number of frames (including bad frames) transmitted that were 64 octets in length. 1 frames transmitted (65to127octets) x?03? total number of frames (including bad frames) transmitted that were between 65 and 127 octets in length inclusive. 1, 3 frames transmitted (128 to 255 octets) x?04? total number of frames (including bad frames) transmitted that were between 128 and 255 octets in length inclusive 1, 3 frames transmitted (256 to 511 octets) x?05? total number of frames (including bad frames) transmitted that were between 256 and 511 octets in length inclusive. 1, 3 frames transmitted (512 to 1023 octets) x?06? total number of frames (including bad frames) transmitted that were between 512 and 1023 octets in length inclusive. 1, 3 frames transmitted (1024to1518octets) x?07? total number of frames (including bad frames) transmitted that were between 1024 and 1518 octets in length inclusive. 1, 3 jumbo frames x?16? total number of frames (including bad frames) transmitted with a length between 1519 and 9018 octets, or between 1523 and 9022 if vlan is asserted. if jumbo is not asserted, the frame is a long frame. long frames transmitted x?08? total number of frames with good crc transmitted that were either: 1) longer than 1518 octets (excluding framing bits, but including crc octets), and were otherwise well formed (good crc), vlan and jumbo are deasserted. 2) vlan frames that were longer than 1522 octets with jumbo deasserted, 3) jumbo frames that were longer than 9018 octets with jumbo deasserted 4) jumbo vlan frames that were longer than 9022 octets. jabber x?09? total number of frames with bad crc transmitted that were either: 1) longer than 1518 octets (excluding framing bits, but including crc octets), and were otherwise well formed (good crc), vlan and jumbo are deasserted. 2) vlan frames that were longer than 1522 octets with jumbo deasserted, 3) jumbo frames that were longer than 9018 octets with jumbo deasserted 4) jumbo vlan frames that were longer than 9022 octets. late collisions x?0a? total number of frames transmitted that experienced a network collision after 64 bytes of the frame had been transmitted. 1 1. the states of vlan or jumbo have no effect on this count. 2. including the frame type byte. 3. excluding framing bits but including crc octets. IBM32NPR161EPXCAC133 ibm powernp preliminary pmm overview page 100 of 444 np3_dl_sec03_pmm.fm.01 09/25/00 total collisions x?0b? 3 best estimate of the total number of collisions on this ethernet segment. 1 single collisions x?0c? total number of frames transmitted that experienced one collision before 64 bytes of the frame were transmitted on the network. 1 multiple collisions x?0d? total number of frames transmitted that experienced more than one col- lision before 64 bytes of the frame were transmitted on the network. 1 excessive deferrals x?0e? total number of frames whose transmission could not be started before the deferral time out expired. the deferral time out value is 24,416 media bit times. 1 underruns x?0f? total number of frames that were not completely transmitted because the data could not be obtained from the egress eds fast enough to maintain the media data rate. aborted frames x?17? total number of frames that had link status pointer parity errors and were aborted by the egress pmm. crc error x?10? 2 total number of frames transmitted that had a legal length (excluding framing bit, but including crc octets) of between 64 and 9018 octets, (64 and 9022 for vlan frames) inclusive, but had a bad crc. excessive collisions x?11? total number of frames that experienced more than 16 collisions during transmit attempts. these frames are dropped and not transmitted. unicast frames transmitted x?12? total number of good frames transmitted that were directed to the uni- cast address (not including multicast frames or broadcast frames). broadcast frames transmitted x?13? total number of good frames transmitted that were directed to the broadcast address (not including multicast frames). multicast frames transmitted x?14? total number of good frames transmitted that were directed to the multi- cast address (not including broadcast frames). total octets transmitted x?15? 0 total number of octets of data (including those in bad frames) transmit- tedonthenetwork. 3 table 37: egress ethernet counters (continued) name counter no. group description cnt 1. the states of vlan or jumbo have no effect on this count. 2. including the frame type byte. 3. excluding framing bits but including crc octets. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec03_pmm.fm.01 09/25/00 pmm overview page 101 of 444 table 38: ethernet support feature ethernet mode 10/100 mac 1000 mbps mac 1000 mbps physical coding sublayer fully compatible with ieee standard 802.3: 1993 (e) x 802.3u / d5.3 x 802.3z/d4 standards x 802.3 clause 36 (tbi) standards x compliant with rfc 1757 management registers and counters (tx/rx counters) additional receive counters for total number of pause frames and total aggregate pause time additional transmit counters for number of single collisions and number of multiple collisions xx supports the ieee standards on flow control by honoring received pause frames and inhibiting frame transmission while maintaining pause counter statistics xx supports the serial medium independent interface (smii) to the phy interfaces with up to ten phys that support the smii interface. each of the ten interfaces can have a bit rate of either 10 mbps or 100 mbps x capable of handling ten ports of 10 mbps or 100 mbps media speeds, any speed mix x supports half duplex operations at media speed on all ports x supports binary exponential back-off (beb) compliant with the ieee std. 802.3: 1993 (e) x supports full duplex point-to-point operations at media speed. x x detects vlan (8100 frame type) ethernet frames and accounts for them when calculating long frames xx supports two ethernet frame types (programmable) and, based on these, detects received frames with a type field that matches one of those types. a match instructs the multi-port 10/100 mac to strip the da, sa, and type fields from the received frame and to instruct the higher chip functions to queue the frame in a different queue. an example of a special function is to identify ethernet encapsulated guided frames. a mismatch results in normal frame queueing and normal higher chip processing. xx programmable cyclic redundancy check (crc) insertion on a frame basis with crc insertion disabled, mac transmits frames as is (suitable for switch environments) with crc insertion enabled, the mac calculates and inserts the crc x includes jumbo frame support. when configured, can transmit and receive up to 9018-byte non- vlan frames or up to 9022-byte vlan frames xx transfers received data to the upper chip layers using a proprietary 16-byte wide interface. in the transmit direction, data from the data mover is sent to the mac on a single 8-bit bus. xx supports the gigabit medium independent interface (gmii) to the physical tbi layer x supports the ibm tbi ?valid byte? signal x can be combined with the tbi to form a complete tbi solution x interfaces with any pma/pmi physical layer using the pma service interface defined in the ieee 802.3 standard x synchronizes the data received from the pma (two phase) clock with the mac (single phase) clock. provides a signal to the mac indicating those clock cycles that contain new data. x checks the received code groups (10 bits) for commas and establishes word synchronization x calculates and checks the tbi running disparity x supports auto-negotiation including two next pages x interfaces with the 1000 mbps ethernet mac through the gmii to form a complete tbi solution x IBM32NPR161EPXCAC133 ibm powernp preliminary pmm overview page 102 of 444 np3_dl_sec03_pmm.fm.01 09/25/00 3.2 pos overview each of the four 8-bit dmus supports packet over sonet (pos) and allows connection to oc-3c, oc-12, or oc-12c framers. to provide an oc-48 link, all four dmus can be attached to a single framer, with four differ- ent 8 bit oc-12c channels, or to four different oc-12c framers. to provide an oc-48c link, dmu-a can be configured to attach to a 32-bit framer and the other three dmus, although configured for oc-48 mode, are disabled, except for their interface pins. figure 32 is an example of an oc-3c/12/12c configuration, in which each of the four dmus can be configured to operate in either a single port mode or in a multi-port mode servicing four ports. each of the four dmus supports an 8-bit data interface in both the ingress and egress directions. 3.2.1 pos counters the following tables provide information about the counters maintained to support pos interfaces. 3.2.1.1 long frames a long frame is defined as a packet whose byte count exceeds the value held in the packet over sonet maximum frame size (pos_max_fs) register (see ibm powernp configuration on page 339), the byte count includes the crc octets. reception of packets meeting the criteria for long frames are aborted by the hardware. abort is indicated in the ingress port control block and in the ingress frame control block. if the packet has not been forwarded by the picocode, the picocode must enqueue the packet to the ingress discard queue. if the packet has been forwarded, then the egress hardware will discard the frame. at the mac, further reception is inhibited until the next packet starts. table 39: receive counter ram addresses for ingress pos mac port name counter number description port 0 long frames received x?00? total number of long frames received with a good crc that were longer than the value contained in the pos maximum frame size register (pos_max_fs) including crc octets. frames with bad crc x?01? total number of frames received that had a length of the value contained in the pos maximum frame size register (pos_max_fs) or less, but had a bad crc. total good frames received x?02? total number of frames (excluding frames with bad crc, and long frames) received. receive errors x?03? total number of frames received in which the framer detected an error and asserted the rx_err signal. total octets received (including frames with errors) x?10? total number of octets of data (including those in bad frames) received on the network. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec03_pmm.fm.01 09/25/00 pmm overview page 103 of 444 port 1 long frames received x?04? total number of long frames received with a good crc that were longer than the value contained in the pos maximum frame size register (pos_max_fs) including crc octets. frames with bad crc x?05? total number of frames received that had a length of the value contained in the pos maximum frame size register (pos_max_fs) or less, but had a bad crc. total good frames received x?06? total number of frames (excluding frames with a bad crc, and long frames) received. receive errors x?07? total number of frames received in which the framer detected an error and asserted the rx_err signal. total octets received (including frames with errors) x?11? total number of octets of data (including those in bad frames) received on the network. port 2 long frames received x?08? total number of long frames received with a good crc that were longer than the value contained in the pos maximum frame reg- ister (pos_max_fs) including crc octets. frames with bad crc x?09? total number of frames received that had a length of the value contained in the pos maximum frame size register (pos_max_fs) or less, but had a bad crc. total good frames received x?0a? total number of frames (excluding frames with a bad crc, and long frames) received. receive errors x?0b? total number of frames received in which the framer detected an error and asserted the rxerr signal. total octets received (including frames with errors) x?12? total number of octets of data (including those in bad frames) received on the network. port 3 long frames received x?0c? total number of long frames received with a good crc that were longer than the value contained in the pos maximum frame reg- ister (pos_max_fs) including crc octets. frames with bad crc x?0d? total number of frames received that had a length of the value contained in the pos maximum frame size register (pos_max_fs) or less, but had a bad crc. total good frames received x?0e? total number of frames (excluding frames with a bad crc, and long frames) received. receive errors x?0f? total number of frames received in which the framer detected an error and asserted the rx_err signal. total octets received (including frames with errors) x?13? total number of octets of data (including those in bad frames) received on the network. table 39: receive counter ram addresses for ingress pos mac (continued) port name counter number description IBM32NPR161EPXCAC133 ibm powernp preliminary pmm overview page 104 of 444 np3_dl_sec03_pmm.fm.01 09/25/00 table 40: transmit counter ram addresses for egress pos mac port name counter number description port 0 long frames transmitted x?00? total number of long frames transmitted with a good crc that were longer than the value contained in the pos maximum frame register (pos_max_fs) including crc octets. frames with bad crc x?01? total number of frames transmitted that had a length of the value contained in the pos maximum frame register (pos_max_fs) or less, but had bad crc. total good frames transmitted x?02? total number of frames (excluding frames with a bad crc, and long frames) transmitted. transmit underruns x?03? total number of frames attempted to be transmitted but an under- runoccurredinthenp4gs3. total octets transmitted (including frames with errors) x?10? total number of octets of data (including those in bad frames) transmitted on the network. aborted frames x?14? total number of frames that had link status pointer parity errors and were aborted by the egress pmm. port 1 long frames received x?04? total number of long frames transmitted with a good crc that were longer than the value contained in the pos maximum frame register (pos_max_fs) including crc octets. frames with bad crc x?05? total number of frames transmitted that had a length of the value contained in the pos maximum frame register (pos_max_fs) or less, but had bad crc. total good frames transmitted x?06? total number of frames (excluding frames with a bad crc, and long frames) transmitted. transmit underruns x?07? total number of frames attempted to be transmitted but an under- runoccurredinthenp4gs3. total octets transmitted (including frames with errors) x?11? total number of octets of data (including those in bad frames) transmitted on the network. aborted frames x?15? total number of frames that had link status pointer parity errors and were aborted by the egress pmm. port 2 long frames transmitted x?08? total number of long frames transmitted with a good crc that were longer than the value contained in the pos maximum frame register (pos_max_fs) including crc octets. frames with bad crc x?09? total number of frames transmitted that had a length of the value contained in the pos maximum frame register (pos_max_fs) or less, but had bad crc. total good frames transmitted x?0a? total number of frames (excluding frames with a bad crc, and long frames) transmitted. transmit underruns x?0b? total number of frames attempted to be transmitted but an under- runoccurredinthenp4gs3. total octets transmitted (including frames with errors) x?12? total number of octets of data (including those in bad frames) transmitted on the network. aborted frames x?16? total number of frames that had link status pointer parity errors and were aborted by the egress pmm. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec03_pmm.fm.01 09/25/00 pmm overview page 105 of 444 port 3 long frames transmitted x?0c? total number of long frames transmitted with a good crc that were longer than the value contained in the pos maximum frame register (pos_max_fs) including crc octets. frames with bad crc x?0d? total number of frames transmitted that had a length of the value contained in the pos maximum frame register (pos_max_fs) or less, but had bad crc. total good frames transmitted x?0e? total number of frames (excluding frames with a bad crc, and long frames) transmitted. transmit underruns x?0f? total number of frames attempted to be transmitted but an under- runoccurredinthenp4gs3. total octets transmitted (including frames with errors) x?13? total number of octets of data (including those in bad frames) transmitted on the network. aborted frames x?17? total number of frames that had link status pointer parity errors and were aborted by the egress pmm. figure 27: receive pos8 interface timing for 8-bit data bus (oc-3c, oc-12, oc-12c, and oc-48). table 40: transmit counter ram addresses for egress pos mac (continued) port name counter number description rxclk rxeof rxval rxdata rxenb rxaddr rxpfa 1 2 3 4 5 6 7 8 9 101112131415161718 1920 0 p 1 p 2 p 3 p 0 p 1 p 1 dp 1 dp 1 dp 1 dp 1 dp 2 dp 2 dp 2 dp 2 dp 2 dp 2 xx dp 2 p 2 p 3 p 0 p 1 p 2 p 3 p 0 p 1 p 2 p 3 p 0 receiving data from port 2 selecting port 1 port 1 data transfer with eof p 1 p 2 p 3 p 0 xx xx xx xx xx xx xx selecting port 2 21 dp 2 xx xx IBM32NPR161EPXCAC133 ibm powernp preliminary pmm overview page 106 of 444 np3_dl_sec03_pmm.fm.01 09/25/00 figure 28: receive pos32 interface timing for 32-bit data bus (oc-48c). figure 29: transmit pos8 interface timing for 8-bit data bus (oc-3c, oc-12) rxclk rxeof rxval rxdata rxenb rxpadl rxpfa 1 2 3 4 5 6 7 8 9 10 1112131415161718 1920 0 00 00 word word word word word word word word word word 0 000020 0000 receiving data 0100 xxxx xxxx xxxx xxxx xxxx xxxx xxxx selecting port framer has data last transfer contains only two data bytes xxxx xxxx word word 00 receiving data txaddr p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 txclk txsof txeof txdata txenb txaddr txpfa 1 2 3 4 5 6 7 8 9 1011121314151617181920 0 p 1 p 2 p 3 p 0 p 1 p 1 dp 1 dp 1 dp 1 dp 1 xx xx xx xx xx dp 1 xx p 3 p 0 p 1 p 2 p 3 p 0 p 1 p 2 p 3 p 0 p 1 transmitting data to port 1 polling selecting port 1 port 1 data transfer with eof p 2 p 2 p 0 p 1 xx xx xx xx xx xx polling selecting port 2 dp 1 dp 1 dp 2 dp 2 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec03_pmm.fm.01 09/25/00 pmm overview page 107 of 444 figure 30: transmit pos8 interface timing for 8-bit data bus (oc-12c, oc-48) figure 31: transmit pos32 interface timing for 32-bit data bus (oc-48c). txclk txsof txeof txdata txenb txaddr txpfa p 0 p 0 p 0 p 0 p 0 p 0 dp 0 dp 0 dp 0 dp 0 xx xx xx xx xx dp 0 xx p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 transmitting data to port 0 port 0 data transfer with eof p 0 p 0 p 0 p 0 xx xx xx xx xx xx selecting port 0 dp 0 dp 0 dp 0 dp 0 selecting port 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 0 txclk txsof txeof txdata txenb txpadl txpfa 00 00 word word word word word word word word word word 0 000002 0000 transmitting data 0000 word xxxx xxxx xxxx xxxx xxxx xxxx selecting port framer fifo not full last transfer contains only two data bytes word word word word 00 transmitting data 1 2 3 4 5 6 7 8 9 1011121314151617181920 0 IBM32NPR161EPXCAC133 ibm powernp preliminary pmm overview page 108 of 444 np3_dl_sec03_pmm.fm.01 09/25/00 figure 33 is an example of an oc-48 configuration in which each dmu is configured to operate in a single port mode to support oc-48. each dmu supports an 8-bit data interface in both the ingress and egress direc- tions. figure 34 is an example of an oc-48c configuration in which dmu-a is configured to operate in a single port 32-bit mode to support oc-48c. except for the i/os, dmus b, c, and d are not used in this configuration, although they must be configured for oc-48 mode and their data ports routed to dmu-a. the attached framer must also be configured for a 32-bit data interface. figure 32: oc-3c/12/12c configuration figure 33: oc-48 configuration framer framer framer framer 4xoc-3c connections oc-12c oc-12 4xoc-3c connections 4ports dmu - a ibm powernp dmu - b dmu - c dmu - d 4ports 4ports 1port connection connection framer oc-48 connection 1port dmu - a ibm powernp dmu - b dmu - c dmu - d 1port 1port 1port IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec03_pmm.fm.01 09/25/00 pmm overview page 109 of 444 figure 34: oc-48c configuration table 41: pos support feature pos mode 8-bit 32-bit supports quad port oc-3c connections, quad port oc-12 connections, or single port oc-12c connections x supports a single port oc-48c connection x compatible with two vendor proprietary 8-bit pos implementations; also compatible with 16-bit pos implementation using external logic x compatible with one vendor proprietary 32-bit pos implementations x programmablecrcinsertiononaframebasis. with crc insertion disabled, the mac transmits frames as is (suitable for switch environments) with crc insertion enabled, the mac calculates and inserts the crc xx the minimum frame length the np4gs3 can handle at a sustainable rate is 18 bytes. smaller frames can be handled, but will consume the bandwidth of an 18-byte frame. an indirect back-pressure between the proces- sor and the framer prevents frames from being lost, unless many small frames are received back-to-back. xx provides the following nine tx counters for testing and debugging purposes: number of bytes transmitted / received number of frames transmitted / received number of long frames transmitted / received number of frames with bad crc transmitted / received number of receive errors xx dmu - a dmu - b dmu - c framer oc-48c connection 1port ibm powernp dmu - d IBM32NPR161EPXCAC133 ibm powernp preliminary pmm overview page 110 of 444 np3_dl_sec03_pmm.fm.01 09/25/00 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec04_ieds.fm.01 09/25/00 ingress enqueuer / dequeuer / scheduler page 111 of 444 4. ingress enqueuer / dequeuer / scheduler 4.1 overview the ingress enqueuer / dequeuer / scheduler (ingress-eds) has interfaces with the pmm, the epc, and the ingress switch interface. frames that have been received by the media are passed through the pmm to the ingress eds. the ingress eds collects the frame data in its internal data store; when sufficient data has been received the frame is enqueued for processing to the epc. once the frame is processed by the epc, forwarding and qos information is provided to the ingress eds. hardware configured flow control mechanisms are invoked and the frame is then either discarded or placed into a queue to wait for transmission. the ingress eds schedules all frames that cross the switch interface. when a frame has been selected, the frame data is passed to the ingress switch interface where the frame is segmented into data cells and sent on the dasl interface. figure 35: logical organization of the data flow managed by the ingress eds ... uc round robin scheduler sof rings priority high unicast tb-run queues 01 62 63 multicast tb-run queues to switch fabric to any sof ring / from epc to epc frame demultiplexer from pmm fcb free queue bcb free queue gc queue gd queue discard tb-run queues output scheduler mc/discard scheduler tb# ... low high low high low high low high low IBM32NPR161EPXCAC133 ibm powernp preliminary ingress enqueuer / dequeuer / scheduler page 112 of 444 np3_dl_sec04_ieds.fm.01 09/25/00 4.2 ingress flow control 4.2.1 overview flow control (whether to forward or discard frames) in the network processor is provided by hardware assist mechanisms and by picocode that implements a selected flow control algorithm. in general, flow control algo- rithms require information about the congestion state of the data flow, the rate at which packets arrive, the current status of the data store, the current status of target blades, and so on. a transmit probability for vari- ous flows is an output of these algorithms. there are two implementations of flow control in the network processor: flow control that is invoked when the frame is enqueued to a sof queue. the hardware assist mecha- nisms use the transmit probability along with tail drop congestion indicators to determine if a forwarding or discard action should be taken during frame enqueue operation. the flow control hardware uses the pic- ocode?s entries in the ingress transmit probability memory to determine what flow control actions are required. flow control that is invoked when frame data enters the network processor. when the ingress data store is sufficiently congested, these flow control actions discard either all frames, all data frames, or new data frames. the thresholds that control the invocation of these actions are bcb_fq threshold for guided traffic, bcb_fq_threshold_0, and bcb_fq_threshold_1 (see table 42: list of flow control hardware facilities on page 113 for more information). 4.2.2 flow control hardware facilities the hardware facilities listed in table 42 are provided for the picocode's use when implementing a flow con- trol algorithm. the picocode uses the information from these facilities to create entries in the ingress transmit probability memory. the flow control hardware uses these entries when determining what flow control actions are required. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec04_ieds.fm.01 09/25/00 ingress enqueuer / dequeuer / scheduler page 113 of 444 table 42: list of flow control hardware facilities name definition access bcb free queue (bcb_fq) control block register provides an instantaneous count of the number of free buffers available in the ingress data store. cab bcb_fq threshold for guided traffic threshold for bcb_fq. when bcb_fq < bcb_fq_gt_th, no further buffers are allocated for incoming data. cab bcb_fq_threshold_0 threshold for bcb_fq. when bcb_fq < bcb_fq_threshold_0, then no further buffers are allocated for incoming user traffic. guided traffic can still allocate new buffers. when this threshold is violated, an interrupt (class 0, bit 0) is signaled. cab bcb_fq_threshold_1 threshold for bcb_fq. when bcb_fq < bcb_fq_threshold_1, then no further buffers are allocated for new incoming user traffic. guided traffic and packets already started can still allocate new buffers. when this threshold is violated, an interrupt (class 0, bit 1) is signaled. cab bcb_fq_threshold_2 bcb_fq < bcb_fq_threshold_2, an interrupt (class 0, bit 2) is signaled. cab flow control ingress free queue threshold (fq_p0_th) threshold for bcb_fq used when determining flow control actions against priority 0 traffic. when bcb_fq < fq_p0_th, the flow control hardware discards the frame. cab flow control ingress free queue threshold (fq_p1_th) threshold for bcb_fq used when determining flow control actions against priority 1 traffic. when bcb_fq < fq_p1_th, the flow control hardware discards the frame. cab bcb fq arrival count arrival rate of data into the ingress data store. this counter increments each time there is a dequeue from the bcb free queue. when read by pico- code, via the cab, this counter is set to 0 (read with reset). cab ingress free queue count exponentially weighted moving average calculated ewma of the bcb fq (bcb_fq_ewma). cab flow control ingress free queue threshold (fq_sbfq_th) threshold for bcb_fq. when bcb_fq < fq_sbfq_th, then the i_freeq_th is set to 1. this is may be used by external devices assisting in flow control. cab localtb_mc_status_0 threshold status of the priority 0 target dmu queues and the multicast queue. the status of the dmu_qcb.qcnt > dmu_qcb.th tests are com- bined into a single result per target blade and the corresponding bit in localtb_mc_status_0 is set. when the qcnt exceeds the threshold (th), the bit is set to 1; otherwise it is set to 0. hardware only target dmu queue control block (dmu_qcb) threshold for number of frames enqueued to the target dmu. these values are used to compare against the queue count when setting localtb_mc_status_0 bits. cab remote tb status 0 this 64-bit register contains the congestion status of all remote target blade's egress data stores. the congestion status of each remote target blade is the result of a comparison between the configured threshold and the ewma of the offered rate of priority 0 traffic (see table 50: list of flow control hardware facilities on page 136). this information is collected via the res_data io. hardware only remote tb status 1 this 64-bit register contains the congestion status of all remote target blade's egress data stores. the congestion status of each remote target blade is the result of a comparison between the configured threshold and the ewma of the offered rate of priority 1 traffic (see table 50: list of flow control hardware facilities on page 136). this information is collected via the res_data io. hardware only IBM32NPR161EPXCAC133 ibm powernp preliminary ingress enqueuer / dequeuer / scheduler page 114 of 444 np3_dl_sec04_ieds.fm.01 09/25/00 4.2.3 hardware function 4.2.3.1 exponentially weighted moving average (ewma) the hardware generates ewma values for the bcb_fq count, thus removing the burden of this calculation from the picocode. in general, ewma for a counter x is calculated as follows: ewma_x = (1-k) * ewma_x + k * x this calculation occurs for a configured sample period and k {1, 1/2, 1/4, 1/8}. 4.2.3.2 flow control hardware actions when the picocode enqueues a packet to be transmitted to a target blade, the flow control hardware exam- ines the state of the fq_p0_th and fq_p1_th threshold status and the priority of the enqueued packet to determine what flow control action is required. if the fcinfo field of the fcbpage of the enqueued packet is set to x'f', flow control is disabled and the packet is forwarded. for priority 0 packets, if fq_p0_th or localtb_mc_status_0 or remote tb status 0 is exceeded, then the packet will be discarded (tail drop discard). a counter block must be set up by the picocode to count these discards. for priority 1 packets, if fq_p1_th is exceeded, then the packet will be discarded (tail drop discard). otherwise the transmit probability table is accessed and the value obtained is compared against a ran- dom number ( { 0 .. 1} ) generated by the hardware. when the transmit probability is less than the ran- dom number, the packet is discarded. the index into the transmit probability table is qqqtcc where: qqq qos class taken from the dscp (ingress fcbpage tos field bits 7:5) t remote tb status 1 bit corresponding to the target blade. (zero when the frame is mul- ticast.) cc dscp assigned color (ingress fcbpage fcinfo field bits 1:0) IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec05_swi.fm.01 09/25/00 switch interface page 115 of 444 5. switch interface 5.1 overview the switch interface (swi) supports two high-speed dasl interfaces to attach to other network processors or to an external switch fabric. each dasl link supports up to 3.25 to 4 gbps throughput. the dasl links can be used in parallel (for example, to interconnect two network processors as dual network processors) or with one as the primary switch interface and the other as an alternate switch interface (for increased system avail- ability). the dasl interfaces enable up to 64 network processors to be interconnected using an external switch fabric. the swi supports the following: two dasl switch interfaces simultaneous transfer of cells on both switch interfaces in both ingress and egress directions building a cell header and frame header for each frame segmenting a frame into 64-byte switch cells cell packing the swi?s ingress side sends data to the switch fabric and its egress side receives data from the switch fab- ric. the dasl bus consists of four paralleled links: one master and three slaves. the network processor sup- ports two dasl channels (a and b). an arbiter sits between the ingress switch data mover (i-sdm) and ingress switch cell interfaces sci_a-1 and sci_b-1. the arbiter directs the data traffic from the i-sdm and probe to the appropriate i-sci, based on switch_bna chip input and the settings in the dasl configuration register (see 13.28.1 dasl configuration register (dasl_config) on page 400). figure 36 on page 116 shows the main functional units of the swi. IBM32NPR161EPXCAC133 ibm powernp preliminary switch interface page 116 of 444 np3_dl_sec05_swi.fm.01 09/25/00 the main units, described in following sections, are: i-sdm: ingress switch data mover i-sci: ingress switch cell interface dasl: data-aligned synchronous links e-sci: egress switch cell interface e-sdm: egress switch data mover figure 36: switch interface functional units switch fabric a i-sci a arb dasl tx dasl rx e-sci a e-sdm a switch interface - egress from ingress eds to egress eds (e-swi) switch interface - ingress (i-swi) dasl component a switch fabric b b b b i-sdm probe b sdc IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec05_swi.fm.01 09/25/00 switch interface page 117 of 444 5.2 ingress switch data mover (i-sdm) the i-sdm is the logical interface between the ingress enqueuer/dequeuer/scheduler?s (eds) frame data flow and the switch fabric?s cell data flow. the i-sdm segments the frames into cells and passes the cells to the i-sci. the ingress eds controls the i-sdm data input by requesting the i-sdm to transmit data to the switch. to do this, the ingress eds gives the i-sdm the control information necessary to transmit one segment (either 48 or 58 bytes) of data from the selected frame. the control information consists of a buffer control block (bcb) address, frame control block (fcb) record contents, and the bcb address of the next frame going to the same switch destination (used for packing). with this information, the i-sdm builds a switch cell under a quadword-aligned format compatible with the data structure in the egress data store. the logical switch cell structure contains three fields: cell header, frame header, and data. the first cell of a frame contains a cell header, a frame header, and 48 bytes of frame data. following cells of a frame contain a cell header followed by 58 bytes of frame data. the final cell of a frame contains the cell header, remaining bytes of frame data, and any necessary bytes to pad out the remainder of the cell. to increase the effective bandwidth to the switch, the network processor implements frame packing where the remaining bytes of a final cell contain the frame header and beginning bytes of the next frame. packing is used when the target blade and priority of the next frame are the same as the target blade and priority of the preceding frame. in this case, the packed cell contains a 6-byte cell header, the remaining data bytes of the first frame, a 10-byte frame header of the second frame, and some data bytes of the second frame. packing of frames occurs on 16-byte boundaries within a cell. 5.2.1 cell header this is a 6-byte field holding control information for the cell. the first 3 bytes are used by the switch fabric for routing and flow control. the last 3 bytes are used by the target network processor. the cell header is sent with each cell across the attached switch fabric. the fields of the cell header illustrated in figure 37 are described in table 43 . figure 37: cell header format msb byte 0 byte 1 byte 2 64-blade mode 16-blade mode byte 3 byte 4 byte 5 sb r r correlator qt endptr r r r qt st rlow (3:0) correlator endptr sb low (3:0) sb hi (5:4) st target blade ucnmc qualifier ucnmc lsb IBM32NPR161EPXCAC133 ibm powernp preliminary switch interface page 118 of 444 np3_dl_sec05_swi.fm.01 09/25/00 table 43: cell header fields field name definition qualifier this 8-bit field indicates the type of cell that is being transmitted. 7,2 cell format value. the type of cell format used for this cell. ?10? frame format ?11? packed frame format all other values are reserved. 6 switch cell header parity. this even parity bit covers the qualifier and the tb fields. when a parity error is detected, the cell is discarded and the event is counted. 5:4 data cell indicator. ?00? idle cell ?11? data cell all other values are reserved. 3 reserved. set to ?0?. 1:0 cell priority ?00? highest priority - used for port mirroring traffic ?01? high priority traffic ?10? low priority traffic ?11? reserved target blade target blade address (16-bit field). encoding of this field depends on the target blade mode. 16-blade the target blade field is a bit map of the destination target blades. target blade 0 corre- sponds to the msb of the target blade field. 64-blade valid unicast target blade field encodes are 0 through 63. multicast encodes are in the range of 512 through 65535. st frame state indicator (2-bit field). provides information about the status of the frame currently being car- ried in the cell. 00 continuation of current frame 01 end of current frame 10 start of new frame 11 start and end of new frame. this code point is also used to indicate a reassembly abort command. abort is indicated when the end pointer field value is ?0?. source blade (sb) source blade address. the size of this field depends on the blade operational mode and indicates the value of the source blade. correlator the size of this field depends on the blade operational mode. 16-blade correlator values 0-63 are used for unicast traffic. correlator values 0-31 are used for multi- cast traffic. 64-blade correlator values 0-15 are used for unicast traffic. correlator values 0-7 are used for multi- cast traffic. qt(1:0) queue type (2-bit field). used to determine the required handling of the cell and the frame. bits 1:0 description 0x user traffic that is enqueued into data queue. 1x guided traffic that is enqueued into the guided traffic queue. x0 cellmaybedroppedduetoswitchcongestion. x1 cell may not be dropped due to switch congestion. qt(1) is set by the hardware when fc info field of the frame header is set to x?f?. endptr end pointer (6-bit field). location of the last data byte in the cell when the state field indicates end of cur- rent frame (state = ?01? or ?11?). when an abort command is indicated (state must be ?11?), the end pointer is set to ?0?. in all other cases (state = ?00? or ?10?), this field contains sequence checking information used by the frame reassembly logic in the network processor. r reserved field, transmitted as ?0? . should not be modified or checked by the switch fabric. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec05_swi.fm.01 09/25/00 switch interface page 119 of 444 5.2.2 frame header this is a 10-byte field containing control information used by the target network processor and is sent once per frame. the fields of the frame header illustrated in figure 38 are described in table 44 . figure 38: frame header format table 44: frame header fields field name description uc unicast. this 1-bit field indicates the format of the frame header. ?0? multicast format. ?1? unicast format. fc info flow control information (4-bit field). indicates the type of connection used for this frame. connection type encoding is used by the network processor?s flow control mechanisms. lid lookup identifier. used by the egress processing to locate the necessary information to forward the frame to the appropriate target port with the correct qos. (1:0) lid blade 64 r r r r r r blade 16 byte 0 byte 1 byte 2 fhe(31:8) byte 6 byte 7 byte 8 fhe(7:0) byte 9 stake (7:6) mc uc mc uc mc uc (1:0) lid stake(5:0) stake(5:0) mid lid(20:2) sp sp byte 4 byte 5 byte 3 correlator with sb) (overwritten correlator with sb) (overwritten dsu dsu ucnmc fhf fhf fc info IBM32NPR161EPXCAC133 ibm powernp preliminary switch interface page 120 of 444 np3_dl_sec05_swi.fm.01 09/25/00 mid multicast identifier. used by the egress processing to locate the multicast tree information which is used to forward the frame to the appropriate target ports with the correct qos. stake available only for the multicast format of the frame header. this 8-bit field is used by egress processing to locate the start of the layer 3 header. dsu available only for the unicast format of the frame header. this 4-bit field indicates which egress data stores are used by this frame. defined as follows (where ?r? indicates a reserved bit that is transmitted as ?0? and is not modified or checked on receipt): 0rr0 data store 0 0rr1 data store 1 1rr0 data store 0 and data store 1 1rr1 data store 0 and data store 1 fhf frame header format. software controlled field. this field, with the addition of the uc field, is used by thehardwareclassifierintheepctodeterminethecodeentrypointfortheframe.theucfieldandthe fhf form a 5-bit index into a configurable lookup table of code entry points used for egress processing. sp source port of the frame. fhe frame header extension (32-bit field). used by ingress processing to pass information to egress pro- cessing. the contents of this field depend on the fhf value used by egress processing to interpret the field. information passed reduces the amount of frame parsing required by egress processing when determining how to forward the frame. correlator the size of this field depends on the blade operational mode. the sb information in the cell header is copied into the byte occupied by the correlator (overlaying the correlator and some reserved bits) when the frame header is written to the egress data store. this provides sb information for egress processing. 16-blade correlator values 0-63 are used for unicast traffic. correlator values 0-31 are used for multi- cast traffic. 64-blade correlator values 0-15 are used for unicast traffic. correlator values 0-7 are used for multicast traffic. table 44: frame header fields field name description IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec05_swi.fm.01 09/25/00 switch interface page 121 of 444 5.3 ingress switch cell interface (i-sci) the i-sci provides a continuous stream of transmit data to the dasl. after power on or reset of the network processor, the i-sci initialization process generates synchronization cells for the dasl. when the dasl is synchronized, the i-sci enters the operational state. when there are no data cells to send, the i-sci gener- ates idle cells for transmission via the dasl. when there are data cells to send, the i-sci receives a logical cell from the i-sdm, translates the cell into the switch cell format, and transmits the cell via the dasl. the i- sci performs formatting on the cell headers to conform with the switch cell format. the i-sci unit relies on an internal fifo of cells, written by the i-sdm at the network processor core clock rate, and read at the switch clock rate performing the translation from logical cell format to switch cell format. 5.3.1 idle cell format when there is no data to send, idle cells are transmitted on the switch interface. all bytes in an idle cell have the value x?cc?, except for the first 3 bytes in the master stream. word 0, word 1, and word 2 of the master stream contain h0, h1, and h2 respectively. . 5.3.1.1 crc bytes: word 15 the crc bytes sent on each byte stream contain an 8-bit crc checksum of the polynomial x 8 +x 4 +x 3 +x 2 +1. each byte stream is independently calculated and the initial value loaded into the crc generator at the end of each idle cell (after word 15) is x?d0?. the final crc value is calculated starting with the first byte following an idle cell up to (but not including) the byte sent as part of word 15 in the next idle cell. table 45: idle cell format transmitted to the switch interface word # slave 1 (byte 0) master (byte 1) slave 3 (byte 2) slave 2 (byte 3) (bits 31:24) (bits 23:16) (bits 15:8) (bits 7:0) w0 x?cc? h0 x?cc? x?cc? w1 x?cc? h1 (x?cc?) x?cc? x?cc? w2 x?cc? h2 (x?cc?) x?cc? x?cc? w3 x?cc? x?cc? x?cc? x?cc? w4 x?cc? x?cc? x?cc? x?cc? w5 x?cc? x?cc? x?cc? x?cc? w6 x?cc? x?cc? x?cc? x?cc? w7 x?cc? x?cc? x?cc? x?cc? w8 x?cc? x?cc? x?cc? x?cc? w9 x?cc? x?cc? x?cc? x?cc? w10 x?cc? x?cc? x?cc? x?cc? w11 x?cc? x?cc? x?cc? x?cc? w12 x?cc? x?cc? x?cc? x?cc? w13 x?cc? x?cc? x?cc? x?cc? w14 x?cc? x?cc? x?cc? x?cc? w15 crc crc crc crc IBM32NPR161EPXCAC133 ibm powernp preliminary switch interface page 122 of 444 np3_dl_sec05_swi.fm.01 09/25/00 5.3.1.2 i-sci transmit header for an idle cell the idle cell header consists of 3 bytes, h0-h2, and are defined as follows: h0: also referred to as the qualifier byte, this 8-bit field indicates the type of cell being transmitted. h1 and h2: set to x?cc?. figure 39: crc calculation example bit(s) definition 7 reserved. transmitted as ?0?. 6 switch cell header parity. this even parity bit covers the h0-h2 fields. 5:4 data cell indicator. ?00? idle cell ?11? data cell all other values are reserved. 3:2 reserved. transmitted as ?00?. 1:0 reserved. this field should not be examined by the switch. idle cell 0 15 data cell 0 15 data cell 0 15 idle cell 0 15 bytes in stream crc calculated on these bytes x?d0? initial value loaded 14 crc value stored in byte 15 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec05_swi.fm.01 09/25/00 switch interface page 123 of 444 5.4 switch data cell format - ingress and egress the table below shows the format of data cells sent to and from the switch interface via the data-aligned synchronous link bus. notice that the packet routing switch cell header bytes (h0, h1, and h2) are all con- tained in the master byte stream. bytes designated ch0 through ch5 are the cell header bytes described in figure 37: cell header format on page 117. table 46: switch data cell format word # slave 1 dasl_out_0 dasl_out_1 master dasl_out_2 dasl_out_3 slave 3 dasl_out_4 dasl_out_5 slave 2 dasl_out_6 dasl_out_7 (bits 31:24) (bits 23:16) (bits 15:8) (bits 7:0) w0 ch5 ch0 (h0) d9 d7 w1 d0 ch1 (h1) d4 d2 w2 d1 ch2 (h2) d5 d3 w3 ch4 ch3 d8 d6 w4 d25 d23 d21 d19 w5 d12 d10 d16 d14 w6 d13 d11 d17 d15 w7 d24 d22 d20 d18 w8 d41 d39 d37 d35 w9 d28 d26 d32 d30 w10 d29 d27 d33 d31 w11 d40 d38 d36 d34 w12 d57 d55 d53 d51 w13 d44 d42 d48 d46 w14 d45 d43 d49 d47 w15 d56 d54 d52 d50 1. dasl_out_x (where x {1,3,5,7}) carry the even bits of the indicated bytes 2. dasl_out_x (where x {0,2,4,6})carrytheoddbitsoftheindicatedbytes 3. dxx indicates the data byte in the cell from the sdm interface 4. chx indicates the cell header IBM32NPR161EPXCAC133 ibm powernp preliminary switch interface page 124 of 444 np3_dl_sec05_swi.fm.01 09/25/00 5.5 data-aligned synchronous link (dasl) the data-aligned synchronous link (dasl) interface is a macro that facilitates high speed point-to-point inter-chip communication. it provides the application designer the ability to relieve i/o constraints imposed by the chip package or card connector. the dasl interface performs multi-bit serialization and de-serialization to reduce the i/o pin count. the interface is frequency synchronous which removes the need for asynchro- nous interfaces that introduce additional interface latency. dasl links are intended to operate over a back- plane without any additional components. the dasl interface macro was developed to interface the core area of a cmos asic to a high speed link. the macro incorporates all the high-speed circuitry necessary to initialize and perform dynamic link timing and data serialization/de-serialization without exposing the core designer to the specific implementation. the core asic interface to dasl is a parallel interface. the dasl macro is scalable based on application needs. the dasl macro was designed for high levels of integration. it uses reduced voltage differential transceivers to reduce power consumption. the macro has been partitioned such that multiple sub-macros share a com- mon controller as well as a common phase locked loop (pll). on the most basic level, the dasl macro is designed to provide a 4 to 1 serialization/de-serialization inter- face. the np4gs3 application utilizes a 32- to 8-bit (32-bit port) pin reduction. the shared dasl controller (sdc) provides control for the dasl tx and dasl rx ports. 5.6 egress switch cell interface (e-sci) the e-sci receives cells from the switch fabric and passes data cells to the e-sdm. the e-sci discards idle cells received from the switch fabric, checks the parity of the received cells, and discards cells with bad parity. the e-sci strips out the target blade per-port grant information from the switch cells and sends this grant information to the network processor ingress units for use in ingress data flow control. the e-sci assists in egress data flow control by throttling the switch fabric to prevent data overruns. 5.6.1 output queue grant (oqg) reporting most fields in the cell header must pass through the switch fabric unchanged (idle cells are not transmitted through a switch fabric; they originate at the output port of the switch). the exception to this is the target blade field (see figure 37 ) which contains output queue grant (oqg) information used by the network pro- cessor's ingress eds when selecting data to be sent to the switch. a target port is not selected if its corre- sponding output queue grant information is set to ?0?. further, output queue grant information is sent for each of the three priorities supported by the network pro- cessor. this is done using multiple cell transfers; starting with priority 0, reporting output queue grant for all supported target blades, then repeating this process for each priority level until a value of 2 is reached, and starting over at priority 0 again. for 16-blade operational mode the sequence is: 1. priority 0; oqg for blades 0:15 (h1 contains 0:7, h2 contains 8:15) 2. priority 1; oqg for blades 0:15 (h1 contains 0:7, h2 contains 8:15) 3. priority 2; oqg for blades 0:15 (h1 contains 0:7, h2 contains 8:15) 4. start over at step 1. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec05_swi.fm.01 09/25/00 switch interface page 125 of 444 the idle cell indicates the priority of the oqg it carries. this allows the network processor to synchronize with the external switch. for 64-blade operational mode the sequence is: 1. priority 0; oqg for blades 0:15 (h1 contains 0:7, h2 contains 8:15) 2. priority 0; oqg for blades 16:31 (h1 contains 16:23, h2 contains 24:31) 3. priority 0; oqg for blades 32:47 (h1 contains 32:39, h2 contains 40:47) 4. priority 0; oqg for blades 48:63 (h1 contains 48:55, h2 contains 56:63) 5. priority 1; oqg for blades 0:15 (h1 contains 0:7, h2 contains 8:15) 6. priority 1; oqg for blades 16:31 (h1 contains 16:23, h2 contains 24:31) 7. priority 1; oqg for blades 32:47 (h1 contains 32:39, h2 contains 40:47) 8. priority 1; oqg for blades 48:63 (h1 contains 48:55, h2 contains 56:63) 9. priority 2; oqg for blades 0:15 (h1 contains 0:7, h2 contains 8:15) 10. priority 2; oqg for blades 16:31 (h1 contains 16:23, h2 contains 24:31) 11. priority 2; oqg for blades 32:47 (h1 contains 32:39, h2 contains 40:47) 12. priority 2; oqg for blades 48:63 (h1 contains 48:55, h2 contains 56:63) 13. start over at step 1. for 64-blade mode, this sequence is interrupted when an idle cell is sent. table 49 illustrates an idle cell that carries the oqg for all blades. status for each priority is given in increasing order; (p0 followed by p1 fol- lowed by p2). the network processor starts the above sequence at step 1 with the arrival of the next data cell. 5.6.2 switch fabric to network processor egress idle cell egress switch interface requires idle cells when there is no data. an idle cell requires: the last bytes on each stream contain a trailer crc. for the master stream, the header h0 as described in ta b l e 4 7 below. for the master stream, h1- h2 contain the target blade grant priority information when in 16-blade mode. for the master stream, h1-h2 contain x?cc? when in 64-blade mode. all other bytes contain x?cc? when in 16-blade mode or oqg (see table 48 on page 126) when in 64- blade mode. IBM32NPR161EPXCAC133 ibm powernp preliminary switch interface page 126 of 444 np3_dl_sec05_swi.fm.01 09/25/00 . table 47: receive cell header byte h0 for an idle cell bit(s) definition 7 reserved. transmitted as ?0?. 6 switch cell header parity. this even parity bit covers the h0-h2 fields. 5:4 data cell indicator. ?00? idle cell ?11? data cell all other values are reserved. 3:2 reserved. transmitted as ?00?. 1:0 output queue grant priority. when in 16-blade mode, indicates the priority level of the output queue grant information carried in h1-h2.otherwise the network processor ignores this field. table 48: idle cell format received from the switch interface - 16-blade mode slave 1 master 1 slave 3 slave 2 byte 0 byte 1 byte 2 byte 3 x?cc? h0 x?cc? x?cc? x?cc? h1 (oqg (0:7)) x?cc? x?cc? x?cc? h2 (oqg (8:15)) x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? x?cc? crc crc crc crc IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec05_swi.fm.01 09/25/00 switch interface page 127 of 444 5.6.3 receive header formats for sync cells sync cells are a special type of idle cells. they are similar to the received idle cell for 16-blade mode (see table 48 on page 126) but h0, h1, and h2 are set to a value of x?cc?. all sync cells are discarded. 5.7 egress switch data mover (e-sdm) the e-sdm is the logical interface between the switch cell data flow of the e-sci and the frame data flow of the egress eds. the e-sdm serves as a buffer for cells flowing from the e-sci to the egress eds. the e- sdm extracts control information, such as the frame correlator, which is passed to the egress eds. the egress eds uses this control information, along with data from the e-sdm, to re-assemble the cells into frames. table 49: idle cell format received from the switch interface - 64-blade mode slave1 master slave3 slave2 byte 0 byte 1 byte 2 byte 3 x?cc? h0 x?cc? x?cc? x?cc? h1 (x?cc?) x?cc? x?cc? x?cc? h2 (x?cc?) x?cc? x?cc? 01 0 1 232 3 454 5 676 7 898 9 10 11 10 11 12 13 12 13 14 15 14 15 16 17 16 17 18 19 18 19 20 21 20 21 22 23 22 23 24 25 24 25 26 27 26 27 28 29 28 29 30 31 30 31 32 33 32 33 34 35 34 35 36 37 36 37 38 39 38 39 40 41 40 41 42 43 42 43 44 45 44 45 46 47 46 47 48 49 48 49 50 51 50 51 52 53 52 53 54 55 54 55 56 57 56 57 58 59 58 59 60 61 60 61 62 63 62 63 01 0 1 232 3 454 5 676 7 898 9 10 11 10 11 12 13 12 13 14 15 14 15 16 17 16 17 18 19 18 19 20 21 20 21 22 23 22 23 24 25 24 25 26 27 26 27 28 29 28 29 30 31 30 31 32 33 32 33 34 35 34 35 36 37 36 37 38 39 38 39 40 41 40 41 42 43 42 43 44 45 44 45 46 47 46 47 48 49 48 49 50 51 50 51 52 53 52 53 54 55 54 55 56 57 56 57 58 59 58 59 60 61 60 61 62 63 62 63 01 0 1 232 3 454 5 676 7 898 9 10 11 10 11 12 13 12 13 14 15 14 15 16 17 16 17 18 19 18 19 20 21 20 21 22 23 22 23 24 25 24 25 26 27 26 27 28 29 28 29 30 31 30 31 32 33 32 33 34 35 34 35 36 37 36 37 38 39 38 39 40 41 40 41 42 43 42 43 44 45 44 45 46 47 46 47 48 49 48 49 50 51 50 51 52 53 52 53 54 55 54 55 56 57 56 57 58 59 58 59 60 61 60 61 62 63 62 63 crc crc crc crc IBM32NPR161EPXCAC133 ibm powernp preliminary switch interface page 128 of 444 np3_dl_sec05_swi.fm.01 09/25/00 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec06_eeds.fm.01 09/25/00 egress enqueuer / dequeuer / scheduler page 129 of 444 6. egress enqueuer / dequeuer / scheduler 6.1 overview the egress enqueuer / dequeuer / scheduler (egress eds) supports reassembly of frames sent from up to 64 network processors up to a total of 3072 simultaneous reassemblies. each switch cell received from the egress switch interface is examined and stored in the appropriate egress data store (egress ds) for reas- sembly into its original frame. when the frame is completely received from the switch interface, the egress eds enqueues the frame to the epc for processing. the epc processes the frame and then enqueues it to either the scheduler, when enabled, or to a target port (tp) queue for transmission out the egress pmm. the egress eds is responsible for handling all the buffer, frame, and queue management for reassembly and transmission on the egress side of the network processor. the egress eds supports the following: external egress data store automatic allocation of buffer and frame control blocks for each frame epc queues (gfq, gtq, gr0, gr1, gb0, gb1, and gpq) target port queues with two priorities buffer thresholds and flow control actions bandwidth and best effort scheduling reading and writing of frame data stored in egress data store up to 512 k buffer twins depending on memory configuration up to 512 k of fcbs depending on memory configuration unicast and multicast frames cell packing 40 external ports plus wrap port interface to the pmm discard function hardware initialization of internal and external data structures IBM32NPR161EPXCAC133 ibm powernp preliminary egress enqueuer / dequeuer / scheduler page 130 of 444 np3_dl_sec06_eeds.fm.01 09/25/00 6.1.1 egress eds components figure 40: egress eds block diagram see egress eds components for term definitions e data store interface writes the external egress data stores during frame reassembly and reads them during frame transmission. also gives the epc access to the egress data stores. the data store interface supports two external data stores: ds0 and ds1. dpq discard port queue. releases twin buffers back to the free queue stack. this is used by the picocode to discard frames where header twins have been allocated. e-gdq discard queue stack. holds frames that need to be discarded. this is used by the hardware to discard frames when the egress ds is congested or to re-walk a frame marked for discard for a half duplex port. used by the picocode to discard frames that do not have header twins allocated. egress pcb egress port control block. contains all the information needed to send a frame to the egress pmm for transmission. the egress eds uses this information to walk the twin buffer chain and send the data to the egress pmm?s output port. there is a pcb entry for each target port, plus one for discard and one for wrap. each entry holds information for two frames: the current frame being sent to the pmm port and the next frame to be sent. fcbfq frame control block free queue. lists free egress fcbs. fcbs store all the infor- mation needed to describe the frame on the egress side, such as starting buffer, length, mcc address, frame alteration, and other enqueue information. the egress eds obtains an fcb from the free queue when the epc enqueues the frame to either a flow qcb (see flow queues on page 144) or a target port after epc pro- cessing and flow control actions are complete. data store interface egress pcb rcb release logic mcc tables flow control wrapq dpq tp39q_p1 tp0q_po gb1 gb0 gr1 gr0 gtq gfq fqs egress pmm egress epc e-gdq swi ds gpq fcbfq scheduler IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec06_eeds.fm.01 09/25/00 egress enqueuer / dequeuer / scheduler page 131 of 444 fqs free queue stack. holds a list of free egress twin buffers which are used by the egress eds during frame reassembly and by the epc during frame alteration. the twin buffers store the frame data or frame alteration header twins and also contain the link pointer to the next buffer in the chain. the fqs is used to obtain a new free twin buffer any time the egress needs one and to return free twin buffers after frames are discarded or transmitted. gb0, gb1 low priority data queues. gb0 is for frames stored in egress ds0. gb1 is for frames stored in egress ds1. gfq guided frame queue. queue that contains guided frames for delivery for the egress side of the network processor to the guided frame handler. gpq powerpc queue. queue that contains frames re-enqueued for delivery to the gph for processing. gr0, gr1 high priority data queues. gr0 is for frames stored in egress ds0. gr1 is for frames stored in egress ds1. gtq general table queue. queue that contains guided frames re-enqueued by pico- code for delivery to the gth. mcc table multicast count table. each entry stores the number of multicast frames associ- ated with a particular set of twin buffers. if a frame is to be multicast to more than one target port, the epc enqueues the frame to each target port causing an entry in the mcc table to be incremented. as each target port finishes its copy of the frame, the mcc table entry is decremented. when all ports have sent their copies of the frame, the associated twin buffers are released. rcb reassembly control block. used by the egress eds to reassemble the cells received from the switch fabric into their original frames. contains pointers to the egress ds to specify where the contents of the current cell should be stored. helps the egress eds to keep track of the frame length and which epc queue to use. release logic releases twin buffers after the pmm has finished with the contents of the buffer. the release logic checks the mcc table to determine if the buffer can be released or is still needed for some other copy of a multicast frame. tp0q - tp39q target port queues. hold linked lists of frames destined for a target port. two queues are associated with each of the 40 possible target ports. these queues are prioritized from high (p0) to low (p1) using a strict priority service scheme (all higher priority queues within a target port set must be empty before starting a lower priority queue). wrapq wrap queue. two wrap queues, one for guided frames and one for data frames, send frames from the egress side to the ingress side of the network processor. these queues allow the network processor to respond to a guided frame sent from a remote control point function. the guided frame is received from the switch fab- ric on the egress side and is wrapped to the ingress side to allow a response to be sent to the cpf across the switch fabric. a data frame may be wrapped when pro- cessing on a remote cpf is required. IBM32NPR161EPXCAC133 ibm powernp preliminary egress enqueuer / dequeuer / scheduler page 132 of 444 np3_dl_sec06_eeds.fm.01 09/25/00 6.2 operation switch cells are received from the egress swi along with information that has been preprocessed by the egress sdm such as the reassembly correlator, source blade, multicast indication, priority, and target data store. in order to optimize the data transfer to and egress ds, the egress eds uses the target data store?s information to determine which egress sdm to service. the two egress dss, ds0 and ds1, use alternating write windows, meaning the egress eds can write one cell to one data store each "cell window time? (the time needed to store an entire switch cell (64 bytes) in external dram). cell window time is configured using the dram parameter register?s 11/10 field. after the appropriate egress sdm has been selected, the egress eds reads the cell data out of the sdm and uses the reassembly correlator, source blade, multicast indication, and priority information to index into the rcb. the rcb contains all the information needed to reassemble the frame, including the buffer address to use in the egress ds. the cell data is stored in the buffer and the rcb is updated to prepare for the next cell associated with this same frame. the egress eds manages 3072 rcb entries and each entry contains infor- mation such as start-of-frame indicator, data store buffer address, current reassembled frame length, and queue type. cells from several source blades are interleaved coming from the switch interface and the egress eds uses the rcb information to rebuild each frame. the egress eds uses a free buffer from the head of the fqs as needed to store frame data in the egress ds. the egress eds stores the cell data in the appropriate buffer and also stores the buffer chaining informa- tion over the cell header data. when a packed cell arrives, the egress eds stores each frame?s information in two separate twin buffers. the first portion of the packed cell contains the end of a frame. this data is stored in the appropriate twin buffer as pointed to by the rcb. the remaining portion of the packed cell will be the beginning of another frame and this data will be stored in a second twin buffer as indicated by the second frame?s rcb entry. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec06_eeds.fm.01 09/25/00 egress enqueuer / dequeuer / scheduler page 133 of 444 when the entire frame is reassembled, the egress eds enqueues the frame to one of several epc queues. if the reassembled frame is a guided frame, the egress eds uses the gfq. high priority frames are placed in either the gr0 or the gr1. low priority frames are placed in either the gb0 or the gb1. the epc services these queues and requests a programmable amount of read data from the various frames in order to process them (see table 126: port configuration memory index on page 200). the egress eds reads the data from the egress data store and passes it back to the epc. additional reads or writes can occur while the epc is processing the frame. the egress eds performs all necessary reads or writes to the egress data store as requested by the epc. figure 41: cell formats and storage in egress data store ch 1 (0:5) fh 1 (0:9) fd 1 (00:15) fd 1 (16:31) fd 1 (32:47) ch 1 (0:5) fh 1 (0:9) fd 1 (00:15) fd 1 (16:31) fd 1 (32:47) ch 1 (0:5) fd 1 (48:57) fd 1 (58:73) fd 1 (74:89) fd 1 (90:105) lp 1 (0:5) fd 1 (48:57) fd 1 (58:73) fd 1 (74:89) fd 1 (90:105) fqs fqs ch 2 (0:5) fd 2 (22:31) fd 2 (32:47) fd 2 (48:63) fd 2 (64:79) lp 2 (0:5) fd 2 (22:31) fd 2 (32:47) fd 2 (48:63) fd 2 (64:79) ch 1 (0:5) fd 1 (106:115) fd 1 (116:120) fh 2 (0:9) fd 2 (00:05) fd 2 (06:21) ch 1 (0:5) fd 1 (106:115) fd 1 (116:120) na (0:10) fh 2 (0:9) fd 2 (00:05) fd 2 (06:21) 128-byte linked twin buffers for frame 1 128-byte linked twin buffers for frame 2 non-packed start of frame cell non-packed continuation cell packed end of frame cell non-packed continuation cell ch = cell header fh = frame header fd = frame data lp = link pointer na = unused bytes data buffer data buffer twin buffer IBM32NPR161EPXCAC133 ibm powernp preliminary egress enqueuer / dequeuer / scheduler page 134 of 444 np3_dl_sec06_eeds.fm.01 09/25/00 when the frame has been processed, the epc enqueues the frame to the egress eds. if the frame?s destina- tion is the general table handler, the egress eds enqueues the frame to the gtq. if the frame is to be dis- carded, it is placed in the dpq. if the frame needs to be wrapped to the ingress side, it is placed in the wrap queue. all other frames are subject to flow control actions. if flow control does not discard the frame, the frame is placed into the scheduler, if enabled, or placed directly into a target port queue. each target port sup- ports two priorities and therefore has two queues. the epc indicates which target port and which priority should be used for each frame enqueued. the two queues per port use a strict priority scheme, which means that all high priority traffic must be transmitted before any lower priority traffic will be sent. frames destined for the scheduler, target ports, or wrap ports have a frame control block (fcb) assigned by the egress eds. the fcb holds all the information needed to transmit the frame including starting buffer address, frame length, and frame alteration information. if the epc needs to forward more than one copy of the frame to different target ports, an entry in the mcc table is used to indicate the total number of copies to send. the epc enqueues the frame to different target ports or different flow qcbs and each enqueue creates a new fcb with (possibly) its own unique frame alteration. figure 42: tpq, fcb, and egress frame example target port queues frame control blocks target port 5 target port 9 multicast frame last frame in target port queue 5 first frame in target port queue 9 unicast frame last frame in target port queue 9 unicast frame first frame in target port queue 5 hc=2t hc=2t fba fl = y fba fl = y fba fl = x fba fl = z h=head t=tail c = queue count fba = first buffer address fl = frame length buf = buffer lp = link pointer frame length =xbytes frame length =ybytes frame length =zbytes buf 32 buf 12 buf 3 buf 9 buf 7 buf 23 buf 15 buf 39 buf 99 lp = 9 lp=15 lp=23 lp=39 lp=99 lp = 7 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec06_eeds.fm.01 09/25/00 egress enqueuer / dequeuer / scheduler page 135 of 444 when a frame reaches the head of a target port queue, it is placed in the egress port control block entry (pcb) for that port and the fcb for that frame is placed on the fcb free queue. the egress eds uses the pcb to manage the frames that are being sent to the pmm for transmission. the pcb stores the information needed to retrieve frame data, such as current buffer address and frame length, from the egress ds. the pcb allows up to 40 frames to be retrieved simultaneously from the egress ds. the pcb also supports the wrap port and the discard port queue. as data is retrieved from the egress ds and passed to the pmm, the pcb monitors the transfers and stores the buffer link pointers that enable the pcb to walk the buffer chain for the frame. when the entire buffer chain has been traversed, the pcb entry is updated with the next frame for that target port. as the pmm uses the data from each buffer, it passes the buffer pointer back to the release logic in the egress eds. the release logic examines the mcc table entry to determine if the buffer should be returned to the fqs. (half-duplex ports will not have their twin buffers released until the entire frame has been trans- mitted, in order to to support the recovery actions that are necessary when a collision occurs on the ethernet media.) if the mcc entry indicates that no other copies of this frame are needed, the buffer pointer is stored in the fqs. however, if the mcc entry indicates that other copies of this frame are still being used, the egress eds decrements the mcc entry, but does no further action with this buffer pointer. the dpq contains frames that have been enqueued for discard by the epc and by the release logic. the hardware uses the dpq to discard the last copy of frames transmitted on half duplex ports. the dpq is dequeued into the pcb?s discard entry, where the frame data is read from the ds to obtain buffer chaining information necessary to locate all twin buffers of the frame and to release these twin buffers back to the free pool (fqs). IBM32NPR161EPXCAC133 ibm powernp preliminary egress enqueuer / dequeuer / scheduler page 136 of 444 np3_dl_sec06_eeds.fm.01 09/25/00 6.3 egress flow control 6.3.1 overview flow control (whether to forward or discard frames) in the network processor is provided by hardware assist mechanisms and picocode that implements a selected flow control algorithm. in general, flow control algo- rithms require information about the congestion state of the data flow, including the rate at which packets arrive, the current status of the data store, the current status of target blades, and so on. a transmit probabil- ity for various flows is an output of these algorithms. there are two implementations of flow control in the network processor: flow control that is invoked when the frame is enqueued to either a target port queue or a flow qcb. the hardware assist mechanisms use the transmit probability along with tail drop congestion indicators to determine if a forwarding or discard action should be taken during frame enqueue operation. the flow control hardware uses the picocode?s entries in the egress transmit probability memory to determine what flow control actions are required. flow control that is invoked when frame data enters the network processor. when the egress ds is suffi- ciently congested, these flow control actions discard all frames. the threshold that controls the invocation of these actions is fq_es_threshold_0 (see table 50: list of flow control hardware facilities on page 136 for more information). 6.3.2 flow control hardware facilities the hardware facilities listed in table 50 are provided for the picocode's use when implementing a flow con- trol algorithm. the picocode uses the information from these facilities to create entries in the egress transmit probability memory. the flow control hardware uses these entries when determining what flow control actions are required. table 50: list of flow control hardware facilities name definition access free queue count instantaneous count of the number of free twins available in the egress data store. cab fq_es_threshold_0 threshold for free queue count. when the free queue count < fq_es_threshold_0, no further twins are allocated for incoming data. user packets that have started reassem- bly are discarded when they receive data when this threshold is violated. guided traffic is not discarded. the number of packets discarded is counted in the reassembly discard counter. when this threshold is violated, an interrupt (class 0, bit 4) is signaled. cab fq_es_threshold_1 threshold for free queue count. when the free queue count < fq_es_threshold_1, an interrupt (class 0, bit 5) is signaled. cab fq_es_threshold_2 threshold for free queue count. when the free queue count < fq_es_threshold_2, an interrupt (class 0, bit 6) is signaled, and if enabled by dmu configuration, the ethernet mac preamble is reduced to 6 bytes. cab arrival rate counter this is the arrival rate of data into the egress data store. this counter increments each time there is a dequeue from the twin free queue. when read by picocode, via the cab, this counter is set to 0 (read with reset). cab fq count ewma this is the calculated ewma of the free queue count cab p0 twin count this counter is the number of twins in priority 0 packets that have been enqueued to flow queues, but have not been dequeued from target port queues. cab IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec06_eeds.fm.01 09/25/00 egress enqueuer / dequeuer / scheduler page 137 of 444 6.3.3 remote egress status bus 6.3.3.1 overview the remote egress status (res) bus communicates the congestion state of the egress datastores of all np4gs3s in a system to the ingress flow control of every np4gs3 in that system. the ingress portion of each np4gs3 can then preemptively discard frames destined for a congested np4gs3 without consuming additional bandwidth through the switch. 6.3.3.2 bus sequence and timing the res bus consists of two bidirectional signals: 1. res_data . this signal is time-division multiplexed between all the np4gs3s in a system. only one np4gs3 at a time drives this signal. each np4gs3 drives two priorities of congestion status sequentially. all of the np4gs3s in a system sample this data and store it for use by the ingress flow control to make p1 twin count this counter is the number of twins in priority 1 packets that have been enqueued to flow queues, but have not been dequeued from target port queues. cab p0 twin count threshold threshold for p0 twin count which is used when determining flow control actions against priority 0 traffic. when p0 twin count < p0 twin count threshold, the flow control hard- ware will discard the frame. cab p1 twin count threshold threshold for p1 twin count which is used when determining flow control actions against priority 1 traffic. when p1 twin count < p1 twin count threshold, the flow control hardware will discard the frame. cab egress p0 twin count ewma this is the calculated ewma of the count of the number of twins allocated to p0 traffic during the sample period. hardware maintains a count of the number of twins allocated to p0 traffic at enqueue. cab egress p1twin count ewma this is the calculated ewma of the count of the number of twins allocated to p1 traffic during the sample period. hardware maintains a count of the number of twins allocated to p1 traffic at enqueue. cab egress p0 twin count ewma threshold the congestion status of the egress data store in each target blade is the result of a comparison between this configured threshold and the ewma of the offered rate of prior- ity 0 traffic (p0 twin count ewma < p0 twin count ewma threshold). this information is transmitted to remote blades via the res_data i/o and is collected in the remote tb sta- tus 0 register in the ingress flow control hardware. cab egress p1 twin count ewma threshold the congestion status of egress data store in each target blade is the result of a compar- ison between this configured threshold and the ewma of the offered rate of priority 0 traf- fic. (p1 twin count ewma < p1 twin count ewma threshold). this information is transmitted to remote blades via the res_data i/o and is collected in the remote tb sta- tus 1 register in the ingress flow control hardware. cab target port pq+fq_th target port port queue plus egress scheduler (flow qcb) threshold. the target port queues maintain a count of the number of twins allocated to the target port. the count is incremented on enqueue (after flow control transmit action is taken) and decremented on dequeue from the target port. thresholds for each priority can be configured for for all ports (0:39). when the number of twins assigned to a target port queue exceeds the threshold, its threshold exceed status is set to 1. the status is used to index into the transmit probability memory for packets going to the target port. cab qcb threshold flow queue threshold. when the number of twins assigned to this flow queue exceeds this threshold, the threshold exceed status is set to 1. the status is used to index into the transmit probability memory. cab table 50: list of flow control hardware facilities (continued) name definition access IBM32NPR161EPXCAC133 ibm powernp preliminary egress enqueuer / dequeuer / scheduler page 138 of 444 np3_dl_sec06_eeds.fm.01 09/25/00 discard decisions. 2. res_sync . this signal is received by all np4gs3s in a system. each np4gs3 samples the negative edge of this signal to derive its time slot to drive egress datastore congestion information. this signal is periodic and repeats to allow the np4gs3s to resynchronize after 16 or 64 time slots have passed, depending on the value of the tb mode register. in a system, one np4gs3 can be configured to drive this signal to the other np4gs3s. alternatively, an external chip can provide the stimulus for this signal. figure 43 shows a timing diagram of the operation of the res bus. the res bus operates on the same clock frequency as the internal dasl clock. this clock period can range from 8 ns to 10 ns. the clock that the res bus uses is not necessarily in phase with the dasl clock. in addi- tion, each np4gs3 is not necessarily in phase with other np4gs3s in the same system. the res_sync sig- nal is responsible for synchronizing all the np4gs3s. the res bus is time-division multiplexed between every np4gs3 in the system. each np4gs3 takes a turn driving its congestion information onto the res bus in the order of its my_tb register (i.e., the np4gs3 with a my_tb setting of 0 drives immediately following the fall of res_sync, followed by the np4gs3 with a my_tb setting of 1, etc.) within each np4gs3 time slot, the np4gs3 puts four values on the res_data signal. each value is held for eight dasl clock cycles. therefore, each np4gs3 time slot is 32 dasl clock cycles. the protocol for send- ing the congestion information is as follows: 1. high-z - the np4gs3 keeps its res_data line in high impedance for eight dasl clock cycles. this allows the bus to turn around from one np4gs3 to another. 2. p0 - the np4gs3 drives its priority 0 (p0) egress datastore congestion information for eight dasl clock cycles. this status is high when the egress p0 twin count ewma register value is greater than the egress p0 twin count ewma threshold register value. it is low otherwise. 3. p1 - the np4gs3 drives its priority 1 (p1) egress datastore congestion information for eight dasl clock cycles. this status is high when the egress p1 twin count ewma register value is greater than the egress p1 twin count ewma threshold register value. it is low otherwise. figure 43: res bus timing res_sync res_data p1 reserved z p0 p1 reserved z p0 1 2 3 4 np 0 np 1 np n 8dasl cycles sampling points IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec06_eeds.fm.01 09/25/00 egress enqueuer / dequeuer / scheduler page 139 of 444 4. reserved - the np4gs3 drives a low value for eight dasl clock cycles. this is reserved for future use. the ingress flow control samples res_data during the midpoint of its eight dasl clock cycles. this pro- vides a large enough sample window to allow for jitter and phase differences between the dasl clocks of two different np4gs3s. the res_sync signal is driven high during the reserved cycle of the last np4gs3?s time slot. the res_sync signal therefore has a period equal to 32 dasl clock periods multiplied by the number of np4gs3s supported in this system. the number of np4gs3s can be either 16 or 64 depending on the value of the tb mode register. 6.3.3.3 configuration the res bus is activated by enabling the ingress and egress portions via the remote egress status bus configuration enables register. this register contains a bit to enable the ingress logic to capture the res_data, a bit to enable the egress logic to send its status on res_data, and a bit to enable one of the np4gs3s to drive res_sync. 6.3.4 hardware function 6.3.4.1 exponentially weighted moving average (ewma) the hardware generates ewma values for the free queue count and the p0/p1 twin counts, thus removing the burden of this calculation from the picocode. in general, ewma for a counter x is calculated as follows: ewma_x = (1-k) * ewma_x + k * x this calculation occurs for a configured sample period and k {1, 1/2, 1/4, 1/8). 6.3.4.2 flow control hardware actions when the picocode enqueues a packet to be transmitted to a target port, the flow control logic examines the state of the target port pq+fq_th, and the priority of the enqueued packet to determine if any flow control actions are required. if the fcinfo field of the fcbpage of the enqueued packet is set to x?f?, flow control is disabled and the packet is forwarded without regard to any of the congestion indicators. for priority 0 packets, if target port pq+fq_th or p0 twin count threshold is exceeded, then the packet will be discarded. a counter block must be set up by the picocode to count these discards. for priority 1 packets, if p1 twin count threshold is exceeded, then the packet will be discarded. other- wise the transmit probability found in the qcb (available only when the scheduler is enabled) and the transmit probability table are accessed. the smaller of these values is compared against a random num- ber ( { 0 .. 1} ) generated by the hardware. when the transmit probability is 0 or is less than the random number, the packet is discarded. a counter block must be set up by the picocode to count these discards. IBM32NPR161EPXCAC133 ibm powernp preliminary egress enqueuer / dequeuer / scheduler page 140 of 444 np3_dl_sec06_eeds.fm.01 09/25/00 the index into the transmit probability table is ttccfp where: tt packet type (egress fcbpage fcinfo field bits 3:2). cc dscp assigned color (egress fcbpage fcinfo field bits 1:0) f threshold exceeded status of the target flow queue (qcb threshold exceeded) p threshold exceeded status of the target port queue (target port pq+fq_th exceeded) IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec06_eeds.fm.01 09/25/00 egress enqueuer / dequeuer / scheduler page 141 of 444 6.4 the egress scheduler 6.4.1 overview the egress scheduler provides shaping functions in the network processor. the egress scheduler manages bandwidth on a per frame basis by determining the amount of bandwidth a frame requires (i.e. the number of bytes to be transmitted) and comparing this against the amount of bandwidth permitted by the configuration of the frame?s flow queue. the amount of bandwidth used by a first frame affects when the scheduler permits the transmission of a second frame of a flow queue. the egress scheduler characterizes flow queues with the parameters listed in table 51 : a graphical representation of the egress scheduler is shown in figure 44: the egress scheduler on page 142. a list of valid combinations of above parameters is given in table 52: valid combinations of scheduler parameters on page 143. table 51: flow queue parameters parameter name description low latency sustainable bandwidth (lls) provides guaranteed bandwidth with qualitative latency reduction. normal latency sustainable bandwidth (nls) provides guaranteed bandwidth. lls has higher service priority over nls, such that flow queues connected to lls have better latency characteristics when compared to flow queues connected to nls. peak bandwidth service (pbs) provides additional bandwidth on a best effort basis. queue weight allows the scheduler to assign available (i.e. not assigned or currently not used by lls and nls) bandwidth to flow queues using best effort or pbs services. assign- ment of different ratios of the available bandwidth is accomplished by assigning dif- ferent queue weights to queues that share the same target port. IBM32NPR161EPXCAC133 ibm powernp preliminary egress enqueuer / dequeuer / scheduler page 142 of 444 np3_dl_sec06_eeds.fm.01 09/25/00 figure 44: the egress scheduler 5 nls flow 0 flow 1 lls 511 0 511 0 511 511 flowid 0 flowid 511 0 511 0 511 511 flowid 0 wfq port 39 peak bandwidth shaping (pbs) 511 0 511 0 511 511 flowid 0 1 0 flow 2047 511 flowid 0 wfq port 0 511 0 3 1 2 4 2 1 3 discard wrap port 0 port 1 port 39 port 0 port 39 port 1 port 38 port 38 high priority target port queues low priority target port queues 4 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec06_eeds.fm.01 09/25/00 egress enqueuer / dequeuer / scheduler page 143 of 444 6.4.2 egress scheduler components the egress scheduler consists of the following components: scheduling calendars 2048 flow queues (flow qcb) and 2048 associated scheduler control blocks (scb) target port queues discard queue wrap queue 6.4.2.1 scheduling calendars the egress scheduler selects a flow queue to service every scheduler_tick. the duration of a scheduler_tick is determined by the configuration of the dram parameter register 11/10 field (bit 6 only). when set to 0, a scheduler_tick is 150 ns. when set t o1ascheduler_tickis165ns. there are three types of scheduling calendars used in the egress calendar design, time based, weighted fair queuing (wfq), and wrap. time based calendars the time based calendars are used for guaranteed bandwidth (lls or nls) and for peak bandwidth shaping. weighted fair queuing calendars the weighted fair queuing calendars allocate available bandwidth to competing flows on a per port basis. available bandwidth is defined as the bandwidth left over after the flows in the nls and lls calendars get their bandwidth. a wfq calendar is selected for service only when no service is required by the nls, lls or pbs calendars and the target port queue does not exceed a programmable threshold. the use of this thresh- old is the method that assures the wfq calendar dequeues frames to the target port at a rate equal to the port's available bandwidth. table 52: valid combinations of scheduler parameters qos lls nls weight pbs low latency with guaranteed bw shaping x normal latency with guaranteed bw shaping x best effort x best effort with peak rate x x normal latency with guaranteed bw shaping and best effort xx normal latency with guaranteed bw shaping and best effort and peak rate xxx IBM32NPR161EPXCAC133 ibm powernp preliminary egress enqueuer / dequeuer / scheduler page 144 of 444 np3_dl_sec06_eeds.fm.01 09/25/00 wrap calendar the wrap calendar is a 2-entry calendar for flows that use the wrap port. selection algorithm between calendar types selection between calendar types occurs each scheduler_tick using a fixed priority mechanism. the priority for each calendar type, with 1 highest, is: 1. time based lls 2. time based nls 3. time based peak bandwidth shaping 4. weighted fair queuing 5. wrap 6.4.2.2 flow queues there are 2048 flow queues (flow qcbs) and scheduler control blocks. a flow qcb contains information about a single flow. information that must be configured before the flow qcb can be used is listed here. configuring sustainable bandwidth (ssd) the sustained service rate (ssr) is defined as the minimum guaranteed bandwidth provided to the flow queue. it is implemented using either the lls or nls calendars. the following transform is used to convert sustained service rate from typical bandwidth specifications to scheduler step units (ssd): ssd = (512 (bytes) / scheduler_tick (sec) ) / sustained_service_rate (bytes/sec) the flow qcb ssd field is entered in exponential notation as x *16 y , where x is the ssd.v field and y is the ssd.e field . when a sustained service rate is not specified, the flow qcb ssd field must be set to 0 during configuration. values of ssd that would cause the calendars to wrap should not be specified. knowing the maximum frame size, ssd max can be bound by: ssd max 1.07 * 10e+9 / maximum frame size (bytes) an ssd value of 0 indicates that this flow queue has no defined guaranteed bandwidth component (ssr). configuring flow qcb flow control thresholds (th) when the number of bytes enqueued in the flow queue exceeds the flow qcb threshold (th), the flow queue is considered to be congested. the flow control hardware uses this congestion indication to select the transmit probability. the following transform is used to specify this threshold: th.e threshold value (units in twin buffers) 0th.v*2**6 1th.v*2**9 2th.v*2**12 3th.v*2**15 th.v and th.e fields are components of the flow control threshold field . the number of bytes in a twin IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec06_eeds.fm.01 09/25/00 egress enqueuer / dequeuer / scheduler page 145 of 444 buffer is approximately 106 bytes. a th value of 0 disables threshold checking. configuring best effort service (qd) the queue weight is used to distribute available bandwidth among queues assigned to a port. the remaining available bandwidth on a port is distributed among contending queues in proportion to the flow?s queue weight. the following transform is used to convert the queue weight into scheduler step units (qd): qd = 1/ (queue weight) a qd of 0 indicates that the flow queue has no best effort component. configuring peak best effort bandwidth (psd) peak service rate is defined as the additional bandwidth that this flow queue is allowed to use (the difference between the guaranteed and the peak bandwidth). for example, if a service level agreement provided for a guaranteed bandwidth of 8 mbps and a peak bandwidth of 10 mbps, then the peak service rate is 2 mbps. the following transform is used to convert peak service rate from typical bandwidth specifications to sched- uler step units (psd): psd = (512 (bytes) / scheduler_tick (sec) ) / peak_service_rate (bytes/sec) the flow qcb psd field is entered in exponential notation as x *16 y , where x is the psd.v field and y is the psd.e field. a psd value of 0 indicates that this flow queue has no peak service rate component. target port (tp) the destination target port id. target port priority (p) the target port priority selects either the lls or nls calendar for the guaranteed bandwidth component of a flow queue. values of 0 (high) and 1 (low) select the lls or nls calendar respectively. during an enqueue to a target port queue, the p selects the correct queue. this field is also used in flow con- trol. transmit probability flow control uses transmit probability. the flow control algorithms running in picocode update this field peri- odically. IBM32NPR161EPXCAC133 ibm powernp preliminary egress enqueuer / dequeuer / scheduler page 146 of 444 np3_dl_sec06_eeds.fm.01 09/25/00 6.4.2.3 target port queues there are 82 target port queues, including 40 target ports with two priorities, a discard port, and a wrap port. the scheduler dequeues frames from flow qcbs and places them into the target port queue that is desig- nated by the flow qcb?s target port (tp) and priority (p) fields. a combination of a work conserving round robin and an absolute priority selection services target port queues. the round robin selects among the 40 media ports (target port ids 0 through 39) within each priority class (high and low as shown in figure 44 on page 142 ). a secondary selection using absolute priority is performed with the priority order as: 1. high priority target port queues 2. low priority target port queues 3. discard queue 4. wrap queue information that must be configured for each target port queue is: port queue threshold (th_pq) when the number of bytes enqueued in the target port queue exceeds the port queue threshold, the corre- sponding wfq calendar cannot be selected for service. this back pressure to the wfq calendars assures that best effort traffic is not allowed to fill the target port queue ahead of frames dequeued from the lls and nls calendars. the back pressure is the mechanism by which the target port bandwidth is reflected in the operation of the wfq calendars. the following transform is used to specify th_pq: th_pq = port_queue_threshold (bytes)/106 (bytes) when configuring this threshold, it is recommended that the value used be larger than the mtu of the target port. port queue + flow queue threshold (th_pq+fq) this is threshold for the total number of bytes in the target port queue plus the total number of bytes in all flow queues that are configured for this target port. when this threshold is exceeded by the value in the queue, the target port is congested. the flow control mechanisms use this congestion indication to select a transmit probability. the following transform is used to specify th_pq+fq: th_pq+fq = port_queue+scheduler_threshold (bytes)/106 (bytes) IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec06_eeds.fm.01 09/25/00 egress enqueuer / dequeuer / scheduler page 147 of 444 6.4.3 configuring flow queues table 53 illustrates how to configure a flow qcb using the same set of combinations found in table 52: valid combinations of scheduler parameters on page 143. 6.4.3.1 additional configuration notes 1. once the scheduler is enabled via the memory configuration register, the picocode is unable to enqueue directly to a target port queue. to disable the scheduler, the software system design must assure that the scheduler is drained of all traffic. all target port queue counts can be examined via the cab; when all counts are zero, the scheduler is drained. 2. a flow qcb must be configured for discards (tp=41). a sustained service rate must be defined (ssd 0). a peak service rate and queue weight must not be specified (psd=0 and qd=0). 3. two flow qcbs must be defined for wrap traffic. one flow qcb must be defined for guided traffic (tp = 40) and one for frame traffic (tp = 42). for these qcbs, the peak service rate and sustained service rate must not be specified (psd=0 and ssd=0). queue weight must be non-zero (qd 0). table 53: configure a flow qcb qos qcb.p qcb.sd qcb.psd qcb.qd low latency with guaranteed bw shaping 0 00 0 normal latency with guaranteed bw shaping best effort 1 00 0 best effort 1 0 0 0 best effort with peak rate 1 0 0 0 normal latency with guaranteed bw shaping with best effort 1 00 0 normal latency with guaranteed bw shaping with best effort, and peak rate 1 0 0 0 IBM32NPR161EPXCAC133 ibm powernp preliminary egress enqueuer / dequeuer / scheduler page 148 of 444 np3_dl_sec06_eeds.fm.01 09/25/00 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 149 of 444 7. embedded processor complex 7.1 overview the embedded processor complex (epc) provides and controls the programmability of the np4gs3. the epc consists of the following components: eight dyadic protocol processors units (dppu) each dppu consists of two core language processors (clp), eight shared coprocessors, one copro- cessors databus, one coprocessor command bus, and a shared memory pool. each clp contains one alu and supports two picocode threads, so each dppu has four threads (see section 7.1.1 thread types on page 152 for more information). although there are 32 independent threads, each clp can execute the command of only one of its picocode threads, so at any one instant in time only 16 threads are executing on all of the clps. the clps and coprocessors contain independent copies of each thread?s registers and arrays. most coprocessors perform specialized functions as described below and can operate concurrently with each other and with the clps. - tree search engine (tse) the tse coprocessor is part of the dppus. it has commands for tree management, direct access to the control store (cs), and search algorithms such as full match (fm), longest prefix match (lpm), and software managed (smt) trees. for more information, see section 8 on page 219. interrupts and timers the np4gs3 has four interrupt vectors. each interrupt can be configured to initiate a dispatch to occur to one of the threads for processing. there are four timers that can be used to generate periodic interrupts. instruction memory the instruction memory consists of eight embedded rams that are loaded during initialization and con- tain the picocode for forwarding frames and managing the system. the total size is 16 k instructions. the memory is 4-way interleaved with four rams for the first 8 k and four rams for the remaining 8 k. control store arbiter (csa) the csa controls access to the control store (cs) which allocates memory bandwidth among the threads of all the dyadic protocol processors. the cs is shared among the tree search engines and the picocode can directly access the cs through commands to the tse coprocessor. the tse coprocessor also accesses the cs during tree searches. dispatch unit the dispatch unit dequeues frame information from the ingress-eds and egress-eds queues. after dequeue, the dispatch unit reads part of the frame from the ingress or egress data store (ds) and places it into the datapool. as soon as a thread becomes idle, the dispatch unit passes the frame with appropriate control information, to the thread for processing. the dispatch unit also handles timers and interrupts by dispatching the work required for these to an available thread. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 150 of 444 np3_dl_sec07_epc.fm.01 09/25/00 completion unit (cu) the cu performs two functions: - it provides the interfaces between the epc and the ingress and egress edss. each eds performs an enqueue action whereby a frame address, together with appropriate parameters, is queued in a transmission queue or a dispatch unit queue. - the cu guarantees frame sequence. since multiple threads can process frames belonging to the same flow, the cu ensures that all frames are enqueued in the ingress or egress transmission queues in the proper order. hardware classifier (hc) the hc provides hardware assisted parsing of frame data that is dispatched to a thread. the results are used to precondition the state of a thread by initializing the thread?s general purpose and coprocessor scalar registers and a starting instruction address for the core language processor. parsing results indicate the type of layer 2 encapsulation, as well as some information about the layer 3 packet. recog- nizable layer 2 encapsulations include ppp, 802.3, dix v2, llc, snap header, and vlan tagging. reportable layer 3 information includes ip and ipx network protocols, five programmable network proto- cols, the detection of ip option fields, and transport protocols (udp, tcp) for ip. ingress and egress data store interface and arbiter each thread has access to the ingress and egress data store through a data store coprocessor. read access is provided when reading ?more data? and write access is provided when writing back the con- tents of the shared memory pool (smp) to the data store. one arbiter is required for each data store since only one thread at a time can access either data store. control access bus (cab) arbiter each thread has access to the cab, which permits access to all memory and registers in the network processor. the cab arbiter arbitrates among the threads for access to the cab. debugging and single step control the cab allows the gfh thread to control each thread on the chip for debugging purposes. for example, the cab can be used by the gfh thread to run a selected thread in single-step execution mode. (see section 12. debug facilities on page 337 for more information.) policy manager the policy manager is a hardware assist of the epc that performs policy management on up to 1 k ingress flows. it supports four management algorithms. one algorithm pair is ?single rate three color marker,? and the other is ?two rate three color marker.? both are operated in color-blind or color-aware mode. the algorithms are specified in ietf rfcs 2697 and 2698 (available at http://www.ietf.org ). counter manager the counter manager is a hardware assist engine used by the epc to manage counters defined by the picocode for statistics, flow control, and policy management. the counter manager is responsible for counter updates, reads, clears, and writes. the counter manager's interface to the counter coprocessor provides picocode access to these functions. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 151 of 444 ludeftable, comptable, and free queues are tables and queues for use by the tree search engine. (for more information, see 8.2.5.1 the ludeftable on page 233 and the ibm powernp np4gs3 hardware reference manual.) figure 45: embedded processor complex block diagram control store arbiter h0 h1 z0 d1 d2 d6 on-chip memories off-chip memories dispatch unit ingress ds egress ds interface instruction memory cab arbiter debug & single step control ingress eds queue egress eds queue ingress data ingress data store interface (rd) egress data egress data store interface (rd) cab internal epc cab ludeftable comptable freeqs interrupts freezeepc exception d0 completion unit counter manager policy manager hardware classifier d3 405 powerpc core interrupt dppu 1 dppu 8 tree search engine store and arbiter (rd+wr) and arbiter (rd+wr) store interface interface interrupts & timers IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 152 of 444 np3_dl_sec07_epc.fm.01 09/25/00 7.1.1 thread types the epc has 32 threads that can simultaneously process 32 frames. a thread has a unique set of general purpose, scalar, and array registers, but shares execution resources in the clp with another thread and execution resources in the coprocessors with three other threads. threads can be classified into five different categories: general data handler (gdh) there are 28 gdh threads. gdhs are used for forwarding frames. guided frame handler (gfh) there is one gfh thread available in the epc. a guided frame can only be processed by the gfh thread, but the gfh can be configured to process data frames like a gdh thread. the gfh executes guided frame related picocode, runs chip management related picocode, and exchanges control information with a control point function or a remote network processor. when there is no such task to perform and the option is enabled, the gfh may execute frame forwarding related picocode. general table handler (gth) there is one gth thread available in the epc. the gth executes tree management commands not available to other threads. the gth performs actions including hardware assist to perform tree inserts, tree deletes, tree aging, and rope management. the gth can process data frames like a gdh when there are no tree management functions to perform. general powerpc handler request (gph-req) there is one gph-req thread available in the epc. the gph-req thread processes frames bound to the embedded powerpc. work for this thread is the result of a re-enqueue action from another thread in the epc to the gpq queue. the gph-req thread moves data bound for the powerpc to the powerpc?s mailbox (a memory area) and then notifies the powerpc that it has data to process. (see section 10.8 mailbox communications and dram interface macro on page 291 for more information.) general powerpc handler response (gph-resp) there is one gph-resp thread available in the epc. the gph-resp thread processes responses from the embedded powerpc. work for this thread is dispatched due to an interrupt initiated by the powerpc and does not use dispatch unit memory. all the information used by this thread is found in the embedded powerpc?s mailbox. (see section 10.8 mailbox communications and dram interface macro on page 291 for more information.) IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 153 of 444 7.2 dyadic protocol processor unit (dppu) each dppu consists of two core language processors, eight coprocessors, one coprocessors databus, one coprocessor command bus, (the coprocessor databus and coprocessor execution interfaces), an da4k byte shared memory pool (1 k bytes per thread). each clp supports two threads, so each dppu has four threads which execute the picocode that is used to forward frames, update tables, and maintain the network processor. the first dppu contains the gfh, gth, and the ppc threads and the other seven dppus contain the gdh threads. each dppu interfaces to the instruction memory, the dispatch unit, the control store arbi- ter, the completion unit, the hardware classifier, the interface and arbiter to the ingress and egress data stores, the cab arbiter, the debugging facilities, the counter manager, the policy manager, and the ludeft- able and comp free queues. figure 46: dyadic protocol processor unit block diagram completion unit processor processor shared memory pool cpdi arbiter cpei arbiter checksum string enqueue data store control access bus interface counter policy 4 cab arbiter counter manager policy manager ingress ds interface tree search engine coprocessor execution interface coprocessor data interface egress ds interface instruction memory interface instruction memory interface hardware classifier hardware classifier cab access core language core language dyadic protocol processor unit copy IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 154 of 444 np3_dl_sec07_epc.fm.01 09/25/00 7.2.1 core language processor (clp) each dppu contains two clps. the clp executes the epc?s core instruction set and controls thread swap- ping and instruction fetching. each clp is a 32-bit picoprocessor consisting of: 16 32-bit or 32 16-bit general purpose registers (gpr) per thread. (for more information, see table 54: core language processor address map on page 156 .) a one-cycle alu supporting an instruction set that includes: - binary addition and subtraction - bit-wise logical and, or, and not - compare - count leading zeros - shift left and right logical - shift right arithmetic - rotate left and right - bit manipulation commands: set, clear, test, and flip - gpr transfer of halfword to halfword, word to word, and halfword to word with and without sign extensions. - all instructions can be coded to run conditionally. this eliminates the need for traditional branch-and- test coding techniques, improving performance and reducing the size of the code. all arithmetic and logical instructions can be coded to execute without setting alu status flags. management for handling two threads with zero overhead for context switching read-only scalar registers that provide access to interrupt vectors, timestamp, output of a pseudo ran- dom number generator, picoprocessor status, work queue status (such as the ingress and egress data queues), and configurable identifiers (such as the blade identification). (for more information, see table 54: core language processor address map on page 156 .) 16-word instruction prefetch shared by each thread instruction execution unit that executes branch instructions, instruction fetch, and access to the copro- cessors coprocessor data interface (cpdi): - access from any byte, halfword, or word of a gpr to an array, or from an array to a gpr. - access to coprocessor scalar registers - various sign, zero, and one extension formats - quadword transfers within the coprocessor arrays coprocessor execution interface (cpei): - synchronous or asynchronous coprocessor operation - multiple coprocessor synchronization - synchronization and branch-on-coprocessor return code IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 155 of 444 figure 47: core language processor alu instruction execution unit cpei interface cpdi interface instruction fetch interface instruction stack 8x32b flags control immediate data cpei cpdi instruction memory 128 b interface gpr pool 16x32b gpr pool 16x32b cpei arbiter cpdi arbiter scalar registers IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 156 of 444 np3_dl_sec07_epc.fm.01 09/25/00 7.2.1.1 core language processor address map table 54: core language processor address map name register (array) 1 number size (bits) access description pc x?00? 16 r program counter. address of the next instruction to be executed. alustatus x?01? 4 r the current alu status flags: 3zero 2carry 1sign 0overflow linkreg x?02? 16 r/w link register. return address for the most recent subroutine copstatus x?03? 10 r indicates whether the coprocessor is busy or idle. a coprocessor that is busy will stall the clp when the coprocessor command was executed synchronously or a wait command was issued for the coprocessor. 1 coprocessor is busy 0coprocessorisidle coprtncode x?04? 10 r the definition of ok/ko is defined by the coprocessor. 1ok 0notok threadnum x?05? 5 r the thread number (0..31) timestamp x?80? 32 r free-running, 1 ms timer randomnum x?81? 32 r random number for programmer?s use intvector0 x?83? 32 r read-only copy of interrupt vector 0. reading this register has no effect on the actual interrupt vector 0. intvector1 x?84? 32 r read-only copy of interrupt vector 1. reading this register has no effect on the actual interrupt vector 1. intvector2 x?85? 32 r read-only copy of interrupt vector 2. reading this register has no effect on the actual interrupt vector 2. intvector3 x?86? 32 r read-only copy of interrupt vector 3. reading this register has no effect on the actual interrupt vector 3. idlethreads x?87? 32 r indicates that a thread is enabled and idle qvalid x?88? 32 r indicates status of the queues (valid or invalid). my_tb x?89? 6 r my target blade. the blade number representing the blade in which this networking processor chip is currently residing (see 13.13.9 my target blade address register (my_tb) on page 365) sw_defined_a x?8a? 32 r software defined register sw_defined_b x?8b? 32 r software defined register sw_defined_c x?8c? 32 r software defined register version_id x?8f? 32 r contains the version number of the hardware. gprw0 x?c0? 32 r general purpose register w0 gprw2 x?c1? 32 r general purpose register w2 gprw4 x?c2? 32 r general purpose register w4 gprw6 x?c3? 32 r general purpose register w6 1. a number in parentheses is the array number for this coprocessor. each array has a register number and an array number. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 157 of 444 gprw8 x?c4? 32 r general purpose register w8 gprw10 x?c5? 32 r general purpose register w10 gprw12 x?c6? 32 r general purpose register w12 gprw14 x?c7? 32 r general purpose register w14 gprw16 x?c8? 32 r general purpose register w16 gprw18 x?c9? 32 r general purpose register w18 gprw20 x?ca? 32 r general purpose register w20 gprw22 x?cb? 32 r general purpose register w22 gprw24 x?cc? 32 r general purpose register w24 gprw26 x?cd? 32 r general purpose register w26 gprw28 x?ce? 32 r general purpose register w28 gprw30 x?cf? 32 r general purpose register w30 pgramstack0 x?fc? (0) 128 r/w entries in the program stack (used by the clp hardware to build instruction address stacks for the branch and link commands) pgramstack1 x?fd? (1) 128 r/w entries in the program stack (used by the clp hardware to build instruction address stacks for the branch and link commands) table 54: core language processor address map (continued) name register (array) 1 number size (bits) access description 1. a number in parentheses is the array number for this coprocessor. each array has a register number and an array number. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 158 of 444 np3_dl_sec07_epc.fm.01 09/25/00 7.2.2 dppu coprocessors each dppu coprocessor is a specialized hardware assist engine that runs in parallel with the two clps and performs functions that would otherwise have required a large amount of serialized picocode. the functions include modifying ip headers, maintaining flow information used in flow control algorithms, accessing internal registers via the cab, maintaining counts for flow control and for standard and proprietary management infor- mation blocks (mib), and enqueueing frames to be forwarded. the dppu coprocessors are: datastore tree search engine (see section 8 on page 219) control access bus interface enqueue checksum stringcopy policy counter a thread?s address space is a distributed model in which registers and arrays reside within the coprocessors (each coprocessor maintains resources for four threads and, for address mapping purposes, the clp is con- sidered to be a coprocessor ). each coprocessor can have a maximum of 252 scalar registers and four arrays. the address of a scalar register or array within the dppu becomes a combination of the coproces- sor number and the address of the entity within the coprocessor. likewise, the coprocessor instruction is a combination of the coprocessor number and the coprocessor opcode. the epc coprocessors are numbered as shown in table 55 . the number is used in accesses on both the coprocessor execute and data interfaces. the tse is mapped to two coprocessor locations so that a thread can execute two searches simultaneously. table 55: coprocessor instruction format coprocessor number coprocessor 0 core language processor (clp) 1 data store interface 2 treesearchengine0 3 treesearchengine1 4cabinterface 5 enqueue 6 checksum 7stringcopy 8 policy 9 counter IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 159 of 444 7.2.3 the data store coprocessor the data store coprocessor provides an interface between the epc and the ingress data store, which con- tains frames that have been received from the media, and the egress data store, which contains reassem- bled frames received from the switch interface. the data store coprocessor also receives configuration information during the dispatch of a timer event or interrupt. there is one set of scalar registers and arrays defined for each thread supported by the data store copro- cessor. the scalar registers control the accesses between the shared memory pool and the ingress and egress data stores. they are maintained in the data store coprocessor. the arrays are defined in the shared memory pool (see 7.2.10 shared memory pool on page 198): the datapool, which can hold eight quadwords two scratch memory arrays, which hold eight and four quadwords respectively the configuration quadword array, which holds the port configuration data that was dispatched to the thread. these shared memory pool arrays can be conceptualized as a work area for the data store coprocessor: instead of reading or writing small increments (anything less than a quadword, or 16 bytes) directly to a data store, a larger amount (1 to 4 quadwords per operation) of frame data is read from the data store into these shared memory pool arrays or from the these arrays into the data store. the data store coprocessor has nine commands available to it. for more information, see section 7.2.3.2 data store coprocessor commands on page 165. 7.2.3.1 data store coprocessor address map table 56: data store coprocessor address map (a thread?s scalar registers and arrays that are mapped within the data store coprocessor) name register (array) 1 number size (bits) access description dsa x?00? 19 r/w address of ingress or egress data store. used in all commands except ?read more? and ?dirty?. (ingress uses the least significant 11 bits and egress uses all 19 bits for the address.) lma x?01? 6 r/w quadword address of shared memory pool. used in all commands except ?read more?. (see 7.2.10 shared memory pool on page 198.) ccta x?02? 19 r/w current address of the ingress cell or the egress twin that was dis- patched to the thread into the datapool. used in ?read more? and ?dirty? commands. the value is unitized at dispatch and updated on ?read more? commands that pass though cell or twin boundaries. nqwa x?03? 3 r/w quadword address of the location in the datapool where the next quadword will be written. iprotocoltype x?04? 16 r layer 3 protocol identifier set by the hardware classifier. (see sec- tion 7.4 hardware classifier on page 202) dirtyqw x?05? 8 r/w quadwords in the datapool that have been written and therefore may not be equivalent to the corresponding data store data. used by the dirty update commands to write back any modified data into the corre- sponding data store. 1. a number in parentheses is the array number for this coprocessor. each array has a register number and an array number. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 160 of 444 np3_dl_sec07_epc.fm.01 09/25/00 the datapool and data store access upon frame dispatch, the dispatch unit automatically copies the first n quadwords of a frame from the data store into the first n quadword positions of the datapool. the value of n is programmable in the port config- uration memory. typically, values of n are as follows: the read more commands (rdmorei and rdmoree) assist the picocode?s reading of additional bytes of a frame by automatically reading the frame data into the datapool at the next quadword address and wrapping automatically to quadword 0 when the boundary of the datapool is reached. the picocode can also read or write the ingress and egress data stores at an absolute address, independent of reading sequential data after a dispatch. bci2byte x?06? 14/20 r/w a special purpose register. the picocode running in the clp writes a 20-bit bci value, but when the register is read, it returns the 14-bit byte count represented by the bci. disp_dsu x?07? 2 r/w initializedduringdispatchtocontainthesamevalueasthedsufield in the egress fcbpage. this register is used by egress write com- mands to determine which egress data store the data store copro- cessor should access when writing data. this register has no meaning for ingress frames. disp_dsusel x?08? 1 r/w initializedduringdispatchtocontainthesamevalueasthedsu_sel field in the egress fcbpage. this register is used by egress read commands to determine which egress data store the data store coprocessor should access when reading data. this register has no meaning for ingress frames. disp_ingress x?09? 1 r dispatched frame?s type 0egressframe 1ingressframe configqw x?fc? (0) 128 r/w port configuration table entry for this frame scratchmem0 x?fd? (1) 512 r/w user defined array (to use to store temporary information, build new frames, and so on.) scratchmem1 x?fe? (2) 1024 r/w user defined array (to use to store temporary information, build new frames, and so on.) datapool x?ff? (3) 1024 r/w contains frame data from the dispatch unit n = 4 ingress frame dispatch n = 2 egress unicast frame dispatch n = 4 egress multicast frame dispatch n = 0 interrupts and timers table 56: data store coprocessor address map (a thread?s scalar registers and arrays that are mapped within the data store coprocessor) name register (array) 1 number size (bits) access description 1. a number in parentheses is the array number for this coprocessor. each array has a register number and an array number. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 161 of 444 the datapool for ingress frames for an ingress dispatch, the n quadwords are stored in the datapool at quadword-address 0, 1, ? n-1. each quadword contains raw frame-bytes, (there are no cell header or frame headers for ingress frames in the datapool). after an ingress dispatch, the datapool contains the first n*16 bytes of the frame, where the first byte of the frame has byte-address 0. the ingress datapool byte address definitions are listed in table 57 . when reading more than n quadwords of a frame (using the rdmorei command), the hardware automati- cally walks the data store?s bcb chain as required. quadwords read from the data store are written to the datapool at consecutive quadword-locations, starting at quadword address n (where n is the number of quadwords written to the datapool by the dispatch unit during frame dispatch). the quadword-address wraps from 7 - 0, therefore the picocode must save quadword 0 in case it is required later. (for example, the quadword can be copied to a scratch array). the ingress data store can also be written and read with an absolute address. the address is a bcb address. reading from an absolute address can be used for debugging and to inspect the contents of the ingress ds. for absolute ingress data store access (reads and writes), the picocode must provide the address in the ingress data store, the quadword address in the datapool, the number of quadwords to be transferred. an example of a frame stored in the ingress data store is shown in figure 48 : table 57: ingress datapool byte address definitions quadword byte address 0 0 1 2 3 4 5 6 7 8 9 101112131415 1 16171819202122232425262728293031 2 32333435363738394041424344454647 3 48495051525354555657585960616263 4 64656667686970717273747576777879 5 80818283848586878889909192939495 6 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 7 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 162 of 444 np3_dl_sec07_epc.fm.01 09/25/00 figure 48: a frame in the ingress data store quadword a quadword b quadword c quadword d frame quadword a quadword b quadword c quadword d data quadword a quadword b quadword c quadword d frame data frame data cell address a0 cell address a1 cell address a2 ingress data store a1 a2 a0 (current buffer) a2 a1 bcbs IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 163 of 444 the datapool for egress frames for an egress dispatch, the n quadwords are stored in the datapool at a starting quadword-address that is determined by where the frame header starts in the twin, which in turn depends on how the frame is packed in the switch cell and stored in the egress data store (see figure 49 ). gpr r0 is initialized during dispatch according to table 58: egress frames datapool quadword addresses on page 164. gpr r0 can be used as an index into the datapool so that the variability of the location of the start of the frame in the datapool is transparent to the picocode. figure 49: a frame in the egress data store (illustrating the effects of different starting locations) quadword a quadword b quadword c quadword d start quadword a ch ch ch ch quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d start quadword b ch ch ch ch quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d fh fh quadword a quadword b quadword c quadword d start quadword c ch ch ch ch quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d fh quadword a quadword b quadword c quadword d start quadword d ch ch ch ch quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d fh quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 164 of 444 np3_dl_sec07_epc.fm.01 09/25/00 the relationship between quadwords a, b, c, and d in the twin buffer and the location of the quadword in the datapool is always maintained. that is, quadword a is always stored at quadword address 0 or 4, quadword b is always stored at quadword address 1 or 5, quadword c is always stored at quadword address 2 or 6, and quadword d is always stored at quadword address 3 or 7. in contrast with the ingress, the datapool for the egress contains cell headers. when the exact content of the twin-buffer is copied into the datapool, it may include the 6-byte np4gs3 cell header if the quadword being copied comes from quadword a in the twin buffer. thedatapoolcanbeaccessedintwomodes: normal datapool access: accesses all bytes in the datapool including the 6-byte cell header. for example, it can be used for guided frames, where information in the cell header may be important, or for debugging and diagnostics. cell header skip datapool access: automatically skips the cell header from the datapool. the hardware assumes a cell header to be present at quadword-address 0 and 4. for example, accessing datapool[2] accesses the byte with phys- ical address 8, datapool[115] accesses the byte with physical address 127, and datapool[118] also accesses the byte with physical address 8. the maximum index that can be used for this access mode is 231. this mode is shown in table 59 . table 58: egress frames datapool quadword addresses frame start in twin buffer frame quadword address in the datapool gpr r0 framestartsatquadwordainthetwinbuffer 0 0 framestartsatquadwordbinthetwinbuffer 1 10 frame starts at quadword c in the twin buffer 2 26 frame starts at quadword d in the twin buffer 3 42 table 59: datapool byte addressing with cell header skip quadword byte address 0 ?????? 0 116 1 117 2 118 3 119 4 120 5 121 6 122 7 123 8 124 9 125 1 10 126 11 127 12 128 13 129 14 130 15 131 16 132 17 133 18 134 19 135 20 136 21 137 22 138 23 139 24 140 25 141 2 26 142 27 143 28 144 29 145 30 146 31 147 32 148 33 149 34 150 35 151 36 152 37 153 38 154 39 155 40 156 41 157 3 42 158 43 159 44 160 45 161 46 162 47 163 48 164 49 165 50 166 51 167 52 168 53 169 54 170 55 171 56 172 57 173 4 ?????? 58 174 59 175 60 176 61 177 62 178 63 179 64 180 65 181 66 182 67 183 5 68 184 69 185 70 186 71 187 72 188 73 189 74 190 75 191 76 192 77 193 78 194 79 195 80 196 81 197 82 198 83 199 6 84 200 85 201 86 202 87 203 88 204 89 205 90 206 91 207 92 208 93 209 94 210 95 211 96 212 97 213 98 214 99 215 7 100 216 101 217 102 218 103 219 104 220 105 221 106 222 107 223 108 224 109 225 110 226 111 227 112 228 113 229 114 230 115 231 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 165 of 444 fewer frame-bytes may be available in the datapool for the egress due to the presence of cell headers. table 60 shows the number of frame-bytes in the datapool after a frame dispatch. for example, when 24 bytes of frame data are always needed, the port configuration memory must be pro- grammed with the n (number of quadwords to dispatch) equal to two. when 32 bytes are always needed, the number of quadwords to dispatch must be set to three. after a dispatch, picocode can use the rdmoree command when more frame-data is required. one, two, three, or four quadwords can be requested. consult the ?guaranteed? column in table 60 to translate the necessary number of bytes into the greater number of quadwords that must be read. for example, if the pico- code must dig into the frame up to byte 64, five quadwords are required. in this example, the number of quad- words specified with the rdmoree command equals 5-n, where n is the number of quadwords initially written in the datapool by the dispatch unit. a general rule: each set of four quadwords provide exactly 58 bytes. 7.2.3.2 data store coprocessor commands the data store coprocessor provides the following commands: table 60: number of frame-bytes in the datapool number of quadwords read start quadword a start quadword b start quadword c start quadword d guaranteed 1 10161616 10 2 26323226 26 3 42484242 42 4 58585858 58 5 68747474 68 6 84909084 84 7 100 106 100 100 100 8 116 116 116 116 116 wreds write egress data store. allows the clp to read data from one of the arrays in the shared memory pool (datapool and scratch memory array) and write it to the egress data store (in multiples of quadwords only). rdeds read egress data store. allows the clp to read data from the egress data store and write it into one of the arrays in the shared memory pool (in multiples of quad- words only). wrids write ingress data store. allows the clp to write data to the ingress data store (in multiples of quadwords only). rdids read ingress data store. allows the clp to read data from the ingress data store (in multiples of quadwords only). IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 166 of 444 np3_dl_sec07_epc.fm.01 09/25/00 rdmoree read more frame data from the egress data store. a hardware assisted read from the egress data store. rdmoree continues reading the frame from where the dispatch or last ?read more? command left off and places the data into the datapool. as data is moved into the datapool, the hardware tracks the current location in the frame that is being read and captures the link pointer from the twin buffers in order to determine the address of the next twin buffer. this address is used by the hardware for subsequent rdmoree requests until the twin is exhausted and the next twin is read. since the contents of the datapool is a map of a twin's content, there is a potential for the frame data to wrap within the datapool; the picocode keeps track of the data?s location within the datapool. rdmorei read more frame data from the ingress data store. a hardware assisted read from the ingress data store. rdmorei continues reading the frame from where the dispatch or last ?read more? command left off and places the data into the datapool. as data is moved into the datapool, the hardware tracks the current location in the frame that is being read and captures the link maintained in the buffer control block area in order to determine the address of the frame?s next data buffer. this address is used by the hardware for subsequent rdmorei requests until the data buffer is exhausted and the next buffer is read. the picocode keeps track of the frame data?s location within the datapool. leasetwin lease twin buffer. returns the address of a free twin buffer (used when creating new data in the egress data store). edirty update dirty quadword egress data store. the coprocessor keeps track of the quadwords within the current twin that have been modified in the datapool array. edirty allows the clp to write only the ?dirty? data back to the egress data store (in multiples of quadwords only). this command is only valid within the datapool array and for the buffer represented by the scalar register current cell/twin address. idirty update dirty quadword ingress data store. the coprocessor keeps track of the quadwords within the current buffer that have been modified in the datapool array. idirty allows the clp to write only the ?dirty? data back to the ingress data store (in multiples of quadword units only). this command is only valid within the datapool array and for the buffer represented by the scalar register current cell/ twin address. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 167 of 444 note: the egress data store has a longer access time than the ingress data store. for performance rea- sons it is recommended to do as much frame parsing on the ingress as possible. wreds (write egress data store) command wreds writes to an absolute address in the egress data store. it can be specified if the quadwords are writ- ten to ds0, ds1, both ds0 and ds1, or if the decision is made automatically by information in the dispatch dsu register. the data store address can be any address in the egress data store, but the picocode must ensure that no twin overflow occurs during writing. for example, it is not a good idea to make the lma point to the last quad- table 61: data store coprocessor commands summary opcode command detail section 0 wreds wreds (write egress data store) command on page 167 1rdeds rdeds (read egress data store) command on page 168 2 wrids wrids (write ingress data store) command on page 168 3 rdids rdids (read ingress data store) command on page 169 5 rdmoree rdmoree (read more quadword from egress) command on page 171 7 rdmorei rdmorei (read more quadword from ingress) command on page 170 8 leasetwin leasetwin command on page 173 10 edirty edirty (update egress dirty quadwords) command on page 171 12 idirty idirty (update ingress dirty quadwords) command on page 172 table 62: wreds input operand source name size direct indirect description nrofquadword 2 imm16(1..0) gpr(1..0) defines the number of quadwords to be written: 01 1 quadword 10 2 quadwords 11 3 quadwords 00 4 quadwords dscontrol 2 imm16(3..2) imm12(3..2) defines if the quadwords are written to ds0, ds1 or both: 00 writes to the default dsu 01 writes to ds0 10 writes to ds1 11 writes to ds0 and ds1 disp_dsu 2 r the default dsu, initialized at dispatch dsa 19 r data store address. the target twin address in the egress data stores. the starting qw destination within the twin is determined by the 3 low-order bits of the lma. 000 - 011 are qw 0-3 of the first buffer of the twin. 100-111 are qw 0-3 of the second buffer of the twin. lma 6 r local memory address. the quadword source address in the shared memory pool (see 7.2.10 shared memory pool on page 198). IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 168 of 444 np3_dl_sec07_epc.fm.01 09/25/00 word in a 64-byte buffer and set nrofquadword to four. rdeds (read egress data store) command rdeds reads from an absolute address in the egress data store. it can be specified if the quadwords are read from ds0 or ds1, or if this decision is made automatically by information in the dispatch dsu register. when dscontrol is set to 00, the quadwords are read from the default ds, which is determined based on the dispatch dsusel field. wrids (write ingress data store) command wrids writes to an absolute address in the ingress data store. table 63: wreds output operand source name size direct indirect description lma 6 r local memory address. the lma will be the input value of the lma incremented by the number of quadword transfers com- pleted by the command. table 64: rdeds input operand source name size direct indirect description nrofquadword 2 imm16(1..0) gpr(1..0) defines the number of quadwords to be read: 01 1 quadword 10 2 quadwords 11 3 quadwords 00 4 quadwords dscontrol 2 imm16(3..2) imm12(3..2) defines if the quadwords are read from ds0 or ds1: 00 reads from the default ds 01 reads from ds0 10 reads from ds1 11 reserved disp_dsusel 1 r indicates the default ds chosen at dispatch. 0ds0 1ds1 dsa 19 r data store address. the source address in the egress data store lma 6 r local memory address. the quadword target address in the shared memory pool (see 7.2.10 shared memory pool on page 198). table 65: rdeds output operand source name size direct indirect description lma 6 r local memory address. the lma will be the input value of the lma incremented by the number of quadword transfers com- pleted by the command. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 169 of 444 the data store address (dsa) can be any address in the ingress data store but the picocode must ensure that no buffer overflow occurs during writing. for example, it is not a good idea to make the dsa point to the last quadword in a 64-byte buffer and set nrofquadword to four. rdids (read ingress data store) command rdids reads from an absolute address in the ingress data store. the data store address (dsa) can be any address in the ingress data store. the picocode must ensure that no buffer overflow occurs during reading. for example, it is not a good idea to make the dsa point to the last quadword in a 64-byte buffer and set nrofquadword to four. table 66: wrids input operand source name size direct indirect description nrofquadword 2 imm16(1..0) gpr(1..0) defines the number of quadwords to be written: 01 1 quadword 10 2 quadwords 11 3 quadwords 00 4 quadwords dsa 19 r data store address. the target address in the ingress data store. the11lsbsofthedsacontaintheaddress.theremaining eight msbs are not used. lma 6 r local memory address. the quadword source address in the shared memory pool (see 7.2.10 shared memory pool on page 198). table 67: wrids output operand source name size direct indirect description lma 6 r local memory address. the lma will be the input value of the lma incremented by the number of quadword transfers com- pleted by the command. table 68: rdids input operand source name size direct indirect description nrofquadword 2 imm16(1..0) gpr(1..0) defines the number of quadwords to be read: 01 1 quadword 10 2 quadwords 11 3 quadwords 00 4 quadwords dsa 19 r data store address. the source address in the ingress data store lma 6 r local memory address. the quadword target address in the shared memory pool (see 7.2.10 shared memory pool on page 198). IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 170 of 444 np3_dl_sec07_epc.fm.01 09/25/00 rdmorei (read more quadword from ingress) command after an ingress frame dispatch, the hardware stores the first n quadwords of the frame in the datapool. rdmorei is used to read more quadwords from the ingress data store. it uses two internal registers that are maintained by the data store coprocessor hardware (current cell/twin address and next quadword address registers) to maintain the current position in the ingress data store and the shared memory pool. during a rdmorei, the hardware automatically reads the bcb to update the current/cell twin register when a cell-boundary is crossed. rdmorei can be executed more than once if more quadwords are required. table 69: rdids output operand source name size direct indirect description lma 6 r local memory address. the lma will be the input value of the lma incremented by the number of quadword transfers com- pleted by the command. table 70: rdmorei input operand source name size direct indirect description nrofquadword 2 imm16(1..0) gpr(1..0) defines the number of quadwords to be read. 01 1 quadword 10 2 quadwords 11 3 quadwords 00 4 quadwords ccta 19 r current cell/twin address. the source address in the ingress data store. initially, this register is set during a dispatch. nqwa 3 r next quadword address.the target address in the datapool. initially, this register is set during a dispatch. table 71: rdmorei output operand source name size direct indirect description ccta 19 r current cell/twin address. this register is updated by hard- ware. executing rdmoree again reads the next quadwords from egress data store. nqwa 3 r next quadword address. this register is updated by hardware. executing rdmoree again causes the quadwords being read to be stored in the next locations in the datapool. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 171 of 444 rdmoree (read more quadword from egress) command after an egress frame dispatch, the hardware stores the first n quadwords of the frame in the datapool. rdmoree is used to read more quadwords from the egress data store. it uses three internal registers that are maintained by the data store coprocessor hardware (dispatch dsusel, current cell/twin address, and next quadword address registers) to maintain the current position in the egress data store and the shared memory pool. during a rdmoree, the hardware automatically reads the bcb memory to update the cur- rent/cell twin register when a twin-boundary is crossed. the rdmoree can be executed more than once if more quadwords are required. edirty (update egress dirty quadwords) command edirty writes a quadword from the datapool array to the egress data store if the quadword has been mod- ified since being loaded into the datapool by a dispatch or a rdmoree command. the data store copro- cessor maintains a register (dirty quadword) which indicates when a quadword within the datapool has been modified. the edirty command uses the dispatch dsu register to determine which egress data store (ds0, ds1, or both) must be updated. when the current cell/twin address is modified due to a rdmoree command, all dirty bits are cleared, indicating no quadwords need to be written back to the egress data store. table 72: rdmoree input operand source name size direct indirect description nrofquadword 2 imm16(1..0) gpr(1..0) defines the number of quadwords to be read. 01 1 quadword 10 2 quadwords 11 3 quadwords 00 4 quadwords dscontrol 2 imm16(3..2) imm12(3..2) defines if the quadwords are read from ds0 or ds1: 00 reads from the default ds 01 reads from ds0 10 reads from ds1 11 reserved disp_dsusel 1 r indicates the default ds chosen at dispatch. 0ds0 1ds1 ccta 19 r current cell/twin address. the source address in the egress data store. initially, this register is set during a dispatch. nqwa 3 r next quadword address. the target address in the datapool. initially, this register is set during a dispatch. table 73: rdmoree output operand source name size direct indirect description ccta 19 r current cell/twin address. this register is updated by hard- ware. executing rdmoree again reads the next quadwords from egress data store. nqwa 3 r next quadword address. this register is updated by hardware. executing rdmoree again causes the quadwords being read to be stored in the next locations in the datapool. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 172 of 444 np3_dl_sec07_epc.fm.01 09/25/00 idirty (update ingress dirty quadwords) command idirty writes a quadword from the datapool array to the ingress data store if the quadword has been mod- ified since being loaded into the datapool by a dispatch or a rdmorei command. the data store coproces- sor maintains a register (dirty quadword) which indicates when a quadword within the datapool has been modified. the idirty command uses the next quadword address to determine which cell within the datapool is represented by the current cell/twin address. when the current cell/twin address is modified due to a rdmorei command, all dirty bits are cleared, indicating no quadwords need to be written back to the ingress data store. edirty inputs operand source name size direct indirect description ccta 19 r current cell/twin address. the source address in the egress data store. initially, this register is set during a dispatch. nqwa 3 r next quadword address. indicates in which cell in the datapool the current cell/twin is valid. 1,2,3,4 : indicates the first cell (first 4 quadwords) is represented by the current cell/twin address. 5,6,7,0 : indicates the second cell (second 4 quadwords) is represented by the current cell/twin address. dirtyqw 8 r this register indicates which quadwords need to be updated. dscontrol 2 imm16(3..2) imm12(3..2) defines if the quadwords are written to ds0, ds1 or both: 00 writes to the default dsu. 01 writes to ds0 10 writes to ds1 11 writes to ds0 and ds1 disp_dsu 2 r the default dsu, initialized at dispatch. table 74: edirty output operand source name size direct indirect description dirtyqw 8 r dirty quadwords. bits which represent the data quadwords that were updated on this command will be reset to ?0?. table 75: idirty inputs operand source name size direct indirect description ccta 19 r current cell/twin address. the source address in the ingress data store. initially, this register is set during a dispatch. nqwa 3 r next quadword address. indicates in which cell in the datapool the current cell/twin is valid. 1,2,3,4 : indicates the first cell (first 4 quadwords) is represented by the current cell/twin address. 5,6,7,0 : indicates the second cell (second 4 quadwords) is represented by the current cell/twin address. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 173 of 444 leasetwin command this command leases a 19-bit twin address from the egress pool of free twins. 7.2.4 the control access bus (cab) coprocessor the cab coprocessor provides interfaces to the cab arbiter and the cab for a thread. a thread must load the operands for a cab access, such as cab address and data. the protocol to access the cab is then han- dled by the cab interface coprocessor. 7.2.4.1 cab coprocessor address map the cab coprocessor has three scalar registers that are accessible to a thread and are shown in table 78 : dirtyqw 8 r this register indicates which quadwords need to be updated. table 76: idirty output operand source name size direct indirect description dirtyqw 8 r dirty quadwords. bits which represent the data quadwords that were updated on this command will be reset to ?0?. table 77: leasetwin output operand source name size direct indirect description ccta 19 r current cell/twin address. contains the address of the newly leased twin. table 78: cab coprocessor address map symbolic register name register number size (bits) access description cabstatus x?00? 3 r status register bit 2 busy bit 1 0 = write access 1 = read access bit 0 arbitration granted cabdata x?01? 32 r/w data to be written to cab, or data read from cab cabaddress x?02? 32 w address used during last cab access table 75: idirty inputs operand source name size direct indirect description IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 174 of 444 np3_dl_sec07_epc.fm.01 09/25/00 7.2.4.2 cab access to np4gs3 structures the control address bus (cab) is the np4gs3's facility for accessing internal registers. the cab is assess- able via picocode and is used for both configuration and operational functions. cab addresses consist of three fields and are defined as follows: the first field, which is comprised of the five most significant bits of the address, selects one of 32 possible functional islands within the device. the correspondence between the encoded functional island value and the functional island name is shown in the cab address, functional island encoding table below. although some functional islands have island_id values, they are not accessed via the cab. these functional islands are the ingress data store, egress data store, and control store. structures in these functional islands are accessed via the data store coprocessor and the tse. the second portion of the cab address consists of the next most significant 23 bits. this address field is seg- mented into structure address and element address. the number of bits used for each segment can vary from functional island to functional island. some functional islands contain only a few large structures while others contain many small structures.the structure address addresses an array within the functional island table 79: cab address field definitions island id structure address element address word addr 5234 32 table 80: cab address, functional island encoding island_id functional island name notes ?00000? ingress data store 1 ?00001? ingress pmm ?00010? ingress eds ?00011? ingress sdm ?00100? embedded processor complex ?00101? spm ?00110? ingress flow control ?00111? embedded powerpc ?01000? control store 1 ?01111? reserved ?10000? egress data store 1 ?10001? egress pmm ?10010? egress eds ?10011? egress sdm ?10100? configuration registers ?10101? dasl ?10110? egress flow control ?10111-11111? reserved 1. these functional islands are not accessible via the cab IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 175 of 444 while the element address addresses an element within the array. the data width of an element is variable and can exceed the 32-bit data width of the cab. the third portion of the cab address consists of a 4-bit word address for selecting 32-bit segments of the ele- ment addressed. this address is necessary for moving structure elements wider than 32-bits across the cab. 7.2.4.3 cab coprocessor commands the cab coprocessor provides the following commands: cabarb (cab arbitration) command cabarb requests to become a master on the cab interface or requests to release the cab after master status has been granted. cabarb does not cause a stall in the clp even if run synchronously. the cab coprocessor always indicates that cabarb was executed immediately, even if the arbiter did not grant the cab interface to the coprocessor. the picocode must release ownership of the cab interface when it is fin- ished accessing the cab or a lockout condition could occur for all non-preempt accesses. cabarb arbitrate for cab access. used by a thread to gain access to the cab. once access is granted, that thread maintains control of the cab until it releases the cab. cabaccess read/write cab. moves data onto or from the cab and the attached cab accessible registers. the source and destination within the dppu are gprs cabpreempt preempt cab. used only by the gfh thread, it allows the gfh to gain control of the cab for a single read/write access, even if the cab has already been granted to another thread. table 81: cab coprocessor commands summary opcode command detail section 0 cabarb cabarb (cab arbitration) command on page 175 1 cabaccess cabaccess command on page 176 3 cabpreempt cabpreempt command on page 176 table 82: cabarb i nput operand source name size direct indirect description start_nend 1 imm16(0) 1 start arbitration. 0 releases arbitration. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 176 of 444 np3_dl_sec07_epc.fm.01 09/25/00 cabaccess command performs a read or write access on the cab. before a cab access can be performed, a cabarb command must have been issued to acquire ownership of the cab interface. cabpreempt command cabpreempt has the same input and output parameters as cabaccess, except that a high-priority access to the cab is performed. no cabarb command is r equired before c abpreempt. if any other coprocessor is cab bus master (because it previously executed a cabarb), cabpreempt takes control of the cab bus and executes the cab read or write. after command execution, control of the cab bus returns to the previous owner. use cabpreempt with care. for example, it might be used in debug mode when the gfh is single stepping one or more other coprocessors. to give a single step command, a cab write must be executed using the cabreempt command because the coprocessor being single stepped may be executing a cabaccess command and become cab bus master. if the gfh used the cabaccess command instead of cabpre- empt, a deadlock would occur. 7.2.5 enqueue coprocessor the enqueue coprocessor manages the interface between a thread and the completion unit and manages the use of the fcbpage that is maintained in the shared memory pool. each thread has three fcbpage locations in which enqueue information about a frame may be maintained. two of the pages improve the per- formance of the completion unit interface when they are alternated during consecutive enqueues. the pico- code written for the thread does not differentiate between these two pages because hardware manages the swap. the thread uses the third page to allow the picocode to create new frames. when a thread issues an enqueue command, the first fcbpage is marked as in-use. if the other fcbpage is available, the coprocessor is not considered ?busy? and will not stall the clp even if the command was issued synchronously. the completion unit fetches the fcbpage from the shared memory pool through the enqueue coprocessor and provides its information to the eds (either ingress or egress as indicated by the enqueue command). the fcbpage is then marked as free. if both fcbpages are marked in use, the enqueue coprocessor is considered busy and stalls the clp if a synchronous command initiated enqueue. to guarantee that fcbpage data is not corrupted, enqueue commands must always be synchronous. note: when an enqueue command is issued and the other location of the fcbpage becomes the ?active? table 83: cabaccess input operand source name size direct indirect description read_nwrite 1 imm12(0) 1 performs a cab read 0performsacabwrite address 32 gpr(31..0) the cab address table 84: cabaccess output operand source name size direct indirect description cabdata 32 r set for cab read command IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 177 of 444 page, the data is not transferred between the fcbpages and should be considered uninitialized. this is an important consideration for picocode written to handle egress multicast frames. 7.2.5.1 enqueue coprocessor address map fcbpage format the fcbpage format varies based on dispatch parameters (ingress or egress frames) and access methods. the fcbpage can be accessed as a defined field, by word, or by quadword. the set of defined fields varies according to the ingress or egress dispatch parameter. fields are mapped into locations of the shared mem- ory pool. fields not defined as a multiple of 8 bits are stored in the least significant bits (right justified) of the byte location. table 85: enqueue coprocessor address map name register address size access description disp_label x?00? 1 r/w indicates whether a label was dispatched to the completion unit for this frame. if the nolabel parameter is not passed during an enqi or enqe command, then this bit is used to determine if the enqueue will be done with or without a label. 0 indicates that a label was not passed to the completion unit for this frame. 1 indicates that a label was passed to the completion unit for this frame. activefcbpage1 x?fc? 384 r/w active fcb page for the current thread. this page is initialized at dispatch. inactivefcbpage1 x?fd? 384 r/w inactive fcb page for the current thread. this page is not ini- tialized at dispatch. this array should never be written. fcbpage2 x?fe? 384 r/w alternate fcbpage figure 50: ingress fcbpage format 01234567 sp (6) abort (1) gt (1) fcinfo (4) wbc (15) fcba (12) 8 9 10 11 12 13 14 15 currentbuffer (11) not used (8) not used (8) tdmu (2) l3stk/idsu (8/4) pib (6) tos (8) 16 17 18 19 20 21 22 23 tb (16) iucnmc (1) priority_sf (2) lid / mid (21 / 17) 24 25 26 27 28 29 30 31 vlanhdr (16) ins_ovlvlan (2) fhf (4) fhe (32) 32 33 34 35 36 37 38 39 not used (8) not used (8) not used (8) not used (8) not used (8) not used (8) not used (8) not used (8) 40 41 42 43 44 45 46 47 countercontrol (14) counterdata (16) counterblockindex (20) IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 178 of 444 np3_dl_sec07_epc.fm.01 09/25/00 table 86: ingress fcbpage description field fcb page offset initialized by dispatch unit enqueue info size (bits) description sp x?00? y n 6 source port of frame abort x?01? y n 1 frame had been marked abort at time of dispatch gt x?02? y n 1 indicates guided traffic fcinfo x?03? y y 4 flow control color and frame drop information. see table 133: flow control information values on page 206. setting this field to x?f? disables flow control. flow control must be disabled when enqueing to the gdq, gfq, gpq or the discard queue. wbc x?04? y n 15 working byte count. the number of bytes available in the ingress data store for this frame at the time it was dispatched. fcba x?06? y y 11 frame control block address for the frame dispatched currentbuffer x?08? y y 11 ingress data store buffer address of the frame dispatched. tdmu x?0c? n y 2 egress target dmu 00 a 01 b 10 c 11 d l3stk/idsu x?0d? n y 8/4 l3stk - when iucnmc = 0 (frame is multicast), this field contains the value of the dll termination offset. the dll termination offset is defined as the number of bytes starting at the beginning of the frame to the position one byte beyond the end of the data link layer. this value is based upon the encapsulation type. typically, this is the same as the start of the layer 3 protocol header, an exception would be for mpls. idsu - data store unit field in the frame header. indicates where the frame should be stored when entering the egress side. used when iucnmc = 1 (frame is unicast). pib x?0e? n y 6 point in buffer. prior to enqueue, indicates location of the first byte of the frame to be sent across the switch interface tos x?0f? y y 8 ip type of service. if the frame is an ip frame, these bits are the tos field in the ip header. otherwise they are initialized to 0?s. tb x?10? n y 16 target blade vector or target blade address. when in 16-blade mode these 16 bits are used as a target blade vector for multicast frames. in all other modes and for uc frames this is a target blade address. as a target blade vector, bit 15 corresponds to target blade address 0, that is, tb(0:15) in 64 blade mode, valid unicast target blade addresses are 0 through 63, multicast addresses are 512 to 65535. iucnmc x?12? n y 1 unicast/multicast indicator 0 multicast frame 1 unicast frame priority_sf x?13? n y 2 priority indicates the user priority assigned to the frame where high priority is indicated by a value of 0. sf is a special field indicator. bit description 0 special field 1priority IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 179 of 444 lid/mid x?14? n y 21/17 lookup id. ingress picocode uses to pass information to the egress picocode. used when iucnmc = 1 (frame is unicast). multicast id: ingress picocode uses to pass information to the egress picocode. used when iucnmc = 0 (frame is multicast). vlanhdr x?18? n y 16 vlan tag ins_ovlvlan x?1a? n y 2 insert or overlay vlan. indicates if the vlan header provided in the vlanhdr scalar register is inserted or overlays an existing vlan tag bit description 0overlayvlan 1 insert vlan fhf x?1b? n y 4 frame header format: 4-bit field used by hardware and set up by picocode. hardware classifier uses this value on the egress side to determine the starting instruction address for the frame. fhe x?1c? n y 32 frame header extension countercontrol x?28? n y 14 passed to flow control for delayed counter manager functions. bits description 13 enable counter operation for this enqueue. counter updates on an enqueue work only when the target is a target blade. counter updates do not occur when enqueueing to the gdq, gfq, gpq, or the discard queue. 12 add/increment 11:8 counter number 7:0 counter definition table index counterdata x?2a? n y 16 data passed to ingress flow control for delayed counter manager add functions counterblockindex x?2c? n y 20 block index passed to ingress flow control for delayed counter manager functions table 86: ingress fcbpage description (continued) field fcb page offset initialized by dispatch unit enqueue info size (bits) description IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 180 of 444 np3_dl_sec07_epc.fm.01 09/25/00 figure 51: egress fcbpage format 01234567 sb (6) eucmc (3) dsusel (1) fcinfo (4) bci (20) 8 9 10 11 12 13 14 15 currtwin (20) type (3) dsu (2) qhd (1) ow (4) 16 17 18 19 20 21 22 23 qid (20) etypeact (3) etypevalue (16) datafirsttwin (19) 24 25 26 27 28 29 30 31 saptr (10) da47_32 (16) da31_0 (32) 32 33 34 35 36 37 38 39 sainsovl (2) mpls_ vlandel (2) crcaction (2) dllstake (6) ttlassist (2) not used (8) not used (8) not used (8) 40 41 42 43 44 45 46 47 countercontrol (14) counterdata (16) counterblockindex (20) table 87: egress fcbpage description field fcb page offset initialized by dispatch unit size (bits) description sb ?00? y 6 source blade eucmc ?01? y 3 egress unicast/multicast bits 000 unicast 001 first multicast 010 middle multicast 011 last multicast 100 unicast static frame enqueue 101 first multicast static frame 110 middle multicast static frame 111 last multicast static frame dsusel ?02? y 1 dispatch and read more interface uses the indicated dsu fcinfo ?03? y 4 flow control color information pulled from the frame header by the hardware classifier. see table 133: flow control information values on page 206 bci ?04? y 20 byte count indicator. passed from the queue to the fcbpage, indicates starting byte location within the first twin, number of data buffers, and ending byte location within the last twin. currtwin ?08? y 20 at dispatch, indicates the first twin address of the frame IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 181 of 444 type ?0c? y 3 type indicates frame type and data store used. type (2:1) 00 frame 01 reserved 10 reserved 11 abort type (0) for gtq, gpq 0dsu0 1dsu1 type(0) for gr0, gb0 0dsu0 1bothdsu0and1 type(0) gr1, gb1 0dsu1 1 both dsu0 and 1 dsu ?0d? y 2 indicates in which dsu(s) the data for this frame is stored. value is dsu(1:0). value description 00 reserved 01 stored in dsu 0 10 stored in dsu 1 11 stored in both dsu 0 and 1 qhd ?0e? n 1 twin header qualifier. indicates type of twin pointed to by currtwin. used for egress frame alteration. 0datatwin 1 header twin ow ?0f? n 4 orphan twin weight. number of twins orphaned by frame alteration actions. when this field is greater than 0, the datafirsttwin scalar must be loaded with the location of the first data twin. when this field is 0, the etypeact and etypevalue scalar registers can be loaded for insert and overlay ethertype frame alterations. qid ?10? n 20 flow queue identifier address datafirsttwin ?14? n 19 address of frame?s first data twin. valid when ow is not 0. etypeact ?15? n 3 ethertype action. valid only when ow is set to 0 etypevalue ?16? n 16 ethertype value used in insert / overlay egress frame alteration saptr ?18? n 10 source address pointer for egress frame alteration. indicates the sa array address used by the e-pmm to locate the source address for egress frame alterations. valid ranges are 0-63. da47_32 ?1a? n 16 most significant bits of a destination address, used by the e-pmm during egress frame alteration da31_0 ?1c? n 32 least significant bits of a destination address, used by the e-pmm during egress frame alteration sainsovl ?20? n 2 egress frame alteration controls for overlay of sa, da, and ethertype (when etypeact is set to ?001?) bit description 1 indicates insert (field value 10) 0 indicates overlay (field value 01) both bits may not be set to 1. (11 = invalid and 00 = no action) table 87: egress fcbpage description field fcb page offset initialized by dispatch unit size (bits) description IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 182 of 444 np3_dl_sec07_epc.fm.01 09/25/00 fcbpage initialization during dispatch during a dispatch to a thread, the hardware classifier and the dispatch unit provide information about the frame being dispatched that is used to initialize some of the fields within the fcbpage. values initialized at the time of dispatch are indicated in table 86 and table 87 . values that are not indicated as initialized at dis- patch are initialized to ?0? for the ?active? fcbpage. mpls_vlandel ?21? n 2 delete vlan tag or mpls label. egress frame alteration controls. removevlantag(bit1setto1) remove mpls label (bit 0 set to 1) crcaction ?22? n 2 egress frame alteration controls for modifying the crc of an ethernet frame. value description 00 no operation 01 reserved 10 append crc 11 overlay crc dllstake ?23? n 6 the value of the dll termination offset. the dll termination offset is defined as the number of bytes starting at the beginning of the frame to the position one byte beyond the end of the data link layer. this value is based upon the encapsulation type. typically, this is the same as the start of the layer 3 protocol header, an exception would be for mpls. ttlassist ?24? n 2 egress frame alteration controls for modifying the time to live field in ip headers or the next hop field in ipx headers. value is ttlassist(1:0) below: value description 00 disabled 01 ipv4, decrement ttl 10 ipx, increment hop count 11 reserved countercontrol ?28? n 14 passed to flow control for delayed counter manager functions bits description 13 enable counter operation for this enqueue. counter updates on an enqueue work only when the target is a target port. counter updates do not occur when enqueing to the grx, gbx, gfq, gpq, gtq or e-gdq. counter updates are supported for the discard port (portid=41) and the wrap ports (portid = 40, 42) 12 add/increment 11:8 counter number 7:0 block definition index counterdata ?2a? n 16 data passed to egress flow control for delayed counter manager add func- tions. counterblockindex ?2c? n 20 block index passed to egress flow control for delayed counter manager functions table 87: egress fcbpage description field fcb page offset initialized by dispatch unit size (bits) description IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 183 of 444 7.2.5.2 enqueue coprocessor commands the following commands are supported by the enqueue coprocessor: enqe (enqueue egress) command enqe enqueues frames to the egress target queues. the qid field in the fcbpage selects the egress target queue. table 90 shows the coding of the qid for this selection. enqe takes a queueclass as a parameter, and some values of queueclass automatically set some bits in the qid field to a predefined value. enqe enqueue egress. enqueues to the egress eds via the completion unit enqi enqueue ingress. enqueues to the ingress eds via the completion unit enqclr enqueue clear. clears (sets all fields to zero in) the specified fcbpage table 88: enqueue coprocessor commands summary opcode command detail section 0enqe enqe (enqueue egress) command on page 183 1enqi enqi (enqueue ingress) command on page 186 2 enqclr enqclr (enqueue clear) command on page 188 table 89: enqe target queues enqde command enqueues a frame in one of these egress target queues target queue description target port/flow queues if the scheduler is disabled, enqueued frames are transmitted on target ports 0 ? 39, and logical ports 40-42. if the scheduler is enabled, enqueued frames are enqueued into the flow queues. gr0 enqueued frames are destined for any gdh (or the gfh when it is enabled for data frame pro- cessing). a unicast frame must be stored in ds0 when queue gr0 is used. a multicast frame must always be stored in both ds0 and ds1. gr1 enqueued frames are destined for any gdh (or the gfh when it is enabled for data frame pro- cessing). a unicast frame must be stored in ds1 when queue gr1 is used. a multicast frame must always be stored in both ds0 and ds1. gb0 same as gr0, but treated by the dispatch unit as lower priority gb1 same as gr1, but treated by the dispatch unit as lower priority gfq enqueued frames in this queue are destined for the gfh gtq enqueued frames in this queue are destined for the gth gpq enqueued frames in the queue are destined for the embedded powerpc discard queue (e-gdq) enqueued frames in this queue are discarded, which involves freeing e-ds space (twins). frames are only discarded when the mcca (multicast counter address) enqueue parameter equals zero, or when the multicast counter itself has the value 1. table 90: egress target queue selection coding scheduler enabled? qid(19-18) target queue class queue address priority target queue yes 00 flow queue qid(10..0) - flow queue IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 184 of 444 np3_dl_sec07_epc.fm.01 09/25/00 when a frame is enqueued, the parameters from the fcbpage parameters are extracted and passed to the egress target queue. enqe takes three parameters: the queueclass, a nolabel flag, and the fcbpage. according to the queue class parameter, bits 19, 18, and 5..0 in the qid field of the fcbpage are changed by the coprocessor according to table 94 . like enqi, enqe does not modify the fcbpage. no 00 target port queue qid(5..0) (tpqid) qid(6) (tppri) 0-39 40 41 42 ports wrap to ingress gfq discard (dpq) wrap to ingress gdq - 11 gqueue qid(2..0) (gqid) - 000 gr0 001 gr1 010 gb0 011 gb1 100 gfq 101 gtq 110 gpq 111 discard (e-gdq) table 91: egress target queue parameters queue type queue select enqueue parameters target port/flow queue qid qid, bci, qhd, ow, datafirsttwin, sb, currtwin, mcca, mpls_vlandel, sainsovl, crcaction, l3stake, ttlassist, dsu, saptr, da, fcinfo, countercontrol, counterdata, counterblockindex gr0, gr1, gb0, gb1, gfq, gtq, gpq qid currtwin, type, bci, mcca, countercontrol, counterdata, counterblockindex discard (e-gdq) qid currtwin, type (see table 92 ), bci, mcca table 92: type field for discard queue type definition 001 discard ds0 010 discard ds1 others reserved table 93: enqe command input operand source name size direct indirect description queueclass 5 imm16(4..0) gpr(4..0) egress queue class as defined in table 94 . table 90: egress target queue selection coding scheduler enabled? qid(19-18) target queue class queue address priority target queue IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 185 of 444 nolabel 1 imm16(5) imm12(5) 0 the cu will use a label if one was dispatched with this frame. this is determined by the status of the disp_label register. 1 the completion unit will not use a label for this enqueue. this enqueue is directly executed and is not part of the frame sequence maintenance. fcbpageid 2 imm16(7..6) imm12(7..6) 00 active fcbpage is enqueued. 10 fcbpage 2 is enqueued. table 94: egress queue class definitions queueclass qid19 qid18 qid2 qid1 qid0 target queue notes 0 ----- reserved 1 0 0 - - - port/flow queue 2 0 0 qid(5..0) = 40 wrap gfq queue 4 3 0 0 qid(5..0) = 41 discard queue (dpq) 4 0 0 qid(5..0) = 42 wrap frame queue 5 1100s grxqueue 1 6 1 1 0 1 s gbx queue 1 7 11100 gfq 8 11101 gtq 9 11110 gpq 10 11111 discardqueue(gdq) 3 15 - - - - - any queue 2 1. the enqe instruction may automatically select the appropriate data store or queue, depending on the dsusel bit. 2. queue class 15 does not modify any qid bits and allows picocode full control of the target queue. 3. the type field is modified: bit 2 is set to 0 and the dsu bits are copied to bits 0 and 1 of the type field. 4. when using queue class 2, 3, or 4, and the scheduler is enabled, it is the responsibility of the picocode to insure that qcb 40, 41 and 42 are initialized for the wrap grq (40), the discard port (41), and wrap data queue (42). note: ?-? - the field is not modified by the enqueue instruction s - the value of the dsusel bit in the fcbpage table 93: enqe command input operand source name size direct indirect description IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 186 of 444 np3_dl_sec07_epc.fm.01 09/25/00 enqi (enqueue ingress) command enqi enqueues frames to the ingress target queues. ingress target queues are selected by means of three fields that are part of the fcbpage: iucnmc, priority_sf, and tdmu. table 96 shows the coding of this selection. when a frame is enqueued the parameters from the fcbpage are extracted and passed to the ingress tar- get queue. table 97 shows the parameters that are passed to the ingress eds. enqi takes three parameters: the queueclass, a nolabel flag, and a fcbpage. according to the queue- class parameter, the priority_sf and tdmu fields in the fcbpage are modified by the enqueue coproces- sor according to table 99 when passed to the ingress eds. for example, to enqueue a unicast frame for table 95: enqi target queues target queue description ingress multicast queue priorities 0/1 enqueued frames are treated as multicast frames. guided frames must be enqueued in a multi- cast queue, even when their destination is a single port. ingress tp queue priorities 0/1 enqueued frames are treated as unicast frames. there are a total of 512 target dmu queues: 256 high priority (priority 0) and 256 low priority. ingress discard queue priorities 0/1 enqueued frames are discarded, which involves freeing ingress buffer space (bcbs and fcbs). discarding frames on ingress consumes ingress scheduler slots, i.e. frames are discarded at 58 bytes per slot. the fcbpage's target blade field (tb) must be set to 0. ingress gpq enqueued frames are destined for the gpq. this queue is currently not supported. ingress gdq enqueued frames are destined for any gdh (or gfh when enabled for data frame processing) ingress gfq enqueued frames are destined for the gfh table 96: ingress target queue selection coding iucnmc priority sf tdmu target queue 0 0 0 - ingress multicast queue ? priority 0 0 1 0 - ingress multicast queue ? priority 1 1 0 0 0 ? 3 ingress tp queue ? priority 0 1 1 0 0 ? 3 ingress tp queue ? priority 1 1010 ingressdiscardqueue?priority0 1110 ingressdiscardqueue?priority1 1x11 ingressgpq 1x12 ingressgdq 1x13 ingressgfq table 97: ingress target queue fcbpage parameters frame type parameters notes uc ethernet fcba, countercontrol, counterdata, counterblockindex, tb, tdmu, fcinfo, priority_sf, iucnmc, lid, idsu, fhf, fhe, vlanhdr, pib, ins_ovlvlan 1 mc ethernet fcba, countercontrol, counterdata, counterblockindex, tb, priority_sf, iucnmc, fcinfo, mid, l3stk, fhf, fhe, vlanhdr, pib, ins_ovlvlan 1 1. pib must equal zero (which is the default value after dispatch of an ingress frame). IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 187 of 444 transmission, the picocode prepares the fcbpage, including the priority and tp fields and invokes enqi with queueclass set to 5. enqi does not modify the fcbpage. for example, if the queueclass parameter is set to txq, the sf field is set to ?0?. this means that in the sf field received by the completion unit and passed to the ingress-eds is modified to ?0?. the sf field in the fcbpage is not modified. table 98: enqi command input operand source name size direct indirect description queueclass 5 imm16(4..0) gpr(4..0) table 99: ingress-queue class definition on page 187 nolabel 1 imm16(5) imm12(5) 0 the cu will use a label if one was dispatched with this frame. this is determined by the status of the disp_label register. 1 the completion unit will not use a label for this enqueue. this enqueue is directly executed and is not part of the frame sequence maintenance. fcbpageid 2 imm16(7..6) imm12(7..6) 00 active fcbpage 1 is enqueued. 10 fcbpage 2 is enqueued. table 99: ingress-queue class definition queue class symbolic name iucnmc priority sf tdmu target queue 0dq1 - 1 0 discard queue. picocode must set the priority field. tb field must be set to 0 by the picocode. fcinfo field must be set to x?f?. 1 gpq 1 1 1 1 gph queue. fcinfo field must be set to x?f?. 2 i-gdq 1 1 1 2 gdh queue. fcinfo field must be set to x?f?. 4 gfq 1 1 1 3 gfh queue. fcinfo field must be set to x?f?. 5txq - - 0 - multicast queue or target port queue (transmission queues). picocode must set iucnmc and tp fields. 7anyq - - - - any queue. picocode must set iucnmc, priority, sf and tp fields. note: a ?-? means the fcbpage field is not modified by the enqi command when passed to the ingress-eds. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 188 of 444 np3_dl_sec07_epc.fm.01 09/25/00 enqclr (enqueue clear) command enqclr takes one parameter, the fcbpage, and fills the entire fcbpage register with zeros. 7.2.6 checksum coprocessor the checksum coprocessor generates checksums using the algorithm found in the ietf network working group rfc 1071 computing the internet checksum (available at http://www.ietf.org ). as such, it performs its checksum operation on half word data with a half word checksum result. 7.2.6.1 checksum coprocessor address map table 100: enqclr command input operand source name size direct indirect description fcbpageid 2 imm16(7..6) imm12(7..6) indicates which fcb is to be cleared by the command. 00 active fcbpage is cleared. 10 fcbpage 2 is cleared. table 101: enqclr output operand source name size direct indirect description fcbpage 384 array the fcbpage array indicated by the input fcbpageid will be reset to all ?0?s. table 102: checksum coprocessor address map name register (array) number access size (bits) description chksum_stat x?00? r 2 status of checksum coprocessor bits description 1 insufficient indicator (if set to 1) 0 bad checksum (if set to 1) chksum_acc x?01? r/w 16 when writing this register, the value is a checksum. when reading this register, the value is a header checksum (the one?s comple- ment of a checksum). chksum_stake x?02? r/w 10 pointer into data store coprocessor arrays where checksum is to be performed. bits description 9:8 data store coprocessor array number 7:0 byte offset into the array chksum_length x?03? r/w 8 working length remaining in the checksum calculation. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 189 of 444 7.2.6.2 checksum coprocessor commands data for the checksum coprocessor must be in one of the data store coprocessor?s arrays. the commands to the checksum coprocessor include: when an ip is indicated, the starting location (i.e. stake) for the layer 3 header is passed. the hardware determines the length of the ip header from the header length field and loads this value into the length scalar register. when generating the checksum, a value of zero is substituted for the half word that contains the cur- rent checksum. when cell header skip is indicated, the cell header in the egress frame is skipped in checksum operations. see the datapool for egress frames on page 163 for more details of cell header skip. gengen generate checksum. generates a checksum over a data block with a specified length. options of this command include initiating a new checksum operation or continuing a checksum where a previous checksum has left off. variations of this command include: genip (generate ip checksum) gengenx (generate checksum with cell header skip) genipx (generate ip checksum with cell header skip) chkgen check checksum. checks a checksum over a data block with a specified length. options of this command include initiating a new checksum operation or continuing a checksum where a previous checksum has left off. variations of this command include: chkip (check ip checksum) chkgenx (check checksum with cell header skip) chkipx (check ip checksum with cell header skip) table 103: checksum coprocessor commands summary opcode command detail section 0gengen gengen/gengenx commands on page 190 1genip genip/genipx commands on page 191 2 chkgen chkgen/chkgenx commands on page 191 3 chkip chkip/chkipx commands on page 192 4gengenx gengen/gengenx commands on page 190 5genipx genip/genipx commands on page 191 6chkgenx chkgen/chkgenx commands on page 191 7 chkipx chkip/chkipx commands on page 192 IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 190 of 444 np3_dl_sec07_epc.fm.01 09/25/00 gengen/gengenx commands table 104: gengen/gengenx command inputs operand source name size direct indirect description load new stake 1 imm(15) imm(11) indicates: 1 stake value is passed in the command. 0 stake value is in chksum_stake. clear accumulation 1 imm(14) imm(10) chksum_acc contains the seed for the checksum opera- tion.the value in this register indicates whether to use or clear the data in chksum_acc. 0 use data 1 clear chksum_acc stake argument 10 imm(9:0) gpr(25:16) the new stake value to be used for the checksum operation if the load new stake argument is ?1?. chksum_stake 10 r thestakevaluetobeusedforthechecksumoperationifthe load new stake argument is ?0?. chksum_acc 16 r contains the seed for the next checksum operation if the ?clear accumulation? argument is a ?0?. (otherwise there is no data in chksum_acc). chksum_length 8 r the number of halfwords to read when calculating the check- sum. table 105: gengen/gengenx/genip/genipx command outputs operand source name size direct indirect description return code 1 cpei signal 0 ko, operation failed because there was not enough data in the datapool 1 ok, operation completed successfully. chksum_stat 2 r status of checksum coprocessor bits description 1 insufficient data in datapool 0 bad checksum chksum_stake 10 r stake register. points to the halfword of data following the last halfword used in the checksum command. chksum_acc 16 r the seed for the next checksum operation contains the resulting checksum if the return code is ok. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 191 of 444 genip/genipx commands for genip/genipx command outputs, see table 105: gengen/gengenx/genip/genipx command outputs on page 190. chkgen/chkgenx commands table 106: genip/genipx command inputs operand source name size direct indirect description load new stake 1 imm(15) imm(11) indicates: 1 stake value is passed in the command. 0 stake value is in chksum_stake. clear accumulation 1 imm(14) imm(10) chksum_acc contains the seed for the checksum opera- tion.the value in this register indicates whether or not to use or clear the data in chksum_acc. 0 use data 1 clear chksum_acc. clear ip count 1 imm(13) imm(9) stake argument 10 imm(9:0) gpr(25:16) the new stake value to be used for the checksum operation if the load new stake argument is ?1?. chksum_stake 10 r thestakevaluetobeusedforthechecksumoperationifthe load new stake argument is ?0?. chksum_acc 16 r contains the seed for the next checksum operation if the ?clear accumulation? argument is a ?0?. (otherwise there is no data in chksum_acc). table 107: chkgen/chkgenx command inputs operand source name size direct indirect description load new stake 1 imm(15) imm(11) indicates: 1 stake value is passed in the command. 0 stake value is in chksum_stake. stake argument 10 imm(9:0) gpr(25:16) the new stake value to be used for the checksum operation if the load new stake argument is ?1?. chksum_stake 10 r thestakevaluetobeusedforthechecksumoperationifthe load new stake argument is ?0?. chksum_acc 16 r this is the checksum to be verified. chksum_length 8 r the number of halfwords to read when calculating the check- sum. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 192 of 444 np3_dl_sec07_epc.fm.01 09/25/00 chkip/chkipx commands for chkip/chkipx command outputs, see table 108: chkgen/chkgenx/chkip/chkipx command outputs on page 192. results of the commands are found in chksum_acc, chksum_stake, and the 1-bit return code to the clp. chksum_acc contains the result of the checksum calculation. chksum_stake contains the byte location fol- lowing the last half word included in the checksum. the return code indicates the operation completed suc- cessfully or was verified. the status register may need to be read to determine the status on a bad return code. 7.2.7 string copy coprocessor the string copy coprocessor extends the dppu?s capabilities to move blocks of data without tying up the clp. the data is moved within the shared memory pool and can start and end on any byte boundary within a defined array. table 108: chkgen/chkgenx/chkip/chkipx command outputs operand source name size direct indirect description return code 1 cpei signal 0 ko, operation failed. check status register for reason. 1 ok, operation completed successfully. chksum_stat 2 r status of checksum coprocessor bits description 1 insufficient data in datapool 0 bad checksum chksum_stake 10 r stake register. points to the halfword of data following the last halfword used in the checksum command. chksum_acc 16 r the seed for the next checksum operation. if equal to 0 the checksum was correct. table 109: chkip/chkipx command inputs operand source name size direct indirect description load new stake 1 imm(15) imm(11) indicates: 1 stake value is passed in the command. 0 stake value is in chksum_stake. clear ip count 1 imm(13) imm(9) stake argument 10 imm(9:0) gpr(25:16) the new stake value to be used for the checksum operation if the load new stake argument is ?1?. chksum_stake 10 r thestakevaluetobeusedforthechecksumoperationifthe load new stake argument is ?0?. chksum_acc 16 r this is the checksum to be verified. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 193 of 444 7.2.7.1 string copy coprocessor address map 7.2.7.2 string copy coprocessor commands strcopy (string copy) command strcopy moves multiple bytes of data between arrays in the shared memory pool. the clp passes the start- ing byte locations of the source and destination data blocks, and the number of bytes to move. table 110: string copy coprocessor address map name register number size (bits) access description strcpy_saddr x?00? 14 r/w the source address for the data to be copied: bit description 14 cell header skip access mode 13:10 coprocessor number 9:8 array number from coprocessor address maps 7:0 byte offset within the array strcpy_daddr x?01? 14 r/w the destination address for the data to be copied: bit description 14 cell header skip access mode 13:10 coprocessor number 9:8 array number from coprocessor address maps 7:0 byte offset within the array strcpy_bytecnt x?02? 8 r the number of bytes remaining to be moved. this is a working reg- ister. once the coprocessor starts, this register will no longer be valid (it will show the number of bytes remaining). table 111: string copy coprocessor commands summary opcode command detail section 0 strcopy strcopy (string copy) command on page 193 table 112: strcopy command input operand source name size direct indirect description strcpy_saddr 14 r source address. see table 110: string copy coprocessor address map on page 193 strcpy_daddr 14 r destination address. see table 110: string copy coprocessor address map on page 193 numbytes 8 imm(7:0) gpr(7:0) number of bytes to transfer IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 194 of 444 np3_dl_sec07_epc.fm.01 09/25/00 7.2.8 policy coprocessor the policy coprocessor provides an interface to the policy manager for threads. a thread requests an update to the "color" of a frame through this interface. frame color is part of the network processor's configurable flow control mechanism which determines what actions may be taken on the frame. a thread must wait until the policy manager, via the policy coprocessor, returns a result. 7.2.8.1 policy coprocessor address map 7.2.8.2 policy coprocessor commands polaccess (access policy manager) command polaccess requests that the policy manager accesses the policy control block for the flow that this frame is a member of. operands include the policy control block address, the length of the packet (usually the ip packet length), and the color currently assigned to the frame. the result returned is a new frame color. table 113: strcopy command output operand source name size direct indirect description strcpy_saddr 14 r source address. the offset field of the source address will be incremented by the number of bytes transferred. strcpy_daddr 14 r destination address. the offset field of the destination address will be incremented by the number of bytes transferred. numbytes 8 r this field is 0. table 114: policy coprocessor address map name register number size (bits) access description polcolor x?00? 2 r/w both the color that is passed to the policy manager and the result color that is passed back from the policy manager polpktlen x?01? 16 r/w the packet length sent to the policy manager polcba x?02? 20 r a value of the policy control block address that was found in a leaf after the frame has been classified and a search was per- formed table 115: policy coprocessor commands summary opcode command detail section 0 polaccess polaccess (access policy manager) command on page 194 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 195 of 444 7.2.9 counter coprocessor the counter coprocessor provides an interface to the counter manager for threads. the counter coproces- sor has an eight-deep queue for holding counter access commands issued by any of the four threads run- ning in each dppu. except for counter reads, the counter coprocessor will not stall the clp on synchronous commands unless the queue is full. this allows for one thread to have multiple counter commands outstand- ing simultaneously. for example one of the threads may have all the outstanding commands in the queue or each thread may have two each. normal coprocessor operation would only allow one outstanding command per thread. 7.2.9.1 counter coprocessor address map 7.2.9.2 counter coprocessor commands the counter coprocessor provides the following commands: table 116: polaccess input operand source name size direct indirect description policy cba 20 gpr(19:0) polcba address polcolor 2 r policy color polpktlen 16 r policy packet length table 117: polaccess output operand source name size direct indirect description polcolor 2 r returned policy color table 118: counter coprocessor address map name register number size (bits) access description ctrdatalo x?00? 32 r/w counter data low. this register holds the least significant 32 bits of a counter on a read commands. on write or add commands the lower 16 bits serve as the data passed to the counter manager. (only bits 15..0 are write accessible). ctrdatahi x?01? 32 r counter data high. this register holds the most significant 32 bits of a counter on a read commands. ctrcontrol x?02? 12 r/w counter control. the bits have the following meaning: 11:8 = counter number - defines which counter in the counterblock should be updated. 7:0 = block definition index - an index in the counterdefmem. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 196 of 444 np3_dl_sec07_epc.fm.01 09/25/00 ctrinc (counter increment) command ctrinc performs an access to the central counter manager to increment a counter. this command does not cause synchronous commands to stall if the counter coprocessor queue is not full. ctrinc counter increment. initiates a modify and increment command to the counter manager. ctradd counter add. initiates a modify and add command to the counter manager. the coprocessor passes the counter manager a 16-bit value to add to the indicated counter. ctrrd counter read. initiates a read and no clear command to the counter manager. the counter manager returns the counter value to the counter coprocessor and leaves the counter unmodified. ctrrdclr counter read with counter clear. initiates a read and clear command to the counter manager. the counter manager returns the counter value to the counter coprocessor and resets the counter. ctrwr15_0 counter write bits 15:0 of a counter. initiates a write command to the counter manager. the coprocessor passes a 16-bit value to be loaded into bits 15:0 of the counter. uses lsb of counter data low register. ctrwr31_16 counter write bits 31:16 of a counter. initiates a write command to the counter manager. the coprocessor passes a 16-bit value to be loaded into bits 31:16 of the counter. uses lsb of counter data low register. table 119: counter coprocessor commands summary opcode command detail section 0ctrinc ctrinc (counter increment) command on page 196 1ctradd ctradd (counter add) command on page 197 4 ctrrd ctrrd (counter read) / ctrrdclr (counter read clear) command on page 197 5 ctrrdclr ctrrd (counter read) / ctrrdclr (counter read clear) command on page 197 6 ctrwr15_0 ctrwr15_0 (counter write 15:0) / ctrwr31_16 (counter write 31:16) command on page 197 7 ctrwr31_16 ctrwr15_0 (counter write 15:0) / ctrwr31_16 (counter write 31:16) command on page 197 table 120: ctrinc input operand source name size direct indirect description blockindex 6 or 20 gpr(19..0) defines a counterblock within an array of counterblocks ctrcontrol 12 gpr(11..0) counter control. the bits have the following meaning: 11:8 = counter number - defines which counter in the counterblock should be updated. 7:0 = block definition index - an index in the counterdefmem. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 197 of 444 ctradd (counter add) command ctradd performs an access to the central counter manager to add a 16-bit value to a counter. this command will not cause synchronous commands to stall if the counter coprocessor queue is not full. ctrrd (counter read) / ctrrdclr (counter read clear) command ctrrd / ctrrdclr performs an access to the central counter manager to read a counter. the ctrrdclr com- mand also clears the counter after the read is performed. ctrwr15_0 (counter write 15:0) / ctrwr31_16 (counter write 31:16) command ctrwr15_0/ctrwr31_16 performs an access to the central counter manager to write a 16-bit value to a counter. the ctrwr15_0 writes the 16-bit data value to bits 15..0 of the counter and the ctrwr31_16 writes the value to bits 31..16 of the counter. this command does not cause synchronous commands to stall if the counter coprocessor queue is not full. table 121: ctradd input operand source name size direct indirect description blockindex 6 or 20 gpr(19..0) defines a counterblock within an array of counterblocks ctrdatalo 16 r(15..0) the value to be added to the counter. ctrcontrol 12 gpr(11..0) counter control. the bits have the following meaning: 11:8 = counter number - defines which counter in the counterblock should be updated. 7:0 = block definition index - an index in the counterdefmem. table 122: ctrrd/ctrrdclr input operand source name size direct indirect description blockindex 6 or 20 gpr(19..0) defines a counterblock within an array of counterblocks ctrcontrol 12 gpr(11..0) counter control. the bits have the following meaning: 11:8 = counter number - defines which counter in the counterblock should be updated. 7:0 = block definition index - an index in the counterdefmem. table 123: ctrrd/ctrrdclr output operand source name size direct indirect description ctrdatalo 32 r for 32-bit counters this register contains the value of the counter once the read is performed. for 64-bit counters, this register contains the least significant 32 bits of the counter once thereadisperformed. ctrdatahi 32 r for 32-bit counters this register is not valid. for 64-bit counters, this register contains the most significant 32 bits of the counter once the read is performed. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 198 of 444 np3_dl_sec07_epc.fm.01 09/25/00 7.2.10 shared memory pool the 4 k byte shared memory pool is used by all threads running in the dppu. 1 k bytes are used by each thread and are subdivided into the following areas per thread: table 124: ctrwr15_0/ctrwr31_16 input operand source name size direct indirect description blockindex 6 or 20 gpr(19..0) defines a counterblock within an array of counterblocks ctrdatalo 16 r(15..0) thevaluetobewrittentothecounter. ctrcontrol 12 gpr(11..0) counter control. the bits have the following meaning: 11:8 = counter number - defines which counter in the counterblock should be updated. 7:0 = block d efinition index - an index in the counterdefmem. table 125: shared memory pool quadword address owning coprocessor array 0-2 enqueue fcb page 1a 3 data store configuration quadword 4-6 enqueue fcb page 1b 7 clp stack 0 8-10 enqueue fcb page 2 11 clp stack 1 12-15 data store scratch memory 0 16-23 data store datapool 24-31 data store scratch memory 1 32-47 tse tree search results area 0 40-47 tse tree search results area 1 48-63 tse tree search results area 2 56-63 tse tree search results area 3 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 199 of 444 7.3 interrupts and timers the np4gs3 provides a set of hardware and software interrupts and timers for the management, control, and debug of the processor. when an interrupt event occurs or a timer expires a task is scheduled to be pro- cessed by the embedded processor complex. the interrupt or timer task does not preempt threads currently processing other tasks, but is scheduled to be dispatched to the next idle thread that is enabled to process the interrupt or timer. the starting address of the task is determined by the interrupt or timer class and read from table 128: port configuration memory content on page 201. 7.3.1 interrupts the interrupt mechanism within the np4gs3 has several registers: the interrupt vector registers 0-3, inter- rupt mask register 0-3, interrupt target register 0-3. and the software interrupt registers. 7.3.1.1 interrupt vector registers the interrupt vector register is a collection of interrupts that will share a common code entry point upon dis- patch to a thread in the epc. a bit representing the individual interrupt within the interrupt vector register is only set on the initial event of the interrupt. even if the interrupt vector register is cleared, an outstanding interrupt will not set the bit in the register again until it is detected that the interrupt condition is going from an inactive to active state. picocode can access the interrupt vector registers either through the dashboard or through the master copy. the interrupt vector register is cleared when it is read from its master copy address. when read from the dashboard, the register is not cleared. 7.3.1.2 interrupt mask registers the interrupt mask registers have a bit to correspond with each bit in the interrupt vector registers. the interrupt mask registers indicate which interrupts in the interrupt vector registers cause an task to be scheduled for processing by the epc. the interrupt mask registers have no affect on the setting of the inter- rupt vector registers. 7.3.1.3 interrupt target registers the interrupt target register indicates which thread types in the epc are enabled to process the interrupt of a given class 0-3. 7.3.1.4 software interrupt registers the software interrupt registers provide 12 unique interrupts (three in each of the four classes) that can be defined by software and accessed through cab accesses. writing a software interrupt register sets the cor- responding bit within the interrupt vector register 0-3 and has the same effect as a hardware defined inter- rupt. 7.3.2 timers the np4gs3 has four timer interrupt counters that can be used to generate delayed interrupts to the epc. 7.3.2.1 timer interrupt counters timer interrupt counters 0-2 are 24 bits in length and decrement at 1 ms intervals. timer interrupt counter 3 IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 200 of 444 np3_dl_sec07_epc.fm.01 09/25/00 is 32 bits in length and decrements at 10 s intervals. the timer interrupt counters are activated by writing a non-zero value to the register. when the timer decrements to a zero value it will schedule a timer task to be processed by the epc 7.3.3 port configuration memory table 128: port configuration memory content on page 201 provides control, default, and software defined information on each dispatch and is passed to the thread to be stored in the configuration quadword array in the data store coprocessor. 7.3.3.1 port configuration memory index definition the port configuration memory index consists of 64 entries that are indexed based upon multiple parameters including ingress port, egress queues, timers, and interrupts as defined in table 126 . table 126: port configuration memory index port configuration memory index definition 0 .. 39 ingress sp (from gdq) 40 ingress wrap frame (i-gdq) 41 reserved 42 i-gfq 43 ingress wrap guided 44 reserved 45 gpq 46 egress gfq 47 gtq 48 egressframeineitherds0ords1 49 egressframeinds0andds1 50 reserved 51 reserved 52 reserved 53 reserved 54 egressabortofframeineitherds0ords1 55 egress abort of frame in ds0 and ds1 56 interrupt 0 57 interrupt 1 58 interrupt 2 59 interrupt 3 60 timer 0 61 timer 1 62 timer 2 63 timer 3 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 201 of 444 7.3.4 port configuration memory contents definition bits 127 .. 24 are software defined and are for use by the picocode. the remaining bits are used by the hard- ware, as defined in table 128 . table 127: relationship between sp field, queue, and port configuration memory index sp field in fcb1 queue port configuration memory index 0 .. 39 (denotes physical port) gdq 0 .. 39 0 .. 39 (denotes physical port) i-gfq 42 40 (denotes wrap port) gdq 40 40 (denotes wrap port) i-gfq 43 table 128: port configuration memory content field name bits description 127 .. 24 for software use. pos_ac 23 0 ac not present 1acpresent ethernet/ppp 22 0 ppp port 1 ethernet port codeentrypoint 21 .. 6 the default code entry point. can be overwritten by the hardware classifier (if enabled). culabgenenabled 5 0 no label is generated. 1 the hardware classifier generates a label that is used by the comple- tion unit to maintain frame sequence. this field must be set to 0 for port configuration memory entries 54, 55 (repre- senting aborted frames on the egress), 56-59 (interrupts), and 60-63 (timers). hardwareassistenabled 4 0 hardware classifier is disabled 1 hardware classifier is enabled and the classifier may overwrite the codeentrypoint reserved 3 .. 2 reserved. set to ?00?. numberofquadwords 1 .. 0 defines the number of quadwords that the dispatch unit will read from the frame and store in the datapool. a value of ?00? represents four quadwords. for port configuration memory entries 56-63 (interrupts and timers), this field is ignored and the dispatch unit will not write any quadword into the datapool. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 202 of 444 np3_dl_sec07_epc.fm.01 09/25/00 7.4 hardware classifier the hardware classifier provides hardware assisted parsing of the ingress and egress frame data that is dis- patched to a thread. the results are used to precondition the state of a thread by initializing the thread?s gen- eral purpose and coprocessor scalar registers along with the registers? resources and a starting instruction address for the clp. parsing results indicate the type of layer 2 encapsulation, as well as some information about the layer 3 frame. recognizable layer 2 encapsulations include ppp, 802.3, dix v2, llc, snap header, and vlan tagging. reported layer 3 information includes ip and ipx network protocols, five pro- grammable network protocols, the detection of option fields, and ip transport protocols (udp and tcp). if enabled, the hardware classifier also generates labels that are passed to the completion unit with a thread identifier. the cu uses them to maintain frame order within a flow. 7.4.1 ingress classification ingress classification, the parsing of frame data which originated in the ingress eds and is now being passed from the dispatch unit to the dppu, can be applied to ethernet/802.3 frames with the following layer 2 encapsulation: dix v2, 802.3 llc, snap header, and vlan tagging. classification can also be done on pos frames using the point-to-point protocol with or without the ac field present (pos_ac) field. 7.4.1.1 ingress classification input the hardware classifier needs the following information to classify an ingress frame: port configuration memory table entry ( table 128 on page 201). the hardware classifier uses the fol- lowing fields: - codeentrypoint - the default starting instruction address. - hardwareassistenabled - culabgenenabled - ethernet/ppp -posac frame data. four quadwords must be dispatched (per frame) for ingress classification. protocol identifiers: the hardware classifier compares the values in the protocol identifier registers with the values of the fields in the frame that correspond to those identifiers to determine if one of the config- ured protocols is encapsulated in the frame. the hardware classifier supports seven ethernet protocols (five of which are configurable) and eight point-to-point protocols (five of which are configurable). two registers need to be configured for each ethernet protocol, the ethernet type value and an 802.2 service access point value. the protocol identifiers are configured from the cab. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 203 of 444 table 129: protocol identifiers cab address access bits description x?2500 0000? r/w 16 ethernet type for protocol 0 x?2500 0010? r/w 16 ethernet type for protocol 1 x?2500 0020? r/w 16 ethernet type for protocol 2 x?2500 0030? r/w 16 ethernet type for protocol 3 x?2500 0040? r/w 16 ethernet type for protocol 4 x?2500 0050? r 16 ethernet type for ipx (x?8137?) x?2500 0060? r 16 ethernet type for ip. (x?0800?) x?2500 0070? 16 reserved x?2500 0080? r/w 16 point to point type for protocol 0 x?2500 0090? r/w 16 point to point type for protocol 1 x?2500 00a0? r/w 16 point to point type for protocol 2 x?2500 00b0? r/w 16 point to point type for protocol 3 x?2500 00c0? r/w 16 point to point type for protocol 4 x?2500 00d0? r 16 point to point type for ipx (x002b?) x?2500 00e0? r 16 point to point type for ip. (x0021?) x?2500 00f0? r 16 point to point control type frame (msbs of type field is ?1?) x?2500 0100? r/w 8 service access point for protocol 0 x?2500 0110? r/w 8 service access point type for protocol 1 x?2500 0120? r/w 8 service access point type for protocol 2 x?2500 0130? r/w 8 service access point type for protocol 3 x?2500 0140? r/w 8 service access point type for protocol 4 x?2500 0150? r 8 service access point type for ipx (x?e0?) x?2500 0160? r 8 service access point type for ip. (x?06?) x?2500 0170? 8 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 204 of 444 np3_dl_sec07_epc.fm.01 09/25/00 7.4.1.2 ingress classification output the outputs of the ingress hardware classification are: the starting instruction address that is stored in the hccia table. this address is only used when the hardware classification is enabled. when the hardware classification is disabled, or if a protocol match is not found, the code entry point from the port configuration memory table ( table 128: port configuration memory content on page 201) is used as the starting instruction address and is passed to the thread. if a protocol match does occur, the starting instruction address is retrieved from the last 24 entries of the hccia table. hccia values are configured from the cab. the address into hccia are provided in ta bl e 130: hccia table on page 204. table 130: hccia table hccia cab address bits classification x?2500 0400? x?2500 05f0? 16 egress locations (see section 7.4.2.1 egress classification input on page 206) x?2500 0600? 16 ethernet protocol 0 classification with no 802.1q vlan x?2500 0610? 16 ethernet protocol 1 classification with no 802.1q vlan x?2500 0620? 16 ethernet protocol 2 classification with no 802.1q vlan x?2500 0630? 16 ethernet protocol 3 classification with no 802.1q vlan x?2500 0640? 16 ethernet protocol 4 classification with no 802.1q vlan x?2500 0650? 16 ethernet ipx classification with no 802.1q vlan x?2500 0660? 16 ethernet ip classification with no 802.1q vlan x?2500 0670? 16 ingress aborted frame at time of dispatch x?2500 0680? 16 ethernet protocol 0 classification with 802.1q vlan x?2500 0690? 16 ethernet protocol 1 classification with 802.1q vlan x?2500 06a0? 16 ethernet protocol 2 classification with 802.1q vlan x?2500 06b0? 16 ethernet protocol 3 classification with 802.1q vlan x?2500 06c0? 16 ethernet protocol 4 classification with 802.1q vlan x?2500 06d0? 16 ethernet ipx classification with 802.1q vlan x?2500 06e0? 16 ethernet ip classification with 802.1q vlan x?2500 06f0? 16 ethernet vlan frame with an erif x?2500 0700? 16 point to point protocol 0 classification x?2500 0710? 16 point to point protocol 1 classification x?2500 0720? 16 point to point protocol 2 classification x?2500 0730? 16 point to point protocol 3 classification x?2500 0740? 16 point to point protocol 4 classification x?2500 0750? 16 point to point ipx classification x?2500 0760? 16 point to point ip classification x?2500 0770? 16 point to point control frame IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 205 of 444 ingress protocol type register contains the output of the ingress hardware classifier. this data store coprocessor register is loaded with the protocol identifier that identifies the frame for the given encapsulation type. the fields in the frame data that correspond to data store coprocessor register settings (see table 131 ) are passed to the ingress protocol type register. if a vlan tagged frame with an e-rif field is present within the frame, or if the hardware classifier is disabled, this field is invalid. dll termination offset if the hardware classifier is enabled, the dll termination offset is loaded into gpr r0. the dll termina- tion offset is defined as the number of bytes, starting at the beginning of the frame, to the position one byte beyond the end of the data link layer. this value is based upon the encapsulation type. typically, this is the same as the start of the layer 3 protocol header, an exception would be for mpls. classification flags: if the hardware classifier is enabled, classification flags will be loaded into the thread?s gpr r1. table 131: protocol identifiers for frame encapsulation types frame encapsulation type data store coprocessor register setting snap ethernet type dix v2 ethernet type sap dsap/ssap point to point protocol point to point type table 132: general purpose register bit definitions for ingress classification flags bit definition bit 15 protocol 7 detected bit 14 protocol 6 detected bit 13 protocol 5 detected bit 12 protocol 4 detected bit 11 protocol 3 detected bit 10 protocol 2 detected bit 9 protocol 1 detected bit 8 protocol 0 detected bit 7 ?0? bit 6 indicates ip options field present bit 5 dix encapsulation bit 4 indicates sap encapsulation bit 3 indicates snap encapsulation bit 2 indicates 802.1q vlan frame bit 1 indicates the 802.1q vlan id was non-zero bit 0 indicates an erif present IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 206 of 444 np3_dl_sec07_epc.fm.01 09/25/00 flow control information the hardware classifier initializes the fcbpage?s flow control information (fcinfo) field. the field?s value is based on ip frame information that includes the frame color indicated by bits 4:3 of the ip header?s tos field and the tcp header?s syn bit. the hardware classifier never sets fcinfo field to ?1111? but once the field is in the fcbpage it can be written by picocode to be a ?1111?. 7.4.2 egress classification egress classification, the parsing of frame that originated in the egress eds and is being transferred from the dispatcher to the dppu is limited to choosing a starting instruction address and generating a label to pass to the completion unit. 7.4.2.1 egress classification input for egress frames, the hardware classifier needs the following information to classify the frame: port configuration memory table entry ( table 128 on page 201). the hardware classifier uses the fol- lowing fields: - codeentrypoint- the default starting instruction address - hardwareassistenabled - culabgenenabled frame data. two quadwords must be dispatched (per frame) for egress classification. table 133: flow control information values fcinfo definition 0000 tcp - green 0001 tcp - yellow 0010 tcp - red 0011 non-ip 0100 udp - green 0101 udp - yellow 0110 udp - red 0111 reserved 1000 tcpsyn- green 1001 tcpsyn - yellow 1010 tcpsyn - red 1011 reserved 1100 other ip - green 1101 other ip - yellow 1110 other ip - red 1111 disable flow control IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 207 of 444 7.4.2.2 egress classification output the outputs of the egress hardware classification are: starting instruction address. the starting instruction address stored in the hccia memory is only used when the hardware classifica- tion is enabled. when the hardware classification is disabled, the code entry point from the port config- uration memory table ( table 128: port configuration memory content on page 201) is used as the starting instruction address and is passed to the thread. if a protocol match does occur, the starting instruction address is retrieved from the first 32 entries of the hccia. the address into hccia is given by the uc field and by the fhf field in the frame header: frame data offset gpr r0 is always (i.e. also when the hardware classification is disabled) set according to table 58: egress frames datapool quadword addresses on page 164 table 134: hccia index definition 14 uc fhf IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 208 of 444 np3_dl_sec07_epc.fm.01 09/25/00 7.5 policy manager the policy manager is a hardware assist of the embedded processor complex that performs policy manage- ment on up to 1 k ingress flows. it supports four management algorithms. one algorithm pair is "single rate three color marker," operated in color-blind or color aware mode. the other is "two rate three color marker," operated again in color-blind or color-aware mode. the algorithms are specified in ietf rfcs 2697 and 2698. the algorithms are specified in ietf rfcs 2697 and 2698 (available at http://www.ietf.org ). the policy manager maintains up to 1024 leaky bucket meters with selectable parameters and algorithms. the picocode sends the policy manager a policy management control block address (polcba), a color, and a packet length for each incoming packet. according to the policy management control block (polcb), two token counters stored in internal memory are regularly incremented (subject to an upper limit) by a rate spec- ified in the polcb and, when a packet arrives, are decremented by one of four possible algorithms (depend- ing upon the incoming packet length). after both actions are complete, the token counters generally have new values and a new color is returned to the picocode. in addition there are three 10-bit wide packet counters in the polcb (redcnt, yellowcnt, and greencnt) that use the output packet colors to count the number of bytes (with a resolution of 64 bytes) of each color. when these counters overflow, the policy manager invokes the counter manager with an increment instruction and counters maintained by the counter manager are used for the overflow count. counter definition 0 is reserved for the policy manager, and must be configured for these overflow counts. the polcb must be configured before use. configuration is accomplished via the cab. the contents of the polcb are illustrated in table 135: polcb field definitions on page 209. classification of a frame by the picocode must result in a polcba. the hardware classifier provides the color of the frame in the fcbpage. the frame length used must be parsed from the ip packet header by the pico- code. figure 52: split between picocode and hardware for the policy manager polcb memory policy manager to c o u n t e r manager cab access polcba (20) color (2) packetlength (16) newcolor (2) picocode hardware IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 209 of 444 the policy manager receives the following inputs from the picocode: polcba (20 bits) color (2 bits), the color of the incoming packet. as encoded in the ds byte, 00 = green, 01 = yellow, 10 = red packet length (in bytes, 16 bits) the policy manager reads the polcb from the memory, executes the algorithm configured by the type field in the polcb, writes the updated polcb back to the memory and returns the new color to the picocode. pico- code might use this information as follows perform no special action discard the packet change the ds byte (i.e. (re-)mark the frame) table 135: polcb field definitions field size description type 4 algorithm type. this field must be initialized by picocode. 0000 color blind single rate three color marker 0001 color aware single rate three color marker 0010 color blind two rate three color marker 0011 color aware two rate three color marker 0100-1111 reserved pa_time 32 previous arrival time in ticks. this field must be initialized to 0 by the picocode. pa_time is compared to a running 32 bit counter which is incremented every 165/150ns. selection of the accuracy of the counter tick is controlled by the setting of the dram parameter regis- ter bit 22 (11/10 ). when set to 1 the tick rate is 165ns when set to 0 the tick rate is 150 ns. c_token 26 token counter for committed rate accounting in bytes. this field must be initialized by pic- ocode to contain the same value as c_burstsize. (format is 17.9) ep_token 26 token counter for excess or peak rate accounting in bytes. this field must be initialized by picocode to contain the same value as ep_burstsize. (format is 17.9) cir 12 committed information rate in bytes/tick used for two rate algorithms. cir uses an expo- nential notation x * 8 y-3 where 11:3 x 2:0 y; valid values of y are ?000? through ?011? a tick for the policy manager is defined to be either 165 or 150 ns. selection of the value for a tick is controlled by the setting of the dram parameter register bit 22 (11/10 ). when set to 1 the tick is 165ns, when set to 0 the tick is 150ns. this field must be initialized by picocode to meet the service level agreement. the pir must be equal to or greater than the cir. cir can be defined in the range of 100kb/s through 3gb/s. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 210 of 444 np3_dl_sec07_epc.fm.01 09/25/00 pir 12 peak information rate in bytes/tick used for two rate algorithms. pir uses an exponential notation x * 8 y-3 where 11:3 x 2:0 y; valid values of y are ?000? through ?011? a tick for the policy manager is defined to be either 165 or 150 ns. selection of the value for a tick is controlled by the setting of the dram parameter register bit 22 (11/10 ). when set to 1 the tick is 165ns, when set to 0 the tick is 150ns. this field must be initialized by picocode to meet the service level agreement. the pir must be equal to or greater than the cir. pir can be defined in the range of 100kb/s through 3gb/s. c_burstsize 17 committed burst size in bytes. this field must be initialized by picocode to meet the service level agreement. for the single rate algorithms, either the c_burstsize or the ep_burstsize must be larger than 0. it is recommended that when the value of c_burstsize or the ep_burstsize is larger than 0, it is larger than or equal to the size of the mtu for that stream. for the two rate algorithms, c_burstsize must be greater than 0. it is recommended that it is larger than or equal to the size of the mtu for that stream. ep_burstsize 17 excess or peak burst size in bytes. definition depends on algorithm selected. this field must be initialized by picocode to meet the service level agreement. for the single rate algorithms, either the c_burstsize or the ep_burstsize must be larger than 0. it is recommended that when the value of c_burstsize or the ep_burstsize is larger than 0, it is larger than or equal to the size of the mtu for that stream. for the two rate algorithms, ep_burstsize must be greater than 0. it is recommended that it is larger than or equal to the size of the mtu for that stream. greencnt 10 number of bytes (with 64 byte resolution) in packets flagged as "green" by the policy man- ager. when this counter overflows, the policy manager uses the counter manager interface to increment an extended range counter. this field must be initialized to 0 by picocode. the counter control block for the policy man- ager must be configured at counter definition table entry 0. the green count is counter number 0. yellowcnt 10 number of bytes (with 64 byte resolution) in packets flagged as "yellow" by the policy man- ager. when this counter overflows, the policy manager uses the counter manager interface to increment an extended range counter. this field must be initialized to 0 by picocode. the counter control block for the policy man- ager must be configured at counter definition table entry 0. the yellow count is counter number 1. redcnt 10 number of bytes (with 64 byte resolution) in packets flagged as "red" by the policy man- ager. when this counter overflows, the policy manager uses the counter manager interface to increment an extended range counter. this field must be initialized to 0 by picocode. the counter control block for the policy man- ager must be configured at counter definition table entry 0. the red count is counter number 2. table 135: polcb field definitions (continued) field size description IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 211 of 444 7.6 counter manager the counter manager is a hardware assist engine used by the epc to control various counts used by the pic- ocode for statistics, flow control, and policy management. the counter manager is responsible for counter updates, reads, clears, and writes, and it allows the picocode to access these functions using single instruc- tions. the counter manager arbitrates between all requestors and acknowledges when the requested opera- tion is completed. the counter manager works in concert with the counter coprocessor logic in order to allow the picocode access to the various counters. the counter manager supports the following: 64-bit counters 32-bit counters 24/40-bit counters read, read/clear, write, increment, and add functions a maximum of 1 k 64-bit, 2 k 32-bit, or some mix of the two not to exceed a total size of 64 k bits, of fast internal counters up to 4 m 64-bit or 32-bit external counters. two 32-bit counters are packed into a 64-bit dram line. selection of the counter is accomplished by the low-order address bit. counter definition table for defining counter groups and storage locations interfaces to all eight dppus, the policy manager, ingress and egress flow control five independent counter storage locations IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 212 of 444 np3_dl_sec07_epc.fm.01 09/25/00 figure 53: counter manager block diagram ingress flow control internal counter dram bank cntrq4 cntrq0 cntrq1 address & update value counter definition table multiplexer / arbitration dppu7 counter coprocessor dppu0 cntrq2 cntrq3 read read read read read ... policy external dram - d2 a dram bank b dram bank c dram bank d manager counter manager counter coprocessor memory egress flow control IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 213 of 444 7.6.1 counter manager usage the counter manager manages various counters for the epc. the epc, policy manager, and the ingress and egress flow control have the ability to update these counters. the picocode accesses these counters for statistics, flow control actions, and policy decisions. before a counter can be used, its counter definition entry must be configured. this entry defines where the counter is stored, how many counters are associated with this set, and the counter?s size. the counter manager supports 256 different counter definition entries. the counter definition entry is written to the counter definition table using the cab. the entry format in shown in table 139 . table 136: counter manager components component name description counter definition table contains definitions for each counter block (256 entries). a counter block is made up of the counter?s memory storage location (bank a, bank b, bank c, bank d, or internal), the base address within that memory, the number of counters within the set, and the counter size. multiplexing and arbitration multiplexing and arbitration logic selects the next counter action from all requestors according to prior- ity. flow control has the highest priority, policy manager the next, and the set of dppus the lowest pri- ority. multiplexing and arbitration logic uses two work conserving round-robins: one between the two flow control requestors and one for the set of dppus. this logic returns the read data to the appropri- ate requestor during counter reads. address and update value address and update value logic uses information gathered from the counter definition table and the parameters passed from the requestor to create the final counter address and update value. cntrq0 - cntrq4 five counter queues used to temporarily hold the counter request and allow the counter manager to access all five memory locations independently. the request is placed into the appropriate queue based on the memory storage location information found in the counter definition table. read read logic gathers the read data from the appropriate memory location and returns it to the requestor. internal counter memory internal counter memory holds the ?fast? internal counters and can be configured to hold 64-bit, 24/40- bit, or 32-bit counters. the internal counter memory size is 1024 locations x 64 bits. table 137: counter types type name description 64-bit counter counter that holds up to a 64-bit value. 24/40-bit counter special 64-bit counter that has a standard 40-bit portion and a special 24-bit increment portion. the 40- bit portion is acted upon by the command passed and the 24-bit portion is incremented. this counter allows ?byte count? and ?frame count? counters to be in one location; the 40-bit portion is the byte count, and the 24-bit portion is the frame count. 32-bit counter counter that holds up to a 32-bit value. table 138: counter actions action name description read read counter and return value (either 64 or 32 bits) to the epc. read/clear read counter and return value (either 64 or 32 bits) to the epc. hardware then writes counter to zero. write write 16 bits to the counter (either bits 31:16 or 15:0) and zero all other bits. increment add one to the counter value and store updated value in memory. add add 16 bits to the counter value and store updated value in memory. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 214 of 444 np3_dl_sec07_epc.fm.01 09/25/00 the counter definition entry describes a set of counters that have similar characteristics and are referenced from the picocode as a single group. the following figure shows several counter definition examples. each counter definition entry can be used for a block of counter sets. the definition describes one counter set and the picocode can reference several consecutive counter sets using the same definition. for example, a counter set is defined as four counters: one for frames less than 500 bytes, one for frames between 500 and 1000 bytes, one for frames between 1001 and 1518 bytes, and the last one for frames greater than 1518. one counter definition entry describes the counters and picocode can use the definition to reference 40 sim- ilar sets of these counters, e.g. one for each source port. counter set 0 is located at the base address table 139: counter definition entry format field bits definition reserved 31:30 not used. 24/40 29 flag to indicate 24/40 counter (1 = 24/40). if set, 64 / 32 must also be set to 1. 64 / 32 28 flag to indicate a 64-bit counter (1 = 64) or a 32-bit counter (0 = 32). number of counters 27:23 number of counters within this counter set. legal values: 1, 2, 4, 8, or 16 counter resource location 22:20 storage used for the counter block. 000 bank a 001 bank b 010 bank c 011 bank d 100 internal memory base address 19:0 base address within the memory where the counter block starts. figure 54: counter definition entry counter definition entry 3 counter definition entry 8 counter definition entry 45 number of counters in set = 4 counter resource = bank a base address = x?0 1004? number of counters in set = 8 counter resource = bank c base address = x?0 1608? number of counters in set = 2 counter resource = internal base address = x?0 0044? IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 215 of 444 defined by the entry, counter set 1 is located at the next available address, and so on. figure 55 shows an example of counter blocks and sets. in order to reference the correct counter, the requestor must pass the counter manager several parameters. these parameters are described in table 140 . figure 55: counter blocks and sets counter definition entry 3 number of counters in set = 4 counter resource = bank a base address = x?0 1004? counter set 0 counter set 1 counter set 39 <500 500 - 1000 1001 - 1518 >1518 counter block 3 IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 216 of 444 np3_dl_sec07_epc.fm.01 09/25/00 the counter manager builds the actual counter address using the following algorithm: address = base address + (counter set index * number of counters) + counter number this address is used to access the counter within the appropriate memory (bank a, bank b, bank c, bank d, or internal). when a 32-bit counter is accessed, the low order bit of the address selects which 32 bits of the 64-bit memory word are being used: 0 = bits 31:0, 1 = bits 63:32. the counter manager supports a special mode of operation when used by the ingress or egress flow con- trol. this mode allows ?delayed increments? to occur based on flow control information. both flow controls pass an additional parameter, flow control action, that causes the counter manager to modify which counter definition entry is used. a standard enqueue sent by either flow control logic causes the counter manager to use the counter definition index that is passed with the request. a discard resulting from the transmit probability table (see the ibm powernp np4gs3 hardware reference manual, sections 3 and 5) causes the counter manager to access the counter definition entry that is located at index+1. a tail drop discard causes the counter manager to access the counter definition entry located at index+2. each type of flow control action uses a different counter definition. when the policy manager requests use of the counter manager, it always uses a counter definition table index of 0. this location is reserved for use by the policy manager. when accessing the internal memory, the counter manager can update these counters at a rate of one every 15 ns. the external dram rates are once each 150 ns or each 165 ns depending on dram cycle configura- tion (10 or 11 cycle windows). the counter manager supports the following actions: read, read/clear, write/lower, write/upper, increment and add. the dppus can read any counter in the counter manager. the flow control and policy manager table 140: counter manager passed parameters parameter bits definition counter definition table index 8 counter definition entry to use for this action counter set index 20 set of counters to reference counter number 4 counter within the set to reference action 3 action to perform on the counter modify 000 increment by 1 001 add 16 bits to counter read 100 standard read 101 read then clear value write 110 write bits 15:0 of counter 111 write bits 31:16 of counter all other code points are reserved. add/write value 16 valuetoaddtocounterwhenmodify/addselected value to write to counter when write selected flow control action (counter definition table index offset) 2 only used by flow control interfaces 00 standard enqueue 01 discard (resulting from the transmit probability table) 10 tail drop discard 11 reserved IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec07_epc.fm.01 09/25/00 embedded processor complex page 217 of 444 logic do not perform counter reads. when a counter is read, the counter manager returns the read data (either 32 or 64 bits) with the acknowledge signal. the picocode can also clear the counter (set to zero) after the read is performed by passing the read/clear action. counter writes of 16 bits are supported and either bits 15:0 or bits 31:16 of the selected counter are set to the write value with all other bits set to zero. the counter manager also supports incrementing or adding to the selected counter. the add value can be up to 16 bits in size and will be added to the counter (either 32, 40, or 64 bits). when a 24/40 counter is incre- mented or added, the 24-bit portion of the counter is incremented and the 40-bit portion receives the incre- ment/add action. the counter manager supports the following maximum numbers of counters (actual number depends on size of dram used and the counter definition table information): up to 1 k 64-bit, or 2 k 32-bit internal counters, or some mix of 64 and 32-bit counters not to exceed 64 k bits total size. up to 1 m 64-bit, or 1 m 32-bit external counters per dram bank, or some mix of 64 and 32-bit counters not to exceed 1 m total counters per bank. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded processor complex page 218 of 444 np3_dl_sec07_epc.fm.01 09/25/00 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 219 of 444 8. tree search engine 8.1 overview the tree search engine (tse) is a hardware assist that performs table searches. tables in the network pro- cessor are maintained as patricia trees, with the termination of a search resulting in the address of a leaf page. the format of a leaf page or object is defined by the picocode; the object is placed into a control store, either internal (h0, h1) or external (z0, d0-d3). 8.1.1 addressing control store references to the control store use a a 26-bit address as shown in table 141 . each address contains a memory id, a bank number, and an offset. table 142: cs address map and use on page 220 provides addressing information and recommended uses for each memory that is supported by the csa and that is accessible via the tse. the memory type provides access width and memory size information. selection for d0 as either single or double wide is by configura- tion ( 13.1.2 dram parameter register (dram_parm) on page 342). table 141: control store address mapping for tse references 26-bit address used to reference the control store 4 bits 2 bits 20 bits memory id bank no. offset virtual bank address IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 220 of 444 np3_dl_sec08_tree.fm.01 09/25/00 table 142: cs address map and use memory id bank no. memory name type offset width (bits) recommended use 0000 00 null 20 01-11 reserved 0001 00 z0 external zbt sram 17 -18 fast pscb 01-11 reserved 512k x 36 0010 00 h0 internal sram 2k x 128 11 fast leaf pages 01 h1 internal sram 2k x 36 11 fast internal sram 10 reserved 11 reserved 0011 00-11 reserved 0100 - 0111 00-11 reserved 1000 00-11 d0 banks a - d ddr dram 18 - 20 single (d0_width=0) or double wide (d0_width=1) configuration. leaf pages d0_width=0 4 x 256k x 64 4 x 512k x 64 4x1mx64 d0_width=1 4 x 256k x 128 4 x 512k x 128 4 x 1m x 128 1001 00-11 d1 banks a - d ddr dram 18 - 20 leaf pages 1010 00-11 d2 banks a - d 4 x 256k x 64 leaf or counter pages 1011 00-11 d3 banks a - d 4 x 512k x 64 dt entries and pscb entries 4x1mx64 1100 00-11 d6 banks a - d ddr dram 4x1mx64 4x2mx64 4x4mx64 20 powerpc external memory tse object access h=1, w=4, or 32 bytes addresses x?00 0000' through ?0f ffff' 1101 addresses x?10 0000' through ?1f ffff' 1110 x?20 0000' through ?2f ffff' 1111 x?30 0000' through ?3f ffff' note: ddr dram is specified as: number of banks x number of entries x burst access width (in bits). IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 221 of 444 8.1.2 control store use restrictions the following restrictions apply: when d2 is used by the counter manager, the last location (highest address) in each bank must not be assigned for any use. dt entries can be stored only in h1, z0, or d3. note that since lpm dt entries are 64 bits wide and dt entries must have a height=width =1, lpm dt entries are restricted to d3. pscbscanbestoredonlyinh1,z0,ord3. leaf pages can be stored only in h0, d0, d1, and d2. 8.1.3 object shapes object shapes specify how the control store stores an object such as a leaf or pattern search control block (pscb). a leaf is a control block that contains the reference key as a reference pattern. the pattern uniquely identifies the leaf in a tree and contains the data needed by the application initiating a tree search. the data is application dependent and its size or memory requirements are defined by the ludeftable entry for the tree. see table 144: height, width, and offset restrictions for tse objects on page 224 and table 156: ludeft- able entry definitions on page 233 for details. shape is defined by two parameters, height and width. objects small enough to fit within a single memory or bank location are defined as having a height and width of 1 (denoted by 1,1), and therefore do not require shaping. for example, both a 32-bit and a 48-bit object stored in a ddr sdram bank would have a shape of (1,1). when objects do not fit into a single memory or bank location, they have heights and/or widths > 1: height denotes the number of consecutive address locations in which an object is stored. for example, if the height of an object = 4 and the control store address = a, the object is stored in locations a, a+1, a+2 and a+3. width denotes the number of consecutive banks in which the object is stored. width is always = 1 for objects stored in zbt sram, and could be > 1 for objects in ddr sdram. for example, if the width of an object = 3, and its height = 1, the object is stored in three consecutive banks (the virtual bank address is incremented by 1). an offset increment can carry out into the bank address bits. this is not a supported use of the cs mem- ory and table allocation algorithms must be defined to avoid this condition. table 143: dtentry, pscb, and leaf shaping object shape dtentry always has a shape of height = 1, width = 1 fm pscb always has a shape of height = 1, width = 1 lpm pscb has a shape of height = 1, width = 1 or height = 2, width = 1 depending on the memory in which the pscb resides. a memory with a line width of at least 64 bits should be used with height = 1 and a memory of 36 bits should be used with height = 2. leaf can have any shape that is allowed by the memory in which the leaf is located -maximum of 512 bits. IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 222 of 444 np3_dl_sec08_tree.fm.01 09/25/00 for height and width, the hardware automatically reads the appropriate number of locations. from a pico- code point of view, an object is an atomic unit of access. restrictions to height, width, and offset are given in table 144: height, width, and offset restrictions for tse objects on page 224 . table 156: ludeftable entry definitions on page 233 specifies the leaf and pscb shapes. figure 56: example shaping dimensions on page 223 illustrates some example placement of objects with dif- ferent shapes in control store. an object may span more than one dram as shown in examples (b) and (c) with the following restrictions: an object may span d1 and d2 when d0 is configured as a single wide (d0_width=0), then an object may span d0 and d1. objects may not span out of d0 when d0 is configured as a double wide (d0_width=1). objects may not span into or out of z0, h0, h1, d3 or d6. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 223 of 444 figure 56: example shaping dimensions (2,1) (3,1) 128 h0 h=1, w=1 h=5, w=1 (note: 4 bits unused) 32 z0 h=1, w=1 36 d1 (height=1,width=4) 64 d2 (1,2) (3,1) 64 64 64 (height=1,width=3) d1 (height=1,width=4) d2 (3,1) (height=1,width=3) (1,1) (1,1) (1,1) ab c d ab c d ab c d ab c d 64 64 64 64 64 64 64 64 64 64 64 64 h=3, w=1 example (a) example (b) example (c) IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 224 of 444 np3_dl_sec08_tree.fm.01 09/25/00 8.1.4 illegal memory access when the tse uses an undefined memoryid (that is., reserved) or an illegal memory shape, the tse aborts the current command, returns a ko status, and sets an exception flag at bit 2 in interrupt class 3. the excep- tion flag can be set to cause an interrupt by setting bit 2 of interrupt mask 3 to ?1?. for debugging purposes, an exception can switch a programmable set of threads into single step mode. table 144: height, width, and offset restrictions for tse objects memory height width total object size (bits) control store address offset must be divisible by h0 1 2 3 4 1 1 1 1 128 256 384 512 1 2 4 4 h1 1 2 3 4 5 6 7 8 1 1 1 1 1 1 1 1 36 64 96 128 160 192 224 256 1 2 4 4 8 8 8 8 z0 1 2 3 4 5 6 7 8 1 1 1 1 1 1 1 1 36 64 96 128 160 192 224 256 1 2 4 4 8 8 8 8 d0 (d0_width=1; double wide configuration) 1 2 3 4 1 2 1 1 1 1 1 1 2 2 3 4 128 256 384 512 256 512 384 512 1 2 4 4 1 2 1 1 d0-d1-d2-d3-d6 (d0_width=0; single wide configuration) 1 2 3 4 5 6 7 8 1 2 3 4 1 2 1 2 1 1 1 1 1 1 1 1 2 2 2 2 3 3 4 4 64 128 192 256 320 384 448 512 128 256 384 512 192 384 256 512 1 2 4 4 8 8 8 8 1 2 4 4 1 2 1 2 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 225 of 444 8.1.5 memory range checking memory range checking can flag access to a programmable range within minbounds and maxbounds. mem- ory range checking can be performed for any tse control store accesses. when memory range checking is enabled, any control store address falling outside the range generates an exception (an exception does not stop tse operation) and sets an exception flag at bit 1 in interrupt class 3 (tsm_addr_range_violation). the exception flag can be set to cause an interrupt by setting bit 1 of interrupt mask 3 to ?1?. 8.2 trees and tree searches the tse uses trees to store and retrieve information. tree searches, retrievals, inserts and deletes are per- formed according to a key that is similar to a mac source address or a concatenation of an ip source and destination address. information is stored in one or more leaves that contain the key as a reference pattern and, typically, contain aging and user information for forwarding purposes such as target blade and target port numbers. to locate a leaf, a search algorithm processes input parameters that include the key and hashes the key. the algorithm then accesses a direct table (dt) and walks the tree through the pscbs. there are three types of trees, each with its own search algorithm and tree-walk rules: full match (fm); longest prefix match (lpm); and software managed (smt). the data structure of fm and lpm trees is the patricia tree. when a leaf is found, the leaf is the only candi- date that can match the input key. a ?compare-at-end? operation compares the input key with a reference pat- tern stored in the leaf to verify a match. search results are ?ok? when a match is found and ?ko? in all other cases. the data structure of smt trees is similar to that of fm trees, but smt trees can have multiple leaves that can be chained in a linked list. all leaves in the chain are checked against the input key until a match is found or the chain is exhausted. search results are ?ok? when a match is found and ?ko? in all other cases. table 145: fm and lpm tree fixed leaf formats field name byte length description nlarope 4 leaf chaining pointer, aging and direct leaf information prefix_len 1 length of the pattern (in bits) for lpm only. not used by tse for fm trees and canbeusedbypicocode pattern 2-18 pattern to be compared with hashedkey. always present. length given by p1p2_max_size from table 156: ludeftable entry definitions on page 233 userdata variable under picocode control. for example, field can include one or more counters IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 226 of 444 np3_dl_sec08_tree.fm.01 09/25/00 8.2.1 input key and color register for fm and lpm trees for fm and lpm trees, the input key is hashed into a hashedkey according to the algorithm specified in the ludeftable. to minimize the depth of the tree that begins after the direct table, the hash function output is always a 192-bit number with a one-to-one correspondence to the original input key. maximum output entropy is contained in the hash function?s most significant bits. the n highest bits of the hashedkey register are used to calculate an index into the direct table, where n is determined by the definition of the dt (direct table) entry for the tree. when colors are enabled for a tree, the 16-bit color register is appended as the lsb to the 176 msbs from the 192-bit hashed output to produce the final 192-bit hashedkey. this occurs directly after the direct table. if the direct table contains 2 n entries, the 16-bit color value is inserted at bit position n. the hash function out- put and the inserted color value (when enabled) are stored in the hashedkey register. when colors are dis- abled, the 192-bit hash function is unmodified. colors can be used to share a single direct table among multiple independent trees. for example, color could indicate a vlanid in a mac source address table. the input key would be the mac sa and the color the vlanid (vlanid is 12 bits and 4 bits of the color would be unused, that is., set to 0). after the hash function, the pattern would be 48 + 16, or 64 bits. the color would be part of the pattern to distinguish mac addresses of different vlans. table 146: smt tree fixed leaf formats field name byte length description nlasmt 4 leaf chaining pointer to chain leaves for smt. includes shape of chained leaf comp_table_index 1 defines index in compdeftable that defines compare between pattern1, pattern2, and hashedkey pattern1 and pattern2 4-36 contains pattern1 and pattern2 bitwise interleaved (even bits represent pattern1 and odd bits represent pattern2). that is, bit 0 of the field contains bit 0 of pattern1, bit 1 contains bit 0 of pattern 2, etc. length given by 2*p1p2_max_size from table 156: ludeftable entry definitions on page 233 userdata variable under picocode control. for example, field can include one or more counters table 147: search input parameters parameter bit length description key 192 key must be stored in the shared memory pool. all 192 bits must be set cor- rectly (for key length shorter than 192, remaining bits in shared memory pool must be set to 0). key length 8 contains key length minus 1 in bits. ludefindex 8 index into ludeftable that points to an entry containing a full definition of the tree in which the search occurs. see section 8.2.5.1 the ludeftable on page 233. lcbanr 1 search results can be stored in either tsrx, as specified by tsedpa. leaf addresses are stored in lcba0 or lcba1 as specified by lcbanr. during a tse search, picocode can access the other tsr to analyze the results of previ- ous searches. color 16 for trees with color enabled, as specified in the ludeftable, the contents of the color register are inserted into the key during hash operation. see section 8.2.1 input key and color register for fm and lpm trees on page 226 for an explanation of the process. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 227 of 444 8.2.2 input key and color register for smt trees for smt trees, the input key is a 192-bit pattern and the color register is ignored. no hashing is performed. 8.2.3 direct table a search starts when a dtentry is read from the direct table. the read address is calculated from the n high- est bits of the hashedkey and from the tree properties defined in the ludeftable. the dtentry can be repre- sented as the root of a tree, with the actual tree data structure depending upon tree type. a patricia tree data structure is used with fm trees. extensions to the patricia tree are used with lpms and smts. using a dt can reduce search time (pscb access time). increasing dt size is a trade-off between memory usage and search performance. when a single leaf is attached to a dtentry, the read data includes a pointer to the leaf. when more than one leaf is attached, the read data defines the root of a tree. when the dtentry is empty, no leaf information is attached. 8.2.3.1 pattern search control blocks (pscb) a search begins after a dtentry has been read if the dtentry is neither empty nor contains a direct leaf. a tree walk search starts at the dtentry and passes one or more pscbs until a leaf is found. for an fm tree, the pscb represents a node in the tree, or the starting point of two branches, ?0? and ?1?. each pscb is associated with a bit position ?p? in the hashedkey. bit p is the next bit to test (nbt) value stored in the previ- ous pscb or in the dtentry. leaves reachable from a pscb through the 0 branch have a ?0? in bit p, and leaves reachable through the 1 branch have a ?1?. leaves reachable through either branch have patterns where bits 0..p-1 are identical, because pattern differences begin at bit p. figure 57: effects of using a direct table direct table (dt) data structure without a direct table data structure with a direct table leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 228 of 444 np3_dl_sec08_tree.fm.01 09/25/00 when an fm tree search encounters a pscb, the tse continues the tree walk on the 0 or 1 branch depend- ing on the value of bit p. thus, pscbs are only inserted in the tree at positions where leaf patterns differ. this allows efficient search operations since the number of pscbs, and thus the search performance, depends on the number of leaves in a tree, not on the length of the patterns. 8.2.3.2 leaves and compare-at-end operation the entire hashedkey is stored in the leaf as a reference pattern, not as the original input key. during a tree walk, only the hashedkey bits for which a pscb exists are tested. when an fm leaf is found, its reference pattern must be compared to the full hashedkey to make sure all the bits match. if the leaf contains a chain pointer or nla field to another leaf, the new leaf?s reference pattern is compared to the hashedkey. lacking a match or another nla field, the search ends and the failure is indicated by a ko status. if the pattern matches, the original input key is checked. if that matches, the whole leaf page is returned to the network pro- cessor. if there is no match, the leaf page is returned with a no match message. 8.2.3.3 cache the direct table can be used as a cache to increase tree search performance since these trees are generally small and contain most likely entries. during a search, the tse first determines whether the dt contains a leaf matching the hashedkey. if so, the leaf is returned, eliminating the need for a search. to the tse, a cache lookup is identical to a normal search, that is., the input key is hashed into a hashedkey and the dt is accessed. caches are enabled in the ludeftable on a per-tree basis. if a cache search uses ludeftable entry i and the search ends with ko, another search using ludeftable entry i+1 starts automatically. this allows multi- ple search chaining, although the full tree should be stored under ludeftable entry i+1. 8.2.3.4 cache flag and nrpscbs registers picocode initiates insert and delete operations to and from the cache. each search result stores information about the cache in the cacheflag and nrpscbs registers as shown in table 148 . each register is divided into two sections, one for searches using tsr0 and the other for searches using tsr1. 8.2.3.5 cache management cache management is performed using picocode. cache inserts are controlled by inspecting the cacheflag and nrpscbs registers after each tree search. inserts are treated like normal fm tree inserts, allowing the association of multiple leaves with a single dtentry, because normal fm inserts create pscbs to handle table148:cachestatusregisters register bit length description cacheflag(0) 1 cacheempty bit - set when cache search finds an empty dtentry in cache dt cacheflag(1) 1 cacheleaffound bit - set when cache search finds a leaf and cache search returns ok. when leaf found bit has been set, full search has not been per- formed. cacheflag(2) 1 cacheko bit - set when cache search returns ko. when cache is empty, this bit is also set. nrpscbs 8 after any search, contains the number of pscbs read during a tree walk. when a cache search finds no leaf and a full search starts, contains the number of pscbsreadduringthesearch. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 229 of 444 multiple leaves. inserts can also be done by writing directly to a dtentry, although only using single leaves. cache deletes use the tree aging mechanism whereby every n seconds all entries in the cache are deleted. 8.2.3.6 search output the output of a search operation consists of the parameters listed in table 149 . 8.2.4 tree search algorithms the tse provides hardware search operations for fm, lpm, and smt trees. software initializes and main- tains trees. leaves can be inserted into and removed from fm and lpm trees without control point function (cpf) intervention, permitting scalable configurations with cpf control when needed. 8.2.4.1 fm trees fm trees provide a mechanism to search tables with fixed size patterns, such as a layer 2 ethernet unicast mac tables which use fixed six-byte address patterns. searches of fm trees are efficient because fm trees benefit from hash functions. the tse offers multiple fixed hash functions that provide very low collision rates. each dtentry is 36 bits wide and contains the formats listed in table 150 . pscbs have the same structure as dtentrys except they contain two pscblines, each of which can have one of the two pointer formats listed in this table : next pointer address (npa) or leaf control block address (lcba) . the two pscblines are allo- cated consecutively in memory and are used as walking branches in the tree. the nbt value signifies which of the two pscblines is used. 8.2.4.2 lpm trees lpm trees provide a mechanism to search tables with variable length patterns or prefixes such as a layer 3 table 149: search output parameters parameter description ok/ko flag 0 ko: unsuccessful operation 1 ok: successful operation that is., leaf pattern matches hashedkey tsrx leaf contents are stored in tsr0 or tsr1, depending on tsrnr lcba0 / 1 leaf address is stored in lcba0 / 1 cacheflags(2) cacheempty bit cacheflags(1) cacheleaffound bit cacheflags(0) cacheko bit nrpscbs number of pscbs read during last search. can be used as a criterion to insert cache entry table 150: dtentry and pscbline formats format conditions valid in dtentry? valid in pscb? format (2 bits) npa/lcba (26 bits) nbt (8 bits) empty dtentry no leaves yes no 00 0 0 pointer to next pscb dtentry contains pointer yes yes 00 npa nbt pointer to leaf single leaf associated with dtentry; lcba field contains pointer yes yes 01 lcba 0 IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 230 of 444 np3_dl_sec08_tree.fm.01 09/25/00 ip forwarding table where ip addresses can be full match host addresses or prefixes for network addresses. the cpf manages lpm trees with assistance from the gth for inserting and removing leaf entries. lpm dtentrys, each of which can contain a node address, an npa, and an lcba, differ from fm dtentrys which cannot contain both a node and leaf address. each dtentry is 64 bits wide and contains the formats listed in table 151: lpm dtentry and pscbline for- mats on page 230. pscbs have the same structure as dtentrys except pscbs contain two pscblines, each of which can have one of the three lcba formats listed in the table. the two pscblines are allocated consecutively in memory and are used as walking branches in the tree. one of the pscb lines may be empty, whichisnotallowedinfmpscbs. 8.2.4.3 smt trees smt trees provide a mechanism to create trees that follow a cpf-defined search algorithm such as an ip quintuple filtering table containing ipsa, ipda, source port, destination port, and protocol. smt trees use the same pscbs as fm trees, but only the first leaf following a pscb is shaped by the table 156: ludeftable entry definitions on page 233. the following leaves in a leaf chain are shaped according to the 5 bits in the chaining pointer contained in the nlasmt leaf field (see table 152 ). unlike fm and lpm, smt trees allow leaves to specify ranges, for instance, that a source port must be in the range of 100..110. smt trees always contain two patterns of the same length in a leaf to define a comparison range. when the first leaf is found after a pscb, a compare-at-end operation is performed. if ok, the search stops. if the comparison returns ko and the nlasmt field is non-zero, the next leaf is read and another compare-at-end operation is per- formed. this process continues until an ?ok? is returned or until the nlasmt field is zero, which returns a ko. 8.2.4.4 compare-at-end operation the input key and the two reference patterns stored in each leaf can be logically divided into multiple fields (see figure 58 on page 231). one of two comparisons can be performed on each field: 1. compare under mask. the input key bits are compared to pattern0 bits under a mask specified in pattern1. a ?1? in the mask means the corresponding bit in the input key must equal the corresponding bit in pattern0. a ?0? means the corresponding bit in the input key has no influence on the comparison. the table 151: lpm dtentry and pscbline formats format conditions valid in dtentry? valid in pscb? format (2 bits) npa (26 bits) nbt (8 bits) lcba (26 bits) spare (2 bits) empty dtentry no leaves yes yes 00 0 0 0 0 lcba not valid dtentry contains pointer to pscb yes yes 00 npa nbt 0 0 lcba valid; npa/ nbt not valid single leaf associated with dtentry; lcba contains pointer to leaf; no pointer to next pscb yes yes 01 0 0 lcba 0 lcba valid; npa/ nbt valid single leaf associated with dtentry; lcba contains pointer to leaf; pointer to next pscb yes yes 01 npa nbt lcba 0 table 152: nlasmt field format 1 bit 2 bits 3 bits 26 bits reserved width of next leaf height of next leaf nla (next leaf address) IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 231 of 444 entire field matches only when all bits match, in which case the tse returns ok. 2. compare under range. the input key bits are treated as an integer and checked to determine whether the integer is within the range specified by min and max, inclusive. if so, the tse returns ok, otherwise the tse returns ko. when all fields return ok, the entire compare-at-end returns ok. otherwise, ko returns. logical field definitions are specified in the compare definition table compdeftable. table 153 shows the entry format for the compdeftable. fields are compare-under-mask unless specified by the compdeftable. each entry specifies one or two range comparisons, although multiple entries can specify more than two range comparisons. each range comparison is defined by offset and length parameters. the offset, which is the position of the first bit in the field, must be at a 16-bit boundary and have a value of 0, 16, 32, 48, 64, 80, 96, 112, or 128. the length of the field must be 8, 16, 24, or 32 bits. in the input key shown in figure 58: example input key and leaf pattern fields on page 231, the compare- figure 58: example input key and leaf pattern fields table 153: compdeftable entry format field range bit length value range 1 offset (r1_offset) 1 8 starting bit position for first range compare. range 1 length (r1_len) 1 8 length and number of bits to be used as a part of range compare starting/ beginning from r1_offset. range 2 offset (r2_offset) 2 8 starting bit position for second range compare. range 2 length (r2_len) 2 8 length and number of bits to be used as a part of range compare starting/ beginning from r2_offset. this field is specified as the number of bits multi- plied by 4. range 2 valid (r2_valid) -- 1 range 2 valid value. this field indicates whether or not the range 2 offset and length fields are valid. 0 range 1 offset and length valid, but range 2 offset and length not valid. 1 range 1 and range 2 offset and length all valid. continue (cont) -- 1 continue indicator value. this field indicates whether the compare opera- tion is continued in the next sequential entry of the table. 0 comparison not continued 1 comparison continued ipsa (32 bits) ipda (32 bits) srcport (16 bits) dstport (16 bits) prot (8 bits) input key value value min min value leaf pattern0 mask mask max max mask leaf pattern1 minmax field1 offset field1 offset field0 length minmax field0 length IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 232 of 444 np3_dl_sec08_tree.fm.01 09/25/00 under-range for the source port (srcport) field would have offset0 set to 64 and minmaxlength0 set to 16. the compare-under-range for the destination (dstport) field would have offset1 set to 80 and minmaxlength1 set to 16. if more than two range comparisons are required, the continue bit would be set to 1 so the next compdeftable entry could be used for additional compare-under-range definitions. the compdeftable index used for tree comparisons is specified in the leaf comp_table_index field (see table 146: smt tree fixed leaf formats on page 226). each compare-under-range operation takes one clock cycle, so use as few compare-under-range operations as possible. if a range is a power of two, or 128- 255, no compare-under-range is required since this range can be compared using compare-under-mask. when a compare-at-end fails and the smtnla leaf field is not 0, the tse reads the next leaf and performs additional compare-at-end operations until the compare returns ok or until the smtnla is 0. 8.2.4.5 ropes as shown in the following figure, leaves in a tree can be linked together in a circular list called a rope. the first field in a leaf is the chaining pointer, or the nlarope. picocode can ?walk the rope,? or sequentially inspect all leaves in a rope. ropes can be created by setting the nlarope_en bit to ?1? in the ludeftable. see table 154: ludeftable rope parameters on page 232. leaf insertion is always done between a ropecla and ropepla. after insertion, the ropepla is unchanged and the ropecla points to the newly inserted leaf. figure 59: rope structure table 154: ludeftable rope parameters parameter description ropecla current leaf address in the rope. all tse instructions related to the rope such as rclr, ardl and tlir (see section 8.2.8 gth hardware assist instructions on page 247) relate to the leaf addressed by rope- cla. ropepla previous leaf address in the rope. always the previous leaf if the rope is related to ropecla unless the rope contains no leaf or one leaf. the following condition is always true for trees with two or more leaves: ropepla->nlarope == ropecla. leafcnt leaf count - number of leaves in the tree leafth leaf threshold causes an exception to be generated when the leafcnt exceeds the threshold leaf1 ropecla th leaf2 leaf3 leaf4 leaf0 ropepla leafcnt part of ludeftable IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 233 of 444 leaf deletion is done two ways: when the rope is not being walked, the rope is a single-chained linked list without a previous pointer. leaves cannot be deleted without breaking the linked list. setting the deletepending bit postpones the deletion until the rope is walked again. a leaf is deleted by setting the deletepending bit of the nlarope field. in this case, leaves are completely deleted and leaf pattern searches will return a ko. when the rope is being walked and the deletepending bit is set, the tse deletes the leaf automatically. 8.2.4.6 aging aging is enabled whenever a rope is created. the nlarope field contains one aging bit that is set to ?1? when a leaf is created. when a leaf is found during a tree search and it matches the leaf pattern, the tse sets the aging bit to ?1? if it has not previously done so, and then writes this information to the control store. an aging function controlled by a timer or other device can walk the rope to delete leaves with aging bits set to ?0? and then write the leaves to the control store with aging bits set to ?0?. when no aging is desired, picocode should not alter the aging bit since bits set to ?1? cannot be changed. 8.2.5 tree configuration and initialization 8.2.5.1 the ludeftable the lookup definition table (ludeftable), an internal memory structure that contains 128 entries to define 128 trees, is the main structure that manages the control store. the table indicates in which memory (ddr- sdram, sram, or internal ram) trees exist, whether caching is enabled, key and leaf sizes, and the search type to be performed. each dtentry contains two indexes to the pattern search and leaf free queue (pscb_leaf_fq). the first index defines which memory to use to create tree nodes, that is, where pscbs are located. the second defines which memory to use to create leaves within a tree. when an entry is added to a tree, the memory required for the insert comes from the pscb_leaf_fq and is returned when the entry is deleted. for smt trees, an lu_def_tbl can be defined to match a value into a given range, but an index to an internal compare type index must be given for the compare table (cmp_tbl). table 155: nlarope field format 2 bits 1 bit 2 bits 1 bit 26 bits reserved aging counter reserved delete pending nla (next leaf address) table 156: ludeftable entry definitions field bit length description cacheentry 1 0 normal tree entry (not a cache entry) 1 a cache entry. when a search returns with ko, and cacheentry = 1, ts instructions will restart using the next entry in the ludeftable (that is., ludefindex + 1). tree_type 2 type of tree. 00 fm 01 lpm 10 smt 11 not used IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 234 of 444 np3_dl_sec08_tree.fm.01 09/25/00 hash_type 4 hash type 0000 no hash 0001 192-bit ip hash 0010 192-bit mac hash 0011 192-bit network dispatch hash 0100 no hash 0101 48-bit mac swap 0110 60-bit mac swap 0111 192-bit smt tree 1000 8-bit hash 1001 12-bit hash 1010 16-bit hash color_en 1 enable color register use by the hash function to construct hashedkey 0 color register not used 1 color register is used p1p2_max_size 5 maximum size of pattern1 and pattern2 in leaf - indicates size in half words (that is., 16 bits) reserved for the ?pattern? as a part of leaf in bytes. the maximum pattern size is 12, which represents 192 bits. nlarope_en 1 enable nlarope field use by leaf (enable aging) 0 leaf does not use nlarope field 1 leaf uses nlarope field pscb_fq_index 6 defines the index of the pscb free list pscb_height 1 height (part of the shape) of a pscbentry. width of a pscb is always 1. 0 height = 1 (fm zbt sram, fm/lpm/smt ddr sdram) 1 height = 2 (lpm/smt zbt sram) dt_base_addr 26 provides dt base address. dt_size 4 direct table size value - defines the number of dt entries within a memory bank. 0001 4 entries 0010 16 entries 0011 64 entries 0100 256 entries 0101 1 k entries 0110 4 k entries 0111 16 k entries 1000 64 k entries 1001 256 k entries 1010 1 m entries others reserved leaf_fq_index 6 defines index of leaf free list leaf_width 2 leaf width leaf_height 3 leaf height ludef_state 2 ludef state - used by product software/user code to indicate current status of the entry. these bits do not affect tree search operation. table 156: ludeftable entry definitions (continued) field bit length description IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 235 of 444 8.2.5.2 tse free lists (tse_fl) the gth has access to a set of 64 tse free list control blocks, each defining a free list using the format shown in table 157 . free lists typically chain unused pscbs and leaves into a linked list, but can also be used by picocode to manage memory. the link pointer is stored in the control store at the address of the pre- vious list object. objects stored in different memories and with different shapes should be placed in different free lists. for example, a list of 64-bit pscbs stored in both zbt sram and internal ram should have differ- ent entries. the gth thread executes the tsenqfl and tsdqfl commands to enqueue and dequeue addresses on a free list. see section 8.2.8.3 tree search enqueue free list (tsenqfl) on page 248 and section 8.2.8.4 tree search dequeue free list (tsdqfl) on page 249. a free list of n objects, each with shape of width = w, height = h and a start address of ?a?, is created by enqueueing address a, a+h, a+2h, a+3h, ? a+(n-1)h in the free list. to prevent memory bottlenecks, free lists can also be created in a ?sprayed? manner for objects contained in sdram. for example, when search- ing a large lpm tree with five pscbs in a single bank, the bank must be accessed five times before reaching a leaf. when the pscbs are sprayed among multiple banks, the number of accesses remains identical but accesses are to multiple banks, thus eliminating bottlenecks. ludef_invalid 1 indicates whether or not this entry is valid for normal tree search command or not. this bit blocks any tree search while the tree is being built or swapped. 0valid 1 invalid when the ludef read request initiated by the tree search command finds this bit set to ?1?, it will re-read this ludefentry every 16 cycles until it is set to valid. this halts the tree search for this particular thread. following fields are valid for gth only ropecla 26 current leaf address for rope ropepla 26 previous leaf address for rope leafcnt 26 number of leaves in tree leafth 10 threshold for the number of leaves in a tree. if the leafcnt is greater than this assigned threshold, then a class 0 interrupt is generated (bit 9 of the class 0 inter- rupt vector). the threshold is formed by the generation of two 26-bit numbers that are bit-wise ored resulting in a threshold value that is compared to the leafcnt: threshold(25:0) = th9_5(25:0) or th4_0(25:0) th9_5(25:0) = 0 when leafth(9:5)=0, otherwise th9_5(25:0) = 2**(leafth(9:5)-1) th4_0(25:0) = 0 when leafth(4:0)=0, otherwise th4_0(25:0) = 2**(leafth(4:0)-1) table 157: free list entry definition field bit length description head 26 free list head address in the control store. tail 26 free list tail address in the control store. qcnt 26 number of entries in the free list. threshold 5 threshold value for the free list control block entry.this field is iniitialized to 0. the threshold is determined as 2**threshold. when the qcnt is less than the threshold, a class 0 interrupt (bit 8) is generated. table 156: ludeftable entry definitions (continued) field bit length description IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 236 of 444 np3_dl_sec08_tree.fm.01 09/25/00 8.2.6 tse registers and register map table 158: tse scalar registers for gth only name read/ write hex address bit length description color r/w 00 16 color - see section 8.2.1 input key and color register for fm and lpm trees on page 226 and section 8.2.2 input key and color register for smt trees on page 227. lcba0 r/w 02 26 leaf control block address 0 - typically contains the control store address of the leaf in tsr0, but is also used as an address register for various tse commands. lcba1 r/w 03 26 leaf control block address 1 - typically contains the control store address of the leaf in tsr1, but is also used as an address register for various tse commands. dta_addr r/w 04 26 dtentry address - valid after a hash has been performed. dta_shape r/w 05 5 shape of a dtentry - always (1,1) when direct leaves are disabled. equals the leaf shape as defined in ludeftable when direct leaves are enabled. always set to ?00000? hashedkeylen r/w 06 8 pattern length minus 1 in hashedkey cacheflags r 07 3 see section 8.2.3.3 cache on page 228 nrpscbs r 08 8 see section 8.2.3.3 cache on page 228 hashedkey r/w 0a-0f 192 contains hashedkey hashedkey 191_160 r/w 0a 32 bits 191..160 of hashedkey hashedkey 159_128 r/w 0b 32 bits 159..128 of hashedkey hashedkey 127_96 r/w 0c 32 bits 127..96 of hashedkey hashedkey 95_64 r/w 0d 32 bits 95..64 of hashedkey hashedkey 63_32 r/w 0e 32 bits 63..32 of hashedkey hashedkey 31_0 r/w 0f 32 bits 31..0 of hashedkey ludefcopy r 10-12 96 contains ludeftable index in use and a copy of the following ludeftablefields: cacheentry, tree_type, hash_type, color_en, dt_size, dt_base_addr, dt_interleaf, directleafen, pscb_height, leaf_width, leaf_height, compindex, p1p2_max_size, nparope_en, npasmt_en, compindex_en ludefcopy 95_64 r 10 32 bits 95..88 = x?0000 0000? bits 87..80 = ludef index = from which location ludefcopy content was read bits 79..64 of ludefcopy ludefcopy 63_32 r 11 32 bits 63..32 of ludefcopy ludefcopy 31_0 r 12 32 bits 31..0 of ludefcopy IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 237 of 444 table159:tsearrayregistersforallgxh name read/ write starting hex address ending hex address bit length description tsr0 r/w 32 47 2048 tree search result area 0 note: portion of the data overlaps with tsr1 tsr1 r/w 40 47 1024 tree search result area 1 note: portion of the data overlaps with tsr0 tsr2 r/w 48 63 2048 tree search result area 2 note: portion of the data overlaps with tsr3 tsr3 r/w 56 63 1024 tree search result area 3 note: portion of the data overlaps with tsr2 note: in this table, starting and ending address represents the offset for the given thread's starting address in the shared memory pool. table 160: tse registers for gth (tree management) name read/ write hex address bit length description patbit_tsr0 r/w 1e 1 contains one bit from the pattern stored in tsr0. set by trs0pat command distposreg r 1f 8 contains result of distpos command luropecopyth r 13 10 contains copy of leafth field of ludeftable luropecopyqcnt r 14 26 contains copy of leafcnt field of ludeftable luropecopyprev r 15 26 contains copy of ropepla field of ludeftable luropecopycurr r 16 26 contains copy of ropecla field of ludeftable table 161: tse scalar registers for gdh and gth name read/ write hex address bit length description lcba0 r/w 02 31 leaf control block address 0 - typically contains the control store address of the leaf in tsrx, but is also used as an address register for various tse commands. bits 30:26 the leaf control block address shape which is used by cmpend instruction only. bits 25:0 leaf control block address lcba1 r/w 03 31 leaf control block address 1 - typically contains the control store address of the leaf in tsrx, but is also used as an address register for various tse commands. bits 30:26 the leaf control block address shape which is used by cmpend instruction only. bits 25:0 leaf control block address cacheflags r 07 3 see section 8.2.3.3 cache on page 228 nrpscbs r 08 8 see section 8.2.3.3 cache on page 228 IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 238 of 444 np3_dl_sec08_tree.fm.01 09/25/00 table 162: pscb register format field bit length control store address for pscb npa0 26 next pscb address - pointer to next pscb in tree for pscb part 0 nbt0 8 next bit to test for pscb part 0 lcba0 26 leaf control block address: pointer to leaf for pscb part 0 npa1 26 next pscb address - pointer to next pscb in tree for pscb part 1 nbt1 8 next bit to test for pscb part 1 lcba1 26 leaf control block address - pointer to leaf for pscb part 1 index 8 index of current pscb physically stored in previous pscb patbit 1 value of hashedkey[index] based on value of index field in pscb register table 163: tse gth indirect registers indirect register bit length description notes pscbx.npa_hk 26 selects either the npa0 field from pscbx or the npa1 field depending on value of register pscbx.index 1, 2, 3 pscbx.npa_tsr0 26 selects either the npa0 field from pscbx or the npa1 field depending on value of register patbit_tsr0. (register patbit_tsr0 must have been initialized previously using tsr0pat command) 1, 2, 4 pscbx.nbt_hk 8 selects either the nbt0 field from pscbx or the nbt1 field depending on value of register pscbx.index 1, 2, 3 pscbx.nbt_tsr0 8 selects either the nbt0 field from pscbx or the nbt1 field depending on value of register patbit_tsr0 1, 2, 4 pscbx.lcba_hk 26 selects either the lcba0 field from pscbx or the lcba1 field depending on value of register pscbx.index 1, 2, 3 pscbx.lcba_tsr0 26 selects either the lcba0 field from pscbx or the lcba1 field, depending on value of register patbit_tsr0 1, 2, 4 pscbx.notnpa_hk 26 selects either the npa0 field from pscbx or the npa1 field depending on inverse value of register pscbx.index 1, 2, 3 pscbx.notnpa_tsr 0 26 selects either the npa0 field from pscbx or the npa1 field depending on inverse value of register patbit_tsr0 1, 2, 4 pscbx.notnbt_hk 8 selects either the nbt0 field from pscbx or the nbt1 field depending on inverse value of register pscbx.index 1, 2, 3 pscbx.notnbt_tsr 0 8 selects either the nbt0 field from pscbx or the nbt1 field depending on inverse value of register patbit_tsr0 1, 2, 4 pscbx.notlcba_hk 26 selects either the lcba0 field from pscbx or the lcba1 field depending on inverse value of register pscbx.index 1, 2, 3 pscbx.notlcba_ts r0 26 selects either the lcba0 field from pscbx or the lcba1 field depending on inverse value of register patbit_tsr0 1, 2, 4 1. x must equal 0, 1, or 2. 2. the indirect registers of the tse select, via dedicated hardware assist, one of the tse registers listed in section 8.2.6 tse reg- isters and register map on page 236. the indirect registers appear in the tse register map with a unique register number. 3. pscbx.index points to a specific bit in the hashedkey. the bit?s value determines whether the 0 or 1 part of pscbx will be read or written. 4. value of patbit_tsr0 determines whether the 0 or 1 part of pscbx will be read or written. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 239 of 444 table 164: address map for pscb0-2 registers in gth pscbx read/write pscb0 pscb1 pscb2 size npa0 r/w 80 a0 c0 26 nbt0 r/w 81 a1 c1 8 lcba0 r/w 82 a2 c2 26 npa1 r/w 84 a4 c4 26 nbt1 r/w 85 a5 c5 8 lcba1 r/w 86 a6 c6 26 addr r/w 88 a8 c8 26 index r/w 89 a9 c9 8 patbit r 8b ab cb 1 npa_hk r/w 90 b0 d0 26 nbt_hk r/w 91 b1 d1 8 lcba_hk r/w 92 b2 d2 26 notnpa_hk r/w 94 b4 d4 26 notnbt_hk r/w 95 b5 d5 8 notlcba_hk r/w 96 b6 d6 26 npa_tsr0 r/w 98 b8 d8 26 nbt_tsr0 r/w 99 b9 d9 8 lcba_tsr0 r/w 9a ba da 26 notnpa_tsr0 r/w 9c bc dc 26 notnbt_tsr0 r/w 9d bd dd 8 notlcba_tsr0 r/w 9e be de 26 IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 240 of 444 np3_dl_sec08_tree.fm.01 09/25/00 8.2.7 tse instructions 8.2.7.1 fm tree search (ts_fm) table 165: general tse instructions opcode command detail section 0null 1ts_fm 8.2.7.1 fm tree search (ts_fm) on page 240 2ts_lpm 8.2.7.2 lpm tree search (ts_lpm) on page 241 3 ts_smt 8.2.7.3 smt tree search (ts_smt) on page 242 4mrd 8.2.7.4 memory read (mrd) on page 243 5mwr 8.2.7.5 memory write (mwr) on page 244 6hk 8.2.7.6 hash key (hk) on page 244 7 rdludef 8.2.7.7 read ludeftable (rdludef) on page 245 8 compend 8.2.7.8 compare-at-end (compend) on page 245 9to15 reserved note: commands can be executed by all gxhs with threads. table 166: fm tree search input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable that controls the search. lcbanr 1 imm16(0) imm12(0) 0 search results are stored in tsrx/lcba0. 1 search results are stored in tsrx/lcba1. tsedpa 4 imm16(4..1) imm12(4..1) tse thread shared memory pool address - stores location of key, keylength, and color and determines leaf destination. the tsedpa is the high order 4 bits of the thread's shared memory pool address (see 7.2.10 shared memory pool on page 198) and is constrained to be on a four-qw boundary. use only values of x'8', x'a', x'c', and x'e'. key 192 shared memory pool key - pattern to be searched. must be initialized before search. located in shared memory pool. keylength 8 shared memory pool keylength - length of pattern minus 1 in key. must be initialized before search (done automatically using key instructions) located in shared memory pool. color 16 shared memory pool color - used only when enabled in ludeftable. must be initialized before search. located in shared memory poo.l following is available for gth only. useludefcopyreg 1 imm16(13) imm12(5) enables tse read of ludefcopy register. can save clock cycles, espe- cially when rdludef is executed asynchronously with the picocode that sets the key. 0 tse reads ludeftable. 1 tse does not read the ludeftable and uses information contained in ludefcopy register. assumes ludeftable was read previously using rdludef. ludefcopy 96 register input only when useludefcopyreg is ?1?. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 241 of 444 8.2.7.2 lpm tree search (ts_lpm) table 167: fm tree search results (tsr) output result bit length source description ok/ko 1 flag 0 ko: unsuccessful operation. 1 ok: successful operation. tsrx 512 shared memory pool when ok/ko is ?1?, leaf is read and stored in tsrx. tsrx is mapped into the shared memory pool, at an offset of 1 qw past the starting qw indicated by the input tsedpa parameter. that is, the shared memory pool qw location = tsedpa*4 + 1 lcba0 / 1 26 register when ok/ko is ?1?, leaf address is stored in lcba0 / 1. cacheflags 3 register see section 8.2.3.3 cache on page 228. nrpscbs 8 register see section 8.2.3.3 cache on page 228. following is available for gth only. ludefcopy 96 register output only when useludefcopyreg is ?0?. set to contents of ludeft- able at entry pointed to by ludefindex. table 168: lpm tree search input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable used to control the search lcbanr 1 imm16(0) imm12(0) 0 searchresultsarestoredintsrx/lcba0 1 searchresultsarestoredintsrx/lcba1 tsedpa 4 imm16(4..1) imm12(4..1) the tsedpa is the high order 4 bits of the thread's shared memory pool address (see 7.2.10 shared memory pool on page 198) and is con- strained to be on a four-qw boundary. use only values of x'8', x'a', x'c', and x'e'. key 192 shared memory pool key - pattern to be searched. must be initialized before search. located in shared memory pool. keylength 8 shared memory pool keylength - length of pattern minus 1 in key. must be initialized before search (done automatically using key instructions). located in shared memory pool. color 16 shared memory pool color - used only when enabled in ludeftable. must be initialized before search. located in shared memory pool. following is available for gth only. useludefcopyreg 1 imm16(13) imm12(5) enables tse read of ludefcopy register can save clock cycles, especially when rdludef is executed asyn- chronously with the picocode that sets the key. 0 tse reads ludeftable 1 tse does not read the ludeftable and uses information contained in ludefcopy register. assumes ludeftable was read previously using rdludef. ludefcopy 96 register input only when useludefcopyreg is ?1?. set to contents of ludeft- able at entry given by ludefindex IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 242 of 444 np3_dl_sec08_tree.fm.01 09/25/00 8.2.7.3 smt tree search (ts_smt) table 169: lpm tree search results (tsr) output result bits source description ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation tsrx 512 shared memory pool when ok/ko is ?1?, leaf is read and stored in tsrx tsrx is mapped into the shared memory pool, at an offset of 1 qw past the starting qw indicated by the input tsedpa parameter. that is, shared memory pool qw location = tsedpa*4 + 1 lcba0 / 1 26 register when ok/ko is ?1?, leaf address is stored in lcba0 / 1 cacheflags 3 register see section 8.2.3.3 cache on page 228 nrpscbs 8 register see section 8.2.3.3 cache on page 228 the following is available for gth only. ludefcopy 96 register output only when useludefcopyreg is ?0?. set to contents of ludeft- able at entry given by ludefindex table 170: smt tree search input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable used to control the search lcbanr 1 imm16(0) imm12(0) 0 search results are stored in tsrx/lcba0 1 search results are stored in tsrx/lcba1 tsedpa 4 imm16(4..1) imm12(4..1) the tsedpa is the high order 4 bits of the thread's shared memory pool address (see 7.2.10 shared memory pool on page 198) and is con- strained to be on a four-qw boundary. use only values of x'8', x'a', x'c', and x'e'. key 192 shared memory pool key - pattern to be searched. must be initialized before search. located in shared memory pool. keylength 8 shared memory pool keylength - length of pattern minus 1 in key. must be initialized before search (done automatically using key instructions). located in shared memory pool. color 16 shared memory pool color - used only when enabled in ludeftable. must be initialized before search. located in shared memory pool. following is available for gth only. useludefcopyreg 1 imm16(13) imm12(5) enables tse read of ludefcopy register can save clock cycles, especially when rdludef is executed asyn- chronously with the picocode that sets the key. 0 tse reads ludeftable 1 tse does not read the ludeftable and uses information contained in ludefcopy register. assumes ludeftable was read previously using rdludef. ludefcopy 96 register input only when useludefcopyreg is ?1?. set to contents of ludeft- able at entry given by ludefindex. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 243 of 444 8.2.7.4 memory read (mrd) the memory read command provides direct read capability from any location in the control store. lcba0 / 1 provide the full read address. shape is provided by the ludeftable (for leaf or pscb) or directly as part of the command field for the object. the content to be read is stored in tsrx. table 171: smt tree search results (tsr) output result bit length source description ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation tsrx 512 shared memory pool when ok is ?1?, leaf is read and stored in tsrx tsrx is mapped into the shared memory pool, at an offset of 1 qw past the starting qw indicated by the input tsedpa parameter. that is, shared memory pool qw location = tsedpa*4 + 1 lcba0 / 1 26 register when ok is ?1?, leaf address is stored in lcba0 / 1 cacheflags 3 register see section 8.2.3.3 cache on page 228 nrpscbs 8 register see section 8.2.3.3 cache on page 228 following are available for gth only. ludefcopy 96 register an output only when useludefcopyreg is ?0?. set to contents of ludeftable at entry given by ludefindex table 172: memory read input operands operand bit length operand source description direct indirect shapectrl 2 imm16(14..13) gpr(9..8) 00 direct shape 10 pscb shape from ludeftable 11 leaf shape from ludeftable ludefindex 8 imm16(12..5) gpr(7..0) ludeftable entry used to read shape information. valid only when shapectrl is ?10? or ?11?. width 2 imm16(9..8) gpr(4..3) width of object to be read. valid only when shapectrl is ?00?. height 3 imm16(7..5) gpr(2..0) height of object to be read. valid only when shapectrl is ?00?. tsedpa 4 imm16(4..1) imm12(4..1) the tsedpa is the high order 4 bits of the thread's shared memory pool address (see 7.2.10 shared memory pool on page 198) and is constrained to be on a four-qw boundary. lcbanr 1 imm16(0) imm12(0) 0 address to be read is lcba0 1 address to be read is lcba1 lcba0 / 1 26 register address to be read table 173: memory read output results result bit length source description tsrx 512 shared mem- ory pool tsrx is mapped into the shared memory pool, starting at the qw indicated by the input tsedpa parameter for a length of 4 qw. ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 244 of 444 np3_dl_sec08_tree.fm.01 09/25/00 8.2.7.5 memory write (mwr) the memory write command provides direct write capability to any location in the control store. lcba0 / 1 provide the full write address. shape is provided by the ludeftable (for leaf or pscb) or directly as part of the command field for the object. the content to be written is stored in tsrx. 8.2.7.6 hash key (hk) table 174: memory write input operands operand bit length operand source description direct indirect shapectrl 2 imm16(14..13) gpr(9..8) 00 direct shape 10 pscb shape from ludeftable 11 leaf shape from ludeftable ludefindex 8 imm16(12..5) gpr(7..0) ludeftable entry used to read shape information. valid only when shapectrl is ?10? or ?11?. width 2 imm16(9..8) gpr(4..3) width of object to be read. valid only when shapectrl is ?00?. height 3 imm16(7..5) gpr(2..0) height of object to be read. valid only when shapectrl is ?00?. tsedpa 4 imm16(4..1) imm12(4..1) the tsedpa is the high order 4 bits of the thread's shared memory pool address (see 7.2.10 shared memory pool on page 198) and is constrained to be on a four-qw boundary. lcbanr 1 imm16(0) imm12(0) 0 address to be written is lcba0 1 address to be written is lcba1 lcba0 / 1 26 register address to be written tsrx 512 shared memory pool data to be written. tsrx is mapped into the shared memory pool, starting at the qw indicated by the input tsedpa parameter for a length of 4 qw table 175: hash key input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable containing hash type tsedpa 4 imm16(4..1) imm12(4..1) thetsedpaisthehighorder4bitsofthethread'ssharedmemorypool address (see 7.2.10 shared memory pool on page 198) and is constrained to be on a four-qw boundary. use only values of x'8', x'a', x'c', and x'e'. direct_ hashtype_en 1 imm16(0) imm12(0) enable direct hashtype definition 0 hashtype defined by ludefentry 1 hashtype defined via command direct_ hashtype 4 imm16(8..5) gpr(3..0) use defined hash type for hashing. valid when direct_hashtype_en = 1 key 192 shared memory pool provides pattern to be searched. must be initialized before search. located in the shared memory pool. keylen 8 shared memory pool defines length of pattern minus 1 in key. must be initialized before search. located in the shared memory pool. color 16 shared memory pool must be initialized before search - used only when enabled in ludeftable. located in the shared memory pool. invalid when direct_hashtype_en is set to value ?1?. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 245 of 444 8.2.7.7 read ludeftable (rdludef) rdludef reads ludeftable at a specified entry and stores the result in the ludefcopy register. the tse can read ludeftable while picocode builds a key because rdludef is executed asynchronously. once the key is ready, the tree search execution can be executed with the useludefcopyreg flag set to ?1?. 8.2.7.8 compare-at-end (compend) compend performs a compare-at-end operation for smt trees. after a tree search command has per- formed a full search including a compend, picocode can obtain a pointer to another leaf chain from the leaf and start another compend on the leaf chain. the first leaf chain could contain leaves with filtering informa- table 176: hash key output results result bit length source description hashedkeyreg 192 shared memory pool hashed key register - contains the hashedkey (including color when enabled in ludeftable) according to section 8.2.1 input key and color register for fm and lpm trees on page 226 and section 8.2.2 input key and color register for smt trees on page 227. hash function is defined in the ludeftable. stored in the shared memory pool. hashedkeylen 8 shared memory pool hashed key length - contains the length of pattern minus 1 in hashedkeyreg. stored in thesharedmemorypool. dta 26 shared memory pool dtentry address. stored in shared memory pool. note: this is not valid when direct_hashtype_en is set to value ?1?. ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation following is available for gth only. ludefcopy 96 register set to contents of ludeftable at entry given by ludefindex. table 177: rdludef input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable tsedpa 4 imm16(4..1) imm12(4..1) the tsedpa is the high order 4 bits of the thread's shared memory pool address (see 7.2.10 shared memory pool on page 198) and is constrained to be on a four-qw boundary. table 178: rdludef output results result bit length source description ludefcopy 96 shared mem- ory pool set to contents of ludeftable at entry given by ludefindex and stored in shared memory pool. the entry is placed into two qw starting at the qw indicated by the tsedpa. the entry is right-justified with the most significant bits padded with 0. for gth, the scalar register will also have content of ludeftable at the entry. ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 246 of 444 np3_dl_sec08_tree.fm.01 09/25/00 tion, and the second could contain leaves with quality of service information. compend should be used only after a tree search command. table 179: compend input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12:5) gpr(7:0) defines the entry in the ludeftable. lcbnanr 1 imm16(0) imm12(0) 0 search results are stored in tsrx/lcba0 1 search results are stored in tsrx/lcba1 tsedpa 4 imm16(4..1) imm12(4..1) the tsedpa is the high order 4 bits of the thread's shared memory pool address (see 7.2.10 shared memory pool on page 198) and is constrained to be on a four-qw boundary. use only values of x?8?, x?a?, x?c?, and x?e?. lcba0 / 1 31 register start address of leaf chain and its shape. bits: 30:29 leaf width 28:26 leaf height 25:0 leaf address note: a valid leaf width and leaf height must be provided with the leaf address. hashedkey 192 shared memory pool output of previous tree search command located in the shared mem- ory pool at an offset of 2 and 3 qw from the qw indicated by the tsedpa. hashedkeylen 8 shared memory pool output of previous tree search command located in the shared mem- ory pool at the qw indicated by the tsedpa table 180: compend output results result bit length source description ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation tsrx 512 shared mem- ory pool when ok is ?1?, leaf is read and stored in tsrx when ok is ?0?, last leaf of chain is stored in tsrx tsrx is mapped into the shared memory pool, starting at an offset of 4 qw past the qw indicated by the input tsedpa parameter for a length of 4 qw. lcba0 / 1 26 register when ok is ?1?, leaf address is stored in lcba0 / 1 when ok is ?0?, leaf address of last leaf in chain is stored in lcba0 / 1 note: shape for the corresponding leaf will not be valid when lcaba0/1 is read. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 247 of 444 8.2.8 gth hardware assist instructions 8.2.8.1 hash key gth (hk_gth) table 181: general gth instructions opcode command detail section 16 hk_gth 8.2.8.1 hash key gth (hk_gth) on page 247 17 rdludef_gth 8.2.8.2 read ludeftable gth (rdludef gth) on page 248 18 tsenqfl 8.2.8.3 tree search enqueue free list (tsenqfl) on page 248 19 tsdqfl 8.2.8.4 tree search dequeue free list (tsdqfl) on page 249 20 rclr 8.2.8.5 read current leaf from rope (rclr) on page 250 21 ardl 8.2.8.6 advance rope with optional delete leaf (ardl) on page 251 22 tlir 8.2.8.7 tree leaf insert rope (tlir) on page 251 23 reserved 24 clrpscb 8.2.8.8 clear pscb (clrpscb) on page 252 25 rdpscb 8.2.8.9 read pscb (rdpscb) on page 252 26 wrpscb 8.2.8.10 write pscb (wrpscb) on page 253 27 pushpscb 8.2.8.11 push pscb (pushpscb) on page 254 28 distpos 8.2.8.12 distinguish (distpos) on page 254 29 tsr0pat 8.2.8.13 tsr0 pattern (tsr0pat) on page 255 30 pat2dta 8.2.8.14 pattern 2dta (pat2dta) on page 255 31 reserved note: the instructions listed in table 165: general tse instructions on page 240 can only be executed by the gth table 182: hash key gth input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable containing hash type tsedpa 4 imm16(4..1) imm12(4..1) thetsedpaisthehighorder4bitsofthethread'ssharedmemorypool address (see 7.2.10 shared memory pool on page 198) and is constrained to be on a four-qw boundary. direct_ hashtype_en 1 imm16(0) imm12(0) enable direct hashtype definition 0 hashtype defined by ludefentry 1 hashtype defined via command direct_ hashtype 4 imm16(8..5) gpr(3..0) use defined hash type for hashing. valid when direct_hashtype_en = 1 key 192 shared memory pool provides pattern to be searched. must be initialized before search. located in the shared memory pool. keylen 8 shared memory pool defines length of pattern minus 1 in key. must be initialized before search. located in the shared memory pool. color 16 shared memory pool must be initialized before search - used only when enabled in ludeftable. located in the shared memory pool. invalid when direct_hashtype_en is set to value ?1?. IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 248 of 444 np3_dl_sec08_tree.fm.01 09/25/00 8.2.8.2 read ludeftable gth (rdludef gth) rdludef reads the ludeftable at a specified entry and stores the result in the ludefcopy register. the tse can read ludeftable while picocode builds a key because rdludef is executed asynchronously. once the key is ready, the tree search execution can be executed with the useludefcopyreg flag set to ?1?. 8.2.8.3 tree search enqueue free list (tsenqfl) tsenqfl releases a control block such as a leaf or pscb to a free list. the address of the memory location to be freed is stored in lcba0 / 1. the leaf or pscb index to the free list is provided by the ludeftable or directly by the command line. the enqueue operation always adds an address to the bottom of a free list fifo-style. entries cannot be added or removed from the middle of a free list. when freelistctrl =11, tsen- qfl increments the leafcount field in ludeftable. table 183: hash key gth output results result bit length source description hashedkeyreg 192 register contains the hashedkey, including color when color is enabled in ludeftable, according to section 8.2.1 input key and color register for fm and lpm trees on page 226 and section 8.2.2 input key and color register for smt trees on page 227. hash function is defined in ludeftable. hashed key is not stored in shared memory pool. hashedkeylen 8 register contains length of pattern minus 1 in hashedkeyreg. hashed key is not stored in shared memory pool. dta 26 register dtentry address (hashed key is not stored in shared memory pool.) ludefcopy 96 register set to contents of ludeftable at entry given by ludefindex. note: valid for gth only. ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation table 184: rdludef_gth input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable table 185: rdludef_gth output results result bit length source description ludefcopy 96 register scalar register contains content of ludeftable at the entry. no content will be written back to shared memory pool. ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 249 of 444 8.2.8.4 tree search dequeue free list (tsdqfl) tsdqfl dequeues an address from a given fqlinklist. the address that has been dequeued from the free list is stored in lcba0 / 1. the leaf or pscb index to the free list is provided by the ludeftable or directly by the command line. when freelistctrl is ?11?, tsdqfl decrements the leafcount field in ludeftable. table 186: tsenqfl input operands operand bit length operand source description direct indirect freelistctrl 2 imm16(14..13) gpr(9..8) 00 direct free list index 10 pscb free list index from ludeftable 11 leaf free list index from ludeftable ludefindex/ freelistindex 8 imm16(12..5) gpr(7..0) defines the entry in the ludeftable used to read free list index infor- mation or directly defines freelistindex. srctype 3 imm16(2..0) imm12(2..0) 000 lcba0 001 lcba1 100 pscb0.addr (for gch only) 101 pscb1.addr (for gch only) 110 pscb2.addr (for gch only) lcba0 / 1 pscb0/1/2.addr 26 register the address to be freed or enqueued table 187: tsenqfl output results result bit length source description ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation table 188: tsdqfl input operands operand bit length operand source description direct indirect freelistctrl 2 imm16(14..13) gpr(9..8) 00 direct free list index 10 pscb free list index from ludeftable 11 leaf free list index from ludeftable ludefindex/ freelistindex 8 imm16(12..5) gpr(7..0) defines the entry in ludeftable used to read free list index informa- tion or directly defines freelistindex. tgttype 3 imm16(2..0) imm12(2..0) 000 lcba0 001 lcba1 100 pscb0.addr (for gch only) 101 pscb1.addr (for gch only) 110 pscb2.addr (for gch only) IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 250 of 444 np3_dl_sec08_tree.fm.01 09/25/00 8.2.8.5 read current leaf from rope (rclr) rclr is used to ?walk the rope? for such processes as aging. rclr reads the leaf at the current leaf address defined in ludeftable. it stores the leaf address in lcba0 and the leaf contents in tsr0. when rope walking begins, the tse invokes rclr and picocode saves the leaf address (lcba0) in a gpr. before reading the next leaf, the tse invokes the advance rope with optional delete leaf command (ardl), after which rclr can be invoked again. to determine whether a rope walk has ended, picocode compares lcba0 with the gpr to verify whether the leaf that was read is the same as the first leaf. if the leaf is the same, the rope walk has ended. at any time during the rope walk, picocode can delete a leaf from the rope using ardl with the deleteleaf flag set to 1. this is useful when the leaf is to be aged out. rclr can automatically delete leaves from the rope when the deletepending bit in the leaf is set. when this feature is enabled, the tse deletes a leaf and reads the next leaf, which is also deleted when the deletepending bit is set. the process is repeated to delete multiple leaves. after rclr has executed with ok = 1, the contents of tsr0 and lcba0 correspond with cla in the ludeft- able, and the previous leaf on the rope has an address of pla. ok = 0, or ko, means the rope is empty. table 189: tsdqfl output results result bit length source description lcbao/1 pscb0/1/2.addr 26 register dequeued address ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation table 190: rclr input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable used to read rope reserved 3 imm16(3..1) imm12(3..1) must be set to ?000? delenable 1 imm16(0) imm12(0) when ?1?, leaves with deletepending bit are automatically deleted from rope and leaf address will be enqueued in leaf free queue tsedpa 4 imm16(4..1) imm12(4..1) location for the leaf to be stored. the tsedpa is the high order 4 bits of the thread's shared memory pool address (see 7.2.10 shared mem- ory pool on page 198) and is constrained to be on a four-qw bound- ary. table 191: rclr output results result bit length source description ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation lcba0 26 register address of leaf that has been read tsrx 512 shared memory pool leaf content is stored in tsrx. tsrx is mapped into the shared memory pool, starting at an offset of 4 qw past the qw indicated by the input tsedpa parameter for a length of 4 qw. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 251 of 444 8.2.8.6 advance rope with optional delete leaf (ardl) ardl advances the rope, or updates cla and pla in ludeftable. the nla field from the leaf already stored in tsr0 is read and stored in cla. pla is then updated to the previous value of cla unless the leaf is deleted. in this case, pla remains the same and the nlarope field for the leaf with the current pla address is set to the new cla. when leaf deletion is enabled, the current leaf is deleted prior to advancing the rope. the contents of tsr0 and lcba0 can be destroyed because ardl uses tsr0 and lcba0 as work areas to update the nlarope field. after ardl is executed, cla and pla (in the ludeftable) are updated and rclr (described in the next section) can be executed again. 8.2.8.7 tree leaf insert rope (tlir) tlir inserts a leaf into the rope. the leaf must already be stored in tsr0 (done automatically by picocode during tlir) and the leaf address must already be available in lcba0. tlir maintains the rope, which involves updating the pva field in ludeftable, the nlarope leaf field in control store, and the nlarope leaf field stored in tsrx. the leaf is inserted into the rope ahead of the current leaf, which has address cla. field pla is updated to the new leaf address, which is lcba0 / 1, in ludeftable. following tlir execution, picocode must invoke mwr to write the leaf into control store. the contents of tsr1 and lcba1 can be destroyed because tlir uses tsr1 and lcba1 as a work area. table 192: ardl input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable deleteleaf 1 imm16(0) imm12(0) enable deletion of current leaf from rope. 0 do not delete leaf. 1 delete leaf tsedpa 4 imm16(4..1) imm12(4..1) location of the current leaf address. the tsedpa is the high order 4 bits of the thread's shared memory pool address (see 7.2.10 shared memory pool on page 198) and is constrained to be on a four-qw boundary. tsrx 26 register contents of current leaf (address cla in ludeftable). tsrx is mapped into the shared memory pool, starting at an offset of 4 qw past the qw indicated by the input tsedpa parameter for a length of 4 qw. table 193: ardl output results result bit length source description tsrx 512 shared memory pool contents of tsrx will not be destroyed lcba0 26 register contents of lcba0 have been destroyed ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 252 of 444 np3_dl_sec08_tree.fm.01 09/25/00 8.2.8.8 clear pscb (clrpscb) this command writes all zeros to pscb0 / 1 / 2. 8.2.8.9 read pscb (rdpscb) rdpscb reads a pscb from the control store and stores it in one of the pscb0 / 1 / 2 registers. for lpm, the entire pscb is read from memory at the address given by pscb IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 253 of 444 8.2.8.10 write pscb (wrpscb) wrpscb writes a pscb stored in pscb0, 1, or 2 to the control store. for lpm, the entire pscb is written to memory to the address given by pscb IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 254 of 444 np3_dl_sec08_tree.fm.01 09/25/00 8.2.8.11 push pscb (pushpscb) pushpscb pushes the pscb stack. 8.2.8.12 distinguish (distpos) distpos performs a pattern compare between the patterns stored in hashedkey and tsr0. the result is stored in the distposreg register. the ok flag is set when a full match has been detected. table 201: pushpscb input operands operand bit length operand source description direct indirect pscb0 -- -- contains a pscb pscb1 -- -- contains a pscb table 202: pushpscb output results result bit length source description pscb2 -- register set to pscb1 pscb1 -- register set to pscb0 pscb0 -- register set to all zeros ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation table 203: distpos input operands operand bit length operand source description direct indirect hashedkey 192 register contains hashed pattern hashedkeylen 8 register contains length of hashed pattern minus 1 tsedpa 4 imm16(4..1) imm12(4..1) the tsedpa is the high order 4 bits of the thread's shared memory pool address (see 7.2.10 shared memory pool on page 198) and is constrained to be on a four-qw boundary. use only values of x'8', x'a', x'c', and x'e'. tsrx 512 shared memory pool contains second pattern with pattern length (for lpm only). tsrx is mapped into the shared memory pool, starting at an offset of 4 qw past the qw indicated by the input tsedpa parameter for a length of 4 qw. table 204: distpos output results result bit length source description ok/ko 1 flag 0 pattern does not match 1 pattern in hashedkey matches pattern in tsrx distpos 8 register smallest bit position where pattern in hashedkey differs from pattern in tsrx ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 255 of 444 8.2.8.13 tsr0 pattern (tsr0pat) tsr0pat reads a bit from the pattern stored in tsrx and stores this bit in the patbit_tsr0 register. 8.2.8.14 pattern 2dta (pat2dta) pat2dta reads a pattern from tsrx, stores it in the hashedkey, and sets the dta register accordingly. pat2dta does not perform a hash since the pattern in a leaf is already hashed. pattern read from tsrx is assumed to be already hashed. table 205: tsr0pat input operands operand bit length operand source description direct indirect bitnum 8 -- gpr(7..0) selects bit in tsr0 pattern tsedpa 4 imm16(4..1) imm12(4..1) the tsedpa is the high order 4 bits of the thread's shared memory pool address (see 7.2.10 shared memory pool on page 198) and is constrained to be on a four-qw boundary. use only values of x'8', x'a', x'c', and x'e'. table 206: tsr0pat output results result bit length source description patbit_tsr0 1 register set to value of bit bitnum of pattern stored in tsr0 ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation table 207: pat2dta input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable used to calculate dta from hashedkey tsedpa 4 imm16(4..1) imm12(4..1) the tsedpa is the high order 4 bits of the thread's shared memory pool address (see 7.2.10 shared memory pool on page 198) and is constrained to be on a four-qw boundary. use only values of x'8', x'a', x'c', and x'e'. table 208: pat2dta output results result bit length source description dta 26 register dtentry address corresponding to dt definition in ludeftable and hashedkey ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 256 of 444 np3_dl_sec08_tree.fm.01 09/25/00 8.2.9 hash functions in the following figures, the input is always the 192-bit key and the output is a 192-bit hashed output before color insertion. if color is enabled, the color is inserted at the bit position given by dtsize in the ludeftable and 16 lsbs of the key are ignored since maximum key length of 176 bits is supported when color is enabled. table 209: general hash functions hash_type name description 0 no hash no hash is performed and hashed output h(191..0) equals input key k(191..0). can be used for smt trees or lpm trees if 32-bit ip lpm hash cannot be used. 1192-bitiphash uses four copies of ip hash box. see figure 61: 192-bit ip hash function on page 257 2 192-bit mac hash see figure 62: mac hash function on page 258 3 192-bit network distpos see figure 63: network dispatcher hash function on page 259 4reserved 5 48-bit mac swap see figure 64: 48-bit mac hash function on page 260 6 60-bit mac swap see figure 65: 60-bit mac hash function on page 261 7 192-bit smt key see figure 60: no-hash function on page 256 8reserved 9reserved 10 reserved figure 60: no-hash function b0 a0 k0 (bits 191..160) d0 c0 b4 a4 k4 (bits 63..32) d4 c4 b5 a5 k5 (bits 31..0) d5 c5 b1 a1 k1 (bits 159..128) d1 c1 b2 a2 k2 (bits 127..96) d2 c2 b3 a3 k3 (bits 95..64) d3 c3 a0 h0 (bits 191..160) d0 c0 b4 a4 h4 (bits 63..32) d4 c4 b5 a5 h5 (bits 31..0) d5 c5 b1 a1 h1 (bits 159..128) d1 c1 b2 a2 h2 (bits 127..96) d2 c2 b3 a3 h3 (bits 95..64) d3 c3 b0 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 257 of 444 figure 61: 192-bit ip hash function b0 a0 k0 (bits 191..160) d0 c0 b4 a4 k4 (bits 63..32) d4 c4 b5 a5 k5 (bits 31..0) d5 c5 b1 a1 k1 (bits 159..128) d1 c1 b2 a2 k2 (bits 127..96) d2 c2 b3 a3 k3 (bits 95..64) d3 c3 ip hash box ip hash box ip hash box ip hash box ip hash box ip hash box a0 h0 (bits 191..160) d0 c0 b4 a4 h4 (bits 63..32) d4 c4 b5 a5 h5 (bits 31..0) d5 c5 b1 a1 h1 (bits 159..128) d1 c1 b2 a2 h2 (bits 127..96) d2 c2 b3 a3 h3 (bits 95..64) d3 c3 b0 IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 258 of 444 np3_dl_sec08_tree.fm.01 09/25/00 figure 62: mac hash function b0 a0 k0 (bits 191..160) d0 c0 b4 a4 k4 (bits 63..32) d4 c4 b5 a5 k5 (bits 31..0) d5 c5 b1 a1 k1 (bits 159..128) d1 c1 b2 a2 k2 (bits 127..96) d2 c2 b3 a3 k3 (bits 95..64) d3 c3 ip hash box ip hash box ip hash box ip hash box ip hash box ip hash box a0 h0 (bits 191..160) d0 c0 b4 a4 h4 (bits 63..32) d4 c4 b5 a5 h5 (bits 31..0) d5 c5 b1 a1 h1 (bits 159..128) d1 c1 b2 a2 h2 (bits 127..96) d2 c2 b3 a3 h3 (bits 95..64) d3 c3 b0 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 259 of 444 figure 63: network dispatcher hash function b0 a0 k0 (bits 191..160) d0 c0 b4 a4 k4 (bits 63..32) d4 c4 b5 a5 k5 (bits 31..0) d5 c5 b1 a1 k1 (bits 159..128) d1 c1 b2 a2 k2 (bits 127..96) d2 c2 b3 a3 k3 (bits 95..64) d3 c3 ip hash box ip hash box ip hash box ip hash box ip hash box ip hash box a0 h0 (bits 191..160) d0 c0 b4 a4 h4 (bits 63..32) d4 c4 b5 a5 h5 (bits 31..0) d5 c5 b1 a1 h1 (bits 159..128) d1 c1 b2 a2 h2 (bits 127..96) d2 c2 b3 a3 h3 (bits 95..64) d3 c3 b0 32-bit bitwise swap o(i) i(31-i) IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 260 of 444 np3_dl_sec08_tree.fm.01 09/25/00 figure 64: 48-bit mac hash function b0 a0 k0 (bits 191..160) d0 c0 b4 a4 k4 (bits 63..32) d4 c4 b5 a5 k5 (bits 31..0) d5 c5 b1 a1 k1 (bits 159..128) d1 c1 b2 a2 k2 (bits 127..96) d2 c2 b3 a3 k3 (bits 95..64) d3 c3 ip hash box ip hash box ip hash box ip hash box ip hash box ip hash box a0 h0 (bits 191..160) d0 c0 b4 a4 h4 (bits 63..32) d4 c4 b5 a5 h5 (bits 31..0) d5 c5 b1 a1 h1 (bits 159..128) d1 c1 b2 a2 h2 (bits 127..96) d2 c2 b3 a3 h3 (bits 95..64) d3 c3 b0 48-bit bitwise swap o(i) i(47-i) IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec08_tree.fm.01 09/25/00 tree search engine page 261 of 444 figure 65: 60-bit mac hash function b0 a0 k0 (bits 191..160) d0 c0 b4 a4 k4 (bits 63..32) d4 c4 b5 a5 k5 (bits 31..0) d5 c5 b1 a1 k1 (bits 159..128) d1 c1 b2 a2 k2 (bits 127..96) d2 c2 b3 a3 k3 (bits 95..64) d3 c3 ip hash box ip hash box ip hash box ip hash box ip hash box ip hash box a0 h0 (bits 191..160) d0 c0 b4 a4 h4 (bits 63..32) d4 c4 b5 a5 h5 (bits 31..0) d5 c5 b1 a1 h1 (bits 159..128) d1 c1 b2 a2 h2 (bits 127..96) d2 c2 b3 a3 h3 (bits 95..64) d3 c3 b0 60-bit bitwise swap o(i) i(59-i) 84 4 IBM32NPR161EPXCAC133 ibm powernp preliminary tree search engine page 262 of 444 np3_dl_sec08_tree.fm.01 09/25/00 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec09_spm.fm.01 09/25/00 serial/parallel manager interface page 263 of 444 9. serial/parallel manager interface the serial/parallel manager (spm) interface is a serial interface to communicate with external devices. the spm interface consists of a clock signal output, a bi-directional data signal, and an interrupt input. on this interface, the np4gs3 is the master and the external spm module is the only slave 1 . the spm interface loads picocode, allowing management of physical layer components and access to card-based functions such as leds. the spm interface supports: an external spm module boot code load via external spm and eeprom boot override via cabwatch interface or boot_picocode configuration chip i/o. access to external phy, led, management, and card-based functions 9.1 spm interface components 1.the external spm module is not supplied by ibm. figure 66: spm interface block diagram boot state machine starts up after reset if configured to do so by an external io pin (boot_picocode set to 0). it selects one of two boot images (picocode loads) based on a configuration flag found in the eeprom and places the code into the instruction memory in the epc. once the code is loaded, the boot state machine causes an interrupt that starts up the gfh. the gfh executes the loaded code. cab interface a memory mapped interface to the np4gs3 that allows the protocol processors to access any external device, including an spm module, external phys, or card leds. parallel to serial control converts between the internal 32-bit read/write parallel interface and the 3-bit external bi-directional serial interface. instruction memory cab boot state machine cab interface parallel to serial control external spm module IBM32NPR161EPXCAC133 ibm powernp preliminary serial/parallel manager interface page 264 of 444 np3_dl_sec09_spm.fm.01 09/25/00 9.2 spm interface data flow the spm interface is used initially to boot the np4gs3. following a reset, the spm interface reads an exter- nal eeprom and loads the eeprom?s contents into the epc?s instruction memory. when loading is com- plete, the spm interface issues a ?boot done? interrupt which causes the guided frame handler (gfh) to start executing the boot code. the boot code initializes the network processor?s internal structures and config- ures all the interfaces that the network processor requires to operate. when all boot processing is complete, the gfh activates the operational signal to indicate its availability to the control point function (cpf). the cpf sends guided frames to further initialize and configure the network processor, preparing it for network operation. figure 67: epc boot image in external eeprom boot flag dasl picocode x?0 0000? x?0 0001? x?0 4000? boot code & post & boot gfh 70 x?0 4001? 16 k 8k x?0 6000? x?0 6001? post overflow & extended post 16 k x?0 a000? x?0 a001? other 24 k not used dasl picocode x?1 0000? x?1 0001? x?1 4000? boot code & post & boot gfh x?1 4001? 16 k 8k x?1 6000? x?1 6001? post overflow & extended post 16 k x?1 a000? x?1 a001? other 24 k x?0 ffff? x?1 ffff? image b image a IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec09_spm.fm.01 09/25/00 serial/parallel manager interface page 265 of 444 the boot state machine supports two images of boot code in external eeprom. the contents of byte x'0 0000' in eeprom is examined during the read process to determine which image to l oad. when the most significant bit of this byte is a ?0?, the current image resides at addresses x?0 0001? - x?0 4000?. otherwise, the current image resides at addresses x?1 0001? - x?1 4000?. the boot state machine will load the appropriate image and allow the other image area to be used for boot code updates. the spm interface is also used during initialization and statistics gathering. it interfaces to the ethernet phys, card leds, and other card-level structures through an external spm interface module supplied by the customer. these external structures are mapped to the cab address space and are accessed from the pico- code using the same methods as those used to access any internal data structures: the picocode issues reads or writes to the appropriate address and the spm interface converts these reads and writes to serial communications with the external spm module. the external spm module re-converts these serial communi- cations to register reads and writes and to access the desired card device. through the spm interface, the picocode has indirect access to all card-level functions and can configure or gather statistics from these devices as if they were directly attached to the cab interface. 9.3 spm interface protocol the spm interface operates synchronously with respect to the 33 mhz clock signal output. data, address, and control information is transferred serially on a bidirectional data signal. transitions on this data signal occur at the rising edges of the clock signal. each data exchange is initiated by the np4gs3 and can be one to four bytes in length. for single byte transfers, the exchange begins when the np4gs3 drives the data signal to ?1? for one clock period. this ?select? indication is followed by a 1-bit write/read indication, a 4-bit burst length indication, and a 25-bit address value. for read and write transfers, when the sdm interface master is waiting for a response from the sdm interface slave, the slave communicates with the master using the following: ack: a ?1? driven onto the databus by the sdm interface slave to indicate each successful byte operation, either read or write. ack : a ?0? driven onto the databus by the sdm interface slave while the byte operation is in progress. for write transfers (see figure 70: spm interface write protocol on page 266), the address is followed imme- diately by eight bits of data. the np4gs3 then puts its driver in high-z mode. one clock period later, the slave drives the data signal to ?0? (ack ) until the byte write operation is complete. the slave then drives the data signal to ?1? (ack). during the byte write operation, the np4gs3 samples the data input looking for a ?1? (ack). immediately following the ack, the slave puts its driver in high-z mode. the transfer is concluded one clock period later. for read transfers (see figure 69: spm interface read protocol on page 266), the address is followed by the np4gs3 putting its driver into high-z mode. one clock period later, the slave drives the data signal to ?0? (ack ) until the byte of read data is ready for transfer. the slave then drives the data signal to ?1? (ack). during this time, the np4gs3 samples the data input looking for an ack. immediately following the ack, the slave drives the eight bits of data onto the data signal and then puts its driver in high-z mode. the transfer is con- cluded one clock period later. the protocol for multiple byte transfers is similar except that each byte written is accompanied by a bus turn- around, zero or more ack s, and an ack. read bursts are characterized by the slave retaining bus ownership until the last byte of the burst is transferred. each successive byte read is preceded by at least one ?0? on the IBM32NPR161EPXCAC133 ibm powernp preliminary serial/parallel manager interface page 266 of 444 np3_dl_sec09_spm.fm.01 09/25/00 databus followed by one ?1? on the databus (ack), and immediately followed by the eight bits of data. exam- ples of the read and write protocols are shown in figure 69 and figure 70 respectively. figure 68: spm bit timing figure 69: spm interface read protocol figure 70: spm interface write protocol t.25t clock ... data .25t .25t ... read sel ... ... idle ... r/w read sel ... ... idle ... ... ... r/w ... onebyteread two byte read (burst length = 0010) one or more ack s preceding one ack zero or more ack s preceding one ack new sequence can begin here bl3 bl0 a24 a0 ts ack d7 d0 ts sel bl3 bl0 a24 a0 ack ts d7 d0 ack d0 ts sel note: bl# = bit # of the burst length a# = bit # of the address ack = acknowledgment sel = select d7 sel write ... ... idle sel write ... ... idle r/w ... one byte write two byte write (burst length = 0010) ... r/w ... ... ... zero or more ack s preceding one ack new sequence can begin here bl3 bl0 a24 a0 d7 d0 ts ack ts sel bl3 bl0 a24 a0 d7 ts ts ts ts d0 ack start d7 ack d0 sel note: bl# = bit # of the burst length a# = bit # of the address ack = acknowledgment sel = select IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec09_spm.fm.01 09/25/00 serial/parallel manager interface page 267 of 444 9.4spmcabaddressspace the spm interface provides cab access to an external eeprom and to other devices attached via an exter- nal spm module developed by the customer. the address space is broken into three areas: byteaccess wordaccess eeprom access 9.4.1 byte access space all elements accessed in byte access space are limited to a single byte in width. 9.4.2 word access space all elements accessed in word access space are a word in width. access type r/w base addresses x?2800 0000? through x?281f ffff? x?2880 0000? through x?28ff ffff? byte data reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description byte data 31:24 data at this location reserved 23:0 reserved access type: r/w base addresses: x?2820 0000? through x?287f ffff? word data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description word data 31:0 data at this location IBM32NPR161EPXCAC133 ibm powernp preliminary serial/parallel manager interface page 268 of 444 np3_dl_sec09_spm.fm.01 09/25/00 9.4.3 eeprom access space the spm interface and a customer supplied spm module can be combined to provide access to an attached eeprom. the eeprom access space contains locations for 8224 1-byte elements. all write accesses are limited to a single byte, but read accesses may be in bursts of 1, 2, 3, or 4 bytes. the cab address is formed using the field definitions shown in table 210 . table 210: field definitions for cab addresses bits description 31:27 ?00101? 26:25 encoded burst length 00 4-byte burst (read only) 01 1-byte burst (read or write) 10 2-byte burst (read only) 11 3-byte burst (read only) 24 ?1? 23:0 starting byte address for read or write action IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec09_spm.fm.01 09/25/00 serial/parallel manager interface page 269 of 444 9.4.3.1 eeprom byte access addresses in this space are used for single-byte read or write access to the eeprom. access type: r/w base addresses: x?2b00 0000? through x?2bff ffff? byte data reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description byte data 31:24 data at starting byte address reserved 23:0 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary serial/parallel manager interface page 270 of 444 np3_dl_sec09_spm.fm.01 09/25/00 9.4.3.2 eeprom 2 byte access addresses in this space are used for a 2-byte read burst access to the eeprom. access type: read only base addresses: x?2d00 0000? through x?2dff ffff? byte 0 data byte 1 data reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description byte 0 data 31:24 data at starting byte address byte 1 data 23:16 data at starting byte address + 1 reserved 15:0 reserved IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec09_spm.fm.01 09/25/00 serial/parallel manager interface page 271 of 444 9.4.3.3 eeprom 3 byte access addresses in this space are used for a 3-byte read burst access to the eeprom. access type: read only base addresses: x?2f00 0000? through x?2fff ffff? byte 0 data byte 1 data byte 2 data reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description byte 0 data 31:24 data at byte address byte 1 data 23:16 data at byte address + 1 byte 2 data 15:8 data byte address + 2 reserved 7:0 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary serial/parallel manager interface page 272 of 444 np3_dl_sec09_spm.fm.01 09/25/00 9.4.3.4 eeprom 4 byte access addresses in this space are used for a 4-byte read burst access to the eeprom. access type: read only base addresses: x?2900 0000? through x?29ff ffff? byte 0 data byte 1 data byte 2 data byte 3 data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description byte 0 data 31:24 data at byte address byte 1 data 23:16 data at byte address + 1 byte 2 data 15:8 data byte address + 2 byte 3 data 7:0 data byte address + 3 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 273 of 444 10. embedded powerpc? 10.1 description the np4gs3 incorporates an embedded powerpc subsystem. this subsystem consists of mixture of mac- ros from ibm?s powerpc macro library and other components that were designed specifically for the np4gs3. standard ibm powerpc macros include the following: 133 mhz 405 processor core with 16 k of instruction cache and 16 k of data cache 133 mhz, 64-bit plb macro with plb arbiter 33/66 mhz, 32-bit pci to 133 mhz, 64-bit plb macro powerpc universal interrupt controller (uic) macro the embedded powerpc subsystem includes a cab interface plb slave unit to access np4gs3 internal structures and a mailbox and dram interface plb slave unit for inter-processor communications and access to powerpc instructions. figure 71: powerpc block diagram powerpc 64-bit plb arbiter pci/plb mailbox & epc gph reset cntl to d r am to p c i bu s cab 405 core interface dram i/f macro dram controller dram arbiter cab arbiter cab interrupts universal interrupt controller IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 274 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.2 processor local bus and device control register buses the on-chip bus structure consisting of the processor local bus (plb) and the device control register bus (dcr) provides a link between the processor core and the other peripherals (plb master and slave devices) used in powerpc subsystem design. the plb is the high performance bus used to access memory, pci devices, and network processor struc- tures through the plb interface units. the plb interface units shown in figure 71 , the cab interface and the mailbox & dram interface, are plb slaves. the processor core has two plb master connections, one for instruction cache and one for data cache. the pci to plb interface unit, which is both a plb master and plb slave device, is also attached to the plb. the plb master corresponds to the pci target and the plb slave corresponds to the pci master. each plb master is attached to the plb through separate address, read data, and write data buses and a plurality of transfer qualifier signals. plb slaves are attached to the plb through shared, but decoupled, address, read data, and write data buses and a plurality of transfer control and status signals for each data bus. access to the plb is granted through a central arbitration mechanism that allows masters to compete for bus ownership. this mechanism is flexible enough to provide for the implementation of various priority schemes. additionally, an arbitration locking mechanism is provided to support master-driven atomic operations. the plb is a fully-synchronous bus. timing for all plb signals is provided by a single clock source that is shared by all masters and slaves attached to the plb. all plb arbiter registers are device control registers. they are accessed by using the move from device control register (mfdcr) and move to device control register (mtdcr) instructions. plb arbiter registers are architected as 32-bits and are privileged for both read and write. the dcr base address of the plb registers is x'080'. the dcr base address of the uic registers is x'0c0'. details regarding the plb and uic device control registers can be found in the ppc405gp embedded controller user?s manual ( http:// www.chips.ibm.com/products/powerpc/chips/ ). the device control register (dcr) bus is used primarily to access status and control registers within the plb and the universal interrupt controller (uic). the dcr bus architecture allows data transfers among peripherals to occur independently from, and concurrent with, data transfers between the processor and memory or among other plb devices. table 211: plb master connections master id master unit description 0 processor core instruction cache unit 1 processor core data cache unit 2 plb/pci macro unit others unused IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 275 of 444 10.3 universal interrupt controller (uic) the universal interrupt controller (uic) provides all the necessary control, status, and communication between the various of interrupts sources and the microprocessor core. the uic supports six on-chip and two external sources of interrupts. status reporting (using the uic status register (uicsr)) is provided to ensure that systems software can determine the current and interrupting state of the system and respond appropri- ately. software can generate interrupts to simplify software development and for diagnostics. the interrupts can be programmed, using the uic critical register (uiccr), to generate either a critical or a non-critical interrupt signal. the uic supports internal and external interrupt sources as defined in table 212. the on-chip interrupts (interrupts 0, and 3-7) and the external interrupts (interrupts 1-2) are programmable. however, the on-chip interrupts must be programmed as shown in table 212. for details regarding the con- trol of the uic, including the programming of interrupts, see the ppc405gp embedded controller user?s manual ( http://www.chips.ibm.com/products/powerpc/chips/ ). table 212: uic interrupt assignments interrupt polarity sensitivity interrupt source 0 high edge dram d6 parity error 1 programmable programmable external interrupt 0 2 programmable programmable external interrupt 1 3 high level pci host to powerpc doorbell interrupt 4 high level pci host to powerpc message interrupt 5 high level embedded processor complex to powerpc doorbell interrupt 6 high level embedded processor complex to powerpc message interrupt 7 high level pci command write interrupt 8-31 unused, interrupt input to uic tied low. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 276 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.4 pci/plb macro the peripheral component interconnect (pci) interface controller provides an interface for connecting plb- compliant devices to pci devices. the controller complies with pci specification, version 2.2. ( http:// www.pcisig.com ). the pci/plb macro responds as a target on the plb bus in several address ranges. these ranges allow a plb master to configure the pci/plb macro, and to cause the pci/plb macro to generate memory, i/o, con- figuration, interrupt acknowledge, and special cycles to the pci bus. table 213 shows the address map from the view of the plb, that is, as decoded by the pci/plb macro as a plb slave. table 213: plb address map for pci/plb macro plb address range description pci address range x?e800 0000? - x?e800 ffff? pci i/o accesses to this range are translated to an i/o access on pci in the range 0 to 64 kb - 1 x?0000 0000? - x?0000 ffff? x?e801 0000 x?e87f ffff? reserved pci/plb macro does not respond (other bridges use this space for non-contiguous i/o). x?e880 0000? - x?ebff ffff? pci i/o accesses to this range are translated to an i/o access on pci intherange8mbto64mb-1 x?0080 0000? - x?03ff ffff? x?ec00 0000? - x?eebf ffff? reserved pci macro does not respond x?eec0 0000? - x?eecf ffff? pcicfgadr and pcicfgdata x?eec0 0000?: config_address x?eec0 0004?: config_data x?eec0 0008? - x?eecf ffff?: reserved (can mirror pcicf- gadr and pcicfgdata) x?eed0 0000? - x?eedf ffff? pci interrupt acknowledge and special cycle x?eed0 0000? read: interrupt acknowledge x?eed0 0000? write: special cycle x?eed0 0004? - x?eedf ffff?: reserved (can mirror interrupt acknowledge and special cycle) x?eee0 0000? - x?ef3f ffff? reserved pci/plb macro does not respond IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 277 of 444 following a general reset of the network processor, the pci target map 1 is enabled for a pci address range of 128 kb and is mapped to the plb address range of x?7800 0000 - 7801 ffff?. the corresponding pci base address for this range must be set by pci configuration of the pci ptm1 base address register. like- wise, the pci target map 2 is enabled for a pci address range of 128 mb and is mapped to the plb address range of x?0000 0000 - 03ff ffff?. the corresponding pci base address for this range must be set by pci configuration of the pci ptm2 base address register. the pci/plb macro has a mode that enables a plb master to access a pci memory range without initial configuration cycles. this mode is enabled by strapping the boot_ppc input pin high. system designers, for instance, may use this mode to allow a processor to access a boot rom in pci memory space. in this mode the pci/plb macro comes out of reset with pmm0 enabled and programmed for the address range x?fffe 0000? - x?ffff ffff?. the me field of the pci command register (pcicmd[me]) is also set to 1 after reset. enabling pci boot mode does not prevent subsequent updates to the pmm0 registers. the general reset initializes the pci/plb macro?s bridge options 2 register (pcibrdgopt2) with its host configuration enable bit set to ?1? (enabled). this allows an external source to access the pci/plb macro?s configuration registers. for further details regarding the pci/plb macro?s control and configuration registers, see the ppc405gp embedded controller user?s manual ( http://www.chips.ibm.com/products/powerpc/chips/ ). x?ef40 0000? - x?ef4f ffff? pci/plb macro local configuration registers x?ef40 0000?: pmm0la x?ef40 0004?: pmm0ma x?ef40 0008?: pmm0pcila x?ef40 000c?: pmm0pciha x?ef40 0010?: pmm1la x?ef40 0014?: pmm1ma x?ef40 0018?: pmm1pcila x?ef40 001c?: pmm1pciha x?ef40 0020?: pmm2la x?ef40 0024?: pmm2ma x?ef40 0028?: pmm2pcila x?ef40 002c?: pmm2pciha x?ef40 0030?: ptm1ms x?ef40 0034?: ptm1la x?ef40 0038?: ptm1ms x?ef40 003c?: ptm1ms x?f400 0400? - x?ef4f ffff?: reserved (can mirror pci local registers) x?0000 0000? - x?ffff ffff? pci memory - range 0 pmm 0 registers map a region in plb space to a region in pci memory space. the address ranges are fully programmable. the pci address is 64 bits. x?0000 0000 0000 0000? x?ffff ffff ffff ffff? x?0000 0000? - x?ffff ffff? pci memory - range 1 pmm 1 registers map a region in plb space to a region in pci memory space. the address ranges are fully programmable. the pci address is 64 bits. x?0000 0000 0000 0000? x?ffff ffff ffff ffff? x?0000 0000? - x?ffff ffff? pci memory - range 2 pmm 2 registers map a region in plb space to a region in pci memory space. the address ranges are fully programmable. the pci address is 64 bits. x?0000 0000 0000 0000? x?ffff ffff ffff ffff? table 213: plb address map for pci/plb macro plb address range description pci address range IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 278 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.5 plb address map components of the embedded powerpc are connected using the processor local bus (plb). these compo- nents recognize plb address values as their own. these plb address values are fixed by hardware. the plb address map describes the association of plb address values and the components that recognize them. symbolic address plb address description access cab interface macro pwrpc_cab_addr x ? 7800 0000 ? powerpc cab address register r/w pwrpc_cab_data x ? 7800 0008 ? powerpc cab data register r/w pwrpc_cab_cntl x ? 7800 0010 ? powerpc cab control register r/w pwrpc_cab_status x ? 7800 0018 ? powerpc cab status register r/w host_cab_addr x ? 7800 8000 ? pci host cab address register r/w host_cab_data x ? 7800 8008 ? pci host cab data register r/w host_cab_cntl x ? 7800 8010 ? pcihostcabcontrolregister r/w host_cab_status x ? 7800 8018 ? pci host cab status register r/w unassigned addresses in the range x ? 7800 0000 ? -x ? 7800 ffff ? are reserved mailbox and dram interface macro pci_interr_status x ? 7801 0000 ? pci interrupt status register r pci_interr_ena x ? 7801 0008 ? pci interrupt enable register r/w p2h_msg_resource x ? 7801 0010 ? powerpc to pci host resource register r&rs/w p2h_msg_addr x ? 7801 0018 ? powerpc to pci host message address register r/w p2h_doorbell x ? 7801 0020 ? powerpc to pci host doorbell register (powerpc access) r/sum x ? 7801 0028 ? powerpc to pci host doorbell register (pci host access) r/rum h2p_msg_addr x ? 7801 0050 ? pci host to powerpc message address register (reset status) r&rs x ? 7801 0060 ? pci host to powerpc message address register r/w h2p_doorbell x ? 7801 0030 ? pci host to powerpc doorbell register (pci host access) r/sum x ? 7801 0038 ? pci host to powerpc doorbell register (powerpc access) r/rum e2p_msg_resource x ? 7801 0040 ? epc to powerpc message resource register r/w e2p_msg_addr x ? 7801 0048 ? epc to powerpc message address register r e2p_doorbell x ? 7801 0058 ? epc to powerpc doorbell register (powerpc access) r/rum p2e_msg_addr x ? 7801 0068 ? powerpc to epc message address register r/w p2e_doorbell x ? 7801 0070 ? powerpc to epc doorbell register (powerpc access) r/sum e2h_msg_resource x ? 7801 0080 ? epc to pci host message resource register r/w e2h_msg_addr x ? 7801 0088 ? epc to pci host message address register r e2h_doorbell x ? 7801 0098 ? epc to pci host doorbell register (pci host access) r/rum h2e_msg_addr x ? 7801 00a8 ? pci host to epc message address register r/w msg_status x ? 7801 00a0? message status register r h2e_doorbell x ? 7801 00b0 ? pci host to epc doorbell register (pci host access) r/sum sear x'7801 00b8' slave error address register r IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 279 of 444 sesr x'7801 00c0' slave error status register r parity_error_cntr x'7801 00c8' parity error counter register r pwrpc_inst_store x ? 0000 0000 ? - x ? 07ff ffff ? powerpc instruction dram r/w unassigned addresses in the range x ? 7801 0000 ? -x?7801ffff ? are reserved symbolic address plb address description access IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 280 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.6 cab address map some components of the embedded powerpc are also accessible via the np4gs3?s cab interface. these components are accessed using cab addresses as shown in the cab address map. symbolic address cab address description access mailbox and dram interface macro boot_redir_inst x ? 3800 0110? - x ? 3800 0117? boot redirection instruction registers for instruction addresses x ? ffff ffe0? - x ? ffff fffc? r/w e2p_msg_resource x?3801 0010 ? epc to powerpc message resource register r&rs e2p_msg_addr x?3801 0020? epc to powerpc message address register r/w e2p_doorbell x?3801 0040? epc to powerpc doorbell register (powerpc access) r/sum p2e_msg_addr x?3801 0080? powerpc to epc message address register r x ? 3802 0010? powerpc to epc message address register r&rs p2e_doorbell x?3801 0100? powerpc to epc doorbell register (powerpc access) r/rum e2h_msg_resource x?3801 0200? epc to pci host message resource register r&rs e2h_msg_addr x?3801 0400? epc to pci host message address register r/w e2h_doorbell x?3801 0800? epc to pci host doorbell register (pci host access) r/sum h2e_msg_addr x?3801 1000? pci host to epc message address register r x ? 3802 0020? pci host to epc message address register r&rs h2e_doorbell x?3801 2000? pci host to epc doorbell register (pci host access) r/rum msg_status x ? 3801 4000? message status register r IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 281 of 444 10.7 cab interface macro the cab interface macro provides duplicate facilities to support independent cab addressing by the pci host processor and the embedded powerpc. exclusive access to these facilities, if required, is enforced through software discipline. the pci host processor can access the np4gs3?s cab interface through the following mechanism: after pci configuration, one or more ranges of pci addresses are mapped to plb addresses. accessing these pci addresses also accesses powerpc plb resources which include the following cab interface registers: cab address register is set to the value of the cab address to be read or written. cab control register is written with parameters that control the behavior for cab access. cab data register, when accessed, initiates a cab access and determines its type (read or write). status register is read to determine whether the cab interface is waiting for a response (busy), whether the cab is locked by the user and, for polled access, whether read data is ready (rd_rdy). the cab control register (w/p ) controls the two modes of cab access: wait access, w/p = ?1?, causes the cab interface macro to insert wait states on the plb until the cab access is complete. software need not read the cab status register to determine completion. polled access, w/p = ?0?, requires software to read the cab status register to determine when a read or write access is complete (rd_rdy = ?0? and busy = ?0?, respectively) before initiating another cab transac- tion. a subsequent read of the cab data register initiates a cab read access from the cab address con- tained in the cab address register (busy = ?1?). the data returned as a result of this read of the cab_data register is discarded. software must then poll the cab status register until the cab access is complete (busy = ?0?). the cab status register indicates that the access is complete and data is waiting in the cab data register (busy = ?0? and rd_rdy = ?1?). a final read of the cab data returns the data IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 282 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 figure 72: polled access flow diagram n busy = 0 y read cab_status start read cab_status n busy = 0 y read cab_data and discard results read cab_data and discard results n y rd_rdy = 0 cab read or write w r write cab_data with data value finish r w read cab_data cab read or write IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 283 of 444 10.7.1 powerpc cab address (pwrpc_cab_addr) register the powerpc cab address register is accessible from the plb and supplies a cab address value for pow- erpc access to np4gs3 structures via the cab interface. access type read/write base address (plb) x?7800 0000? pwrpc_cab_addr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description pwrpc_cab_addr 0:31 x?0000 0000? cabaddressvalueforpowerpcaccesstonp4gs3structuresviathe cab interface. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 284 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.7.2 powerpc cab data (pwrpc_cab_data) register the powerpc cab data register is accessible from the plb and contains the value of cab data written or read when the powerpc accesses np4gs3 structures via the cab interface. writing to the pwrpc_cab_data register has the side effect of initiating a write access on the cab. the data value written to the pwrpc_cab_data register is written to the cab address contained in the pwrpc_cab_addr register. when the pwrpc_cab_cntl register has been configured with its w/p bit set to ?1? or if its w/p bit is set to ?0? and the rd_rdy bit of the pwrpc_cab_status register is set to ?0?, a read of the pwrpc_cab_data register has the side effect of initiating a corresponding read access on the cab. at the end of the cab read access, the data value indicated by the pwrpc_cab_addr register is stored in the pwrpc_cab_data register and the rd_rdy bit of the pwrpc_cab_status register is set to '1. when the w/p bit set to ?1?, the data value is also returned to the plb. otherwise, a subsequent read access of the pwrpc_cab_data register is required to retrieve the data value. access type read/write base address (plb) x?7800 0008? pwrpc_cab_data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description pwrpc_cab_data 0:31 x?0000 0000? cab data written or read when the powerpc accesses np4gs3 struc- tures via the cab interface. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 285 of 444 10.7.3 powerpc cab control (pwrpc_cab_cntl) register the powerpc cab control register is accessible from the plb and controls the cab access protocol used by the powerpc. the bit in this register indicates whether the wait or polled protocol is used when the powerpc accesses cab connected structures within the np4gs3. access type read/write base address (plb) x?7800 0010? reserved w/p 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description reserved 0:30 reserved w/p 31 0 wait or polled access control value 0 powerpc polls the pwrpc_cab_status register to determine when access is complete 1 cab interface macro inserts wait states on the plb until the cab access is complete IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 286 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.7.4 powerpc cab status (pwrpc_cab_status) register the powerpc cab status register is accessible from the plb and monitors the status of powerpc cab accesses. bits within this register indicate the status of powerpc accesses of cab connected structures within the np4gs3. access type read/write base address (plb) x?7800 0018? reserved rd_rdy busy 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description reserved 0:29 reserved rd_rdy 30 0 read data ready indicator (used for polled access mode w/p = ?0? only). 0 no data in cab data register, if busy = ?0?, a new cab access can begin 1 data from a cab read access is waiting in the cab data register busy 31 0 busy indicator value. 0 cab access is not pending. set when the access is complete. 1 cab access is pending. set when an access command (read or write) is initiated. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 287 of 444 10.7.5 pci host cab address (host_cab_addr) register the pci host cab address register is accessible from the plb and supplies a cab address value for pci host access to np4gs3 structures via the cab interface. access type read/write base address (plb) x?7800 8000? host_cab_addr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description host_cab_addr 0:31 x?0000 0000? cabaddressvalueforpcihostaccesstonp4gs3structuresviathe cab interface. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 288 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.7.6 pci host cab data (host_cab_data) register the pci host cab data register is accessible from the plb and contains the value of cab data written or read when the pci host accesses np4gs3 structures via the cab interface. writing to the host_cab_data register has the side effect of initiating a write access on the cab. the data value written to the host_cab_data register is written to the cab address contained in the host_cab_addr register. when the host_cab_cntl register has been configured with its w/p bit set to ?1? or if its w/p bit is set to ?0? and the rd_rdy bit of the host_cab_status register is set to ?0?, a read of the host_cab_data register has the side effect of initiating a corresponding read access on the cab. at the end of the cab read access, the data value indicated by the host_cab_addr register is stored in the host_cab_data register and the rd_rdy bit of the host_cab_status register is set to '1. when the w/p bit set to ?1?, the data value is also returned to the plb. otherwise, a subsequent read access of the host_cab_data register is required to retrieve the data value. access type read/write base address (plb) x?7800 8008? host_cab_data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description host_cab_data 0:31 x?0000 0000? cab data written or read when the pci host accesses np4gs3 struc- tures via the cab interface. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 289 of 444 10.7.7 pci host cab control (host_cab_cntl) register the pci host control register is accessible from the plb and controls the cab access protocol used by the pci host. the bit in this register indicates whether the wait or polled protocol is used when the pci host accesses cab connected structures within the np4gs3. reserved w/p 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 access type read/write base address (plb) x?7800 8010? field name bit(s) reset description reserved 0:30 reserved w/p 31 0 wait or polled access control value 0 pci host polls the host_cab_status register to determine when access is complete 1 cab interface macro inserts wait states on the plb until the cab access is complete IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 290 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.7.8 pci host cab status (host_cab_status) register the pci host cab status register is accessible from the plb and monitors the status of pci host cab accesses. bits within this register indicate the status of pci host accesses of cab connected structures within the np4gs3. access type read/write base address (plb) x?7800 8018? reserved rd_rdy busy 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description reserved 0:29 reserved rd_rdy 30 0 read data ready indicator (used for polled access mode w/p = ?0? only). 0 no data in cab data register, if busy = ?0?, a new cab access can begin 1 data from a cab read access is waiting in the cab data register busy 31 0 busy indicator value. 0 cab access is not pending. set when the access is complete. 1 cab access is pending. set when an access command (read or write) is initiated. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 291 of 444 10.8 mailbox communications and dram interface macro the mailbox and dram interface macro consists of two major portions. the first portion is a set of facilities for constructing and signalling messages between the various processors. a set of message resource regis- ters allocates buffers for message construction, a set of message address registers accomplishes message signalling, and a set of doorbell registers accomplishes other inter-processor signalling. the second portion is hardware that interfaces the np4gs3?s dram controller to the plb. the dram interface maps a range of plb addresses into dram addresses. dram connected via this interface stores powerpc instructions, mes- sage data, and other data associated with the powerpc. the mailbox and dram interface macro also provides redirection of boot code. this function is used in sys- tem implementations in which the np4gs3 does not boot from pci memory. in these cases, hardware decodes the first powerpc instruction fetch and supplies up to eight instructions from registers internal to the mailbox and dram interface. these registers are accessible via the cab and are loaded by software prior to releasing the powerpc?s reset (pwrpc_reset). code stored in these registers redirects execution to loca- tions in the dram. 10.8.1 mailbox communications between pci host and powerpc communication between the pci host and the powerpc is accomplished through pci host to powerpc (h2p) and powerpc to pci host (p2h) interrupts. the p2h interrupt is implemented by asserting the np4gs3?s inta# signal output. pci interrupts are level sensitive and are asynchronous with the pci_clk sig- nal. the existing pci macro?s inta# signal is supplemented with other interrupt generation outside of the pci macro. using the pci macro, the powerpc can send an interrupt to the pci host by writing to the pci/plb macro?s pci interrupt control/status register. this interrupt signal is recorded in the pci interrupt status reg- ister. doorbell and message register operations are additional sources of pci interrupts. the pci macro can interrupt the powerpc by setting bit 13 of the pci macro?s bridge options 2 register. this interrupt signal is applied to the powerpc?s universal interrupt controller (uic). communications between the pci host and the powerpc use message buffers in pci address space. soft- ware running in the pci host manages these buffers. for communications from the powerpc to the pci host, the starting address of empty message buffers are stored in the p2h message resource (p2h_msg_resource) register. this register is accompanied by a p2h_bufr_valid status flag, located in the msg_status register, that indicates whether or not the p2h_msg_resource register contains a valid buffer address. the pci host writes the p2h_msg_resource register with the pci address of an empty message buffer and the valid indicator flag is set. the powerpc reads the flag value when a message buffer is required and then reads the valid message buffer address value from the p2h_msg_resource register. reading the p2h_msg_resource register resets the valid indicator bit. by polling this indicator bit, the pci host knows when to replenish the p2h_msg_resource register with a new buffer address value. having acquired a message buffer, the powerpc composes a message in the buffer and writes the buffer?s starting address value into the p2h_msg_addr register. this write also sets the pci_interr_status register?s p2h_msg bit. a pci interrupt is generated when the corresponding bit of the pci_interr_ena register is set. the pci host reads the p2h_msg_addr register to find and process the message. the read clears the inter- rupt condition. for communication from the pci host to the powerpc, messages are composed in buffers in the pci address space. each message is then signalled to the powerpc by writing its starting pci address value into the h2p_msg_addr register. writing this register sets the h2p_msg_interr to the powerpc?s uic and sets the h2p_msg_busy bit of the msg_status register. an interrupt is generated when enabled by the uic. the powerpc reads the h2p_msg_addr register at one address location to find and process the message and, IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 292 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 due to the read, the interrupt condition is cleared. a subsequent read of the h2p_msg addr register at another address location will reset the h2p_msg_busy bit of the msg_status register. this second read sig- nals the pci host that the powerpc has finished processing the data buffer, allowing it to be reused. the p2h_msg_addr register is written by the powerpc and read by the pci host processor. whenever the powerpc writes the p2h_msg_addr register, a bit in the pci interrupt status register is set to ?1? and is inde- pendent of the value written. the pci interrupt status register indicates the source of the pci interrupt. the pci interrupt status register bit is reset to '0' when the pci host processor reads the p2h_msg_addr regis- ter. software discipline controls the setting of the interrupt by the powerpc and the resetting of the interrupt by the pci host (only the powerpc writes this register and only the pci host reads this register). the doorbell register is written and read by either the powerpc or the pcihost processor. the value recorded in this register depends upon the data value to be written, the current contents of the register, and whether the powerpc or the pci host processor is writing the register. when written by the powerpc, each bit of the register?s current contents is compared with the corresponding data bit to be written. if the value of the data bit is ?1?, then the corresponding doorbell register is set to ?1?. otherwise it remains unchanged (?0? or ?1?). this effect is referred to as set-under-mask (sum). when written by the pci host processor, each bit of the register?s current contents is compared with the cor- responding data bit to be written. if the value of the data bit is ?1?, then the corresponding doorbell register bit is reset to ?0?. otherwise, it remains unchanged (?0? or ?1?). this effect is referred to as reset-under-mask (rum). if one or more of the bits in the doorbell register are ?1?, then a signal is generated and stored in the pci interrupt status register. any of the signals recorded as ?1? in the pci interrupt status register activates the inta# signal if the corre- sponding condition is enabled in the np4gs3?s pci interrupt enable register. the pci host processor reads the pci interrupt status register to determine the interrupt source. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 293 of 444 10.8.2 pci interrupt status (pci_interr_status) register the pci interrupt status register is accessible from the plb and records the source of the pci interrupts gen- erated by the np4gs3. this register?s bits are set by hardware and are read by pci host software. when the interrupt source is cleared, the corresponding bit of the pci_interr_status register is also cleared. access type read only base address (plb) x?7801 0000? reserved pci_macro reserved e2h_db e2h_msg p2h_db p2h_msg 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description reserved 0:23 reserved pci_macro 24 0 pci interrupt from macro indicator. 0 interrupt absent 1 interrupt present reserved 25:27 reserved e2h_db 28 0 epc to pci host doorbell indicator. 0 pci interrupt from e2h_doorbell register absent 1 pci interrupt from e2h_doorbell register present e2h_msg 29 0 epc to pci host message indicator. 0 pci interrupt from e2h_message register absent 1 pci interrupt from e2h_message register present p2h_db 30 0 powerpc to pci host doorbell indicator. 0 pci interrupt from p2h_doorbell register absent 1 pci interrupt from p2h_doorbell register present p2h_msg 31 0 powerpc to pci host message indicator. 0 pci interrupt from p2h_message register absent 1 pci interrupt from p2h_message register present IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 294 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.8.3 pci interrupt enable (pci_interr_ena) register the pci interrupt enable register is accessible from the plb and enables pci interrupts from sources within the np4gs3. access type read/write base address (plb) x?7801 0008? reserved pci_macro reserved e2h_db e2h_msg p2h_db p2h_msg 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description reserved 0:23 reserved pci_macro 24 0 pci macro interrupt - controls the assertion of a pci interrupt from the pci macro. 0 interrupt disabled 1 interrupt enabled reserved 25:27 reserved e2h_db 28 0 epc to pci host doorbell interrupt - controls the assertion of a pci inter- rupt from the e2h_doorbell register. 0 interrupt disabled 1 interrupt enabled e2h_msg 29 0 epc to pci host message interrupt - controls the assertion of a pci inter- rupt from the e2h_message register. 0 interrupt disabled 1 interrupt enabled p2h_db 30 0 powerpc to pci host doorbell interrupt - controls the assertion of a pci interrupt from the p2h_doorbell register. 0 interrupt disabled 1 interrupt enabled p2h_msg 31 0 powerpc to pci host message interrupt - controls the assertion of a pci interrupt from the p2h_message register. 0 interrupt disabled 1 interrupt enabled IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 295 of 444 10.8.4 powerpc to pci host message resource (p2h_msg_resource) register the powerpc to pci host message resource register is accessible from the plb. the powerpc uses this register to obtain message buffers in pci address space for messages the powerpc sends to the pci host processor. the pci host writes the starting pci address value of a message buffer into the p2h_msg_resource register. writing to this register sets the p2h_bufr_valid flag and reading the p2h_msg_resource register clears this flag. access type read/write base address (plb) x?7801 0010? p2h_msg_resource 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description p2h_msg_resource 0:31 x?0000 0000? powerpctopcihostmessageresourcevalue,writtenwiththepci starting address of a message buffer. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 296 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.8.5 powerpc to host message address (p2h_msg_addr) register the powerpc to pci host message address register is accessible from the plb and is used by the powerpc to send messages to the pci host processor. the value written into this register is the pci address at which the message begins. writing to this register sets the p2h_msg bit of the pci_interr_status register. when the corresponding bit of the pci_interr_ena register is set to ?1?, the inta# signal of the pci bus is activated. the p2h_msg bit of the pci_interr_status register is reset when the interrupt service routine reads the p2h_msg_addr register. access type read/write base address (plb) x?7801 0018? p2h_msg_addr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description p2h_msg_addr 0:31 x?0000 0000? powerpc to pci host message address value, indicates the pci starting address of a message. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 297 of 444 10.8.6 powerpc to host doorbell (p2h_doorbell) register the powerpc to pci host doorbell register is accessible from the plb and is used by the powerpc to signal interrupts to the pci host processor. the powerpc has read and sum write access to this register. the data contains the mask used to access this register. when bits of this register are set to ?1? and the corresponding bit of the pci_interr_ena register is set to ?1?, the inta# signal of the pci bus is activated. the pci host pro- cessor reads this register to determine which of the doorbells have been activated. the pci host processor has read and rum write access to this register using a different plb address value. access type power pc x?7801 0020? host x?7801 0028? base address (plb) power pc read/set-under-mask host read/reset-under-mask p2h_msg_doorbell 31 p2h_msg_doorbell 30 p2h_msg_doorbell 29 p2h_msg_doorbell 28 p2h_msg_doorbell 27 p2h_msg_doorbell 26 p2h_msg_doorbell 25 p2h_msg_doorbell 24 p2h_msg_doorbell 23 p2h_msg_doorbell 22 p2h_msg_doorbell 21 p2h_msg_doorbell 20 p2h_msg_doorbell 19 p2h_msg_doorbell 18 p2h_msg_doorbell 17 p2h_msg_doorbell 16 p2h_msg_doorbell 15 p2h_msg_doorbell 14 p2h_msg_doorbell 13 p2h_msg_doorbell 12 p2h_msg_doorbell 11 p2h_msg_doorbell 10 p2h_msg_doorbell 9 p2h_msg_doorbell 8 p2h_msg_doorbell 7 p2h_msg_doorbell 6 p2h_msg_doorbell 5 p2h_msg_doorbell 4 p2h_msg_doorbell 3 p2h_msg_doorbell 2 p2h_msg_doorbell 1 p2h_msg_doorbell 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description p2h_msg_doorbell 31 0 0 powerpc to pci host doorbell - indicates which of the 32 possible door- bells have been activated. 0 not activated 1 activated p2h_msg_doorbell 30:1 1:30 0 for all p2h_msg_doorbell 0 31 0 IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 298 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.8.7 host to powerpc message address (h2p_msg_addr) register the pci host to powerpc message address register is accessible from the plb and is used by the pci host to send messages to the powerpc processor. the value written into this register is a message?s pci starting address. writing to this register activates the h2p_msg_interr input to the powerpc's uic. when this inter- rupt is enabled, an interrupt to the powerpc is generated. reading this register resets the h2p_msg_interr input to the uic. reading this register at an alternate plb address resets the msg_status register?s h2p_msg_busy bit. access type 1 read and reset status 2 read/write base address (plb) 1 x?7801 0050? 2 x?7801 0060? h2p_msg_addr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description h2p_msg_addr 0:31 x?0000 0000? the value is a message?s pci starting address. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 299 of 444 10.8.8 host to powerpc doorbell (h2p_doorbell) register the pci host to powerpc doorbell (h2p_doorbell) register is accessible from the plb and is used by the pci host processor to signal interrupts to the powerpc. the pci host processor has read and sum write access to this register. the data contains the mask used to access this register. when any of this register?s bits are set to ?1?, an interrupt signal of the powerpc?s uic is activated. the powerpc reads this register to determine which of the doorbells have been activated. the powerpc has read and rum write access to this register using a different plb address value. access type host read/set-under-mask write powerpc read/reset-under-mask write base address (plb) host x?7801 0030? powerpc x?7801 0038? h2p_doorbells h2p_msg_doorbell 31 h2p_msg_doorbell 30 h2p_msg_doorbell 29 h2p_msg_doorbell 28 h2p_msg_doorbell 27 h2p_msg_doorbell 26 h2p_msg_doorbell 25 h2p_msg_doorbell 24 h2p_msg_doorbell 23 h2p_msg_doorbell 22 h2p_msg_doorbell 21 h2p_msg_doorbell 20 h2p_msg_doorbell 19 h2p_msg_doorbell 18 h2p_msg_doorbell 17 h2p_msg_doorbell 16 h2p_msg_doorbell 15 h2p_msg_doorbell 14 h2p_msg_doorbell 13 h2p_msg_doorbell 12 h2p_msg_doorbell 11 h2p_msg_doorbell 10 h2p_msg_doorbell 9 h2p_msg_doorbell 8 h2p_msg_doorbell 7 h2p_msg_doorbell 6 h2p_msg_doorbell 5 h2p_msg_doorbell 4 h2p_msg_doorbell 3 h2p_msg_doorbell 2 h2p_msg_doorbell 1 h2p_msg_doorbell 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name plb bit(s) reset description h2p_msg_doorbell 31 0 0 pci host to powerpc doorbell - indicates which of the 32 possible door- bells have been activated. 0 not activated 1 activated h2p_msg_doorbell 30:1 1:30 0 for all h2p_msg_doorbell 0 31 0 IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 300 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.8.9 mailbox communications between powerpc and epc communication between the powerpc and the epc is accomplished by writing message data into buffers in the powerpc?s dram and signalling the destination processor with an interrupt. the powerpc software manages message data buffers for powerpc to epc (p2e) messages and epc to powerpc (e2p) mes- sages. message data buffers are allocated to the epc by writing the buffers? starting address into the e2p_msg_resource register. writing to this register sets the e2p_bufr_valid flag in the msg_status register. this flag indicates to the epc that the buffer is valid and can be used by the epc. the epc reads the e2p_bufr_valid value when a message buffer is required. the epc then reads the e2p_msg_resource reg- ister via the cab interface to obtain the address of the message buffer and the e2p_bufr_valid indicator bit is reset. by polling this indicator bit, the powerpc knows when to replenish the e2p_msg_resource register with a new buffer address value. having acquired a message data buffer, the epc composes a message in the buffer and writes the buffer?s starting address value into the e2p_msg_addr register. writing to this regis- ter generates an interrupt signal to the powerpc?s uic. the powerpc reads this register to find and process the message and, due to the read, the interrupt condition is cleared. there is no need for a p2e_msg_resource register because the powerpc software manages the message data buffers the powerpc composes a message in one of the data buffers and writes the starting address of the buffer into the p2e_msg_addr register. writing to this register produces an interrupt to the epc and sets the p2e_msg_busy bit of the msg_status register. as long as this flag is set, the epc is processing the mes- sage buffer. the epc reads the p2e_msg_addr register to locate the buffer in the powerpc?s dram. the epc resets the p2e_msg_busy bit by reading the p2e_msg_address register at an alternate cab address when message processing is complete. the powerpc will poll the busy flag to determine when the buffer can be reused. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 301 of 444 10.8.10 epc to powerpc resource (e2p_msg_resource) register the powerpc accesses the epc to powerpc message resource register from the plb while the epc accesses this register from its cab interface. the epc uses this register to obtain message buffers in the powerpc?s dram address space for messages it sends to the powerpc processor. the powerpc writes the starting dram address value of a message buffer. writing to this register sets the e2p_bufr_valid flag in the msg_status register. reading the e2p_msg_resource register from the cab resets this flag. cab view plb view cab view plb view access type cab read plb read/write base address cab x?3801 0010? plb x?7801 0040? e2p_msg_resource 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e2p_msg_resource 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description e2p_msg_resource 31:0 x?0000 0000? epc to powerpc message resource - written with the powerpc?s dram starting address of a message buffer. field name bit(s) reset description e2p_msg_resource 0:31 x?0000 0000? epc to powerpc message resource - written with the powerpc?s dram starting address of a message buffer. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 302 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.8.11 epc to powerpc message address (e2p_msg_addr) register the powerpc accesses the epc to powerpc message address register from the plb while the epc accesses this register from its cab interface. the epc uses this register to send messages to the powerpc processor. the value written into this register is the powerpc?s dram address at which the message begins. writing to this register sets e2p_msg_interr input to the powerpc?s uic. when the uic is configured to enable this input, an interrupt signal to the powerpc is activated. reading the e2p_msg_addr register via the plb address resets the e2p_msg_interr input to the powerpc?s uic. cab view plb view cab view plb view access type cab read/write plb read base address cab x?3801 0020? plb x?7801 0048? e2p_msg_addr 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e2p_msg_addr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description e2p_msg_addr 0:31 x?0000 0000? epc to powerpc message address - indicates the pci starting address of a message. field name bit(s) reset description e2p_msg_addr 0:31 x?0000 0000? epc to powerpc message address - indicates the pci starting address of a message. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 303 of 444 10.8.12 epc to powerpc doorbell (e2p_doorbell) register the powerpc accesses the epc to powerpc doorbell register from the plb while the epc accesses this register from the cab interface. the epc uses this register to signal interrupts to the powerpc. the epc has read and sum write access to this register using a cab address value. the data contains the mask used to access this register. when any of this register?s bits are set to ?1? an interrupt signal to the powerpc?s uic is activated. the powerpc reads this register to determine which of the doorbells have been activated.the powerpc has read and rum write access to this register using a plb address value. cab view plb view cab view access type cab read/set-under-mask write plb read/reset-under-mask write base address cab x?3801 0040? plb x?7801 0058? e2p_doorbells e2p_msg_doorbell 31 e2p_msg_doorbell 30 e2p_msg_doorbell 29 e2p_msg_doorbell 28 e2p_msg_doorbell 27 e2p_msg_doorbell 26 e2p_msg_doorbell 25 e2p_msg_doorbell 24 e2p_msg_doorbell 23 e2p_msg_doorbell 22 e2p_msg_doorbell 21 e2p_msg_doorbell 20 e2p_msg_doorbell 19 e2p_msg_doorbell 18 e2p_msg_doorbell 17 e2p_msg_doorbell 16 e2p_msg_doorbell 15 e2p_msg_doorbell 14 e2p_msg_doorbell 13 e2p_msg_doorbell 12 e2p_msg_doorbell 11 e2p_msg_doorbell 10 e2p_msg_doorbell 9 e2p_msg_doorbell 8 e2p_msg_doorbell 7 e2p_msg_doorbell 6 e2p_msg_doorbell 5 e2p_msg_doorbell 4 e2p_msg_doorbell 3 e2p_msg_doorbell 2 e2p_msg_doorbell 1 e2p_msg_doorbell 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e2p_doorbells e2p_msg_doorbell 31 e2p_msg_doorbell 30 e2p_msg_doorbell 29 e2p_msg_doorbell 28 e2p_msg_doorbell 27 e2p_msg_doorbell 26 e2p_msg_doorbell 25 e2p_msg_doorbell 24 e2p_msg_doorbell 23 e2p_msg_doorbell 22 e2p_msg_doorbell 21 e2p_msg_doorbell 20 e2p_msg_doorbell 19 e2p_msg_doorbell 18 e2p_msg_doorbell 17 e2p_msg_doorbell 16 e2p_msg_doorbell 15 e2p_msg_doorbell 14 e2p_msg_doorbell 13 e2p_msg_doorbell 12 e2p_msg_doorbell 11 e2p_msg_doorbell 10 e2p_msg_doorbell 9 e2p_msg_doorbell 8 e2p_msg_doorbell 7 e2p_msg_doorbell 6 e2p_msg_doorbell 5 e2p_msg_doorbell 4 e2p_msg_doorbell 3 e2p_msg_doorbell 2 e2p_msg_doorbell 1 e2p_msg_doorbell 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description e2p_msg_doorbell 31 31 0 epc to powerpc doorbell - indicates which of the 32 possible doorbells is activated. 0 not activated 1 activated e2p_msg_doorbell 30:1 30:1 0 for all e2p_msg_doorbell 0 0 0 IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 304 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 plb view field name bit(s) reset description e2p_msg_doorbell 31 0 0 epc to powerpc doorbell - indicates which of the 32 possible doorbells is activated. 0 not activated 1 activated e2p_msg_doorbell 30:1 1:30 0 for all e2p_msg_doorbell 0 31 0 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 305 of 444 10.8.13 epc interrupt vector register the epc contains an interrupt vector 2 register which is accessible from the cab interface. this register records the source of epc interrupts generated by the np4gs3. this register?s bits are set by hardware and are read by epc software to determine the source of interrupts. (for more information on interrupt vector registers, see section 3 of the ibm network processor hardware reference manual.) 10.8.14 epc interrupt mask register the epc contains a interrupt mask 2 register which is accessible from the cab interface. this register enables epc interrupts from sources within the np4gs3. (for more information on interrupt mask registers, see section 3 of the ibm network processor hardware reference manual.) IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 306 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.8.15 powerpc to epc message address (p2e_msg_addr) register the powerpc accesses the powerpc to epc message address register from the plb while the epc accesses this register from the cab interface. this register is used by the powerpc to send messages to the epc. the value written into this register is the powerpc?s dram address at which the message begins. writ- ing to this register sets the p2e_msg_interr signal to the epc and the p2e_msg_busy bit of the msg_status register. reading the p2e_msg_addr register from the cab will reset the p2e_msg_interr signal to the epc. reading the p2e_msg_addr from an alternate cab address will reset the p2e_msg_busy bit of the msg_status register. cab view plb view cab view plb view access type cab 1 read cab 2 read and reset status plb read/write base address cab 1 x?3801 0080? cab 2 x?3802 0010? plb x?7801 0068? p2e_msg_addr 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p2e_msg_addr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description p2e_msg_addr 31:0 x?0000 0000? powerpc to epc message address - indicates a message?s powerpc dram starting address. field name bit(s) reset description p2e_msg_addr 0:31 x?0000 0000? powerpc to epc message address - indicates a message?s powerpc dram starting address. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 307 of 444 10.8.16 powerpc to epc doorbell (p2e_doorbell) register the powerpc accesses the powerpc to epc doorbell register from the plb while the epc accesses this register from the cab interface. the powerpc uses this register to signal interrupts to the epc. the pow- erpc has read and sum write access to this register. the data contains the mask used to access this regis- ter. when any of this register?s bits are set to ?1?, an interrupt signal of the epc is activated. this register is read by the epc to determine which of the doorbells have been activated.the epc has read and rum write access to this register using a cab address value. cab view plb view cab view access type cab read/reset-under-mask write plb read/set-under-mask write base address cab x?3801 0100? plb x?7801 0070? p2e_doorbells p2e_msg_doorbell 31 p2e_msg_doorbell 30 p2e_msg_doorbell 29 p2e_msg_doorbell 28 p2e_msg_doorbell 27 p2e_msg_doorbell 26 p2e_msg_doorbell 25 p2e_msg_doorbell 24 p2e_msg_doorbell 23 p2e_msg_doorbell 22 p2e_msg_doorbell 21 p2e_msg_doorbell 20 p2e_msg_doorbell 19 p2e_msg_doorbell 18 p2e_msg_doorbell 17 p2e_msg_doorbell 16 p2e_msg_doorbell 15 p2e_msg_doorbell 14 p2e_msg_doorbell 13 p2e_msg_doorbell 12 p2e_msg_doorbell 11 p2e_msg_doorbell 10 p2e_msg_doorbell 9 p2e_msg_doorbell 8 p2e_msg_doorbell 7 p2e_msg_doorbell 6 p2e_msg_doorbell 5 p2e_msg_doorbell 4 p2e_msg_doorbell 3 p2e_msg_doorbell 2 p2e_msg_doorbell 1 p2e_msg_doorbell 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p2e_doorbells p2e_msg_doorbell 31 p2e_msg_doorbell 30 p2e_msg_doorbell 29 p2e_msg_doorbell 28 p2e_msg_doorbell 27 p2e_msg_doorbell 26 p2e_msg_doorbell 25 p2e_msg_doorbell 24 p2e_msg_doorbell 23 p2e_msg_doorbell 22 p2e_msg_doorbell 21 p2e_msg_doorbell 20 p2e_msg_doorbell 19 p2e_msg_doorbell 18 p2e_msg_doorbell 17 p2e_msg_doorbell 16 p2e_msg_doorbell 15 p2e_msg_doorbell 14 p2e_msg_doorbell 13 p2e_msg_doorbell 12 p2e_msg_doorbell 11 p2e_msg_doorbell 10 p2e_msg_doorbell 9 p2e_msg_doorbell 8 p2e_msg_doorbell 7 p2e_msg_doorbell 6 p2e_msg_doorbell 5 p2e_msg_doorbell 4 p2e_msg_doorbell 3 p2e_msg_doorbell 2 p2e_msg_doorbell 1 p2e_msg_doorbell 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description p2e_msg_doorbell 31 31 0 powerpc to epc doorbell - indicates which of the 32 possible doorbells is activated. 0 not activated 1 activated p2e_msg_doorbell 30:1 30:1 0 for all p2e_msg_doorbell 0 0 0 IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 308 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 plb view field name bit(s) reset description p2e_msg_doorbell 31 0 0 powerpc to epc doorbell - indicates which of the 32 possible doorbells is activated. 0 not activated 1 activated p2e_msg_doorbell 30:1 1:30 0 for all p2e_msg_doorbell 0 31 0 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 309 of 444 10.8.17 mailbox communications between pci host and epc communication between the pci host processor and the epc is accomplished by writing message data into buffers in the powerpc?s dram and signalling the destination processor with an interrupt. the pci host pro- cessor software manages message data buffers for pci host processor to epc (h2e) messages and epc to pci host processor (e2h) messages. message data buffers are allocated to the epc by writing the buffers? starting address into the e2h_msg_resource register. writing this register sets the e2h_bufr_valid flag in the msg_status register. this flag indicates to the epc that the buffer is valid and can be used by the epc. the epc reads the e2h_bufr_valid value when a message buffer is required. the epc then reads the e2h_msg_resource reg- ister via the cab interface and the e2p_bufr_valid indicator bit is reset. by polling this indicator bit, the pci host processor knows when to replenish the e2h_msg_resource register with a new buffer address value. having acquired a message data buffer, the epc will compose a message in the buffer and write the buffer?s starting address value into the e2h_msg_addr register. writing to this register generates an interrupt to the pci host processor. the pci host processor reads this register to find and process the message. reading this register clears the interrupt condition. since the pci host processor software manages the message data buffers, there is no need for an h2e_msg_resource register. the pci host processor composes a message in one of the data buffers and writes the starting address of the buffer into the h2e_msg_addr register. writing to this register produces an interrupt input signal to the epc and sets the h2e_msg_busy bit of the msg_status register. as long as this flag is set, the epc is processing the message buffer. the epc reads the h2e_msg_addr register to locate the buffer in the powerpc?s dram and reset the interrupt input signal to the epc. the epc resets the h2e_msg_busy bit by reading the p2e_msg_addr register from an alternate cab address when message processing is complete. the powerpc will poll the h2e_msg_busy bit to determine when the buffer can be reused. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 310 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.8.18 epc to pci host resource (e2h_msg_resource) register the pci host processor accesses the epc to pci host message resource register from the plb while the epc accesses this register from its cab interface. this epc uses this register to obtain message buffers in the powerpc?s dram address space for messages it sends to the pci host processor. the pci host pro- cessor writes the starting dram address value of a message buffer into the e2p_msg_resource register. writing to this register sets the e2h_bufr_valid flag. reading the e2h_msg_resource register from the cab resets this flag. cab view plb view cab view plb view access type cab read plb read/write base address cab x?3801 0200? plb x?7801 0080? e2h_msg_resource 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e2h_msg_resource 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description e2h_msg_resource 31:0 x?0000 0000? epc to pci host message resource - written with the powerpc?s dram starting address of a message buffer. field name bit(s) reset description e2h_msg_resource 0:31 x?0000 0000? epc to pci host message resource - written with the powerpc?s dram starting address of a message buffer. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 311 of 444 10.8.19 epc to pci host message address (e2h_msg_addr) register the pci host processor accesses the epc to pci host message address register from the plb while the epc accesses this register from its cab interface. the epc uses this register to send messages to the pci host processor. the value written into this register is the powerpc?s dram address at which the message begins. writing to this register sets the e2h_msg bit of the pci_interr_status register. when the correspond- ing bit of the pci_interr_ena register is set to ?1?, an interrupt signal to the pci host processor is activated. reading the e2h_msg_addr register from the plb resets the e2h_msg bit of the pci_interr_status register. cab view plb view cab view plb view access type cab read/write plb read base address cab x?3801 0400? plb x?7801 0088? e2h_msg_addr 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e2h_msg_addr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description e2h_msg_addr 31:0 x?0000 0000? epc to pci host message address - indicates the powerpc?s dram starting address of a message. field name bit(s) reset description e2h_msg_addr 0:31 x?0000 0000? epc to pci host message address - indicates the powerpc?s dram starting address of a message. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 312 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.8.20 epc to pci host doorbell (e2h_doorbell) register the pci host processor accesses the epc to pci host doorbell register from the plb while the epc accesses this register from the cab interface. the epc uses this register to signal interrupts to the pci host processor. the epc has read and sum write access to this register using a cab address value. the mask used to access this register is contained in the data. when any of this register?s bits are set to ?1? and the cor- responding bit of the pci_interr_ena register is set to ?1?, an interrupt signal of the pci host processor is acti- vated. this register is read by the pci host processor to determine which of the doorbells have been activated. the pci host processor has read and rum write and read access to this register using a plb address value. cab view plb view cab view access type cab read/set_under_mask write plb read/reset_under_mask write base address cab x?3801 0800? plb x?7801 0098? e2h_doorbells e2h_msg_doorbell 31 e2h_msg_doorbell 30 e2h_msg_doorbell 29 e2h_msg_doorbell 28 e2h_msg_doorbell 27 e2h_msg_doorbell 26 e2h_msg_doorbell 25 e2h_msg_doorbell 24 e2h_msg_doorbell 23 e2h_msg_doorbell 22 e2h_msg_doorbell 21 e2h_msg_doorbell 20 e2h_msg_doorbell 19 e2h_msg_doorbell 18 e2h_msg_doorbell 17 e2h_msg_doorbell 16 e2h_msg_doorbell 15 e2h_msg_doorbell 14 e2h_msg_doorbell 13 e2h_msg_doorbell 12 e2h_msg_doorbell 11 e2h_msg_doorbell 10 e2h_msg_doorbell 9 e2h_msg_doorbell 8 e2h_msg_doorbell 7 e2h_msg_doorbell 6 e2h_msg_doorbell 5 e2h_msg_doorbell 4 e2h_msg_doorbell 3 e2h_msg_doorbell 2 e2h_msg_doorbell 1 e2h_msg_doorbell 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e2h_doorbells e2h_msg_doorbell 31 e2h_msg_doorbell 30 e2h_msg_doorbell 29 e2h_msg_doorbell 28 e2h_msg_doorbell 27 e2h_msg_doorbell 26 e2h_msg_doorbell 25 e2h_msg_doorbell 24 e2h_msg_doorbell 23 e2h_msg_doorbell 22 e2h_msg_doorbell 21 e2h_msg_doorbell 20 e2h_msg_doorbell 19 e2h_msg_doorbell 18 e2h_msg_doorbell 17 e2h_msg_doorbell 16 e2h_msg_doorbell 15 e2h_msg_doorbell 14 e2h_msg_doorbell 13 e2h_msg_doorbell 12 e2h_msg_doorbell 11 e2h_msg_doorbell 10 e2h_msg_doorbell 9 e2h_msg_doorbell 8 e2h_msg_doorbell 7 e2h_msg_doorbell 6 e2h_msg_doorbell 5 e2h_msg_doorbell 4 e2h_msg_doorbell 3 e2h_msg_doorbell 2 e2h_msg_doorbell 1 e2h_msg_doorbell 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description e2h_msg_doorbell 31 31 0 epc to pci host doorbell - indicates which of the 32 possible doorbells is activated. 0 not activated 1 activated e2h_msg_doorbell 30:1 30:1 0 for all e2h_msg_doorbell 0 0 0 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 313 of 444 plb view field name bit(s) reset description e2h_msg_doorbell 31 0 0 epc to pci host doorbell - indicates which of the 32 possible doorbells is activated. 0 not activated 1 activated e2h_msg_doorbell 30:1 1:30 0 for all e2h_msg_doorbell 0 31 0 IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 314 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.8.21 pci host to epc message address (h2e_msg_addr) register the pci host processor accesses the pci host to epc message address register from the plb while the epc accesses this register from the cab interface. the pci host uses this register to send messages to the epc. the value written into this register is the powerpc?s dram address at which the message begins. writ- ing to this register sets the h2e_msg_interr signal to the epc and the h2e_msg_busy bit of the msg_status register. reading the h2e_msg_addr register from the cab will reset the h2e_msg_interr signal to the epc. reading the h2e_msg_addr from an alternate cab will reset the h2e_msg_busy bit of the msg_status reg- ister. cab view plb view cab view plb view access type cab 1 read cab 2 read & reset status plb read/write base address cab 1 x?3801 1000? cab 2 x?3802 0020? plb x?7801 00a8? h2e_msg_addr 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 h2e_msg_addr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description h2e_msg_addr 31:0 x?0000 0000? pci host to epc message address - indicates a message?s powerpc dram starting address. field name bit(s) reset description h2e_msg_addr 0:31 x?0000 0000? pci host to epc message address - indicates a message?s powerpc dram starting address. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 315 of 444 10.8.22 pci host to epc doorbell (h2e_doorbell) register the pci host processor accesses the pci host to epc doorbell register from the plb while the epc accesses this register from the cab interface. the pci host processor uses this register to signal interrupts to the epc. the pci host processor has read and sum write access to this register. the data contains the mask used to access this register. when any of this register?s bits are set to ?1?, an interrupt signal of the epc is activated. this register is read by the epc to determine which of the doorbells have been activated.the epc has read and rum write access to this register using a cab address value. cab view plb view cab view access type cab read/reset_under_mask write plb read/set_under_mask write base address cab x?3801 2000? plb x?7801 00b0? h2e_doorbells h2e_msg_doorbell 31 h2e_msg_doorbell 30 h2e_msg_doorbell 29 h2e_msg_doorbell 28 h2e_msg_doorbell 27 h2e_msg_doorbell 26 h2e_msg_doorbell 25 h2e_msg_doorbell 24 h2e_msg_doorbell 23 h2e_msg_doorbell 22 h2e_msg_doorbell 21 h2e_msg_doorbell 20 h2e_msg_doorbell 19 h2e_msg_doorbell 18 h2e_msg_doorbell 17 h2e_msg_doorbell 16 h2e_msg_doorbell 15 h2e_msg_doorbell 14 h2e_msg_doorbell 13 h2e_msg_doorbell 12 h2e_msg_doorbell 11 h2e_msg_doorbell 10 h2e_msg_doorbell 9 h2e_msg_doorbell 8 h2e_msg_doorbell 7 h2e_msg_doorbell 6 h2e_msg_doorbell 5 h2e_msg_doorbell 4 h2e_msg_doorbell 3 h2e_msg_doorbell 2 h2e_msg_doorbell 1 h2e_msg_doorbell 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 h2e_doorbells h2e_msg_doorbell 31 h2e_msg_doorbell 30 h2e_msg_doorbell 29 h2e_msg_doorbell 28 h2e_msg_doorbell 27 h2e_msg_doorbell 26 h2e_msg_doorbell 25 h2e_msg_doorbell 24 h2e_msg_doorbell 23 h2e_msg_doorbell 22 h2e_msg_doorbell 21 h2e_msg_doorbell 20 h2e_msg_doorbell 19 h2e_msg_doorbell 18 h2e_msg_doorbell 17 h2e_msg_doorbell 16 h2e_msg_doorbell 15 h2e_msg_doorbell 14 h2e_msg_doorbell 13 h2e_msg_doorbell 12 h2e_msg_doorbell 11 h2e_msg_doorbell 10 h2e_msg_doorbell 9 h2e_msg_doorbell 8 h2e_msg_doorbell 7 h2e_msg_doorbell 6 h2e_msg_doorbell 5 h2e_msg_doorbell 4 h2e_msg_doorbell 3 h2e_msg_doorbell 2 h2e_msg_doorbell 1 h2e_msg_doorbell 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit reset description h2e_msg_doorbell 31 31 0 pci host to epc doorbell - indicates which of the 32 possible doorbells have been activated. 0 not activated 1 activated h2e_msg_doorbell 30:1 30:1 0 for all h2e_msg_doorbell 0 0 0 IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 316 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 plb view field name plb bit reset description h2e_msg_doorbell 31 0 0 pci host to epc doorbell - indicates which of the 32 possible doorbells is activated. 0 not activated 1 activated h2e_msg_doorbell 30:1 1:30 0 for all h2e_msg_doorbell 0 31 0 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 317 of 444 10.8.23 message status (msg_status) register the message status register provides status information associated with inter-processor messaging. this read only register is accessible from either the plb or the cab for the purpose of checking status associated with messaging. cab view plb view access type cab read plb read base address cab x?3801 4000? plb x?7801 00a0? reserved p2h_bufr_valid h2p_msg_busy e2p_bufr_valid p2e_msg_busy e2h_bufr_valid h2e_msg_busy 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved p2h_bufr_valid h2p_msg_busy e2p_bufr_valid p2e_msg_busy e2h_bufr_valid h2e_msg_busy 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 318 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 cab view plb view field name cab bit(s) reset description reserved 31:6 reserved p2h_bufr_valid 5 0 powerpc to pci host message buffer valid indicator. 0buffernotvalid 1buffervalid h2p_msg_busy 4 0 pci host to powerpc message busy indicator. 0 not busy processing h2p message 1 busy processing h2p message e2p_bufr_valid 3 0 epc to powerpc message buffer valid indicator. 0buffernotvalid 1buffervalid p2e_msg_busy 2 0 powerpc to epc message busy indicator. 0 not busy processing p2e message 1 busy processing p2e message e2h_bufr_valid 1 0 epc to pci host message buffer valid indicator. 0buffernotvalid 1buffervalid h2e_msg_busy 0 0 pci host to epc message busy indicator. 0 not busy processing h2e message 1 busy processing h2e message field name bit(s) reset description reserved 0:25 reserved p2h_bufr_valid 26 0 powerpc to pci host message buffer valid indicator. 0buffernotvalid 1buffervalid h2p_msg_busy 27 0 pci host to powerpc message busy indicator. 0 not busy processing h2p message 1 busy processing h2p message e2p_bufr_valid 28 0 epc to powerpc message buffer valid indicator. 0buffernotvalid 1buffervalid p2e_msg_busy 29 0 powerpc to epc message busy indicator. 0 not busy processing p2e message 1 busy processing p2e message e2h_bufr_valid 30 0 epc to pci host message buffer valid indicator. 0buffernotvalid 1buffervalid h2e_msg_busy 31 0 pci host to epc message busy indicator. 0 not busy processing h2e message 1 busy processing h2e message IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 319 of 444 10.8.24 slave error address register (sear) the slave error address register records the address value of the last occurrence of a parity error encoun- tered by the dram interface slave unit. access type read base address (plb) x?7801 00b8? error address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description error address 0:31 x?0000 0000? last plb address value that resulted in a parity error when using the dram interface slave unit. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 320 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.8.25 slave error status register (sesr) the slave error status register contains status information that indicates which masters have encountered parity errors in reading from the dram and whether these errors occurred in a byte with an even (perr_byte0) or an odd (perr_byte1) address value. the powerpc subsystem has three plb masters: the instruction cache unit (icu), the data cache unit (dcu), and the pci macro. the contents of this register are reset to x?0000 0000? when read. access type read and reset base address (plb) x?7801 00c0? icu_error_status dcu_error_status pci_error_status reserved perr_byte0 perr_byte1 reserved perr_byte0 perr_byte1 reserved perr_byte0 perr_byte1 reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description reserved 0:5 reserved perr_byte0 6 0 byte 0 parity error indication - whether or not the instruction cache unit plb master encountered a parity error since the register was last read. 0 no parity error encountered 1 parity error encountered perr_byte1 7 0 byte 1 parity error indication- whether or not the instruction cache unit plb master encountered a parity error since the register was last read. 0 no parity error encountered 1 parity error encountered reserved 8:13 reserved perr_byte0 14 0 byte 0 parity error indication - whether or not the data cache unit plb master encountered a parity error since the register was last read. 0 no parity error encountered 1 parity error encountered perr_byte1 15 0 byte 1 parity error indication - whether or not the data cache unit plb master encountered a parity error since the register was last read. 0 no parity error encountered 1 parity error encountered reserved 16:21 reserved perr_byte0 22 0 byte 0 parity error indication - whether or not the pci macro plb master encountered a parity error since the register was last read. 0 no parity error encountered 1 parity error encountered perr_byte1 23 0 byte 1 parity error indication - whether or not the pci macro plb master encountered a parity error since the register was last read. 0 no parity error encountered 1 parity error encountered reserved 24:31 reserved IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 321 of 444 10.8.26 parity error counter (perr_count) register the parity error counter register contains two 16-bit counter values. these counters accumulate the total number of parity errors for even and odd byte addresses since the last time the chip was reset. these counters rollover to zero when their maximum value is reached (65535). access type read base address (plb) x?7801 00c8? byte0_perr_count byte1_perr_count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field name bit(s) reset description byte0_perr_count 0:15 x?0000? count of byte 0 parity errors encountered when reading dram from dram interface slave unit. byte1_perr_count 16:31 x?0000? count of byte 1parity errors encountered when reading dram from dram interface slave unit. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 322 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.9 system start-up and initialization 10.9.1 np4gs3 resets a general reset is performed whenever the np4gs3?s reset input pin is activated. a general reset includes the powerpc core, and the np4gs3 network function reset domains. the powerpc core and the np4gs3 network function reset domains are also controlled by separate configuration registers, powerpc_reset and soft_reset, respectively. each of these registers are accessible via the np4gs3?s cab interface. a general reset sets the powerpc_reset to ?1? (activated), but the soft_reset will be set to ?0? (deactivated). when the general reset is deactivated, the powerpc core remains in reset and the powerpc macros and the np4gs3 network function are in an idle condition with state machines active and control structures un-ini- tialized. the np4gs3 network function will be functional once epc picocode has been loaded and control structures are initialized. the epc is activated by setting the boot_done control bit to ?1?. the powerpc core is activated by clearing the bit of the powerpc_reset register. the powerpc core and the np4gs3 network function domains are separately reset and activated by set- ting and clearing their respective reset registers. setting the control bit in the soft_reset register causes the network function to be momentarily reset while the powerpc is held in reset. the powerpc_reset is also activated whenever the watch dog timer of the powerpc core expires for a second time and watch dog reset enable (wd_reset_ena) is set to ?1?. when enabled, the second expiration of the watch dog timer results in a pulse on the serr# signal of the pci bus. the tcr [wrc] of the powerpc core is set to ?10? to generate a chip reset request on the second expiration of the watch dog timer. the powerpc core can be reset from the riscwatch debugger environment. a core reset performed from riscwatch resets the 405 core, but does not set the powerpc_reset control register. this allows a momen- tary reset of the powerpc core and does not require a release of the powerpc core by clearing the powerpc_reset control register. the powerpc core is also reset and the powerpc_reset control register is set when a chip reset is performed from riscwatch. this resets the powerpc core and holds it in reset until the powerpc_reset register is cleared. table 214: reset domains reset domain applies powerpc core applies only to the 405 processor core and is used to control its start-up during system initialization network function applies to all other functions in the np4gs3 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 323 of 444 10.9.2 systems initialized by external pci host processors system implementations with control function centralized in a pci host processor are initialized primarily by an external pci host processor. these systems do not use the spm interface or its associated flash memory to boot the epc and dasl picocode. the host processor loads code for the powerpc processor and the epc and dasl picoprocessors. the general sequence of the start-up and initialization is as follows: 1. the host processor boots and performs blade level configuration and testing while holding blade sub- systems in reset. 2. the host processor releases each of the blade subsystems? reset signals in sequence. 3. release of the general reset input pin of the np4gs3 activates its state machines. the np4gs3 is in an idle state with un-initialized structures and the 405 core remains in reset. 4. the host system uses the pci configuration protocol to configure internal registers of the pci interface macro. this configuration sets the base address values of the pci target maps. the pci master maps are disabled. 5. the host processor uses the appropriate pci target address values to configure and initialize the np4gs3?s dram controllers via the cab interface. 6. the host processor uses the appropriate pci target address values to load the powerpc code into one of the np4gs3?s drams. this code includes the branch code loaded into the boot_redir_inst registers. 7. the host loads the picocode memories of the epc and dasl. these memories are accessible via the cab interface macro. the addresses of the registers controlling this interface were mapped to pci addresses in step 4. 8. the host processor starts the 405 core by clearing the powerpc_reset configuration register. this regis- ter is accessed via the cab interface. the powerpc starts by fetching the instruction at plb address x?ffff fffc?. this address is decoded by hardware to provide an unconditional branch to instruction space in the powerpc?s dram memory. 9. the host processor uses the cab interface to set the boot_done control bit to start the epc code. this code controls the initialization of the np4gs3 structures in preparation for network traffic. alternatively, this initialization is performed by the host processor via the cab interface. 10. communication ports are configured and enabled by either the host processor or the 405 core. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 324 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.9.3 systems with pci host processors and initialized by powerpc the powerpc primarily controls start-up and initialization sequences of systems of this category. these sys- tems do not use the spm interface or its associated flash memory for booting the epc boot picocode. the powerpc loads code for the powerpc and the epc and dasl picoprocessors. the general sequence of the start-up and initialization is as follows: 1. the host processor boots and performs blade level configuration and testing while holding blade sub- systems in reset. 2. the host processor releases each of the blade subsystems? reset signals in sequence. 3. release of the general reset input pin of the np4gs3 activates its state machines. the np4gs3 is in an idle state with un-initialized structures and the 405 core remains in reset. 4. the host system uses the pci configuration protocol to configure internal registers of the pci interface macro. this configuration sets the base address values of the pci target maps. the pci master maps are disabled except for the pmm0 which maps plb addresses x?fffe 0000? through x?ffff ffff? to the same addresses in pci address space. 5. the host processor starts the 405 core by clearing the powerpc_reset configuration register. this regis- ter is accessed via the cab interface. 6. the 405 core will boot from code residing in the pci address space starting at address x?ffff fffc?. 7. the 405 core processor configures and initializes the np4gs3?s dram controllers via the cab interface. 8. the 405 core processor loads the powerpc code, via the dram interface macro, into one of the np4gs3?s drams. 9. the 405 core processor loads the picocode for the epc and dasl via the cab interface. 10. using the cab interface, the host processor sets the boot_done control bit to start the epc picocode. this picocode will control the initialization of the np4gs3 structures in preparation for network traffic. alternatively, this initialization is performed by the 405 core processor via the cab interface. 11. communication ports are configured and enabled by the 405 core. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec10_eppc.fm.01 09/25/00 embedded powerpc? page 325 of 444 10.9.4 systems without pci host processors and initialized by powerpc the epc initially controls start-up and initialization sequences of systems of this category, but they are prima- rily controlled by the powerpc. these systems use the spm interface and its associated flash memory for booting the epc picocode. the powerpc loads code for the powerpc and the epc and dasl picoproces- sors. the general sequence of the start-up and initialization is as follows: 1. release of the general reset input pin of the np4gs3 activates its state machines. the pci master maps are disabled except for the pmm0 which maps plb addresses x?fffe 0000? through x?ffff ffff? to the same addresses in pci address space. epc boot picocode is loaded from the flash memory via the spm interface hardware. the spm interface hardware sets the boot_done signal to start the epc and the 405 core remains in reset. 2. epc code executes diagnostic and initialization code which includes the initialization of the np4gs3?s dram controllers. 3. the epc starts the 405 core by clearing the powerpc_reset configuration register. this register is accessed via the cab interface. 4. the 405 core will boot from code residing in the pci address space starting at address x?ffff fffc?. 5. the 405 core processor loads the powerpc code via the dram interface macro into one of the np4gs3?s drams. 6. the 405 core processor or the epc loads the picocode for the dasl via the cab interface. 7. communication ports are configured and enabled by the 405 core. IBM32NPR161EPXCAC133 ibm powernp preliminary embedded powerpc? page 326 of 444 np3_dl_sec10_eppc.fm.01 09/25/00 10.9.5 systems without pci interface hardware and initialized by epc the epc controls start-up and initialization sequences of systems of this category. these systems use the spm interface and its associated flash memory for booting the epc picocode. code for the powerpc and the epc are loaded by the spm interface hardware and the epc. code for the powerpc exists in the flash mem- ory or is provided using guided traffic. the general sequence of the start-up and initialization is as follows: 1. release of the general reset input pin of the np4gs3 activates its state machines. epc picocode is loaded from the flash memory via the spm interface hardware. the boot_done signal is set by the spm interface hardware to start the epc. the 405 core remains in reset. 2. epc code executes diagnostic and initialization code, which includes the initialization of the np4gs3?s dram controllers. 3. the epc loads the code for the powerpc from the flash memory into the dram. this code includes the branch code loaded into the boot_redir_inst registers. alternatively, this code is loaded using guided traffic. guided traffic flows once the communications port connecting the source has been enabled (see step 6.). 4. the epc starts the 405 core by clearing the powerpc_reset configuration register. this register is accessed via the cab interface. 5. the 405 core will boot from code residing in the plb address space starting at address x?ffff fffc?. this address is decoded by hardware to provide an unconditional branch to instruction space in the pow- erpc?s dram memory. 6. communication ports are configured and enabled by the 405 core or, alternatively, by the epc. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec11_reset.fm.01 09/25/00 reset and initialization page 327 of 444 11. reset and initialization the intent of this section is to provide, by example, a method for initializing the np4gs3. it is not intended to be exhaustive in scope, since there are many configurations and environments where the np4gs3 may be applied. the external serial parallel manager (spm) field programmable gate array (fpga) mentioned in this chapter is a component of the network processor evaluation kit. however, the design for the spm fpga is not provided by ibm. 11.1 overview the np4gs3 supports a variety of system and adapter configurations. in order to support a particular envi- ronment, the network processor must be initialized with parameters that match that environment?s system or adapter requirements. the sequence of reset and initialization is shown in table 215 : some system environments do not require all of the steps and some require that certain steps be performed differently. the np4gs3 supports the system environments shown in figure 73 for reset and initialization. table 215: reset and initialization sequence step action notes 1 set i/os chip i/os set to match adapter requirements 2 reset must be held in reset for minimum of 1 s 3 boot several boot options 4 setup 1 low level hardware setup 5 diagnostics 1 memory and register diagnostics 6 setup 2 basic hardware setup 7 hardware initialization hardware self-initialization of various data structures 8 diagnostics 2 data flow diagnostics 9 operational everything ready for first guided frame 10 configure functional configuration 11 initialization complete everything ready for first data frame IBM32NPR161EPXCAC133 ibm powernp preliminary reset and initialization page 328 of 444 np3_dl_sec11_reset.fm.01 09/25/00 the following sections describe each step in the reset and initialization sequence and the various ways to accomplish each step. 11.2 step 1: set i/os there are several np4gs3 i/os that must be set to appropriate values in order to operate correctly. most of these i/os will be set to a fixed value at the card level, but some will be set to the appropriate value based on system parameters. the following table lists all configurable i/os that must be set prior to initial reset. figure 73: system environments table 216: set i/os checklist i/o values notes testmode(1:0) see table 29: miscellaneous pins on page 63 for the encoding of these i/o adapter may require mechanism to set test mode i/os in order to force various test scenarios. boot_picocode see table 29: miscellaneous pins on page 63 for the encoding of this i/o controls which interface loads the internal epc instruction memory and boots the guided frame handler thread. boot_ppc see table 29: miscellaneous pins on page 63 for the encoding of this i/o controls from where the internal ppc fetches its initial boot code. pci_speed see table 25: pci interface pins on page 59 for the encoding of this i/o controls the speed of the pci bus switch_bna see table 29: miscellaneous pins on page 63 for the encoding of this i/o initial value for primary switch interface spm eeprom cabwatch eeprom host eeprom *externalspmfpga *externaleeprom * optional cabwatch spm eeprom cabwatch spm eeprom cabwatch * external spm fpga * external eeprom * optional cabwatch * external pci eeprom for powerpc * optional spm fpga * optional eeprom * optional cabwatch * optional pci eeprom for powerpc * external pci host pci pci ibm powernp ibm powernp ibm powernp IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec11_reset.fm.01 09/25/00 reset and initialization page 329 of 444 additional configuration bits could be utilized by defining additional i/o on an external spm fpga as configu- ration inputs. if the user defines registers in the spm cab address space and a corresponding external spm fpga design, the np4gs3 can read these spm i/os and make configuration adjustments based on their val- ues (for example, the type of cp interface might be 100 mb or 1 gb). custom boot picocode is required to take advantage of these additional features. all clocks must be operating prior to issuing a reset to the np4gs3. the clock_core, switch clock a, and switch clock b drive internal plls that must lock before the internal clock logic will release the operational signal. the clock125 and dmu_*(3) inputs, if applicable, should also be operating in order to properly reset the dmu interfaces. the pci clock (pci_clk) must be operating in order to properly reset the pci interface. 11.3 step 2: reset the np4gs3 once all the configuration i/os are set and the clocks are running, the np4gs3 can be reset using the blade_reset signal. this signal must be held active for a minimum of 1 s and then returned to its inactive state. internal logic requires an additional 101 s to allow the plls to lock and all internal logic to be reset. the pci bus must be idle during this interval to ensure proper initialization of the pci bus state machine. at this point, the np4gs3 is ready to be booted. in addition to the blade_reset signal, the np4gs3 supports two other ?soft? reset mechanisms: the soft_reset register allows the entire np4gs3 to be reset (just like a blade_reset ), and the powerpc_reset register allows the powerpc core to be reset. a blade_reset or soft_reset causes the powerpc_reset register to activate and hold the powerpc core in reset until this reg- ister is cleared. therefore, a blade_reset resets the entire np4gs3 and holds the powerpc core in reset until it is released by the epc or an external host using the pci bus. 11.4 step 3: boot 11.4.1 boot the embedded processor complex (epc) booting the np4gs3's epc involves loading the internal picocode instruction space and turning over control of execution to the gfh thread. the gfh thread executes the loaded picocode and completes the appropri- ate steps in the bringup process. the np4gs3 supports four ways to load the internal picocode instruction space: through the spm interface logic, through the pci bus from an external host, through the embedded powerpc, or through cabwatch. once the picocode instruction space is loaded, the boot done signal needs to be set by the loading device using the boot_override register, and the gfh thread starts executing the code stored at address '0'. cpdetect_a see table 14: pmm interface pin multiplex- ing on page 44 for the encoding of this i/o used to find a locally attached control point function (cpf) cpdetect_b see table 14: pmm interface pin multiplex- ing on page 44 for the encoding of this i/o used to find a locally attached cpf cpdetect_c see table 14: pmm interface pin multiplex- ing on page 44 for the encoding of this i/o used to find a locally attached cpf cpdetect_d see table 14: pmm interface pin multiplex- ing on page 44 for the encoding of this i/o used to find a locally attached cpf spare_tst_rcvr(9:0) see table 29: miscellaneous pins on page 63 for the correct tie values for these i/o used during manufacturing testing table 216: set i/os checklist i/o values notes IBM32NPR161EPXCAC133 ibm powernp preliminary reset and initialization page 330 of 444 np3_dl_sec11_reset.fm.01 09/25/00 11.4.2 boot the powerpc there are two steps in the process of booting the np4gs3's embedded powerpc. first, using the boot_ppc i/o, the powerpc support logic must be configured to boot the powerpc from either the external d6 dram or the pci bus. second, the powerpc must be released to execute the appropriate boot code. the powerpc boot code can be mapped either into pci address space or into the np4gs3's external d6 dram, depending on the setting of the boot_ppc i/o. if an external host processor is used on the pci bus, it should use the pci configuration protocol to set the np4gs3's pci target maps for access into the network processor's internal address space. if the boot_ppc i/o chooses the pci bus, the internal plb bus addresses x'fffe 0000' through x'ffff ffff' are mapped to pci address space. once the powerpc_reset register is cleared (by either the epc or by an external host across the pci bus), the powerpc will fetch and execute the boot code from across the pci bus. if the boot_ppc i/o chooses the external d6 dram, the d6 dram must be written with the appropriate boot code and the boot_redir_inst registers must be written to point to the code in the d6 dram before the powerpc_reset register is released. the internal logic maps the powerpc's boot addresses of x'ffff ffe0' through x'ffff fffc' to the boot_redir_inst registers and the remaining boot code is fetched from the external d6 dram. the d6 dram and the boot_redir_inst registers can be written by either the epc or an external host on the pci bus. when everything is set up, use a cab write to clear the powerpc_reset register to allow the powerpc core to execute the boot code. 11.4.3 boot summary the epc must be booted by first loading its picocode instructions (by either the spm, an external pci host, the embedded powerpc, or cabwatch) and then issuing the boot done signal (by the picocode loader). if the embedded powerpc is to be used, it must have its instruction space loaded (if d6 is used), then pointing the boot logic to the appropriate boot location (pci or d6), and finally releasing the powerpc_reset register (by either the epc, an external pci host, or cabwatch). once one or both systems are booted, the following steps can be performed by one or both processing complexes. (some accesses to external memories can only be performed by the epc complex.) 11.5 step 4: setup 1 setup 1 is needed to set some low level hardware functions that enable the np4gs3 to interface with its external drams and to configure some internal registers that enable the execution of step 5: diagnostics 1. setup 1 should configure or check the following registers according to the system setup and usage: table 217: setup 1 checklist register fields notes memory configuration register all this register is set to match the populated external memories. dram parameter register all this register is set to match the external dram's characteristics. thread enable register all this register enables the non-gfh threads. the gfh is always enabled. initialization register dram cntl start this bit starts the dram interfaces. initialization done register cm init done e_ds init done these bits indicate that the dram initialization has completed. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec11_reset.fm.01 09/25/00 reset and initialization page 331 of 444 11.6 step 5: diagnostics 1 diagnostics 1 tests internal registers, internal memories, and external memories as required by the diagnos- tics program (read and write tests). this step comes before the hardware initialization step because several of these structures will be initialized by the hardware to contain functional data structures. by testing these structures first, the diagnostics program does not need to be concerned with corrupting the contents of these locations during hardware initialization. care must be taken that the values written to the structures do not force an undesirable situation (such as soft resetting the chip). however, most of these structures can be tested by the diagnostics program to ensure proper operation. table 218 lists some of the structures that could be tested by this step. table 218: diagnostics 1 checklist structure test notes phase locked loop fail verify all plls locked if any pll fails, any further operation is questionable dppu processors alu, scratch memory, internal processor registers test each thread ingress data store read/write egress data store read/write control store d0-d4 read/write control store d6 read/write coordinated with powerpc code loading control store h0-h1 read/write counter definition table configure setup to test counters counter memory read/write/add policy manager memory read/write egress qcbs read/write egress rcb read/write egress target port queues read/write mcca read/write pmm rx/tx counters read/write pmm sa tables read/write ingress bcb read/write ingress fcb read/write not all fields are testable cia memory read/write ingress flow control probability memory read/write egress flow control probability memory read/write dasl-a picocode memory read/write dasl-b picocode memory read/write various internal configuration registers read/write not all fields will be testable, care must be taken when chang- ing certain control bits. IBM32NPR161EPXCAC133 ibm powernp preliminary reset and initialization page 332 of 444 np3_dl_sec11_reset.fm.01 09/25/00 11.7 step 6: setup 2 setup 2 is needed to setup the hardware for self-initialization and to configure the hardware structures for operational state. these configuration registers must be set to the desirable values based on the system design and usage: 11.8 step 7: hardware initialization hardware initialization allows the np4gs3 to self-initialize several internal structures, thereby decreasing the overall time required to prepare the processor for operation. several internal structures will be initialized with free lists, default values, or initial states in order to accept the first guided frames from the cpf. once these data structures are initialized, the picocode should not modify them with further read/write diagnostics. to ini- tiate the hardware self-initialization, the registers shown in table 220 need to be written. table 219: setup 2 checklist register fields notes master grant mode all tb mode all egress reassembly sequence check all aborted frame reassembly action control all packing control all ingress bcb_fq thresholds all egress sdm stack threshold all free queue extended stack maximum size all egress fq thresholds all g queue maximum size all dmu configuration all dmu configuration can be postponed until step 10: configure if dmu init start is also postponed. dmu for cpf must be done dur- ing setup 2. if the dmu is configured, the appropriate external physical devices must also be configured. packet over sonet control all pos configuration can be postponed until step 10: configure if dmu init start is also postponed. ethernet encapsulation type for control all ethernet encapsulation type for data all dasl picocode memory both a and b written with appropriate dasl picocode. dasl initialization and configuration primary set dasl init can be postponed until the configure step if dasl start is also postponed and cpf is locally attached. dasl initialization and configuration dasl wrap mode dasl wrap mode can be postponed until the configure step. dasl wrap all IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec11_reset.fm.01 09/25/00 reset and initialization page 333 of 444 11.9 step 8: diagnostics 2 diagnostics 2 determines if the np4gs3 is ready for operation and allows testing of data flow paths. the items listed in table 221 should be setup, checked, and/or tested. table 220: hardware initialization checklist register fields notes dasl start all only start the dasl interface after the primary set of dasl con- figuration bits have been configured. dasl initialization and configuration alt_ena only start the alternate dasl after the primary dasl has been started. initialization dmu set only start each dmu after its associated dmu configuration has been set. initialization functional island starts all other island's self-initialization. table 221: diagnostic 2 checklist register fields notes initialization done all started in hardware initialization step the code polls this register until a timeout occurs or all expected bits are set. dasl timeout = 20 ms e_eds timeout = 15 ms dasl initialization and configuration pri_sync_term if primary dasl was initialized and sync termination should occur from the network processor, this register should be set to cause idle cells to be sent. dasl initialization and configuration alt_sync_term if alternate dasl was initialized and sync termination should occur from the network processor, this register should be set to cause idle cells to be sent. lu def table read/write test these structures can only be tested after hardware initializa- tion. smt compare table read/write test these structures can only be tested after hardware initializa- tion. tree search free queues read/write test these structures can only be tested after hardware initializa- tion. not all fields are testable port configuration table all set to default values for diagnostics 2 lu def table all set to default values for diagnostics 2 ingress target port data storage map all set to default values for diagnostics 2 target port data storage map all set to default values for diagnostics 2 build frame on egress side lease twins and store test frame in egress data store half wrap wrap test frame from egress to ingress using wrap dmu full wrap wrap ingress frame back to egress side if dasl in wrap mode or dasl has been completely configured including target blade information. external wrap if external physical devices are configured, full external wraps canbeperformed. tree searches to test the tree search logic, tree searches can be performed on a pre-built sample tree written to memory. IBM32NPR161EPXCAC133 ibm powernp preliminary reset and initialization page 334 of 444 np3_dl_sec11_reset.fm.01 09/25/00 11.10 step 9: operational after the diagnostics 2 tests have finished, any previously written default values may need to be updated to allow this step to proceed. if all diagnostics have passed, the operational signal can be activated to indicate to an external cpf that the np4gs3 is ready to receive guided frames. this signal is activated by writing the np4gs3 ready register which then activates the operational i/o. if some portion of the diagnostics have not passed, the ready register should not be written. this causes the cpf to timeout and realize the diagnostic failure. to determine what portion of the diagnostics have failed, the system designer must make provisions at the board or system level to record the status in a location that is accessible by the cpf. one method is to provide an i 2 c interface to an external spm fpga which the cpf could access. 11.11 step 10: configure after the operational signal has been activated, the cpf can send guided frames to the np4gs3 for func- tional configuration. items that can be configured include: table 222: configure checklist register fields notes dasl initialization and configuration primary set the primary set can be configured if postponed during the setup 2 step. dasl initialization and configuration dasl wrap mode dasl wrap mode can be set if postponed during setup 2 step. dasl start all primary dasl can be started if postponed during setup 2 step. dasl initialization and configuration alt_ena the alternate set can be configured if postponed during the setup 2 step. initialization done p_dasl init done this bit should be polled if started during the configure step initialization done a_dasl init done this bit should be polled if started during the configure step dasl initialization and configuration pri_sync_term if primary dasl was initialized and sync termination should occur from the network processor, this register should be set to cause idle cells to be sent. dasl initialization and configuration alt_sync_term if alternate dasl was initialized and sync termination should occur from the network processor, this register should be set to cause idle cells to be sent. dmu configuration all configure now if dmu configuration was postponed during setup 2 step. if the dmu is configured, the appropriate external physical devices also need to be configured. packet over sonet control all configure now if pos configuration was postponed during setup 2 step. functional picocode all functional picocode should be loaded into the instruction memory port config table all functional values for the pct should be set lu def table all functional values should be set. cia memory all functional values should be set. hardware classifier e_type all functional values should be set. hardware classifier sap all functional values should be set. hardware classifier ppp_type all functional values should be set. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec11_reset.fm.01 09/25/00 reset and initialization page 335 of 444 11.12 step 11: initialization complete once steps 1 through 10 are complete, and all the items on the checklists have been configured, the np4gs3 is ready for data traffic. the ports can be enabled (at the physical devices) and switch cells can start to flow. interrupt masks all functional values should be set. timer target all functional values should be set. interrupt target all functional values should be set. address bounds check control all functional values should be set. static table entries all any static table entries should be loaded. ingress target port data storage map all my target blade address all local target blade vector all local mc target blade vector all target port data storage map all egress qcbs all qd accuracy all sa address array all cpf address all counter definition table all counters all any counters used by counter manager must be read/ cleared. policy manager memory all setup initial values for policies. table 222: configure checklist (continued) register fields notes IBM32NPR161EPXCAC133 ibm powernp preliminary reset and initialization page 336 of 444 np3_dl_sec11_reset.fm.01 09/25/00 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec12_debug.fm.01 09/25/00 debug facilities page 337 of 444 12. debug facilities 12.1 debugging picoprocessors the np4gs3 provides several mechanisms to facilitate debugging of the picoprocessors. 12.1.1 single step each thread of the np4gs3 can be enabled individually for single step instruction execution. single step is defined as advancing the instruction address by one cycle and executing the instruction accordingly for enabled threads. coprocessors are not affected by single step mode. therefore coprocessor operations that at ?live? speed would take several cycles may seem to take only one cycle in single step mode. there are two ways to enable a thread for single step operation. the first is to write the single step enable register. this register is a single step bit mask for each thread and can be accessed through the control access bus (cab). the second is the single step exception register. this register is also a bit mask, one for each thread, but when set indicates which threads are to be placed into single step mode on a class3 inter- rupt . when a thread is in single step mode, the thread can only be advanced by writing the single step command register. 12.1.2 break points the np4gs3 supports one instruction break point that is shared by all of the threads. when a thread?s instruction address matches the break point address, a class3 level interrupt is generated. this causes all threads enabled in the single step exception register to enter single step mode. the break point address is configured in the break point address register. 12.1.3 cab accessible registers the scalar and array registers of the core language processor (clp) and of the dppu coprocessors are accessible through the cab for evaluation purposes. the clp?s general purpose registers, which are directly accessible with the clp, are mapped to read only scalar registers on the control access bus. IBM32NPR161EPXCAC133 ibm powernp preliminary debug facilities page 338 of 444 np3_dl_sec12_debug.fm.01 09/25/00 12.2 riscwatch the np4gs3 supports riscwatch through the jtag interface. riscwatch is a hardware and software development tool for the powerpc 600 family of microprocessors and the powerpc 400series of embedded controllers. the source-level debugger and processor-control fea- tures provide developers with the tools needed to develop and debug hardware and software quickly and effi- ciently. developers who take advantage of riscwatch are provided a wealth of advanced debug capabilities. among the advanced features of this full-functioned debugger are: real-time trace, ethernet hardware inter- face, c++ support, extensive command file support, and on-chip debug support. in the future, multi-process- ing will be supported. all this in a debugger that supports both xcoff and the embedded abi for powerpc industry standard. riscwatch includes: on-chip debugging via ieee 1149.1 (jtag) interface target monitor debugging os open real-time operating system aware debugging source-level and assembler debugging of c/c++ executables real-time trace support via the risctrace feature for the powerpc 400series network support for remote debugging of the system under development supports industry standard embedded abi for powerpc and xcoff abi command-file support for automated test and command sequences simple and reliable 16-pin interface to the system under development ethernet to target jtag interface hardware multiple hosts supported intuitive and easy-to-use windowed user interface that reduces development time for more information, go to http://www.chips.ibm.com/products/powerpc/tools/riscwatc.html . IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 339 of 444 13. ibm powernp configuration the np4gs3 must be configured after internal diagnostics have run. configuration is performed by a cpf that generates guided traffic to write configuration registers. these configuration registers are reset by the hardware to a minimal option set. the following sections describe all configuration registers and their reset state. a base address and offset is provided. 13.1 memory configuration the np4gs3 is supported by a number of memory subsystems as shown in figure 2 below. these memories contain data buffers and controls used by the np4gs3. the d0, d1, d2, d3, d4, ds_0, and ds_1 are required for the base configuration of the np4gs3 to operate. the other memory subsystems, z0, z1, and d6, are optional and provide additional functionality or capability when added to the required set of memory subsystems. in its base configuration, the np4gs3 does not perform enhanced scheduling, and has a limited look-up search capability. the enabling of memory subsystem interfaces is controlled by the contents of the memory configuration register. the bits in this register are set by hardware during reset to enable the base configura- tion. figure 74: np4gs3 memory subsystems d4 d6 z0 d0 d3 57 51 33 48 51 ds0 51 ds1 d1 33 d2 33 51 z1 39 ibm powernp IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 340 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.1.1 memory configuration register (memory_config) the memory configuration register enables or disables memory interfaces. it also enables the egress sched- uler and the z1 memory interface required by the egress scheduler to operate. access type read/write base address x?a000 0120? reserved sch_ena z0 d4 d3 d2 d1 d0 reserved d6 ds_1 ds_0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:11 reserved sch_ena 10 0 scheduler enabled control enables both egress scheduler and z1 mem- ory interface. 1 scheduler enabled 0 scheduler disabled when setting this to a value of 1, the target port queue count qcnt_pq must be zero for all ports. when setting this value to 0, the target port queue count qcnt_pq+fq must be zero for all ports. z0 9 0 z0 memory subsystem interface enabled control 1 interface enabled 0 interface disabled d4 8 1 d4 memory subsystem interface enabled control 1 interface enabled 0 interface disabled d3 7 1 d3 memory subsystem interface enabled control 1 interface enabled 0 interface disabled d2 6 1 d2 memory subsystem interface enabled control 1 interface enabled 0 interface disabled d1 5 1 d1 memory subsystem interface enabled control 1 interface enabled 0 interface disabled d0 4 1 d0 memory subsystem interface enabled control 1 interface enabled 0 interface disabled reserved 3 0 reserved d6 2 0 d6 memory subsystem interface enabled control 1 interface enabled 0 interface disabled ds_1 1 1 ds_1 memory subsystem interface enabled control 1 interface enabled 0 interface disabled IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 341 of 444 ds_0 0 1 ds_0 memory subsystem interface enabled control 1 interface enabled 0 interface disabled field name bit(s) reset description IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 342 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.1.2 dram parameter register (dram_parm) the dram parameter register controls the operation of the drams used by the epc and the egress eds. these drams are controlled separately. access type read/write base address x?a000 2400? epc_dram_parms eds_dram_parms r:w_ratio window/bank cas_ latency 8_bank_ena 11/10 drive_strength dll_disable dqs_clamping_dis dram_size fet_cntl_ena d6_parity_mode d0_width reserved ds_error_checking_disable d4_error_checking_disable cas_ latency 8_bank_ena 11/10 drive_strength dll_disable dqs_clamping_dis dram_size fet_cntl_ena 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description r:w_ratio 31:28 x?f? read to write ratio controls the ratio of read to write window accesses associated with the epc drams. window/bank 27 0 window or bank control value controls access to the epc drams on a window by window or bank by bank basis. 0 bankbybankaccess 1 window by window access cas_latency 26:24, 10:8 x?010? dram column address strobe latency value corresponds to the dram?s read latency measured from the column address. 000 - 001 reserved 010 2 clock cycles 011 3 clock cycles 100 - 101 reserved 110 2.5 clock cycles 111 reserved 8_bank_enable 23, 7 0 eight bank addressing mode enable control value. 11/10 22, 6 1 eleven or ten cycle dram control value controls the number of core clock cycles the dram controller uses to define an access window. 0 10 cycle dram 1 11 cycle dram drive_strength 21, 5 0 dram drive strength control dll_disable 20, 4 0 dll disable control dqs_clamping_dis 19, 3 0 dqs disable control dram_size 18:17 00 dram size indicates the size of the control stores d0-d3 in drams. 00 4x1mx16 ddr dram, burst=4 01 4x2mx16 ddr dram, burst=4 10 4x4mx16 ddr dram, burst=4 11 reserved fet_cntl_ena 16, 0 0 fet control enable control IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 343 of 444 d6_parity_mode 15 1 dram d6 parity mode disable control value. 0 d6 interface supports an additional 2 ddr drams which support byte parity. the hardware generates on write and checks parity on read. 1 d6 interface does not support parity. d0_width 14 1 d0 width control indicates if one or two drams are used for the d0 cs. 0 single wide configuration using one dram. a single bank access provides 64 bits of data. 1 double wide configuration using two drams. a single bank access provides 128 bits of data reserved 13 reserved ds_error_checking_disable 12 0 egress datastore error checking disable control. when this field is set to 1, all dram error checking for the egress datastore is disabled. d4_error_checking_disable 11 0 d4 dram error checking disable. when this field is set to 1, all dram error checking for the d4 dram is disabled. dram_size 2:1 00 dram size indicates the size of the egress datastore and d4 drams. 00 4x1mx16 ddr dram, burst=4, x2 01 4x2mx16 ddr dram, burst=4, x2 10 4x4mx16 ddr dram, burst=4, x2 11 reserved the setting of this field affects the size of the extended stack queues as follows: gq 00 01 10 11 gtq 48 k 96 k 192 k reserved ppq 48 k 96 k 192 k reserved gfq 96k 192k 384k reserved gr0 96k 192k 384k reserved gr1 96k 192k 384k reserved gb0 96k 192k 384k reserved gb1 96k 192k 384k reserved discard 96 k 192 k 384 k reserved field name bit(s) reset description IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 344 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.2 master grant mode register (mg_mode) this configuration register configures the master grant io (mgrant_a, mgrant_b) for either nested priority or independent priority mode. access type read/write base address x'a000 0820' reserved mg_mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:1 reserved mg_mode 0 0 0 the mgrant io is defined for nested priority encoding which is defined as: 00 no grant (on any priority) 01 priority 0 has grant 10 priority0and1havegrant 11 priority 0, 1 and 2 have grant 1 the mgrant io is defined for independent priority encoding which is defined as: 00 no grant (on any priority) 01 priority0and1havegrant 10 priority 2 has grant 11 priority 0, 1 and 2 have grant IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 345 of 444 13.3 tb mode register (tb_mode) the target blade mode configures the maximum number of target network processors supported. access type read/write base address x'a000 0410' reserved tb_mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:2 reserved tb_mode 1:0 00 target blade mode. this field is used to define the target blade mode cur- rently in use by the npr. the field is defined as: 00 16 blade mode. valid addresses are 0:15. multicast is indicated as a 16-bit vector. 01 reserved 10 64 blade mode. valid unicast target blade field encodes are 0 through 63. multicast encodes are in the range of 512 through 65535. 11 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 346 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.4 egress reassembly sequence check register (e_reassembly_seq_ck) this configuration register enables sequence checking by the egress reassembly logic. the sequence check- ing insures that start of frame, optional middle of frame, and end of frame indications occur in the expected order for each cell of a frame being reassembled. each cell that does not indicate start or end of frame carries a sequence number that is checked for proper order. access type read/write base address x'a000 0420' reserved seq_chk_ena 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:1 reserved seq_chk_ena 0 1 sequence check enable control 0 sequence checking disabled 1 sequence checking enabled for the e_eds IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 347 of 444 13.5 aborted frame reassembly action control register (afrac) this configuration register controls the action the hardware takes on a frame whose reassembly was aborted due to the receipt of an abort command in a cell header for the frame. access type read/write base address x'a000 0440' reserved afrac 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:1 reserved afrac 0 0 aborted frame reassembly action control 0 aborted frames are enqueued to the discard queue 1 aborted frames are enqueued with other frames on the associated gq IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 348 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.6 packing control register (pack_ctrl) this configuration register is used to enable cell packing by the i-sdm. access type read/write base address x'a000 0480' reserved pack_ena 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:1 reserved pack_ena 0 1 packing enabled flag 0 cell packing disabled 1 cell packing enabled IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 349 of 444 13.7 initialization control registers 13.7.1 initialization register (init) this register controls the initialization of the functional islands. each functional island and the dram control- lers begin initialization when the bits in this register are set to ?1?. each functional island signals the successful completion of initialization by setting its bit in the init_done register. once a functional island has been initial- ized, changing the state of these bits will not longer have any effect until a reset occurs. access type read/write base address x?a000 8100? dmu_init functional_island_init dram_cntl_start reserved dcba 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description dmu_init 31:28 0000 data mover unit initialization control individually initializes each dmu. functional_island_init 27 0 functional island initialization control. 0nop 1 functional islands start hardware initialization. completion of hard- ware initialization is reported in the initialization done register. dram_cntl_start 26 0 dram controller start control. 0nop 1 causes the dram controllers to initialize and start operation. when initialization completes, the dram controllers set the cntl_mem init done and e-ds init done bits of the initialization done register. reserved 25:0 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 350 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.7.2 initialization done register (init_done) this register indicates that functional islands have completed their initialization when the corresponding bits are set to ?1?. this register tracks the initialization state of the functional islands. the gch reads this register during the initialization of the np4gs3. access type read only base address x?a000 8200? e_sched_init_done dmu_init_done i_eds_init_done reserved epc_init_done reserved cm_init_done e_ds_init_done e_eds_init_done reserved reserved p_dasl_init_done a_dasl_init_done reserved dcbaw 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description e_sched_init_done 31 0 set to ?1? by the hardware when the egress scheduler hardware com- pletes its initialization. dmu_init_done 30:26 0 set to ?1? by the hardware when the dmu hardware has completed its ini- tialization. bit dmu 30 d 29 c 28 b 27 a 26 wrap i_eds_init_done 25 0 set to ?1? by the hardware when the ingress eds completes its initializa- tion. reserved 24 reserved epc _ init_done 23 0 set to ?1? by the hardware when the epc completes its initialization. reserved 22 reserved cm_init_done 21 0 set to ?1? by the hardware when the tse?s dram controller for the tse completes its initialization. e_ds_init_done 20 0 set to ?1? by the hardware when the egress data stores? dram controller completes its initialization. e_eds_init_done 19 0 set to ?1? by the hardware when the egress eds completes its initializa- tion reserved 18:17 reserved p_dasl_init_done 16 0 set to ?1? by the hardware when the primary dasl completes its initializa- tion. the dasl interface continues to send synchronization cells. a_dasl_init_done 15 0 set to ?1? by the hardware when the alternate dasl completes its initial- ization. the dasl interface continues to sent synchronization cells. reserved 14:0 reserved IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 351 of 444 13.8 network processor ready register (npr_ready) access type read/write base address x?a004 0020? ready reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description ready 31 0 readyisconfiguredbypicocodetodriveachippintoindicatethatthe np4gs3 has been initialized and is ready to receive guided traffic. 0 np4gs3 not ready 1 np4gs3 ready reserved 30:0 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 352 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.9 phase locked loop fail register (pll_lock_fail) access type read only base address x?a000 0220? reserved pll_c_lock pll_b_lock pll_a_lock fail 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:4 reserved pll_c_lock 3 current status of lock indictor of the core clock pll 0 phase/frequency lock 1 phase/frequency seek pll_b_lock 2 current status of lock indictor of the dasl-b pll 0 phase/frequency lock 1 phase/frequency seek pll_a_lock 1 current status of lock indictor of the dasl-a pll 0 phase/frequency lock 1 phase/frequency seek fail 0 phased locked loop fail indicator - indicates that an on-chip pll has failed. this field is written by the clock logic. 0pllsok 1 pll failed if fail is indicated at the end of the reset interval (101 micro seconds after reset is started) the operational chipioissetto?1?.aftertheendofthe reset interval, a change in fail will not affect operational chip io. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 353 of 444 13.10 software controlled reset register (soft_reset) this register provides a control for software to reset the network processor. access type write only base address x?a000 0240? full_reset reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description full_reset 31 0 full reset value resets the np4gs3 hardware via the picocode. this is the same full reset function provided by the blade_reset io. 0 reserved 1 np4gs3 performs an internal hardware reset reserved 30:0 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 354 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.11 ingress free queue threshold configuration 13.11.1 bcb_fq threshold registers the value of the queue count in the bcb_fq control block is continuously compared to the values each of the three threshold registers contains. the result of this comparison affects the np4gs3?s flow control mech- anisms. the values in these registers must be chosen such that bcb_fq_th_gt bcb_fq_th_0 bcb_fq_th_1 bcb_fq_th_2. for proper operation the minimum value for bcb_fq_th_gt is x'08'. 13.11.2 bcb_fq threshold for guided traffic (bcb_fq_th_gt) the ingress eds reads this register to determine when to discard all packets received. access type read/write base address x'a000 1080' bcb_fq_th_gt reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description bcb_fq_th_gt 31:27 x?08? bcb free queue threshold gt value is measured in units of individual buffers. for example, a threshold value of x?01? represents a threshold of one buffer. reserved 26:0 reserved IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 355 of 444 13.11.3 bcb_fq_threshold_0 / _1 / _2 registers (bcb_fq_th_0/_1/_2) access type read/write base address bcb_fq_th_0 x?a000 1010? bcb_fq_th_1 x?a000 1020? bcb_fq_th_2 x?a000 1040? bcb_fq_th_0 / _1 / _2 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description bcb_fq_th_0 bcb_fq_th_1 bcb_fq_th_2 31:24 x?00? bcb free queue threshold 0 / 1 / 2 value, as measured in units of 16 buffers. for example, a threshold value of x?01? represents a threshold of 16 buffers. the ingress eds reads this field to determine when to perform a discard action. violation of this threshold (bcb queue count is less than this threshold), sends an interrupt to the epc. when bcb_fq_th_0 is violated, the discard action is to perform partial packet discards. new data buffers are not allocated for frame traffic and portions of frames may be lost. when bcb_fq_th_1 is violated, the discard action is to perform packet discards. new data buffers are not allocated for new frame traffic, but frames already started continue to allocated buffers as needed. reserved 23:0 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 356 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.12 ingress target dmu data storage map register (i_tdmu_dsu) this register defines the egress data storage units (dsu) used for each dmu. access type read/write base address x?a000 0180? dsu_encode reserved dmu_d dmu_c dmu_b dmu_a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description dsu_encode 31:24 00 during enqueue operations, the values in this configuration register are loaded into the ingress frame control block?s dsu field when a dsu value is not specified by the enqueue. the hardware determines the tar- get dmu from enqueue information and uses the corresponding field in this configuration register to load the dsu field. four fields are defined, one for each dmu, with the following encode: 00 dsu 0 01 dsu 1 10 reserved 11 dsu0, dsu1 bits dmu 31:30 dmu_d 29:28 dmu_c 27:26 dmu_b 24:25 dmu_a reserved 23:0 reserved IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 357 of 444 13.13 embedded processor complex configuration 13.13.1 powerpc core reset register (powerpc_reset) this register contains a control value used to hold the powerpc core in reset state. access type read/write base address x?a000 8010? ppc_reset reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description ppc_reset 31 1 powerpc core reset - holds the power pc core in a reset state when set to 1. the rest of the power pc functional island is not affected by this con- trol and can only be reset by a full reset. 0 powerpc core reset disabled 1 powerpc core held in reset reserved 30:0 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 358 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.13.2 powerpc boot redirection instruction registers (boot_redir_inst) in system implementations in which the embedded powerpc boots from the d6 dram, the mailbox and dram interface macro performs powerpc boot address redirection. under these conditions, the hardware provides instructions that redirect the boot sequence to a location in the powerpc?s dram. storage for eight instructions is provided by the boot_redir_inst registers. the powerpc boot redirection instruction (boot_redir_inst) registers are accessed from the cab interface. these registers provide capacity for eight instructions for plb addresses x?ffffffe0? - x?fffffffc? these instructions redirect the powerpc to boot from a location in the powerpc?s dram and are configured before the ppc_reset is cleared. access type read/write base address x?3800 0110? - x?3800 0117? boot_redir_inst 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description boot_redir_inst 31:0 x?0000 0000? powerpc boot redirection instruction address values contains instructions used by the powerpc to redirect the boot sequence to a location in d6 dram. offset corresponding powerpc instruction address 0 x?ffff ffe0? 1 x?ffff ffe4? 2 x?ffff ffe8? 3 x?ffff ffec? 4 x?ffff fff0? 5 x?ffff fff4? 6 x?ffff fff8? 7 x?ffff fffc? IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 359 of 444 13.13.3 watch dog reset enable register (wd_reset_ena) this register controls the action of a watch dog timer expiration. when set to 1, the second expiration of the watch dog timer causes a reset to the powerpc core. access type read/write base address x?a000 4800? wd_reset_ena reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description wd_reset_ena 31 0 reset enable. 0 disable reset of powerpc core 1 enable reset of powerpc core on watch dog expire reserved 30:0 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 360 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.13.4 boot override register (boot_override) this register provides boot sequence control in a debug environment. when the np4gs3 is powered on in debug mode, the bl_override bit is set and the spm interface is inhibited from loading the boot picocode. using cabwatch, different boot picocode can be loaded via the cabwatch interface. the gfh can then be started by setting the bd_override bit to ?1?. alternatively, the bl_override bit can be set to ?0?, and the boot picocode will be loaded by the spm interface. access type read/write base address x?a000 8800? bl_override bd_override reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description bl_override 31 see description this is set to the value of the boot_picocode io during reset. 0 boot code is loaded by the spm interface state machine. 1 boot code is loaded by intervention of software. the bootcode can be loaded using the cabwatch interface, using the pci bus, or by using the embedded power pc. when reset to ?1?, a cab write can set this field to ?0? to start the spm interface controlled boot sequence. the spm interface reads this field to control the behavior of its state machine. bd_override 30 0 boot done override control value. 0nop 1 when the spm interface controlled boot loading sequence is over- ridden, this bit is set after the epc?s instruction memory has been loaded to start the epc. a cab write can set this field to ?1? to indicate that the epc?s instruction memory is loaded. the configuration register logic reads this field when generating the por interrupt to the epc. reserved 29:0 reserved IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 361 of 444 13.13.5 thread enable register (thread_enable) this register contains control information used to enable or disable each thread. access type read/write bits 31:1 read only bit 0 base address x?a000 8020? thread_num_ena (31:0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description thread_num_ena (31:1) 31:1 0 thread enable. 0disabled 1 corresponding thread enabled for use thread_num_ena 0 0 1 thread 0 (the gfh) is always enabled and cannot be disabled through this bit. IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 362 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.13.6 gfh data disable register (gfh_data_dis) this register is used to enable the dispatch to assign data frames to the gfh for processing. access type read/write base address x?24c0 0030? reserved gfh_data_dis 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:1 reserved gfh_data_dis 0 0 guided frame handler data enable control. 0 enabled 1notenabled this field is configured to enable or disable the dispatching of data frames to the gfh. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 363 of 444 13.13.7 ingress maximum dcb entries (i_max_dcb) this register defines the maximum number of ingress frames that are currently allowed to be simultaneously serviced by the dispatch unit. this limits the total number of ingress frames occupying space in the dis- patcher control block. access type read/write base address x?2440 0c40? i_max_dcb reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description i_max_dcb 31:28 x?6? maximum number of ingress frames allowed service in the dispatcher control block. reserved 27:0 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 364 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.13.8 egress maximum dcb entries (e_max_dcb) this register defines the maximum number of egress frames that are currently allowed to be simultaneously serviced by the dispatch unit. this limits the total number of egress frames occupying space in the dispatcher control block. access type read/write base address x?2440 0c50? e_max_dcb reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description e_max_dcb 31:28 x?6? maximum number of egress frames allowed service in the dispatcher con- trol block. reserved 27:0 reserved IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 365 of 444 13.13.9 my target blade address register (my_tb) this register contains the local blade address value. access type master copy read/write thread copies read only base addresses thread address thread address master copy x?a000 4080? 16 x?2100 0890? 0 x?2000 0890? 17 x?2110 0890? 1 x?2010 0890? 18 x?2120 0890? 2 x?2020 0890? 19 x?2130 0890? 3 x?2030 0890? 20 x?2140 0890? 4 x?2040 0890? 21 x?2150 0890? 5 x?2050 0890? 22 x?2160 0890? 6 x?2060 0890? 23 x?2170 0890? 7 x?2070 0890? 24 x?2180 0890? 8 x?2080 0890? 25 x?2190 0890? 9 x?2090 0890? 26 x?21a0 0890? 10 x?20a0 0890? 27 x?21b0 0890? 11 x?20b0 0890? 28 x?21c0 0890? 12 x?20c0 0890? 29 x?21d0 0890? 13 x?20d0 0890? 30 x?21e0 0890? 14 x?20e0 0890? 31 x?21f0 0890? 15 x?20f0 0890? reserved tb 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:6 reserved tb 5:0 0 blade address of this network processor. the value in this field is limited by the tb_mode configured (see the ibm powernp np4gs3 hardware reference manual, section 1). it is further limited when configured for dasl wrap mode (see the ibm powernp np4gs3 hardware reference manual, section 1) to a value of either 1 or 0. IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 366 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.13.10 local target blade vector register (local_tb_vector) when both the dasl-a and dasl-b are active, this register is used to determine the interface used when for- warding traffic. the register is defined as a target blade bit vector where each bit in the register represents a target blade address. for unicast traffic, in all target blade modes, the target blade address (defined in both the fcbpage and fcb2) is used to select the appropriate bit in the register for comparison. if the selected bit is set to 1, then local dasl interface is used to transmit the cell, otherwise the remote dasl interface is used for multicast traffic (in 16 blade mode only) the target blade address, (defined in both the fcbpage and fcb2 as a bit vector) is compared bit by bit to the contents of this register. when a bit in the target blade address is set to 1, and the corresponding bit in this register is also set to 1, then the local dasl interface is used to transmit the cell. when a bit in the target blade address is set to 1 and the corresponding bit in this register is set to 0, then the remote dasl interface is used to transmit the cell. for multicast traffic (in 64 blade mode) the local mctarget blade vector register is used (see local mctar- get blade vector register (local_mc_tb_max) on page 367). base address offset 0 base address offset 1 base address offset 0 base address offset 1 access type read/write base addresses x?a000 4100? tb(0:31) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tb(32:63) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description tb(0:31) 31:0 0 this is a bit vector representing target blade addresses 0 to 31. field name bit(s) reset description tb(32:63) 31:0 0 this is a bit vector representing target blade addresses 32 to 63. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 367 of 444 13.13.11 local mctarget blade vector register (local_mc_tb_max) when configured for 64 blade mode, with both the dasl-a and the dasl-b active, this register is used to determine the interface to be used when forwarding multicast traffic. the target blade address (defined in both the fcbpage and fcb2) is compared to the value in the tb_multicast_indentifier field. if the target blade address is less than this value, then the local dasl interface is used to transmit the cell, otherwise the remote dasl interface is used. the tb_multicast_indentifier field is reset to 0, causing all multicast traffic to use the remote dasl, during power on. access type read/write base addresses x'a000 4200' tb_multicast_identifier reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description tb_multicast_identifier 31:16 0 multicast local maximum. the tb field for a frame is compared to the value of this field; when smaller the frame is local. used only when not configured for 16 blade mode. reserved 15:0 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 368 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.14 flow control structures 13.14.1 ingress flow control hardware structures 13.14.1.1 ingress transmit probability memory register (i_tx_prob_mem) the ingress flow control hardware contains an internal memory that holds 64 different transmit probabilities for flow control. the probability memory occupies 16 entries in the cab address space. each probability entry in the cab is 32 bits wide and contains four 7-bit probabilities. the 4-bit access address to each probability entry com- prises two components: the 3-bit qosclass field (qqq) and the 1-bit remote egress status bus value for the current priority (t). the address is formed as qqqt. the qosclass is taken from the ingress fcbpage. the remote egress status bus value for the current priority reflects the threshold status of the egress? leased twin count. the ingress flow control hardware accesses probabilities within each probability memory entry by using the 2-bit color portion of the fc_info field taken from the ingress fcbpage as an index. the probabilities are organized as shown below. access type read/write base address x?3000 00#0? note: ?the base address is listed with a ?#? replacing one of the hex digits. the ?#? ranges from x?0? to x?f?, and indicates which probability entry is being referenced. reserved prob_0 reserved prob_1 reserved prob_2 reserved prob_3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31 reserved prob_0 30:24 transmit probability 0 - transmit probability accessed when color is ?11? reserved 23 reserved prob_1 22:16 transmit probability 1 - transmit probability accessed when color is ?10? reserved 15 reserved prob_2 14:8 transmit probability 2- transmit probability accessed when color is ?01? reserved 7 reserved prob_3 6:0 transmit probability 3- transmit probability accessed when color is ?00? IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 369 of 444 13.14.1.2 ingress pseudo-random number register (i_rand_num) this register contains a 32-bit pseudo-random number used in the flow control algorithms. the cab accesses this register in order to modify its starting point in the pseudo-random sequence. however, a write to this register is not necessary to start the pseudo-random sequence: it starts generating pseudo-random numbers as soon as the reset is finished. access type read/write base addresses x?3000 0100? rand_num 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description rand_num 31:0 32-bit pseudo-random number IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 370 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.14.1.3 free queue thresholds register (fq_th) this register contains three thresholds that are compared against the ingress free queue. the results of this comparison are used in the flow control algorithms. thresholds are in units of 16 buffers. access type read/write base addresses x?a040 0020? reserved fq_sbfq_th fq_p0_th fq_p1_th 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:24 reserved fq_sbfq_th 23:16 x?ff? source blade free queue threshold value compared against the ingress free queue count and used to set the i_freeq_th io to '1'. fq_p0_th 15:8 x?ff? source blade free queue threshold value for priority 0 traffic that is com- pared against the ingress free queue count. fq_p1_th 7:0 x?ff? source blade free queue threshold value for priority 1 traffic that is com- pared against the ingress free queue count. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 371 of 444 13.14.2 egress flow control structures 13.14.2.1 egress transmit probability memory (e_tx_prob_mem) register the egress flow control hardware contains an internal memory that holds 64 different transmit probabilities for flow control. the probability memory occupies 16 entries in the cab address space. each probability entry in the cab is 32 bits wide and contains four 7-bit probabilities. an entry in the egress probability memory is accessed by using the 4-bit fc_info field taken from the egress fcbpage as an index. the egress flow control hardware uses a 2-bit address to access the probabilities within each probability memory entry. this address (formed as fp) comprises two components: a 1-bit ?threshold exceeded? value for the current priority of the flow queue count , and a 1-bit ?threshold exceeded? value for the current priority of the combined flow/port queue count . access type read/write base addresses x?b000 00#0? note: the base address is listed with a ?#? replacing one of the hex digits. the ?#? ranges from x?0? to x?f?, and indicates which probability entry is being referenced. reserved prob_0 reserved prob_1 reserved prob_2 reserved prob_3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31 reserved prob_0 30:24 transmit probability 0 - transmit probability accessed when ?fp? is ?11? reserved 23 reserved prob_1 22:16 transmit probability 1 - transmit probability accessed when ?fp? is ?10? reserved 15 reserved prob_2 14:8 transmit probability 2- transmit probability accessed when ?fp? is ?01? reserved 7 reserved prob_3 6:0 transmit probability 3- transmit probability accessed when ?fp? is ?00? IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 372 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.14.2.2 egress pseudo-random number (e_rand_num) this register contains a 32-bit pseudo-random number used in the flow control algorithms. the cab accesses this register in order to modify its starting point in the pseudo-random sequence. however, a write to this register is not necessary to start the pseudo-random sequence: it starts generating pseudo-random numbers as soon as the reset is finished. access type read/write base addresses x?b000 0100? rand_num 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description rand_num 31:0 32-bit pseudo-random number IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 373 of 444 13.14.2.3 p0 twin count threshold (p0_twin_th) this register contains the threshold value that is compared against the priority 0 twin count. the results of this comparison are used in the flow control algorithms. access type read/write base addresses x?a040 0100? reserved p0_twin_th 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:19 reserved p0_twin_th 18:0 x?0 0000? p0 twin count threshold value used in the egress flow control hard- ware algorithm. IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 374 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.14.2.4 p1 twin count threshold (p1_twin_th) this register contains the threshold value that is compared against the priority 1 twin count. the results of this comparison are used in the flow control algorithms. access type read/write base addresses x?a040 0200? reserved p1_twin_th 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:19 reserved p1_twin_th 18:0 x?0 0000? p1 twin count threshold value used in the egress flow control hard- ware algorithm. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 375 of 444 13.14.2.5 egress p0 twin count ewma threshold register (e_p0_twin_ewma_th) this register contains the threshold value that is compared against the egress p0 twin count ewma . the results of this comparison are placed on the remote egress status bus. access type read/write base addresses x?a040 0400? reserved p0_twin_ewma_th 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:19 reserved p0_twin_ewma_th 18:0 x?0 0000? priority 0 egress leased twin count exponentially weighted moving average threshold value. this value is compared against the egress p0 twin count ewma and its result placed on the remote egress status bus. IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 376 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.14.2.6 egress p1 twin count ewma threshold register (e_p1_twin_ewma_th) this register contains the threshold value that is compared against the egress p1 twin count ewma . the results of this comparison are placed on the remote egress status bus. access type read/write base addresses x?a040 0800? reserved p1_twin_ewma_th 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:19 reserved p1_twin_ewma_th 18:0 x?0 0000? egress priority 1 twin count exponentially weighted moving average threshold value. this value is compared against the egress p1 twin count ewma and its result placed on the remote egress status bus. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 377 of 444 13.14.3 exponentially weighted moving average constant (k) register (ewma_k) this register contains constant (k) values for the various exponentially weighted moving averages calcu- lated in the ingress and egress flow control hardware. the k value is encoded as follows: k encoding constant value 00 1 01 1/2 10 1/4 11 1/8 access type read/write base addresses x?a040 0040? reserved e_fq_ewma_k e_twin_ewma_k i_fq_ewma_k 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:6 reserved e_fq_ewma_k 5:4 00 k value for the egress free queue count exponentially weighted moving average calculation in the egress flow control hardware. e_twin_ewma_k 3:2 00 k value for the egress p0/p1 twin count ewma calculation in the egress flow control hardware. i_fq_ewma_k 1:0 00 k value for the ingress free queue count exponentially weighted moving average calculation in the ingress flow control hardware. IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 378 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.14.4 exponentially weighted moving average sample period (t) register (ewma_t) this register contains the sample periods for the various exponentially weighted moving averages calculated in the ingress and egress flow control hardware. the values in this register are the number of 10 smulti- ples for the interval between calculations of the respective expwas. the computation of an ewma does not occur unless the respective field in this register is non-zero. access type read/write base addresses x?a040 0080? reserved e_fq_ewma_t e_twin_ewma_t i_fq_ewma_t 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:30 reserved e_fq_ewma_t 29:20 x?000? sample period for the egress free queue count exponentially weighted moving average calculation in the egress flow control hardware. e_twin_ewma_t 19:10 x?000? sample period for the egress p0/p1 twin count ewma calculation in the egress flow control hardware. i_fq_ewma_t 9:0 x?000? sample period for the ingress free queue count exponentially weighted moving average calculation in the ingress flow control hardware. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 379 of 444 13.14.5 remote egress status bus configuration enables (res_data_cnf) this register controls operation of the remote egress status bus. the remote egress status bus is a 2-bit bus that allows communication between the system made up of all of the egress flow control hardware components and the system made up of all of the ingress flow control hardware. one bit of this bus is the sync pulse, and the other bit is tdm data reflecting the status of the egress leased twin counts as they relate to their respective thresholds. access type read/write base addresses x?a000 0880? reserved e_res_data_en e_res_sync_en i_res_data_en 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:3 reserved e_res_data_en 2 1 egress remote egress status bus data enable. 0 sets the res_data io to a hi-z state. 1 places data about this np's egress data store congestion state. e_res_sync_en 1 0 egress remote egress status bus sync enable. when this field is set to 1, the np4gs3 transmits a sync pulse every remote egress status bus interval. only one network processor in a sys- tem will have this bit enabled. i_res_data_en 0 1 ingress remote egress status bus data enable. 0 disables use of the remote egress status bus for ingress flow con- trol. the ingress flow control hardware treats the remote egress status bus as if it contained all 0s. 1 enables use of the remote egress status bus for ingress flow con- trol. values are captured for each remote target blade and used for ingress flow control. IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 380 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.15 target port data storage map (tp_ds_map) register the target port data storage map indicates in which data store, ds_0 or ds_1 or both, that data is found for a port. each port is configured with 2 bits; when set to 1, it indicates the data is found in the corresponding data store. base address offset 0 base address offset 1 base address offset 2 access type read/write base address x?a000 0140? dmu_d dmu_c port 9 port 8 port 7 port 6 port 5 port 4 port 3 port 2 port 1 port 0 port 9 port 8 port 7 port 6 port 5 port 4 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dmu_c dmu_b dmu_a port 3 port 2 port 1 port0 port 9 port 8 port 7 port 6 port 5 port 4 port 3 port 2 port 1 port 0 port 9 port 8 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dmu_a reserved port 7 port 6 port 5 port 4 port 3 port 2 port 1 port 0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 ds_1 ds_0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 381 of 444 base address offset 0 base address offset 1 field name bit(s) reset description dmu_d port 9 31:30 01 the relationship between individual bits and the datastore is shown in detail in the diagram above. dmu_d port 8 29:28 01 the relationship between individual bits and the datastore is shown in detail in the diagram above. dmu_d port 7 27:26 01 dmu_d port 6 25:24 01 dmu_d port 5 23:22 01 dmu_d port 4 21:20 01 dmu_d port 3 19:18 01 dmu_d port 2 17:16 01 dmu_d port 1 15:14 01 dmu_d port 0 13:12 01 dmu_c port 9 11:10 01 dmu_c port 8 9:8 01 dmu_c port 7 7:6 01 dmu_c port 6 5:4 01 dmu_c port 5 3:2 01 dmu_c port 4 1:0 01 field name bit(s) reset description dmu_c port 3 31:30 01 the relationship between individual bits and the datastore is shown in detail in the diagram above. dmu_c port 2 29:28 01 dmu_c port 1 27:26 01 dmu_c port 0 25:24 01 dmu_b port 9 23:22 01 dmu_b port 8 21:20 01 dmu_b port 7 19:18 01 dmu_b port 6 17:16 01 dmu_b port 5 15:14 01 dmu_b port 4 13:12 01 dmu_b port 3 11:10 01 dmu_b port 2 9:8 01 dmu_b port 1 7:6 01 dmu_b port 0 5:4 01 dmu_a port 9 3:2 01 dmu_a port 8 1:0 01 IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 382 of 444 np3_dl_sec13_config.fm.01 09/25/00 base address offset 2 field name bit(s) reset description dmu_a port 7 31:30 01 the relationship between individual bits and the datastore is shown in detail in the diagram above. dmu_a port 6 29:28 01 dmu_a port 5 27:26 01 dmu_a port 4 25:24 01 dmu_a port 3 23:22 01 dmu_a port 2 21:20 01 dmu_a port 1 19:18 01 dmu_a port 0 17:16 01 reserved 15:0 reserved IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 383 of 444 13.16 egress sdm stack threshold register (e_sdm_stack_th) access type read/write base address x?a000 1800? threshold reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description threshold 31:28 x?8? e-sdm stack threshold value. when this threshold is violated (threshold value is less than the count of empty entries in the e-sdm stack), send grant is set to its disable state. reserved 27:0 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 384 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.17 free queue extended stack maximum size (fq_es_max) register this register sets the number of buffers that are released into the free queue and thus made available for the storage of received frames. the egress eds reads this register when building the fq_es. access type read/write base address x?a000 2100? fq_es_max reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description fq_es_max 31:24 x?08? maximum size of the free queue extended stack measured in incre- ments of 2 k buffer twins. the egress eds reads this value when building thefq_es.themaximumsizeislimitedbytheddrdramusedbythe egress data store. each 128-bit page holds six entries each. once this register is written, the hardware creates entries in the buffer free queue (fq) at a rate of 6 entries every 150 or 165 ns (rate is dependent on the setting of bit 6 of the dram parameter register - 11/10 ). the value in this register may be modified during operation. however, the new value may not be smaller than the current value. reserved 23:0 reserved IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 385 of 444 13.18 egress free queue thresholds a queue count is maintained by the free queue extended stack management hardware. the count value is continuously compared to the value contained in each of three threshold registers. the result of this compari- son affects the np4gs3?s flow control mechanisms. the register values must be chosen such that fq_es_th_0 fq_es_th_1 fq_es_th_2. 13.18.1 fq_es_threshold_0 register (fq_es_th_0) access type read/write base address x?a000 2010? fq_es_thresh_0 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description fq_es_thresh_0 31:17 x?0000? free queue extended stack threshold 0 as measured in units of 16 twins. when this threshold is violated (the threshold value is greater than the number of remaining twins in the free queue): frame data received at the switch interface is discarded (the number of frames discarded is counted). frames that have started re-assembly that receive data while this thresholdisviolatedarealsodiscarded(alldataassociatedwiththe frame is discarded). guided traffic data is not discarded. an interrupt is sent to the epc. reserved 16:0 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 386 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.18.2 fq_es_threshold_1 register (fq_es_th_1) access type read/write base address x?a000 2020? fq_es_thresh_1 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description fq_es_thresh_1 31:17 x?0000? free queue extended stack threshold 1 as measured in units of 16 twins. when this threshold is violated (the threshold value is greater than the number of remaining twins in the free queue), an interrupt is sent to the epc. reserved 16:0 reserved IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 387 of 444 13.18.3 fq_es_threshold_2 register (fq_es_th_2) access type read/write base address x?a000 2040? fq_es_thresh_2 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description fq_es_thresh_2 31:17 x?0000? free queue extended stack threshold 2 as measured in units of 16 twins. when this threshold is violated (the threshold value is greater than the number of remaining twins in the free queue), an interrupt is sent to the epc and, if enabled by dmu configuration, the ethernet preamble is reducedto6bytes reserved 16:0 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 388 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.19 discard flow qcb register (discard_qcb) this register is used by the egress hardware when the scheduler and flow control are enabled. this register contains the address of the flow qcb to be used when egress flow control actions require that the frame be discarded. this register and the qcb referenced by the address must be configured by hardware. see table 53 on page 147 for details on configuring the qcb. when the scheduler is disabled, the register contains the target port queue to which the flow control dis- carded frames are sent. this value should be set to x?029?. access type read/write base address x?a000 1400? reserved discard_qid 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:11 reserved discard_qid 10:0 x?029? the discard qid field contains the address of the qcb that has been con- figured for discarding egress frames while the scheduler is enabled. when the scheduler is disabled, this is the target port id (x?029?) to which dis- carded frames due to flow control discard actions are sent. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 389 of 444 13.20 frame control block fq size register (fcb_fq_max) this register sets the number of frame control blocks that are released to the fcb fq during initialization. access type read/write base address x?a000 2200? fcb_fq _max reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description fcb_fq_max 31:30 00 indicates the number of fcbs released into the fcb free queue during initialization. 00 128k 01 256k 10 512k 11 1m reserved 29:0 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 390 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.21 data mover unit (dmu) configuration there are four data mover units (dmu) configured for internal mac operation, for external connection detec- tion (i.e. attached control point detection), and for external bus operation (i.e tmii, smii, tbi, and pos framer). base address offset 0 base address offset 1 base address offset 2 base address offset 3 access type base address offset 0 read only base address offset 1 read/write base address offset 2 read/write base address offset 3 read/write base address dmu_a x?a001 0010? dmu_b x?a001 0020? dmu_c x?a001 0040? dmu_d x?a001 0080? reserved in_reset cp_detect 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved framer_ac_strip ac_strip_ena framer_ac_insert ac_insert_ena bus_delay crc_type_32 vlan_chk_dis etype_chk_dis pause_chk_dis ignore_crc enet_catchup_ena tx_thresh dm_bus_mode tx_ena(9:0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved rx_ena (9:0) fdx/hdx (9:0) jumbo (9:0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved honor_pause (9:0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 391 of 444 base address offset 0 base address offset 1 field name bit(s) reset description reserved 31:2 reserved in_reset 1 1 dmu in reset indicator originates in the clocking logic. 0 written when the clock logic removes the reset signal for the dmu. 1 dmu is held in reset mode. cp_detect 0 0 control point detected indicator value originates in the pmm. 0 control point processor connection not present 1 dmu detected a control point processor connection. field name bit(s) reset description reserved 31:28 reserved framer_ac_strip 27 0 configures the mac operation for an attached pos framer. 0 framer passes ac field to the network processor 1 framer does not pass ac field to the network processor. the crc checking performed is modified to account for the missing field. ac value of x'ff03' is assumed. ac_strip_ena 26 0 configures the mac operation for an attached pos framer. 0 ac field is not stripped from the packet. 1 ac field is stripped from the packet prior to being stored in the ingress data store. framer_ac_insert 25 0 configures the mac operation for an attached pos framer. 0 ac field is assumed present in the packet sent to the framer. 1 ac field is not present in the packet sent to the framer. the framer inserts this field and crc generation is adjusted to account for the missing ac field. an ac value of x'ff03' is assumed. ac_insert_ena 24 1 configures the mac operation for an attached pos framer. 0 ac field is not inserted by the mac. for proper operation, framer_ac_insert must be set to 1. 1 ac field is inserted by the mac. for proper operation, framer_ac_insert must be set to 0. bus_delay 23 0 bus delay controls the length of the delay between a poll request being made and when the mac samples the framer?s response. 0 sampleistaken1cycleafterthepollrequest 1 sample is taken 2 cycles after the poll request. crc_type_32 22 0 crc_type_32 controls the type of frame crc checking and generation performed in the mac. 0 16-bit crc in use. 1 32-bit crc in use vlan_chk_dis 21 0 vlan checking disable control value. 0 enable vlan checking. 1 disable vlan checking by the dmu. etype_chk_dis 20 0 ethernet type checking disable control value. 0 enable dmu checking. 1 disable dmu checking of e_type_c and e_type_d IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 392 of 444 np3_dl_sec13_config.fm.01 09/25/00 base address offset 2 pause_chk_dis 19 0 pause frame checking disable control value. 0 pause frames are processed by the mac. they are not sent to the ingress eds. 1 pause frames are not processed by the mac. the frames are sent to the ingress eds for service. see also honor_pause in offset 3 for additional control of the mac in rela- tion to pause frames. ignore_crc 18 0 ignore crc controls the behavior of crc checking for each dmu. 0 discard frames with bad crc 1 ignore bad crc enet_catchup_ena 17 1 ethernet mac catch up enabled. when enabled and fq_es_threshold_2 is violated, the mac uses a 6-byte preamble instead of a 7-byte preamble. 0disabled 1 enabled tx_thresh 16:14 100 transmit threshold configures the number of cell buffers that must be filled before the transmission of a frame can start. 000 invalid 001-100 valid range 101-111 invalid dm_bus_mode 13:10 1010 data mover bus mode configures the mode in which the dm bus oper- ates. 0000 reserved 0001 10/100 ethernet smii mode 0010 gigabit ethernet gmii mode 0011 gigabit ethernet tbi mode 0100 pos oc12 mode; non-polling pos support 0101 pos 4xoc3 mode; polling pos support 0110-1001 reserved 1010 cp detect mode 1011 debug mode (dmu d only) 1100-1101 reserved 1110 dmu disabled 1111 pos oc48 mode; quad dmu mode, non-polling, pos sup- port tx_ena(9:0) 9:0 0 port transmit enable control is a bitwise enable for each port?s transmit- ter. 0disableport 1 enable port field name bit(s) reset description reserved 31:30 reserved rx_ena(9:0) 29:20 0 port receive enable control is a bitwise enable for each port?s receiver. 0disableport 1 enable port fdx/hdx (9:0) 19:10 0 full duplex or half duplex operation mode for ports 9 to 0 controls the mode of operation for the associated port. 0 half duplex (hdx) operation 1 full duplex (fdx) operation field name bit(s) reset description IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 393 of 444 base address offset 3 jumbo(9:0) 9:0 0 jumbo frame operation mode for ports 9 to 0 controls the mode of opera- tion for the associated port. 0 jumbo frames disabled 1 jumbo frames enabled field name bit(s) reset description reserved 31:10 reserved honor_pause(9:0) 9:0 0 honor pause control value is a bitwise control value for the port?s pause function. 0 ignore pause frames received by corresponding port 1 pause when pause frame received by corresponding port field name bit(s) reset description IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 394 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.22 qd accuracy register (qd_acc) the qd accuracy register tunes the egress scheduler?s wfq rings. the values assure fairness and some benefit to queues with lower defined qd values which expect better service when enqueueing to an empty queue. the value is also a scaling factor when servicing queues. configuration recommendations are depen- dent on the maximum frame sizes expected for a dmu. max frame size qd_acc_dmu 2k 6 9k 8 14 k 10 there is one field defined per media dmu (a-d). access type read/write base address x?a002 4000? qd_acc_ dmu_d qd_acc_ dmu_c qd_acc_ dmu_b qd_acc_ dmu_a reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description qd_acc_dmu_d 31:28 0 qd accuracy value used for dmu_d qd_acc_dmu_c 27:24 0 qd accuracy value used for dmu_c qd_acc_dmu_b 23:20 0 qd accuracy value used for dmu_b qd_acc_dmu_a 19:16 0 qd accuracy value used for dmu_a reserved 15:0 reserved IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 395 of 444 13.23 packet over sonet control register (pos_ctrl) one configuration register per dmu is provided to control pos framer interaction. it configures transmit and receive burst sizes and sets the value used for ac field insertion. access type read/write base address dmu_a x?a004 0100? dmu_b x?a004 0200? dmu_c x?a004 0400? dmu_d x?a004 0800? tx_burst_size rx_burst_size a/c insert value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description tx_burst_size 31:24 x'10' transmit burst size. used only for oc3 modes of operation. oc12 and oc48 interfaces transmit until the framer de-assertstxpfa. when set to 0 the mac uses txpfa from the frame to stop transmission of data. when set to a value other than 0, the mac will burst data to the framer up to the burst size or until the framer drops txpfa. it is recommended that the low water mark in the frame be set to a value equal to or greater than the value of tx_burst_size. rx_burst_size 23:16 x'10' receive burst size a/c insert value 15:0 x'ff03' value used by the mac when ac_insert_ena is set to 1 IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 396 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.24 packet over sonet maximum frame size (pos_max_fs) this register controls the maximum frame size supported by the network processor. pos permits frames up to 64 k bytes, however, the network processor is constrained to 14 k (14336) bytes maximum. this register allows setting for smaller frame sizes. frames received by the network processor that exceed the length specified by this register are aborted during reception. access type read/write base address x?a004 0080? reserved pos_max_fs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:14 reserved pos_max_fs 13:0 x?3800? packet over sonet maximum frame size sets the maximum frame size that the network processor can receive on a pos port. the value in this register is used to determine the length of a long frame for the ingress and egress long frame counters. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 397 of 444 13.25 ethernet encapsulation type register for control (e_type_c) this configuration register is used by the pmm to recognize ethernet-encapsulated guided frames. when the ethernet frame?s type field matches this value, the mac da, sa, and type fields of the frame are stripped and the frame is queued onto the gfq. access type read/write base addresses x?a001 1000? e_type reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description e_type 31:16 x?0000? ethernet type used for encapsulated guided traffic. reserved 15:0 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 398 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.26 ethernet encapsulation type register for data (e_type_d) this configuration register is used by the pmm to recognize ethernet-encapsulated data frames. when the ethernet frame?s type field matches this value, the mac da, sa, and type fields of the frame are stripped and the frame is queued onto the gdq. access type read/write base addresses x?a001 2000? e_type reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description e_type 31:16 x?0000? ethernet type used for encapsulated cp data traffic. reserved 15:0 reserved IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 399 of 444 13.27 source address array (sa_array) the sa array is a register array containing 64 source address values. the sa pointer from the egress fcb references elements of this register array. the value retrieved from the sa array is used to insert or overlay the sa field of transmitted frames during egress frame alteration. base address offset 0 base address offset 1 base address offset 0 base address offset 1 access type read/write base addresses note: each dmu listed below contains 64 entries. nibbles 5 and 6 of the base address is incremented by x?01? for each successive entry, represented by ?##?, and ranging from x?00? to x?3f?. the word offset is represented by ?w?, and ranges from x?0? to x?1?. dmu_a x?8810 0##w? dmu_b x?8811 0##w? dmu_c x?8812 0##w? dmu_d x?8813 0##w? wrap x?8814 0##w? sa (47:16) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sa (15:0) reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description sa(47:16) 31:0 not defined source address value. the dmu accesses an sa value when it performs egress frame alteration functions. the data is the source address that is either overlaid or inserted into a frame. the entry address is inferred from the contents of the fcb. field name bit(s) reset description sa(15:0) 31:16 not defined source address value. the dmu accesses an sa value when it performs egress frame alteration functions. the data is the source address that is either overlaid or inserted into a frame. the entry address is inferred from the contents of the fcb. reserved 15:0 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 400 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.28 dasl initialization and configuration 13.28.1 dasl configuration register (dasl_config) this register contains control information for the dasl-a and dasl-b interfaces. access type read/write base address x?a000 0110? external_wrap_mode gs_mode gs_throttle switchover_init alt_ena pri_sync_term alt_sync_term sdm_priority sdm_use_primary sdm_use_alternate probe_priority probe_use_primary probe_use_alternate reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description external_wrap_mode 31 0 external wrap mode indicator value. 0 the network processor is configured for dasl connection to one or two switches supporting up to 64 target blades. 1 the network processor is configured for external dasl wrap con- nections. one or two network processors can be supported in this mode, restricting target blade addressing to the values of 0 or 1. gs_mode 30:29 01 grant status mode controls the setting of and response to grant status by a functional unit. 00 switch grant status algorithm 01 deassert grant status when e-sdm is full. ingress eds stops sending cells to the swi. 10 deassert grant status one out of every n+1 times, where the value n is contained in the gs throttle field. 11 deassert grant status when e-sdm if full. i-sif i-sci stops send- ing cells to the dasl. gs_throttle 28:22 x?00? grant status throttle when gs mode is set to '10', gs throttle controls the rate at which grant status is deasserted. that rate is once every ?gs_throttle + 1? cell times. switchover_init 21 0 switchover initialization 0nop 1 switchover initialization re-starts the primary dasl interface (nor- mal use is in response to a switchover event). alt_ena 20 0 alternate dasl enable control flag. 0nop 1 set by swi to enable the alternate dasl port. then the swi starts sending sync cells and the receiver searches the attain synchroni- zation with the incoming serial stream. pri_sync_term 19 0 primary dasl synchronization termination 0nop 1 stops the np4gs3?s primary dasl interface from sending the syn- chronization pattern that completes the dasl synchronization sequence on the primary dasl interface. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 401 of 444 alt_sync_term 18 0 alternate dasl synchronization termination 0nop 1 stops the np4gs3?s alternate dasl interface from sending the synchronization pattern that completes the dasl synchronization sequence on the alternate dasl interface. sdm_priority 17 1 i-sdm priority configures the arbitration priority of i-sdm accesses to the dasl interface. 0 high priority 1lowpriority sdm use primary 16 1 sdm use primary 0nop 1 configures the i-sdm traffic to use the primary dasl interface. sdm_use_alternate 15 0 sdm use alternate 0nop 1 configures the i-sdm traffic to use the alternate dasl interface. probe_priority 14 0 probe_priority configures the arbitration priority of the probe accesses to the dasl interface. 0 high priority 1lowpriority probe_use_primary 13 0 probe use primary 0nop 1 configures the probe traffic to use the primary dasl interface. probe_use_alternate 12 1 probe use alternate 0nop 1 configures the probe traffic to use the alternate dasl interface. reserved 11:0 reserved field name bit(s) reset description IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 402 of 444 np3_dl_sec13_config.fm.01 09/25/00 13.28.2 dasl bypass and wrap register (dasl_bypass_wrap) this register controls the internal wrap path which bypasses the dasl interface. access type read/write base address x?a002 0080? bypass_ wrap_ena b a reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description bypass_wrap_ena 31:30 00 dasl bypass and wrap control enables or disables the dasl bypass and internal wrap path. bit 31 controls the wrap for the dasl-b interface. bit 30 controls the wrap for the dasl-a interface. 0 wrap disabled 1 wrap enabled reserved 29:0 reserved IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec13_config.fm.01 09/25/00 ibm powernp configuration page 403 of 444 13.28.3 dasl start register (dasl_start) this configuration register initializes the dasl interfaces when the dasl_init field makes a transition from ?0? to ?1?. the completion of dasl initialization is reported in the init_done register. access type read/write base address x?a000 0210? dasl_init reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description dasl_init 31 0 dasl initialization control value. switching this value from ?0? to ?1? causes the dasl interfaces to initialize. reserved 30:0 reserved IBM32NPR161EPXCAC133 ibm powernp preliminary ibm powernp configuration page 404 of 444 np3_dl_sec13_config.fm.01 09/25/00 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec14_elec.fm.01 09/25/00 electrical and thermal specifications page 405 of 444 14. electrical and thermal specifications the np4gs3 utilizes ibm cmos sa27e technology. table 223: absolute maximum ratings symbol parameter rating units notes 1.8 v v dd power supply voltage 1.95 v 1 t a operating temperature (ambient) -40 to +100 c1 t j junction temperature -55 to +125 c1 t stg storagetemperature -65to+150 c1 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reli- ability. table 224: input capacitance (pf) (page 1 of 21) t a =25 c,f=1mhz,v dd =3.3v 0.3v) grid position signal name total incap a02 sch_addr(11) 11.31 a03 spare_tst_rcvr(2) 9.37 a04 sch_addr(02) 11.01 a05 switch_clk_b 8.67 a06 sch_data(08) 10.81 a07 sch_addr(00) 10.21 a08 sch_data(15) 10.31 a09 sch_data(07) 10.01 a10 sch_data(00) 9.91 a11 d4_addr(01) 9.81 a12 dd_ba(0) 10.01 a13 d4_data(31) 8.8 a14 d4_data(24) 8.5 a15 d4_data(19) 8.7 a16 d4_data(11) 8.5 a17 d4_data(04) 8.7 a18 ds1_data(26) 8.5 a19 ds1_data(19) 8.8 a20 ds1_data(14) 8.7 a21 ds1_data(06) 9 a22 ds1_data(00) 9.1 a23 ds0_addr(10) 10.21 IBM32NPR161EPXCAC133 ibm powernp preliminary electrical and thermal specifications page 406 of 444 np3_dl_sec14_elec.fm.01 09/25/00 a24 ds0_dqs(2) 9 a25 ds0_data(28) 9.2 a26 ds0_data(20) 9.5 a27 ds0_data(14) 9.5 a28 ds0_addr(00) 11.41 a29 ds0_data(09) 10 a30 ds0_data(13) 10.4 a31 ds0_cs 11.81 a32 ds0_data(01) 10.8 a33 ds0_data(03) 11.7 aa03 dasl_in_a(7) 6.5 aa04 dasl_in_a(6) 5.9 aa05 lu_addr(17) 7.31 aa06 lu_data(23) 7.71 aa07 lu_data(28) 7.51 aa08 lu_data(29) 7.01 aa09 lu_addr(00) 6.81 aa10 lu_addr(02) 6.31 aa11 lu_addr(18) 5.81 aa12 d0_data(00) 4.8 aa14 d0_addr(04) 6.11 aa15 d1_data(06) 5 aa16 d3_data(01) 5.1 aa17 d3_addr(06) 6.21 aa18 d2_data(03) 5 aa19 d2_addr(12) 6.21 aa20 da_ba(1) 6.1 aa22 jtag_tck 5.85 aa23 jtag_tdo 6.15 aa25 dmu_a(28) 7.05 aa26 dmu_a(27) 7.25 aa27 dmu_a(26) 7.15 aa28 dmu_a(25) 7.55 aa29 dmu_a(24) 7.85 aa30 dmu_a(23) 8.45 aa31 dmu_a(22) 8.95 table 224: input capacitance (pf) (continued) (page 2 of 21) t a =25 c,f=1mhz,v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec14_elec.fm.01 09/25/00 electrical and thermal specifications page 407 of 444 aa32 dmu_a(21) 9.55 aa33 dmu_a(20) 9.95 ab03 dasl_in_a(6) 6.4 ab05 lu_addr(14) 7.81 ab07 lu_addr(03) 7.51 ab09 lu_addr(16) 6.91 ab11 d0_data(03) 4.7 ab13 d0_data(28) 5 ab15 d0_addr(05) 6.11 ab17 d1_addr(00) 6.21 ab19 d2_dqs(0) 5.1 ab21 d6_data(04) 5 ab23 c405_debug_halt 6.15 ab25 pci_ad(02) 8.55 ab27 pci_ad(01) 8.55 ab29 pci_ad(00) 9.75 ab31 dmu_a(30) 8.85 ab33 dmu_a(29) 9.95 ac01 lu_addr(07) 9.41 ac02 dasl_in_a(5) 7 ac03 dasl_in_a(5) 6.6 ac04 lu_addr(11) 8.41 ac08 lu_r_wrt 7.51 ac09 lu_addr(04) 7.01 ac11 d0_data(13) 5 ac12 d0_dqs(1) 5 ac14 d0_addr(10) 6.31 ac15 d0_data(29) 5.1 ac16 d1_data(15) 5.1 ac17 d3_dqs(1) 5.1 ac18 d3_addr(07) 6.41 ac20 d2_addr(05) 6.51 ac21 d6_data(10) 5.1 ac22 d6_data(15) 5.1 ac23 pci_bus_m_int 7.45 ac24 pci_ad(11) 8.15 table 224: input capacitance (pf) (continued) (page 3 of 21) t a =25 c,f=1mhz,v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 ibm powernp preliminary electrical and thermal specifications page 408 of 444 np3_dl_sec14_elec.fm.01 09/25/00 ac25 pci_ad(10) 8.55 ac26 pci_ad(09) 8.45 ac27 pci_ad(08) 8.65 ac28 pci_cbe(0) 9.25 ac29 pci_ad(07) 9.65 ac30 pci_ad(06) 10.35 ac31 pci_ad(05) 10.45 ac32 pci_ad(04) 10.85 ac33 pci_ad(03) 11.35 ad01 dasl_in_a(4) 7.6 ad03 dasl_in_a(4) 6.8 ad07 lu_addr(12) 7.71 ad09 d0_data(01) 5.9 ad11 d0_data(23) 5.2 ad13 db_ba(1) 6.5 ad15 d1_cs 6.61 ad19 d3_we 6.81 ad21 d2_addr(06) 6.81 ad25 pci_cbe(1) 8.55 ad27 pci_ad(15) 9.45 ad29 pci_ad(14) 9.95 ad31 pci_ad(13) 10.65 ad33 pci_ad(12) 11.45 ae01 dasl_in_a(3) 7.7 ae02 dasl_in_a(1) 7.2 ae03 dasl_in_a(3) 6.9 ae06 lu_addr(05) 8.61 ae07 lu_addr(06) 7.61 ae08 lu_addr(15) 7.71 ae09 d0_data(11) 5.9 ae10 d0_data(22) 5.9 ae11 d0_dqs(2) 5.8 ae12 d1_data(00) 5.7 ae13 db_ras 6.7 ae14 d1_addr(07) 6.91 ae15 d3_data(03) 5.8 table 224: input capacitance (pf) (continued) (page 4 of 21) t a =25 c,f=1mhz,v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec14_elec.fm.01 09/25/00 electrical and thermal specifications page 409 of 444 ae16 d3_data(09) 5.7 ae17 d2_data(08) 6.3 ae18 d3_addr(05) 7.11 ae19 d3_addr(12) 7.21 ae20 d2_data(07) 6 ae21 d2_data(09) 6 ae22 d6_data(14) 6 ae23 d6_data(09) 6.1 ae24 d6_addr(02) 7.3 ae25 mgrant_b(1) 7.15 ae26 pci_frame 8.75 ae27 pci_irdy 9.65 ae28 pci_trdy 10.25 ae29 pci_devsel 10.05 ae30 pci_stop 10.55 ae31 pci_perr 10.75 ae32 pci_serr 11.05 ae33 pci_par 11.55 af01 dasl_in_a(1) 8 af07 lu_addr(13) 7.91 af09 d0_data(20) 6.5 af11 d0_addr(12) 7.51 af13 d1_addr(06) 7.21 af15 d3_data(14) 6.1 af17 d3_addr(02) 7.01 af19 d3_data(15) 6.2 af21 d6_dqs_par(01) 6.3 af23 d6_byteen(1) 7.7 af25 d6_addr(04) 7.5 af27 pci_ad(17) 9.55 af29 pci_ad(16) 10.35 af31 pci_cbe(2) 11.15 af33 pci_clk 11.85 ag03 d0_data(09) 8 ag05 lu_addr(09) 10.01 ag06 lu_addr(10) 8.81 table 224: input capacitance (pf) (continued) (page 5 of 21) t a =25 c,f=1mhz,v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 ibm powernp preliminary electrical and thermal specifications page 410 of 444 np3_dl_sec14_elec.fm.01 09/25/00 ag07 d0_data(02) 6.7 ag08 d0_data(21) 6.6 ag09 d0_dqs(0) 6.5 ag10 d0_addr(11) 7.71 ag11 db_ba(0) 6.4 ag12 d1_addr(05) 7.61 ag13 d3_data(00) 6.5 ag14 d3_data(02) 6.5 ag15 d3_data(13) 6.4 ag16 d3_data(10) 6.4 ag17 d3_data(12) 6.2 ag18 d3_addr(04) 7.71 ag19 d3_addr(00) 7.71 ag20 d3_dqs(0) 6 ag21 d6_addr(11) 7.1 ag22 d2_data(10) 6.1 ag23 d2_addr(07) 7.61 ag24 d6_byteen(0) 8.2 ag25 da_ras 8.2 ag26 d6_addr(03) 8.3 ag27 mgrant_b(0) 8.25 ag28 pci_ad(23) 10.45 ag29 pci_ad(22) 11.65 ag30 pci_ad(21) 10.95 ag31 pci_ad(20) 11.05 ag32 pci_ad(19) 11.75 ag33 pci_ad(18) 11.85 ah01 dasl_in_a(2) 8.7 ah03 dasl_in_a(2) 7.9 ah05 de_ba(1) 8.61 ah07 d0_data(10) 7.7 ah09 d0_dqs(3) 6.7 ah11 d1_data(11) 6.3 ah13 d1_data(14) 6.2 ah15 d1_addr(11) 7.41 ah17 d3_data(11) 6.1 table 224: input capacitance (pf) (continued) (page 6 of 21) t a =25 c,f=1mhz,v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec14_elec.fm.01 09/25/00 electrical and thermal specifications page 411 of 444 ah19 db_clk 7.4 ah21 d2_addr(01) 7.71 ah23 d2_addr(04) 8.01 ah25 d6_data(08) 7.3 ah27 d6_addr(12) 9.6 ah29 pci_ad(24) 10.25 ah31 pci_cbe(3) 11.65 ah33 pci_idsel 12.45 aj02 dasl_in_a(0) 8.5 aj03 lu_clk 9.51 aj04 de_clk 9 aj05 de_clk 8.7 aj06 d0_data(14) 8.6 aj07 d0_data(16) 7.4 aj08 d0_data(31) 7.2 aj09 d0_addr(02) 8.31 aj10 d1_data(03) 6.9 aj11 d1_data(07) 6.4 aj12 db_cas 7.8 aj13 d1_addr(01) 7.21 aj14 d1_dqs(0) 6.7 aj15 d1_addr(12) 7.91 aj16 d3_addr(01) 7.61 aj17 d3_addr(03) 7.81 aj18 db_clk 7.4 aj19 d2_data(01) 6.8 aj20 d2_data(04) 6.9 aj21 d2_data(14) 7.1 aj22 d2_addr(00) 8.41 aj23 d2_addr(11) 8.61 aj24 d2_we 8.61 aj25 d6_we 8.7 aj26 d6_data(12) 7.9 aj27 d6_addr(07) 9.1 aj28 d6_addr(09) 10.4 aj29 pci_ad(29) 10.65 table 224: input capacitance (pf) (continued) (page 7 of 21) t a =25 c,f=1mhz,v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 ibm powernp preliminary electrical and thermal specifications page 412 of 444 np3_dl_sec14_elec.fm.01 09/25/00 aj30 pci_ad(28) 10.95 aj31 pci_ad(27) 11.35 aj32 pci_ad(26) 12.15 aj33 pci_ad(25) 12.25 ak01 dasl_in_a(0) 9.3 ak03 de_ras 9.91 ak05 d0_data(15) 8 ak07 d0_data(30) 8.1 ak09 d1_data(04) 7.7 ak11 d1_data(08) 7.2 ak13 d1_addr(02) 8.41 ak15 d3_data(07) 7.3 ak17 d3_addr(11) 8.11 ak19 d3_addr(08) 8.71 ak21 d2_data(13) 7.5 ak23 d2_addr(10) 8.81 ak25 d2_dqs(1) 8.3 ak27 d6_data(13) 8.7 ak29 d6_addr(08) 9.8 ak31 pci_ad(31) 11.65 ak33 pci_ad(30) 12.95 al01 spare_tst_rcvr(4) 8.25 al02 de_cas 10.61 al03 d0_data(12) 9.2 al04 d0_data(08) 8.8 al05 switch_clk_a 7.87 al06 d0_data(26) 8.5 al07 d0_data(19) 8.2 al08 d0_addr(07) 9.11 al09 d0_data(25) 7.7 al10 d0_addr(00) 9.01 al11 d0_addr(09) 6.61 al12 d1_data(02) 7.7 al13 d1_data(09) 6.6 al14 d1_addr(09) 8.81 al15 d3_data(06) 5.1 table 224: input capacitance (pf) (continued) (page 8 of 21) t a =25 c,f=1mhz,v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec14_elec.fm.01 09/25/00 electrical and thermal specifications page 413 of 444 al16 d1_we 8.91 al17 d3_data(04) 7.5 al18 d3_cs 8.91 al19 d3_addr(09) 9.11 al20 d2_data(05) 7.7 al21 d2_addr(09) 8.91 al22 d2_cs 9.21 al23 d6_data(00) 7.9 al24 d6_data(07) 8.3 al25 da_clk 9.2 al26 d6_data(02) 8.4 al27 d6_addr(05) 9.8 al28 d6_addr(00) 10.2 al29 d6_addr(10) 10.3 al30 d6_dqs(0) 9.5 al31 d6_cs 11 al32 pci_grant 12.35 al33 pci_request 13.05 am01 de_ba(0) 11.31 am03 d0_data(05) 9.5 am05 d0_data(27) 9.4 am07 d0_addr(06) 9.91 am09 d0_we 9.71 am11 d0_addr(08) 9.51 am13 d1_data(12) 8 am15 d1_addr(03) 9.21 am17 d3_data(05) 8.2 am19 d2_data(12) 8 am21 d2_addr(03) 9.41 am23 d6_data(01) 8.6 am25 da_clk 9.9 am27 d6_data(03) 9.3 am29 d6_parity(00) 10 am31 d6_dqs(3) 10.2 am33 pci_inta 13.05 an01 d0_data(06) 9.3 table 224: input capacitance (pf) (continued) (page 9 of 21) t a =25 c,f=1mhz,v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 ibm powernp preliminary electrical and thermal specifications page 414 of 444 np3_dl_sec14_elec.fm.01 09/25/00 an02 d0_data(04) 10.1 an03 d0_data(07) 9.9 an04 d0_data(17) 9.8 an05 switch_clk_a 7.77 an06 d0_addr(03) 10.81 an07 d0_data(18) 9 an08 d0_data(24) 9.1 an09 d0_cs 9.41 an10 d0_addr(01) 9.91 an11 d1_data(01) 7.4 an12 d1_data(10) 8.8 an13 d1_data(13) 6.4 an14 d1_addr(04) 9.71 an15 d1_addr(08) 9.91 an16 d1_dqs(1) 8.5 an17 d3_addr(10) 9.91 an18 d2_data(00) 8.5 an19 d2_data(06) 8.8 an20 d2_data(11) 8.7 an21 d2_addr(02) 10.21 an22 d2_addr(08) 10.31 an23 d6_parity(01) 9 an24 d6_data(06) 9 an25 d6_data(11) 9.2 an26 d6_addr(01) 10.5 an27 da_cas 10.5 an28 d6_data(05) 10.2 an29 da_ba(0) 11 an30 d6_addr(06) 11.4 an31 d6_dqs(1) 10.6 an32 d6_dqs_par(00) 10.8 an33 d6_dqs(2) 11.7 b01 sch_addr(16) 11.31 b03 sch_addr(13) 10.71 b05 sch_addr(01) 10.61 b07 d4_addr(12) 9.91 table 224: input capacitance (pf) (continued) (page 10 of 21) t a =25 c, f = 1mhz, v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec14_elec.fm.01 09/25/00 electrical and thermal specifications page 415 of 444 b09 sch_data(06) 9.71 b11 d4_addr(07) 9.51 b13 dd_clk 9 b15 d4_data(25) 8 b17 ds1_dqs(0) 8.2 b19 ds1_data(13) 8 b21 ds1_data(05) 8.2 b23 ds0_addr(05) 9.81 b25 ds0_data(29) 8.9 b27 ds0_addr(03) 10.51 b29 ds0_data(23) 10 b31 ds0_data(02) 10.2 b33 clock125 11.65 c01 sch_addr(17) 11.31 c02 sch_addr(14) 10.61 c03 sch_addr(09) 10.41 c04 sch_addr(12) 10.01 c05 switch_clk_b 7.87 c06 sch_data(12) 9.71 c07 sch_clk 9.41 c08 d4_addr(09) 9.11 c09 sch_data(14) 8.91 c10 sch_data(01) 9.01 c11 d4_addr(06) 8.81 c12 d4_addr(00) 8.91 c13 dd_clk 8.4 c14 d4_data(17) 7.6 c15 d4_data(03) 7.7 c16 d4_data(10) 7.7 c17 ds1_we 8.61 c18 ds1_data(27) 7.7 c19 ds1_dqs(1) 7.9 c20 ds1_data(21) 7.7 c21 dc_ras 8.7 c22 ds0_addr(11) 9.21 c23 ds0_addr(06) 9.11 table 224: input capacitance (pf) (continued) (page 11 of 21) t a =25 c, f = 1mhz, v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 ibm powernp preliminary electrical and thermal specifications page 416 of 444 np3_dl_sec14_elec.fm.01 09/25/00 c24 ds0_dqs(1) 8.3 c25 ds0_data(21) 8.2 c26 ds0_addr(04) 9.61 c27 ds0_data(15) 8.8 c28 ds0_data(22) 9.2 c29 ds0_data(08) 9.3 c30 ds0_data(04) 9.5 c31 ds0_data(05) 10 c32 operational 10.95 c33 core_clock 11.65 d01 dasl_in_b(0) 9.3 d03 sch_addr(15) 9.91 d05 sch_addr(10) 9.21 d07 sch_data(13) 9.31 d09 d4_addr(08) 8.91 d11 d4_dqs(0) 7.2 d13 d4_data(26) 7.2 d15 d4_data(02) 7.3 d17 d4_data(05) 7 d19 ds1_dqs(2) 7.5 d21 ds1_data(12) 7.5 d23 dc_clk 8.6 d25 dc_ba(0) 9.3 d27 ds0_data(26) 8.7 d29 ds0_data(11) 8.8 d31 dmu_d(01) 10.25 d33 dmu_d(00) 11.55 e02 dasl_in_b(0) 8.5 e03 spare_tst_rcvr(1) 7.81 e04 sch_addr(05) 9.21 e05 sch_addr(18) 8.91 e06 sch_addr(03) 9.81 e07 sch_addr(04) 8.61 e08 sch_data(09) 8.41 e09 d4_data(18) 7.1 e10 d4_cs 8.11 table 224: input capacitance (pf) (continued) (page 12 of 21) t a =25 c, f = 1mhz, v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec14_elec.fm.01 09/25/00 electrical and thermal specifications page 417 of 444 e11 d4_dqs(1) 6.9 e12 d4_data(29) 6.8 e13 d4_data(27) 6.8 e14 d4_data(16) 6.7 e15 d4_data(12) 6.7 e16 ds1_cs 7.61 e17 ds1_addr(03) 7.81 e18 ds1_data(20) 6.4 e19 ds1_data(25) 6.8 e20 ds1_data(22) 6.9 e21 ds1_data(11) 7.1 e22 ds1_data(08) 7.2 e23 dc_clk 8.4 e24 ds0_addr(12) 8.61 e25 ds0_dqs(3) 7.7 e26 ds0_data(27) 7.9 e27 ds0_data(12) 8.1 e28 ds0_data(10) 9.4 e29 blade_reset 9.25 e30 dmu_d(04) 9.55 e31 dmu_d(29) 9.95 e32 dmu_d(12) 10.75 f01 dasl_in_b(2) 8.7 f03 dasl_in_b(2) 7.9 f05 sch_addr(07) 8.61 f07 sch_addr(08) 8.91 f09 sch_data(02) 7.91 f11 d4_we 7.51 f13 d4_data(30) 6.2 f15 d4_data(13) 6.2 f17 ds1_addr(10) 7.31 f19 ds1_data(24) 6.4 f21 ds1_data(07) 6.5 f23 ds1_data(04) 6.8 f25 ds0_dqs(0) 7.3 f27 ds0_data(06) 8.6 table 224: input capacitance (pf) (continued) (page 13 of 21) t a =25 c, f = 1mhz, v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 ibm powernp preliminary electrical and thermal specifications page 418 of 444 np3_dl_sec14_elec.fm.01 09/25/00 f29 dmu_d(07) 8.85 f31 dmu_d(06) 10.25 f33 dmu_d(05) 11.05 g02 dasl_in_b(3) 8 g03 spare_tst_rcvr(5) 7.51 g04 dasl_in_b(3) 7.3 g05 sch_r_wrt 10.01 g06 sch_data(10) 8.81 g07 sch_data(11) 7.91 g08 sch_data(17) 7.81 g09 sch_data(05) 7.71 g10 d4_addr(04) 7.71 g11 dd_cas 7.81 g12 d4_data(22) 6.4 g13 d4_data(08) 6.5 g14 d4_data(07) 6.5 g15 ds1_addr(08) 7.61 g16 ds1_addr(11) 7.61 g17 ds1_addr(09) 7.41 g18 ds1_addr(02) 7.71 g19 ds1_addr(05) 7.71 g20 ds1_data(30) 6 g21 ds1_data(29) 6.1 g22 ds1_data(15) 6.1 g23 ds1_data(01) 6.4 g24 ds0_addr(07) 8.41 g25 ds0_data(30) 7.2 g26 ds0_data(17) 7.3 g27 pci_bus_nm_int 9.65 g28 dmu_d(02) 9.05 g29 dmu_d(11) 10.25 g30 dmu_d(10) 9.55 g31 dmu_d(30) 9.65 g32 dmu_d(08) 10.35 h01 dasl_in_b(1) 8 h07 sch_addr(06) 7.91 table 224: input capacitance (pf) (continued) (page 14 of 21) t a =25 c, f = 1mhz, v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec14_elec.fm.01 09/25/00 electrical and thermal specifications page 419 of 444 h09 d4_data(06) 6.5 h11 d4_addr(03) 7.51 h13 d4_data(23) 6 h15 ds1_addr(07) 7.31 h17 ds1_addr(04) 7.11 h19 ds1_addr(06) 7.41 h21 ds0_data(07) 6.3 h23 ds0_addr(08) 7.91 h25 ds0_data(16) 6.5 h27 dmu_d(16) 8.15 h29 dmu_d(15) 8.95 h31 dmu_d(14) 9.75 h33 dmu_d(13) 10.45 j01 dasl_in_b(4) 7.7 j02 dasl_in_b(1) 7.2 j03 dasl_in_b(4) 6.9 j06 mg_data 7.88 j07 mg_clk 7.28 j08 mg_nintr 6.98 j10 sch_data(16) 7.11 j11 sch_data(03) 7.01 j12 d4_addr(02) 6.91 j13 dd_ba(1) 6.91 j14 d4_data(21) 5.7 j15 ds1_data(17) 5.8 j16 ds1_addr(12) 6.91 j17 dc_ba(1) 6.9 j18 ds1_addr(01) 7.11 j19 ds1_data(31) 6 j20 ds1_data(18) 6 j21 ds1_data(16) 6 j22 ds0_addr(09) 7.21 j23 ds0_we 7.31 j24 ds0_data(18) 6.3 j25 dmu_d(25) 7.15 j26 dmu_d(24) 7.35 table 224: input capacitance (pf) (continued) (page 15 of 21) t a =25 c, f = 1mhz, v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 ibm powernp preliminary electrical and thermal specifications page 420 of 444 np3_dl_sec14_elec.fm.01 09/25/00 j27 dmu_d(23) 8.35 j28 dmu_d(22) 8.85 j29 dmu_d(03) 8.65 j30 dmu_d(20) 9.15 j31 dmu_d(19) 9.35 j32 dmu_d(18) 9.65 j33 dmu_d(17) 10.15 k01 dasl_in_b(5) 7.6 k03 dasl_in_b(5) 6.8 k07 boot_picocode 6.98 k13 dd_ras 6.71 k15 d4_data(09) 5.4 k19 ds1_data(28) 5.6 k21 ds1_data(02) 5.6 k23 ds0_data(19) 5.5 k25 dmu_d(09) 7.15 k27 dmu_d(21) 8.05 k29 dmu_d(28) 8.55 k31 dmu_d(27) 9.25 k33 dmu_d(26) 10.05 l02 dasl_in_b(6) 7 l03 dasl_in_b(6) 6.6 l04 boot_ppc 7.68 l12 sch_data(04) 6.21 l13 d4_addr(05) 6.31 l15 d4_data(20) 5.1 l16 d4_data(01) 5.1 l17 ds1_data(10) 5.2 l18 ds1_data(09) 5.2 l19 ds0_data(25) 5.2 l20 ds1_data(03) 5.3 l22 ds0_data(31) 5.1 l23 dmu_c(10) 6.05 l24 dmu_c(09) 6.75 l25 dmu_c(08) 7.15 l26 dmu_c(07) 7.05 table 224: input capacitance (pf) (continued) (page 16 of 21) t a =25 c, f = 1mhz, v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec14_elec.fm.01 09/25/00 electrical and thermal specifications page 421 of 444 l27 dmu_c(06) 7.25 l28 dmu_c(05) 7.85 l29 dmu_c(04) 8.25 l30 dmu_c(03) 8.95 l31 dmu_c(02) 9.05 l32 dmu_c(01) 9.45 l33 dmu_c(00) 9.95 m03 dasl_in_b(7) 6.4 m07 pci_speed 6.78 m13 d4_addr(10) 6.21 m15 d4_dqs(3) 4.9 m17 d4_data(00) 4.9 m19 ds0_addr(02) 6.31 m21 ds0_data(24) 5 m23 dmu_c(16) 6.15 m25 dmu_c(15) 7.15 m27 dmu_c(14) 7.15 m29 dmu_c(13) 8.35 m31 dmu_c(12) 8.85 m33 dmu_c(11) 9.95 n04 dasl_in_b(7) 5.9 n14 d4_addr(11) 6.11 n15 d4_dqs(2) 5 n16 d4_data(15) 5.1 n17 ds1_addr(00) 6.31 n18 ds1_data(23) 5 n19 dc_cas 6 n20 ds0_addr(01) 6.31 n23 dmu_c(27) 6.15 n24 dmu_c(26) 6.55 n25 dmu_c(25) 7.05 n26 dmu_c(24) 7.25 n27 dmu_c(23) 7.15 n28 dmu_c(22) 7.55 n29 dmu_c(21) 7.85 n30 dmu_c(20) 8.45 table 224: input capacitance (pf) (continued) (page 17 of 21) t a =25 c, f = 1mhz, v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 ibm powernp preliminary electrical and thermal specifications page 422 of 444 np3_dl_sec14_elec.fm.01 09/25/00 n31 dmu_c(19) 8.95 n32 dmu_c(18) 9.55 n33 dmu_c(17) 9.95 p15 d4_data(28) 5.2 p19 ds0_data(00) 5.3 p21 mc_grant_b(1) 5.55 p23 dmu_b(02) 6.15 p25 dmu_b(01) 7.05 p27 dmu_b(00) 7.15 p29 dmu_c(30) 8.15 p31 dmu_c(29) 8.75 p33 dmu_c(28) 9.85 r04 lu_addr(08) 8.01 r05 lu_data(33) 7.51 r07 lu_data(04) 7.21 r08 lu_data(05) 6.81 r17 d4_data(14) 5.6 r18 ds1_dqs(3) 5.6 r20 mc_grant_b(0) 5.65 r21 switch_bna 5.55 r22 dmu_b(18) 5.85 r23 dmu_b(13) 6.15 r24 dmu_b(12) 6.55 r25 dmu_b(11) 6.85 r26 dmu_b(10) 7.15 r27 dmu_b(09) 6.95 r28 dmu_b(08) 7.55 r29 dmu_b(07) 8.15 r30 dmu_b(06) 8.55 r31 dmu_b(05) 8.95 r32 dmu_b(04) 9.45 r33 dmu_b(03) 9.95 t01 spare_tst_rcvr(3) 7.52 t03 spare_tst_rcvr(8) 6.61 t07 lu_data(03) 7.21 t09 lu_data(02) 6.61 table 224: input capacitance (pf) (continued) (page 18 of 21) t a =25 c, f = 1mhz, v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec14_elec.fm.01 09/25/00 electrical and thermal specifications page 423 of 444 t15 lu_data(24) 7.21 t19 send_grant_b 5.95 t21 res_data 5.55 t23 dmu_b(19) 6.15 t25 jtag_trst 6.85 t27 dmu_b(17) 6.95 t29 dmu_b(16) 7.65 t31 dmu_b(15) 8.95 t33 dmu_b(14) 9.75 u01 lu_data(30) 9.41 u03 lu_data(35) 8.11 u05 spare_tst_rcvr(0) 5.47 u06 testmode(1) 5.78 u08 lu_data(08) 6.61 u10 lu_data(34) 6.21 u12 lu_data(11) 6.11 u13 lu_data(01) 6.41 u15 lu_data(00) 7.11 u19 mgrant_a(1) 5.95 u21 res_sync 5.55 u22 jtag_tms 5.75 u23 rx_lbyte(0) 6.15 u24 dmu_b(29) 6.55 u25 dmu_b(28) 6.85 u26 dmu_b(27) 6.95 u27 dmu_b(26) 7.25 u28 dmu_b(25) 7.25 u29 dmu_b(24) 7.85 u30 dmu_b(23) 8.15 u31 dmu_b(22) 8.75 u32 dmu_b(21) 9.45 u33 spare_tst_rcvr(9) 8.12 v01 spare_tst_rcvr(6) 7.51 v03 spare_tst_rcvr(7) 6.58 v05 testmode(0) 5.98 v07 lu_data(09) 7.21 table 224: input capacitance (pf) (continued) (page 19 of 21) t a =25 c, f = 1mhz, v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 ibm powernp preliminary electrical and thermal specifications page 424 of 444 np3_dl_sec14_elec.fm.01 09/25/00 v09 lu_data(10) 6.61 v11 lu_data(14) 5.91 v13 lu_data(18) 6.41 v15 lu_data(12) 7.21 v19 mgrant_a(0) 5.95 v21 i_freeq_th 5.55 v23 rx_lbyte(1) 6.15 v25 dmu_b(20) 6.85 v27 dmu_a(02) 6.95 v29 dmu_a(01) 7.65 v31 dmu_a(00) 8.95 v33 dmu_b(30) 9.75 w01 lu_data(20) 9.41 w04 lu_data(13) 8.01 w05 lu_data(07) 7.51 w06 lu_data(06) 7.71 w07 lu_data(15) 7.21 w08 lu_data(16) 6.81 w09 lu_data(21) 6.51 w10 lu_data(25) 6.31 w11 lu_data(31) 5.81 w12 lu_data(26) 6.01 w13 lu_data(19) 6.41 w14 lu_data(27) 6.81 w16 d1_addr(10) 6.91 w17 d3_data(08) 5.7 w18 d2_data(02) 5.6 w20 send_grant_a 5.65 w21 mc_grant_a(1) 5.55 w22 jtag_tdi 5.85 w23 dmu_a(13) 6.15 w24 dmu_a(12) 6.55 w25 dmu_a(11) 6.85 w26 dmu_a(10) 7.15 w27 dmu_a(09) 6.95 w28 dmu_a(08) 7.55 table 224: input capacitance (pf) (continued) (page 20 of 21) t a =25 c, f = 1mhz, v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec14_elec.fm.01 09/25/00 electrical and thermal specifications page 425 of 444 w29 dmu_a(07) 8.15 w30 dmu_a(06) 8.55 w31 dmu_a(05) 8.95 w32 dmu_a(04) 9.45 w33 dmu_a(03) 9.95 y03 dasl_in_a(7) 6.2 y05 lu_data(32) 7.51 y07 lu_data(17) 7.41 y09 lu_data(22) 6.81 y11 lu_addr(01) 5.81 y15 d1_data(05) 5.2 y19 d2_data(15) 5.3 y21 mc_grant_a(0) 5.55 y23 dmu_a(19) 6.15 y25 dmu_a(18) 6.95 y27 dmu_a(17) 7.15 y29 dmu_a(16) 8.15 y31 dmu_a(15) 8.75 y33 dmu_a(14) 9.85 table 224: input capacitance (pf) (continued) (page 21 of 21) t a =25 c, f = 1mhz, v dd =3.3v 0.3v) grid position signal name total incap IBM32NPR161EPXCAC133 ibm powernp preliminary electrical and thermal specifications page 426 of 444 np3_dl_sec14_elec.fm.01 09/25/00 14.1 driver specifications table 225: operating supply voltages symbol parameter rating units notes min typ max v dd25 v dd 2.5 v power supply 2.375 2.5 2.625 v 1 v dd33 v dd2 v dd3 v dd5 3.3 v power supply 3.135 3.3 3.465 v 1 v dd18 v dd4 1.8 v power supply 1.71 1.8 1.89 v 1 plla_v dd pllb_v dd pllc_v dd pll voltage reference 1.71 1.8 1.89 v 1, 1 v refr1(2-0) v refr2(8-0) sstl2 power supply (used for sstl2 i/o) 1.1875 1.25 1.3125 v 1 1. important power sequencing requirements: (the following conditions must be met at all times, including power-up and power- down: v ref *(1.25 v reference) v dd25 +0.4 v pll*_v dd (2.5 v reference) v dd33 +0.4 v v dd15 v dd25 +0.4v v dd25 v dd33 +0.4 v v dd33 v dd25 +1.9v 1. see also pll filter circuit on page 65. table 226: thermal characteristics thermal characteristic min nominal max units estimated power dissipation tbd tbd tbd c operating junction temperature (tj) 0 105 c table 227: definition of terms term definition maul maximum allowable up level. the maximum voltage that can be applied without affecting the specified reliability. cell functionality is not implied. maximum allowable applies to overshoot only. mpul maximum positive up level. the most positive voltage that maintains cell functionality. the maximum positive logic level. lpul least positive up level. the least positive voltage that maintains cell functionality. the minimum positive logic level. mpdl most positive down level. the most positive voltage that maintains cell functionality. the maximum negative logic level. lpdl least positive down level. the least positive voltage that maintains cell functionality. the minimum negative logic level. madl minimum allowable down level. the minimum voltage that can be applied without affecting the specified reliability. mini- mum allowable applies to undershoot only. cell functionality is not implied. IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec14_elec.fm.01 09/25/00 electrical and thermal specifications page 427 of 444 table 228: 1.8 v cmos driver dc voltage specifications function maul (v) 1 mpul (v) lpul (v) mpdl (v) lpdl (v) madl (v) 2 cmos v dd 3 +0.45 v dd 3 v dd 3 - 0.45 0.45 0.00 -0.60 1. maximum allowable applies to overshoot only. 2. minimum allowable applies to undershoot only. 3. v dd ranges as specified in table 225 (typical = 1.8 v). table 229: 1.8 v cmos driver minimum dc currents at rated voltage v dd = 1.65 v, t = 100c driver type v high (v) i high (ma) v low (v) i low (ma) cmos 50 ohm driver outputs 1.2 8.0/23.0 1 0.45 7.8 1 1. 23 ma is the electromigration limit for 100k power on hours (poh) = 100 c and 100% duty cycle. this limit can be adjusted for dif- ferent temperature, duty cycle, and poh. consult your ibm application engineer for further details . table 230: 2.5 v cmos driver dc voltage specifications function maul (v) 1 mpul (v) lpul (v) mpdl (v) lpdl (v) madl (v) 2 cmos v dd 3 +0.6 v dd 3 2.0 0.4 0.00 -0.60 1. maximum allowable applies to overshoot only. 2. minimum allowable applies to undershoot only. 3. v dd ranges as specified in table 225 (typical = 2.5 v). table 231: 2.5 v cmos driver minimum dc currents at rated voltage v dd =2.3v,t=100c driver type v high (v) i high (ma) v low (v) i low (ma) cmos 50 ohm driver outputs 2.0 5.2/23 1 0.4 6.9 1 1. 23 ma is the electromigration limit for 100k power on hours (poh) = 100 c and 100% duty cycle. this limit can be adjusted for dif- ferent temperature, duty cycle, and poh. consult your ibm application engineer for further details . table 232: 3.3 v-tolerant 2.5 v cmos driver dc voltage specifications (see note 1) function maul (v) 2 mpul (v) 3 lpul (v) mpdl (v) lpdl (v) madl (v) 4 lvttl 3.9 v dd 5 2.0 0.4 0.00 -0.60 1. all levels adhere to the jedec standard jesd12-6, ?interface standard for semi-custom integrated circuits,? march 1991. 2. maximum allowable applies to overshoot only. output disabled. 3. output active. 4. minimum allowable applies to undershoot only. 5. v dd ranges as specified in table 225 (typical = 2.5 v). IBM32NPR161EPXCAC133 ibm powernp preliminary electrical and thermal specifications page 428 of 444 np3_dl_sec14_elec.fm.01 09/25/00 14.2 receiver specifications table 233: 3.3 v lvttl driver dc voltage specifications function maul (v) 1 mpul (v) lpul (v) mpdl (v) lpdl (v) madl (v) 2 lvttl v dd330 3 +0.3 v dd330 3 2.4 0.4 0.00 -0.60 1. maximum allowable applies to overshoot only. 2. minimum allowable applies to undershoot only. 3. v dd 33 ranges as specified in table 225 (typical = 3.3 v). table 234: 3.3 v lvttl/5.0 v-tolerant driver dc voltage specifications function maul (v) 1 mpul (v) lpul (v) mpdl (v) lpdl (v) madl (v) 2 lvttl v dd330 3 +0.3 v dd330 3 2.4 0.4 0.00 -0.60 1. maximum allowable applies to overshoot only. 2. minimum allowable applies to undershoot only. 3. v dd 33 ranges as specified in table 225 (typical = 3.3 v). table 235: 3.3 v lvttl driver minimum dc currents at rated voltage (v dd =3.0v,t=100c) driver type v high (v) i high (ma) v low (v) i low (ma) lvttl 50 ohm driver outputs 2.40 10.3/23 1 0.4 7.1 1 1. 23 ma is the electromigration limit for 100k power on hours (poh) = 100c and 100% duty cycle. this limit can be adjusted for dif- ferent temperature, duty cycle, and poh. consult your ibm application engineer for further details. table 236: 1.8 v cmos receiver dc voltage specifications function maul (v) 1 mpul (v) lpul (v) mpdl (v) lpdl (v) madl (v) 2 cmos v dd 3 +0.45 v dd 3 0.65v dd 3 0.35v dd 3 0.00 -0.60 1. maximum allowable applies to overshoot only. 2. minimum allowable applies to undershoot only. 3. v dd ranges as specified in table 225 (typical = 1.8 v). table 237: 2.5 v cmos receiver dc voltage specifications function maul (v) 1 mpul (v) lpul (v) mpdl (v) lpdl (v) madl (v) 2 cmos v dd 3 +0.6 v dd 1.7 0.70 0.00 -0.60 1. maximum allowable applies to overshoot only. 2. minimum allowable applies to undershoot only. 3. v dd ranges as specified in table 225 (typical = 2.5 v). IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec14_elec.fm.01 09/25/00 electrical and thermal specifications page 429 of 444 table 238: 3.3 v lvttl receiver dc voltage specifications function maul (v) 1 mpul (v) lpul (v) mpdl (v) lpdl (v) madl (v) 2 lvttl v dd330 3 +0.3 v dd330 3 2.00 0.80 0.00 -0.60 1. maximum allowable applies to overshoot only. 2. minimum allowable applies to undershoot only. 3. v dd 33 ranges as specified in table 225 (typical = 3.3 v). table 239: 3.3 v lvttl/5v-tolerant receiver dc voltage specifications function maul (v) 1 mpul (v) lpul (v) mpdl (v) lpdl (v) madl (v) 2 lvttl 5.5 v 5.5 v 2.00 0.80 0.00 -0.60 1. maximum allowable applies to overshoot only. 2. minimum allowable applies to undershoot only. table 240: receiver maximum input leakage dc current input specifications function i il ( a) i ih ( a) without pull-up element or pull-down element 0 at v in =lpdl 0atv in =mpul with pull-down element 0 at v in =lpdl 200atv in =mpul with pull-up element -150 at v in =lpdl 0atv in =mpul 1. see section 3.3v lvttl/5v tolerant bp33 and ip33 receiver input current/voltage curve on page 429 . figure 75: 3.3v lvttl/5v tolerant bp33 and ip33 receiver input current/voltage curve 1. curve shows best case process - 0c, 3.6v 0.00 - 50.00 -100.00 -150.00 -200.00 -250.00 -300.00 0.00 0.50 1.00 1.50 2.50 3.00 i pad ( a) v pad (v) 2.00 IBM32NPR161EPXCAC133 ibm powernp preliminary electrical and thermal specifications page 430 of 444 np3_dl_sec14_elec.fm.01 09/25/00 14.3 other driver and receiver specifications table 241: lvds receiver dc specifications symbol parameter min nom max units comments v dd device supply voltage 1.65 1.8 1.95 v receiver uses only v dd supply. temp temperature range 0 50 100 c rec pwr input buffer power 9.3 mw including on-chip terminator v pad - v padn =0.4v v ih receiver input voltage v dd + 0.20 v receiver esd connected to v dd v il receiver input voltage -0.20 v v ih - v il receiver input voltage range 100 mv @600 mhz v icm receiver common mode range 0 1.25 v dd v notes: 1. all dc characteristics are based on power supply and temperature ranges as specified above. 2. lvds design reference: ieee standard for low-voltage differential signals (lvds) for scalable coherent interface (sci), ieee standard 1596.3,1996. 3. maximum frequency is load and package dependent. 600 mhz (1.2 gbps) is achievable with a minimum of 100 mv input swing over the wide common range as specified. the customer is responsible for determining optimal frequency and switching capabilities through thorough simulation and analysis. table 242: sstl2 dc specifications symbol parameter min nom max units comments v dd device supply voltage 1.65 1.8 1.95 v v ddq output supply voltage 2.3 2.5 2.7 v v ddq =v dd250 v tt termination voltage 1.11 - 1.19 1.25 1.31 - 1.39 v 0.5*v ddq v ref differential input reference voltage 1.15 1.25 1.35 v 0.5*v ddq v oh (class ii) output high voltage 1.95 v i oh = 15.2 ma @ 1.95v v ol (class ii) output low voltage 0.55 v i ol = 15.2 ma @ 0.55v r oh max (class ii) max pull-up impedance 36.2 ? notes: 1. all sstl2 specifications are consistent with jedec committee re-ballot (jc-16-97-58a), 10/14/97. 2. di/dt and performance are chosen by performance level selection (a and b). a. performance level a is targeted to run at 200 mhz or faster depending on loading conditions. di/dt is comparable to 110 ma/ns 2.5 v/3.3 v lvttl driver. b. performance level b is targeted to run at 250 mhz or faster depending on loading conditions. di/dt is comparable to 150 ma/ns 2.5 v/3.3 v lvttl driver. 3. the differential input reference supply (v ref ) is brought on chip through vsstl2r1 and vsstl2r2 i/o cells. 4. termination voltage (v tt ) is generated off chip. 5. sstl2 driver is rated at 20 ma @100c and 50% duty cycle for 100k power on hours (poh). IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec14_elec.fm.01 09/25/00 electrical and thermal specifications page 431 of 444 r ol max (class ii) max pull-down impedance 36.2 ? v ih input high voltage v ref +0.18 v ddq +0.3 v v il input low voltage -0.3 v ref -0.18 v i oz 3-state leakage current 010 adriverhi-z temp temperature 0 50 100 c table 242: sstl2 dc specifications symbol parameter min nom max units comments notes: 1. all sstl2 specifications are consistent with jedec committee re-ballot (jc-16-97-58a), 10/14/97. 2. di/dt and performance are chosen by performance level selection (a and b). a. performance level a is targeted to run at 200 mhz or faster depending on loading conditions. di/dt is comparable to 110 ma/ns 2.5 v/3.3 v lvttl driver. b. performance level b is targeted to run at 250 mhz or faster depending on loading conditions. di/dt is comparable to 150 ma/ns 2.5 v/3.3 v lvttl driver. 3. the differential input reference supply (v ref ) is brought on chip through vsstl2r1 and vsstl2r2 i/o cells. 4. termination voltage (v tt ) is generated off chip. 5. sstl2 driver is rated at 20 ma @100c and 50% duty cycle for 100k power on hours (poh). IBM32NPR161EPXCAC133 ibm powernp preliminary electrical and thermal specifications page 432 of 444 np3_dl_sec14_elec.fm.01 09/25/00 IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec15_glos.fm.01 09/25/00 glossary of terms and abbreviations page 433 of 444 15. glossary of terms and abbreviations term definition alu arithmetic and logic unit api application programming interface arb arbitration ardl advance rope with optional delete leaf arp address resolution protocol ath actual threshold bcb buffer control block bci byte count information beb binary exponential back-off bfq buffer free queue bgp border gateway protocol bird an intermediate leaf. it occurs when the pscbline contains an intermediate lcba pointing to this leaf and an npa pointing to the next pscb. bl burst length bsm-ccga bottom surface metallurgy - ceramic column grid array byte 8 bits cab control access bus chap challenge-handshake authentication protocol cia common instruction address clns connectionless-mode network service clp see core language processor core language processor (clp) the picoprocessor core, also referred to as coprocessor 0. the clp executes the base instruction set and controls thread swapping and instruction fetching. cp control point cpf control point function cpix common programming interface crc see cyclic redundancy check cs control store IBM32NPR161EPXCAC133 ibm powernp preliminary glossary of terms and abbreviations page 434 of 444 np3_dl_sec15_glos.fm.01 09/25/00 csa control store arbiter cyclic redundancy check (crc) a system of error checking performed at both the sending and receiving station after a block-check character has been accumulated. da destination address dasl data-aligned synchronous link data store in the network processor, the place where a frame is stored while waiting for processing or forwarding to its destination. dbgs debug services ddr double data rate diffserv differentiated services distinguishing position (distpos) the index value of a first mismatch bit between the input key and the reference key found in a leaf pattern distpos see distinguishing position (distpos) dlq discard list queue dmu data mover unit doubleword 2 words dppu dyadic protocol processor unit dq discard queue dram dynamic random-access memory ds see data store dscp diffserv code point dsi distributed software interface dt direct table dvmrp distance vector multicast routing protocol e- egress ecc error correcting code ecmp equal-cost multipath eds enqueuer / dequeuer / scheduler e-ds egress data store term definition IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec15_glos.fm.01 09/25/00 glossary of terms and abbreviations page 435 of 444 e-gdq discard queue stack. holds frames that need to be discarded. this is used by the hardware to discard frames when the egress ds is congested or to re-walk a frame marked for discard for a half duplex port. used by the picocode to discard frames that do not have header twins allocated. egress eds egress enqueuer / dequeuer / scheduler enet mac ethernet mac eof end of frame epc embedded processor complex e-pmm egress-physical mac multiplexer ewma exponentially weighted moving average exponentially weighted average see exponentially weighted moving average exponentially weighted moving average a method of smoothing a sequence of instantaneous measurements. typically, the average a(t) at time t is combined with the measurement m(t) at time t to yield the next average value: a(t+dt) = w*m(t)+(1-w)*a(t) here weight w is a number with 0 < w <= 1. if the weight is 1, then the average is just the previous value of the measurement and no smoothing occurs. else previous values of m contribute to the current value of a with more recent m val- ues being more influential. fcb frame control block ffa flexible frame alternation fhe frame header extension fhf frame header format fm full match fpga field-programmable gate array fta first twin-buffer address gdh see general data handler . general data handler (gdh) a type of thread used to forward frames in the epc. there are 28 gdh threads. general powerpc handler request (gph-req) a type of thread in the epc that processes frames bound to the embedded powerpc. work for this thread is usually the result of a reenqueue action to the ppc queue (it processes data frames when there are no entries to process in the ppc queue). term definition IBM32NPR161EPXCAC133 ibm powernp preliminary glossary of terms and abbreviations page 436 of 444 np3_dl_sec15_glos.fm.01 09/25/00 general powerpc handler response (gph-resp) a type of thread in the epc that processes responses from the embedded powerpc. work for this thread is dispatched due to an interrupt and does not use dispatcher memory. general table handler (gth) the gth executes commands not available to a gdh or gfh thread, including hardware assist to perform tree inserts, tree deletes, tree aging, and rope man- agement. it processes data frames when there are no tree management func- tions to perform. gfh see guided frame handler . gfq guided frame queue gmii gigabit medium independent interface gph-req see general powerpc handler request . gph-resp see general powerpc handler response . gpp general-purpose processor gpq powerpc queue. the queue that contains frames re-enqueued for delivery to the gph for processing. gpr general-purpose register gth see general table handler . gui graphical user interface guided frame handler (gfh) there is one gfh thread available in the epc. a guided frame can be pro- cessed only by the gfh thread, but it can be configured to enable it to process data frames like a gdh thread. the gfh executes guided frame-related pico- code, runs chip management-related picocode, and exchanges control informa- tion with a control point function or a remote network processor. when there is no such task to perform and the option is enabled, the gfh can execute frame forwarding-related picocode. gxh generalized reference to any of the defined threads of the epc halfword 2 bytes hc hardware classifier hdlc see high-level data link control . high-level data link control (hdlc) in data communication, the use of a specified series of bits to control data links in accordance with the international standards for hdlc: iso 3309 frame structure and iso 4335 elements of procedures. i- ingress icmp internet control message protocol term definition IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec15_glos.fm.01 09/25/00 glossary of terms and abbreviations page 437 of 444 i-ds ingress data store ingress eds ingress enqueuer / dequeuer / scheduler ingress gdq ingress general data queue ims interface manager services ipc interprocess communication i-pmm ingress-physical mac multiplexer ipps internet protocol version 4 protocol services ipv4 internet protocol version 4 i-sdm ingress switch data mover k2 10 , or 1024 in decimal notation lcba leaf control block address ldp label distribution protocol leaf a control block that contains the corresponding key as a reference pattern and other user data such as target blade number, qos, and so on. lh latched high (a characteristic of a register or a bit in a register (facility)). when an operational condition sets the facility to a value of 1, the changes to the oper- ational condition do not affect the state of the facility until the facility is read. lid lookup identifier ll latched low (a characteristic of a register or a bit in a register (facility)). when an operational condition sets the facility to a value of 0, the changes to the oper- ational condition do not affect the state of the facility until the facility is read. lls low-latency sustainable bandwidth lpm longest prefix match lsb least significant bit lsb least significant byte lsp label-switched path ludef lookup definition m 2 20 , or 1 048 576 in decimal notation mac medium access control term definition IBM32NPR161EPXCAC133 ibm powernp preliminary glossary of terms and abbreviations page 438 of 444 np3_dl_sec15_glos.fm.01 09/25/00 management information base (mib) in osi, the conceptual repository of management information within an open system. maximum burst size (mbs) in the network processor egress scheduler, the duration a flow can exceed its guaranteed minimum bandwidth before it is constrained to its guaranteed mini- mum bandwidth. maximum transmission unit (mtu) in lans, the largest possible unit of data that can be sent on a given physical medium in a single frame. for example, the mtu for ethernet is 1500 bytes. mbs see maximum burst size mcc multicast count mcca multicast count address mh mid handler mib see management information base mid multicast id mm mid manager mms mid manager services mpls multiprotocol label switching mpps million packets per second msb most significant bit msb most significant byte msc message sequence charts mtu see maximum transmission unit my_tb my target blade nbt next bit to test nfa next frame control block (fcb) address nla next leaf address nls normal latency sustainable bandwidth np network processor npa next pcsb address pointer npasm ibm network processor assembler term definition IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec15_glos.fm.01 09/25/00 glossary of terms and abbreviations page 439 of 444 npdd network processor device driver npddis network processor device driver initialization services npms network processor manager services npscope ibm network processor debugger npsim ibm network processor simulator nptest ibm network processor test case generator ns nanosecond nta next twin-buffer address oqg output queue grant pap password authentication protocol pbs peak bandwidth service pc program counter pcb port control block pcs physical coding sublayer pct port configuration table phy see physical layer . may also refer to a physical layer device. physical layer in the open systems interconnection reference model, the layer that provides the mechanical, electrical, functional, and procedural means to establish, main- tain, and release physical connections over the transmission medium. (t) plb processor local bus pll phased lock loop pma physical medium attachment pmm physical mac multiplexer polcb policing control block pos packet over sonet post power-on self-test postcondition an action or series of actions that the user program or the npdd must perform after the function has been called and completed. for example, when the func- tion that defines a table in the npdd has been completed, the npdd must dis- patch a guided frame from the powerpc core to instruct one or more epcs to define the table. term definition IBM32NPR161EPXCAC133 ibm powernp preliminary glossary of terms and abbreviations page 440 of 444 np3_dl_sec15_glos.fm.01 09/25/00 ppc powerpc ppp point-to-point protocol pprev previous discard probability precondition a requirement that must be met before the user program calls the api function. for example, a precondition exists if the user program must call one function and allow it to be completed before a second function is called. one function that has a precondition is the function that deregisters the user program. the user program must call the register function to obtain a user_handle before calling the deregistering function. pscb pattern search control block ptl physical transport layer pts physical transport services quadword 4 words quality of service (qos) for a network connection, a set of communication characteristics such as end- to-end delay, jitter, and packet loss ratio. qcb queue control block qos see quality of service rbuf raw buffer rcb reassembly control block rclr read current leaf from rope red random early detection rmon remote network monitoring rpc remote procedure call rtp real-time transport protocol rum access type ?reset under mask? r/w access type ?read/write? rwr access type ?read with reset? sa source address sap service access point sc self clearing (a characteristic of a register or a bit in a register (facility)). when written to a value of 1, will automatically reset to a value of 0 when the indicated operation completes. term definition IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec15_glos.fm.01 09/25/00 glossary of terms and abbreviations page 441 of 444 scb schedule control block sci switch cell interface sdc shared dasl controller sdm switchdatamover smt software-managed tree smii serial media-independent interface sof start-of-frame sonet synchronous optical network spm serial/parallel manager sram static random-access memory ss system services sum access type ?set under mask? swi switch interface target blade grant (tbg) an internal facility used by the ingress scheduler to determine which target blades are accepting data transfer. derived from the output queue grant (oqg) information the network processor receives. tb target blade tbg see target blade grant . tbr target blade running tb_sof target blade start-of-frame tcp transmission control protocol thread a stream of picocode instructions that utilizes a private set of registers and shared computational resources within a dppu. in the network processor, a dppu provides both shared and private resources for four threads. two threads are bound to a single picoprocessor, allowing for concurrent execution of two threads within a dppu. the coprocessors are designed to support all four threads. in general, the computational resources (alu, hardware-assist state machines, and so on) are shared among the threads. the private resources provided by each picoprocessor or coprocessor include the register set that makes up its architecture (gprs, program counters, link stacks, data pool, and so on). tlir tree leaf insert rope term definition IBM32NPR161EPXCAC133 ibm powernp preliminary glossary of terms and abbreviations page 442 of 444 np3_dl_sec15_glos.fm.01 09/25/00 tlv type length vectors tms table management services tp target port tsdqfl tree search dequeue free list ts transport services tse tree search engine tsenqfl tree search enqueue free list tsfl_id tree search free list identifier tsr tree search result ttl time to live uc unicast udp user datagram protocol wfq weighted fair queueing word 4 bytes zbt zero bus turnaround term definition IBM32NPR161EPXCAC133 preliminary ibm powernp np3_dl_sec15_glos.fm.01 09/25/00 revision log page 443 of 444 revision log rev description of modification 11/11/99 initial release of databook for IBM32NPR161EPXCAC133 (revision 00), follow-up document to datasheet for ibmnpr100exxcab133 and IBM32NPR161EPXCAC133 (revision 01, 11/08/99) 09/25/00 release IBM32NPR161EPXCAC133 databook (revision 01), including revisions to all sections. IBM32NPR161EPXCAC133 ibm powernp preliminary revision log page 444 of 444 np3_dl_sec15_glos.fm.01 09/25/00 |
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