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c9631 low emi 166mhz clock generator for sis630s/pentium ? iii/celeron ? chipsets advanced information imi confidential international microcircuits, inc. 525 los coches st. rev 0.7 4/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 1 of 18 http://www.imicorp.com product features 166mhz clock support supports pentium ? iii and celeron cpus designed to sis630s chipset requirements 3 cpu clocks 13 sdram clocks (3 dimm support) 6 pci clocks, one free running 2 agp clocks 2 ref clocks (1x or 2x strength via i2c) 1 48mhz usb clock (non ssc) 1 programmable sio 24mhz/ 48mhz (non ssc) imi spread spectrum for best emi reduction i 2 c support with read back capabilities dial-a-frequency ? feature dial-a-db? feature 48 pin ssop package block diagram frequency table (mhz) agp(0,1) sel (3:0)* cpu (0:2) sdram (0:12) pci (_f, 1:5) ref (0:1) agp_sel=0 agp_sel=1 0000 66.80 66.80 33.40 14.318 66.80 50.10 0001 100.20 100.20 33.40 14.318 66.80 50.10 0010 166.67 166.67 33.33 14.318 66.67 55.56 0011 133.50 133.50 33.38 14.318 66.75 53.40 0100 66.80 100.20 33.40 14.318 66.80 50.10 0101 100.20 66.80 33.40 14.318 66.80 50.10 0110 100.20 133.60 33.40 14.318 66.80 50.10 0111 133.60 100.20 33.40 14.318 66.80 50.10 1000 112.00 112.00 33.60 14.318 67.20 56.00 1001 124.00 124.00 31.00 14.318 62.00 49.60 1010 138.00 138.00 34.50 14.318 69.00 50.18 1011 150.00 150.00 33.33 14.318 66.67 50.00 1100 66.80 133.60 33.40 14.318 66.80 50.10 1101 100.00 150.00 33.33 14.318 66.67 50.00 1110 150.00 100.00 33.33 14.318 66.67 50.00 1111 160.00 120.00 30.00 14.318 60.00 60.00 table 1 * can also be programmed via i 2 c interface. pin configuration vdd vdd vdds vdd vdd xin xout agp_sel/ref1 sel3/ref0 sdram(0:7, 12) sel0/48m pm_sel/24m_48m sdata sclk pll1 rin s1 s0 sdata sclk cpu sdram pci s3 s2 pll2 rin 48 i2c-clk i2c-data 24 or 48 1 1 30pf 300k 30pf vddc 3 cpu(0:2) 9 vddp pci(2:5) 4 vddp sel1/pci_f 1 1 vddp sel2/pci1 1 1 pd#/sdram8 sdr_stp#/sdram9 1 1 1 1 pci_stp#/sdram10 cpu_stp#/sdram11 sdram pd# sdram sdr_stp# sdram pci_stp# sdram cpu_stp# agp_sel vdd agp (0,1) 2 agp pm_sel vdd agp_sel/ref1 sel3/ref0 vss xin xou t vddp sel1/pci_f sel2/pci1 pci2 pci3 pci4 pci5 vss vdd agp0 agp1 vss vss sel0/48m pm_sel/24m_48m vdd48 sdat a scl k vddc cpu0 cpu1 cpu2 vss vdds sdram0 sdram1 sdram2 vss sdram3 sdram4 sdram5 vdds sdram6 sdram7 vss pd#/sdram8 sdr_stp#/sdram9 vss pci_stp#/sdram10 cpu_stp#/sdram11 sdram12 vdds 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
c9631 low emi 166mhz clock generator for sis630s/pentium ? iii/celeron ? chipsets advanced information imi confidential international microcircuits, inc. 525 los coches st. rev 0.7 4/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 2 of 18 http://www.imicorp.com pin description pin name pwr i/o type description 5 xin vdd i oscillator buffer input. connect to a crystal or to an external clock. 6 xout vdd o oscillator buffer output. connect to a crystal. do not connect when an external clock is applied at xin. 2 agp_sel/ref1 vdd i/o pd power-on bi-directional input / output. at power-up, agp_sel is the input. when the power supply voltage exceeds the input buffer threshold voltage, ref1 becomes the buffered output of xin. agp-sel selects the agp(0,1) output frequency. see frequency table. ref1 is the buffered output of xin. select 1x or 2x strength via i2c byte6 bit 7. default is 1x. 20 sel0/48m vdd i/o pd power-on bi-directional input / output. at power-up, sel0 is the input. when the power supply voltage exceeds the input buffer threshold voltage, 48m becomes the output. see frequency table for sel0 selections. 48m is a 48mhz clock output. 8 sel1/pci_f vdd i/o pd power-on bi-directional input / output. at power-up, sel1 is the input. when the power supply voltage exceeds the input buffer threshold voltage, pci_f becomes the free running pci clock output. see frequency table for sel1 selections. pci_f is the free running pci clock. this clock is not affected by pci_stp#. 9 sel2/pci1 vdd i/o pd power-on bi-directional input / output. at power-up, sel2 is the input. when the power supply voltage exceeds the input buffer threshold voltage, pci1 becomes the output. see frequency table for sel2 selections. 3 sel3/ref0 vdd i/o pd power-on bi-directional input / output. at power-up, sel3 is the input. when the power supply voltage exceeds the input buffer threshold voltage, ref0 becomes the buffered output of xin. see frequency table for sel3 selections. ref0 is the buffered output of xin. select 1x or 2x strength via i2c byte6 bit 7. default is 1x. 21 pm_sel/24m_48m vdd i/o pd power-on bi-directional input / output. at power-up, pm_sel is the input. when the power supply voltage exceeds the input buffer threshold voltage, 24m_48m becomes the output. if pm_sel = 0, then pins 27,28,30,31 are sdram clocks. if pm_sel = 1, then pins 27,28,30,31 are power management pins. 24m_48m is sio/usb clock output. it is programmable to 24mhz or 48mhz clock output. default is 24mhz, but also provide 48mhz by programming i 2 c.
c9631 low emi 166mhz clock generator for sis630s/pentium ? iii/celeron ? chipsets advanced information imi confidential international microcircuits, inc. 525 los coches st. rev 0.7 4/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 3 of 18 http://www.imicorp.com pin description (cont.) pin name pwr i/o type description 27 cpu_stp#/ sdram11 vdd i/o pu bi-directional input / output. if pm_sel = 0, then sdram11 is the output. if pm_sel = 1, then cpu_stp# is the input. when cpu_stp# = 0, cpu clock is stopped. 28 pci_stp#/ sdram10 vdd i/o pu bi-directional input / output. if pm_sel = 0, then sdram10 is the output. if pm_sel = 1, then pci_stp# is the input. when pci_stp# = 0, then pci(1:5) clock outputs are set low. 30 sdr_stp#/ sdram9 vdd i/o pu bi-directional input / output. if pm_sel = 0, then sdram9 is the output. if pm_sel =1, then sdr_stp# is the input. when sdr_stp# = 0, then sdram(0:12) clock outputs are set low. 31 pd#/sdram8 vdd i/o pu bi-directional input / output. if pm_sel = 0, then sdram8 is the output. if pm_sel = 1, then pd# is the input. when pd# = 0, then all clock outputs are set low. 23 sdata i serial data input. conforms to the philips i 2 c specification of a slave receive/transmit device. it is an input when receiving data. it is an open drain output when acknowledging or transmitting data. 24 sclk i serial clock input. conforms to the philips i 2 c specification. 46, 47 cpu(1,0) vddc o host clock outputs. see frequency table. 45 cpu2 vddc o cpu clock output. this clock is used for the chipset. see frequency table. 26, 33, 34, 36, 37, 38, 40, 41, 42 sdram (12, 7:0) vdds o sdram clock outputs. are synchronous to cpu clocks. see frequency table. 10, 11, 12, 13 pci(2:5) vddp o pci clock outputs. are synchronous to cpu clocks. see frequency table. 16, 17 agp(0,1) vdd o agp clock outputs. are synchronous to cpu clocks. see frequency table 48 vddc 2.5v power supply for cpu(0:2). 25, 35, 43 vdds 3.3v power supply for sdram(0:12) 7 vddp 3.3v power supply for pci(_f, 1:5) 22 vdd48 3.3v power supply for 48m_usb, 24mhz-48mhz output. 1, 15 vdd 3.3v common power supply 4, 14, 18, 19, 29, 32, 39, 44 vss common ground a bypass capacitor (0.1 m f) should be placed as close as possible to each positive power pin. if these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces. pu = internal pull-up. pd = internal pull-down. typically 120k (70k to 170k).
c9631 low emi 166mhz clock generator for sis630s/pentium ? iii/celeron ? chipsets advanced information imi confidential international microcircuits, inc. 525 los coches st. rev 0.7 4/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 4 of 18 http://www.imicorp.com device clock phase relationships figure 1 frequency smooth switching groups group ext, sel(3:0) (byte 0, bits 2, 7, 6, 5, 4) 1 00000, 00100, 01100, 01100, 10101 2 00001, 00101, 00110, 10001, 10011, 10100, 10110, 11000, 11001 3 00010, 01011, 01110, 10010, 11111 4 00011, 00111, 01000, 01001, 01010, 01101, 01111, 10010, 10111, 11010, 11011, 11100, 11101, 11110 table 2 table 2 above describes 4 different groups of frequencies. within the same group, frequency may be switched through i2c byte 0 without causing any glitching or clock discontinuity at the cpu(0:2) outputs, therefore allowing frequency smooth switching of the clock. switching frequency from one group to another is permitted but will cause the cpu(0:2) clocks to jump immediately to the next frequency. (non smooth switching.). internal vco sdram to cpu or cpu to sdram condition 1: cpu frequency = sdram frequency tskew4 ext, sel(3:0) = 00000, 00001, 00010, 00011, 01000, 01001, 01010, 01011,10001, 10111, 11010, 11011, 11100, 11101, 11110, 11111 internal vco tskew4 ext, sel(3:0) = 00100, 00101, 01101, 01110, 10000, 10010, 10101 condition 2: cpu frequency = 1.5 x sdram fre q uenc y or sdram fre q uenc y = 1.5 x cpu frequency or cpu sdram to cpu to sdram internal vco condition 3: cpu frequency = 1.3 x sdram frequency or sdram frequency = 1.3 x cpu frequency tskew4 ext, sel(3:0) = 00110, 00111, 01111, 10011, 10100, 10110, 11000, 11001 or cpu sdram to cpu to sdram ext, sel(3:0) = 01100 condition 4: sdram frequency = 2 x cpu frequency tskew4 sdram cpu internal vco
c9631 low emi 166mhz clock generator for sis630s/pentium ? iii/celeron ? chipsets advanced information imi confidential international microcircuits, inc. 525 los coches st. rev 0.7 4/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 5 of 18 http://www.imicorp.com power on bi-directional pins power up condition: pins 2, 3, 8, 9, 20, and 21are power up bi-directional pins used for selecting the host frequencies (table 1), agp clocks, and power management. during power-up of the device, these pins are in input mode (see figure 2), therefore; they are considered input select pins internal to the ic. after the power supply voltage crosses the input threshold voltage, the input data is latch into the internal control register and these pins become outputs. - hi-z input toggle outputs power supply ramp input data is latched into register, then pin becomes the output. ref1 / agp_sel ref0 / sel3 pci_f / sel1 pci1 / sel2 48m/sel0 24m _ 48m/pm _ sel vdd strapping resistor options: the power up bi-directional pins have a large value pull- down each (250k w) , therefore, a selection 0 is the default. if the system uses a slow power supply (over 5ms settling time), then it is recommended to use an external pull-down (rdn) in order to insure a low selection. in this case, the designer may choose one of two configurations, see figures 3a and 3b. figure 3a represents an additional pull down resistor rdn = 50k w connected from the pin to the ground plane, which allows a faster pull to a low level. if a selection 1 is desired, then a jumper is placed on jp1 to a rup = 10k w resistor as implemented as shown in figure 3a. please note the selection resistors (rup and rdn ) are placed before the damping resistor (rd) close to the pin. figure 3b represent a single resistor 10k w connected to a 3-way jumper, jp2. when a 1 selection is desired, a jumper is placed between leads1 and 3. when a 0 selection is desired, a jumper is placed between leads 3 and 2. . figure 2 figure 3a fi g ure 3b 123 load load vdd vdd imic9631 bidirectional 10k 50k rd jp1 imic9631 bidirectional rd 10k jp2
c9631 low emi 166mhz clock generator for sis630s/pentium ? iii/celeron ? chipsets advanced information imi confidential international microcircuits, inc. 525 los coches st. rev 0.7 4/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 6 of 18 http://www.imicorp.com power management functions power management on this device is controlled by the pd#, cpu_stp#, pci_stp#, and sdr_stp# pins. when pd# is high (default) the device is in normal running mode and all signals are active. the pd# signal is used to bring all clocks to a low level in an orderly fashion. when in power down all outputs are synchronously stopped in a low state, all plls are shut off, and the crystal oscillator is disabled. when in shutdown, the i 2 c function is also disabled. when the device is powered down through the i 2 c interface by activating pd# the oscillator is not turned off. this will enable the user to power up the clock generator through i 2 c. cpu_stp#, pci_stp#, and sdr_stp# are inputs to the clock generator and are used to turn off the cpu, pci, and sdram clocks respectively. these inputs are made synchronous to the clock driver pci_f output. only one rising edge of pci_f occurs after the clock control logic is switched for the output clocks to become enabled/disabled. figure 4 pci_f pci_stp# pci(1:5) cpu_stp# cpu sdr_stp# sdram (0:11)
c9631 low emi 166mhz clock generator for sis630s/pentium ? iii/celeron ? chipsets advanced information imi confidential international microcircuits, inc. 525 los coches st. rev 0.7 4/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 7 of 18 http://www.imicorp.com 2-wire i 2 c control interface the 2-wire control interface implements a read/write slave only interface according to philips i2c specification (ic12, 1996). the device can be read back by using standard i 2 c command bytes. sub addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. the 2-wire control interface allows each clock output to be individually enabled or disabled. 100 kbits/second (standard mode) data transfer is supported. during normal data transfer, the sdata signal only changes when the sclk signal is low, and is stable when sclk is high. there are two exceptions to this. a high to low transition on sdata while sclk is high is used to indicate the start of a data transfer cycle. a low to high transition on sdata while sclk is high indicates the end of a data transfer cycle. data is always sent as complete 8-bit bytes, after which an acknowledge is generated. the first byte of a transfer cycle is a 7-bit address with a read/write bit (r/w#) as the lsb. r/w# = 1 in read mode. r/w# = 0 in write mode. a maximum of 10 bytes of data may be written/read data is transferred msb first at a max rate of 100kbits/s.the device will not respond to any other control interface conditions. in the write mode (see figure 5a), the clock gen. acknowledges address byte, d2, then receives two additional bytes: 1) command code byte, and 2) byte count byte. although the data (bits) in these two bytes are considered dont care; they must be sent and will be acknowledged. subsequently, the below-described sequence (byte 0, byte 1, byte2,) will be valid and acknowledged. in the read mode (see figure 5b), the clock gen. acknowledges address d3, and immediately transmits data starting with byte count, then byte 0, 1, 2, ... after each transmitted byte, this device waits for an acknowledge before transmitting the next byte. serial control registers note: power up conditions for each bit are listed in the @pup column. byte 0: frequency, function select register bit @pup pin# description 7 0 - sel3 (for frequency table 3, selection by software via i2c), selection valid if bit3 = 1 6 0 - sel2 (for frequency table 3, selection by software via i2c), selection valid if bit3 = 1 5 0 - sel1 (for frequency table 3, selection by software via i2c), selection valid if bit3 = 1 4 0 - sel0 (for frequency table 3, selection by software via i2c), selection valid if bit3 = 1 3 0 - 0 = frequency selected by hardware, pins 3, 8, 9, and 20 1 = frequency selection via i 2 c byte0 bits 2, 7:4 2 0 - ext (for extended frequencies), selection valid if bit 3 = 1. default = 0. 1 1 - 0 = spread spectrum disabled 1 = spread spectrum enabled 0 0 - 0 = running 1 = tri-state all outputs
c9631 low emi 166mhz clock generator for sis630s/pentium ? iii/celeron ? chipsets advanced information imi confidential international microcircuits, inc. 525 los coches st. rev 0.7 4/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 8 of 18 http://www.imicorp.com serial configuration command bitmap byte0: functionality and frequency select register (default = 0), msb0=msb1 =1, ssts = 1 ext sel3 sel2 sel1 sel0 description agp(0,1) bit 2 bit7 bit6 bit5 bit4 cpu sdram pci agp_sel=0 agp_sel=1 spread spectrum 0000066.866.833.4 66.8 50.1 0 to C0.5 00001 100.2 100.2 33.4 66.8 50.1 0 to C0.5 00010 166.6 166.6 33.3 66.6 55.6 +/- 0.25 00011 133.5 133.5 33.4 66.7 53.4 0 to C0.5 0010066.8 100.2 33.4 66.8 50.1 0 to C0.5 00101 100.2 66.8 33.4 66.8 50.1 0 to C0.5 00110 100.2 133.6 33.4 66.8 50.1 +/-0.25 00111 133.6 100.2 33.4 66.8 50.1 0 to C0.5 01000 112.0 112.0 33.6 67.2 56.0 +/-0.25 01001 124.0 124.0 31.0 62.0 49.6 0 to C0.5 01010 138.0 138.0 34.5 69.0 50.2 +/-0.25 01011 150.0 150.0 33.3 66.6 50.0 +/-0.25 0110066.8 133.6 33.4 66.8 50.1 +/-0.25 01101 100.0 150.0 33.3 66.6 50.0 +/-0.25 01110 150.0 100.0 33.3 66.6 50.0 0 to C0.5 01111 160.0 120.0 30.0 60.0 60.0 0 to C0.5 1000066.8 100.2 33.4 66.8 50.1 +/-0.25 10001 100.2 100.2 33.4 66.8 50.1 +/-0.25 10010 166.0 110.7 33.3 66.6 55.6 +/-0.25 10011 100.2 133.6 33.4 66.7 53.4 +/-0.25 1010075.0 100.0 37.5 66.8 50.1 +/-0.25 1010183.3 125.0 31.3 66.8 50.1 +/-0.25 10110 105.0 140.0 35.0 66.8 50.1 +/-0.25 10111 133.6 133.6 33.4 66.8 50.1 +/-0.25 11000 110.3 147.0 36.8 67.2 56.0 +/-0.25 11001 115.0 153.3 38.3 62.0 49.6 +/-0.25 11010 120.0 120.0 30.0 69.0 50.2 +/-0.25 11011 138.0 138.0 34.5 66.6 50.0 +/-0.25 11100 140.0 140.0 35.0 66.8 50.1 +/-0.25 11101 145.0 145.0 36.3 66.6 50.0 +/-0.25 11110 147.5 147.5 29.5 66.6 50.0 +/-0.25 11111 160.0 160.0 32 60.0 60.0 +/-0.25 table 3
c9631 low emi 166mhz clock generator for sis630s/pentium ? iii/celeron ? chipsets advanced information imi confidential international microcircuits, inc. 525 los coches st. rev 0.7 4/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 9 of 18 http://www.imicorp.com serial control registers (cont.) byte 1: cpu clock register (1 = enable, 0 = stopped) bit @pup pin# description 7 1 21 24m_48m 1 = selects 24mhz (default) 0 = selects 48mhz 6 1 - ssts, see table 6 5 1 - msb1. see table 6 4 1 - msb0. see table 6 3 1 47 cpu0 enable/stopped 2 1 46 cpu1 enable/stopped 1 1 45 cpu2 enable/stopped 0 1 - reserved for imi test byte 2: pci clock register (1 = enable, 0 = stopped) bit @pup pin# description 71 - reserved 6 1 - reserved 5 1 13 pci5 enable/stopped 4 1 12 pci4 enable/stopped 3 1 11 pci3 enable/stopped 2 1 10 pci2 enable/stopped 1 1 9 pci1 enable/stopped 0 1 8 pci_f enable/stopped byte 3: sdram clock register (1 = enable, 0 = stopped) bit @pup pin# description 7 1 33 sdram7 enable/stopped 6 1 34 sdram6 enable/stopped 5 1 36 sdram5 enable/stopped 4 1 37 sdram4 enable/stopped 3 1 38 sdram3 enable/stopped 2 1 40 sdram2 enable/stopped 1 1 41 sdram1 enable/stopped 0 1 42 sdram0 enable/stopped byte 4: additional sdram clock register (1=enable, 0=stopped) bit @pup pin# description 71 -r5 6 1 21 24_48mhz enable/stopped 5 1 20 48mhz enable/stopped 4 1 26 sdram12 enable/stopped 3 1 27 sdram11 enable/stopped 2 1 28 sdram10 enable/stopped 1 1 30 sdram9 enable/stopped 0 1 31 sdram8 enable/stopped byte 5: agp clock register (1 = enable, 0 = stopped) bit @pup pin# description 7 0 3 sel3, readback h/w strapping status 6 0 9 sel2, readback h/w strapping status 5 0 8 sel1, readback h/w strapping status 4 0 20 sel0, readback h/w strapping status 3 1 2 ref1 enable/stopped 2 1 3 ref0 enable/stopped 1 1 17 agp1 enable/stopped 0 1 16 agp0 enable/stopped * inverted read back of hardware settings. byte 6: control register (1 = enable, 0 = stopped) bit @pup pin# description 7 0 2,3 ref_1x2x_control 6 0 45 cpu_stop_control. controls cpu2 clock to stop/run when cpu_stp# is active. 5 0 2 agp_sel# 4 0 21 pm_sel , read only 3 1 27 cpu_stp# 2 1 28 pci_stp# 1 1 30 sdr_stp# 01 31pd# byte 7: vender information / r register (1 = enable, 0 = stopped) bit @pup pin# description 7 0 - vender identity. see table 5 6 1 - vender identity. see table 5 5 1 - vender identity. see table 5 4 0 - pin / r4* 3 0 - pin / r3* 2 0 - pin / r2* 1 0 - pin / r1* 0 0 - pin / r0, lsb* pin = product id number (read only) *when r(4:0) are programmed into this register, they will override the pin values. byte 8: dial-a-frequency? n register (1 = enable, 0 = stopped) bit @pup pin# description 70 -n6 60 -n5 50 -n4 40 -n3 30 -n2 20 -n1 1 0 - n0 , lsb 0 0 - 1 = enable i 2 c n and r
c9631 low emi 166mhz clock generator for sis630s/pentium ? iii/celeron ? chipsets advanced information imi confidential international microcircuits, inc. 525 los coches st. rev 0.7 4/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 10 of 18 http://www.imicorp.com test function table: applicable only when byte 1, bit0=0. cpu (0:2) pci (0:6) sdram (0:13) ref(0,1) 48mhz 24_48mhz agp = xin / 3 = xin / 8 = xin / 2 = xin = xin = xin / 2 = xin/6 table 4 dial-a-frequency ? feature i2c dial-a-frequency feature is available in this device via byte 6, byte 7, and byte 8. see application note an-0025. dial-a-frequency? p values table ext, sel(3:0) p 00000, 00100, 01100, 10000, 10101 32005333 00001, 00101, 00110, 10001, 10011, 10100, 10110, 11000, 11001 48008000 00011, 00111, 0100x, 01010, 01101, 01111, 10111, 1101x, 1110x, 11110 64010667 00010, 01011, 01110, 10010, 11111 96016000 i 2 c communication waveform for information regarding i 2 c communication waveforms see application note an-0022. spread spectrum clock generation (sscg) spread spectrum is a modulation technique applied here for maximum efficiency in minimizing electro-magnetic interference radiation generated from repetitive digital signals mainly clocks. a clock accumulates em energy at the center frequency it is generating. spread spectrum distributes this energy over a small frequency bandwidth therefore spreading the same amount of energy over a spectrum. this technique is achieved by modulating the clock down from (figure 6a) or around the center (figure 6b) of its resting frequency by a certain percentage (which also determines the energy distribution bandwidth). in this device, spread spectrum is enabled by setting i2c byte0, bit1 = 1. the default of the device at power up keeps the spread spectrum disabled, it is therefore, important to have i2c accessibility to turn-on the spread spectrum function. once the spread spectrum is enabled, the spread bandwidth option is selected by ssts and mbs(1,0) in i2c byte 1 as indicated below in table 6. in down spread mode the center frequency is shifted down from its rested (non-spread) value by ? of the total spread %. (eg.: assuming the center frequency is 100mhz in non-spread mode; when down spread of C0.5% is enabled, the center frequency shifts to 99.75mhz.). in center spread mode, the center frequency remains the same as in the non-spread mode.
c9631 low emi 166mhz clock generator for sis630s/pentium ? iii/celeron ? chipsets advanced information imi confidential international microcircuits, inc. 525 los coches st. rev 0.7 4/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 11 of 18 http://www.imicorp.com spread spectrum clock generation (sscg) (cont.0 spread spectrum selection table ssts mbs1 mbs0 spread% 0 0 0 -0.25* 00 1 -1.0 0 1 0 -0.7** 01 1 -0.5 1 0 0 +/-0.125 1 0 1 +/- 0.5 1 1 0 +/- 0.35 1 1 1 see table 3 table 6 *maximum frequency is offset by C0.125% **maximum frequency is offset by C0.15% maximum ratings maximum input voltage relative to vss: vss - 0.3v maximum input voltage relative to vdd: vdd + 0.3v storage temperature: -65 c to + 150 c operating temperature: 0 c to +70 c maximum esd protection 2kv maximum power supply: 5.5v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range: vss<(vin or vout) c9631 low emi 166mhz clock generator for sis630s/pentium ? iii/celeron ? chipsets advanced information imi confidential international microcircuits, inc. 525 los coches st. rev 0.7 4/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 12 of 18 http://www.imicorp.com dc parameters (vdd =vdds=vddp=vdd48= 3.3v 5%, vddc = 2.5v 5%, ta = 0 c to +70 c) characteristic symbol min typ max units conditions input low voltage vil - - 1.0 v input high voltage vih 2.2 - - v note 2 input low current (@vil = vss) iil -5 a input high current (@vil =vdd) iih 5 a for internal pull down resistors, notes 1,3 tri-state leakage current ioz - - 10 a dynamic supply current idd3.3v - - tbd ma dynamic supply current idd2.5v - - tbd ma power down supply current ipd3.3v 1 ma pd# = 0 power down supply current ipd2.5v 1 ma pd# = 0 input pin capacitance cin - - 5 pf output pin capacitance cout - - 6 pf pin inductance lpin - - 7 nh crystal pin capacitance xin/xout 28 30 32 pf measured from pin to ground. note 5 crystal startup time txs - - 40 m s from stable 3.3v power supply. note1: applicable to sel(0:3), agp_sel, pm_sel, cpu_stp#, pci_stp#, sdr_stp#,pd#. note2: applicable to sdata, sclk. note3: although internal pull-down resistors have a typical value of 120k, this value may vary between 70k and 170k. note4: all outputs loaded as per table 4 below. note5: although the device will reliably interface with crystals of a 15pf C 20pf c l range, it is optimized to interface with a typical c l = 16pf crystal specifications. clock name max load (in pf) cpu, ref 20 pci, sdram, agp 30 24mhz, 48mhz 15 table 4
c9631 low emi 166mhz clock generator for sis630s/pentium ? iii/celeron ? chipsets advanced information imi confidential international microcircuits, inc. 525 los coches st. rev 0.7 4/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 13 of 18 http://www.imicorp.com ac parameters 133 mhz host 100 mhz host symbol parameter min max min max units notes tperiod cpu(0:2) period 7.5 8.0 10.0 10.5 ns 5, 6, 8 thigh cpu(0:2) high time 1.87 - 3.0 - ns 6,10 tlow cpu(0:2) low time 1.67 - 2.8 - ns 6, 11 tr / tf cpu(0:2) rise and fall times 0.4 1.6 0.4 1.6 ns 6, 7 tskew0 any cpu to any cpu skew time - 175 - 175 ps 6, 8, 9 tccj cpu(0:2) cycle to cycle jitter - 250 - 250 ps 6, 8, 9 tperiod sdram[0:12] period 7.5 8.0 10.0 10.5 ns 5, 6, 8 thigh sdram[0:12] high time 1.87 - 3.0 - ns 6,10 tlow sdram[0:12] low time 1.67 - 2.8 - ns 6, 11 tr / tf sdram[0:12] rise and fall times 0.4 1.6 0.4 1.6 ns 6, 7 tskew1 any sdram to any sdram - 250 - 250 ps 6, 8, 9 tccj sdram[0:12] cycle to cycle jitter - 250 - 250 ps 6, 8, 9 tperiod pci(_f, 1:5) period 30.0 - 30.0 - ns 5, 6, 8 thigh pci(_f, 1:5) high time 12.0 - 12.0 - ns 6,10 tlow pci(_f, 1:5) low time 12.0 - 12.0 - ns 6, 11 tr / tf pci(_f, 1:5) rise and fall times 0.5 2.0 0.5 2.0 ns 6, 7 tskew2 (any pci clock) to (any pci clock) - 500 - 500 ps 6, 8, 9 tccj pci(_f, 1:5) cycle to cycle jitter - 500 - 500 ps 6, 8, 9 tperiod agp(0,1) period 15.0 16.0 15.0 16.0 ns 5, 6, 8 thigh agp(0,1) high time 5.25 - 5.25 - ns 6,10 tlow agp(0,1) low time 5.05 - 5.05 - ns 6, 11 tr / tf agp(0,1 rise and fall times 0.5 2.0 0.5 2.0 ns 6, 7 tskew3 (any agp clock) to (any agp clock) - 175 - 175 ps 6, 8, 9 tccj agp(0,1) cycle to cycle jitter - 175 - 175 ps 6, 8, 9 tperiod 48mhz period ( conforms to +167ppm max) 20.8299 20.8333 20.8299 20.8333 ns 5, 6, 8 tr / tf 48mhz rise and fall times 1.0 4.0 1.0 4.0 ns 6, 7 tccj 48mhz cycle to cycle jitter - 500 - 500 ps 6, 8, 9 tperiod 24mhz period 41.6598 41.6666 41.6598 41.6666 ns 5, 6, 8 tr / tf 24mhz rise and fall times 1.0 4.0 1.0 4.0 ns 6, 7 tccj 24 mhz cycle to cycle jitter - 500 - 500 ps 6, 8, 9
c9631 low emi 166mhz clock generator for sis630s/pentium ? iii/celeron ? chipsets advanced information imi confidential international microcircuits, inc. 525 los coches st. rev 0.7 4/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 14 of 18 http://www.imicorp.com ac parameters (cont.) symbol parameter 133 mhz host 100 mhz host units notes tperiod ref(0,1) period 69.8413 71.0 69.8413 71.0 ns 5, 6, 8 tr / tf ref(0,1) rise and fall times (2x) 1.0 2.0 1.0 2.0 ns 6, 7 tr / tf ref(0,1) rise and fall times (1x) 1.0 4.0 1.0 4.0 ns 6, 7 tccj ref(0,1) cycle to cycle jitter - 1000 - 1000 ps 6, 8 tpzl, tpzh output enable delay (all outputs) 1.0 10.0 1.0 10.0 ns 13 tplz, tphz output disable delay (all outputs) 1.0 10.0 1.0 10.0 ns 13 tstable all clock stabilization from power-up 3 3 ms 12 tskew4 any cpu to any sdram (see fig. 1) 0 250 0 250 ps 5, 6, 8 note 5: this parameter is measured as an average over 1us duration, with a crystal center frequency of 14.31818mhz note 6: all outputs loaded as per table 7. note 7: probes are placed on the pins, and measurements are acquired between 0.4v and 2.4v for 3.3v signals. (see figures 7) note 8: probes are placed on the pins, and measurements are acquired at 1.5v for 3.3v signals. (see figures 7) note 9: this measurement is applicable with spread on or spread off. note 10: probes are placed on the pins, and measurements are acquired at 2.4v for 3.3v signals. (see figures 7) note 11: probes are placed on the pins, and measurements are acquired at 0.4v. note 12: the time specified is measured from when all vdds reach their respective supply rail (3.3v ) till the frequency output is stable and operating within the specifications note 13: measured from when both sel1 and sel0 are low test and measurement condition figure 7 - - 2.4v 0.4v 3.3v 0v tr tf 1.5v 3.3v signals tdc 0.4v 2.0v 1.25v 2.5v 0v 2.5v signals tdc tr tf probe output under test load cap - -
c9631 low emi 166mhz clock generator for sis630s/pentium ? iii/celeron ? chipsets advanced information imi confidential international microcircuits, inc. 525 los coches st. rev 0.7 4/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 15 of 18 http://www.imicorp.com output buffer characteristics, cpu characteristic symbol min typ max units conditions pull-up current ioh 1 -15 -31 -51 ma vout =vddc - 0.5v pull-up current ioh 2 -26 -58 -101 ma vout = 1.2v pull-down current iol 1 12 24 40 ma vout = 0.4v pull-down current iol 2 27 56 93 ma vout = 1.2v dynamic output impedance z0 13.5 45 w pci, agp characteristic symbol min typ max units conditions pull-up current ioh 1 -20 -25 -33 ma vout =vdd C 0.5v pull-up current ioh 2 -30 -54 -184 ma vout = 1. 5v pull-down current iol 1 9.4 18 38 ma vout = 0.4v pull-down current iol 2 28 55 148 ma vout = 1.5v dynamic output impedance z0 12 55 w 24mhz, 48mhz, and ref characteristic symbol min typ max units conditions pull-up current ioh 1 -12 -16 -28 ma vout =vdd C 0.5v pull-up current ioh 2 -27 -43 -92 ma vout = 1. 5v pull-down current iol 1 9 13 27 ma vout = 0.4v pull-down current iol 2 26 39 79 ma vout = 1.5v dynamic output impedance z0 20 60 w sdram characteristic symbol min typ max units conditions pull-up current ioh 1 -28 -40 -60 ma vout =vdd C 0.5v pull-up current ioh 2 -67 -107 -184 ma vout = 1. 4 v pull-down current iol 1 23 34 53 ma vout = 0.4v pull-down current iol 1 64 98 159 ma vout = 1.5v dynamic output impedance z0 10 24 w vdd=vdds=vddp=vdd48=3.3v 5%, vddc= 2.5v 5% ta=0 to 70 c
c9631 low emi 166mhz clock generator for sis630s/pentium ? iii/celeron ? chipsets advanced information imi confidential international microcircuits, inc. 525 los coches st. rev 0.7 4/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 16 of 18 http://www.imicorp.com suggested oscillator crystal parameters characteristic symbol min typ max units conditions frequency f o 12.00 14.31818 16.00 mhz tolerance t c - - +/-100 ppm note 1 t s - - +/- 100 ppm stability (t a -10 to +60c) note 1 t a - - 5 ppm aging (first year @ 25c) note 1 operating mode - - - - parallel resonant, note 1 load capacitance c xtal - 16 - pf the crystals rated load. note 1 effective series resistance (esr) r esr - 40 - ohms note 2 note1: for best performance and accurate frequencies from this device, it is recommended but not mandatory that the chosen crystal meets or exceeds these specifications note 2: larger values may cause this device to exibit oscillator startup problems to obtain the maximum accuracy, the total circuit loading capacitance should be equal to c xtal . this loading capacitance is the effective capacitance across the crystal pins and includes the clock generating device pin capacitance (c ftg ), any circuit traces (c pcb ), and any onboard discrete load capacitors (c disc ). the following formula and schematic may be used to understand and calculate either the loading specification of a crystal for a design or the additional discrete load capacitance that must be used to provide the correct load to a known load rated crystal. c l = (c xinpcb + c xinftg + c xindisc ) x (c xoutpcb + c xoutftg + c xoutdisc ) (c xinpcb + c xinftg + c xindisc ) + (c xoutpcb + c xoutftg + c outdisc ) where: c xtal = the load rating of the crystal c xoutftg = the clock generators xin pin effective device internal capacitance to ground c xoutftg = the clock generators xout pin effective device internal capacitance to ground c xinpcb = the effective capacitance to ground of the crystal to device pcb trace c xoutpcb = the effective capacitance to ground of the crystal to device pcb trace c xindisc = any discrete capacitance that is placed between the xin pin and ground c xoutdisc = any discrete capacitance that is placed between the xout pin and ground c xinpcb c xoutpcb c xoutdisc c xindisc c xinftg c xoutftg xin xout clock generator
c9631 low emi 166mhz clock generator for sis630s/pentium ? iii/celeron ? chipsets advanced information imi confidential international microcircuits, inc. 525 los coches st. rev 0.7 4/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 17 of 18 http://www.imicorp.com suggested oscillator crystal parameters as an example, and using this formula for this datasheets device, a design that has no discrete loading capacitors (c disc ) and each of the crystal to device pcb traces has a capacitance (c pcb ) to ground of 2pf (typical value) would calculate as: c l = (2pf + 30pf + 0pf) x (2pf + 30pf + 0pf) = 32 x 32 = 16 pf (2pf + 30pf + 0pf) + (2pf + 30pf + 0pf) 32 + 32 therefore to obtain output frequencies that are as close to this data sheets specified values as possible, in this design example, you should specify a parallel cut crystal, with c l = 16pf.
c9631 low emi 166mhz clock generator for sis630s/pentium ? iii/celeron ? chipsets advanced information imi confidential international microcircuits, inc. 525 los coches st. rev 0.7 4/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 18 of 18 http://www.imicorp.com package drawing and dimensions 48 pin ssop outline dimensions inches millimeters symbol min nom max min nom max a 0.095 0.102 0.110 2.41 2.59 2.79 a 1 0.008 0.012 0.016 0.20 0.30 0.406 a2 0.088 0.090 0.092 2.24 - 2.34 b 0.008 0.010 0.0135 0.203 0.254 0.343 c 0.005 0.008 0.010 0.127 0.20 0.254 d 0.620 0.625 0.630 15.75 15.88 16.18 e 0.291 0.295 0.299 7.39 7.49 7.60 e 0.025 bsc 0.635 bsc h 0.395 0.408 0.420 10.03 10.36 10.67 l 0.020 0.030 0.040 0.508 - 1.06 a0o 4o8o 0o4o8o ordering information part number package type production flow C9631AY 48 pin ssop commercial, 0 c to +70 c marking: example: imi c9631 date code, lot # imiC9631AY package y = ssop revision imi device number b e a a 1 a 2 e a l c d h

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