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1 features ? dual 6-bit resolution ? 700 mhz full-power input bandwidth (-3 db) ? band flatness (0.5 db) from dc to 350 mhz ? 1 gsps sampling rate ? sinad = 35 db typ (5.7 enob) ? thd = -47 db, sfdr = -48 db at f s = 1 gsps, f in = 250 mhz, (sfsr = -0.5db fs) ? 2-tone imd: -47 dbc min at 1 gsps, f in = 249 mhz, 251 mhz ? dnl = 0.35 lsb typ, inl = 0.5 lsb typ ? channel-to-channel input offset error: 1 lsb max, 0 lsb typ ? gain matching (channel-to-channel): 0.25 db max, 0 db typ ? phase matching (channel-to-channel): 2 deg max, 0 deg typ ? channel-to-channel mean difference error: 0.5 lsb (rms) ? channel-to-channel max difference error: 2 lsb typ ? low bit error rate (10 -9 ) at 1 gsps ? very low input capacitance: 1 pf ? 800 mv pp differential or single analog inputs ? differential or single-ended 50 ? pecl-compatible clock inputs ? lvds output compatibility (100 ? ) ? 1:2 data output demultiplexer per adc ? low power consumption: ? 700 mw at v cca = v ccd = 3.15v/v cco = 2.25v ? power supply: 3.15v (analog), 3.15v (digital), 2.25v (output) ? available in 80-lead tqfp package ? temperature range: ? industrial -20 c < t a < 85 c, ? commercial 0 c < t a < 70 c applications ? satellite receiver ? direct rf down-conversion ? test instrumentation ? wlan description the at76cl610 is a monolithic dual 6-bit analog-to-digital converter, designed for digitizing in-phase (i) and quadrature (q) wide bandwidth analog signals at very high sampling rates of up to 1 gsps (giga-samples per second). the ability to directly inter- face i and q signals makes the at76cl610 ideal for use in applications such as direct satellite demodulation. the at76cl610 uses an innovative architec ture and is fabricated with an advanced high-speed bicmos process. the two on-chip adc cores have a closely matched 700 mhz full-power input band- width, providing excellent dynamic perfo rmance in undersampling applications (high if digitizing). the samples from each a/d converter are de-multiplexed by a 1:2 ratio and the output data stream is lvds-compliant. dual adc 6-bit 1 gsps converter at76cl610 preliminary specification for more information, please contact hotline- bdc@gfo.atmel.com rev. 2158a?bdc?04/03
2 at76cl610 2158a?bdc?04/03 figure 1. at76cl610 symbol at76cl610 v cca v ccd v cco v ini v inib v inq v inqb clk clkb gnda gndd gndo doai0:doai5 doai0n:doai5n dobi0:dobi5 dobi0n:dobi5n doaq0:doaq5 doaq0n:doaq5n dobq0:dobq5 dobq0n:dobq5n 2 doir, doirn 2 clko clkob 24 24 i q i q table 1. signal description signal name function direction v cca positive analog power supply i v ccd positive digital power supply i v cco positive output power supply i gnda analog ground i gndd digital ground i gndo output ground i v ini , v inib differential analog inputs i i v inq , v inqb differential analog inputs q i clk, clkb differential clock inputs i clko, clkob differential clock outputs o doai0:doai5; doai0n:doai5n dobi0:dobi5; dobi0n:dobi5n differential output data port channel i o doaq0:doaq5; doaq0n:doaq5n dobq0:dobq5; dobq0n:dobq5n differential output data port channel q o doir, doirn combined (i and q) output in range data o
3 at76cl610 2158a?bdc?04/03 table 2. digital output coding differential or single analog input voltage level digital output i or q binary out of range > +406 mv > positive full scale + 1/2 lsb 111111 1 +406 mv positive full scale + 1/2 lsb 111111 0 +393 mv positive full scale - 1/2 lsb 111111 0 +206 mv positive 1/2 scale + 1/2 lsb 110000 0 +193 mv positive 1/2 scale - 1/2 lsb 101111 0 +6.25 mv bipolar zero + 1/2 lsb 100000 0 -6.25 mv bipolar zero - 1/2 lsb 011111 0 -206 mv negative 1/2 scale + 1/2 lsb 010000 0 -193 mv negative 1/2 scale - 1/2 lsb 001111 0 -393 mv negative full scale + 1/2 lsb 000000 0 -406 mv negative full scale - 1/2 lsb 000000 0 <-406 mv < negative full scale - 1/2 lsb 000000 1
4 at76cl610 2158a?bdc?04/03 figure 2. at76cl610 simplified block diagram functional description the at76cl610 is a dual 6-bit, 1 gsps adc based on an advanced high-speed bicmos technology. each adc has a 6-bit flash-like core architecture. the output data is followed by a 1:2 demultiplexer and lvds output buffer (100 ? ). a common over-range combiner (doir = doiri + doirq) is provided for external gain control adjustment. the at76cl610 works in fully differential mode from analog inputs to digital outputs. the at76cl610 features a full-power input bandwidth of 700 mhz. application scenario figure 3 shows the at76cl610 integrated into a typical application scenario for digital signal reception and demodulation. doirq dobq, dobqn doaq, doaqn doir, doirn dobi, dobin doai, doain clko, clkon + - 2k 2k v inqb v inq 6 12 2 12 lvds range buffer doiri + doirq + - 2k 2k 0.62 v cca 0.62 v cca 0.62 v cca 0.62 v cca v inib v ini 6 12 12 lvds i doiri 6-bit adc i 6-bit adc q 1:2 i lvds q 1:2 q divider 2 lvds clock buffer clock buffer 2 clk clkb
5 at76cl610 2158a?bdc?04/03 figure 3. functional application (typical) control functions: clock and carrier recovery, gain adjustment... i q at76cl610 clock i q 0 90 local oscillator if band filter tunable band filter low pass filter synthesizer 1.5 ... 2.5 ghz local oscillator 11..12 ghz 1..2 ghz bandpass amplifier bandpass amplifier satellite agc low noise converter demodulation quadrature i q parabolic antenna analog digital in-phase
6 at76cl610 2158a?bdc?04/03 electrical characteristics notes: 1. absolute maximum ratings are limiting values (referenced to gnd = 0v), to be applied individually, while other paramete rs are within specified operating conditions. long exposure to maximum ratings may affect device reliability. 2. limiting values given are in accordance with the absolute maximum rating system (iec 134). these are stress ratings only and operation of the device at these or at any other conditions above those given in the electrical characteristics sections of the specifications is not implied. exposure to limiting values for extended periods may affect device reliability. table 3. absolute maximum ratings symbol parameter value unit v cca analog positive supply voltage gnd to 6 v v ccd digital positive supply voltage gnd to 6 v vcco output supply voltage gnd to 6 v dv cca to v cco maximum difference between v cca and v cco 2.4 v dv cca to v ccd maximum difference between v cca and v ccd 0.8 v dv ccd to v cco maximum difference between v ccd and v cco 1.6 v v ini - v inib v inq - v inqb differential analog input voltages 2 v pp v clk or v clkb clock input voltage -0.3 to v ccd + 0.3 v v clk - v clkb maximum difference between v clk and v clkb 2v pp t j maximum junction temperature +125 c t stg storage temperature -65 to +150 c t leads lead temperature (soldering 10s) +300 c table 4. recommended conditions of use symbol parameter min typ max unit v cca analog supply voltage 3.0 3.15 3.3 v v ccd digital supply voltage 3.0 3.15 3.3 v v cco output supply voltage 2.0 2.25 3.3 v v ini - v inib or v inq - v inqb differential or single analog input voltage (full scale) 750 800 850 mv pp v clk - v clkb clock input level differential 500 mv pp t a ambient temperature range 0 < t a < 70 ("c" grade) -20 < t a < 85 ("v" grade) c
7 at76cl610 2158a?bdc?04/03 operating characteristics the following conditions apply to the electrical operating characteristics given in table 5. the test levels are given in table 6 on page 10. v cca = 3.15v, v ccd = 3.15v, v cco = 2.25v, v ini - v inib or v inq - v inqb = 800 mv pp -0.5 db full scale differential input (digital outputs lvds 100 ? ), 50% clock duty cycle t a (typical) = 25 c table 5. electrical operating characteristics symbol parameter test level min typ max unit power requirements v cca power supply voltage analog i 3.0 3.15 3.3 v v ccd power supply voltage digital i 3.0 3.15 3.3 v v cco power supply voltage output digital (lvds) i 2.0 2.25 3.3 v i cca supply current analog i 52 60 ma i ccd supply current digital i 110 130 ma i cco supply current output i 100 110 ma pd nominal power dissipation i 700 850 mw psrr single channel power supply rejection ratio (v cca ) iii tbf db resolution 6bits analog inputs v ini or v inq full scale input voltage range (differential mode) 0.62 v cca common mode voltage iii 750 800 850 mv v inib or v inqb full scale input voltage range (single mode) 0.62 v cca common mode voltage iii 750 800 850 mv c in analog input capacitance i and q ii, iv 2 pf r in input resistance i and q i 1.3 2 k ? fpbw full-power input bandwidth (-3 db) iii 600 700 mhz clock input logic compatibility for clock inputs pecl/ecl/lvds v il - v ilh differential logic level iv 300 mv power level into 50 ? termination dbm into 50 ? clock input power level iii -10 -6 -4 dbm c clk clock input capacitance ii 2 pf digital outputs logic compatibility for digital outputs (depending on the value of v cco )lvds v od differential output voltages swings (assuming v cco = 2.25v and v ccd = 3.15v) iii, i 250 300 400 mv output levels (assuming v cco = 2.25v and v ccd = 3.15v) 100 ? differentially terminated ii v ol logic 0 voltage i, iii 0.9 1.1 1.2 v
8 at76cl610 2158a?bdc?04/03 v oh logic 1 voltage i, iii 1.3 1.4 1.47 v v os output offset voltage (assuming v cco = 2.25v and v ccd = 3.15v) 100 ? differentially terminated i, iii 1125 1200 1275 mv change in v od between 0 and 1 iii 25 mv change in v os between 0 and 1 iii 25 mv output current (shorted output) iii 12 ma output current (grounded output) not allowed output level drift with temperature iii 1.4 mv/ c differential output amplitude drift with temperature iii 0.16 mv/ c dc accuracy single-ended 50% clock duty cycle (clk, clkb); binary output data format. t a (typical) = 25 c. dnl differential non-linearity i, iii 0.25 0.35 lsb inl integral non-linearity i, iii 0.35 0.5 lsb no missing codes guaranteed over specified temperature range output offset code (single channel i or q) i, iii 31 31.5 32 lsb input offset voltage (single channel i or q) i, iii 0.62 x v cca v gain error drift against temperature iii tbf mv/ c gain error drift against analog supply iii tbf mv/v input offset matching channel i or q (static) i, iii -1 0 1 lsb gain matching channel i or q (static) i, iii 0 0.25 db transient performance ber bit error rate fs = 1 gsps, f in = 250 mhz iii 10 -9 error/ sample ort overvoltage recovery time iii tbd ns ac performance differential input and clock mode; 50% clock duty cycle (clk, clkb); t a = 25 c, unless otherwise specified. sinad fs = 1 gsps, f in = 10 mhz (single-ended input) i, iii 35 36 db fs = 1 gsps, f in = 20 mhz iii 35 36 db fs = 1 gsps, f in = 250 mhz iii 34 35 db enob fs = 1 gsps, f in = 10 mhz (single-ended input) i, iii 5.6 5.8 bits fs = 1 gsps, f in = 20 mhz iii 5.4 5.75 bits fs = 1 gsps, f in = 250 mhz iii 5.3 5.70 bits table 5. electrical operating characteristics (continued) symbol parameter test level min typ max unit
9 at76cl610 2158a?bdc?04/03 thd fs = 1 gsps, f in = 10 mhz (single-ended input) i, iii -42 -49 dbc fs = 1 gsps, f in = 20 mhz iii -42 -49 dbc fs = 1 gsps, f in = 250 mhz iii -40 -47 dbc sfdr fs = 1 gsps, f in = 10 mhz (single-ended input) i, iii -44 -49 dbc fs = 1 gsps, f in = 20 mhz iii -44 -49 dbc fs = 1 gsps, f in = 250 mhz iii -40 -48 dbc imd two-tone inter-modulation distortion (single channel) f in1 = 249 mhz, f in2 = 251 mhz at f s = 1 gsps iii -48 dbc gf gain flatness: 0.5 db iii 250 350 mhz dg gain matching (channel i and q) f in = 250 mhz, fs = 1 ghz iii 0 0.25 db d phase matching (channel i and q), f in = 250 mhz, fs = 1 ghz iii -2 0 2 deg cr crosstalk channel i versus channel q, f in = 250 mhz, fs = 1 ghz iii <<- 52 db switching performance and characteristics ? see figure 4 on page 10 f s maximum clock frequency ii 1 gsps f s minimum clock frequency ii 10 msps tc1 minimum clock pulse width (high) ii 0.400 0.500 50 ns tc2 minimum clock pulse width (low) ii 0.400 0.500 50 ns ta aperture delay ii +350 ps jitter aperture uncertainty ii 0.4 ps(rms) tdclk clock output delay between input clock and output clock (50%) iii tbd 1.03 tbd ns tdo data output delay between input clock and data iii tbd 1.28 tbd ns data output skew iii 50 100 ps tr/tf output rise/fall time for data ready (10% - 90%) with 7 pf load iii 300 350 500 ps td data output delay 50% with data ready iii tbd 250 tbd ps pd data pipeline delay 1 for port b 2 for port a clock cycles table 5. electrical operating characteristics (continued) symbol parameter test level min typ max unit
10 at76cl610 2158a?bdc?04/03 figure 4. timing diagram test levels only minimum and maximum values are guar anteed (typical values are issued from characterization results). note: 1. unless otherwise specified, all tests are pulsed tests: therefore t j = t c = t a , where t j , t c and t a are junction, case and ambient temperature respectively. t a t do data n data n+1 data n+2 n-2 n n-4 n-1 n+1 n-3 t r /t f t d t d t dclk data n-1 input clock output a output b data ready output clock analog input t d t r /t f table 6. test levels d 100% wafer tested at +25 c (1) i 100% production tested at +25 c (1) (for packaged device) ii parameter is guaranteed by design iii characterization testing: thermal steady-state conditions at specified temperature) iv parameter is a typical value only
11 at76cl610 2158a?bdc?04/03 equivalent input/output schematics figure 5. simplified input model for signal figure 6. simplified lvds output model figure 7. simplified input model for clock v cca cnda v ini v inib 0.62 x v cca 0.62 x v cca 2 k ? 2 k ? gndo v cco doai0:doai5 dobi0:dobi5 doai0n:doai5n dobi0n:dobi5n v ccd gndd clk clkb v cca/2 50 ? 50 ? 100 ? 100 ?
12 at76cl610 2158a?bdc?04/03 applying the at76cl610 power supplies decoupling, bypassing and grounding here are the recommended bypassing, decoupling and grounding schemes for the dual 6-bit 1 gsps adc power supplies. figure 8. v ccd and v cca bypassing and grounding scheme figure 9. v cco bypassing and grounding scheme figure 10. power supplies decoupling scheme note: the bypassing capacitors (1 f and 100 pf) should be placed as close as possible to the board connectors, whereas the decoupling capacitors (100 pf, 10 nf) should be placed as close as possible to the device. 100 pf 1 f v ccd c c v cca pc board +3.15v pc board gnd l l c v cco l 100 pf 1 f pc board +2.25v pc board gnd v cca gnda v ccd gndd v cco gndo at76cl610 v cca 10 nf 100 pf v cco gnda v ccd gndo 100 pf 10 nf gndd 100 pf 10 nf
13 at76cl610 2158a?bdc?04/03 analog inputs the analog inputs can be entered only in differential mode. a dc decoupling capaci- tance of 10 nf allows the removal of an input common mode voltage of 0.62 v cca . a terminal load of 100 ? is located on-board. the analog input resistance of the at76cl610 is equal to 2 k ? . figure 11. differential rf generator and dual 6-bit configuration note: the user should use an rf generator with a differential output signal or use an external splitter to create a differential signal. figure 12. rf generator single-ended and differential input clock inputs the clock inputs can be entered in differential or single-ended mode. moreover, it is possible for the clock input common mode to be 0v. an ac coupling capacitance (10 nf) can be used to remove the input common mode voltage. it is not necessary to have an on-board 100 ? terminal load as it exists inside the at76cl610. an rf generator is used in single mode for the clk signal. the clkbb sma must be terminated by a 50 ? load. vin_i or vin_q at76cl610 vin_ib or vin_qb rf generator vout evaluation board rf generator voutb 50 ? 10 nf 10 nf 50 ? 100 ? 50 ? 50 ? vini at76cl610 vinib 2 tp-101 6 4 rf generator vout evaluation board 50 ? 10 nf 10 nf 100 ?
14 at76cl610 2158a?bdc?04/03 figure 13. single-ended configuration an rf generator with a differential output signal for i and q or an external splitter can also be used in order to create a differential signal. figure 14. input differential configuration clk at76cl610 clkb rf generator evaluation board load termination 50 ? 10 nf 10 nf 50 ? clk at76cl610 clkb rf generator vout evaluation board rf generator voutb 50 ? 10 nf 10 nf 50 ?
15 at76cl610 2158a?bdc?04/03 package description 80-lead tqfp pin description table 7. at76cl610 80-lead tqfp pin description symbol pin number function gnda, gndd, gndo 1, 4, 5, 8, 13, 16, 17, 20, 30, 36, 66, 71 ground pins. to be connected to external ground plane. v cca 9, 12 analog positive supply: 3.15v typ. v ccd 3, 19, 65 +3.15v digital supply v cco 29, 35, 72 +2.25v output supply v ini 14 in-phase (+) analog input signal of the sample and hold differential preamplifier channel i v inib 15 inverted phase (-) of analog input signal (v ini ) v inq 7 in-phase (+) analog input signal of the sample and hold differential preamplifier channel q v inqb 6 inverted phase (-) of analog input signal (v inq ) clk 10 in-phase (+) clock input signal. the analog input is sampled and held on the rising edge of the clk signal. clkb 11 inverted phase (-) of clock input signal (clk) doai0:doai5 21, 25, 31, 37, 41, 45 in-phase (+) digital outputs first phase demultiplexer doai0 is the lsb. d0ai5 is the msb. channel i. doai0n:doai5n 22, 26, 32, 38, 42, 46 in-phase (-) digital outputs first phase demultiplexer doai0n is the lsb. d0ai5n is the msb. channel i. dobi0:dobi5 23, 27, 33, 39, 43, 47 in-phase (+) digital outputs second phase demultiplexer dobi0 is the lsb. d0bi5 is the msb. channel i. dobi0n:dobi5n 43, 47, 53, 57, 61, 65 in-phase (-) digital outputs second phase demultiplexer dobi0n is the lsb. d0bi5n is the msb. channel i. doaq0:doaq5 56, 60, 64, 70, 76, 80 in-phase (+) digital outputs first phase demultiplexer doai0 is the lsb. d0ai5 is the msb. channel q. doaq0n:doaq5n 55, 59, 63, 69, 75, 79 in-phase (-) digital outputs first phase demultiplexer doai0n is the lsb. d0ai5n is the msb. channel q. dobq0:dobq5 54, 58, 62, 68, 74, 78 in-phase (+) digital outputs second phase demultiplexer dobq0 is the lsb. d0bq5 is the msb. channel q. dobq0n:dobq5n 53, 57, 61, 67, 73, 77 in-phase (-) digital outputs second phase demultiplexer dobq0n is the lsb. d0bq5n is the msb. channel q. doir 49 combined (i and q) in-phase (+) out-of-range bit first phase demultiplexer. out-of-range is high on the leading edge of code 0 and code 64. doirn 50 combined (i and q) in-phase (-) out-of-range bit first phase demultiplexer clko 52 output clock in-phase (+),1/2 input clock frequency clkob 51 output clock in-phase (-),1/2 input clock frequency nc 2, 18 not connected
16 at76cl610 2158a?bdc?04/03 figure 15. 80-lead tqfp pinout tqfp80 12 x 12 x 1.0 mm atmel - dual 6-bit nc nc gndd gndd gndd gndd gnda vinqb vinq vini vinib gnda gnda gnda vccd vcca vcca ckl clkb vccd 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 dobq2n dobq2 doaq2n doaq2 vccd gndd dobq3n dobq3 doaq3n doaq3 gndo vcco dobq4n dobq4 doaq4n doaq4 dobq5n dobq5 doaq5n doaq5 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 doai1 doai1n dobi1 dobi1n doai0 doai0n dobi0 dobi0n doir doirn clkob clko dobq0n dobq0 doaq0n doaq0 dobq1n dobq1 doaq1n doaq1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 dobi2n dobi2 doai2n doai2 gndo vcco dobi3n dobi3 doai3n doai3 gndo vcco dobi4n dobi4 doai4n doai4 dobi5n dobi5 doai5n doai5
17 at76cl610 2158a?bdc?04/03 package dimensions figure 16. 80-lead tqfp package dimensions d ab c gauge plane seating plane lead coplanarity e 1 e d 1 d n 1 ddd a-b cd mss ccc c a l 1.00 ref b - 0.20 rad. nom. 0.20 rad. nom. e 12 typ. 12 typ. a 2 a 1 a 0.25 stand off a 1 notes: 1. all dimensions are in millimeters. 2. dimensions shown are nominal with tolerances as indicated. 3. l/f: eftec 64t copper, 0.127 mm (0.005") thick. 4. foot length: "l" is measured at gauge plane, at 0.25 mm above the seating plane. a dimensions 1.4 mm thickness - body +2.00 mm footprint a1 a2 d d1 e e1 l e b ddd ccc max. tolerances 0.50 0.05 0.20 4 6 0.20 0.05 +0.15/-0.10 basic 0.05 max. max. 1.20 0.05 min./0.15 max. 1.00 14.00 12.00 14.00 12.00 0.60 0.50 0.22 0.08 0.08 0 - 7 table 8. 80-lead tqfp package characteristics package type ja ( c/w) 80-lead tqfp 39.0
18 at76cl610 2158a?bdc?04/03 definition of terms table 9. definition of terms ber bit error rate probability of exceeding a specified error threshold for a sample. an error code is a code that differs by more than 4 lsbs from the correct code. fpbw full-power input bandwidth analog input frequency for which the fundamental component in the digitally reconstructed output has fallen by 3 db with respect to its low frequency value (determined by fft analysis) for input at full scale. sinad signal-to-noise and distortion ratio ratio expressed in db of the rms signal amplitude, set to 1 db below full scale, to the rms sum of all other spectral components, including the harmonics except dc. thd total harmonic distortion ratio expressed in dbc of the rms sum of the first five harmonic components, to the rms value of the measured fundamental spectral component. sfdr spurious free dynamic range ratio expressed in db of the rms signal amplitude, set at 1 db below full scale, to the rms value of the next highest spectral component (peak spurious spectral component). sfdr is the key parameter for selecting a converter to be used in a frequency domain application (radar systems, digital receiver, network analyzer...). it may be reported in dbc (i.e., degrades as signal levels are lowered), or in dbfs (i.e., always related back to converter full scale). enob effective number of bits where a is the actual input amplitude and v is the full scale range of the adc under test dnl differential non-linearity the differential non-linearity for an output code (i) is the difference between the measured step size of code (i) and the ideal lsb step size. dnl (i) is expressed in lsbs. dnl is the maximum value of all dnl (i). a dnl error specification of less than 1 lsb guarantees that there are no missing output codes and that the transfer function is monotonic. measured with a histogram method. inl integral non-linearity the integral non-linearity for an output code (i) is the difference between the measured input voltage at which the transition occurs and the ideal value of this transition. inl (i) is expressed in lsbs, and is the maximum value of all |inl (i)|. measured with a histogram method. ta aperture delay delay between the rising edge of the differential clock inputs (clk, clkb) (zero crossing point), and the time at which (v in , v inb ) is sampled. jitter aperture uncertainty sample-to-sample variation in aperture delay. the voltage error due to jitter depends on the slew rate of the signal at the sampling point. ort overvoltage recovery time time to recover 0.2% accuracy at the output, after a 150% full scale step applied on the input is reduced to mid-scale. tdo digital data output delay delay from the falling edge of the differential clock inputs (clk, clkb) (zero crossing point) to the next point of change in the differential output data (zero crossing) with specified load. td time delay from clock ready to data time delay from data transition ready to data. tpd pipeline delay number of clock cycles between the sampling edge of input data and the associated output data being made available (not taking in account the tdo). tr rise time time delay for the output data signals to rise from 10% to 90% of the delta between low level and high level. tf fall time time delay for the output data signals to fall from 90% to 10% of the delta between low level and high level. enob sinad 1.76 ? 20 log a / v /2 () + 6.02 ----------------------------------------------------------------------------------- =
19 at76cl610 2158a?bdc?04/03 ordering information psrr power supply rejection ratio ratio of input offset variation to a change in power supply voltage. offi,q offset output code i or q mean output code with no input signal applied. imd inter-modulation distortion the two-tone intermodulation distortion (imd) rejection is the ratio of either input tone to the worst third order intermodulation products. the input tone levels are at -7 db full scale. table 9. definition of terms (continued) table 10. ordering information part number package temperature range screening comments at76cl610-10ax tqfp 80 ambient prototype prototype at76cl610-10ac tqfp 80 "c" grade 0 c < t a < 70 c standard AT76CL610-10AI tqfp 80 "i" grade -20 c < t a < 85c standard at76cl610-eb tqfp 80 ambient prototype evaluation kit
20 at76cl610 2158a?bdc?04/03 datasheet status description life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reas onably be expected to result in personal injury. atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify atmel for any damages resulting from such improper use or sale. table 11. datasheet status datasheet status validity objective specification this datasheet contains target and goal specifications for discussion with the customer and application validation. before design phase target specification this datasheet contains target or goal specifications for product development. valid during the design phase preliminary specification -site this datasheet contains preliminary data. additional data may be published later and could include simulation results. valid before characterization phase preliminary specification -site this datasheet contains characterization results. valid before the industrialization phase product specification this datasheet contains final product specifications. valid for production purposes limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limitin g values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification.
printed on recycled paper. ? atmel corporation 2003. disclaimer: atmel corporation makes no warranty for the use of its product s, other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions locat ed on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or spec ifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained her ein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel produc ts, expressly or by implication. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 2158a?bdc?04/03 0m ? atmel corporation 2003 . all rights reserved. atmel ? is a registered trademar k of atmel corporation. other terms and product names may be the trademarks of others.

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