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| - 1 - k4j52324ki rev. 1.2, mar. 2010 samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" bas is, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, tradem ark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered tradem arks belong to their respective owners. ? 2010 samsung electronics co., ltd. all rights reserved. datasheet 512mb gddr3 sgram i-die 136 fbga with halogen-free & lead-free (rohs compliant)
- 2 - k4j52324ki datasheet gddr3 sgram rev. 1.2 revision history revision no. history draft date remark editor 0.1 - target spec jul. 2009 - s.h.kim 0.2 - correction typo jul. 2009 - s.h.kim 0.3 - changed part number aug. 2009 - s.h.kim - changed package dimension 0.5 - changed ac characteristics - ii sep. 2009 - s.h.kim 0.6 - changed ball height/package height oct. 2009 - s.h.kim - changed part number 1.0 - added idd currnent values oct. 2009 - s.h.kim 1.1 - changed layout dec. 2009 - s.h.kim - added thermal characteristcs values - added ibis values 1.2 - changed twr in 2.6 & 2.4gbps mar. 2010 - s.h.kim - 3 - k4j52324ki datasheet gddr3 sgram rev. 1.2 table of contents 512mb gddr3 sgram i-die 1. features.................................................................................................................... ............................................... 4 2. ordering information ........................................................................................................ ................................ 4 3. general description ......................................................................................................... .................................. 4 4. definition of signal state terminology ...................................................................................... ............... 5 5. input/output functiona l description ....... .............. .............. .............. .............. .............. ............ ................. 6 6. block diagram (2mbit x 32i/o x8 bank) ....................................................................................... .......................... 7 7. functional description ...................................................................................................... ............................... 8 7.1 simplified state diagram ................................................................................................... ...................................... 8 7.2 initialization............................................................................................................. ................................................. 9 7.3 mode register set (mrs) .................................................................................................... ................................... 10 7.4 extended mode register set (emr s) ............. .............. .............. .............. .............. ........... .......... ........................... 15 7.5 clock frequency change sequence during the device operation ................................................................ ....... 18 7.6 boundary scan function ..................................................................................................... .................................... 19 7.7 mirror function ............................................................................................................ ............................................ 23 7.8 commands .............. ............... .............. .............. .............. ........... ........... ........... ........... ........................................... 24 7.9 operations ................................................................................................................. .............................................. 28 7.9.1. bank/row activation ....... .............................................................................................. ................................... 28 7.9.2. reads ................................................................................................................... .......................................... 29 7.9.3. writes.................................................................................................................. .......................................... 37 7.9.4. precharge............................................................................................................... .......................................... 44 7.9.5. power-down (cke not active) ............................................................................................. ........................... 44 7.10 gddr3 tfaw definition ..................................................................................................... ................................... 45 8. truth table ................................................................................................................. ............................................ 46 9. ac & dc operating conditions................................................................................................ .......................... 50 9.1 absolute maximem ratings ...... ............................................................................................. .................................. 50 9.2 power & dc operating conditions ............................................................................................ .............................. 50 9.3 clock input operating conditions....................... .................................................................... ................................. 51 9.4 capacitance (vdd=1.8v, ta= 25c, f=1mhz) ................................................................................... ..................... 51 9.5 thermal characteristics ( 2.6gbps at vdd=1.8v + 0.1v, vddq=1.8v + 0.1v )................................................... .. 51 9.6 dc characteristics......................................................................................................... .......................................... 52 9.7 ac characteristics......................................................................................................... .......................................... 54 10. ibis : i/v characteristics for input and output buffers .................................................................... 59 11. package dimensions (fbga).................................................................................................. ............................ 61 - 4 - k4j52324ki datasheet gddr3 sgram rev. 1.2 1. features 2. ordering information note : pod_135 is currently under discussion at jedec gddr5 tg. 3. general description the k4j52324ki is 536,870,912 bits of hyper synchronous data rate dynamic ram organized as 8 x 2,097,152 words by 32 bits, fabr icated with sam- sung?s high performance cmos technology. sy nchronous features with data strobe allo w extremely high performance up to 10.4gb/s/ chip. i/o trans- actions are possible on both edges of the clock cycle. range of operating frequencies , and programmable latencies allow the dev ice to be useful for a variety of high performance memory system applications. ? 1.8v 0.1 power supply for device operation ? 1.8v 0.1 power supply for i/o interface ? on-die termination (odt) ? output driver strength adjustment by emrs ? calibrated output drive ? 1.8v pseudo open drain compatible inputs/outputs ? 8 internal banks for concurrent operation ? differential clock inputs (ck and ck ) ? commands entered on each positive ck edge ? cas latency : 7, 8, 9, 10, 11, 12, 13, 14, 15 (clock) ? programmable burst length : 4 and 8 ? programmable write latency : 1, 2, 3, 4, 5, 6 and 7 (clock) ? single ended read strobe (rdqs) per byte ? single ended write strobe (wdqs) per byte ? rdqs edge-aligned with data for reads ? wdqs center-aligned with data for writes ? data mask(dm) for masking write data ? auto & self refresh modes ? auto precharge option ? 32ms, auto refresh (8k cycle) ? halogen - free and lead - free 136 ball fbga ? maximum clock frequency up to 1.3ghz ? maximum data rate up to 2.6gbps/pin ? dll for outputs ? boundary scan function with sen pin mirror function with mf pin part number max freq. max data rate vdd & vddq package k4j52324ki-hc7a 1.3ghz 2.6gbps/pin 1.8v 0.1v 136 ball fbga k4j52324ki-hc08 1.2ghz 2.4gbps/pin k4j52324ki-hc1a 1.0ghz 2.0gbps/pin k4j52324ki-hc12 800mhz 1.6gbps/pin k4j52324ki-hc14 700mhz 1.4gbps/pin - 5 - k4j52324ki datasheet gddr3 sgram rev. 1.2 4. definition of signal state terminology normal package (top view) vddq vdd vss zq vssq dq0 dq1 vssq vddq dq2 dq3 vddq vssq wdqs0 rdqs0 vssq vddq dq4 dm0 vddq vdd dq6 dq5 cas vss vssq dq7 ba0 vref a1 ras cke vssa rfu1 rfu2 vddq vdda a10 a2 a0 vss vssq dq25 a11 vdd dq24 dq27 a3 vddq dq26 dm3 vddq vssq wdqs3 rdqs3 vssq vddq dq28 dq29 vddq vssq dq30 dq31 vssq vddq vdd vss sen mf vss vdd vddq vssq dq9 dq8 vssq vddq dq11 dq10 vddq vssq rdqs1 wdqs1 vssq vddq dm1 dq12 vddq cs dq13 dq14 vdd ba1 dq15 vssq vss we a5 vref vddq ck ck vssa a4 a6 a8/ap vdda a7 dq17 vssq vss a9 dq19 dq16 vdd vddq dm2 dq18 vddq vssq rdqs2 wdqs2 vssq vddq dq21 dq20 vddq vssq dq23 dq22 vssq reset vss vdd vddq 1 2 3 4 5678 9 10 11 12 a b c d e f g h j k l m n p r t v ba2 note : 1. rfu1 is reserved for future use 2. rfu2 is reserved for future use - 6 - k4j52324ki datasheet gddr3 sgram rev. 1.2 5. input/output functional description symbol type function ck, ck input clock : ck and ck are differential clock inputs. cmd, add inputs are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). ck and ck should be maintained stable except self-refresh mode. cke input clock enable : cke high activates, and cke low deactivates, inte rnal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and se lf refresh operation (all banks idle), or active power- down (row active in any bank). cke is sy nchronous for power down entry and exit, and for self refresh entry. cke is asyn- chronous for self refresh exit. cke must be maintained hi gh throughout read and write acce sses. input buffers, excluding ck, ck and cke are disabled during power-down. input buffers, excluding cke, are disa bled during self refresh. cs input chip select : all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ras , cas , we input command inputs : ras , cas and we (along with cs ) define the command being entered. dm0 ~dm3 input input data mask : dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of clock. although dm pins are input only, the dm loading matches the dq and wdqs loading. ba0 ~ ba2 input bank address inputs : ba0, ba1 and ba2 define to which bank an acti ve, read, write or precharge command is being applied. a0 ~ a11 input address inputs : provided the row address for active commands and the column address and auto precharge bit for read/write commands to select one location out of the memory array in the respective bank. a8 is sampled during a pre- charge command to determine whether the precharge applies to one bank (a8 low) or all banks (a8 high). if only one bank is to be precharged, the bank is selected by ba0, ba1,ba2. the address inputs also provide the op-code during mode register set commands. row addresses : ra0 ~ ra11, column addresses : ca0 ~ ca7, ca9 . column address ca8 is used for auto precharge. dq0 ~ dq31 input/ output data input/ output: bi-directional data bus. rdqs0 ~ rdqs3 output read data strobe: output with read data. rdqs is edge-aligned with read data. wdqs0 ~ wdqs3 input write data strobe: input with write data. wdqs is center-aligned to the input data. nc/rfu no connect: no internal electrical connection is present. v ddq supply dq power supply v ssq supply dq ground v dd supply power supply v ss supply ground v dda supply dll power supply v ssa supply dll ground v ref supply reference voltage: 0.7*vddq , 2 pins : (h12) for data input , (h1) for cmd and address mf input mirror function for clamshell m ounting of drams. vddq cmos input. zq reference resistor connection pi n for on-die termination. res input reset pin: reset pin is a vddq cmos input sen input scan enable : must tie to the ground in case not in use. vddq cmos input. - 7 - k4j52324ki datasheet gddr3 sgram rev. 1.2 6. block diagram (2mbit x 32i/o x8 bank) * ick : internal clock bank select timing register address register refresh counter row buffer row decoder col. buffer data input register serial to parallel 2m x 32 sense amp 4-bit prefetch output buffer i/o control column decoder latency & burst length programming register strobe gen. ick addr lcke ick cke cs ras cas we dmi ldmi ck,ck lcas lras lcbr lwe lwcbr lras lcbr 128 32 32 lwe ldmi x32 dqi input buffer 128 output dll input buffer rdqs wdqs 2m x 32 2m x 32 2m x 32 2m x 32 2m x 32 2m x 32 2m x 32 - 8 - k4j52324ki datasheet gddr3 sgram rev. 1.2 7. functional description 7.1 simplified state diagram self auto idle mrs emrs row precharge power write power act read a read refs refsx refa ckel mrs ckeh ckeh ckel write power applied automatic sequence command sequence read a write a read pre pre pre pre refresh refresh down power down active on a read a read a write a preall active precharge precharge preall read write preall = precharge all banks mrs = mode register set emrs = extended mode register set refs = enter self refresh refsx = exit self refresh refa = auto refresh ckel = enter power down ckeh = exit power down act = active write a = write with autoprecharge read a = read with autoprecharge pre = precharge write - 9 - k4j52324ki datasheet gddr3 sgram rev. 1.2 7.2 initialization gddr3 sgrams must be powered up and in itialized in a predefined manner. operational procedur es other than those speci- fied may result in undefined operation. 1. apply power and keep cke/reset at low state (all other inputs may be undefined) - apply vdd and vddq simultaneously - apply vddq before vref. (inputs are not recognized as valid until after v ref is applied) - the vdd voltage ramp time must be no greater than 200ms from 300mv to vddmin and the vdd voltage ramps are without an y slope reversal 2. required minimum 100us for the stabl e power before reset pin transition to high - upon power-up the address/command active terminatio n value will automatically be set based off the state of reset and cke. - on the rising edge of reset the cke pin is latched to determine the address a nd command bus termination value. if cke is sampled at a zero the address termination is set to 1/2 of zq. if cke is sampled at a one the address termination is set to zq. - reset must be maintained at a logic low level and cs at a logic high value during power-up to ensure that the dq outp uts will be in a high-z state, all active terminators off, and all dlls off. 3. minimum 200us delay required prio r to applying any executable command after stabl e power and clock. during this time, ck e should be brought to high and deselect or nop command should be applied. 4. once the 200us delay has been satisf ied, a deselect or nop command should be applied. 5. issue a precharge all command following after nop command. 6. issue a emrs command (ba1ba0="01") to enable the dll. 7. issue mrs command (ba0ba1 = "00") to reset the dll and to program the operating parameters. 20k clock cycles are required to lock the dll. 8. issue a precharge all command 9. issue at least two auto refresh command to update the driver impedance and calibrate the output drivers. following these requirements, the gddr3 sgram is ready for normal operation. code v dd v ddq v ref ck ck res cke command dm a0-a7, a9-a11 a8 ba0, ba1 rdqs wdqs dq ra code ra code bao=h, ba nop pre lmr lmr pre ar ar act high high high ba1 =l bao=l, ba1 =l trp tmrd trfc trp trfc load extended mode register tmrd 20k load mode register t is t ih code t is t ih t is t ih t is t ih t0 t1 ta0 tb0 tc0 td0 te0 tf0 t ch t cl t is t ih precharge all banks precharge all banks 1st auto refresh 2nd auto refresh dll reset all banks all banks t=10ns power-up: vdd and clock stable t = 200us t ats t ath t = 100us - 10 - k4j52324ki datasheet gddr3 sgram rev. 1.2 7.3 mode register set (mrs) the mode register stores the data for cont rolling the various operating modes of gddr3 sgram. it programs cas latency, addressi ng mode, test mode and various vendor specific options to make gddr3 sgram useful for variety of differen t applications. the default value of the mode register is not defined, therefore the mode register must be written after emrs setting for the proper operation. the mode register is written by asserting low on cs , ras , cas and we (the gddr3 sgram should be in active mode with cke already high prior to writing into t he mode register). the state of address pins a0 ~ a11 and ba0, ba1, ba2 in the same cycle as cs , ras , cas and we going low is written in the mode regi ster. minimum clock cycles specified as tmrd are required to complete the write operation in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as l ong as all banks are in the idle state. the mode register is divided into various fields depending on function- ality. the burst length uses a0 ~ a1. cas latency (read latency from column address) uses a2, a6 ~ a4. a7 is used for test mo de. a8 is used for dll reset. a9 ~ a11 are used for write latency. refer to the tabl e for specific codes for various addressing modes and cas latenci es. cas latency a2 a6 a5 a4 cas latency 0000 8 0001 9 0010 10 0011 11 0100 reserved 0101 reserved(5) 0110 reserved(6) 0111 7 1000 12 1001 13 1010 14 1011 15 1100 reserved 1101 reserved 1110 reserved 1111 reserved ba2ba1ba0a11a10a9a8a7a6a5a4a3a2a1a0 test mode a7 mode 0normal 1test burst type a3 burst type 0 sequential 1reserved dll a8 dll reset 0no 1yes rfu 0 0 wl dll tm cas latency bt cl burst length burst length a1 a0 burst length 00 reserved 01 reserved 10 4 11 8 ba1 ba0 an ~ a0 00 mrs 01emrs write latency a11 a10 a9 write latency 0 0 0 reserved 001 1 010 2 011 3 100 4 101 5 110 6 111 7 note : dll reset is self-clearing rfu(reserved for future use) should stay "0" during mrs cycle - 11 - k4j52324ki datasheet gddr3 sgram rev. 1.2 programmable impedance output bu ffer and active terminator the gddr3 sgram is equipped with programmable impedance output buff ers and active terminators. this allows a user to match the driver impedance to the system. to adjust the impedance, an external precision re sistor(rq) is connected between t he zq pin and vss. the value o f the resistor must be six times of the desired output impedance. for example, a 240 resistor is required for an output impedance of 40 . to ensure that output impedance is one sixth the value of rq (within 10 %), the range of rq is 120 to 360 (20 to 60 ) output impedance. mf,sen, res, ck and ck are not internally terminated. ck and /ck will be terminated on the system module using external 1% resisters. the output impedance is updated during all auto refresh commands and nop commands when a read is not in progress to compensate for variati ons in volt- age supply and temperature. the output impedance updates are trans parent to the system. impedance updates do not affect device operation, and all data sheet timing and current specifications are met during update . to guarantee optimum output driver impedance after power-up , the gddr3(x32) needs at least 20us after the cl ock is applied and stable to calibrate the impedance upon power-up. the user may operate the pa rt with less than 20us, but the optimal output impedance is not guaranteed. the value of zq is also used to calibrated the internal address/command ter mination resisters. the two termination values that are selectable during power up are 1/2 of zq and zq. the value of zq is used to calibrate the inter nal dq termination resist- ers. the two termination values that are selectable are 1/4 of zq and 1/2 of zq. burst length read and write accesses to the gddr3 sgram are burst oriented, wi th the burst length being programmable, as shown in mrs table. the burst length determines the maximum number of column locations that can be ac cessed for a given read or write command. reserved states shoul d not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of col umns equal to the burst length is effectively selected. all accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a2-a i when the burst length is set to four (where a i is the most significant column address bit for a given con- figuration). the remaining (least significant) address bit(s) is (are) used to select th e starting location within the block. t he programmable burst length applies to both read and write bursts. burst type accesses within a given burst must be programmed to be sequential; this is referred to as the burst type and is selected via bi t m3. this device does not support the interleaved burst mode found in ddr sgram devices. the ordering of accesses within a burst is determined by the bur st length, the burst type, and the starting column address, as shown in below table: burst definition [ table 1 ] burst definition note : 1. for a burst length of four, a2-a7 select the block of four burst. 2. for a burst length of eight, a3-a7 select the block of eight burst; a2 select the starting column within the block. 3. the value x of a0 and a1 column is "don?t care". burst length starting column address order of accesses within a burst type= sequential 4 a2 a1 a0 0 x x 0 - 1 - 2 - 3 8 a2 a1 a0 0 x x 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 1 x x 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 - 12 - k4j52324ki datasheet gddr3 sgram rev. 1.2 cas latency (read latency) the cas latency is the delay, in clock c ycles, between the registration of a read command and the availability of the first bit of output data. the latency can be set to 7~15 clocks. if a r ead command is registered at clock edge n , and the latency is m clocks, the data will be av ailable nominally coincident with clock edge n + m . below table indicates the operating frequencies at which each c as latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. [ table 2 ] cas latency speed allowable cas latency cl=15 cl=14 cl=12 cl=11 cl=10 1300mhz o - - - - 1200mhz o o - - - 1000mhz o o o - - 800mhz o o o o - 700mhz o o o o o nop nop nop read t0 t5 t7 t7n ck ck command t6 rdqs dq cl = 7 nop nop nop read t0 t6 t8 t8n ck ck command t7 rdqs dq cl = 8 burst length = 4 in the cases shown shown with nominal t ac and nominal t dsdq don?t care transitioning data - 13 - k4j52324ki datasheet gddr3 sgram rev. 1.2 write latency the write latency (wl) is the delay, in clock cycles, between the registration of a write command and the availability of the f irst bit of input data. the latency can be set from 1 to 7 clocks depending in the operat ing frequency and desired current draw. when the write latencies a re set to 1 or 2 or 3 clocks, the input receivers never turn of f when the write command is registered. if a write command is registered at clock edge n , and the latency is m clocks, the data will be available nominally coincident with clock edge n + m . reserved states should not be used as unknown operation or incompatibil- ity with future versions may result. nop nop nop write t0 t1 t3 t3n ck ck command t2 dq wl = 3 nop nop nop write t0 t2 t4 t4n ck ck command t3 dq wl = 4 burst length = 4 in the cases shown don?t care transitioning data wdqs wdqs - 14 - k4j52324ki datasheet gddr3 sgram rev. 1.2 test mode the normal operating mode is selected by issuing a mode register set command with bits a7 set to zero, and bits a0-a6 and a8-a1 1 set to the desired values. test mode is entered by issu ing a mode register set command with bit a7 set to one, and bits a0-a6 and a8-a11 s et to the desired values. test mode functions are specific to each dram manufacturer and its ex act functions are hidden from the user. dll reset the normal operating mode is selected by issuing a mode register set command with bit a7 set to zero, and bits a0-a6 and a8-a11 set to the desired values. a dll reset is initiated by issuing a mode regist er set command with bit a8 set to one, and bits a0-a7 and a9-a 11 set to the desired values. when a dll reset is complete the gddr3 sgram reset bit 8 of the mode register to a zero. after dll reset mrs, power down can not be issued within 10 clock. in case the clock frequency need to be changed after the power-up, 512mb gddr3 doesn?t require dll reset. instead, dll shoul d be disabled first before the frequency changed and then change the clock frequency as needed. after the clock frequency changed, there needed som e time till clock become stable and then enable the dll and then 20k cycle required to lock the dll. figure 1. clock frequency change sequence after the power-up(example) command wait until ck 700mbps 1000mbps emrs dll disable clock stable emrs dll enable 20k cycle for dll locking time ~ ~ ~ ~ ~ ~ ~ ~ any command ck - 15 - k4j52324ki datasheet gddr3 sgram rev. 1.2 7.4 extended mode register set (emrs) the extended mode register stores the data output driver st rength and on-die termination options. the extended mode register is written by asserting low on cs , ras , cas , we and high on ba0(the gddr3 sgram should be in all bank precharge with cke already high prior to writing into the extended mode register). the state of address pins a0 ~ a11 and ba0,ba1,ba2 in the same cycle as cs , ras , cas and we going low are written in the extended mode register. the minimum clock cycles s pecified as tmrd are required to complete the write operation in the extended mode reg ister. 4 kinds of the output driver strength are supported by emrs (a1, a0) code. t he mode register contents can be changed using the same command an d clock cycle requirements during operation as long as all banks are in the idle state. "high" on ba0 is used for emrs. refer to the table fo r specific codes. ba2 ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 dll a6 dll 0 enable 1 disable rfu 0 1 term id ron 0 twr dll twr termination driver strength ba1 ba0 an ~ a0 00 mrs 01emrs addr/cmd termination a11 termination 0 default 1 half of default vendor id a10 vendor id 0off 1on twr a7 a5 a4 twr 000 11 001 13 010 5 011 6 100 7 101 8 110 9 111 10 drive strength a1 a0 driver strength 00 autocal 01 30 10 40 11 50 data termination a3 a2 termination 00 odt disabled *1 01 reserved 10 zq/4 11 zq/2 * zq : resistor connection pin for on-die termination rfu(reserved for future use) should stay "0" during emrs cycle * 1 : all odt will be disabled default value is determined by cke status at the rising edge of reset during power-up ron of pull-up a9 ron 040 160 - 16 - k4j52324ki datasheet gddr3 sgram rev. 1.2 dll enable/disable the dll must be enabled for normal operation. dll enable is r equired during power-up initialization and upon returning to norm al operation after dis- abling the dll for debugging or evaluation. (when the device exits self refresh mode, the dll is enabled automatically.) any ti me the dll is enabled, 20k clock cycles must occur bef ore a read command can be issued. data termination the data termination, dt, is used to determine the value of t he internal data termination resisters. the gddr3 sgram supports 60 and 120 termi- nation. the termination may also be disabled for testing and other purposes. data driver impedance the data driver impedance (dz) is used to determine the val ue of the data drivers impedance. when autocalibration is used the data driver impedance is set to rq/6 and it?s tolerance is determined by the calibration accuracy of the device. when any other value is selected the target impedan ce is set nominally to the desired impedance. however, the accuracy is now determined by the dev ice?s specific process corner, applied vo ltage and operating temperature. manufacturers vendor code and revision identification the manufacturers vendor code, v, is selected by issuing a ext ended mode register set command with bits a10 set to one, and bi ts a0-a9 and a11 set to the desired values. when the v function is enabled th e gddr3 sgram will pr ovide its manufacturers vendor code on dq[ 3:0] and revision identification on dq[7:4] manufacturer dq[7:4] dq[3:0] samsung 2[0010] 1[0001] dqs dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 vendor id 0 0 1 0 0 0 0 1 - 17 - k4j52324ki datasheet gddr3 sgram rev. 1.2 figure 2. vendor id read don?t care transitioning data t0 t1 tb3 tc4 td5 ck ck te 6 ta 2 tf7 res cke cke command dq[3:0] t is t ih t ch t cl t is t ih high vendor code >20ns >20ns 200 cycle t rp t mrd t mrd t mrd t rp precharge all banks emrs vendor_id on mrs 1st auto refresh precharge all banks emrs vendor_id off ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ emrs emrs mrs pre - 18 - k4j52324ki datasheet gddr3 sgram rev. 1.2 7.5 clock frequency change sequen ce during the device operation both existing tck and desired tck are in dll-on mode - change frequency from existing frequency to desired frequency - issue precharge all banks command - issue mrs command to reset the dll while othe r fields are valid and required 20k tck to lock the dll - issue precharge all banks command. issue at least auto-refresh command existing tck is in dll-on mode wh ile desired tck is in dll-off mode - issue precharge all banks command - issue emrs command to disable the dll - issue precharge all banks command - change the frequency from existing to desired. - issue auto-refresh command at least two. issue mrs command clock frequency change in case existing tck is in dll-off mode while desired tck is in dll-on mode - issue precharge all banks command and issue emrs command to disable the dll. - issue precharge all banks command. - change the clock fr equency from existing to desired - issue precharge all banks command. - issue emrs command to enable the dll - issue mrs command to reset the dll and required 20k tck to lock the dll. - issue precharge all banks command. - issue auto-refresh command at least two nop nop nop nop nop nop pre mrs pre nop ar nop tfchg trp frequency change all banks precharge dll reset tmrd all banks precharge 20ktck (dll locking time) ck ck cmd trp all banks precharge dll off tmrd all banks precharge dll reset tmrd trp all banks precharge dll off tmrd all banks precharge - 19 - k4j52324ki datasheet gddr3 sgram rev. 1.2 7.6 boundary scan function general information the 512mb gddr3 incorporates a modified boundary scan test mode as an optional feature. this mode doesn?t operate in accordance with ieee stan- dard 1149.1 - 1990. to save the current gddr3 ball-out, this mode will scan parallel data input and output and the scanned da ta through wdqs0 pin controlled by an add-on pin, sen which is located at v-4 of 136 ball package. for the normal device operation other than boundary scan, there r equired device re-initializati on by device power-off and then power-on. disabling the scan feature it is possible to operate the 512mb gddr3 without using the boundary scan feature. sen(at v-4 of 136 ball package) should be ti ed low(vss) to pre- vent the device from entering the boundary scan mode. the ot her pins which are used for scan mode, res, mf, wdqs0 and cs will be operating at nor- mal gddr3 functionalities when sen is deasserted. figure 3. internal block diagram (reference only) pins under test ck d dq dm0 tie to iogic 0 ck d dq dqs ck d dq dq4 ck d dq rdqs0 res (ssh,scan shift) cs# (sck, scan clock) mf (soe#, output enable) rfu at v-4 (sen, scan enable) wdqs0 (sout,scan out) puts device into scan mode and re-maps pins to scan functionality dedicated scan flops (1per signal under test) the following lists the rest of the signals on the scan chain: dq[3:0], dq[31:6], rdqs[3:1], wdqs[3:1], dm[3:1], rfu, cas , we , cke, ba[2:0], a[11:0], ck, ck and zq two rfu?s(j-2 and j-3 on 136-ball package) will be on the scan chain and will read as a logic "0" the following lists signals not on the scan chain: nc, vdd, vss, vddq, vssq, vref in case zq pin is connected to the external resistor, it will be read as logic "0". however, if the zq pin is open, it will be read as floating. accordi ngly, zq pin should be driven by any signal. - 20 - k4j52324ki datasheet gddr3 sgram rev. 1.2 [ table 3 ] boundary scan exit order note : 1. when the device is in scan mode, the mirror func tion will be disabled and none of the pins are remapped. 2. since the other input of t he mux for dm0 tied to gnd, the device will output t he continuous zeros afte r scanning a bit #67, if the chip stays in scan shift mode. 3. two rfu balls(#57and #58) in the scan order, will be read as a logic"0". [ table 4 ] scan pin description note : 1. when sen is asserted, no commands are to be executed by th e gddr3. this applies to both user commands and manufacturing com mands which may exist while res is deasserted. 2. all scan functionalities are valid only after the appropriate power-up and initialization sequence. (res and cke, to set the odt of the c/a) 3. in scan mode, the odt for the address and control lines set to a nominal termination value of zq. the odt for dq?s will be d isabled. it is not necessary for the termination to be calibrated. 4. in a double-load clam-shell configuration, sen will be asserted to both devices. separate two soe ?s should be provided to top and bo ttom devices to access the scanned output. when either of the devices is in scan mode, soe for the other device which not in a scan will be disabled. bit# ball bit# ball bit# ball bit# ball bit# ball bit# ball 1 d-3 13 e-10 25 k-11 37 r-10 49 l-3 61 g-4 2 c-2 14 f-10 26 k-10 38 t-11 50 m-2 62 f-4 3 c-3 15 e-11 27 k-9 39 t-10 51 m-4 63 f-2 4 b-2 16 g-10 28 m-9 40 t-3 52 k-4 64 g-3 5 b-3 17 f-11 29 m-11 41 t-2 53 k-3 65 e-2 6 a-4 18 g-9 30 l-10 42 r-3 54 k-2 66 f-3 7 b-10 19 h-9 31 n-11 43 r-2 55 l-4 67 e-3 8 b-11 20 h-10 32 m-10 44 p-3 56 j-3 9 c-10 21 h-11 33 n-10 45 p-2 57 j-2 10 c-11 22 j-11 34 p-11 46 n-3 58 h-2 11 d-10 23 j-10 35 p-10 47 m-3 59 h-3 12 d-11 24 l-9 36 r-11 48 n-2 60 h-4 package ball symbol normal function type description v-9 ssh res input scan shift. capture the data input from the pad at logic low and shift the data on the chain at logic high. f-9 sck cs input scan clock. not a true cl ock, could be a single pu lse or series of pulses. all scan inputs will be referenced to rising edge of the scan clock. d-2 sout wdqs0 output scan output. v-4 sen rfu input scan enable. logic high would enable the device into scan mode and will be disabled at logic low. must be tied to gnd when not in use. a-9 soe mf input scan output enable. enables (registered low) and disables (registered high) sout data. this pin will be tied to vdd or g nd through a resistor (typically 1k ) for normal operation. tester needs to overdrive this pi n guarantee the required input logic level in scan mode. - 21 - k4j52324ki datasheet gddr3 sgram rev. 1.2 [ table 5 ] scan dc electrical characteristics and operating conditions note : 1. the parameter applies only when sen is asserted. 2. all voltages referenced to gnd. figure 4. scan capture timing figure 5. scan shift timing parameter/conditon symbol min max units note input high (logic 1) voltage v ih (dc) v ref +0.15 - v 1,2 input low (logic 0) voltage v il (dc) - v ref -0.15 v 1,2 tses tscs tsds tsdh valid low sck sen ssh soe pins under test not a true clock, but a single pulse or series of pulses don?t care sck sen ssh soe sout tses tscs tscs scan out bit 0 scan out bit 1 scan out bit 2 scan out bit 3 tsac tsoh transitioning data - 22 - k4j52324ki datasheet gddr3 sgram rev. 1.2 [ table 6 ] scan ac electrical characteristics note : 1. the parameter applies only when sen is asserted. 2. scan enable should be issued earlier than other scan commands by 3ns. figure 6. scan initialization sequence parameter/conditon symbol min max units note clock clock cycle time tsck 40 - ns 1 scan command time scan enable setup time tses 20 - ns 1,2 scan enable hold time tseh 20 - ns 1 scan command setup time for ssh, soe# and sout tscs 14 - ns 1 scan command hold time for ssh, soe# and sout tsch 14 - ns 1 scan capture time scan capture setup time tsds 10 - ns 1 scan capture hold time tsdh 10 - ns 1 scan shift time scan clock to valid scan output tsac - 6 ns 1 scan clock to scan output hold tsoh 1.5 - ns 1 tath tats tscs tsch tscs tsch tsds tsdh valid tsds tsdh valid tses tsds tsdh valid tscs t = 200us reset at power - up boundary scan mode scan out bit0 tscs vdd vddq vref res (ssh in scan mode) cke (dual-load c/a) cke (quad-load c/a) sen sck soe# sout pins under test note : to set the pre-defined odt for c/a, a boundary scan mode should be issued after an appropriate odt initialization sequence with res and cke signals - 23 - k4j52324ki datasheet gddr3 sgram rev. 1.2 7.7 mirror function the gddr3 sgram provides a mirror functi on (mf) ball to change the physical location of the control lines and all address lines which helps to route devices back to back. the mf ball will affect ras , cas , we , cs and cke on balls h3, f5, h9, f9 and h4 respectively and a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, ba0, ba1 and ba2 on balls k4, h2, k3, m4, k9 , h11, k10, l9, k11, m9, k2, l4, g4, g9 and h10 respectively and only detects a dc input. the mf ball should be tied directly to vss or vdd dependi ng on the control line orientation desired. when the mf ball is tied low the ball orien- tation is as follows, ras - h3, cas - f4, we - h9, cs - f9, cke - h4, a0 - k4, a1 - h2, a2 - k3, a3 - m4, a4 - k9, a5 - h11, a6 - k10, a7 - l9, a8 - k11, a9 - m9, a10 - k2, a11 - l4, ba0 - g4, ba1 - g9 and ba2 - h10. the high condition on the mf ball will change the location of th e control balls as follows; cs - f4, cas - f9, ras - h10, we - h4, cke - h9, a0 - k9, a1 - h11, a2 - k10, a3 - m9, a4 - k4, a5 - h2, a6 - k3, a7 - l4, a8 - k2, a9 - m4, a10 - k11, a11 - l9, ba0 - g9, ba1 - g4 and ba2 - h3. [ table 7 ] mirror function signal mapping pin mf logic state high low ras h10 h3 cas f9 f4 we h4 h9 cs f4 f9 cke h9 h4 a0 k9 k4 a1 h11 h2 a2 k10 k3 a3 m9 m4 a4 k4 k9 a5 h2 h11 a6 k3 k10 a7 l4 l9 a8 k2 k11 a9 m4 m9 a10 k11 k2 a11 l9 l4 ba0 g9 g4 ba1 g4 g9 ba2 h3 h10 - 24 - k4j52324ki datasheet gddr3 sgram rev. 1.2 7.8 commands below truth table-commands provides a quick reference of available commands. this is fo llowed by a verbal description of each c ommand. two addi- tional truth tables appear following the operation section : t hese tables provide current state/next state information. [ table 8 ] truth table - commands [ table 9 ] truth table - dm operation note : 1. cke is high for all commands except self refresh. 2. ba0~ba1 select either the mode register or the extended mode register (ba0=0, ba1=0 select the mode register; ba0=1, ba1=0 select extended mode register; other combinati ons of ba0~ba1 are reserved). a0~a11 provide the op-code to be written to the selected mode register. 3. ba0~ba2 provide bank address and a0~a11 provide row address. 4. ba0~ba2 provide bank address; a0~a7 and a9 provide co lumn address; a8 high enables the auto precharge feature (non persistent) , and a8 low disables the auto precharge feature. 5. a8 low : ba0~ba2 determine which bank is precharged. a8 high : all banks are precharged and ba0~ba2 are "don?t care." 6. this command is auto refresh if ck e is high, self refresh if cke is low. 7. internal refresh counter contro ls row addressing; all inputs and i/os are "don?t care" except for cke. 8. deselect and nop are functionally interchangeable. 9. cannot be in powerdown or self-refresh state. 10. used to mask write data ; provided coincident with the corresponding data. 11. except data termination disable. name (function) cs ras cas we addr note deselect (nop) h x x x x 8, 11 no operation (nop) l h h h x 8 active (select bank and activate row) l l h h bank/row 3 read (select bank and column, and start read burst) l h l h bank/col 4 write (select bank and column, and start write burst) l h l l bank/col 4 precharge (deactivate row in bank or banks) l l h l code 5 auto refresh or self refresh (enter self refresh mode) l l l h x 6, 7 load mode register l l l l op-code 2 data terminator disable x h l h x name (function) dm dqs note write enable l valid write inhibit h x 10 - 25 - k4j52324ki datasheet gddr3 sgram rev. 1.2 deselect the deselect function (cs high) prevents new commands from being executed by th e gddr3(x32). the gddr3(x32) sgram is effectively dese- lected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to inst ruct selected gddr3(x32) to perform a nop (cs low). this prevents unwanted commands from being registered during idle or wait states. o perations already in progress are not affected. load mode register the mode registers are loaded via inputs a0-a11. see mode register descriptions in the register definition section. the load mo de register command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tmrd is met. active the active command is used to open (or activate) a row in a partic ular bank for a subsequent access. the value on the ba0,ba1, ba2 inputs selects the bank, and the address provided on inputsa0-a11 selects the row. this row remains active (or open) for accesses until a prec harge command is issued to that bank. a precharge command must be is sued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1, ba2 inputs selects the ba nk, and the address provided on inputs a0-a7, a9 selects the starting column locati on. the value on input a8 determines whether or not auto prechar ge is used. if auto pre- charge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1, ba2 inputs selects the bank, and the address provided on inputs a0-a7, a9 selects the starting column locati on. the value on inputs a8 determines whether or not auto precha rge is used. if auto pre- charge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dm input logic level app earing coincident with the data. if a given dm signal is registered lo w. the corresponding data will be written to memory; if the dm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a pa rticular bank or the open row in all banks. the bank(s) will be available for a sub- sequent row access a specified time (t rp ) after the precharge command is issued. input a8 determines whether one or all banks are to be pre- charged, and in the case where only one banks are to be precharged, inputs ba0,ba1,ba2 select the bank. otherwise ba0, ba1,ba2 are treated as "don?t care." once a bank has been precharged, it is in the idle state and must be activated prior to any read or write comman d will be treated as a nop if there is no open row is already in the process of precharging. - 26 - k4j52324ki datasheet gddr3 sgram rev. 1.2 auto precharge auto precharge is a feature which performs the same individual- bank precharge function described ab ove, but without requiring a n explicit command. this is accomplished by using a8 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically perfo rmed upon completion of the read or write burst. auto precharge is nonpersis- tent in that it is either enable or disabled for each individual read or write command. auto precharge ensures that the prechar ge is initiated at the ear- liest valid state within a burst. this "earliest valid stage" is determined as if an explicit pr echarge command was issued at t he earliest possible time, without violating t ras(min) , as described for each burst type in the o peration section of this data sheet. the us er must not issue another command to the same bank until the precharge time(t rp ) is completed. auto refresh auto refresh is used during normal operation of the gddr3 sgram and is analogous to cas -before-ras (cbr) refresh in fpm/edo drams. this command is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the interna l refresh controller. this makes the address bits a "don?t care" during an auto refresh command. the 512mb(x32) gddr3 requires auto refresh cycles at an a verage interval of 3.9us (maximum). a maximum auto refresh commands can be posted to any given gddr3( x32) sgram, meaning that the maximum absolute interval betwee n any auto refresh command and the next auto refresh command is 9 x 3.9us(35.1us ). this maximum absolute interval is to allow gddr3(x32) s gram output drivers and internal terminators to automatically recalibrate compensati ng for voltage and temperature changes. self refresh the self refresh command can be used to retain data in the gddr3(x32) sgram ,even if the rest of the system is powered down. se lf refresh command can be issued only in case all banks are in precharge state. when in the self refresh mode, the gddr3(x32) sgram retai ns data without external clocking. the self refresh command is initiated like an auto refresh command ex cept cke is disabled (low). the dll is automati- cally disabled upon entering self refresh and is automatically ena bled and reset upon exiting self refresh. the active terminat ion is also dis- abled upon entering self refresh and enabled upon exiting self refresh. (20k clock cycles must t hen occur before a read command can be issued). input signals except cke are "don?t care" during self refresh. the procedure for exiting self refresh requires a sequence of co mmands. first, ck and ck must be stable prior to cke going back high. once cke is high ,the gddr3(x32) must have nop commands issued for txsnr because t ime is required for the completion of any internal refresh in progre ss. a simple algorithm for meeting both refresh, dll requiremen ts and out-put calibration is to apply nops for 20k clock cycles before appl ying any other command to allow the dll to lock and the output drivers to recalib rate. * once the device enters the power down mode, it should be in no p state at least for 10ns. the minimum duration for the power down mode once cke brought to down should be at least 10ns. command cke t xsnr self refresh ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ck ck ~ ~ ~ ~ ~ ~ read t xsr active t is t ih - 27 - k4j52324ki datasheet gddr3 sgram rev. 1.2 data terminator disable (bus snooping for read command) the data terminator disable command is detected by the device by snooping the bus for read commands excluding /cs. the gddr3 d ram will disable its data terminators when a r ead command is detected. the terminators are disable cl-1 clocks after the read comma nd is detected. in a two rank system both dram devices will s noop the bus for read commands to either devi ce and both will disable their terminators if a read command is detected. the command and address terminators and always enabled. on-die termination bus snooping for read commands other than /cs is used to cont rol the on-die termination in the dual load configuration. the gd dr3 sgram will dis- able the on-die termination when a read command is detected, regardless of the state of /cs, when the odt for the dq pins are set for dual loads (120 ). the on-die termination is disabled x cl ocks after the read command where x equals cl-1 and stay off for a duration of bl/2 + 2, as below figure, data termination disable timing. in a two-rank system, both dram devices snoop the bus for read commands to either device and both will disable the on- die termination if a read command is detected. the on-die termi nation for all other pins on the device are always on for both a si ngle-rank system and a dual-rank system. the on-die termination value on address and c ontrol pins is determined during power-up in relation to the state of cke on the first transition of reset. on the rising edge of reset, if cke is sampled low, then the c onfiguration is determined to be a single-rank system. the on-die termination is then set to one-half zq for the address pins. on t he rising edge of reset, if cke is sampled high, then the configuration is determined to be a dual-rank system. the on-die termination for the dqs, wdqs , and dm pins is set in the emrs. note : 1. do n = data-out from column n . 2. burst length = 4. 3. three subsequent elements of data-out appear in the specified order following do n . 4. shown with nominal t ac and t dqsq . 5. rdqs will start driving high one-half cycle prior to the first falling edge. 6. the data terminators are disabled star ting at cl-1 and the duration is bl/2 + 2 7. reads to either rank disable both ranks? termination regardless of the logic level of /cs. figure 7. data termination disable timing nop nop nop nop nop read t0 t7 t8 t8n t9 t9n t10 t11 ck ck command address rdqs dq bank a, col n cl = 8 do n dq termination gddr3 data termination is disabled don?t care transitioning data - 28 - k4j52324ki datasheet gddr3 sgram rev. 1.2 7.9 operations 7.9.1 bank/row activation figure 8. example : meeting t rcd before any read or write commands can be issued to a banks within the gddr3 sgram, a row in that bank must be "opened." this is ac complished via the active command, which selects both the bank and the row to be activated. after a row is opened with an active command, a read or write command may be issued to that row, subject to the t rcd specification. t rcd(min) should be divided by the clock per iod and rounded up to the next whole number to determine the earliest clock edge after the active command in which a read or write command can be entered. for example, a t rcd specification of 14ns with a 700mhz clock (1.4ns period) results in 10 clocks. this is reflected in be low figure, which covers any case where 10 - 30 - k4j52324ki datasheet gddr3 sgram rev. 1.2 figure 9. data output timing (1) - t dqsq , t qh and data valid window note : 1. t dqsq represents the skew between the 8 dq lines and the respective rdqs pin. 2. t dqsq is derived at each rdqs clock edge and is not cumulative over time and begins with first dq transition and ends with the last valid transition of dqs. 3. t dqhp is the lesser of tdqsl or tdqsh strobe tr ansition collectively when a bank is active. 4. the data valid window is derived for eac h rdqs transitions and is defined by t dv . 5. there are 4 rdqs pins for this device with rdqs0 in relation to dq0-dq7, rdqs1 in relation dq8-dq15, rdqs2 in relation to dq 16-24 and rdqs3 in relation to dq25-dq31. 6. this diagram only represents one of the four byte lanes. figure 10. data output timing (2) - t dqsq , t qh and data valid window t0 t1 t2 t2n t3 t3n t4 ck ck rdqs 1.5 dq(last data valid) dq(first data no longer valid) all dqs and rdqs, collectively 4 t ch t dqsq 2 (max) t cl t2 t2n t3 t3n t2 t2n t3 t3n t2 t2n t3 t3n t dqsq 2 (min) t dqsq 2 (min) t dqsq 2 (max) t dqsh 3 t dqsl 3 t dv 3 t dv 3 t dv 3 t dv 3 t0 t1 t2 t2n t3 t3n t4 ck ck rdqs 1.5 all dqs and rdqs, collectively 4 t2 t2n t3 t3n t dqsl 3 t dqsh 3 t2 t2n t3 t3n t dqsck (max) t dqsl 3 t dqsh 3 t dqsck (min) all dqs and rdqs, collectively 4 rdqs 1.5 t ch t cl - 31 - k4j52324ki datasheet gddr3 sgram rev. 1.2 note : 1. do n =data-out from column n . 2. burst length = 4 3. three subsequent elements of data-out appear in the programmed order following dq n . 4. shown with nominal t ac and t dqsq. 5. rdqs will start driving high 1/2 clock cycle prior to the first falling edge. figure 11. read burst nop nop nop nop nop read t0 t7 t8 t9 t9n t10 t11 command address rdqs dq bank a, col n cl = 9 do n don?t care transitioning data nop nop nop nop nop read t0 t7 t8 t8n t9 t9n t10 t11 ck ck command address rdqs dq bank a, col n cl = 8 do n ck ck - 32 - k4j52324ki datasheet gddr3 sgram rev. 1.2 note : 1. do n (or b ) = data-out from column n (or column b ). 2. burst length = 4 3. three subsequent elements of data-out appear in the programmed order following dq n . 4. three subsequent elements of data-out appear in the programmed order following dq b . 5. shown with nominal t ac and t dqsq. 6. rdqs will start driving high one half-clock cycle prior to the first falling edge of rdqs. figure 12. consecutive read burst nop read nop nop nop read t0 t7 t8 t8n t9 t10 command address rdqs dq bank a, col n cl = 8 do n bank a, col b t10n t9n do b don?t care transitioning data t2 ck ck - 33 - k4j52324ki datasheet gddr3 sgram rev. 1.2 note : 1. do n (or b ) = data-out from column n (or column b ). 2. burst length = 4 3. three subsequent elements of data-out appear in the programmed order following dq n . 4. three subsequent elements of data-out appear in the programmed order following dq b . 5. shown with nominal t ac and t dqsq. 6. example applies when read commands are issued to different devices or nonconsecutive reads. 7. rdqs will start driving high one half-clock cycle prior to the first falling edge of rdqs. figure 13. nonconsecutive read burst nop nop nop read nop read t0 t7 t8 t8n t9 t9n t10 t17 command address rdqs dq bank a, col n cl = 8 do n bank a, col b t17n t18 nop do b don?t care transitioning data ck ck - 34 - k4j52324ki datasheet gddr3 sgram rev. 1.2 note : 1. do n (or x or b or g ) = data-out from column n (or column x or column x or column b or column g ). 2. burst length = 4 3. n ? or x or b ? or g ? indicates the next data-out following do n or do x or do b or do g , respectively 4. reads are to an active row in any bank. 5. shown with nominal t ac and t dqsq. 6. rdqs will start driving high one half-clock cycle prior to the first falling edge of rdqs. figure 14. random read accesses don?t care transitioning data nop nop read nop nop read t0 t1 t2 t8 t8n t9 t10 ck ck command address rdqs dq bank a, col n cl = 8 do n bank a, col b t10n t9n do b do n do n do n - 35 - k4j52324ki datasheet gddr3 sgram rev. 1.2 note : 1. do n = data-out from column n . 2. di b = data-in from column b . 3. burst length = 4 4. one subsequent element of data-out appears in the programmed order following do n . 5. data-in elements are applied following di b in the programmed order. 6. shown with nominal t ac and t dqsq. 7. t dqss in nominal case. 8. rdqs will start driving high one half-clock cycle prior to the first falling edge of rdqs. 9. the gap between data termination enable to the first data-in should be greater than 1tck figure 15. read to write don?t care transitioning data nop nop write nop nop read t0 t7 t8 t9 t9n t10 t11 ck command address rdqs dq bank col n cl = 8 dm t8n do n di b t wl = 4 wdqs dq nop t12 t12n bank a, col b 1tck < termination dq termination disabled dq termination enabled ck - 36 - k4j52324ki datasheet gddr3 sgram rev. 1.2 note : 1. do n (or b ) = data-out from column n (or column b ). 2. burst length = 4 3. three subsequent elements of data-out appear in the programmed order following dq n. 4. three subsequent elements of data-out appear in the programmed order following dq b . 5. shown with nominal t ac and t dqsq. 6. example applies when read commands are issued to different devices or nonconsecutive reads. 7. rdqs will start driving high one half-clock cycle prior to the first falling edge of rdqs. 8. the minimum delay from a read to a precharge command is bl/2. figure 16. read to precharge don?t care transitioning data nop nop pre nop act read t0 t1 t2 t8 t8n t9 t10 ck ck command address rdqs dq bank a, col n cl = 8 do n bank a, (a or all) t9n bank a, row t rp bl/2 - 37 - k4j52324ki datasheet gddr3 sgram rev. 1.2 7.9.3 writes write bursts are initiated with a write command, as shown in figure. the starting column and bank addresses are provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row bei ng accessed is precharged at the completion of the burst. for the generic write commands used in the foll owing illustrations, auto precharge is disabled. during write bursts, the first valid data-in element wi ll be registered in a rising edge of wdqs following the write latency set in the mode register and subs equent data elements will be registered on successive edges of wdqs. prior to the first valid wdqs edge a half cycle is needed and specified as the write pre- amble; the half cycle in wdqs following the last data-in element is known as the write postamble. the time between the write command and the first valid falling edge of wdqs (t dqss ) is specified with a relative to the write latency. all of the write diagrams show the nominal case, and where the two extreme cases (i.e., t dqss(min) and t dqss(max) ) might not be intuitive, they have also been included. write burst fig- ure shows the nominal case and the extremes of td qss for a burst of 4. upon completion of a burst, assuming no other commands have been initiated, the dq s will remain high-z and any additional input data will be ignored. data for any write burst may not be truncated with a subsequent write command. the new write command can be issued on any positive edge of clock following the previous write command after the burst has completed. the new write command should be issued x cycles after the first write command should be equals the number of desired nibbles (nibbles are required by 4n-prefetch architec- ture). an example of nonconsecutive writes is shown in nonconsecutive write to read figure. full-speed random write accesses within a page or pages can be performed as shown in random write cycles fig- ure. data for any write burst may be followed by a subsequent read command. data for any write burst may be followed by a subsequent precharge command. to follow a write the write burst, t wr should be met as shown in write to precharge figure. data for any write burst can not be tr uncated by a subsequent precharge command. ck ck ca en ap dis ap ba cs ras cas we a0-a7, a9 a10, a11 a8 ba0,1,2 cke high write command ca = column address ba = bank address en ap = enable auto precharge dis ap = disable auto precharge don?t care - 38 - k4j52324ki datasheet gddr3 sgram rev. 1.2 note : 1. di b = data-in for column b. 2. three subsequent elements of data-in are applied in the programmed order following di b. 3. a burst of 4 is shown. 4. a8 is low with the write command (auto precharge is disabled). 5. write latency is set to 4 figure 17. write burst nop nop nop nop nop write t0 t1 t2 t3 t3n t4 t5 ck ck command address bank a, col b t dqss nop t4n t5n t6 dq dm di b wdqs di b di b t dqss (nom) dq dm wdqs t dqss (min) dq dm wdqs t dqss (max) t dqss t dqss don?t care transitioning data - 39 - k4j52324ki datasheet gddr3 sgram rev. 1.2 note : 1. di b , etc. = data-in for column b , etc. 2. three subsequent elements of data-in are applied in the programmed order following di b . 3. three subsequent elements of data-in are applied in the programmed order following di n . 4. burst of 4 is shown. 5. each write command may be to any bank of the same device. 6. write latency is set to 3 figure 18. consecutive write to write don?t care transitioning data nop nop write nop nop write t0 t1 t3 t3n t4 t5 ck ck command address bank col b t dqss (nom) nop t4n t5n t6 dq dm wdqs t2 t6n t7 nop di b di n bank col n - 40 - k4j52324ki datasheet gddr3 sgram rev. 1.2 note : 1. di b, etc. = data-in for column b, etc. 2. three subsequent elements of data-in are applied in the programmed order following di b. 3. three subsequent elements of data-in are applied in the programmed order following di n. 4. burst of 4 is shown. 5. each write command may be to any bank. 6. write latency is set to 3 figure 19. nonconsecutive write to write don?t care nop nop nop write nop write t0 t1 t3 t3n t4 t5 ck ck command address bank, col b nop t4n t5n t6 dq dm di b wdqs t2 t6n t7 nop di n bank, col n t dqss (nom) don?t care transitioning data - 41 - k4j52324ki datasheet gddr3 sgram rev. 1.2 note : 1. di b , etc. = data-in for column b , etc. 2. three subsequent elements of data-in are applied in the programmed order following di b . 3. three subsequent elements of data-in are applied in the programmed order following di n . 4. burst of 4 is shown. 5. each write command may be to any bank of the same device. 6. write latency is set to 3 figure 20. randum write cycles don?t care transitioning data nop nop write nop nop write t0 t1 t3 t3n t4 t5 ck ck command address bank col b t dqss (nom) nop t4n t5n t6 dq dm wdqs t2 t6n t7 nop di b di n bank col n - 42 - k4j52324ki datasheet gddr3 sgram rev. 1.2 note : 1. di b = data-in for column b . 2. three subsequent elements of data-in the programmed order following di b. 3. a burst of 4 is shown. 4. t cdlr is referenced from the first positive ck edge after the last data-in pair. 5. the read and write commands are to the same device. however, the read and write commands may be to different devices, in wh ich case t cdlr is not required and the read command could be applied earlier. 6. a8 is low with the write command (auto precharge is disabled). 7. write latency is set to 3 figure 21. write to read don?t care transitioning data nop nop nop nop nop write t0 t1 t3 t3n t4 t5 ck ck command address bank col b t dqss nop t4n t6 dq dm wdqs t2 t10 read di b t17 t18 nop nop t dqss (nom) bank a. col n cl = 8 rdqs t dqss dq dm wdqs di b do n t dqss (min) cl = 8 rdqs do n t dqss dq dm wdqs di b do n t dqss (max) cl = 8 rdqs tcdlr = 5 t18n - 43 - k4j52324ki datasheet gddr3 sgram rev. 1.2 note : 1. di b = data-in for column b . 2. three subsequent elements of data-in the programmed order following di b . 3. a burst of 4 is shown. 4. a8 is low with the write command (auto precharge is disabled). 5. write latency is set to 3 figure 22. write to precharge don?t care transitioning data nop nop nop nop nop write t0 t1 t3 t3n t4 t5 ck ck command address bank col b t dqss nop t4n t8 dq dm wdqs t2 t9 pre di b t10 t11 nop nop t dqss (nom) bank (a or all) t dqss dq dm wdqs di b t dqss (min) t dqss dq dm wdqs di b t dqss (max) t wr t rp - 44 - k4j52324ki datasheet gddr3 sgram rev. 1.2 7.9.4 precharge * once the device enters the power down mode, it should be in no p state at least for 10ns. the minimum duration for the power down mode once cke brought to down should be at least 10ns. figure 23. power-down the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available fo r a subsequent row access some specified time (t rp ) after the precharge command is issued. input a8 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1, ba2 select the bank. when all banks are to be precharged, inputs ba0, ba1, ba2 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to the bank. 7.9.5 power-down (cke not active) unlike sdr sgrams,gddr3(x32) sgram requires cke to be active at all times an access is in progress; from the issuing of a read or write command until completion of the burst. for reads, a burst completion is defined when the read postambl e is satisfied; for writes, a burst comple- tion is defined bl/2 cycles after t he write postamble is satisfied. power-down is entered when cke is registered low. if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding ck,/ck and c ke. for maximum power savings, the user has the option of disabling the dll prior to entering power-down. however, power-down duration is lim- ited by the refresh requirements of the device, so in most applications, the self-refresh mode is pre- ferred over the dll-disabled power-down mode. when in power-down, cke low and a stable clock signal must be maintained at the inputs of the gddr3 sgram, while all other input signals are ?d on?t care? except data terminator disable com- mand. the power-down state is synchronously exited when cke is registered high (in conjunction with a nop or deselect command). a valid executable command may be applied tpdex later. all banks one bank ba cs ras cas we a0-a7, a9-a11 ba0,1,2 ba=bank address ck ck cke high a8 (if a8 is low; otherwise "don?t care") precharge command don?t care nop nop nop valid t 0 t 1 ta 0 ta 1 ta 2 ck ck command valid ta 7 t2 cke t is t pdex t is no pead/write access in progress * enter power - down mode exit power - down mode - 45 - k4j52324ki datasheet gddr3 sgram rev. 1.2 7.10 gddr3 tfaw definition for eight banks gddr3 devices, ther e is a need to limit the number of activates in a rolling window to ensure that the instanta neous current supplying capability of the devices is not exceeded. to reflect the true capability of t he dram instantaneous current supply, the same pa rameter tfaw(four activate window) as ddr2 is defined. eight bank device sequential bank activation re striction: no more than 4 banks may be activated in a rolling tfaw window. conve rting to clocks is done by dividing tfaw(ns) by tck(ns) and rounding up to next integer value. as an example of the rolling window, if (tfaw/tck) round s up to 10 clocks, and an activate command is issued in clock n, no more than three fu rther activate commands may be issued in clocks n+1 through n+9. t rrd clk act t rrd t rrd t rrd t rrd t rrd cmd t faw t faw + 3*t rrd act act act act act act act - 46 - k4j52324ki datasheet gddr3 sgram rev. 1.2 8. truth table [ table 10 ] clock enable (cke) note : 1. cken is the logic state of cke at clock edge n ; cken-1was the state of cke at the previous clock edge. 2. current state is the state of the gddr3(x32) immediately prior to clock edge n . 3. commandn is the command registered at clock edge n , and action n is a result of command n 4. all state and sequence not shown are illegal or reserved. 5. deselect or nop commands should be issued on any clock edges occurring during the t xsa period. cken-1 cken current state commandn actionn note ll power-down x maintain power-down self refresh x maintain self refresh lh power-down deselect or nop exit power-down self refresh deselect or nop exit self refresh 5 hl all banks idle deselect or nop precharge power-down entry bank(s) active deselect or nop active power-down entry all banks idle auto refresh self refresh entry - 47 - k4j52324ki datasheet gddr3 sgram rev. 1.2 [ table 11 ] current state bank n - command to bank n note : 1. this table applies when cke n-1 was high and cke n is high (see cke truth table) and after t xsnr has been met (if the previous state was self refresh). 2. this table is bank-specific, except w here noted (i.e., the current state is for a specific bank and the commands shown are t hose allowed to be issued to that bank when in that state). exceptions are covered in the notes below. 3. current state definitions : idle : the bank has been precharged, and t rp has been met. row active : a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read : a read burst has been initiated, with auto precharge disabled. write : a write burst has been initiated, with auto precharge disabled. 4. the following states must not be interrupted by a command issued to the same bank. command inhibit or nop commands, or allow able commands to the other bank should be issued on any clock edge occurring du ring these states. allowable commands to the other bank are determined by its c urrent state and truth table- current state bank n command to bank n . and according to truth table - current state bank n -command to bank m. precharging : starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating : starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the :row active" state. read w/ auto- : starts with registration of an read command with auto precharge enabled and ends precharge enabled when trp has been met. once t rp is met, the bank will be in the idle state. write w/ auto- : starts with registration of a write command with auto precharge enabled and ends precharge enabled when t rp has been met. once t rp is met, the bank will be in the idle state. 5. the following states must not be interrupted by any execut able command ; command inhibit or nop commands must be applied on each positive clock edge during these states. refreshing : starts with registration of an auto refresh command and ends when t rc is met. once t rc is met, the gddr3(x32) will be in the all banks idle state. accessing mode : starts with registration of a load mode register command and ends when t mrd has been met. once t mrd is met, the gddr3(x32) sgram will be in the all banks idle state. precharge all : starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state. read or write : starts with registration of the active command and ends the last valid data nibble. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specific; requires that all banks are idle, and bursts are not in progress. 8. may or may not be bank-specific ; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or write s with auto precharge disabled. 10. requires appropriate dm masking. 11. a write command may be applied after the completion of the read burst. current state cs ras cas we command/ action note any h x x x deselect (nop/ continue previous operation) l h h h no operation (nop/continue previous operation) x h l h data terminator disable idle l l h h active (select and activate row) l l l h auto refresh 7 row active l l l l load mode register 7 l h l h read (select column and start read burst) 9 l h l l write (select column and start write burst) 9 l l h l precharge (deactivate row in bank or banks) 8 read (auto-precharge disable) l h l h read (select column and start new read burst) 9 l h l l write (select column and start write burst) 9, 11 l l h l precharge (only after the read burst is complete) 8 write (auto-precharge disabled) l h l h read (select column and start read burst) 9, 10 l h l l write (select column and start new write burst) 9 l l h l precharge (only after the write burst is complete) 8, 10 - 48 - k4j52324ki datasheet gddr3 sgram rev. 1.2 [ table 12 ] current state bank n - command to bank m note : 1. this table applies when cke n-1 was high and cke n is high (see truth table- cke ) and after t xsnr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m , assuming that bank m is in such a state that the given comm and is allowable). exceptions are covered in the notes below. 3. current state definitions : idle : the bank has been precharged, and t rp has been met. row active : a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read : a read burst has been initiated, with auto precharge disabled. write : a write burst has been initiated, with auto precharge disabled. read w/ auto- precharge enabled : see following text write w/ auto- precharge enabled : see following text 3a. the read with auto precharge enabled or write with auto pr echarge enabled states can each be broken into two parts : the access period and the precharge period. for read with auto precharge, the precharge period is defined as if the same burst was executed wit h auto precharge disabled and th en followed with the earliest possible precharge command that still accesses all of the data in the burst. for write with auto precharge, the precharge period begins when twr ends, with twr command and ends where the precharge period (or t rp ) begins. during the precharge period of the read with au to precharge enabled or write with auto precharge enabled states, active, precharge, read and write commands to the other bank may be applied. in either case, all other related limitati ons apply (e.g., contention between read data write data must be avoided). 3b. the minimum delay from a read or write command with auto precharge enabled, to a command to a different bank is summarized below. current state cs ras cas we command/ action note any h x x x deselect (nop/ continue previous operation) l h h h no operation (nop/con tinue previous operation) x h l h data terminator disable idle x x x x any command otherwise allowed to bank m row activating, active or prechrging l l h h active (select and activate row) l h l h read (select column and start read burst) 6 l h l l write (select column and start write burst) 6 l l h l precharge read (auto-precharge disable) l l h h active (select and activate row) l h l h read (select column and start new read burst) 6 l h l l write (select column and start write burst) 6 l l h l precharge write (auto-precharge disabled) l l h h active (select and activate row) l h l h read (select column and start read burst) 6, 7 l h l l write (select column and start new write burst) 6 l l h l precharge read (with auto-precharge) l l h h active (select and activate row) l h l h read (select column and start new read burst) 6 l h l l write (select column and start write burst) 6 l l h l precharge write (with auto-precharge) l l h h active (select and activate row) l h l h read (select column and start read burst) 6 l h l l write (select column and start new write burst) 6 l l h l precharge - 49 - k4j52324ki datasheet gddr3 sgram rev. 1.2 4. auto refresh and load mode register commands may only be issued when all banks are idle. 5. all states and sequences not shown are illegal or reserved. 6. reads or writes listed in the command/action column incl ude reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 7. requires appropriate dm masking. from command to command minimum delay (with concurrent auto precharge) write w/ap read or read w/ap [wl + (bl/2)] tck + twr write or write w/ap (bl/2) * tck precharge 1 tck active 1 tck read w/ap read or read w/ap (bl/2) * tck write or write w/ap [cl + (bl/2)] - wl * tck + 2 tck precharge 1 tck active 1 tck - 50 - k4j52324ki datasheet gddr3 sgram rev. 1.2 9. ac & dc operating conditions 9.1 absolute maximem ratings note : stresses greater than those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stre ss rating only, and functional operation of the device at these or any other conditions above those indica ted in the operational sections of this specification is not i mplied. exposure periods may affect reliability. 9.2 power & dc operating conditions recommended operating conditions (voltage referenced to 0 c tc 85 c) note : 1. under all conditions, v ddq must be less than or equal to v dd . 2. v ref is expected to equal 70% of v ddq for the transmitting device and to track variations in the dc level of the same. peak-to-peak noise on v ref may not exceed + 2 percent of the dc value. thus, from 70% of v ddq , v ref is allowed + 25mv for dc error and an additional + 25mv for ac noise. 3. the dc values define where the input slew rate requirements ar e imposed, and the input signal must not violate these levels in order to maintain a valid level. the inputs require the ac value to be achieved during signal transition ed ge and the driver should achieve the same slew rate through the ac values. 4. input and output slew rate =3v/ns. if the input slew rate is less than 3v/ns, input timing may be compromised. all slew rate are measured between vih(ac) and vil(ac). dq and dm input slew rate must not deviate from dqs by more than 10%. if the dq,dm and dqs slew rate is less than 3v/ns, timin g is longer than referenced to the mid-point but to the vil(ac) maximum and vih(ac) minimum points. 5. vih overshoot: vih(max) = vddq + 0.5v for a pulse width 500ps and the pulse width can not be greater than 1/3 of the cycle rate. vil undershoot: vil(min)=0.0v for a pulse width 500ps and the pulse width can not be greater than 1/3 of the cycle rate. parameter symbol value unit voltage on any pin relative to vss vin, vout -0.5 ~ vddq + 0.5v v voltage on vdd supply relative to vss vdd -0.5 ~ 2.5 v voltage on vddq supply relative to vss vddq -0.5 ~ 2.5 v max junction temperature tj +125 c storage temperature tstg -55 ~ +150 c power dissipation pd 4 w short circuit output current ios 50 ma parameter symbol min typ max unit note device supply voltage v dd 1.7 1.8 1.9 v1 output supply voltage v ddq 1.7 1.8 1.9 v 1 reference voltage v ref 0.69*v ddq - 0.71*v ddq v2 dc input logic high voltage v ih (dc) v ref +0.15 --v3 dc input logic low voltage v il (dc) -- v ref -0.15 v3 output logic low voltage v ol (dc) - - 0.76 v ac input logic high voltage v ih (ac) v ref +0.25 - - v 3,4,5 ac input logic low voltage v il (ac) -- v ref -0.25 v 3,4,5 input leakage current any input 0v- - 52 - k4j52324ki datasheet gddr3 sgram rev. 1.2 9.6 dc characteristics (0 c tc 85 c ; vdd=1.8v + 0.1v, vddq=1.8v + 0.1v ) note : 1. measured with outputs open and odt off 2. refresh period is 32ms 3. vih(ac) and vil(ac) (0 c tc 85 c ; vdd=1.8v + 0.1v, vddq=1.8v + 0.1v ) note : 1. measured with outputs open and odt off 2. refresh period is 32ms 3. vih(ac) and vil(ac) parameter symbol test condition version unit note -hc7a -hc08 operating current (one bank active) icc1 burst length=4 trc trc(min) iol=0ma, tcc= tcc(min) 380 360 ma 1 precharge standby current in power-down mode icc2p cke vil(max), tcc= tcc(min) 95 90 ma 1,3 precharge standby current in non power-down mode icc2n cke vih(min), cs vih(min), tcc= tcc(min) 170 160 ma 1,3 active standby current power-down mode icc3p cke vil(max), tcc= tcc(min) 130 125 ma 1,3 active standby current in in non power-down mode icc3n cke vih(min), cs vih(min), tcc= tcc(min) 290 280 ma 1,3 operating current (burst mode) icc4 iol=0ma ,tcc= tcc(min), page burst, all banks activated. 660 630 ma 1 refresh current icc5 trc trfc 360 350 ma 1,2 self refresh current icc6 cke 0.2v 20 20 ma 1 operating current (4bank interleaving) icc7 burst length=4 trc trc(min) iol=0ma, tcc= tcc(min) 760 720 ma 1 parameter symbol test condition version unit note -hc1a operating current (one bank active) icc1 burst length=4 trc trc(min) iol=0ma, tcc= tcc(min) 340 ma 1 precharge standby current in power-down mode icc2p cke vil(max), tcc= tcc(min) 85 ma 1,3 precharge standby current in non power-down mode icc2n cke vih(min), cs vih(min), tcc= tcc(min) 140 ma 1,3 active standby current power-down mode icc3p cke vil(max), tcc= tcc(min) 120 ma 1,3 active standby current in in non power-down mode icc3n cke vih(min), cs vih(min), tcc= tcc(min) 260 ma 1,3 operating current ( burst mode) icc4 iol=0ma ,tcc= tcc(min), page burst, all banks activated. 580 ma 1 refresh current icc5 trc trfc 310 ma 1,2 self refresh current icc6 cke 0.2v 20 ma 1 operating current (4bank interleaving) icc7 burst length=4 trc trc(min) iol=0ma, tcc= tcc(min) 660 ma 1 - 53 - k4j52324ki datasheet gddr3 sgram rev. 1.2 (0 c tc 85 c ; vdd=1.8v + 0.1v, vddq=1.8v + 0.1v) note : 1. measured with outputs open and odt off 2. refresh period is 32ms 3. vih(ac) and vil(ac) parameter symbol test condition version unit note -hc12 -hc14 operating current (one bank active) icc1 burst length=4 trc trc(min) iol=0ma, tcc= tcc(min) 320 300 ma 1 precharge standby current in power-down mode icc2p cke vil(max), tcc= tcc(min) 75 70 ma 1,3 precharge standby current in non power-down mode icc2n cke vih(min), cs vih(min), tcc= tcc(min) 120 110 ma 1,3 active standby current power-down mode icc3p cke vil(max), tcc= tcc(min) 110 105 ma 1,3 active standby current in in non power-down mode icc3n cke vih(min), cs vih(min), tcc= tcc(min) 220 210 ma 1,3 operating current ( burst mode) icc4 iol=0ma ,tcc= tcc(min), page burst, all banks activated. 500 480 ma 1 refresh current icc5 trc trfc 270 240 ma 1,2 self refresh current icc6 cke 0.2v 20 20 ma 1 operating current (4bank interleaving) icc7 burst length=4 trc trc(min) iol=0ma, tcc= tcc(min) 580 540 ma 1 - 54 - k4j52324ki datasheet gddr3 sgram rev. 1.2 9.7 ac characteristics [ table 13 ] ac characteristics - i parameter symbol -hc7a(1.3ghz) -hc08(1.2ghz) unit note min max min max dqs out access time from ck tdqsck -0.18 0.18 -0.19 0.19 ns ck high-level width tch 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 tck ck cycle time cl=15 tck 0.77 - - - ns cl=14 0.83 0.83 ns write latency twl 1,2,3 - 1,2,3 - tck 1 dq and dm input hold time relative to dqs tdh 0.11 - 0.12 - ns dq and dm input setup time relative to dqs tds 0.11 - 0.12 - ns active termination setup time tats 10 - 10 - ns active termination hold time tath 10 - 10 - ns dqs input high pulse width tdqsh 0.48 0.52 0.48 0.52 tck dqs input low pulse widthl tdqsl 0.48 0.52 0.48 0.52 tck data strobe edge to dout edge tdqsq -0.10 0.10 -0.11 0.11 ns dqs read preamble trpre 0.4 0.6 0.4 0.6 tck dqs read postamble trpst 0.4 0.6 0.4 0.6 tck write command to first dqs latching tran sition tdqss wl-0.2 wl+0.2 wl-0.2 wl+0.2 tck dqs write preamble twpre 0.4 0.6 0.4 0.6 tck 2 dqs write preamble setup time twpres 0 - 0 - ns dqs write postamble twpst 0.4 0.6 0.4 0.6 tck 3 half strobe period thp tclmin or tchmin - tclmin or tchmin -tck data output hold time from dqs tqh thp-0.10 - thp-0.11 - ns data-out high-impedance window from ck and /ck thz -0.3 - -0.3 - ns 4 data-out low-impedance window from ck and /ck tlz -0.3 - -0.3 - ns 4 address and control input hold time tih 0.23 - 0.24 - ns address and control input setup time tis 0.23 - 0.24 - ns address and control input pulse width tipw 0.6 - 0.65 - ns jitter over 1~6 clock cycle error tj - 0.03 - 0.03 tck 5 cycle to cyde duty cycle error tdcerr - 0.03 - 0.03 tck rise and fall times of ck tr, tf - 0.2 - 0.2 tck - 55 - k4j52324ki datasheet gddr3 sgram rev. 1.2 parameter symbol -hc1a(1ghz) unit note min max dqs out access time from ck tdqsck -0.20 +0.20 ns ck high-level width tch 0.45 0.55 tck ck low-level width tcl 0.45 0.55 tck ck cycle time cl=12 tck 1.0 3.3 ns cl=11 1.1/1.25 ns cl=10 1.4 ns write latency twl 1,2,3,7 - tck 1 dq and dm input hold time relative to dqs tdh 0.13 - ns dq and dm input setup time relative to dqs tds 0.13 - ns active termination setup time tats 10 - ns active termination hold time tath 10 - ns dqs input high pulse width tdqsh 0.48 0.52 tck dqs input low pulse widthl tdqsl 0.48 0.52 tck data strobe edge to dout edge tdqsq -0.130 0.130 ns dqs read preamble trpre 0.4 0.6 tck dqs read postamble trpst 0.4 0.6 tck write command to first dqs latchi ng transition tdqss wl-0.2 wl+0.2 tck dqs write preamble twpre 0.4 0.6 tck 2 dqs write preamble setup time twpres 0 - ns dqs write postamble twpst 0.4 0.6 tck 3 half strobe period thp tclmin or tchmin -tck data output hold time from dqs tqh t hp -0.12 -ns data-out high-impedance window from ck and ck thz -0.3 - ns 4 data-out low-impedance window from ck and ck tlz -0.3 - ns 4 address and control input hold time tih 0.27 - ns address and control input setup time tis 0.27 - ns address and control input pulse width tipw 0.8 - ns jitter over 1~6 clock cycle error tj - 0.03 tck 5 cycle to cyde duty cycle error tdcerr - 0.03 tck rise and fall times of ck tr, tf - 0.2 tck - 56 - k4j52324ki datasheet gddr3 sgram rev. 1.2 note : 1. the write latency can be set from 1 to 7 clocks. when the write latency is set to 1 or 2 or 3 clocks, the input buffers a re turned on during the active commands reducing the latency but added power. when the write latency is set to 5 ~7 clocks which must be greater t han 7ns, the input buffers are turned on during the write commands for lower power operation. 2. a low to high transition on the wdqs line is not a llowed in the half clock prior to the write preamble. 3. the last rising edge of wdqs after the write postamble must be driven high by the controller. wdqs can not be pulled high by the on-die termination alone. 4. thz and tlz transitions occur in the same access time windows as valid data transitions. thes e parameters are not reference d to a specific voltage level, but specify when the device output is no longer driving (hz) or begins driving (lz). 5. the cycle to cycle jitter over 1~6 cycle short term jitter parameter symbol -hc12(800mhz) -hc14(700mhz) unit note min max min max dqs out access time from ck tdqsck -0.23 +0.23 -0.26 +0.26 ns ck high-level width tch 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 tck ck cycle time cl=11 tck 1.25 3.3 - 3.3 ns cl=10 1.4 1.4 ns write latency twl 1,2,3,6,7 - 1,2,3,5,6,7 - tck 1 dq and dm input hold time relative to dqs tdh 0.16 - 0.18 - ns dq and dm input setup time relative to dqs tds 0.16 - 0.18 - ns active termination setup time tats 10 - 10 - ns active termination hold time tath 10 - 10 - ns dqs input high pulse width tdqsh 0.48 0.52 0.48 0.52 tck dqs input low pulse widthl tdqsl 0.48 0.52 0.48 0.52 tck data strobe edge to dout edge tdqsq -0.140 0.140 -0.160 0.160 ns dqs read preamble trpre 0.4 0.6 0.4 0.6 tck dqs read postamble trpst 0.4 0.6 0.4 0.6 tck write command to first dqs latching tran sition tdqss wl-0.2 wl+0.2 wl-0.2 wl+0.2 tck dqs write preamble twpre 0.35 - 0.4 0.6 tck 2 dqs write preamble setup time twpres 0 - 0 - ns dqs write postamble twpst 0.4 0.6 0.4 0.6 tck 3 half strobe period thp tclmin or tchmin - tclmin or tchmin -tck data output hold time from dqs tqh t hp -0.14 - t hp -0.16 -ns data-out high-impedance window from ck and ck thz -0.3 - -0.3 - ns 4 data-out low-impedance window from ck and ck tlz -0.3 - -0.3 - ns 4 address and control input hold time tih 0.3 - 0.35 - ns address and control input setup time tis 0.3 - 0.35 - ns address and control input pulse width tipw 0.9 - 1.0 - ns jitter over 1~6 clock cycle error tj - 0.03 - 0.03 tck 5 cycle to cycle duty cycle error tdcerr - 0.03 - 0.03 tck rise and fall times of ck tr, tf - 0.2 - 0.2 tck - 57 - k4j52324ki datasheet gddr3 sgram rev. 1.2 [ table 14 ] ac characteristics - ii parameter symbol -hc7a(1.3ghz) -hc08(1.2ghz) unit note min max min max row active time tras 36 100k 34 100k tck row cycle time trc 51 - 48 - tck refresh row cycle time trfc 66 - 62 - tck ras to cas delay for read trcdr 17 - 16 - tck ras to cas delay for write trcdw 13 - 12 - tck row precharge time trp 15 - 14 - tck row active to row active trrd 13 - 12 - tck last data in to row precharge (pre or autopre ) twr 13 - 13 - tck last data in to read command tcdlr 8 - 8 - tck cas to cas command delay tccd bl/2 - bl/2 - tck mode register set cycle time tmrd 10 - 10 - tck auto precharge write recovery time + precharge tdal 30 - 29 - tck exit self refresh to read command txsr 20000 - 20000 - tck exit self refresh to non-read command txsnr 100 - 100 - tck power-down exit time tpdex 10tck +tis - 10tck +tis -tck refresh interval time tref - 3.9 - 3.9 us cke minimum pulse width (high and low pulse width) tcke 5 - 5 - tck parameter symbol -hc1a(1ghz) unit note min max row active time tras 29 100k tck row cycle time trc 41 - tck refresh row cycle time trfc 52 - tck ras to cas delay for read trcdr 14 - tck ras to cas delay for write trcdw 10 - tck row precharge time trp 12 - tck row active to row active trrd 10 - tck last data in to row precharge (pre or auto-pre) twr 13 - tck last data in to read command tcdlr 7 - tck mode register set cycle time tmrd 9 - tck cas to cas command delay tccd bl/2 - tck auto precharge write recovery time + precharge tdal 25 - tck exit self refresh to read command txsr 20000 - tck exit self refresh to non-read command txsnr 100 - tck power-down exit time tpdex 8tck +tis -tck refresh interval time tref - 3.9 us cke minimum pulse width (high and low pulse width) tcke 5 - tck - 58 - k4j52324ki datasheet gddr3 sgram rev. 1.2 note : 1. the alternative solution for 8bank activation without tfaw restriction is to set trrd=12ns regardless of frequency. in this case, the minimum number of clock cycles is determined by dividing the minimum time required with clo ck cycle time and then rounding off to the next higher integer unc onditionally. parameter symbol -hc12(800mhz) -hc14(700mhz) unit note min max min max row active time tras 25 100k 22 100k tck row cycle time trc 35 - 31 - tck refresh row cycle time trfc 45 - 39 - tck ras to cas delay for read trcdr 12 - 10 - tck ras to cas delay for write trcdw 8 - 6 - tck row precharge time trp 10 - 9 - tck row active to row active trrd 8 - 8 - tck four activate window tfaw 40 - 40 - tck 1 last data in to row precharge (pre or auto-pre) twr 11 - 10 - tck last data in to read command tcdlr 6 - 5 - tck cas to cas command delay tccd bl/2 - bl/2 - tck mode register set cycle time tmrd 7 - 6 - tck auto precharge write recovery time + precharge tdal 21 - 19 - tck exit self refresh to read command txsr 20000 - 20000 - tck exit self refresh to non-read command txsnr 100 - 100 - tck power-down exit time tpdex 7tck+tis - 6tck +tis -tck refresh interval time tref - 3.9 - 3.9 us cke minimum pulse width (high and low pulse width) tcke 5-5-tck - 59 - k4j52324ki datasheet gddr3 sgram rev. 1.2 10. ibis : i/v characteristics for input and output buffers ocd (40 ) pulldown current (ma) pullup current (ma) voltage (v) minimum maximum minimum maximum 0.1 2.8 3.2 -2.4 -3.1 0.2 5.5 9.6 -4.7 -6.2 0.3 8.1 12.8 -7.0 -9.2 0.4 10.8 15.9 -9.2 -12.1 0.5 13.3 19.0 -11.4 -14.9 0.6 15.8 22.0 -13.4 -17.7 0.7 18.2 25.1 -15.3 -20.3 0.8 20.5 28.0 -17.1 -22.8 0.9 22.8 31.0 -18.8 -25.2 1.0 24.9 33.8 -20.3 -27.5 1.1 26.9 36.7 -21.7 -29.6 1.2 28.8 36.7 -22.9 -31.6 1.3 30.6 39.4 -23.9 -33.3 1.4 32.2 42.1 -24.8 -34.9 1.5 33.7 44.7 -25.4 -36.3 1.6 35.2 47.0 -26.0 -37.5 1.7 36.3 49.2 -26.5 -38.3 1.8 37.7 51.4 -27.0 -39.3 1.9 38.7 53.3 -27.4 -40.0 - 60 - k4j52324ki datasheet gddr3 sgram rev. 1.2 pull down 0 10 20 30 40 50 60 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 voltage(v) iol(ma) min max pull up -45 -40 -35 -30 -25 -20 -15 -10 -5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 voltage(v) ioh(ma ) min max - 61 - k4j52324ki datasheet gddr3 sgram rev. 1.2 11. package dimensions (fbga) a b c d e f h j k l m n p r g t v 87654321 9 10 11 12 10.00 0.10 0.80 2.00 4.40 0.80 x 11 = 8.80 14.00 0.10 6.40 0.80 x 16 = 12.80 a b # a1 index mark (datum b) molding area bottom 0.95 1.90 136- ? 0.45 solder ball 0.2 m ab (post reflow 0.50 0.05) 10.00 0.10 14.00 0.10 #a1 top (datum a) 0.80 0.80 unit: mm 0.10max 0.35 0.05 1.10 0.10 |
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