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preliminary: the specifications of this device are subject to change without notice. please contact your nearest hitachi?s sales dept. regarding specifications. hm62w8201h series 16m high speed sram (2-mword 8-bit) ade-203-955a (z) preliminary rev. 0.1 may. 28, 1999 description the hm62w8201h series is an asynchronous high speed static ram organized as 2-mword 8-bit. it has realized high speed access time by employing the most advanced cmos process and high speed circuit designing technology. it is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. it has the package variations of standard 44-pin plastic tsopii and 36-pin plastic soj. features ? single 3.3 v supply: 3.3 v 0.3 v ? access time: 10 ns/12 ns/15 ns (max) ? completely static memory ? no clock or timing strobe required ? equal access and cycle times ? directly ttl compatible ? all inputs and outputs ? operating current: 180 ma/160 ma/140 ma (max) ? ttl standby current: 70 ma/60 ma/50 ma (max) ? cmos standby current: 20 ma (max) ? center v cc and v ss type pinout
hm62w8201h series 2 ordering information type no. access time package hm62w8201hjp-10 HM62W8201HJP-12 hm62w8201hjp-15 10 ns 12 ns 15 ns 400-mil 36-pin plastic soj (cp-36d) hm62w8201hljp-10 hm62w8201hljp-12 hm62w8201hljp-15 10 ns 12 ns 15 ns hm62w8201htt-10 hm62w8201htt-12 hm62w8201htt-15 10 ns 12 ns 15 ns 400-mil 44-pin plastic tsopii (ttp-44de) hm62w8201hltt-10 hm62w8201hltt-12 hm62w8201hltt-15 10 ns 12 ns 15 ns
hm62w8201h series 3 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 a0 a1 a2 a3 a4 cs i/o0 i/o1 v cc v ss i/o2 i/o3 we a5 a6 a7 a8 a9 a20 a19 a18 a17 a16 oe i/o7 i/o6 v ss v cc i/o5 i/o4 a15 a14 a13 a12 a11 a10 (top view) 36-pin soj nc nc a0 a1 a2 a3 a4 cs i/o0 i/o1 v cc v ss i/o2 i/o3 we a5 a6 a7 a8 a9 nc nc (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 nc nc a20 a19 a18 a17 a16 oe i/o7 i/o6 v ss v cc i/o5 i/o4 a15 a14 a13 a12 a11 a10 nc nc 44-pin tsop pin description pin name function a0 to a20 address input i/o0 to i/o7 data input/output chip select output enable write enable v cc power supply v ss ground nc no connection
hm62w8201h series 4 block diagram i/o0 . . . i/o7 we input data control column i/o column decoder memory matrix 4096 rows 512 columns 8 bit (16,777,216 bits) row decoder oe cs cs cs cs a a a a a a a a a a a a a a a a a a a a a a v cc v ss operating table i/o operation h high-z standby l h l dout read l l h din write l l l din write l h h high-z output disable note: h: v ih , l: v il , : v ih or v il
hm62w8201h series 5 absolute maximum ratings parameter symbol value unit power supply voltage relative to v ss v cc ?0.5 to +4.6 v terminal voltage on any pin relative to v ss v t ?0.5* 1 to v cc +0.5* 2 ( 4.6 v (max)) v power dissipation p t 1.0 w storage temperature tstg ?55 to +125 c storage temperature under bias tbias ?10 to +85 c notes: 1. v t (min) = ?2.0 v for pulse width (under shoot) 8 ns. 2. v t (max) = v cc + 2.0 v for pulse with (over shoot) 8 ns. dc operating conditions parameter symbol min typ max unit notes supply voltage v cc 3.0 3.3 3.6 v 3 v ss 0 0 0 v 4 input high voltage v ih 2.2 ? v cc + 0.5* 2 v input low voltage v il ?0.5* 1 ? 0.8 v ambient temperature ta 0 ? 70 c notes: 1. v il (min) = ?2.0 v for pulse width (under shoot) 8 ns. 2. v ih (max) = v cc + 2.0 v for pulse width (over shoot) 8 ns. 3. the supply voltage with all v cc pins must be on the same level. 4. the supply voltage with all v ss pins must be on the same level.
hm62w8201h series 6 dc characteristics parameter symbol min typ * 1 max unit test conditions input leakage current ii li i ? ? 2 a vin = v ss to v cc output leakage current ii lo i ? ? 2 a vin = v ss to v cc operating current 10 ns cycle i cc ? ? 180 ma min cycle = v il , lout = 0 ma other inputs = v ih /v il 12 ns cycle i cc ? ? 160 ma 15 ns cycle i cc ? ? 140 ma standby current 10 ns cycle i sb ? ? 70 ma min cycle = v ih , other inputs = v ih /v il 12 ns cycle i sb ? ? 60 ma 15 ns cycle i sb ? ? 50 ma i sb1 ? ? 20 ma f = 0 mhz v cc v cc - 0.2 v, (1) 0 v vin 0.2 v or (2) v cc vin v cc - 0.2 v i sb1 * 2 ? ? tbd ma output high voltage v oh 2.4 ? ? v i oh = ? 4 ma output low voltage v ol ? ? 0.4 v i ol = 8 ma notes: 1. typical values are at v cc = 3.3 v, ta = +25 c and not guaranteed. 2. this characteristics is guaranteed only for l-version. capacitance (ta = + 25 c, f = 1.0 mhz) parameter symbol min typ max unit test conditions note input capacitance cin ? ? 6 pf vin = 0 v 1 input/output capacitance c i/o ? ? 8 pf v i/o = 0 v 1 note: 1. this parameter is sampled and not 100% tested.
hm62w8201h series 7 ac characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v) test conditions ? input pulse levels: v il = 0 v, v ih = 3.0 v ? input rise and fall time: 3 ns ? input and output timing reference levels: 1.5 v ? output load: see figures (including scope and jig) dout 353 ? 319 ? 3.3 v 5 pf output load (b) (for t clz , t olz , t chz , t ohz , t whz , and t ow ) dout rl=50 ? output load (a) 1.5 v zo=50 ? read cycle hm62w8201h -10 -12 -15 parameter symbol min max min max min max unit notes read cycle time t rc 10 ? 12 ? 15 ? ns address access time t aa ? 10 ? 12 ? 15 ns chip select access time t acs ? 10 ? 12 ? 15 ns output enable to output valid t oe ? 5 ? 6 ? 7 ns output hold from address change t oh 3 ? 3 ? 3 ? ns chip select to output in low-z t clz 3 ? 3 ? 3 ? ns 1 output enable to output in low-z t olz 0 ? 0 ? 0 ? ns 1 chip deselect to output in high-z t chz ? 5 ? 6 ? 7 ns 1 output disable to output in high-z t ohz ? 5 ? 6 ? 7 ns 1
hm62w8201h series 8 write cycle hm62w8201h -10 -12 -15 parameter symbol min max min max min max unit notes write cycle time t wc 10 ? 12 ? 15 ? ns address valid to end of write t aw 7 ? 8 ? 10 ? ns chip select to end of write t cw 7 ? 8 ? 10 ? ns 9 write pulse width t wp 7 ? 8 ? 10 ? ns 8 address setup time t as 0 ? 0 ? 0 ? ns 6 write recovery time t wr 0 ? 0 ? 0 ? ns 7 data to write time overlap t dw 5 ? 6 ? 7 ? ns data hold from write time t dh 0 ? 0 ? 0 ? ns write disable to output in low-z t ow 3 ? 3 ? 3 ? ns 1 output disable to output in high-z t ohz ? 5 ? 6 ? 7 ns 1 write enable to output in high-z t whz ? 5 ? 6 ? 7 ns 1 notes: 1. transition is measured 200 mv from steady voltage with load (b). this parameter is sampled and not 100% tested. 2. address should be valid prior to or coincident with transition low. 3. and/or must be high during address transition time. 4. if and are low during this period, i/o pins are in the output state. then, the data input signals of opposite phase to the outputs must not be applied to them. 5. if the low transition occurs simultaneously with the low transition or after the transition, output remains a high impedance state. 6. t as is measured from the latest address transition to the later of or going low. 7. t wr is measured from the earlier of or going high to the first address transition. 8. a write occurs during the overlap of a low and a low . a write begins at the latest transition among going low and going low. a write ends at the earliest transition among going high and going high. t wp is measured from the beginning of write to the end of write. 9. t cw is measured from the later of going low to the end of write.
hm62w8201h series 9 timing waveforms read timing waveform (1) ( = v ih ) t aa t acs t rc t oe t clz valid data address cs dout valid address high impedance t ohz oe t oh t chz t olz high impedance read timing waveform (2) ( = v ih , = v il , = v il ) t aa t rc valid data address dout valid address t oh t oh read timing waveform (3) ( = v ih , = v il )* 2 valid data cs dout high impedance high impedance t clz t acs t rc t chz
hm62w8201h series 10 write timing waveform (1) ( controlled) address we * 3 dout din t wc t wp t wr t cw t dw t dh t ow valid address t aw valid data t as cs * 3 t whz * 4 * 4 high impedance oe t ohz t olz
hm62w8201h series 11 write timing waveform (2) ( controlled) t wc t cw t wp t aw t wr valid address t as t dw t dh valid data *5 high impedance address we dout din cs
hm62w8201h series 12 low v cc data retention characteristics (ta = 0 to +70 c) this characteristics is guaranteed only for l-version. parameter symbol min typ * 1 max unit test conditions v cc for data retention v dr 2.0 ? ? v v cc v cc ? 0.2 v (1) 0 v vin 0.2 v or (2) v cc vin v cc ? 0.2 v data retention current 10 ns cycle i ccdr ? ? tbd ma v cc = 3 v, v cc v cc ? 0.2 v (1) 0 v vin 0.2 v or (2) v cc vin v cc ? 0.2 v 12 ns cycle i ccdr ? ? tbd ma 15 ns cycle i ccdr ? ? tbd ma chip deselect to data retention time t cdr 0 ? ? ns see retention waveform operation recovery time t r 5 ? ? ms note: 1. typical values are at v cc = 3.0 v, ta = + 25 c, and not guaranteed. low v cc data retention timing waveform v cc 3.0 v 2.2 v 0 v cs t cdr t r v cc cs v cc ? 0.2 v v dr data retention mode
hm62w8201h series 13 package dimensions hm62w8201hjp/hljp series (cp-36d) 9.40 0.25 1 18 *0.43 0.10 3.50 0.26 19 36 23.62 max 23.25 0.74 10.16 0.13 11.18 0.13 1.30 max 2.85 0.12 0.10 1.27 0.80 +0.25 ? 0.17 0.41 0.08 hitachi code jedec eiaj weight (reference value) cp-36d conforms conforms 1.4 g unit: mm *dimension including the plating thickness base material dimension
hm62w8201h series 14 hm62w8201htt/hltt series (ttp-44de) hitachi code jedec eiaj weight (reference value) ttp-44de ? ? 0.43 g unit: mm *dimension including the plating thickness base material dimension 0.13 m 0.10 0.80 44 23 122 18.41 18.81 max *0.27 0.07 1.20 max 10.16 0.13 0.05 11.76 0.20 0 ? 5 *0.145 0.05 1.005 max 0.50 0.10 0.68 0.80 0.25 0.05 0.125 0.04
hm62w8201h series 15 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi ? s or any third party ? s patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party ? s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi ? s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi ? s sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ? hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra ? e 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:
hm62w8201h series 16 revision record rev. date contents of modification drawn by approved by 0.0 sep. 15, 1998 initial issue k. homma k. mitsumoto 0.1 may. 28, 1999 addition of hm62w8201h-10 series addition of hm62w8201hjp/hljp (cp-36d) dc characteristics i cc max: 150/130 ma to 180/160/140 ma i sb max: 60/50 ma to 70/60/50 ma i sb1 max: 30/10 ma to 20 ma i sb1 (l-version) max: 3.0/1.5 ma to tbd ac characteristics change of timing waveforms for write cycle (1) controlled low v cc data retention characteristics i ccdr max: 3.0/1.5 ma to tbd/tbd/tbd

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