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16mb 1x1lp, lvcmos, rev 0.2 1 / 27 july 6, 2001 cxk79m72c161gb sony s s ram 33/4/44 cxk79m36c161gb cxk79m18c161gb 16mb 1x1lp lvcmos high speed synchronous srams (256kb x 72 or 512kb x 36 or 1mb x 18) preliminary description features ? 3 speed bins cycle time / data access time -33 3.3ns / 1.8ns -4 4.0ns / 2.1ns -44 4.4ns / 2.3ns ? single 1.8v power supply (v dd ): 1.7v (min) to 1.95v (max) ? dedicated output supply voltage (v ddq ): 1.8v or 1.5v typical ? lvcmos-compatible i/o interface ? common i/o ? single data rate (sdr) data transfers ? pipelined (pl) read operations ? late write (lw) write operations ? burst capability with internally controlled linear burst address sequencing ? burst length of two, three, or four, with automatic address wrap ? full read/write data coherency ? byte write capability ? two cycle deselect ? single-ended input clock (ck) ? data-referenced output clocks (cq/ cq ) ? selectable output driver impedance via dedicated control pin (zq) ? depth expansion capability (2 or 4 banks) via programmable chip enables (e2, e3, ep2, ep3) ? jtag boundary scan (subset of ieee standard 1149.1) ? 209 pin (11x19), 1mm pitch, 14mm x 22mm ball grid array (bga) package the cxk79m72c161gb (organized as 262,144 words by 72 bits), cxk79m36c161gb (organized as 524,288 words by 36 bits), and the cxk79m18c161gb (organized as 1,048,576 words by 18 bits) are high speed cmos synchronous static rams with common i/o pins. they are manufactured in compliance with the jedec-standard 209 pin bga package pinouts defined for sigmarams. they integrate input registers, high speed ram, output registers, and a two-deep write buffer onto a single monolithic ic. single data rate (sdr) pipelined (pl) read operations and late write (lw) write operations are supported, providing a high-performance user interface. positive and negative output clocks are provided for applications requiring source- synchronous operation. all address and control input signals are registered on the rising edge of the ck input clock. during read operations, output data is driven valid once, from the rising edge of ck, one full cycle after the address and contr ol signals are registered. during write operations, input data is registered once, on the rising edge of ck, one full cycle after the address and control signals are registered. output drivers are series-terminated, and output impedance is selectable via the zq control pin. when zq is tied ?low?, the impedance of the sram?s output drivers is set to ~25 w . when zq is tied ?high? or left unconnected, the impedance of the sram?s output drivers is set to ~50 w. 300 mhz operation (300 mbps) is obtained from a single 1.8v power supply. jtag boundary scan interface is provided using a subset of ieee standard 1149.1 protocol.
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 2 / 27 july 6, 2001 256kb x 72 pin assignment (top view) 1 2 3 4 5 6 7 8 9 10 11 a dqg dqg a e2 a (16m) adv a (8m) e3 a dqb dqb b dqg dqg bw c bw g nc w a bw b bw f dqb dqb c dqg dqg bw h bw d nc (128m) e1 nc bw e bw a dqb dqb d dqg dqg v ss nc nc mcl nc nc v ss dqb dqb e dqg dqc v ddq v ddq v dd v dd v dd v ddq v ddq dqf dqb f dqc dqc v ss v ss v ss zq v ss v ss v ss dqf dqf g dqc dqc v ddq v ddq v dd ep2 v dd v ddq v ddq dqf dqf h dqc dqc v ss v ss v ss ep3 v ss v ss v ss dqf dqf j dqc dqc v ddq v ddq v dd m4 v dd v ddq v ddq dqf dqf k cq cq ck nc v ss mcl v ss nc nc cq cq l dqh dqh v ddq v ddq v dd m2 v dd v ddq v ddq dqa dqa m dqh dqh v ss v ss v ss m3 v ss v ss v ss dqa dqa n dqh dqh v ddq v ddq v dd mch v dd v ddq v ddq dqa dqa p dqh dqh v ss v ss v ss mcl v ss v ss v ss dqa dqa r dqd dqh v ddq v ddq v dd v dd v dd v ddq v ddq dqa dqe t dqd dqd v ss nc nc mcl nc nc v ss dqe dqe u dqd dqd nc a nc (64m) a nc (32m) a nc dqe dqe v dqd dqd a (2m) a a a1 a a a (4m) dqe dqe w dqd dqd tms tdi a a0 a tdo tck dqe dqe
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 3 / 27 july 6, 2001 512kb x 36 pin assignment (top view) 1 2 3 4 5 6 7 8 9 10 11 a nc nc a e2 a (16m) adv a (8m) e3 a dqb dqb b nc nc bw c nc a (x36) w a bw b nc dqb dqb c nc nc nc bw d nc (128m) e1 nc nc bw a dqb dqb d nc nc v ss nc nc mcl nc nc v ss dqb dqb e nc dqc v ddq v ddq v dd v dd v dd v ddq v ddq nc dqb f dqc dqc v ss v ss v ss zq v ss v ss v ss nc nc g dqc dqc v ddq v ddq v dd ep2 v dd v ddq v ddq nc nc h dqc dqc v ss v ss v ss ep3 v ss v ss v ss nc nc j dqc dqc v ddq v ddq v dd m4 v dd v ddq v ddq nc nc k cq cq ck nc v ss mcl v ss nc nc cq cq l nc nc v ddq v ddq v dd m2 v dd v ddq v ddq dqa dqa m nc nc v ss v ss v ss m3 v ss v ss v ss dqa dqa n nc nc v ddq v ddq v dd mch v dd v ddq v ddq dqa dqa p nc nc v ss v ss v ss mcl v ss v ss v ss dqa dqa r dqd nc v ddq v ddq v dd v dd v dd v ddq v ddq dqa nc t dqd dqd v ss nc nc mcl nc nc v ss nc nc u dqd dqd nc a nc (64m) a nc (32m) a nc nc nc v dqd dqd a (2m) a a a1 a a a (4m) nc nc w dqd dqd tms tdi a a0 a tdo tck nc nc
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 4 / 27 july 6, 2001 1mb x 18 pin assignment (top view) 1 2 3 4 5 6 7 8 9 10 11 a nc nc a e2 a (16m) adv a (8m) e3 a nc nc b nc nc bw b nc a (x36) w a nc nc nc nc c nc nc nc nc nc (128m) e1 a (x18) nc bw a nc nc d nc nc v ss nc nc mcl nc nc v ss nc nc e nc dqb v ddq v ddq v dd v dd v dd v ddq v ddq nc nc f dqb dqb v ss v ss v ss zq v ss v ss v ss nc nc g dqb dqb v ddq v ddq v dd ep2 v dd v ddq v ddq nc nc h dqb dqb v ss v ss v ss ep3 v ss v ss v ss nc nc j dqb dqb v ddq v ddq v dd m4 v dd v ddq v ddq nc nc k cq cq ck nc v ss mcl v ss nc nc cq cq l nc nc v ddq v ddq v dd m2 v dd v ddq v ddq dqa dqa m nc nc v ss v ss v ss m3 v ss v ss v ss dqa dqa n nc nc v ddq v ddq v dd mch v dd v ddq v ddq dqa dqa p nc nc v ss v ss v ss mcl v ss v ss v ss dqa dqa r nc nc v ddq v ddq v dd v dd v dd v ddq v ddq dqa nc t nc nc v ss nc nc mcl nc nc v ss nc nc u nc nc nc a nc (64m) a nc (32m) a nc nc nc v nc nc a (2m) a a a1 a a a (4m) nc nc w nc nc tms tdi a a0 a tdo tck nc nc
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 5 / 27 july 6, 2001 pin description symbol type description a input address inputs - registered on the rising edge of ck. a1, a0 input address inputs 1,0 - registered on the rising edge of ck. initialize burst counter. dqa, dqb dqc, dqd dqe, dqf dqg, dqh i/o data inputs / outputs - registered on the rising edge of ck during write operations. driven from the rising edge of ck during read operations. dqa - indicates data byte a dqb - indicates data byte b dqc - indicates data byte c dqd - indicates data byte d dqe - indicates data byte e dqf - indicates data byte f dqg - indicates data byte g dqh - indicates data byte h ck input input clock cq, cq output output clocks e1 input chip enable control input - registered on the rising edge of ck. e1 = 0 enables the device to accept read and write commands. e1 = 1 disables the device. see the clock truth table section for further information. e2, e3 input programmable chip enable control inputs - registered on the rising edge of ck. see the clock truth table and depth expansion sections for further information. ep2, ep3 input programmable chip enable active-level select inputs - these pins must be tied ?high? or ?low? at power-up. see the clock truth table and depth expansion sections for further infor- mation. adv input address advance control input - registered on the rising edge of ck. adv = 0 loads a new address and begins a new operation when the device is enabled. adv = 1 increments the address and continues the previous operation when the device is enabled. see the clock truth table section for further information. w input write enable control input - registered on the rising edge of ck. w = 0 specifies a write operation when adv = 0 and the device is enabled. w = 1 specifies a read operation when adv = 0 and the device is enabled. see the clock truth table section for further information. bw a, bw b bw c, bw d bw e, bw f bw g, bw h input byte write enable control inputs - registered on the rising edge of ck. bw a = 0 specifies write data byte a during a write operation bw b = 0 specifies write data byte b during a write operation bw c = 0 specifies write data byte c during a write operation bw d = 0 specifies write data byte d during a write operation bw e = 0 specifies write data byte e during a write operation bw f = 0 specifies write data byte f during a write operation bw g = 0 specifies write data byte g during a write operation bw h = 0 specifies write data byte h during a write operation see the clock truth table section for further information. m2, m3, m4 input operation protocol control inputs - these pins must be tied ?high?, ?high?, and ?low? respec- tively, at power-up, to select single data rate pipelined read / late write operation protocol. zq input output impedance control input - this pin must be tied ?high? or ?low? at power-up. zq = 0 selects ~25 w output impedance zq = 1 selects ~50 w output impedance note: this pin can also be left unconnected. there is a small pull-up device on this input buffer such that an unconnected pin is treated the same as if the pin were tied ?high?.
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 6 / 27 july 6, 2001 v dd 1.8v core power supply - core supply voltage. v ddq output power supply - output buffer supply voltage. v ss ground tck input jtag clock tms input jtag mode select tdi input jtag data in tdo output jtag data out mcl *input* must connect ?low? - may not be actual input pins. mch *input* must connect ?high? - may not be actual input pins. nc no connect - these pins are true no-connects, i.e. there is no internal chip connection to these pins. they can be left unconnected or tied directly to v dd , v ddq , or v ss . symbol type description
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 7 / 27 july 6, 2001 clock truth table notes: 1. if e2 = ep2 and e3 = ep3 then e = ?t? else e = ?f?. 2. if one or more bw x = 0 then bw = ?t? else bw = ?f?. 3. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. 4. ?***? indicates that the dq input requirement / output state and cq output state are determined by the previous operation. 5. dqs are tri-stated in response to bank deselect, deselect, and write commands, one full cycle after the command is sam- pled. 6. cqs are tri-stated in response to bank deselect commands only, one full cycle after the command is sampled. 7. up to three (3) continue operations may be initiated after a read or write operation is initiated to burst transfer up to four (4) distinct pieces of data per single external address input. if a fourth (4th) continue operation is initiated, the internal address wraps back to the initial external (base) address. ck e1 (t n ) e (t n ) adv (t n ) w (t n ) bw (t n ) previous operation current operation dq(t n ) dq(t n+1 ) cq(t n ) cq(t n+1 ) 0 ? 1 x f 0 x x x bank deselect *** hi-z *** hi-z 0 ? 1 x x 1 x x bank deselect bank deselect (continue) hi-z hi-z hi-z hi-z 0 ? 1 1 t 0 x x x deselect *** hi-z *** cq 0 ? 1 x x 1 x x deselect deselect (continue) hi-z hi-z cq cq 0 ? 1 0 t 0 0 t x write loads new address stores dqx if bw x = 0 *** d1(t n ) *** cq 0 ? 1 0 t 0 0 f x write (abort) loads new address no data stored *** hi-z *** cq 0 ? 1 x x 1 x t write write continue increments address by 1 stores dqx if bw x = 0 d1(t n-1 ) d2(t n ) cq cq 0 ? 1 x x 1 x f write write continue (abort) increments address by 1 no data stored d1(t n-1 ) hi-z cq cq 0 ? 1 0 t 0 1 x x read loads new address *** q1(t n ) *** cq 0 ? 1 x x 1 x x read read continue increments address by 1 q1(t n-1 ) q2(t n ) cq cq
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 8 / 27 july 6, 2001 state diagram notes: 1. the notation ?x,x,x,x? controlling the state transitions above indicate the states of inputs e1 , e, adv, and w respectively. 2. if (e2 = ep2 and e3 = ep3) then e = ?t? else e = ?f?. 3. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. deselect bank deselect read read write write continue x,f,0,x or x,x,1,x continue x,f,0,x 1,t,0,x x,f,0,x 1,t,0,x 1,t,0,x x,f,0,x 1,t,0,x 1,t,0,x or x,x,1,x 0,t,0,0 0,t,0,1 0,t,0,0 0,t,0,1 x,f,0,x x,f,0,x 0,t,0,0 0,t,0,1 x,x,1,x x,x,1,x 0,t,0,0 0,t,0,1 1,t,0,x 0,t,0,0 0,t,0,1 x,x,1,x x,x,1,x 0,t,0,1 0,t,0,0
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 9 / 27 july 6, 2001 ? burst (continue) operations burst operations follow the linear burst address sequence depicted in the table below: up to three (3) continue operations may be initiated after a read or write operation is initiated to burst transfer up to four (4) distinct pieces of data per single external address input. if a fourth (4th) continue operation is initiated, the internal address wraps back to the initial external (base) address. ? depth expansion depth expansion in these devices is supported via programmable chip enables e2 and e3. the active levels of e2 and e3 are programmable through the static inputs ep2 and ep3 respectively. when ep2 is tied ?high?, e2 functions as an active- high input. when ep2 is tied ?low?, e2 functions as an active-low input. similarly, when ep3 is tied ?high?, e3 functions as an active-high input. and, when ep3 is tied ?low?, e3 functions as an active-low input. the programmability of e2 and e3 allows four banks of depth expansion to be accomplished with no additional logic. by programming e2 and e3 of four devices in a binary sequence (00, 01, 10, 11), and by driving e2 and e3 with external address signals, the four devices can be made to look like one larger device. when these devices are deselected via chip enable e1 , the output clocks continue to toggle. however, when these devices are deselected via programmable chip enables e2 or e3, the output clocks are forced to a hi-z state. see the clock truth table for further information. ? output driver impedance control the impedance of the data and clock output drivers in these devices can be controlled via the static input zq. when zq is tied ?low?, output driver impedance is set to ~25 w . when zq is tied ?high? or left unconnected, output driver imped- ance is set to ~50 w . see the dc electrical characteristics section for further information. ? power-up sequence for reliability purposes, sony recommends that power supplies power up in the following sequence: v ss , v dd , v ddq , and inputs. v ddq should never exceed v dd . if this power supply sequence cannot be met, a large bypass diode may be required between v dd and v ddq . please contact sony memory application department for further information. a(1:0) sequence key 1st (base) address 00 01 10 11 a1, a0 2nd address 01 10 11 00 (a1 xor a0), a0 3rd address 10 11 00 01 a1 , a0 4th address 11 00 01 10 (a1 xor a0) , a0
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 10 / 27 july 6, 2001 ? absolute maximum ratings (1) (1) stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect reliability. ? dc recommended operating conditions ( v ss = 0v , t a = 0 to 85 o c) 1. parameters apply when v ddq = 1.8v nominally (for 1.8v lvcmos i/o). 2. parameters apply when v ddq = 1.5v nominally (for 1.5v lvcmos i/o). 3. v ih (max) ac = +1.5*v ddq for pulse widths less than one-quarter of the cycle time (t cyc /4). 4. v il (min) ac = -0.5*v ddq for pulse widths less than one-quarter of the cycle time (t cyc /4). item symbol rating units supply voltage v dd -0.5 to +2.5 v output supply voltage v ddq -0.5 to +2.3 v input voltage (address, control, data, clock) v in -0.5 to v ddq +0.5 (2.3v max) v input voltage (ep2, ep3, m2, m3, m4, zq) v min -0.5 to v dd +0.5 (2.5v max) v input voltage (tck, tms, tdi) v tin -0.5 to v dd +0.5 (2.5v max) v operating temperature t a 0 to 85 c junction temperature t j 0 to 110 c storage temperature t stg -55 to 150 c item symbol min typ max units notes supply voltage v dd 1.7 1.8 1.95 v output supply voltage v ddq-1.8 1.7 1.8 v dd v 1 v ddq-1.5 1.4 1.5 1.6 v 2 input high voltage (address, control, data, clock) v ih-1.8 1.2 --- v ddq + 0.3 v 1,3 v ih-1.5 1.0 --- v ddq + 0.3 v 2,3 input low voltage (address, control, data, clock) v il-1.8 -0.3 --- 0.6 v 1,4 v il-1.5 -0.3 --- 0.5 v 2,4 input high voltage (ep2, ep3, m2, m3, m4, zq) v mih-1.8 1.3 --- v dd + 0.3 v 1 v mih-1.5 1.1 --- v dd + 0.3 v 2 input low voltage (ep2, ep3, m2, m3, m4, zq) v mil-1.8 -0.3 --- 0.5 v 1 v mil-1.5 -0.3 --- 0.4 v 2
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 11 / 27 july 6, 2001 ? dc electrical characteristics (v dd = 1.8v 0.1v, v ss = 0v, t a = 0 to 85 o c) ? i/o capacitance (t a = 25 o c, f = 1 mhz) note: these parameters are sampled and are not 100% tested. item symbol test conditions min typ max units input leakage current (address, control, clock) i li v in = v ss to v ddq -5 --- 5 ua input leakage current (ep2, ep3, m2, m3, m4) i mli v min = v ss to v dd -10 --- 10 ua input leakage current (data) i dli v din = v ss to v ddq -10 --- 10 ua average power supply operating current (x72) i dd-33 i dd-4 i dd-44 i out = 0 ma v in = v ih or v il --- --- --- --- --- --- 850 750 700 ma average power supply operating current (x36) i dd-33 i dd-4 i dd-44 i out = 0 ma v in = v ih or v il --- --- --- --- --- --- 630 550 510 ma average power supply operating current (x18) i dd-33 i dd-4 i dd-44 i out = 0 ma v in = v ih or v il --- --- --- --- --- --- 510 450 420 ma power supply deselect operating current (nop current) i dd2 i out = 0 ma v in = v ih or v il --- --- 250 ma output high voltage v oh i oh = -4.0 ma rq = 250 w v ddq -0.4 --- --- v output low voltage v ol i ol = 4.0 ma rq = 250 w --- --- 0.4 v output driver impedance r out v oh , v ol = v ddq /2 zq = v il 17 25 33 w v oh , v ol = v ddq /2 zq = v ih 35 50 65 w item symbol test conditions min max units input capacitance address c a v in = 0v --- 3.5 pf control c b v in = 0v --- 3.5 pf ck clock c ck v in = 0v --- 3.5 pf output capacitance data c dq v out = 0v --- 4.5 pf cq clock c cq v out = 0v --- 4.5 pf
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 12 / 27 july 6, 2001 ? ac electrical characteristics ( t a = 0 to 85 o c) all parameters are measured from the mid-point of the object signal to the mid-point of the reference signal, unless otherwise n oted. 1. these parameters apply to control inputs e1 , e2, e3, adv, w , and bw x. 2. these parameters are verified through device characterization, and are not 100% tested. 3. these parameters are measured at 50mv from steady state voltage. parameter symbol -33 -4 -44 units notes min max min max min max input clock cycle time t khkh 3.3 --- 4.0 --- 4.4 --- ns input clock high pulse width t khkl 1.3 --- 1.5 --- 1.5 --- ns input clock low pulse width t klkh 1.3 --- 1.5 --- 1.5 --- ns address input setup time t avkh 0.7 --- 0.8 --- 0.8 --- ns address input hold time t khax 0.4 --- 0.5 --- 0.5 --- ns control input setup time t bvkh 0.7 --- 0.8 --- 0.8 --- ns 1 control input hold time t khbx 0.4 --- 0.5 --- 0.5 --- ns 1 data input setup time t dvkh 0.7 --- 0.8 --- 0.8 --- ns data input hold time t khdx 0.4 --- 0.5 --- 0.5 --- ns input clock high to output data valid t khqv --- 1.8 --- 2.1 --- 2.3 ns input clock high to output data hold t khqx 0.5 --- 0.5 --- 0.5 --- ns 2 input clock high to output data low-z t khqx1 0.5 --- 0.5 --- 0.5 --- ns 2,3 input clock high to output data high-z t khqz 0.5 1.8 0.5 2.1 0.5 2.3 ns 2,3 input clock high to output clock high t khch 0.5 1.7 0.5 2.0 0.5 2.2 ns input clock high to output clock low-z t khcx1 0.5 --- 0.5 --- 0.5 --- ns 2,3 input clock high to output clock high-z t khcz --- 1.7 --- 2.0 --- 2.2 ns 2,3 output clock high to output data valid t chqv --- 0.4 --- 0.5 --- 0.5 ns 2 output clock high to output data hold t chqx -0.4 --- -0.5 --- -0.5 --- ns 2 output clock high pulse width t chcl t khkl 0.2 t khkl 0.25 t khkl 0.25 ns 2 output clock low pulse width t clch t klkh 0.2 t klkh 0.25 t klkh 0.25 ns 2
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 13 / 27 july 6, 2001 ? ac electrical characteristics (note) the two ac timing parameters listed below are tested according to specific combinations of output clocks (cqs) and output data (dqs): 1. t chqv - output clock high to output data valid (max) 2. t chqx - output clock high to output data hold (min) the specific cq / dq combinations are defined as follows: 256kb x 72 512kb x 36 1mb x 18 cqs dqs cqs dqs cqs dqs 1k, 2k 1a, 2a, 1b, 2b, 1c, 2c, 1d, 2d, 1e, 2e, 1f, 2f, 1g, 2g, 1h, 2h, 1j, 2j, 1l, 2l, 1m, 2m, 1n, 2n, 1p, 2p, 2r, 1r, 1t, 2t, 1u, 2u, 1v, 2v, 1w, 2w 1k, 2k 2e, 1f, 2f, 1g, 2g, 1h, 2h, 1j, 2j, 1r, 1t, 2t, 1u, 2u, 1v, 2v, 1w, 2w 1k, 2k 2e, 1f, 2f, 1g, 2g, 1h, 2h, 1j, 2j 10k, 11k 10a, 11a, 10b, 11b, 10c, 11c, 10d, 11d, 11e, 10e, 10f, 11f, 10g, 11g, 10h, 11h, 10j, 11j, 10l, 11l, 10m, 11m, 10n, 11n, 10p, 11p, 10r, 11r, 10t, 11t, 10u, 11u, 10v, 11v, 10w, 11w 10k, 11k 10a, 11a, 10b, 11b, 10c, 11c, 10d, 11d, 11e, 10l, 11l, 10m, 11m, 10n, 11n, 10p, 11p, 10r 10k, 11k 10l, 11l, 10m, 11m, 10n, 11n, 10p, 11p, 10r
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 14 / 27 july 6, 2001 ? ac test conditions (v ddq = 1.8v) (v dd = 1.8v 0.1v, v ddq = 1.8v 0.1v, t a = 0 to 85 c ) item symbol conditions units notes input high level v ih 1.4 v input low level v il 0.4 v input rise & fall time 2.0 v/ns input reference level 0.9 v clock input high voltage v kih 1.4 v clock input low voltage v kil 0.4 v clock input rise & fall time 2.0 v/ns clock input reference level 0.9 v output reference level 0.9 v output load conditions zq = v ih see figure 1 below dq 0.9 v figure 1: ac test output load (v ddq = 1.8v) 50 w 50 w 5 pf 16.7 w 0.9 v 50 w 50 w 5 pf 16.7 w 16.7 w
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 15 / 27 july 6, 2001 ? ac test conditions (v ddq = 1.5v) (v dd = 1.8v 0.1v, v ddq = 1.5v 0.1v, t a = 0 to 85 c ) item symbol conditions units notes input high level v ih 1.25 v input low level v il 0.25 v input rise & fall time 2.0 v/ns input reference level 0.75 v clock input high voltage v kih 1.25 v clock input low voltage v kil 0.25 v clock input rise & fall time 2.0 v/ns clock input reference level 0.75 v output reference level 0.75 v output load conditions zq = v ih see figure 2 below dq 0.75 v figure 2: ac test output load (v ddq = 1.5v) 50 w 50 w 5 pf 16.7 w 0.75 v 50 w 50 w 5 pf 16.7 w 16.7 w
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 16 / 27 july 6, 2001 timing diagram of read-write-read operations one bank example (e2 = ep2 and e3 = ep3) a2 a3 a4 a5 sa e1 dq q11 d32 d41 q12 q21 t khax t avkh t khbx t bvkh d31 t khdx t dvkh a1 q51 read read continue read deselect deselect write write continue write read deselect deselect figure 3 ck cq cq adv w t khch t chcl t clch t khkh t khkl t klkh bw x (continue) t khqx1 t khqz t khqv t khqx t chqx t chqv note: in the diagram above, two deselect operations are inserted between read and write operations to control the data bus transition from output to input. this depiction is for clarity purposes only. it is not a requirement. depending on the ap- plication, one deselect operation may be sufficient.
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 17 / 27 july 6, 2001 timing diagram of read-write-read operations two bank example (bank 1: ep2 low and e3 = ep3, bank 2: ep2 high and e3 = ep3) a2 a3 a4 a5 sa e1 dq (b1) q11 d41 q12 a1 b-deselect r-continue b-deselect read b-deselect deselect write b-deselect w-continue b-deselect read deselect b-deselect deselect figure 4 ck cq (b1) cq (b1) adv w bw x e2 b1: b2: read b-deselect deselect b-deselect b-deselect write b-deselect b-deselect dq (b2) d32 q21 d31 q51 cq (b2) cq (b2) t khcz t khcx1 note: in the diagram above, two deselect operations are inserted between read and write operations to control the data bus transition from output to input. this depiction is for clarity purposes only. it is not a requirement. depending on the ap- plication, one deselect operation may be sufficient.
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 18 / 27 july 6, 2001 ? test mode description these devices provide a jtag test access port (tap) and boundary scan interface using a limited set of ieee std. 1149.1 functions. this test mode is intended to provide a mechanism for testing the interconnect between master (proces- sor, controller, etc.), srams, other components, and the printed circuit board. in conformance with a subset of ieee std. 1149.1, these devices contain a tap controller and four tap registers. the tap registers consist of one instruction register and three data registers (id, bypass, and boundary scan registers). the tap consists of the following four signals: tck: test clock induces (clocks) tap controller state transitions. tms: test mode select inputs commands to the tap controller. sampled on the rising edge of tck. tdi: test data in inputs data serially to the tap registers. sampled on the rising edge of tck. tdo: test data out outputs data serially from the tap registers. driven from the falling edge of tck. disabling the tap when jtag is not used, tck should be tied ?low? to prevent clocking the sram. tms and tdi should either be tied ?high? through a pull-up resistor or left unconnected. tdo should be left unconnected. note: operation of the tap does not disrupt normal sram operation except when the extest-a or sample-z in- struction is selected. consequently, tck, tms, and tdi can be controlled any number of ways without adversely affect- ing the functionality of the device. jtag dc recommended operating conditions (v dd = 1.8v 0.1v, t a = 0 to 85 c ) jtag ac test conditions (v dd = 1.8v 0.1v, t a = 0 to 85 c ) parameter symbol test conditions min max units jtag input high voltage v tih --- 1.2 v dd + 0.3 v jtag input low voltage v til --- -0.3 0.6 v jtag output high voltage (cmos) v toh i toh = -100ua v dd - 0.1 --- v jtag output low voltage (cmos) v tol i tol = 100ua --- 0.1 v jtag output high voltage (ttl) v toh i toh = -8ma v dd - 0.4 --- v jtag output low voltage (ttl) v tol i tol = 8ma --- 0.4 v jtag input leakage current i tli v tin = v ss to v dd -10 10 ua parameter symbol conditions units notes jtag input high level v tih 1.8 v jtag input low level v til 0.0 v jtag input rise & fall time 1.0 v/ns jtag input reference level 0.9 v jtag output reference level 0.9 v jtag output load condition see figure 1 (page 14)
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 19 / 27 july 6, 2001 jtag ac electrical characteristics jtag timing diagram parameter symbol min max units tck cycle time t thth 20 ns tck high pulse width t thtl 8 ns tck low pulse width t tlth 8 ns tms setup time t mvth 5 ns tms hold time t thmx 5 ns tdi setup time t dvth 5 ns tdi hold time t thdx 5 ns tck low to tdo valid t tlqv 10 ns tck low to tdo hold t tlqx 0 ns figure 5 t thtl t tlth t thth t thmx t mvth t thdx t dvth t tlqv t tlqx tck tms tdi tdi tdo
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 20 / 27 july 6, 2001 tap registers tap registers are serial shift registers that capture serial input data (from tdi) on the rising edge of tck, and drive serial output data (to tdo) on the subsequent falling edge of tck. they are divided into two groups: ?instruction registers?, of which there is one - the instruction register, and ?data registers?, of which there are three - the id register, the bypass register, and the boundary scan register. individual tap registers are ?selected? (inserted between tdi and tdo) when the appropriate sequence of commands is given to the tap controller. instruction register (3 bits) the instruction register stores the instructions that are executed by the tap controller when the tap controller is in the ?run-test / idle? state, or in any of the various ?data register? states. it is loaded with the idcode instruction at power- up, or when the tap controller is in the ?test-logic reset? state or the ?capture-ir? state. it is inserted between tdi and tdo when the tap controller is in the ?shift-ir? state, at which time it can be loaded with a new instruction. how- ever, newly loaded instructions are not executed by the tap controller until the tap controller has reached the ?update- ir? state. the instruction register is 3 bits wide, and is encoded as follows: bit 0 is the lsb of the instruction register, and bit 2 is the msb. when the instruction register is selected, tdi serially shifts data into the msb, and the lsb serially shifts data out through tdo. bypass register (1 bit) the bypass register is one bit wide, and provides the minimum length serial path between tdi and tdo. it is loaded with a logic ?0? when the bypass instruction has been loaded in the the instruction register and the tap controller is in the ?capture-dr? state. it is inserted between tdi and tdo when the bypass instruction has been loaded into the instruction register and the tap controller is in the ?shift-dr? state. code (2:0) instruction description 000 extest-a captures the sram?s i/o ring contents in the boundary scan register. inserts the boundary scan register between tdi and tdo. enables the sram?s data and clock output drivers. moves the portion of the boundary scan register compris- ing the sram?s output signals (dqs and cqs) to the input side of the sram?s output register. 001 idcode inserts the id register between tdi and tdo. 010 sample-z captures the sram?s i/o ring contents in the boundary scan register. inserts the boundary scan register between tdi and tdo. disables the sram?s data and clock output drivers. 011 bypass inserts the bypass register between tdi and tdo. 100 sample captures the sram?s i/o ring contents in the boundary scan register. inserts the boundary scan register between tdi and tdo. 101 private do not use. reserved for manufacturer use only. 110 bypass inserts the bypass register between tdi and tdo. 111 bypass inserts the bypass register between tdi and tdo.
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 21 / 27 july 6, 2001 id register (32 bits) the id register is loaded with a predetermined device- and manufacturer-specific identification code when the idcode instruction has been loaded into the instruction register and the tap controller is in the ?capture-dr? state. it is inserted between tdi and tdo when the idcode instruction has been loaded into the instruction register and the tap control- ler is in the ?shift-dr? state. the id register is 32 bits wide, and is encoded as follows: bit 0 is the lsb of the id register, and bit 31 is the msb. when the id register is selected, tdi serially shifts data into the msb, and the lsb serially shifts data out through tdo. boundary scan register (123 bits for x72, 84 bits for x36, 65 bits for x18) the boundary scan register is equal in length to the number of active signal connections to the sram (excluding the tap pins) plus a number of place holder locations reserved for density and/or functional upgrades. the boundary scan register is loaded with the contents of the sram?s i/o ring when the extest-a, sample, or sample-z instruction has been loaded into the instruction register and the tap controller is in the ?capture-dr? state. it is inserted between tdi and tdo when the extest-a, sample, or sample-z instruction has been loaded into the instruction register and the tap controller is in the ?shift-dr? state. the boundary scan register contains the following bits: for deterministic results, all signals composing the sram?s i/o ring must meet setup and hold times with respect to tck (same as tdi and tms) when sampled. place holders are required for some nc pins to allow for future density and/or functional upgrades. they are connected to v ss internally, regardless of pin connection externally. the boundary scan order assignment tables that follow depict the order in which the bits from the table above are ar- ranged in the boundary scan register. in each notation, bit 1 is the lsb bit of the register. when the boundary scan register is selected, tdi serially shifts data into the msb, and the lsb serially shifts data out through tdo. device revision number (31:28) part number (27:12) sony id (11:1) start bit (0) 256kb x 72 xxxx tbd 0000 1110 001 1 512kb x 36 xxxx tbd 0000 1110 001 1 1mb x 18 xxxx tbd 0000 1110 001 1 256kb x 72 512kb x 36 1mb x 18 dq 72 dq 36 dq 18 a, a1, a0 18 a, a1, a0 19 a, a1, a0 20 ck 1 ck 1 ck 1 cq, cq 4 cq, cq 4 cq, cq 4 e1 , adv, w , bw x 11 e1 , adv, w , bw x 7 e1 , adv, w , bw x 5 e2, e3, ep2, ep3 4 e2, e3, ep2, ep3 4 e2, e3, ep2, ep3 4 m2, m3, m4, zq 4 m2, m3, m4, zq 4 m2, m3, m4, zq 4 place holder 9 place holder 9 place holder 9
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 22 / 27 july 6, 2001 boundary scan order assignments (by exit sequence) tbd
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 23 / 27 july 6, 2001 tap instructions idcode idcode is the default instruction loaded into the instruction register at power-up, and when the tap controller is in the ?test-logic reset? state. when the idcode instruction is selected, a predetermined device- and manufacturer-specific identification code is load- ed into the id register when the tap controller is in the ?capture-dr? state, and the id register is inserted between tdi and tdo when the tap controller is in the ?shift-dr? state. normal sram operation is not disrupted when the idcode instruction is selected. bypass when the bypass instruction is selected, a logic ?0? is loaded into the bypass register when the tap controller is in the ?capture-dr? state, and the bypass register is inserted between tdi and tdo when the tap controller is in the ?shift-dr? state. normal sram operation is not disrupted when the bypass instruction is selected. sample when the sample instruction is selected, the individual logic states of all signals composing the sram?s i/o ring (see the boundary scan register description for the complete list of signals) are loaded into the boundary scan register when the tap controller is in the ?capture-dr? state, and the boundary scan register is inserted between tdi and tdo when the tap controller is in the ?shift-dr? state. normal sram operation is not disrupted when the sample instruction is selected. sample-z when the sample-z instruction is selected, the individual logic states of all signals composing the sram?s i/o ring (see the boundary scan register description for the complete list of signals) are loaded into the boundary scan register when the tap controller is in the ?capture-dr? state, and the boundary scan register is inserted between tdi and tdo when the tap controller is in the ?shift-dr? state. additionally, when the sample-z instruction is selected, the sram?s data and clock output drivers are disabled. consequently, normal sram operation is disrupted when the sample-z instruction is selected. read operations initi- ated while the sample-z instruction is selected will fail. extest-a when the extest-a instruction is selected, the individual logic states of all signals composing the sram?s i/o ring (see the boundary scan register description for the complete list of signals) are loaded into the boundary scan register when the tap controller is in the ?capture-dr? state, and the boundary scan register is inserted between tdi and tdo when the tap controller is in the ?shift-dr? state. additionally, when the extest-a instruction is selected, the sram?s data and clock output drivers are enabled, and the portion of the boundary scan register comprising the sram?s data and clock output signals is moved to the input side of the sram?s output register. the sram?s input clock can then be used to transfer the boundary scan register contents directly to the sram?s output pins (the input clock controls the sram?s output register). a single rising edge of the input clock is sufficient to transfer the data; additional rising edges have no further effect, provided the contents of the boundary scan register remain unchanged. consequently, normal sram operation is disrupted when the extest-a instruction is selected. read and write opera- tions initiated while the extest-a instruction is selected will fail.
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 24 / 27 july 6, 2001 tap controller the tap controller is a 16-state state machine that controls access to the various tap registers and executes the opera- tions associated with each tap instruction (see figure 7 below). state transitions are controlled by tms and occur on the rising edge of tck . the tap controller enters the ?test-logic reset? state in one of two ways: 1. at power up. 2. when a logic ?1? is applied to tms for at least 5 consecutive rising edges of tck. the tdi input receiver is sampled only when the tap controller is in either the ?shift-ir? state or the ?shift-dr? state. the tdo output driver is active only when the tap controller is in either the ?shift-ir? state or the ?shift-dr? state. tap controller state diagram figure 6 test-logic reset run-test / idle select dr-scan select ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 25 / 27 july 6, 2001 ? ordering information part number v dd i/o type configuration speed (cycle time / data access time) cxk79m72c161gb-33 1.8v lvcmos 256kb x 72 3.3ns / 1.8ns cxk79m72c161gb-4 1.8v lvcmos 256kb x 72 4.0ns / 2.1ns CXK79M72C161GB-44 1.8v lvcmos 256kb x 72 4.4ns / 2.3ns cxk79m36c161gb-33 1.8v lvcmos 512kb x 36 3.3ns / 1.8ns cxk79m36c161gb-4 1.8v lvcmos 512kb x 36 4.0ns / 2.1ns cxk79m36c161gb-44 1.8v lvcmos 512kb x 36 4.4ns / 2.3ns cxk79m18c161gb-33 1.8v lvcmos 1mb x 18 3.3ns / 1.8ns cxk79m18c161gb-4 1.8v lvcmos 1mb x 18 4.0ns / 2.1ns cxk79m18c161gb-44 1.8v lvcmos 1mb x 18 4.4ns / 2.3ns sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illus - trating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuit s.
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 26 / 27 july 6, 2001 ? (11x19) 209 pin bga package dimensions
sony ? s s ram cxk79m72c161gb / cxk79m36c161gb / cxk79m18c161gb preliminary 16mb 1x1lp, lvcmos, rev 0.2 27 / 27 july 6, 2001 ? revision history rev. # rev. date description of modifications rev 0.0 06/23/00 initial version. rev 0.1 02/23/01 1. added sony part numbers for each device. 2. removed asynchronous output enable ( g ) support. pin 6d now defined as ?mcl?. 3. modified dc recommended operating conditions section (p. 10). v mih-1.8 (min) 1.2v to 1.3v v mih-1.5 (min) 1.2v to 1.1v v mil-1.8 (max) 0.3v to 0.5v v mil-1.5 (max) 0.3v to 0.4v 3. modified dc electrical characteristics section (p. 11). added average power supply operating current specifications at 250 mhz (i dd-4 ). added power supply deselect operating current specification at 250 mhz (i dd2-4) . 4. modified ac electrical characteristics section (p. 12). removed ?-5? bin. added ?-44? bin. all bins removed t klcl specifications -33 t avkh , t bvkh , t dvkh 0.4ns to 0.7ns t khqv , t khqz 1.85ns to 1.8ns t khch , t khcz 1.65ns to 1.7ns t chqv 0.2ns to 0.4ns t chqx -0.2ns to -0.4ns t chcl t khkl 0.1 to t khkl 0.2 t clch t klkh 0.1 to t klkh 0.2 -4 t avkh , t bvkh , t dvkh 0.5ns to 0.8ns t khqv , t khqz 2.25ns to 2.1ns t chqv 0.2ns to 0.5ns t chqx -0.2ns to -0.5ns t chcl t khkl 0.1 to t khkl 0.25 t clch t klkh 0.1 to t klkh 0.25 5. updated the size and content of the boundary scan registers (p. 21). rev 0.2 07/06/01 1. modified dc electrical characteristics section (p. 11). added i dd-33 and i dd-44 average power supply operating current specifications. 2. added 209 pin bga package dimensions (p. 26).

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