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sprs086k ? january 1999 ? revised april 2003 1 post office box 1443 ? houston, texas 77251?1443 high-performance fixed-point digital signal processor (dsp) ? tms320c62x ? ? 4-, 3.33-ns instruction cycle time ? 250-, 300-mhz clock rate ? eight 32-bit instructions/cycle ? 2000, 2400 mips c6203b and c6202 gls ball grid array (bga) packages are pin-compatible with the c6204 glw bga package ? c6203b and c6202b gnz and gny packages are pin-compatible velociti ? advanced very-long-instruction- word (vliw) c62x ? dsp core ? eight highly independent functional units: ? six alus (32-/40-bit) ? two 16-bit multipliers (32-bit result) ? load-store architecture with 32 32-bit general-purpose registers ? instruction packing reduces code size ? all instructions conditional instruction set features ? byte-addressable (8-, 16-, 32-bit data) ? 8-bit overflow protection ? saturation ? bit-field extract, set, clear ? bit-counting ? normalization 7m-bit on-chip sram ? 3m-bit internal program/cache (96k 32-bit instructions) ? 4m-bit dual-access internal data (512k bytes) ? organized as two 256k-byte blocks for improved concurrency 32-bit external memory interface (emif) ? glueless interface to synchronous memories: sdram or sbsram ? glueless interface to asynchronous memories: sram and eprom ? 52m-byte addressable external memory space four-channel bootloading direct-memory-access (dma) controller with an auxiliary channel flexible phase-locked-loop (pll) clock generator 32-bit expansion bus (xbus) ? glueless/low-glue interface to popular pci bridge chips ? glueless/low-glue interface to popular synchronous or asynchronous microprocessor buses ? master/slave functionality ? glueless interface to synchronous fifos and asynchronous peripherals three multichannel buffered serial ports (mcbsps) ? direct interface to t1/e1, mvip, scsa framers ? st-bus-switching compatible ? up to 256 channels each ? ac97-compatible ? serial-peripheral interface (spi) compatible (motorola ? ) two 32-bit general-purpose timers ieee-1149.1 (jtag ? ) boundary-scan-compatible 352-pin bga package (gnz) 384-pin bga package (gls) 384-pin bga package (gny) 0.15- m/5-level metal process ? cmos technology 3.3-v i/os, 1.5-v internal please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. tms320c62x, velociti, and c62x are trademarks of texas instruments. motorola is a trademark of motorola, inc. all trademarks are the property of their respective owners. ? for more details, see the gls bga package bottom view. ? ieee standard 1149.1-1990 standard-test-access port and boundary scan architecture. copyright ? 2003, texas instruments incorporated
sprs086k ? january 1999 ? revised april 2003 2 post office box 1443 ? houston, texas 77251 ? 1443 table of contents parameter measurement information 44 . . . . . . . . . . . . . . . signal transition levels 44 . . . . . . . . . . . . . . . . . . . . . . . . . . timing parameters and board routing analysis 45 . . . . . . input and output clocks 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous memory timing 49 . . . . . . . . . . . . . . . . . . . . . synchronous-burst memory timing 52 . . . . . . . . . . . . . . . . . synchronous dram timing 56 . . . . . . . . . . . . . . . . . . . . . . . . hold /holda timing 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external interrupt timing 66 . . . . . . . . . . . . . . . . . . . . . . . . . . expansion bus synchronous fifo timing 67 . . . . . . . . . . . . expansion bus asynchronous peripheral timing 69 . . . . . . expansion bus synchronous host-port timing 72 . . . . . . . . expansion bus asynchronous host-port timing 78 . . . . . . . xhold/xholda timing 80 . . . . . . . . . . . . . . . . . . . . . . . . . . multichannel buffered serial port timing 82 . . . . . . . . . . . . . dmac, timer, power-down timing 94 . . . . . . . . . . . . . . . . . . jtag test-port timing 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . mechanical data 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . revision history 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnz, gls, and gny bga packages (bottom view) 4 . . . . description 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device characteristics 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c62x device compatibility 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . functional and cpu (dsp core) block diagram 9 . . . . . . . . . cpu (dsp core) description 10 . . . . . . . . . . . . . . . . . . . . . . . memory map summary 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripheral register descriptions 13 . . . . . . . . . . . . . . . . . . . . . dma synchronization events 18 . . . . . . . . . . . . . . . . . . . . . . . interrupt sources and interrupt selector 19 . . . . . . . . . . . . . . signal groups description 20 . . . . . . . . . . . . . . . . . . . . . . . . . . signal descriptions 23 development support 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . documentation support 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock pll 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply sequencing 41 . . . . . . . . . . . . . . . . . . . . . . . . . . ieee 1149.1 jtag compatibility statement 42 . . . . . . . . . . . absolute maximum ratings over operating case temperature ranges 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions 43 . . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature 43 . . revision history this data sheet revision history highlights the technical changes made to the sprs086j device-specific data sheet to make it an sprs086k revision. scope: applicable updates to the c62x device family, specifically to the c6203b devices, have been incorporated. added device-specific information for the new extended-temperature device (c6203bgnza-250). deleted c6203bgnza-300 device reference. page(s) no. additions/changes/deletions 7 table 1, characteristics of the pin-compatible dsps: added extended-temperature device-specific information for c6203b and c6202b device columns. changed the device product status for the c6202b device from advance information (ai) to production data (pd) deleted footnote description of product preview and advance information 8 c62x ? device compatibility section: added ? device clock speeds ? bullet and paragraph explanation 36 table 15, tms320c6203b device part numbers (p/ns) and ordering information: deleted extended-temperature device ? tms320c6203bgnza-173, 300 mhz/2400 mips, 1.7 v, 3.3 v, ? 40 c to 105 c corrected the device orderable p/n from ? tms32c6203bgnza 173 ? to ? tms32c6203bgnza 250 ? [may 2003]. 36 figure 4, tms320c6000 ? dsp platform device nomenclature (including tms320c6203b): added additional devices to the ? c6000 dsp: ? category 37 documentation support section: added paragraph referencing the tms320c6203, tms320c6203b digital signal processors silicon errata [literature number sprz174] added paragraph referencing the using ibis models for timing analysis application report [literature number spra839]
sprs086k ? january 1999 ? revised april 2003 3 post office box 1443 ? houston, texas 77251 ? 1443 page(s) no. additions/changes/deletions 38 clock pll section: deleted table 16, compatible clkin external clock source and associated paragraph reference 43 ? 96 electricals: added the device-specific information on the extended-temperature device (c6203bgnza-250) 43 absolute maximum ratings over operating case temperature ranges section: added the extended-temperature device-specific information to the ? operating case temperature ranges, t c : (a version) ? 43 recommended operating conditions table: added ? :c6203bgnza-250 ? to the a version of t c 45 timing parameters and board routing analysis section: added reference to the using ibis models for timing analysis application report (literature number spra839) in first paragraph. changed the title of table 19 to ? board-level timings example ? changed the title of figure 11 to ? board-level input/output timings ? 53 synchronous-burst memory timing section: timing requirements for synchronous-burst sram cycles for c6203b rev. 3 table: added c6203bgnza-250 extended-temperature device deleted c6203bgnza173-300 extended-temperature device 53 ? 54 synchronous-burst memory timing section: switching characteristics over recommended operating conditions for synchronous-burst sram cycles for c6203b rev. 3 table: added c6203bgnza-250 extended-temperature device deleted c6203bgnza173-300 extended-temperature device 57 synchronous dram timing section: timing requirements for synchronous dram cycles for c6203b rev. 3 table: added c6203bgnza-250 extended-temperature device deleted c6203bgnza173-300 extended-temperature device 58 ? 59 synchronous dram timing section: switching characteristics over recommended operating conditions for synchronous dram cycles for c6203b rev. 3 table: added c6203bgnza-250 extended-temperature device deleted c6203bgnza173-300 extended-temperature device 97 replaced gnz (s-pbga-n352) mechanical with latest version
sprs086k ? january 1999 ? revised april 2003 4 post office box 1443 ? houston, texas 77251 ? 1443 gnz, gls, and gny bga packages (bottom view) gnz 352-pin ball grid array (bga) package (bottom view) af ad ab aa ac w y u v ae r n p l h j k m f g d e b a c t 25 26 22 23 20 19 21 17 15 16 12 13 14 18 10 9 8 7 5 6 4 3 2 111 24
sprs086k ? january 1999 ? revised april 2003 5 post office box 1443 ? houston, texas 77251 ? 1443 gnz, gls, and gny bga packages (bottom view) (continued) 22 19 20 17 16 18 13 14 11 10 12 15 aa u w n r 8 7 5 4 6 j l e g 2 1 a c 3 9 21 b d f h k m p t v y ab gls 384-pin bga package (bottom view) the c6203b and c6202 gls bga packages are pin-compatible with the c6204 glw package except that the inner row of balls (which are additional power and ground pins) are removed for the c6204 glw package. these balls are not applicable for the c6204 devices 340-pin glw bga package. gny 384-pin bga package (bottom view) 22 19 20 17 16 18 13 14 11 10 12 15 aa u w n r 8 7 5 4 6 j l e g 2 1 a c 3 9 21 b d f h k m p t v y ab
sprs086k ? january 1999 ? revised april 2003 6 post office box 1443 ? houston, texas 77251 ? 1443 description the tms320c6203b device is part of the tms320c62x ? fixed-point dsp generation in the tms320c6000 ? dsp platform. the c62x ? dsp devices are based on the high-performance, advanced velociti ? very-long-instruction-word (vliw) architecture developed by texas instruments (ti), making these dsps an excellent choice for multichannel and multifunction applications. the tms320c62x ? dsp offers cost-effective solutions to high-performance dsp-programming challenges. the tms320c6203b has a performance capability of up to 2400 mips at a clock rate of 300 mhz. the c6203b dsp possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. this processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. the eight functional units provide six arithmetic logic units (alus) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. the c6203b can produce two multiply-accumulates (macs) per cycle for a total of 600 million macs per second (mmacs). the c6203b dsp also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. the c6203b device program memory consists of two blocks, with a 256k-byte block configured as memory-mapped program space, and the other 128k-byte block user-configurable as cache or memory-mapped program space. data memory for the c6203b consists of two 256k-byte blocks of ram. the c6203b device has a powerful and diverse set of peripherals. the peripheral set includes three multichannel buffered serial ports (mcbsps), two general-purpose timers, a 32-bit expansion bus (xbus) that offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit external memory interface (emif) capable of interfacing to sdram or sbsram and asynchronous peripherals. the c62x ? devices have a complete set of development tools which includes: a new c compiler, an assembly optimizer to simplify programming and scheduling, and a windows ? debugger interface for visibility into source code execution. device characteristics table 1 provides an overview of the tms320c6203b, tms320c6202, tms320c6202b, and tms320c6204 dsps. the table shows significant features of each device, including the capacity of on-chip ram, the peripherals, the execution time, and the package type with pin count, etc. this data sheet primarily focuses on the functionality of the tms320c6203b device although it also identifies to the user the pin-compatibility of the c6203b and c6202 gls, and the c6204 glw bga packages. this data sheet identifies the pin-compatibility of the c6203b and the c6202b gnz and gny packages. for the functionality information on the tms320c6202/02b devices, see the tms320c6202, tms320c6202b fixed-point digital signal processors data sheet (literature number sprs104). for the functionality information on the tms320c6204 device, see the tms320c6204 fixed-point digital signal processor data sheet (literature number sprs152). and for more details on the c6000 ? dsp part numbering, see figure 4. tms320c6000 and c6000 are trademarks of texas instruments. windows is a registered trademark of the microsoft corporation.
sprs086k ? january 1999 ? revised april 2003 7 post office box 1443 ? houston, texas 77251 ? 1443 device characteristics (continued) table 1. characteristics of the pin-compatible dsps hardware features c6203b c6202 c6202b c6204 emif peri p herals dma 4-channel with throughput enhancements 4-channel 4-channel with throughput enhancements 4-channel with throughput enhancements peripherals expansion bus mcbsps 3 3 3 2 32-bit timers 2 2 2 2 size (bytes) 384k 256k 256k 64k internal program memory organization block 0: 256k-byte mapped program block 1: 128k-byte cache/mapped program block 0: 128k-byte mapped program block 1: 128k-byte cache/mapped program block 0: 128k-byte mapped program block 1: 128k-byte cache/mapped program 1 block: 64k-byte cache/mapped program size (bytes) 512k 128k 128k 64k internal data memory organization 2 blocks: four 16-bit banks per block 50/50 split 2 blocks: four 16-bit banks per block 50/50 split 2 blocks: four 16-bit banks per block 50/50 split 2 blocks: four 16-bit banks per block 50/50 split cpu id + cpu rev id control status register (csr.[31:16]) 0x0003 0x0002 0x0003 0x0003 frequency mhz 250, 300 200, 250 250, 300 200 cycle time ns 3.33 ns (6203b-300) 4 ns (6203b-250) 4 ns (03bgnza-250) 4 ns (6202 ? 250) 5 ns (6202 ? 200) 3.33 ns (6202b-300) 4 ns (6202b-250) 4 ns (02bgnza-250) 5 ns (6204-200) core (v) 1.5 18 15 15 voltage core (v) 1.7 1.8 1.5 1.5 voltage i/o (v) 3.3 3.3 3.3 3.3 pll options clkin frequency multiplier [bypass (x1), x4, x6, x7, x8, x9, x10, and x11] all pll options (gls/gny pkgs) x1, x4, x8, x10 (gnz pkg) x1, x4 (both pkgs) all pll options (gny pkg) x1, x4, x8, x10 (gnz pkg) x1, x4 (both pkgs) 27 x 27 mm 352-pin gnz 352-pin gjl 352-pin gnz ? bga 18 x 18 mm 384-pin gls 384-pin gls ? 340-pin glw bga packages 18 x 18 mm 384-pin gny (2.x, 3.x only) ? 384-pin gny ? 16 x 16 mm ? ? ? 288-pin ghk process technology m 0.15 m 0.18 m 0.15 m 0.15 m product status ? product preview (pp) advance information (ai) production data (pd) pd pd pd pd ? production data information is current as of publication date. products conform to specifications per the terms of t exas instruments standard warranty. production processing does not necessarily include testing of all parameters.
sprs086k ? january 1999 ? revised april 2003 8 post office box 1443 ? houston, texas 77251 ? 1443 c62x ? device compatibility the tms320c6202, c6202b, c6203b, and c6204 devices are pin-compatible; thus, making new system designs easier and providing faster time to market. the following list summarizes the c62x ? dsp device characteristic differences: core supply voltage (1.8 v versus 1.7 v versus 1.5 v) the c6202 device core supply voltage is 1.8 v while the c6202b, c6203b, c6204 devices have core supply voltages of 1.5 v. the c6203b device (gls, gny, and gnz packages) also has a 1.7-v core supply voltage. device clock speeds the c6202b and c6203b devices run at ? 250 and ? 300 mhz clock speeds (with a c620xbgnza extended temperature device that also runs at ? 250 mhz), while the c6202 device runs at ? 200 and ? 250 mhz, and the c6204 device runs at ? 200 mhz clock speed. pll options availability table 1 identifies the available pll multiply factors [e.g., clkin x1 (pll bypassed), x4, etc.] for each of the c62x ? dsp devices. for additional details on the pll clock module and specific options for the c6203b device, see the clock pll section of this data sheet. for additional details on the pll clock module and specific options for the c6202/02b devices, see the clock pll section of the tms320c6202, tms320c6202b fixed-point digital signal processors data sheet (literature number sprs104). and for additional details on the pll clock module and specific options for the c6204 device, see the clock pll section of the tms320c6204 fixed-point digital signal processor data sheet (literature number sprs152). on-chip memory size the c6202/02b, c6203b, and c6204 devices have different on-chip program memory and data memory sizes (see table 1). mcbsps the c6202, c6202b, and c6203b devices have three mcbsps while the c6204 device has two mcbsps on-chip. for a more detailed discussion on migration concerns, and similarities/differences between the c6202, c6202b, c6203b, and c6204 devices, see the how to begin development today and migrate across the tms320c6202/02b/03b/04 dsps application report (literature number spra603).
sprs086k ? january 1999 ? revised april 2003 9 post office box 1443 ? houston, texas 77251 ? 1443 functional and cpu (dsp core) block diagram 32 multichannel buffered serial port 1 32 direct memory access controller (dma) (see table 1) test c62x cpu (dsp core) data path b b register file program access/cache controller instruction fetch instruction dispatch instruction decode data path a a register file pll (x1, x4, x6, x7, x8, x9, x10, x11) ? data access controller power- down logic .l1 .s1 .m1 .d1 .d2 .m2 .s2 .l2 sdram or sbsram rom/flash sram i/o devices synchronous fifos i/o devices timer 0 timer 1 external memory interface (emif) multichannel buffered serial port 0 multichannel buffered serial port 2 expansion bus (xbus) 32-bit internal program memory: 1 block program (256k bytes) 1 block program/cache (128k bytes) control registers control logic internal data memory (512k bytes) in-circuit emulation interrupt control framing chips: h.100, mvip, scsa, t1, e1 ac97 devices, spi devices, codecs host connection master /slave ti pci2040 power pc 683xx 960 c6203b digital signal processor peripheral control bus dma bus boot configuration interrupt selector ? for additional details on the pll clock module and specific options for the c6203b device, see table 1 and the clock pll section of this data sheet.
sprs086k ? january 1999 ? revised april 2003 10 post office box 1443 ? houston, texas 77251 ? 1443 cpu (dsp core) description the cpu fetches velociti ? advanced very-long instruction words (vliw) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. the velociti ? vliw architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. the first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. fetch packets are always 256 bits wide; however, the execute packets can vary in size. the variable-length execute packets are a key memory-saving feature, distinguishing the c62x cpu from other vliw architectures. the cpu features two sets of functional units. each set contains four units and a register file. one set contains functional units .l1, .s1, .m1, and .d1; the other set contains units .d2, .m2, .s2, and .l2. the two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. the two sets of functional units, along with two register files, compose sides a and b of the cpu [see the functional and cpu (dsp core) block diagram and figure 1]. the four functional units on each side of the cpu can freely share the 16 registers belonging to that side. additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. while register access by functional units on the same side of the cpu as the register file can service all the units in a single clock cycle, register access using the register file across the cpu supports one read and one write per cycle. another key feature of the c62x cpu is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). two sets of data-addressing units (.d1 and .d2) are responsible for all data transfers between the register files and the memory. the data address driven by the .d units allows data addresses generated from one register file to be used to load or store data to or from the other register file. the c62x cpu supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. all instructions are conditional, and most can access any one of the 32 registers. some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically ? true ? ). the two .m functional units are dedicated for multiplies. the two .s and .l functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. the processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. the 32-bit instructions destined for the individual functional units are ? linked ? together by ? 1 ? bits in the least significant bit (lsb) position of the instructions. the instructions that are ? chained ? together for simultaneous execution (up to eight in total) compose an execute packet. a ? 0 ? in the lsb of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. if an execute packet crosses the 256-bit-wide fetch-packet boundary, the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with nop instructions. the number of execute packets within a fetch packet can vary from one to eight. execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. after decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. while most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. all load and store instructions are byte-, half-word, or word-addressable.
sprs086k ? january 1999 ? revised april 2003 11 post office box 1443 ? houston, texas 77251 ? 1443 cpu (dsp core) description (continued) 8 8 2x 1x .l2 .s2 .m2 .d2 .d1 .m1 .s1 .l1 long src dst src 2 src 1 src 1 src 1 src 1 src 1 src 1 src 1 src 1 8 8 8 8 long dst long dst dst dst dst dst dst dst dst src 2 src 2 src 2 src 2 src 2 src 2 src 2 long src da1 da2 st1 ld1 ld2 st2 32 32 register file a (a0 ? a15) long src long dst long dst long src data path b data path a register file b (b0 ? b15) control register file figure 1. tms320c62x cpu (dsp core) data paths
sprs086k ? january 1999 ? revised april 2003 12 post office box 1443 ? houston, texas 77251 ? 1443 memory map summary table 2 shows the memory map address ranges of the c6203b device. the c6203b device has the capability of a map 0 or map 1 memory block configuration. these memory block configurations are set up at reset by the boot configuration pins (generically called bootmode[4:0]). for the c6203b device, the bootmode configuration is handled, at reset, by the expansion bus module (specifically xd[4:0] pins). for more detailed information on the c6203b device settings, which include the device boot mode configuration at reset and other device-specific configurations, see the boot configuration section and the boot configuration summary table of the tms320c6000 peripherals reference guide (literature number spru190). table 2. tms320c6203b memory map summary memory block description block size hex address range map 0 map 1 block size (bytes) hex address range external memory interface (emif) ce0 internal program ram 384k 0000_0000 ? 0005_ffff emif ce0 reserved 4m ? 384k 0006_0000 ? 003f_ffff emif ce0 emif ce0 12m 0040_0000 ? 00ff_ffff emif ce1 emif ce0 4m 0100_0000 ? 013f_ffff internal program ram emif ce1 384k 0140_0000 ? 0145_ffff reserved emif ce1 4m ? 384k 0146_0000 ? 017f_ffff emif registers 256k 0180_0000 ? 0183_ffff dma controller registers 256k 0184_0000 ? 0187_ffff expansion bus (xbus) registers 256k 0188_0000 ? 018b_ffff mcbsp 0 registers 256k 018c_0000 ? 018f_ffff mcbsp 1 registers 256k 0190_0000 ? 0193_ffff timer 0 registers 256k 0194_0000 ? 0197_ffff timer 1 registers 256k 0198_0000 ? 019b_ffff interrupt selector registers 512 019c_0000 ? 019c_01ff power-down registers 256k ? 512 019c_0200 ? 019f_ffff reserved 256k 01a0_0000 ? 01a3_ffff mcbsp 2 registers 256k 01a4_0000 ? 01a7_ffff reserved 5.5m 01a8_0000 ? 01ff_ffff emif ce2 16m 0200_0000 ? 02ff_ffff emif ce3 16m 0300_0000 ? 03ff_ffff reserved 1g ? 64m 0400_0000 ? 3fff_ffff xbus xce0 256m 4000_0000 ? 4fff_ffff xbus xce1 256m 5000_0000 ? 5fff_ffff xbus xce2 256m 6000_0000 ? 6fff_ffff xbus xce3 256m 7000_0000 ? 7fff_ffff internal data ram 512k 8000_0000 ? 8007_ffff reserved 2g ? 512k 8008_0000 ? ffff_ffff
sprs086k ? january 1999 ? revised april 2003 13 post office box 1443 ? houston, texas 77251 ? 1443 peripheral register descriptions table 3 through table 12 identify the peripheral registers for the c6203b device by their register names, acronyms, and hex address or hex address range. for more detailed information on the register contents, bit names, and their descriptions, see the tms320c6000 peripherals reference guide (literature number spru190). table 3. emif registers hex address range acronym register name comments 0180 0000 gblctl emif global control 0180 0004 cectl1 emif ce1 space control external or internal; dependent on map0 or map1 configuration (selected by the map bit in the emif gblctl register) 0180 0008 cectl0 emif ce0 space control external or internal; dependent on map0 or map1 configuration (selected by the map bit in the emif gblctl register) 0180 000c ? reserved 0180 0010 cectl2 emif ce2 space control corresponds to emif ce2 memory space: [0200 0000 ? 02ff ffff] 0180 0014 cectl3 emif ce3 space control corresponds to emif ce3 memory space: [0300 0000 ? 03ff ffff] 0180 0018 sdctl emif sdram control 0180 001c sdtim emif sdram refresh control 0180 0020 ? 0180 0054 ? reserved 0180 0058 ? 0183 ffff ? reserved
sprs086k ? january 1999 ? revised april 2003 14 post office box 1443 ? houston, texas 77251 ? 1443 peripheral register descriptions (continued) table 4. dma registers hex address range acronym register name 0184 0000 prictl0 dma channel 0 primary control 0184 0004 prictl2 dma channel 2 primary control 0184 0008 secctl0 dma channel 0 secondary control 0184 000c secctl2 dma channel 2 secondary control 0184 0010 src0 dma channel 0 source address 0184 0014 src2 dma channel 2 source address 0184 0018 dst0 dma channel 0 destination address 0184 001c dst2 dma channel 2 destination address 0184 0020 xfrcnt0 dma channel 0 transfer counter 0184 0024 xfrcnt2 dma channel 2 transfer counter 0184 0028 gblcnta dma global count reload register a 0184 002c gblcntb dma global count reload register b 0184 0030 gblidxa dma global index register a 0184 0034 gblidxb dma global index register b 0184 0038 gbladdra dma global address register a 0184 003c gbladdrb dma global address register b 0184 0040 prictl1 dma channel 1 primary control 0184 0044 prictl3 dma channel 3 primary control 0184 0048 secctl1 dma channel 1 secondary control 0184 004c secctl3 dma channel 3 secondary control 0184 0050 src1 dma channel 1 source address 0184 0054 src3 dma channel 3 source address 0184 0058 dst1 dma channel 1 destination address 0184 005c dst3 dma channel 3 destination address 0184 0060 xfrcnt1 dma channel 1 transfer counter 0184 0064 xfrcnt3 dma channel 3 transfer counter 0184 0068 gbladdrc dma global address register c 0184 006c gbladdrd dma global address register d 0184 0070 auxctl dma auxiliary control register 0184 0074 ? 0187 ffff ? reserved
sprs086k ? january 1999 ? revised april 2003 15 post office box 1443 ? houston, texas 77251 ? 1443 peripheral register descriptions (continued) table 5. expansion bus (xbus) registers hex address range acronym register name comments 0188 0000 xbgc expansion bus global control register 0188 0004 xcectl1 xce1 space control register corresponds to xbus xce0 memory space: [4000 0000 ? 4fff ffff] 0188 0008 xcectl0 xce0 space control register corresponds to xbus xce1 memory space: [5000 0000 ? 5fff ffff] 0188 000c xbhc expansion bus host port interface control register dsp read/write access only 0188 0010 xcectl2 xce2 space control register corresponds to xbus xce2 memory space: [6000 0000 ? 6fff ffff] 0188 0014 xcectl3 xce3 space control register corresponds to xbus xce3 memory space: [7000 0000 ? 7fff ffff] 0188 0018 ? reserved 0188 001c ? reserved 0188 0020 xbima expansion bus internal master address register dsp read/write access only 0188 0024 xbea expansion bus external address register dsp read/write access only 0188 0028 ? 018b ffff ? reserved ? xbisa expansion bus internal slave address ? xbd expansion bus data table 6. interrupt selector registers hex address range acronym register name comments 019c 0000 muxh interrupt multiplexer high selects which interrupts drive cpu interrupts 10 ? 15 (int10 ? int15) 019c 0004 muxl interrupt multiplexer low selects which interrupts drive cpu interrupts 4 ? 9 (int04 ? int09) 019c 0008 extpol external interrupt polarity sets the polarity of the external interrupts (ext_int4 ? ext_int7) 019c 000c ? 019c 01ff ? reserved 019c 0200 pdctl peripheral power-down control register 019c 0204 ? 019f ffff ? reserved table 7. peripheral power-down control register hex address range acronym register name 019c 0200 pdctl peripheral power-down control register
sprs086k ? january 1999 ? revised april 2003 16 post office box 1443 ? houston, texas 77251 ? 1443 peripheral register descriptions (continued) table 8. mcbsp 0 registers hex address range acronym register name comments 018c 0000 drr0 mcbsp0 data receive register the cpu and dma controller can only read this register; they cannot write to it. 018c 0004 dxr0 mcbsp0 data transmit register 018c 0008 spcr0 mcbsp0 serial port control register 018c 000c rcr0 mcbsp0 receive control register 018c 0010 xcr0 mcbsp0 transmit control register 018c 0014 srgr0 mcbsp0 sample rate generator register 018c 0018 mcr0 mcbsp0 multichannel control register 018c 001c rcer0 mcbsp0 receive channel enable register 018c 0020 xcer0 mcbsp0 transmit channel enable register 018c 0024 pcr0 mcbsp0 pin control register 018c 0028 ? 018f ffff ? reserved table 9. mcbsp 1 registers hex address range acronym register name comments 0190 0000 drr1 data receive register the cpu and dma controller can only read this register; they cannot write to it. 0190 0004 dxr1 mcbsp1 data transmit register 0190 0008 spcr1 mcbsp1 serial port control register 0190 000c rcr1 mcbsp1 receive control register 0190 0010 xcr1 mcbsp1 transmit control register 0190 0014 srgr1 mcbsp1 sample rate generator register 0190 0018 mcr1 mcbsp1 multichannel control register 0190 001c rcer1 mcbsp1 receive channel enable register 0190 0020 xcer1 mcbsp1 transmit channel enable register 0190 0024 pcr1 mcbsp1 pin control register 0190 0028 ? 0193 ffff ? reserved
sprs086k ? january 1999 ? revised april 2003 17 post office box 1443 ? houston, texas 77251 ? 1443 peripheral register descriptions (continued) table 10. mcbsp 2 registers hex address range acronym register name comments 01a4 0000 drr2 mcbsp2 data receive register the cpu and dma controller can only read this register; they cannot write to it. 01a4 0004 dxr2 mcbsp2 data transmit register 01a4 0008 spcr2 mcbsp2 serial port control register 01a4 000c rcr2 mcbsp2 receive control register 01a4 0010 xcr2 mcbsp2 transmit control register 01a4 0014 srgr2 mcbsp2 sample rate generator register 01a4 0018 mcr2 mcbsp2 multichannel control register 01a4 001c rcer2 mcbsp2 receive channel enable register 01a4 0020 xcer2 mcbsp2 transmit channel enable register 01a4 0024 pcr2 mcbsp2 pin control register 01a4 0028 ? 01a7 ffff ? reserved table 11. timer 0 registers hex address range acronym register name comments 0194 0000 ctl0 timer 0 control register determines the operating mode of the timer, monitors the timer status, and controls the function of the tout pin. 0194 0004 prd0 timer 0 period register contains the number of timer input clock cycles to count. this number controls the tstat signal frequency. 0194 0008 cnt0 timer 0 counter register contains the current value of the incrementing counter. 0194 000c ? 0197 ffff ? reserved table 12. timer 1 registers hex address range acronym register name comments 0198 0000 ctl1 timer 1 control register determines the operating mode of the timer, monitors the timer status, and controls the function of the tout pin. 0198 0004 prd1 timer 1 period register contains the number of timer input clock cycles to count. this number controls the tstat signal frequency. 0198 0008 cnt1 timer 1 counter register contains the current value of the incrementing counter. 0198 000c ? 019b ffff ? reserved
sprs086k ? january 1999 ? revised april 2003 18 post office box 1443 ? houston, texas 77251 ? 1443 dma synchronization events the c6203b dma supports up to four independent programmable dma channels, plus an auxiliary channel used for servicing the hpi module. the four main dma channels can be read/write synchronized based on the events shown in table 13. selection of these events is done via the rsync and wsync fields in the primary control registers of the specific dma channel. for more detailed information on the dma module, associated channels, and event-synchronization, see the direct memory access (dma) controller chapter of the tms320c6000 peripherals reference guide (literature number spru190). table 13. tms320c6203b dma synchronization events dma event number (binary) event name event description 00000 reserved reserved 00001 tint0 timer 0 interrupt 00010 tint1 timer 1 interrupt 00011 sd_int emif sdram timer interrupt 00100 ext_int4 external interrupt pin 4 00101 ext_int5 external interrupt pin 5 00110 ext_int6 external interrupt pin 6 00111 ext_int7 external interrupt pin 7 01000 dma_int0 dma channel 0 interrupt 01001 dma_int1 dma channel 1 interrupt 01010 dma_int2 dma channel 2 interrupt 01011 dma_int3 dma channel 3 interrupt 01100 xevt0 mcbsp0 transmit event 01101 revt0 mcbsp0 receive event 01110 xevt1 mcbsp1 transmit event 01111 revt1 mcbsp1 receive event 10000 dsp_int host processor-to-dsp interrupt 10001 xevt2 mcbsp2 transmit event 10010 revt2 mcbsp2 receive event 10011 ? 11111 reserved reserved. not used.
sprs086k ? january 1999 ? revised april 2003 19 post office box 1443 ? houston, texas 77251 ? 1443 interrupt sources and interrupt selector the c62x dsp core supports 16 prioritized interrupts, which are listed in table 14. the highest-priority interrupt is int_00 (dedicated to reset) while the lowest-priority interrupt is int_15. the first four interrupts (int_00 ? int_03) are non-maskable and fixed. the remaining interrupts (int_04 ? int_15) are maskable and default to the i nterrupt source specified in table 14. the interrupt source for interrupts 4 ? 15 can be programmed by modifying the selector value (binary value) in the corresponding fields of the interrupt selector control registers: muxh (address 0x019c0000) and muxl (address 0x019c0004). table 14. c6203b dsp interrupts cpu interrupt number interrupt selector control register selector value (binary) interrupt event interrupt source int_00 ? ? ? reset int_01 ? ? ? nmi int_02 ? ? ? reserved reserved. do not use. int_03 ? ? ? reserved reserved. do not use. int_04 ? muxl[4:0] 00100 ext_int4 external interrupt pin 4 int_05 ? muxl[9:5] 00101 ext_int5 external interrupt pin 5 int_06 ? muxl[14:10] 00110 ext_int6 external interrupt pin 6 int_07 ? muxl[20:16] 00111 ext_int7 external interrupt pin 7 int_08 ? muxl[25:21] 01000 dma_int0 dma channel 0 interrupt int_09 ? muxl[30:26] 01001 dma_int1 dma channel 1 interrupt int_10 ? muxh[4:0] 00011 sd_int emif sdram timer interrupt int_11 ? muxh[9:5] 01010 dma_int2 dma channel 2 interrupt int_12 ? muxh[14:10] 01011 dma_int3 dma channel 3 interrupt int_13 ? muxh[20:16] 00000 dsp_int host-processor-to-dsp interrupt int_14 ? muxh[25:21] 00001 tint0 timer 0 interrupt int_15 ? muxh[30:26] 00010 tint1 timer 1 interrupt ? ? 01100 xint0 mcbsp0 transmit interrupt ? ? 01101 rint0 mcbsp0 receive interrupt ? ? 01110 xint1 mcbsp1 transmit interrupt ? ? 01111 rint1 mcbsp1 receive interrupt ? ? 10000 reserved reserved. not used. ? ? 10001 xint2 mcbsp2 transmit interrupt ? ? 10010 rint2 mcbsp2 receive interrupt ? ? 10011 ? 11111 reserved reserved. do not use. ? interrupts int_00 through int_03 are non-maskable and fixed. ? interrupts int_04 through int_15 are programmable by modifying the binary selector values in the interrupt selector control registers fields. table 14 shows the default interrupt sources for interrupts int_04 through int_15. for more detailed informat ion on interrupt sources and selection, see the interrupt selector and external interrupts chapter of the tms320c6000 peripherals reference guide (literature number spru190).
sprs086k ? january 1999 ? revised april 2003 20 post office box 1443 ? houston, texas 77251 ? 1443 signal groups description trst ext_int7 clock/pll ieee standard 1149.1 (jtag) emulation reserved reset and interrupts dma status power-down status control/status tdi tdo tms tck clkin clkout1 clkmode0 pllv pllg pllf emu1 emu0 rsv2 rsv1 rsv0 nmi iack inum3 inum2 inum1 inum0 dmac3 dmac2 dmac1 dmac0 pd rsv4 ext_int6 ext_int5 ext_int4 reset clkout2 clkmode1 clkmode2 ? ? clkmode2 is not available on the gnz package for the c6203b device. rsv3 figure 2. cpu (dsp core) signals
sprs086k ? january 1999 ? revised april 2003 21 post office box 1443 ? houston, texas 77251 ? 1443 signal groups description (continued) ce3 are ed[31:0] ce2 ce1 ce0 ea[21:2] be3 be2 be1 be0 hold holda tout1 clkx1 fsx1 dx1 clkr1 fsr1 dr1 clks1 aoe awe ardy sda10 sdras /ssoe sdcas /ssads sdwe /sswe tout0 clkx2 fsx2 dx2 clkr2 fsr2 dr2 clks2 data memory map space select word address byte enables hold/ holda 32 20 asynchronous memory control synchronous memory control emif (external memory interface) timer 1 transmit transmit timer 0 timers mcbsp1 mcbsp2 receive receive clock clock mcbsps (multichannel buffered serial ports) tinp1 tinp0 clkx0 fsx0 dx0 clkr0 fsr0 dr0 clks0 transmit mcbsp0 receive clock figure 3. peripheral signals
sprs086k ? january 1999 ? revised april 2003 22 post office box 1443 ? houston, texas 77251 ? 1443 signal groups description (continued) xd[31:0] xbe2 /xa4 xbe1 /xa3 xbe0 /xa2 xrdy xhold xholda xfclk xclkin xoe xre data byte-enable control/ address control arbitration 32 clocks i/o port control expansion bus xwe /xwait xce3 xce2 xce1 xce0 xcs xas host interface control xcntl xw/r xblast xboff xbe3 /xa5 figure 3. peripheral signals (continued)
sprs086k ? january 1999 ? revised april 2003 23 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions signal pin no. signal name gnz gls/ gny type ? description clock/pll clkin c12 b10 i clock input clkout1 ad20 y18 o clock output at full device speed clkout2 ac19 ab19 o clock output at half (1/2) of device speed ? used for synchronous memory interface clkmode0 b15 b12 i clock mode selects ? selects what multi p ly factors of the in p ut clock frequency the cpu frequency clkmode1 c11 a9 i ? selects what multiply factors of the input clock frequency the cpu frequency equals. for more details on the gnz gls and gny clkmode pins and the pll m ltipl clkmode2 ? a14 i for more details on the gnz, gls, and gny clkmode pins and the pll multiply factors for the c6203b device, see the clock pll section of this data sheet. pllv ? d13 c11 a pll analog v cc connection for the low-pass filter pllg ? d14 c12 a pll analog gnd connection for the low-pass filter pllf ? c13 a11 a pll low-pass filter connection to external components and a bypass capacitor jtag emulation tms ad7 y5 i jtag test-port mode select (features an internal pullup) tdo ae6 aa4 o/z jtag test-port data out tdi af5 y4 i jtag test-port data in (features an internal pullup) tck ae5 ab2 i jtag test-port clock trst ac7 aa3 i jtag test-port reset (features an internal pulldown) emu1 af6 aa5 i/o/z emulation pin 1, pullup with a dedicated 20-k ? resistor ? emu0 ac8 ab4 i/o/z emulation pin 0, pullup with a dedicated 20-k ? resistor ? reset and interrupts reset k2 j3 i device reset nmi l2 k2 i nonmaskable interrupt ? edge-driven (rising edge) ext_int7 v4 u2 external interru p ts ext_int6 y2 u3 i e xterna l i nterrupts ? ed g e-driven ext_int5 aa1 w1 i ? edge-driven ? polarity independently selected via the external interrupt polarity register bits (extpol [3 0]) ext_int4 w4 v2 yy yg (extpol.[3:0]) iack y1 v1 o interrupt acknowledge for all active interrupts serviced by the cpu inum3 v2 r3 inum2 u4 t1 o active interrupt identification number ? valid during iack for all active interrupts (not just external) inum1 v3 t2 o ? valid during iack for all active interrupts (not just external) ? encoding order follows the interru p t - service fetch -p acket ordering inum0 w2 t3 ? encoding order follows the interru t - service fetch - acket ordering ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? pllv, pllg, and pllf are not part of external voltage supply or ground. see the clock pll section for information on how to connect these pins. a = analog signal (pll filter) ? for emulation and normal operation, pull up emu1 and emu0 with a dedicated 20-k ? resistor. for boundary scan, pull down emu1 and emu0 with a dedicated 20-k ? resistor.
sprs086k ? january 1999 ? revised april 2003 24 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal pin no. signal name gnz gls/ gny type ? description power-down status pd ab2 y2 o power-down modes 2 or 3 (active if high) expansion bus xclkin a9 c8 i expansion bus synchronous host interface clock input xfclk b9 a8 o expansion bus fifo interface clock output xd31 d15 c13 xd30 b16 a13 xd29 a17 c14 xd28 b17 b14 xd27 d16 b15 xd26 a18 c15 xd25 b18 a15 xd24 d17 b16 xd23 c18 c16 xd22 a20 a17 eibdt xd21 d18 b17 expansion bus data ? used for transfer of data address and control xd20 c19 c17 ? u se d f or t rans f er o f d a t a, a dd ress, an d con t ro l ? also controls initialization of dsp modes and expansion bus at reset xd19 a21 b18 ? also controls initialization of dsp modes and ex ansion bus at reset [note: for more information on pin control and boot configuration fields, see the boot modes d c fi ti h t f th tms320c6000 p i h l r f g id (lit t xd18 d19 a19 and configuration chapter of the tms320c6000 peripherals reference guide (literature number spru190)] xd17 c20 c18 num b er spru190)] xd16 b21 b19 i/o/z xd[30:16] ? xce[3:0] memory type xd13 xblast polarit xd15 a22 c19 i/o/z xd13 ? xblast polarity xd12 ? xw/r p olarity xd14 d20 b20 xd12 ? xw/r polarity xd11 ? asynchronous or synchronous host operation xd13 b22 a21 xd11 asynchronous or synchronous host o eration xd10 ? arbitration mode (internal or external) xd9 fifo mode xd12 e25 c21 xd9 ? fifo mode xd8 ? little endian/big endian xd11 f24 d20 xd8 ? little endian/big endian xd[4:0] ? boot mode xd10 e26 b22 xd[4:0] boot mode all other ex p ansion bus data p ins not listed should be p ulled down xd9 f25 d21 all other expansion bus data pins not listed should be pulled down. xd8 g24 e20 xd7 h23 e21 xd6 f26 d22 xd5 g25 f20 xd4 j23 f21 xd3 g26 e22 xd2 h25 g20 xd1 j24 g21 xd0 k23 g22 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sprs086k ? january 1999 ? revised april 2003 25 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal pin no. signal name gnz gls/ gny type ? description expansion bus (continued) xce3 f2 d2 xce2 e1 b1 o/z expansion bus i/o port memory space enables ? enabled by bits 28 29 and 30 of the word address xce1 f3 d3 o/z ? enabled by bits 28, 29, and 30 of the word address ? only one asserted during any i/o p ort data access xce0 e2 c2 ? only one asserted during any i/o ort data access xbe3 /xa5 c7 c5 xbe2 /xa4 d8 a4 i/o/z expansion bus multiplexed byte-enable control/address signals ? act as byte enable for host p ort o p eration xbe1 /xa3 a6 b5 i/o/z ? act as byte-enable for host-port operation ? act as address for i/o p ort o p eration xbe0 /xa2 c8 c6 ? act as address for i/o ort o eration xoe a7 a6 o/z expansion bus i/o port output-enable xre c9 c7 o/z expansion bus i/o port read-enable xwe /xwait d10 b7 o/z expansion bus i/o port write-enable and host-port wait signals xcs a10 c9 i expansion bus host-port chip-select input xas d9 b6 i/o/z expansion bus host-port address strobe xcntl b10 b9 i expansion bus host control. xcntl selects between expansion bus address or data register. xw/r d11 b8 i/o/z expansion bus host-port write/read-enable. xw/r polarity is selected at reset. xrdy a5 c4 i/o/z expansion bus host-port ready (active low) and i/o port ready (active high) xblast b6 b4 i/o/z expansion bus host-port burst last-polarity selected at reset xboff b11 a10 i expansion bus back off xhold b5 a2 i/o/z expansion bus hold request xholda d7 b3 i/o/z expansion bus hold acknowledge emif ? control signals common to all types of memory ce3 ab25 y21 ce2 aa24 w20 o/z memory space enables ? enabled by bits 24 and 25 of the word address ce1 ab26 aa22 o/z ? enabled by bits 24 and 25 of the word address ? only one asserted during any external data access ce0 aa25 w21 ? only one asserted during any external data access be3 y24 v20 byte-enable control be2 w23 v21 o/z b yte-ena bl e contro l ? decoded from the two lowest bits of the internal address be1 aa26 w22 o/z ? decoded from the two lowest bits of the internal address ? byte-write enables for most types of memory c b di tl t d t sdram d d it k i l (sdqm) be0 y25 u20 yyy ? can be directly connected to sdram read and write mask signal (sdqm) ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sprs086k ? january 1999 ? revised april 2003 26 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal pin no. signal name gnz gls/ gny type ? description emif ? address ea21 j25 h20 ea20 j26 h21 ea19 l23 h22 ea18 k25 j20 ea17 l24 j21 ea16 l25 k21 ea15 m23 k20 ea14 m24 k22 ea13 m25 l21 ea12 n23 l20 o/z e ternal address ( ord address) ea11 p24 l22 o/z external address (word address) ea10 p23 m20 ea9 r25 m21 ea8 r24 n22 ea7 r23 n20 ea6 t25 n21 ea5 t24 p21 ea4 u25 p20 ea3 t23 r22 ea2 v26 r21 emif ? data ed31 ad8 y6 ed30 ac9 aa6 ed29 af7 ab6 ed28 ad9 y7 ed27 ac10 aa7 ed26 ae9 ab8 ed25 af9 y8 ed24 ac11 aa8 ed23 ae10 aa9 i/o/z e ternal data ed22 ad11 y9 i/o/z external data ed21 ae11 ab10 ed20 ac12 y10 ed19 ad12 aa10 ed18 ae12 aa11 ed17 ac13 y11 ed16 ad14 ab12 ed15 ac14 y12 ed14 ae15 aa12 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sprs086k ? january 1999 ? revised april 2003 27 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal pin no. signal name gnz gls/ gny type ? description emif ? data (continued) ed13 ad15 aa13 ed12 ac15 y13 ed11 ae16 ab13 ed10 ad16 y14 ed9 ae17 aa14 ed8 ac16 aa15 ed7 af18 y15 i/o/z e ternal data ed6 ae18 ab15 i/o/z external data ed5 ac17 aa16 ed4 ad18 y16 ed3 af20 ab17 ed2 ac18 aa17 ed1 ad19 y17 ed0 af21 aa18 emif ? asynchronous memory control are v24 t21 o/z asynchronous memory read-enable aoe v25 r20 o/z asynchronous memory output-enable awe u23 t22 o/z asynchronous memory write-enable ardy w25 t20 i asynchronous memory ready input emif ? synchronous dram (sdram)/synchronous burst sram (sbsram) control sda10 ae21 aa19 o/z sdram address 10 (separate for deactivate command) sdcas /ssads ae22 ab21 o/z sdram column-address strobe/sbsram address strobe sdras /ssoe af22 y19 o/z sdram row-address strobe/sbsram output-enable sdwe /sswe ac20 aa20 o/z sdram write-enable/sbsram write-enable emif ? bus arbitration hold y26 v22 i hold request from the host holda v23 u21 o hold-request-acknowledge to the host timer 0 tout0 f1 d1 o timer 0 or general-purpose output tinp0 h4 e2 i timer 0 or general-purpose input timer 1 tout1 j4 f2 o timer 1 or general-purpose output tinp1 g2 f3 i timer 1 or general-purpose input dma action complete status dmac3 y3 v3 dmac2 aa2 w2 o dma action complete dmac1 ab1 aa1 o dma action complete dmac0 aa3 w3 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sprs086k ? january 1999 ? revised april 2003 28 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal pin no. signal name gnz gls/ gny type ? description multichannel buffered serial port 0 (mcbsp0) clks0 m4 k3 i external clock source (as opposed to internal) clkr0 m2 l2 i/o/z receive clock clkx0 m3 k1 i/o/z transmit clock dr0 r2 m2 i receive data dx0 p4 m3 o/z transmit data fsr0 n3 m1 i/o/z receive frame sync fsx0 n4 l3 i/o/z transmit frame sync multichannel buffered serial port 1 (mcbsp1) clks1 g1 e1 i external clock source (as opposed to internal) clkr1 j3 g2 i/o/z receive clock clkx1 h2 g3 i/o/z transmit clock dr1 l4 h1 i receive data dx1 j1 h2 o/z transmit data fsr1 j2 h3 i/o/z receive frame sync fsx1 k4 g1 i/o/z transmit frame sync multichannel buffered serial port 2 (mcbsp2) clks2 r3 n1 i external clock source (as opposed to internal) clkr2 t2 n2 i/o/z receive clock clkx2 r4 n3 i/o/z transmit clock dr2 v1 r2 i receive data dx2 t4 r1 o/z transmit data fsr2 u2 p3 i/o/z receive frame sync fsx2 t3 p2 i/o/z transmit frame sync reserved for test rsv0 l3 j2 i reserved for testing, pullup with a dedicated 20-k ? resistor rsv1 g3 e3 i reserved for testing, pullup with a dedicated 20-k ? resistor rsv2 a12 b11 i reserved for testing, pullup with a dedicated 20-k ? resistor rsv3 c15 b13 o reserved (leave unconnected, do not connect to power or ground) rsv4 d12 c10 o reserved (leave unconnected, do not connect to power or ground) ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sprs086k ? january 1999 ? revised april 2003 29 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal pin no. signal name gnz gls/ gny type ? description supply voltage pins a11 a3 a16 a7 b7 a16 b8 a20 b19 d4 b20 d6 c6 d7 c10 d9 c14 d10 c17 d13 c21 d14 g4 d16 g23 d17 h3 d19 h24 f1 k3 f4 k24 f19 l1 f22 l26 g4 dv dd n24 g19 s 3.3-v supply voltage (i/o) dv dd p3 j4 s 3.3 v su ly voltage (i/o) t1 j19 t26 k4 u3 k19 u24 l1 w3 m22 w24 n4 y4 n19 y23 p4 ad6 p19 ad10 t4 ad13 t19 ad17 u1 ad21 u4 ae7 u19 ae8 u22 ae19 w4 ae20 w6 af11 w7 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sprs086k ? january 1999 ? revised april 2003 30 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal pin no. signal name gnz gls/ gny type ? description supply voltage pins (continued) af16 w9 ? w10 ? w13 ? w14 ? w16 dv dd ? w17 s 3.3-v supply voltage (i/o) dv dd ? w19 s 3.3 v su ly voltage (i/o) ? ab5 ? ab9 ? ab14 ? ab18 a1 e7 a2 e8 a3 e10 a24 e11 a25 e12 a26 e13 b1 e15 b2 e16 b3 f7 b24 f8 b25 f9 b26 f11 c1 f12 c2 f14 15v l lt ( ) cv dd c3 f15 s 1.5-v supply voltage (core) 17 - vsu pp ly voltage (core) (c6203bgls c6203bgny and c6203bgnz 1 7 - v p arts only) cv dd c4 f16 s 1 . 7 - v supp l y vo lt age ( core ) (c6203bgls , c6203bgny , an d c6203bgnz 1 . 7 - v par t s on l y ) c23 g5 c24 g6 c25 g17 c26 g18 d3 h5 d4 h6 d5 h17 d22 h18 d23 j6 d24 j17 e4 k5 e23 k18 ab4 l5 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sprs086k ? january 1999 ? revised april 2003 31 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal pin no. signal name gnz gls/ gny type ? description supply voltage pins (continued) ab23 l6 ac3 l17 ac4 l18 ac5 m5 ac22 m6 ac23 m17 ac24 m18 ad1 n5 ad2 n18 ad3 p6 ad4 p17 ad23 r5 ad24 r6 ad25 r17 ad26 r18 ae1 t5 ae2 t6 15v l lt ( ) cv dd ae3 t17 s 1.5-v supply voltage (core) 17 - vsu pp ly voltage (core) (c6203bgls c6203bgny and c6203bgnz 1 7 - v p arts only) cv dd ae24 t18 s 1 . 7 - v supp l y vo lt age ( core ) (c6203bgls , c6203bgny , an d c6203bgnz 1 . 7 - v par t s on l y ) ae25 u7 ae26 u8 af1 u9 af2 u11 af3 u12 af24 u14 af25 u15 af26 u16 ? v7 ? v8 ? v10 ? v11 ? v12 ? v13 ? v15 ? v16 ground pins a4 a1 v a8 a5 gnd gro nd pins v ss a13 a12 gnd ground pins a14 a18 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sprs086k ? january 1999 ? revised april 2003 32 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal pin no. signal name gnz gls/ gny type ? description ground pins (continued) a15 a22 a19 b2 a23 b21 b4 c1 b12 c3 b13 c20 b14 c22 b23 d5 c5 d8 c16 d11 c22 d12 d1 d15 d2 d18 d6 e4 d21 e5 d25 e6 d26 e9 v e3 e14 gnd gro nd pins v ss e24 e17 gnd ground pins f4 e18 f23 e19 h1 f5 h26 f6 k1 f10 k26 f13 m1 f17 m26 f18 n1 h4 n2 h19 n25 j1 n26 j5 p1 j18 p2 j22 p25 k6 p26 k17 r1 l4 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sprs086k ? january 1999 ? revised april 2003 33 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal pin no. signal name gnz gls/ gny type ? description ground pins (continued) r26 l19 u1 m4 u26 m19 w1 n6 w26 n17 aa4 p1 aa23 p5 ab3 p18 ab24 p22 ac1 r4 ac2 r19 ac6 u5 ac21 u6 ac25 u10 ac26 u13 ad5 u17 ad22 u18 ae4 v4 v ss ae13 v5 gnd ground pins v ss ae14 v6 gnd ground ins ae23 v9 af4 v14 af8 v17 af10 v18 af12 v19 af13 w5 af14 w8 af15 w11 af17 w12 af19 w15 af23 w18 ? y1 ? y3 ? y20 ? y22 ? aa2 ? aa21 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sprs086k ? january 1999 ? revised april 2003 34 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal pin no. signal name gnz gls/ gny type ? description ground pins (continued) ? ab1 ? ab3 ? ab7 v ss ? ab11 gnd ground pins v ss ? ab16 gnd ground ins ? ab20 ? ab22 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground development support ti offers an extensive line of development tools for the tms320c6000 ? dsp platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. the following products support development of c6000 ? dsp-based applications: software development tools: code composer studio ? integrated development environment (ide) including editor c/c++/assembly code generation, and debug plus additional development tools scalable, real-time foundation software (dsp/bios ? ), which provides the basic run-time target software needed to support any dsp application. hardware development tools: extended development system (xds ? ) emulator (supports c6000 ? dsp multiprocessor system debug) evm (evaluation module) for a complete listing of development-support tools for the tms320c6000 ? dsp platform, visit the texas instruments web site on the worldwide web at http://www.ti.com uniform resource locator (url). for information on pricing and availability, contact the nearest ti field sales office or authorized distributor. code composer studio, dsp/bios, xds, and tms320 are trademarks of texas instruments.
sprs086k ? january 1999 ? revised april 2003 35 post office box 1443 ? houston, texas 77251 ? 1443 device and development-support tool nomenclature to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all tms320 ? dsp devices and support tools. each tms320 ? dsp commercial family member has one of three prefixes: tmx, tmp, or tms. texas instruments recommends two of three possible prefix designators for support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (tmx/tmdx) through fully qualified production devices/tools (tms/tmds). device development evolutionary flow: tmx experimental device that is not necessarily representative of the final device ? s electrical specifications tmp final silicon die that conforms to the device ? s electrical specifications but has not completed quality and reliability verification tms fully qualified production device support tool development evolutionary flow: tmdx development-support product that has not yet completed t exas instruments internal qualification testing. tmds fully qualified development-support product tmx and tmp devices and tmdx development-support tools are shipped against the following disclaimer: ? developmental product is intended for internal evaluation purposes. ? tms devices and tmds development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti ? s standard warranty applies. predictions show that prototype devices (tmx or tmp) have a greater failure rate than the standard production devices. t exas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. ti device nomenclature also incl udes a suffix with the device family name. this suffix indicates the package type (for example, gls), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -300 is 300 mhz). table 15 lists the device orderable part numbers (p/ns) and figure 4 provides a legend for reading the complete device name for any member of the tms320c6000 ? dsp platform. for more information on the c6203b device orderable p/ns, visit the texas instruments web site on the worldwide web at http://www.ti.com url, or contact the nearest ti field sales office or authorized distributor.
sprs086k ? january 1999 ? revised april 2003 36 post office box 1443 ? houston, texas 77251 ? 1443 device and development-support tool nomenclature (continued) table 15. tms320c6203b device part numbers (p/ns) and ordering information device orderable p/n device speed core and i/o voltage operating case temperature device orderable p/n device speed cv dd (core) dv dd (i/o) temperature range c6203b rev. 2 tms32c6203bgls173h 250 mhz/2000 mips 1.5 v 3.3 v 0 c to 90 c tms32c6203bgls173h 300 mhz/2400 mips 1.7 v 3.3 v 0 c to 90 c tms320c6203bgls-3h 300 mhz/2400 mips 1.5 v 3.3 v 0 c to 90 c c6203b rev. 3 tms320c6203bgny300 300 mhz/2400 mips 1.5 v 3.3 v 0 c to 90 c tms320c6203bgny300 300 mhz/2400 mips 1.7 v 3.3 v 0 c to 90 c tms320c6203bgny173 250 mhz/2000 mips 1.5 v 3.3 v 0 c to 90 c tms320c6203bgny173 300 mhz/2400 mips 1.7 v 3.3 v 0 c to 90 c tms320c6203bgny3e 300 mhz/2400 mips 1.5 v 3.3 v 0 c to 90 c tms320c6203bgnz300 300 mhz/2400 mips 1.5 v 3.3 v 0 c to 90 c tms320c6203bgnz300 300 mhz/2400 mips 1.7 v 3.3 v 0 c to 90 c tms320c6203bgnz173 250 mhz/2000 mips 1.5 v 3.3 v 0 c to 90 c tms320c6203bgnz173 300 mhz/2400 mips 1.7 v 3.3 v 0 c to 90 c tms32c6203bgnza250 250 mhz/2000 mips 1.5 v 3.3 v ? 40 c to 105 c prefix device speed range tms 320 c 6203b gnz 300 tmx = experimental device tmp = prototype device tms = qualified device smj = mil-prf-38535, qml sm = high rel (non-38535) device family 320 = tms320 dsp family technology package type ? gfn = 256-pin plastic bga ggp = 352-pin plastic bga gjc = 352-pin plastic bga gjl = 352-pin plastic bga gls = 384-pin plastic bga glw = 340-pin plastic bga gny = 384-pin plastic bga gnz = 352-pin plastic bga glz = 532-pin plastic bga ghk = 288-pin plastic microstar bga c = cmos device c6000 dsp: 6201 6205 6415 6711c 6202 6211 6416 6712 6202b 6211b 6701 6712c 6203b 6411 6711 6713 6204 6414 6711b ? bga = ball grid array temperature range (default: 0 c to 90 c) ( ) blank = 0 c to 90 c, commercial temperature a= ? 40 c to 105 c, extended temperature 100 mhz 120 mhz 150 mhz 167 mhz 200 mhz 233 mhz 250 mhz 300 mhz 500 mhz 600 mhz figure 4. tms320c6000 ? dsp platform device nomenclature (including tms320c6203b) microstar bga is a trademark of texas instruments.
sprs086k ? january 1999 ? revised april 2003 37 post office box 1443 ? houston, texas 77251 ? 1443 documentation support extensive documentation supports all tms320 ? dsp family devices from product announcement through applications development. the types of documentation available include: data sheets, such as this document, with design specifications; complete user ? s reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. the following is a brief, descriptive list of support documentation specific to the c6000 ? dsp devices: the tms320c6000 cpu and instruction set reference guide (literature number spru189) describes the c6000 ? cpu (dsp core) architecture, instruction set, pipeline, and associated interrupts. the tms320c6000 peripherals reference guide (literature number spru190) describes the functionality of the peripherals available on the c6000 ? dsp platform of devices, such as the 64-/32-/16-bit external memory interfaces (emifs), 32-/16-bit host-port interfaces (hpis), multichannel buffered serial ports (mcbsps), direct memory access (dma), enhanced direct-memory-access (edma) controller, expansion bus (xbus), peripheral component interconnect (pci), clocking and phase-locked loop (pll); and power-down modes. this guide also includes information on internal data and program memories. the how to begin development today and migrate across the tms320c6202/02b/03b/04 dsps application report (literature number spra603) describes the migration concerns and identifies the similarities and differences between the c6202, c6202b, c6203b, and c6204 c6000 ? dsp devices. the tms320c6203, tms320c6203b digital signal processors silicon errata (literature number sprz174) describes the known exceptions to the functional specifications for particular silicon revisions of the tms320c6203 and tms320c6203b devices. the using ibis models for timing analysis application report (literature number spra839) describes how to properly use ibis models to attain accurate timing analysis for a given system. the tools support documentation is electronically available within the code composer studio ? ide. for a complete listing of the latest c6000 ? dsp documentation, visit the texas instruments web site on the worldwide web at http://www.ti.com uniform resource locator (url).
sprs086k ? january 1999 ? revised april 2003 38 post office box 1443 ? houston, texas 77251 ? 1443 clock pll most of the internal c6203b clocks are generated from a single source through the clkin pin. this source clock either drives the pll, which multiplies the source clock in frequency to generate the internal cpu clock, or bypasses the pll to become the internal cpu clock. to use the pll to generate the cpu clock, the external pll filter circuit must be properly designed. figure 5, and table 16 through table 18 show the external pll circuitry for either x1 (pll bypass) or x4 pll multiply modes. figure 6 shows the external pll circuitry for a system with only x1 (pll bypass) mode. to minimize the clock jitter, a single clean power supply should power both the c6203b device and the external clock oscillator circuit. noise coupling into pllf directly impacts pll clock jitter. the minimum clkin rise and fall times should also be observed. for the input clock timing requirements, see the input and output clocks electricals section. clkmode0 clkmode1 pll pllv clkin loop filter pllclk pllmult clkin pllg c2 internal to c6203b cpu clock c1 r1 3.3 v 10 f 0.1 f pllf c3 c4 1 0 clkmode2 ? (for the pll options and clkmode pins setup, see table 16 through table 18) emi filter ? the clkmode2 pin is not available for the c6203b gnz package. notes: a. keep the lead length and the number of vias between pin pllf, pin pllg, r1, c1, and c2 to a minimum. in addition, place all pll components (r1, c1, c2, c3, c4, and emi filter) as close to the c6000 ? dsp device as possible. best performance is achieved with the pll components on a single side of the board without jumpers, switches, or components other than the ones shown. b. for reduced pll jitter, maximize the spacing between switching signals and the pll external components (r1, c1, c2, c3, c4, and the emi filter). c. the 3.3-v supply for the emi filter must be from the same 3.3-v power plane supplying the i/o voltage, dv dd . d. emi filter manufacturer: tdk part number acf451832-333, 223, 153, 103. panasonic part number exccet103u. figure 5. external pll circuitry for either pll multiply modes or x1 (bypass) mode
sprs086k ? january 1999 ? revised april 2003 39 post office box 1443 ? houston, texas 77251 ? 1443 clock pll (continued) pll pllv clkin loop filter pllclk pllmult clkin pllg internal to c6203b cpu clock pllf 1 0 3.3v clkmode0 clkmode1 clkmode2 ? ? the clkmode2 pin is not available for the c6203b gnz package. notes: a. for a system with only pll x1 (bypass) mode, short the pllf to pllg. b. the 3.3-v supply for pllv must be from the same 3.3-v power plane supplying the i/o voltage, dv dd . figure 6. external pll circuitry for x1 (bypass) pll mode only table 16. tms320c6203b gls and c6203b gny packages pll multiply and bypass (x1) options ? gls package ? 18 x 18 mm bga gny package ? 18 x 18 mm bga bit clkmode2 clkmode1 clkmode0 devices and pll clock options bit (pin no.) clkmode2 (a14) clkmode1 (a9) clkmode0 (b12) gls gny 0 0 0 bypass (x1) bypass (x1) 0 0 1 x4 x4 0 1 0 x8 x8 val e 0 1 1 x10 x10 value 1 0 0 x6 x6 1 0 1 x9 x9 1 1 0 x7 x7 1 1 1 x11 x11 ? f(cpu clock) = f(clkin) x (pll mode) table 17. tms320c6203b gnz package pll multiply and bypass (x1) options ? gnz package 27 x 27 mm bga bit (pin no.) clkmode2 (n/a) ? clkmode1 (c11) clkmode0 (b15) devices and pll clock options 0 0 bypass (x1) value n/a 0 1 x4 value n/a 1 0 x8 1 1 x10 ? f(cpu clock) = f(clkin) x (pll mode) ? the clkmode2 pin is not available (n/a) for the c6203b gnz package.
sprs086k ? january 1999 ? revised april 2003 40 post office box 1443 ? houston, texas 77251 ? 1443 clock pll (continued) table 18. tms320c6203b pll component selection table ? clkmode ? clkin range (mhz) cpu clock frequency range (mhz) clkout2 range (mhz) r1 [ 1%] (revision no.) c1 [ 10%] (revision no.) c2 [ 10%] (revision no. ) typical lock time ( s) x4 32.5 ? 75 x6 21.7 ? 50 x7 18.6 ? 42.9 60 4 ? (1 ) 27 f (1 ) 560 f (1 ) x8 16.3 ? 37.5 130 ? 300 65 ? 150 60.4 ? (1.x) 45 3 ? (2 x 3 x) 27 nf (1.x) 47 nf (2 x 3 x) 560 pf (1.x) 10 p f(2x 3x) 75 x9 14.4 ? 33.3 130 300 65 150 45 . 3 ? (2 .x, 3 .x ) 47 n f (2 .x, 3 .x ) 10 p f (2 .x, 3 .x ) 75 x10 13 ? 30 x11 11.8 ? 27.3 ? under some operating conditions, the maximum pll lock time may vary by as much as 150% from the specified typical value. for ex ample, if the typical lock time is specified as 100 s, the maximum value may be as long as 250 s. ? clkmode x1, x4, x6, x7, x8, x9, x10, and x11 apply to the gls/gny devices. the gnz device is restricted to x1, x4, x8, and x10 multiply factors.
sprs086k ? january 1999 ? revised april 2003 41 post office box 1443 ? houston, texas 77251 ? 1443 power-supply sequencing ti dsps do not require specific power sequencing between the core supply and the i/o supply. however, systems should be designed to ensure that neither supply is powered up for extended periods of time ( > 1 second) if the other supply is below the proper operating voltage. system-level design considerations system-level design considerations, such as bus contention, may require supply sequencing to be implemented. in this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the i/o buffers. this is to ensure that the i/o buffers receive valid inputs from the core before the output buffers are powered up, thus, preventing bus contention with other chips on the board. power-supply design considerations a dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and i/o power up. a schottky diode can also be used to tie the core rail to the i/o rail (see figure 7). dv dd cv dd v ss c6000 dsp schottky diode i/o supply core supply gnd figure 7. schottky diode diagram core and i/o supply voltage regulators should be located close to the dsp (or dsp array) to minimize inductance and resistance in the power delivery path. additionally, when designing for high-performance applications utilizing the c6000 ? platform of dsps, the pc board should include separate power planes for core, i/o, and ground, all bypassed with high-quality low-esl/esr capacitors. on systems using c62x and c67x dsps, the core may consume in excess of 2 a per dsp until the i/o supply powers on. this extra current results from uninitialized logic within the dsp(s). a normal current state returns once the i/o power supply turns on and the cpu sees a clock pulse. decreasing the amount of time between the core supply power-up and the i/o supply power-up reduces the effects of the current draw. if the external supply to the dsp core cannot supply the excess current, the minimum core voltage may not be achieved until after normal current returns. this voltage starvation of the core supply during power up will not affect run-time operation. voltage starvation can affect power supply systems that gate the i/o supply via the core supply, causing the i/o supply to never turn on. during the transition from excess to normal current, a voltage spike may be seen on the core supply. care must be taken when designing overvoltage protection circuitry on the core supply to not restart the power sequence due to this spike. otherwise, the supply may cycle indefinitely.
sprs086k ? january 1999 ? revised april 2003 42 post office box 1443 ? houston, texas 77251 ? 1443 ieee 1149.1 jtag compatibility statement for compatibility with ieee 1149.1 jtag programmers, the trst pin may need to be externally pulled up via a 1-k ? resistor. for these c62x devices, this pin is internally pulled down, holding the jtag port in reset by default. this is typically only a problem in systems where the dsp shares a scan chain with some other device. some jtag programmers for these other devices do not actively drive trst high, leaving the scan chain inoperable while the c62x jtag port is held in reset. ti emulators do drive trst high, so the external pullup resistor is not needed in systems where ti emulators are the only devices that control jtag scan chains on which the dsp(s) reside. if the system has other devices in the same scan chain as the dsp, and the programmer for these devices does not drive trst high, then an external 1-k ? pullup resistor is required. with this external 1-k ? pullup resistor installed, care must be taken to keep the dsp in a usable state under all circumstances. when trst is pulled up, the jtag driver must maintain the tms signal high for 5 tclk cycles, forcing the dsp(s) into the test logic reset (tlr) state. from the tlr state, the dsp ? s data scan path can be put in bypass (scan all 1s into the ir) to scan the other devices. the tlr state also allows normal operation of the dsp. if operation without anything driving the jtag port is desired, the pullup resistor should be jumpered so that it may be engaged for programming the other devices and disconneted for running without a jtag programmer or emulator.
sprs086k ? january 1999 ? revised april 2003 43 post office box 1443 ? houston, texas 77251 ? 1443 absolute maximum ratings over operating case temperature ranges (unless otherwise noted) ? supply voltage range, cv dd (see note 1) ? 0.3 v to 1.8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage range, dv dd (see note 1) ? 0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range ? 0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range ? 0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating case temperature ranges, t c :(default) 0 c to 90 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a version): c6203bgnza-250 ? 40 c to105 c . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . temperature cycle range, (1000-cycle performance) ? 40 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltage values are with respect to v ss . recommended operating conditions min nom max unit cv supply voltage, core 1.43 1.5 1.57 v cv dd supply voltage, core ? 1.65 1.7 1.75 v dv dd supply voltage, i/o 3.14 3.3 3.46 v v ss supply ground 0 0 0 v v ih high-level input voltage 2 v v il low-level input voltage 0.8 v i oh high-level output current ? 8 ma i ol low-level output current 8 ma t c o p erating case tem p erature default 0 90 c t c operating case temperature a version: c6203bgnza-250 ? 40 105 c ? supply voltage, core for the c6203b 1.7 v devices which are identified in the orderable part number with a ? 17 ? following the device number and the package type identifiers. electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage dv dd = min, i oh = max 2.4 v v ol low-level output voltage dv dd = min, i ol = max 0.6 v i i input current v i = v ss to dv dd 10 ua i oz off-state output current v o = dv dd or 0 v 10 ua i dd2v supply current, cpu + cpu memory access ? c6203b, cv dd = nom, cpu clock = 300 mhz 510 ma i dd2v supply current, peripherals ? c6203b, cv dd = nom, cpu clock = 300 mhz 352 ma i dd3v supply current, i/o pins ? c6203b, cv dd = nom, cpu clock = 300 mhz 67 ma c i input capacitance 10 pf c o output capacitance 10 pf tms and tdi are not included due to internal pullups. trst is not included due to internal pulldown. ? measured with average activity (50% high / 50% low power). for more details on cpu, peripheral, and i/o activity, see the tms320c6000 power consumption summary application report (literature number spra486).
sprs086k ? january 1999 ? revised april 2003 44 post office box 1443 ? houston, texas 77251 ? 1443 parameter measurement information tester pin electronics v comm i ol c t i oh output under test 50 ? where: i ol = 2 ma i oh = 2 ma v comm = 1.5 v c t = 15-pf typical load-circuit capacitance figure 8. test load circuit for ac timing measurements signal transition levels all input and output timing parameters are referenced to 1.5 v for both ? 0 ? and ? 1 ? logic levels. v ref = 1.5 v figure 9. input and output voltage reference levels for ac timing measurements all rise and fall transition timing parameters are referenced to v il max and v ih min for input clocks, and v ol max and v oh min for output clocks. v ref = v il max (or v ol max) v ref = v ih min (or v oh min) figure 10. rise and fall transition time voltage reference levels
sprs086k ? january 1999 ? revised april 2003 45 post office box 1443 ? houston, texas 77251 ? 1443 parameter measurement information (continued) timing parameters and board routing analysis the timing parameter values specified in this data sheet do not include delays by board routings. as a good board design practice, such delays must always be taken into account. timing values may be adjusted by increasing/decreasing such delays. ti recommends utilizing the available i/o buffer information specification (ibis) models to analyze the timing characteristics correctly. to properly use ibis models to attain accurate timing analysis for a given system, see the using ibis models for timing analysis application report (literature number spra839). if needed, external logic hardware such as buffers may be used to compensate any timing differences. for inputs, timing is most impacted by the round-trip propagation delay from the dsp to the external device and from the external device to the dsp. this round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see table 19 and figure 11). figure 11 represents a general transfer between the dsp and an external device. the figure also represents board route delays and how they are perceived by the dsp and the external device. table 19. board-level timings examples (see figure 11) no. description 1 clock route delay 2 minimum dsp hold time 3 minimum dsp setup time 4 external device hold time requirement 5 external device setup time requirement 6 control signal route delay 7 external device hold time 8 external device access time 9 dsp hold time requirement 10 dsp setup time requirement 11 data route delay 1 2 3 4 5 6 7 8 10 11 clkout2 (output from dsp) clkout2 (input to external device) control signals ? (output from dsp) control signals (input to external device) data signals ? (output from external device) data signals ? (input to dsp) 9 ? control signals include data for writes. ? data signals are generated during reads from an external device. figure 11. board-level input/output timings
sprs086k ? january 1999 ? revised april 2003 46 post office box 1443 ? houston, texas 77251 ? 1443 input and output clocks timing requirements for clkin (pll used) ?? (see figure 12) no -250 -300 unit no. min max min max unit 1 t c(clkin) cycle time, clkin 4 * m 3.33 * m ns 2 t w(clkinh) pulse duration, clkin high 0.4c 0.4c ns 3 t w(clkinl) pulse duration, clkin low 0.4c 0.4c ns 4 t t(clkin) transition time, clkin 5 5 ns ? the reference points for the rise and fall transitions are measured at v il max and v ih min. ? m = the pll multiplier factor (x4, x6, x7, x8, x9, x10, or x11) for c6203b gls and gny only. m = the pll multiplier factor (x4, x8, or x10) for c6203b gnz only. for more details on both devices, see the clock pll section of this data sheet. c = clkin cycle time in ns. for example, when clkin frequency is 50 mhz, use c = 20 ns. timing requirements for clkin [pll bypassed (x1)] ?? (see figure 12) no -250 -300 unit no. min max min max unit 1 t c(clkin) cycle time, clkin 4 3.33 ns 2 t w(clkinh) pulse duration, clkin high 0.45c 0.45c ns 3 t w(clkinl) pulse duration, clkin low 0.45c 0.45c ns 4 t t(clkin) transition time, clkin 0.6 0.6 ns ? the reference points for the rise and fall transitions are measured at v il max and v ih min. ? c = clkin cycle time in ns. for example, when clkin frequency is 50 mhz, use c = 20 ns. the maximum clkin cycle time in pll byp ass mode (x1) is 200 mhz. clkin 1 2 3 4 4 figure 12. clkin timings
sprs086k ? january 1999 ? revised april 2003 47 post office box 1443 ? houston, texas 77251 ? 1443 input and output clocks (continued) timing requirements for xclkin ? (see figure 13) no. -250 -300 unit no . min max unit 1 t c(xclkin) cycle time, xclkin 4p ns 2 t w(xclkinh) pulse duration, xclkin high 1.8p ns 3 t w(xclkinl) pulse duration, xclkin low 1.8p ns ? p = 1/cpu clock frequency in nanoseconds (ns). xclkin 1 2 3 figure 13. xclkin timings switching characteristics over recommended operating conditions for clkout2 ? (see figure 14) no. parameter -250 -300 unit no . parameter min max unit 1 t c(cko2) cycle time, clkout2 2p ? 0.7 2p + 0.7 ns 2 t w(cko2h) pulse duration, clkout2 high p ? 0.7 p + 0.7 ns 3 t w(cko2l) pulse duration, clkout2 low p ? 0.7 p + 0.7 ns ? p = 1/cpu clock frequency in ns. the reference points for the rise and fall transitions are measured at v ol max and v oh min. clkout2 1 3 2 figure 14. clkout2 timings
sprs086k ? january 1999 ? revised april 2003 48 post office box 1443 ? houston, texas 77251 ? 1443 input and output clocks (continued) switching characteristics over recommended operating conditions for xfclk ?? (see figure 15) no. parameter -250 -300 unit no . parameter min max unit 1 t c(xfck) cycle time, xfclk d * p ? 0.7 d * p + 0.7 ns 2 t w(xfckh) pulse duration, xfclk high (d/2) * p ? 0.7 (d/2) * p + 0.7 ns 3 t w(xfckl) pulse duration, xfclk low (d/2) * p ? 0.7 (d/2) * p + 0.7 ns ? p = 1/cpu clock frequency in ns. ? d = 8, 6, 4, or 2; fifo clock divide ratio, user-programmable xfclk 1 2 3 figure 15. xfclk timings
sprs086k ? january 1999 ? revised april 2003 49 post office box 1443 ? houston, texas 77251 ? 1443 asynchronous memory timing timing requirements for asynchronous memory cycles ??? (see figure 16 ? figure 19) no. -250 -300 unit no . min max unit 3 t su(edv-areh) setup time, edx valid before are high 1 ns 4 t h(areh-edv) hold time, edx valid after are high 4.9 ns 6 t su(ardyh-arel) setup time, ardy high before are low ? [(rst ? 3) * p ? 6] ns 7 t h(arel-ardyh) hold time, ardy high after are low (rst ? 3) * p + 2 ns 9 t su(ardyl-arel) setup time, ardy low before are low ? [(rst ? 3) * p ? 6] ns 10 t h(arel-ardyl) hold time, ardy low after are low (rst ? 3) * p + 2 ns 11 t w(ardyh) pulse width, ardy high 2p ns 15 t su(ardyh-awel) setup time, ardy high before awe low ? [(wst ? 3) * p ? 6] ns 16 t h(awel-ardyh) hold time, ardy high after awe low (wst ? 3) * p + 2 ns 18 t su(ardyl-awel) setup time, ardy low before awe low ? [(wst ? 3) * p ? 6] ns 19 t h(awel-ardyl) hold time, ardy low after awe low (wst ? 3) * p + 2 ns ? to ensure data setup time, simply program the strobe width wide enough. ardy is internally synchronized. if ardy does meet setu p or hold time, it may be recognized in the current cycle or the next cycle. thus, ardy can be an asynchronous input. ? rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold. these parameters are programmed via the emif ce space control registers. p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.33 ns. ? the sum of rs and rst (or ws and wst) must be a minimum of 4 in order to use ardy input to extend strobe width. switching characteristics over recommended operating conditions for asynchronous memory cycles ?? # (see figure 16 ? figure 19) no. parameter -250 -300 unit no . parameter min typ max unit 1 t osu(selv-arel) output setup time, select signals valid to are low rs * p ? 2 ns 2 t oh(areh-seliv) output hold time, are high to select signals invalid rh * p ? 2 ns 5 t w(arel) pulse width, are low rst * p ns 8 t d(ardyh-areh) delay time, ardy high to are high 3p 4p + 5 ns 12 t osu(selv-awel) output setup time, select signals valid to awe low ws * p ? 3 ns 13 t oh(aweh-seliv) output hold time, awe high to select signals invalid wh * p ? 2 ns 14 t w(awel) pulse width, awe low wst * p ns 17 t d(ardyh-aweh) delay time, ardy high to awe high 3p 4p + 5 ns ? rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold. these parameters are programmed via the emif ce space control registers. p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.33 ns. ? the sum of rs and rst (or ws and wst) must be a minimum of 4 in order to use ardy input to extend strobe width. # select signals include: cex , be[3:0] , ea[21:2], aoe; and for writes, include ed[31:0], with the exception that cex can stay active for an additional 7p ns following the end of the cycle.
sprs086k ? january 1999 ? revised april 2003 50 post office box 1443 ? houston, texas 77251 ? 1443 asynchronous memory timing (continued) setup = 2 strobe = 3 hold = 2 5 2 1 4 3 2 1 2 1 7 6 clkout1 cex ? be[3:0] ed[31:0] aoe are awe ardy 2 1 ea[21:2] ? cex stays active for seven minus the value of read hold cycles after the last access (dma transfer or cpu access). for example, if read hold = 1, then cex stays active for six more cycles. this does not affect performance, it merely reflects the emif ? s overhead. figure 16. asynchronous memory read timing (ardy not used) setup = 2 strobe = 3 not ready hold = 2 8 2 1 4 3 2 1 2 1 2 1 11 10 9 clkout1 cex ? be[3:0] ed[31:0] aoe are awe ardy ea[21:2] ? cex stays active for seven minus the value of read hold cycles after the last access (dma transfer or cpu access). for example, if read hold = 1, then cex stays active for six more cycles. this does not affect performance, it merely reflects the emif ? s overhead. figure 17. asynchronous memory read timing (ardy used)
sprs086k ? january 1999 ? revised april 2003 51 post office box 1443 ? houston, texas 77251 ? 1443 asynchronous memory timing (continued) setup = 2 strobe = 3 hold = 2 14 13 12 13 12 13 12 13 12 16 15 cex ? be[3:0] ed[31:0] aoe are awe ardy ea[21:2] clkout1 ? if no write accesses are scheduled for the next cycle and write hold is set to 1 or greater, then cex stays active for three cycles after the value of the programmed hold period. if write hold is set to 0, then cex stays active for four more cycles. this does not affect performance, it merely reflects the emif ? s overhead. figure 18. asynchronous memory write timing (ardy not used) setup = 2 strobe = 3 not ready hold = 2 17 13 12 13 12 13 12 13 12 11 19 18 cex ? be[3:0] ea[21:2] ed[31:0] aoe are awe ardy clkout1 ? if no write accesses are scheduled for the next cycle and write hold is set to 1 or greater, then cex stays active for three cycles after the value of the programmed hold period. if write hold is set to 0, then cex stays active for four more cycles. this does not affect performance, it merely reflects the emif ? s overhead. figure 19. asynchronous memory write timing (ardy used)
sprs086k ? january 1999 ? revised april 2003 52 post office box 1443 ? houston, texas 77251 ? 1443 synchronous-burst memory timing timing requirements for synchronous-burst sram cycles for c6203b rev. 2 (see figure 20) rev. 2 no. -250 -300 unit no. min max min max unit 7 t su(edv-cko2h) setup time, read edx valid before clkout2 high 2.0 1.7 ns 8 t h(cko2h-edv) hold time, read edx valid after clkout2 high 2.0 1.5 ns switching characteristics over recommended operating conditions for synchronous-burst sram cycles for c6203b rev. 2 ?? (see figure 20 and figure 21) rev. 2 no. parameter -250 -300 unit no. parameter min max min max unit 1 t osu(cev-cko2h) output setup time, cex valid before clkout2 high p ? 0.8 p + 0.1 ns 2 t oh(cko2h-cev) output hold time, cex valid after clkout2 high p ? 3 p ? 2.3 ns 3 t osu(bev-cko2h) output setup time, bex valid before clkout2 high p ? 0.8 p + 0.1 ns 4 t oh(cko2h-beiv) output hold time, bex invalid after clkout2 high p ? 3 p ? 2.3 ns 5 t osu(eav-cko2h) output setup time, eax valid before clkout2 high p ? 0.8 p + 0.1 ns 6 t oh(cko2h-eaiv) output hold time, eax invalid after clkout2 high p ? 3 p ? 2.3 ns 9 t osu(adsv-cko2h) output setup time, sdcas /ssads valid before clkout2 high p ? 0.8 p + 0.1 ns 10 t oh(cko2h-adsv) output hold time, sdcas /ssads valid after clkout2 high p ? 3 p ? 2.3 ns 11 t osu(oev-cko2h) output setup time, sdras /ssoe valid before clkout2 high p ? 0.8 p + 0.1 ns 12 t oh(cko2h-oev) output hold time, sdras /ssoe valid after clkout2 high p ? 3 p ? 2.3 ns 13 t osu(edv-cko2h) output setup time, edx valid before clkout2 high p ? 1.2 p + 0.1 ns 14 t oh(cko2h-ediv) output hold time, edx invalid after clkout2 high p ? 3 p ? 2.3 ns 15 t osu(wev-cko2h) output setup time, sdwe /sswe valid before clkout2 high p ? 0.8 p + 0.1 ns 16 t oh(cko2h-wev) output hold time, sdwe /sswe valid after clkout2 high p ? 3 p ? 2.3 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.33 ns. ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as ssads , ssoe , and sswe , respectively, during sbsram accesses. for the first write in a series of one or more consecutive adjacent writes, the write data is generated one clkout2 cycle early to accommodate the ed enable time.
sprs086k ? january 1999 ? revised april 2003 53 post office box 1443 ? houston, texas 77251 ? 1443 synchronous-burst memory timing (continued) timing requirements for synchronous-burst sram cycles for c6203b rev. 3 (see figure 20) rev. 3 no. c6203bgny173-250 c6203bgnz173-250 c6203bgnza-250 c6203bgny173-300 c6203bgny300-300 c6203bgnz173-300 c6203bgnz300-300 c6203bgny3e-300 unit min max min max min max 7 t su(edv-cko2h) setup time, read edx valid before clkout2 high 2.9 1.6 1.6 ns 8 t h(cko2h-edv) hold time, read edx valid after clkout2 high 2.1 2.3 2.3 ns switching characteristics over recommended operating conditions for synchronous-burst sram cycles for c6203b rev. 3 ?? (see figure 20 and figure 21) rev. 3 no. parameter c6203bgny173-250 c6203bgnz173-250 c6203bgnza-250 c6203bgny173-300 c6203bgny300-300 c6203bgnz173-300 c6203bgnz300-300 c6203bgny3e-300 unit min max min max min max 1 t osu(cev-cko2h) output setup time, cex valid before clkout2 high p ? 1.7 p ? 1 p ? 1.5 ns 2 t oh(cko2h-cev) output hold time, cex valid after clkout2 high p ? 3.4 p ? 2.7 p ? 2.7 ns 3 t osu(bev-cko2h) output setup time, bex valid before clkout2 high p ? 1.7 p ? 1 p ? 1.5 ns 4 t oh(cko2h-beiv) output hold time, bex invalid after clkout2 high p ? 3.4 p ? 2.7 p ? 2.7 ns 5 t osu(eav-cko2h) output setup time, eax valid before clkout2 high p ? 1.7 p ? 1 p ? 1.5 ns 6 t oh(cko2h-eaiv) output hold time, eax invalid after clkout2 high p ? 3.4 p ? 2.7 p ? 2.7 ns 9 t osu(adsv-cko2h) output setup time, sdcas /ssads valid before clkout2 high p ? 1.7 p ? 1 p ? 1.5 ns 10 t oh(cko2h-adsv) output hold time, sdcas /ssads valid after clkout2 high p ? 3.4 p ? 2.7 p ? 2.7 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.33 ns. ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as ssads , ssoe , and sswe , respectively, during sbsram accesses. for the first write in a series of one or more consecutive adjacent writes, the write data is generated one clkout2 cycle early to accommodate the ed enable time.
sprs086k ? january 1999 ? revised april 2003 54 post office box 1443 ? houston, texas 77251 ? 1443 synchronous-burst memory timing (continued) switching characteristics over recommended operating conditions for synchronous-burst sram cycles for c6203b rev. 3 ?? (see figure 20 and figure 21) (continued) rev. 3 no. parameter c6203bgny173-250 c6203bgnz173-250 c6203bgnza-250 c6203bgny173-300 c6203bgny300-300 c6203bgnz173-300 c6203bgnz300-300 c6203bgny3e-300 unit min max min max min max 11 t osu(oev-cko2h) output setup time, sdras /ssoe valid before clkout2 high p ? 1.7 p ? 1 p ? 1.5 ns 12 t oh(cko2h-oev) output hold time, sdras /ssoe valid after clkout2 high p ? 3.4 p ? 2.7 p ? 2.7 ns 13 t osu(edv-cko2h) output setup time, edx valid before clkout2 high p ? 2.3 p ? 1.6 p ? 1.6 ns 14 t oh(cko2h-ediv) output hold time, edx invalid after clkout2 high p ? 3.2 p ? 2.5 p ? 2.5 ns 15 t osu(wev-cko2h) output setup time, sdwe /sswe valid before clkout2 high p ? 1.7 p ? 1 p ? 1.5 ns 16 t oh(cko2h-wev) output hold time, sdwe /sswe valid after clkout2 high p ? 3.4 p ? 2.7 p ? 2.7 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.33 ns. ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as ssads , ssoe , and sswe , respectively, during sbsram accesses. for the first write in a series of one or more consecutive adjacent writes, the write data is generated one clkout2 cycle early to accommodate the ed enable time.
sprs086k ? january 1999 ? revised april 2003 55 post office box 1443 ? houston, texas 77251 ? 1443 synchronous-burst memory timing (continued) clkout2 cex be[3:0] ea[21:2] ed[31:0] sdcas /ssads ? sdras /ssoe ? sdwe /sswe ? be1 be2 be3 be4 a1 a2 a3 a4 q1 q2 q3 q4 12 11 10 9 6 5 4 3 2 1 8 7 ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as ssads , ssoe , and sswe , respectively, during sbsram accesses. figure 20. sbsram read timing clkout2 cex be[3:0] ea[21:2] ed[31:0] sdras /ssoe ? sdwe /sswe ? sdcas /ssads ? be1 be2 be3 be4 a1 a2 a3 a4 q1 q2 q3 q4 16 15 10 9 14 13 6 5 4 3 2 1 ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as ssads , ssoe , and sswe , respectively, during sbsram accesses. figure 21. sbsram write timing
sprs086k ? january 1999 ? revised april 2003 56 post office box 1443 ? houston, texas 77251 ? 1443 synchronous dram timing timing requirements for synchronous dram cycles for c6203b rev. 2 (see figure 22) rev. 2 no. -250 -300 unit no. min max min max unit 7 t su(edv-cko2h) setup time, read edx valid before clkout2 high 1.2 0.5 ns 8 t h(cko2h-edv) hold time, read edx valid after clkout2 high 2.7 2 ns switching characteristics over recommended operating conditions for synchronous dram cycles for c6203b rev. 2 ?? (see figure 22 ? figure 27) rev. 2 no. parameter -250 -300 unit no. parameter min max min max unit 1 t osu(cev-cko2h) output setup time, cex valid before clkout2 high p ? 0.9 p + 0.6 ns 2 t oh(cko2h-cev) output hold time, cex valid after clkout2 high p ? 2.9 p ? 1.8 ns 3 t osu(bev-cko2h) output setup time, bex valid before clkout2 high p ? 0.9 p + 0.6 ns 4 t oh(cko2h-beiv) output hold time, bex invalid after clkout2 high p ? 2.9 p ? 1.8 ns 5 t osu(eav-cko2h) output setup time, eax valid before clkout2 high p ? 0.9 p + 0.6 ns 6 t oh(cko2h-eaiv) output hold time, eax invalid after clkout2 high p ? 2.9 p ? 1.8 ns 9 t osu(casv-cko2h) output setup time, sdcas /ssads valid before clkout2 high p ? 0.9 p + 0.6 ns 10 t oh(cko2h-casv) output hold time, sdcas /ssads valid after clkout2 high p ? 2.9 p ? 1.8 ns 11 t osu(edv-cko2h) output setup time, edx valid before clkout2 high p ? 1.5 p + 0.6 ns 12 t oh(cko2h-ediv) output hold time, edx invalid after clkout2 high p ? 2.8 p ? 1.8 ns 13 t osu(wev-cko2h) output setup time, sdwe /sswe valid before clkout2 high p ? 0.9 p + 0.6 ns 14 t oh(cko2h-wev) output hold time, sdwe /sswe valid after clkout2 high p ? 2.9 p ? 1.8 ns 15 t osu(sda10v-cko2h) output setup time, sda10 valid before clkout2 high p ? 0.9 p + 0.6 ns 16 t oh(cko2h-sda10iv) output hold time, sda10 invalid after clkout2 high p ? 2.9 p ? 1.8 ns 17 t osu(rasv-cko2h) output setup time, sdras /ssoe valid before clkout2 high p ? 0.9 p + 0.6 ns 18 t oh(cko2h-rasv) output hold time, sdras /ssoe valid after clkout2 high p ? 2.9 p ? 1.8 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.33 ns. ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as sdcas , sdras , and sdwe , respectively, during sdram accesses. for the first write in a series of one or more consecutive adjacent writes, the write data is generated one clkout2 cycle early to accommodate the ed enable time.
sprs086k ? january 1999 ? revised april 2003 57 post office box 1443 ? houston, texas 77251 ? 1443 synchronous dram timing (continued) timing requirements for synchronous dram cycles for c6203b rev. 3 (see figure 22) rev. 3 no. c6203bgny173-250 c6203bgnz173-250 c6203bgnza-250 c6203bgny173-300 c6203bgny300-300 c6203bgnz173-300 c6203bgnz300-300 c6203bgny3e-300 unit min max min max min max 7 t su(edv-cko2h) setup time, read edx valid before clkout2 high 1.3 0 0 ns 8 t h(cko2h-edv) hold time, read edx valid after clkout2 high 2.3 2.3 2.7 ns
sprs086k ? january 1999 ? revised april 2003 58 post office box 1443 ? houston, texas 77251 ? 1443 synchronous dram timing (continued) switching characteristics over recommended operating conditions for synchronous dram cycles for c6203b rev. 3 ?? (see figure 22 ? figure 27) rev. 3 no. parameter c6203bgny173-250 c6203bgnz173-250 c6203bgnza-250 c6203bgny173-300 c6203bgny300-300 c6203bgnz173-300 c6203bgnz300-300 c6203bgny3e-300 unit min max min max min max 1 t osu(cev-cko2h) output setup time, cex valid before clkout2 high p ? 1.7 p ? 1 p ? 1.5 ns 2 t oh(cko2h-cev) output hold time, cex valid after clkout2 high p ? 3 p ? 2.3 p ? 2.3 ns 3 t osu(bev-cko2h) output setup time, bex valid before clkout2 high p ? 1.7 p ? 1 p ? 1.5 ns 4 t oh(cko2h-beiv) output hold time, bex invalid after clkout2 high p ? 3 p ? 2.3 p ? 2.3 ns 5 t osu(eav-cko2h) output setup time, eax valid before clkout2 high p ? 1.7 p ? 1 p ? 1.5 ns 6 t oh(cko2h-eaiv) output hold time, eax invalid after clkout2 high p ? 3 p ? 2.3 p ? 2.3 ns 9 t osu(casv-cko2h) output setup time, sdcas /ssads valid before clkout2 high p ? 1.7 p ? 1 p ? 1.5 ns 10 t oh(cko2h-casv) output hold time, sdcas /ssads valid after clkout2 high p ? 3 p ? 2.3 p ? 2.3 ns 11 t osu(edv-cko2h) output setup time, edx valid before clkout2 high p ? 2.3 p ? 1.6 p ? 1.5 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.33 ns. ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as sdcas , sdras , and sdwe , respectively, during sdram accesses. for the first write in a series of one or more consecutive adjacent writes, the write data is generated one clkout2 cycle early to accommodate the ed enable time.
sprs086k ? january 1999 ? revised april 2003 59 post office box 1443 ? houston, texas 77251 ? 1443 synchronous dram timing (continued) switching characteristics over recommended operating conditions for synchronous dram cycles for c6203b rev. 3 ?? (see figure 22 ? figure 27) (continued) rev. 3 no. parameter c6203bgny173-250 c6203bgnz173-250 c6203bgnza-250 c6203bgny173-300 c6203bgny300-300 c6203bgnz173-300 c6203bgnz300-300 c6203bgny3e-300 unit min max min max min max 12 t oh(cko2h-ediv) output hold time, edx invalid after clkout2 high p ? 2.7 p ? 2 p ? 2 ns 13 t osu(wev-cko2h) output setup time, sdwe /sswe valid before clkout2 high p ? 1.7 p ? 1 p ? 1.5 ns 14 t oh(cko2h-wev) output hold time, sdwe /sswe valid after clkout2 high p ? 3 p ? 2.3 p ? 2.3 ns 15 t osu(sda10v-cko2h) output setup time, sda10 valid before clkout2 high p ? 1.7 p ? 1 p ? 1.5 ns 16 t oh(cko2h-sda10iv) output hold time, sda10 invalid after clkout2 high p ? 3 p ? 2.3 p ? 2.3 ns 17 t osu(rasv-cko2h) output setup time, sdras /ssoe valid before clkout2 high p ? 1.7 p ? 1 p ? 1.5 ns 18 t oh(cko2h-rasv) output hold time, sdras /ssoe valid after clkout2 high p ? 3 p ? 2.3 p ? 2.3 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.33 ns. ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as sdcas , sdras , and sdwe , respectively, during sdram accesses. for the first write in a series of one or more consecutive adjacent writes, the write data is generated one clkout2 cycle early to accommodate the ed enable time.
sprs086k ? january 1999 ? revised april 2003 60 post office box 1443 ? houston, texas 77251 ? 1443 synchronous dram timing (continued) clkout2 cex be[3:0] ea[15:2] ed[31:0] sda10 sdras /ssoe ? sdcas /ssads ? sdwe /sswe ? be1 be2 be3 ca1 ca2 ca3 d1 d2 d3 10 9 16 15 6 5 4 3 2 1 8 7 read read read ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as sdcas , sdras , and sdwe , respectively, during sdram accesses. figure 22. three sdram read commands clkout2 cex be[3:0] ea[15:2] ed[31:0] sda10 sdras /ssoe ? sdcas /ssads ? sdwe /sswe ? be1 be2 be3 ca1 ca2 ca3 d1 d2 d3 14 13 10 9 16 15 12 11 6 5 4 3 2 1 write write write ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as sdcas , sdras , and sdwe , respectively, during sdram accesses. figure 23. three sdram wrt commands
sprs086k ? january 1999 ? revised april 2003 61 post office box 1443 ? houston, texas 77251 ? 1443 synchronous dram timing (continued) clkout2 cex be[3:0] ea[15:2] ed[31:0] sda10 sdras /ssoe ? sdcas /ssads ? sdwe /sswe ? bank activate/row address row address 18 17 15 5 2 1 actv ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as sdcas , sdras , and sdwe , respectively, during sdram accesses. figure 24. sdram actv command clkout2 cex be[3:0] ea[15:2] ed[31:0] sda10 sdras /ssoe ? sdcas /ssads ? sdwe /sswe ? 14 18 16 2 15 1 17 13 dcab ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as sdcas , sdras , and sdwe , respectively, during sdram accesses. figure 25. sdram dcab command
sprs086k ? january 1999 ? revised april 2003 62 post office box 1443 ? houston, texas 77251 ? 1443 synchronous dram timing (continued) clkout2 cex be[3:0] ea[15:2] ed[31:0] sda10 sdras /ssoe ? sdcas /ssads ? sdwe /sswe ? 10 9 18 17 2 1 refr ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as sdcas , sdras , and sdwe , respectively, during sdram accesses. figure 26. sdram refr command clkout2 cex be[3:0] ea[15:2] ed[31:0] sda10 sdras /ssoe ? sdcas /ssads ? sdwe /sswe ? mrs value 14 10 18 6 2 1 5 17 9 13 mrs ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as sdcas , sdras , and sdwe , respectively, during sdram accesses. figure 27. sdram mrs command
sprs086k ? january 1999 ? revised april 2003 63 post office box 1443 ? houston, texas 77251 ? 1443 hold /holda timing timing requirements for the hold /holda cycles ? (see figure 28) no. -250 -300 unit no . min max unit 3 t oh(holdal-holdl) output hold time, hold low after holda low p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.33 ns. switching characteristics over recommended operating conditions for the hold /holda cycles ?? (see figure 28) no. parameter -250 -300 unit no . parameter min max unit 1 t d(holdl-emhz) delay time, hold low to emif bus high impedance 3p ns 2 t d(emhz-holdal) delay time, emif bus high impedance to holda low 0 2p ns 4 t d(holdh-emlz) delay time, hold high to emif bus low impedance 3p 7p ns 5 t d(emlz-holdah) delay time, emif bus low impedance to holda high 0 2p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.33 ns. ? emif bus consists of ce[3:0] , be[3:0] , ed[31:0], ea[21:2], are , aoe , awe , sdcas /ssads , sdras /ssoe , sdwe /sswe , and sda10. all pending emif transactions are allowed to complete before holda is asserted. the worst case for this is an asynchronous read or write with external ardy used or a minimum of eight consecutive sdram reads or writes when rbtr8 = 1. if no bus transactions are occurring , then the minimum delay time can be achieved. also, bus hold can be indefinitely delayed by setting nohold = 1. hold holda emif bus ? dsp owns bus external requestor owns bus dsp owns bus c6203b c6203b 1 3 25 4 ? emif bus consists of ce[3:0] , be[3:0] , ed[31:0], ea[21:2], are , aoe , awe , sdcas /ssads , sdras /ssoe , sdwe /sswe , and sda10. figure 28. hold /holda timing
sprs086k ? january 1999 ? revised april 2003 64 post office box 1443 ? houston, texas 77251 ? 1443 reset timing timing requirements for reset ? (see figure 29) no. -250 -300 unit no . min max unit 1 t width of the reset pulse (pll stable) ? 10p ns 1 t w(rst) width of the reset pulse (pll needs to sync up) 250 s 10 t su(xd) setup time, xd configuration bits valid before reset high ? 5p ns 11 t h(xd) hold time, xd configuration bits valid after reset high ? 5p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.33 ns. ? this parameter applies to clkmode x1 when clkin is stable, and applies to clkmode x4, x6, x7, x8, x9, x10, and x11 when clkin and pl l are stable for c6203b gls and gny devices. and applies to clkmode x4, x6, x8, and x10 when clkin and pll are stable for c6203b gnz devices. this parameter applies to clkmode x4, x6, x7, x8, x9, x10, and x11 only (it does not apply to clkmode x1) for c6203b gls and gny dev ices. this parameter applies to clkmode x4, x6, x8, and x10 only (it does not apply to clkmode x1) for c6203b gnz devices. the reset signal is not connected internally to the clock pll circuit. the pll, however, may need up to 250 s to stabilize following device power up or after pll configuration has been changed. during that time, reset must be asserted to ensure proper device operation. see the clock pll section for pll lock times. ? xd[31:0] are the boot configuration pins during device reset. switching characteristics over recommended operating conditions during reset ? # (see figure 29) no. parameter -250 -300 unit no . parameter min max unit 2 t d(rstl-cko2iv) delay time, reset low to clkout2 invalid p ns 3 t d(rsth-cko2v) delay time, reset high to clkout2 valid 4p ns 4 t d(rstl-highiv) delay time, reset low to high group invalid p ns 5 t d(rsth-highv) delay time, reset high to high group valid 4p ns 6 t d(rstl-lowiv) delay time, reset low to low group invalid p ns 7 t d(rsth-lowv) delay time, reset high to low group valid 4p ns 8 t d(rstl-zhz) delay time, reset low to z group high impedance p ns 9 t d(rsth-zv) delay time, reset high to z group valid 4p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.33 ns. # high group consists of: xfclk, holda low group consists of: iack, inum[3:0], dmac[3:0], pd, tout0, and tout1 z group consists of: ea[21:2], ed[31:0], ce[3:0] , be[3:0] , are , awe , aoe , sdcas /ssads , sdras /ssoe , sdwe /sswe , sda10, clkx0, clkx1, clkx2, fsx0, fsx1, fsx2, dx0, dx1, dx2, clkr0, clkr1, clkr2, fsr0, fsr1, fsr2, xce[3:0] , xbe[3:0] /xa[5:2], xoe , xre , xwe /xwait , xas , xw/r, xrdy, xblast, xhold, and xholda
sprs086k ? january 1999 ? revised april 2003 65 post office box 1443 ? houston, texas 77251 ? 1443 reset timing (continued) clkout1 9 8 7 6 5 4 3 2 11 10 reset clkout2 high group ? low group ? z group ? xd[31:0] ? 1 boot configuration ? high group consists of: xfclk, holda low group consists of: iack, inum[3:0], dmac[3:0], pd, tout0, and tout1. z group consists of: ea[21:2], ed[31:0], ce[3:0] , be[3:0] , are , awe , aoe , sdcas /ssads , sdras /ssoe , sdwe /sswe , sda10, clkx0, clkx1, clkx2, fsx0, fsx1, fsx2, dx0, dx1, dx2, clkr0, clkr1, clkr2, fsr0, fsr1, fsr2, xce[3:0] , xbe[3:0] /xa[5:2], xoe , xre , xwe /xwait , xas , xw/r, xrdy, xblast, xhold, and xholda. ? xd[31:0] are the boot configuration pins during device reset. figure 29. reset timing
sprs086k ? january 1999 ? revised april 2003 66 post office box 1443 ? houston, texas 77251 ? 1443 external interrupt timing timing requirements for interrupt response cycles ? (see figure 30) no. -250 -300 unit no . min max unit 2 t w(ilow) width of the interrupt pulse low 2p ns 3 t w(ihigh) width of the interrupt pulse high 2p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.33 ns. switching characteristics over recommended operating conditions during interrupt response cycles ?? (see figure 30) no. parameter -250 -300 unit no . parameter min max unit 1 t r(einth ? iackh) response time, ext_intx high to iack high 9p ns 4 t d(cko2l-iackv) delay time, clkout2 low to iack valid ? 1.5 10 ns 5 t d(cko2l-inumv) delay time, clkout2 low to inumx valid ? 2.0 10 ns 6 t d(cko2l-inumiv) delay time, clkout2 low to inumx invalid ? 2.0 10 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.33 ns. ? when clkout2 is in half (1/2) mode (see clkout2 in signal descriptions table), timings are based on falling edges . 1 2 3 5 4 4 6 clkout2 (1/2) ext_intx, nmi intr flag iack inumx interrupt number figure 30. interrupt timing
sprs086k ? january 1999 ? revised april 2003 67 post office box 1443 ? houston, texas 77251 ? 1443 expansion bus synchronous fifo timing timing requirements for synchronous fifo interface (see figure 31, figure 32, and figure 33) no. -250 -300 unit no . min max unit 5 t su(xdv-xfckh) setup time, read xdx valid before xfclk high 3 ns 6 t h(xfckh-xdv) hold time, read xdx valid after xfclk high 2.5 ns switching characteristics over recommended operating conditions for synchronous fifo interface (see figure 31, figure 32, and figure 33) no. parameter -250 -300 unit no . parameter min max unit 1 t d(xfckh-xcev) delay time, xfclk high to xcex valid 1.5 5.5 ns 2 t d(xfckh-xav) delay time, xfclk high to xbe[3:0] /xa[5:2] valid ? 1.5 5.5 ns 3 t d(xfckh-xoev) delay time, xfclk high to xoe valid 1.5 5.5 ns 4 t d(xfckh-xrev) delay time, xfclk high to xre valid 1.5 5.5 ns 7 t d(xfckh-xwev) delay time, xfclk high to xwe /xwait ? valid 1.5 5.5 ns 8 t d(xfckh-xdv) delay time, xfclk high to xdx valid 6 ns 9 t d(xfckh-xdiv) delay time, xfclk high to xdx invalid 1.5 ns ? xbe[3:0] /xa[5:2] operate as address signals xa[5:2] during synchronous fifo accesses. ? xwe /xwait operates as the write-enable signal xwe during synchronous fifo accesses. xa1 xa2 xa3 xa4 d1 d2 d3 d4 6 5 4 4 3 3 2 2 1 1 xfclk xce3 ? xbe[3:0] /xa[5:2] ? xoe xre xwe /xwait xd[31:0] ? fifo read (glueless) mode only available in xce3 . ? xbe[3:0] /xa[5:2] operate as address signals xa[5:2] during synchronous fifo accesses. xwe /xwait operates as the write-enable signal xwe during synchronous fifo accesses. figure 31. fifo read timing (glueless read mode)
sprs086k ? january 1999 ? revised april 2003 68 post office box 1443 ? houston, texas 77251 ? 1443 expansion bus synchronous fifo timing (continued) xa1 xa2 xa3 xa4 d1 d2 d3 d4 6 5 4 4 3 3 2 2 1 1 xfclk xcex xbe[3:0] /xa[5:2] ? xoe xre xwe /xwait ? xd[31:0] ? xbe[3:0] /xa[5:2] operate as address signals xa[5:2] during synchronous fifo accesses. ? xwe /xwait operates as the write-enable signal xwe during synchronous fifo accesses. figure 32. fifo read timing xa1 xa2 xa3 xa4 d1 d2 d3 d4 9 8 7 7 2 2 1 1 xfclk xcex xbe[3:0] /xa[5:2] ? xoe xre xd[31:0] xwe /xwait ? ? xbe[3:0] /xa[5:2] operate as address signals xa[5:2] during synchronous fifo accesses. ? xwe /xwait operates as the write-enable signal xwe during synchronous fifo accesses. figure 33. fifo write timing
sprs086k ? january 1999 ? revised april 2003 69 post office box 1443 ? houston, texas 77251 ? 1443 expansion bus asynchronous peripheral timing timing requirements for asynchronous peripheral cycles ??? (see figure 34 ? figure 37) no. -250 -300 unit no . min max unit 3 t su(xdv-xreh) setup time, xdx valid before xre high 4.5 ns 4 t h(xreh-xdv) hold time, xdx valid after xre high 2.5 ns 6 t su(xrdyh-xrel) setup time, xrdy high before xre low ? [(rst ? 3) * p ? 6] ns 7 t h(xrel-xrdyh) hold time, xrdy high after xre low (rst ? 3) * p + 2 ns 9 t su(xrdyl-xrel) setup time, xrdy low before xre low ? [(rst ? 3) * p ? 6] ns 10 t h(xrel-xrdyl) hold time, xrdy low after xre low (rst ? 3) * p + 2 ns 11 t w(xrdyh) pulse width, xrdy high 2p ns 15 t su(xrdyh-xwel) setup time, xrdy high before xwe low ? [(wst ? 3) * p ? 6] ns 16 t h(xwel-xrdyh) hold time, xrdy high after xwe low (wst ? 3) * p + 2 ns 18 t su(xrdyl-xwel) setup time, xrdy low before xwe low ? [(wst ? 3) * p ? 6] ns 19 t h(xwel-xrdyl) hold time, xrdy low after xwe low (wst ? 3) * p + 2 ns ? to ensure data setup time, simply program the strobe width wide enough. xrdy is internally synchronized. if xrdy does meet setu p or hold time, it may be recognized in the current cycle or the next cycle. thus, xrdy can be an asynchronous input. ? rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold. these parameters are programmed via the xbus xce space control registers. p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. ? the sum of rs and rst (or ws and wst) must be a minimum of 4 in order to use xrdy input to extend strobe width. switching characteristics over recommended operating conditions for asynchronous peripheral cycles ?? # (see figure 34 ? figure 37) no. parameter -250 -300 unit no . parameter min typ max unit 1 t osu(selv-xrel) output setup time, select signals valid to xre low rs * p ? 2 ns 2 t oh(xreh-seliv) output hold time, xre low to select signals invalid rh * p ? 2 ns 5 t w(xrel) pulse width, xre low rst * p ns 8 t d(xrdyh-xreh) delay time, xrdy high to xre high 3p 4p + 5 ns 12 t osu(selv-xwel) output setup time, select signals valid to xwe low ws * p ? 3 ns 13 t oh(xweh-seliv) output hold time, xwe low to select signals invalid wh * p ? 2 ns 14 t w(xwel) pulse width, xwe low wst * p ns 17 t d(xrdyh-xweh) delay time, xrdy high to xwe high 3p 4p + 5 ns ? rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold. these parameters are programmed via the xbus xce space control registers. p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. ? the sum of rs and rst (or ws and wst) must be a minimum of 4 in order to use xrdy input to extend strobe width. # select signals include: xcex , xbe[3:0]/ xa[5:2], xoe ; and for writes, include xd[31:0], with the exception that xcex can stay active for an additional 7p ns following the end of the cycle.
sprs086k ? january 1999 ? revised april 2003 70 post office box 1443 ? houston, texas 77251 ? 1443 expansion bus asynchronous peripheral timing (continued) setup = 2 strobe = 3 hold = 2 5 2 1 4 3 2 1 2 1 7 6 clkout1 xcex xbe[3:0] / xa[5:2] ? xd[31:0] xoe xre xwe /xwait ? xrdy ? xbe[3:0] /xa[5:2] operate as address signals xa[5:2] during expansion bus asynchronous peripheral accesses. ? xwe /xwait operates as the write-enable signal xwe during expansion bus asynchronous peripheral accesses. xrdy operates as active-high ready input during expansion bus asynchronous peripheral accesses. figure 34. expansion bus asynchronous peripheral read timing (xrdy not used) setup = 2 strobe = 3 not ready hold = 2 8 2 1 4 3 2 1 2 1 11 10 9 clkout1 xcex xd[31:0] xoe xre xbe[3:0] / xa[5:2] ? xwe /xwait ? xrdy ? xbe[3:0] /xa[5:2] operate as address signals xa[5:2] during expansion bus asynchronous peripheral accesses. ? xwe /xwait operates as the write-enable signal xwe during expansion bus asynchronous peripheral accesses. xrdy operates as active-high ready input during expansion bus asynchronous peripheral accesses. figure 35. expansion bus asynchronous peripheral read timing (xrdy used)
sprs086k ? january 1999 ? revised april 2003 71 post office box 1443 ? houston, texas 77251 ? 1443 expansion bus asynchronous peripheral timing (continued) setup = 2 strobe = 3 hold = 2 14 13 12 13 12 13 12 16 15 clkout1 xcex xd[31:0] xre xbe[3:0] / xa[5:2] ? xwe /xwait ? xrdy xoe ? xbe[3:0] /xa[5:2] operate as address signals xa[5:2] during expansion bus asynchronous peripheral accesses. ? xwe /xwait operates as the write-enable signal xwe during expansion bus asynchronous peripheral accesses. xrdy operates as active-high ready input during expansion bus asynchronous peripheral accesses. figure 36. expansion bus asynchronous peripheral write timing (xrdy not used) xoe setup = 2 strobe = 3 not ready hold = 2 17 13 12 13 12 13 12 11 19 18 clkout1 xcex xd[31:0] xre xbe[3:0] / xa[5:2] ? xwe /xwait ? xrdy ? xbe[3:0] /xa[5:2] operate as address signals xa[5:2] during expansion bus asynchronous peripheral accesses. ? xwe /xwait operates as the write-enable signal xwe during expansion bus asynchronous peripheral accesses. xrdy operates as active-high ready input during expansion bus asynchronous peripheral accesses. figure 37. expansion bus asynchronous peripheral write timing (xrdy used)
sprs086k ? january 1999 ? revised april 2003 72 post office box 1443 ? houston, texas 77251 ? 1443 expansion bus synchronous host-port timing timing requirements with external device as bus master (see figure 38 and figure 39) rev. 2 rev. 3 no. -250 -300 -250 -300 unit min max min max 1 t su(xcsv-xckih) setup time, xcs valid before xclkin high 3.5 3.5 ns 2 t h(xckih-xcs) hold time, xcs valid after xclkin high 2.8 2.8 ns 3 t su(xas-xckih) setup time, xas valid before xclkin high 3.5 3.5 ns 4 t h(xckih-xas) hold time, xas valid after xclkin high 2.8 2.8 ns 5 t su(xctl-xckih) setup time, xcntl valid before xclkin high 3.5 3.5 ns 6 t h(xckih-xctl) hold time, xcntl valid after xclkin high 2.8 2.8 ns 7 t su(xwr-xckih) setup time, xw/r valid before xclkin high ? 3.5 3.5 ns 8 t h(xckih-xwr) hold time, xw/r valid after xclkin high ? 2.8 2.8 ns 9 t su(xbltv-xckih) setup time, xblast valid before xclkin high ? 3.5 3.5 ns 10 t h(xckih-xbltv) hold time, xblast valid after xclkin high ? 2.8 2.8 ns 16 t su(xbev-xckih) setup time, xbe[3:0] /xa[5:2] valid before xclkin high 3.5 3.5 ns 17 t h(xckih-xbev) hold time, xbe[3:0] /xa[5:2] valid after xclkin high 2.8 2.8 ns 18 t su(xd-xckih) setup time, xdx valid before xclkin high 3.5 3.5 ns 19 t h(xckih-xd) hold time, xdx valid after xclkin high 2.8 2.8 ns ? xw/r input/output polarity selected at boot. ? xblast input polarity selected at boot xbe[3:0] /xa[5:2] operate as byte-enables xbe[3:0] during host-port accesses. switching characteristics over recommended operating conditions with external device as bus master ? (see figure 38 and figure 39) rev. 2 rev. 3 no. parameter -250 -300 -250 -300 unit min max min max 11 t d(xckih-xdlz) delay time, xclkin high to xdx low impedance 0 0 ns 12 t d(xckih-xdv) delay time, xclkin high to xdx valid 16.5 4p ? 0.5 ns 13 t d(xckih-xdiv) delay time, xclkin high to xdx invalid 5 3 ns 14 t d(xckih-xdhz) delay time, xclkin high to xdx high impedance 4p 4p ns 15 t d(xckih-xry) delay time, xclkin high to xrdy invalid # 5 16.5 3 4p ? 0.5 ns 20 t d(xckih-xrylz) delay time, xclkin high to xrdy low impedance 5 16.5 3 4p ? 0.5 ns 21 t d(xckih-xryhz) delay time, xclkin high to xrdy high impedance # 2p + 5 3p + 16.5 2p + 3 7p ? 0.5 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. # xrdy operates as active-low ready input/output during host-port accesses.
sprs086k ? january 1999 ? revised april 2003 73 post office box 1443 ? houston, texas 77251 ? 1443 expansion bus synchronous host-port timing (continued) d1 d2 d3 d4 15 13 12 11 10 9 10 9 8 7 8 7 6 5 4 3 2 1 xclkin xcs xas xcntl xw/r ? xw/r ? xbe[3:0] /xa[5:2] ? xblast xblast xd[31:0] xrdy ? 15 14 20 21 ? xw/r input/output polarity selected at boot ? xbe[3:0] /xa[5:2] operate as byte-enables xbe[3:0] during host-port accesses. xblast input polarity selected at boot ? xrdy operates as active-low ready input/output during host-port accesses. figure 38. external host as bus master ? read
sprs086k ? january 1999 ? revised april 2003 74 post office box 1443 ? houston, texas 77251 ? 1443 expansion bus synchronous host-port timing (continued) xbe1 xbe2 xbe3 xbe4 d1 d2 d3 d4 19 18 10 9 10 9 17 16 6 5 4 3 2 1 xclkin xcs xas xcntl xw/r ? xw/r ? xblast xblast xd[31:0] 8 7 8 7 xbe[3:0] /xa[5:2] ? 15 xrdy ? 15 20 21 ? xw/r input/output polarity selected at boot ? xbe[3:0] /xa[5:2] operate as byte-enables xbe[3:0] during host-port accesses. xblast input polarity selected at boot ? xrdy operates as active-low ready input/output during host-port accesses. figure 39. external host as bus master ? write
sprs086k ? january 1999 ? revised april 2003 75 post office box 1443 ? houston, texas 77251 ? 1443 expansion bus synchronous host-port timing (continued) timing requirements with c62x ? as bus master (see figure 40, figure 41, and figure 42) rev. 2 rev. 3 no. -250 -300 -250 -300 unit min max min max 9 t su(xdv-xckih) setup time, xdx valid before xclkin high 3.5 3.5 ns 10 t h(xckih-xdv) hold time, xdx valid after xclkin high 2.8 2.8 ns 11 t su(xry-xckih) setup time, xrdy valid before xclkin high ? 3.5 3.5 ns 12 t h(xckih-xry) hold time, xrdy valid after xclkin high ? 2.8 2.8 ns 14 t su(xbff-xckih) setup time, xboff valid before xclkin high 3.5 3.5 ns 15 t h(xckih-xbff) hold time, xboff valid after xclkin high 2.8 2.8 ns ? xrdy operates as active-low ready input/output during host-port accesses. switching characteristics over recommended operating conditions with c62x ? as bus master ? (see figure 40, figure 41, and figure 42) rev. 2 rev. 3 no. parameter -250 -300 -250 -300 unit min max min max 1 t d(xckih-xasv) delay time, xclkin high to xas valid 5 16.5 3 4p ? 0.5 ns 2 t d(xckih-xwrv) delay time, xclkin high to xw/r valid 5 16.5 3 4p ? 0.5 ns 3 t d(xckih-xbltv) delay time, xclkin high to xblast valid ? 5 16.5 3 4p ? 0.5 ns 4 t d(xckih-xbev) delay time, xclkin high to xbe[3:0] /xa[5:2] valid # 5 16.5 3 4p ? 0.5 ns 5 t d(xckih-xdlz) delay time, xclkin high to xdx low impedance 0 0 ns 6 t d(xckih-xdv) delay time, xclkin high to xdx valid 16.5 4p ? 0.5 ns 7 t d(xckih-xdiv) delay time, xclkin high to xdx invalid 5 3 ns 8 t d(xckih-xdhz) delay time, xclkin high to xdx high impedance 4p 4p ns 13 t d(xckih-xwtv) delay time, xclkin high to xwe /xwait valid || 5 16.5 3 4p ? 0.5 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. xw/r input/output polarity selected at boot. ? xblast output polarity is always active low. # xbe[3:0] /xa[5:2] operate as byte-enables xbe[3:0] during host-port accesses. || xwe /xwait operates as xwait output signal during host-port accesses.
sprs086k ? january 1999 ? revised april 2003 76 post office box 1443 ? houston, texas 77251 ? 1443 expansion bus synchronous host-port timing (continued) be ad d1 d2 d3 d4 13 13 12 11 10 9 8 7 6 5 4 4 3 3 2 2 1 1 xclkin xas xw/r ? xw/r ? xblast ? xbe[3:0] /xa[5:2] xd[31:0] xrdy xwe /xwait ? ? xw/r input/output polarity selected at boot ? xblast output polarity is always active low. xbe[3:0] /xa[5:2] operate as byte-enables xbe[3:0] during host-port accesses. ? xwe /xwait operates as xwait output signal during host-port accesses. figure 40. c62x ? as bus master ? read addr d1 d2 d3 d4 13 13 12 11 8 7 6 5 4 4 3 3 2 2 1 1 xclkin xas xw/r ? xw/r ? xblast ? xbe[3:0] /xa[5:2] xd[31:0] xrdy xwe /xwait ? ? xw/r input/output polarity selected at boot ? xblast output polarity is always active low. xbe[3:0] /xa[5:2] operate as byte-enables xbe[3:0] during host-port accesses. ? xwe /xwait operates as xwait output signal during host-port accesses. figure 41. c62x ? as bus master ? write
sprs086k ? january 1999 ? revised april 2003 77 post office box 1443 ? houston, texas 77251 ? 1443 expansion bus synchronous host-port timing (continued) addr d1 d2 15 14 12 11 8 7 6 5 4 4 2 2 1 1 xclkin xas xw/r ? xw/r ? xblast ? xd[31:0] xrdy xboff xhold ? xholda ? xhold # xholda # xbe[3:0] /xa[5:2] ? xw/r input/output polarity selected at boot ? xblast output polarity is always active low. xbe[3:0] /xa[5:2] operate as byte-enables xbe[3:0] during host-port accesses. ? internal arbiter enabled # internal arbiter disabled || this diagram illustrates xboff timing. bus arbitration timing is shown in figure 45 and figure 46. figure 42. c62x ? as bus master ? xboff operation ||
sprs086k ? january 1999 ? revised april 2003 78 post office box 1443 ? houston, texas 77251 ? 1443 expansion bus asynchronous host-port timing timing requirements with external device as asynchronous bus master ? (see figure 43 and figure 44) no. -250 -300 unit no . min max unit 1 t w(xcsl) pulse duration, xcs low 4p ns 2 t w(xcsh) pulse duration, xcs high 4p ns 3 t su(xsel-xcsl) setup time, expansion bus select signals ? valid before xcs low 1 ns 4 t h(xcsl-xsel) hold time, expansion bus select signals ? valid after xcs low 3.4 ns 10 t h(xryl-xcsl) hold time, xcs low after xrdy low p + 1.5 ns 11 t su(xbev-xcsh) setup time, xbe[3:0] /xa[5:2] valid before xcs high 1 ns 12 t h(xcsh-xbev) hold time, xbe[3:0] /xa[5:2] valid after xcs high 3 ns 13 t su(xdv-xcsh) setup time, xdx valid before xcs high 1 ns 14 t h(xcsh-xdv) hold time, xdx valid after xcs high 3 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. ? expansion bus select signals include xcntl and xr/w. xbe[3:0] /xa[5:2] operate as byte-enables xbe[3:0] during host-port accesses. switching characteristics over recommended operating conditions with external device as asynchronous bus master ? (see figure 43 and figure 44) no. parameter -250 -300 unit no . parameter min max unit 5 t d(xcsl-xdlz) delay time, xcs low to xdx low impedance 0 ns 6 t d(xcsh-xdiv) delay time, xcs high to xdx invalid 0 12 ns 7 t d(xcsh-xdhz) delay time, xcs high to xdx high impedance 4p ns 8 t d(xryl-xdv) delay time, xrdy low to xdx valid ? 4 1.8 ns 9 t d(xcsh-xryh) delay time, xcs high to xrdy high ? 1 12 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns.
sprs086k ? january 1999 ? revised april 2003 79 post office box 1443 ? houston, texas 77251 ? 1443 expansion bus asynchronous host-port timing (continued) word 9 9 7 6 8 5 7 6 8 5 4 3 4 3 4 3 4 3 4 3 4 3 xcs xcntl xbe[3:0] /xa[5:2] ? xr/w ? xr/w ? xd[31:0] xrdy 10 1 2 1 10 ? xbe[3:0] /xa[5:2] operate as byte-enables xbe[3:0] during host-port accesses. ? xw/r input/output polarity selected at boot figure 43. external device as asynchronous master ? read word 9 9 14 13 14 13 4 3 4 3 4 3 4 3 12 11 12 11 4 3 4 3 10 10 xcs xcntl xbe[3:0] /xa[5:2] ? xr/w ? xr/w ? xd[31:0] xrdy 1 2 1 word ? xbe[3:0] /xa[5:2] operate as byte-enables xbe[3:0] during host-port accesses. ? xw/r input/output polarity selected at boot figure 44. external device as asynchronous master ? write
sprs086k ? january 1999 ? revised april 2003 80 post office box 1443 ? houston, texas 77251 ? 1443 xhold/xholda timing timing requirements for expansion bus arbitration (internal arbiter enabled) ? (see figure 45) no. -250 -300 unit no . min max unit 3 t oh(xhdah-xhdh) output hold time, xhold high after xholda high p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. switching characteristics over recommended operating conditions for expansion bus arbitration (internal arbiter enabled) ?? (see figure 45) no. parameter -250 -300 unit no . parameter min max unit 1 t d(xhdh-xbhz) delay time, xhold high to xbus high impedance 3p ns 2 t d(xbhz-xhdah) delay time, xbus high impedance to xholda high 0 2p ns 4 t d(xhdl-xhdal) delay time, xhold low to xholda low 3p ns 5 t d(xhdal-xblz) delay time, xholda low to xbus low impedance 0 2p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. ? xbus consists of xbe[3:0] /xa[5:2], xas , xw/r, and xblast. all pending xbus transactions are allowed to complete before xholda is asserted. 2 dsp owns bus external requestor dsp owns bus c6203b c6203b 5 1 4 3 xhold (input) xholda (output) owns bus xbus ? ? xbus consists of xbe[3:0] /xa[5:2], xas , xw/r, and xblast. figure 45. expansion bus arbitration ? internal arbiter enabled
sprs086k ? january 1999 ? revised april 2003 81 post office box 1443 ? houston, texas 77251 ? 1443 xhold/xholda timing (continued) switching characteristics over recommended operating conditions for expansion bus arbitration (internal arbiter disabled) ? (see figure 46) no. parameter -250 -300 unit no . parameter min max unit 1 t d(xhdah-xblz) delay time, xholda high to xbus low impedance ? 2p 2p + 10 ns 2 t d(xbhz-xhdl) delay time, xbus high impedance to xhold low ? 0 2p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. ? xbus consists of xbe[3:0] /xa[5:2], xas , xw/r, and xblast. c6203b 1 2 xhold (output) xholda (input) xbus ? ? xbus consists of xbe[3:0] /xa[5:2], xas , xw/r, and xblast. figure 46. expansion bus arbitration ? internal arbiter disabled
sprs086k ? january 1999 ? revised april 2003 82 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing timing requirements for mcbsp ?? (see figure 47) no. -250 -300 unit no . min max unit 2 t c(ckrx) cycle time, clkr/x clkr/x ext 2p ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x ext p ? 1 ? ns 5 t set p time e ternal fsr high before clkr lo clkr int 9 ns 5 t su(frh-ckrl) setup time, external fsr high before clkr low clkr ext 2 ns 6 t hold time e ternal fsr high after clkr lo clkr int 6 ns 6 t h(ckrl-frh) hold time, external fsr high after clkr low clkr ext 3 ns 7 t set p time dr alid before clkr lo clkr int 8 ns 7 t su(drv-ckrl) setup time, dr valid before clkr low clkr ext 0.5 ns 8 t hold time dr valid after clkr low clkr int 3 ns 8 t h(ckrl-drv) hold time, dr valid after clkr low clkr ext 4.5 ns 10 t set p time e ternal fsx high before clkx lo clkx int 9 ns 10 t su(fxh-ckxl) setup time, external fsx high before clkx low clkx ext 2 ns 11 t hold time e ternal fsx high after clkx lo clkx int 6 ns 11 t h(ckxl-fxh) hold time, external fsx high after clkx low clkx ext 4 ns ? clkrp = clkxp = fsrp = fsxp = 0. if the polarity of any of the signals is inverted, then the timing references of that signal a re also inverted. ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. the maximum bit rate for the c6203b device is 100 mbps or cpu/2 (the slower of the two). care must be taken to ensure that the ac timings specified in this data sheet are met. the maximum bit rate for mcbsp-to-mcbsp communications is 100 mhz; therefore, the minimum clkr/x clock cycle is either twice the cpu cycle time (2p), or 10 ns (100 mhz), whichever value is larger. for example, when running p arts at 300 mhz (p = 3.3 ns), use 10 ns as the minimum clkr/x clock cycle (by setting the appropriate clkgdv ratio or external clock source). w hen running parts at 100 mhz (p = 10 ns), use 2p = 20 ns (50 mhz) as the minimum clkr/x clock cycle. the maximum bit rate for mcbsp-to-mcbs p communications applies when the serial port is a master of the clock and frame syncs (with clkr connected to clkx, fsr connecte d to fsx, clkxm = fsxm = 1, and clkrm = fsrm = 0) in data delay 1 or 2 mode (r/xdatdly = 01b or 10b) and the other device the mcbsp communicates to is a slave. ? the minimum clkr/x pulse duration is either (p ? 1) or 4 ns, whichever is larger. for example, when running parts at 300 mhz (p = 3.3 ns), use 4 ns as the minimum clkr/x pulse duration. when running parts at 100 mhz (p = 10 ns), use (p ? 1) = 9 ns as the minimum clkr/x pulse duration.
sprs086k ? january 1999 ? revised april 2003 83 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) switching characteristics over recommended operating conditions for mcbsp ?? (see figure 47) no. parameter -250 -300 unit no . parameter min max unit 1 t d(cksh-ckrxh) delay time, clks high to clkr/x high for internal clkr/x generated from clks input 4 16 ns 2 t c(ckrx) cycle time, clkr/x clkr/x int 2p ? ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x int c ? 1 # c + 1 # ns 4 t d(ckrh-frv) delay time, clkr high to internal fsr valid clkr int ? 2 3 ns 9 t dela time clkx high to internal fsx alid clkx int ? 2 3 ns 9 t d(ckxh-fxv) delay time, clkx high to internal fsx valid clkx ext 2 9 ns 12 t disable time, dx hi g h impedance followin g last data bit from clkx int ? 1 5 ns 12 t dis(ckxh-dxhz) disable time , dx high im edance following last data bit from clkx high clkx ext 2 9 ns 13 t delay time clkx high to dx valid clkx int ? 0.5 4 ns 13 t d(ckxh-dxv) delay time, clkx high to dx valid clkx ext 2 11 ns 14 t dela y time, fsx hi g h to dx valid only applies when in data fsx int ? 1 5 ns 14 t d(fxh-dxv) delay time , fsx high to dx valid only a lies when in data delay 0 (xdatdly = 00b) mode. fsx ext 0 10 ns ? clkrp = clkxp = fsrp = fsxp = 0. if the polarity of any of the signals is inverted, then the timing references of that signal a re also inverted. ? minimum delay times also represent minimum output hold times. p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. ? the maximum bit rate for the c6203b device is 100 mbps or cpu/2 (the slower of the two). care must be taken to ensure that the ac timings specified in this data sheet are met. the maximum bit rate for mcbsp-to-mcbsp communications is 100 mhz; therefore, the minimum clkr/x clock cycle is either twice the cpu cycle time (2p), or 10 ns (100 mhz), whichever value is larger. for example, when running p arts at 300 mhz (p = 3.3 ns), use 10 ns as the minimum clkr/x clock cycle (by setting the appropriate clkgdv ratio or external clock source). w hen running parts at 100 mhz (p = 10 ns), use 2p = 20 ns (50 mhz) as the minimum clkr/x clock cycle. the maximum bit rate for mcbsp-to-mcbs p communications applies when the serial port is a master of the clock and frame syncs (with clkr connected to clkx, fsr connecte d to fsx, clkxm = fsxm = 1, and clkrm = fsrm = 0) in data delay 1 or 2 mode (r/xdatdly = 01b or 10b) and the other device the mcbsp communicates to is a slave. # c = h or l s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero clkgdv should be set appropriately to ensure the mcbsp bit rate does not exceed the 100-mhz limit.
sprs086k ? january 1999 ? revised april 2003 84 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) bit(n-1) (n-2) (n-3) bit 0 bit(n-1) (n-2) (n-3) 14 13 12 11 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 clks clkr fsr (int) fsr (ext) dr clkx fsx (int) fsx (ext) fsx (xdatdly=00b) dx 13 figure 47. mcbsp timings
sprs086k ? january 1999 ? revised april 2003 85 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) timing requirements for fsr when gsync = 1 (see figure 48) no. -250 -300 unit no . min max unit 1 t su(frh-cksh) setup time, fsr high before clks high 4 ns 2 t h(cksh-frh) hold time, fsr high after clks high 4 ns 2 1 clks fsr external clkr/x (no need to resync) clkr/x (needs resync) figure 48. fsr timing when gsync = 1
sprs086k ? january 1999 ? revised april 2003 86 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 ?? (see figure 49) no -250 -300 unit no. master slave unit min max min max 4 t su(drv-ckxl) setup time, dr valid before clkx low 12 2 ? 3p ns 5 t h(ckxl-drv) hold time, dr valid after clkx low 4 5 + 6p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 ?? (see figure 49) no parameter -250 -300 unit no. parameter master slave unit min max min max 1 t h(ckxl-fxl) hold time, fsx low after clkx low ? t ? 2 t + 3 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high # l ? 2 l + 3 ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid ? 3 4 3p + 4 5p + 17 ns 6 t dis(ckxl-dxhz) disable time, dx high impedance following last data bit from clkx low l ? 2 l + 3 ns 7 t dis(fxh-dxhz) disable time, dx high impedance following last data bit from fsx high p + 3 3p + 17 ns 8 t d(fxl-dxv) delay time, fsx low to dx valid 2p + 2 4p + 17 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero clkgdv should be set appropriately to ensure the mcbsp bit rate does not exceed the 100-mhz limit. ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx).
sprs086k ? january 1999 ? revised april 2003 87 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 clkx fsx dx dr figure 49. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 0
sprs086k ? january 1999 ? revised april 2003 88 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 ?? (see figure 50) no -250 -300 unit no. master slave unit min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 12 2 ? 3p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 6p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 ?? (see figure 50) no parameter -250 -300 unit no. parameter master slave unit min max min max 1 t h(ckxl-fxl) hold time, fsx low after clkx low ? l ? 2 l + 3 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high # t ? 2 t + 3 ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid ? 2 4 3p + 4 5p + 17 ns 6 t dis(ckxl-dxhz) disable time, dx high impedance following last data bit from clkx low ? 2 4 3p + 3 5p + 17 ns 7 t d(fxl-dxv) delay time, fsx low to dx valid h ? 2 h + 4 2p + 2 4p + 17 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero the maximum transfer rate for spi mode is limited to the above ac timing constraints. ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx).
sprs086k ? january 1999 ? revised april 2003 89 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 4 3 7 6 2 1 clkx fsx dx dr 5 figure 50. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 0
sprs086k ? january 1999 ? revised april 2003 90 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 ?? (see figure 51) no -250 -300 unit no. master slave unit min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 12 2 ? 3p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 6p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 ?? (see figure 51) no parameter -250 -300 unit no. parameter master slave unit min max min max 1 t h(ckxh-fxl) hold time, fsx low after clkx high ? t ? 2 t + 3 ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low # h ? 2 h + 3 ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid ? 3 4 3p + 4 5p + 17 ns 6 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit from clkx high h ? 2 h + 3 ns 7 t dis(fxh-dxhz) disable time, dx high impedance following last data bit from fsx high p + 3 3p + 17 ns 8 t d(fxl-dxv) delay time, fsx low to dx valid 2p + 2 4p + 17 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero the maximum transfer rate for spi mode is limited to the above ac timing constraints. ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx).
sprs086k ? january 1999 ? revised april 2003 91 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 clkx fsx dx dr figure 51. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 1
sprs086k ? january 1999 ? revised april 2003 92 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 ?? (see figure 52) no -250 -300 unit no. master slave unit min max min max 4 t su(drv-ckxl) setup time, dr valid before clkx low 12 2 ? 3p ns 5 t h(ckxl-drv) hold time, dr valid after clkx low 4 5 + 6p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 ?? (see figure 52) no parameter -250 -300 unit no. parameter master slave unit min max min max 1 t h(ckxh-fxl) hold time, fsx low after clkx high ? h ? 2 h + 3 ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low # t ? 2 t + 2 ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid ? 3 4 3p + 4 5p + 17 ns 6 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit from clkx high ? 2 4 3p + 3 5p + 17 ns 7 t d(fxl-dxv) delay time, fsx low to dx valid l ? 2 l + 5 2p + 2 4p + 17 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero clkgdv should be set appropriately to ensure the mcbsp bit rate does not exceed the 100-mhz limit. ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx).
sprs086k ? january 1999 ? revised april 2003 93 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 7 6 2 1 clkx fsx dx dr figure 52. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 1
sprs086k ? january 1999 ? revised april 2003 94 post office box 1443 ? houston, texas 77251 ? 1443 dmac, timer, power-down timing switching characteristics over recommended operating conditions for dmac outputs ? (see figure 53) no. parameter -250 -300 unit no . parameter min max unit 1 t w(dmach) pulse duration, dmac high 2p ? 3 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. dmac[3:0] 1 figure 53. dmac timing timing requirements for timer inputs ? (see figure 54) no. -250 -300 unit no . min max unit 1 t w(tinph) pulse duration, tinp high 2p ns 2 t w(tinpl) pulse duration, tinp low 2p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. switching characteristics over recommended operating conditions for timer outputs ? (see figure 54) no. parameter -250 -300 unit no . parameter min max unit 3 t w(touth) pulse duration, tout high 2p ? 3 ns 4 t w(toutl) pulse duration, tout low 2p ? 3 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. tinpx toutx 4 3 2 1 figure 54. timer timing
sprs086k ? january 1999 ? revised april 2003 95 post office box 1443 ? houston, texas 77251 ? 1443 dmac, timer, power-down timing (continued) switching characteristics over recommended operating conditions for power-down outputs ? (see figure 55) no. parameter -250 -300 unit no . parameter min max unit 1 t w(pdh) pulse duration, pd high 2p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 300 mhz, use p = 3.3 ns. pd 1 figure 55. power-down timing
sprs086k ? january 1999 ? revised april 2003 96 post office box 1443 ? houston, texas 77251 ? 1443 jtag test-port timing timing requirements for jtag test port (see figure 56) no. -250 -300 unit no . min max unit 1 t c(tck) cycle time, tck 35 ns 3 t su(tdiv-tckh) setup time, tdi/tms/trst valid before tck high 11 ns 4 t h(tckh-tdiv) hold time, tdi/tms/trst valid after tck high 9 ns switching characteristics over recommended operating conditions for jtag test port (see figure 56) no. parameter -250 -300 unit no . parameter min max unit 2 t d(tckl-tdov) delay time, tck low to tdo valid ? 4.5 13.5 ns tck tdo tdi/tms/trst 1 2 3 4 2 figure 56. jtag test-port timing
sprs086k ? january 1999 ? revised april 2003 97 post office box 1443 ? houston, texas 77251 ? 1443 mechanical data gnz (s ? pbga ? n352) plastic ball grid array 4202595-2/e 12/02 2,80 max 0,60 0,40 27,20 26,80 sq 24,80 25,20 sq seating plane a 2 1 0,50 25,00 typ 0,50 0,70 b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 0,50 nom m 0,10 1,00 0,15 1,00 0,50 bottom view a1 corner notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. flip chip application only. d. substrate color may vary. thermal resistance characteristics (s-pbga package) no c/w air flow m/s ? 1 r jc junction-to-case 6.35 n/a 2 r ja junction-to-free air 20.0 0.00 3 r ja junction-to-free air 17.0 0.50 4 r ja junction-to-free air 16.3 1.00 5 r ja junction-to-free air 15.2 2.00 ? m/s = meters per second
sprs086k ? january 1999 ? revised april 2003 98 post office box 1443 ? houston, texas 77251 ? 1443 mechanical data gls (s-pbga-n384) plastic ball grid array 0,40 0,80 0,12 0,80 m 0,10 4188959-3/e 11/01 1,00 nom seating plane 0,55 0,45 a 1 0,40 16,80 typ 0,35 0,45 17,90 18,10 sq 2 b 2,80 max heat slug 3579111315171921 4 6 8 10 12 14 16 18 20 22 c e g j l n r u w aa d f h k m p t v y ab bottom view a1 corner notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. thermally enhanced plastic package with heat slug (hsl) d. flip chip application only thermal resistance characteristics (s-pbga package) no c/w air flow m/s ? 1 r jc junction-to-case 0.85 n/a 2 r ja junction-to-free air 21.6 0.0 3 r ja junction-to-free air 18.0 0.5 4 r ja junction-to-free air 15.5 1.0 5 r ja junction-to-free air 12.8 2.0 ? m/s = meters per second
sprs086k ? january 1999 ? revised april 2003 99 post office box 1443 ? houston, texas 77251 ? 1443 mechanical data gny (s-pbga-n384) plastic ball grid array m ? 0,10 0,80 0,12 0,80 4201137/c 11/01 seating plane 0,55 0,45 a 1 0,40 16,80 typ 0,35 0,45 17,90 18,10 sq 2 b 2,35 max 3 5 7 9 11 13 15 17 19 21 4 6 8 10 12 14 16 18 20 22 c e g j l n r u w aa d f h k m p t v y ab 0,40 bottom view a1 corner notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. flip chip application only d. substrate color may vary thermal resistance characteristics (s-pbga package) no c6203b air flow m/s ? no c6203b ( c/w) air flow m/s ? 1 r jc junction-to-case 6.27 n/a 2 r ja junction-to-free air 17.6 0.0 3 r ja junction-to-free air 13.9 0.5 4 r ja junction-to-free air 13.1 1.0 5 r ja junction-to-free air 11.9 2.0 ? m/s = meters per second
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