1 ? fn7281.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003, 2006. all rights reserved. all other trademarks mentioned are the property of their respective owners. el7182 2-phase, high speed ccd driver the el7182 is extremely well suited for driving ccd's, especially where high contrast imaging is desirable. the 16v supply rating is attractive for higher voltage ccd applications, as in color fax machines. the input is ttl and 3v compatible. the low quiescent current requirement is advantageous in portable/ba ttery powered systems. the el7182 is available in 8 ld pdip and 8 ld soic packages. pinout el7182 (8 ld pdip, soic) top view features ? 3v and 5v input compatible ? clocking speeds up to 10mhz ? reduced clock skew ? 20ns switching/delay time ? 2a peak drive ? low quiescent current ? wide operating voltage: 4.5v?16v ? pb-free plus anneal available (rohs compliant) applications ? ccd drivers requiring high-contrast imaging ? differential line drivers ? push-pull circuits manufactured under u.s. patent nos. 5,334,883, #5,341,047 ordering information part number part marking temp. range (c) package pkg. dwg. # el7182cn el7182cn -40 to +85 8 ld pdip mdp0031 el7182cs 7182cs -40 to +85 8 ld soic mdp0027 el7182csz (note) 7182csz -40 to +85 8 ld soic (pb-free) mdp0027 el7182csz-t7 (note) 7182csz 8 ld soic (7? tape and reel) (pb-free) el7182csz-t13 (note) 7182csz 8 ld soic (7? tape and reel) (pb-free) note: intersil pb-free plus anneal pr oducts employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet june 15, 2006
2 fn7281.1 june 15, 2006 absolute maxi mum ratings (t a = 25c) supply (v+ to gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5v input pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v above v+ combined peak output current. . . . . . . . . . . . . . . . . . . . . . . . . . .4a storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . 125c power dissipation soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mw pdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mw caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications t a = 25c, v = 15v unless otherwise specified parameter description test conditions min typ max units input v ih logic ?1? input voltage 2.4 v i ih logic ?1? input current @v+ 0.1 10 a v il logic ?0? input voltage 0.8 v i il logic ?0? input current @0v 0.1 10 a v hvs input hysteresis 0.3 v output r oh pull-up resistance i out = -100ma 3 6 ? r ol pull-down resistance i out = +100ma 4 6 ? i pk peak output current source 2 a sink 2 a i dc continuous output current source/sink 100 ma power supply i s power supply current input high 2.5 5 ma v s operating voltage 4.5 16 v ac electrical specifications t a = 25c, v = 15v unless otherwise specified parameter description test conditions min typ max units switching characteristics t r rise time c l = 500pf 7.5 ns c l = 1000pf 10 20 ns t f fall time c l = 500pf 10 ns c l = 1000pf 13 20 ns t d-on turn-on delay time 18 25 ns t d-off turn-off delay time 20 25 ns el7182
3 fn7281.1 june 15, 2006 timing table standard test configuration simplified schematic el7182
4 fn7281.1 june 15, 2006 typical performance curves max power/derating curves switch threshold vs supply voltage input current vs voltage peak drive vs supply voltage quiescent supply current ?on? re sistance vs supply voltage case: input level curve gnd b v+ d average supply current vs voltage and frequency average supply current vs capacitive load el7182
5 fn7281.1 june 15, 2006 typical performance curves (continued) rise/fall time vs load rise/fall time vs supply voltage rise/fall time vs temperature propagation delay vs supply voltage delay time vs temperature el7182
6 fn7281.1 june 15, 2006 el7182 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) tolerance notes a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. l 2/01 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
7 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7281.1 june 15, 2006 el7182 plastic dual-in-line packages (pdip) notes: 1. plastic or metal protrusions of 0.010? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions e and ea are measured with the l eads constrained perpendicular to the seating plane. 4. dimension eb is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. mdp0031 plastic dual-in-line package symbol pdip8 pdip14 pdip16 pdip18 pdip20 tolerance notes a 0.210 0.210 0.210 0.210 0.210 max a1 0.015 0.015 0.015 0.015 0.015 min a2 0.130 0.130 0.130 0.130 0.130 0.005 b 0.018 0.018 0.018 0.018 0.018 0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 d 0.375 0.750 0.750 0.890 1.020 0.010 1 e 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 e1 0.250 0.250 0.250 0.250 0.250 0.005 2 e 0.100 0.100 0.100 0.100 0.100 basic ea 0.300 0.300 0.300 0.300 0.300 basic eb 0.345 0.345 0.345 0.345 0.345 0.025 l 0.125 0.125 0.125 0.125 0.125 0.010 n 8 14 16 18 20 reference rev. b 2/99 d l a e b a1 note 5 a2 seating plane l n pin #1 index e1 12 n/2 b2 e eb ea c
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