View DEI3283-SAB-G_6842129.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

?2010 device engineering inc page 1 of 11 ds-mw-03283-01 rev k 08/10/10 features ? two separate analog receiver channels ? converts arinc 429 levels to serial data ? arinc 429 inputs withstand +/-200v ? ttl inputs to test complete analog/digital rx function ? ttl and cmos compatible outputs ? low power dissipation ? internal band gap voltage reference ? mil-std-883b burn-in screening available ? package options: 20 lead ceramic dip, 20 terminal ceramic lcc, and 20 lead soic ? direct replacement for fairchild/raytheon rm3283 and rm3183 and holt hi-8482 function diagram 385 east alamo drive chandler, az 85225 phone: (480) 303-0822 fax: (480) 303-0824 e-mail: admin@deiaz.com dei3283 dual arinc 429 line receiver d evice e ngineering incorporated
?2010 device engineering inc page 2 of 11 ds-mw-03283-01 rev k 08/10/10 general description the dei3283 consists of two analog arinc 429 receivers which take differentially encoded arinc level data and convert it to serial ttl level data. the dei3283 provides two complete analog ar inc receivers with no external components required. input level shifting thin film resistors and bipolar technology allow arinc input voltage transients up to 200v without damage to the dei3283. each channel is identical, featur ing symmetrical propagation delays for better high speed performance. input common mode rejection is excellent and threshold voltage is stable , independent of supply voltage. data outputs are ttl and cmos compatible. two ttl compatible test inputs used to test the arinc ch annels are available. they can be used to override the arin c input data and set the channel outputs to a known state. the dei arinc line driver family ic?s are companion chips to the dei32 83 line receiver. together they provide the analog functions needed for the arinc 429 interface. functional description the dei3283 contains two discrete arinc 429 receiver channels. each channel contains three main sections: a resistor input network, a window comparator, and a logic output buffer stage. the first stage provides over voltage protection and biases the signal using voltage dividers and current sources, providing excellent input common mode rejection. the test inputs are provided to se t the outputs to a predetermined state for built-in channel test capability. if the test inputs are not used, they should be grounded . the window comparator section detects data from the resistor input network. a logic 1 corresponds to arinc ?high? state (outa) and a logic 0, to arinc ?low? state (outb). an arinc ?null? state at the inputs forces both outputs to logic 0. threshold and hysteresis voltages are generated by a band gap voltage reference to maintain stable switching characteristics over tempera ture and power supply variations. the output stage generates a ttl compatible logic output capable of driving 3ma of load. pin assignments pin name description 1 -vs supply voltage (-15v) 2 test a logic input, see functional characteristics. 3 cap2b a429 input, ch 2, b capacitor node 4 in2b a429 input, ch 2, b input 5 out2b logic output, ch 2, b?s output 6 in2a a429 input, ch 2, a input 7 cap2a a429 input, ch 2, a capacitor node
?2010 device engineering inc page 3 of 11 ds-mw-03283-01 rev k 08/10/10 pin name description 8 out2a logic output, ch 2, a?s output 9 +vl supply voltage (+5v) 10 nc 11 +vs supply voltage (+15v) 12 out1b logic output, ch 1, b?s output 13 nc 14 gnd supply return 15 out1a logic output, ch 1, a?s output 16 in1b a429 input, ch 1, b input 17 cap1b a429 input, ch 1, b capacitor node 18 in1a a429 input, ch 1, a input 19 cap1a a429 input, ch 1, a capacitor node 20 testb logic input, see functional characteristics. absolute maximum ratings parameter min. max. units supply voltage: +vs to -vs +vs to gnd -vs to gnd -20 +36 +20 v v v +vl voltage +7 v logic input voltage -0.3 +vl + 0.3 v arinc 429 input voltage -200 +200 v storage -65 +150 c temperature range operating -55 +125 c junction temperature ceramic plastic -55 -55 +175 +145 c lead soldering temperature (60 sec., dip, lcc) +300 c peak body temperature, j-std-020 (soic) non-g package -g package +240 +260 c recommended operating conditions symbol parameters min. max. units +v s positive supply voltage 13.5 16.5 v -v s negative supply voltage -16.5 -13.5 v +vl +vl supply voltage 4.5 5.5 v t op case temperature ceramic plastic: -sa -se -55 -40 -55 +125 +125 +85 c c c
?2010 device engineering inc page 4 of 11 ds-mw-03283-01 rev k 08/10/10 electrical characteristics symbol parameter conditions (1,2) min. max. units power supplies icc +vs (+15v) supply current supply = +/- 16.5v, vl = 5.0v, test inputs = 0v test inputs = 5v 3.5 3.5 6.0 6.0 ma iee -vs (-15v) supply current supply = +/- 16.5v, vl = 5.0v, test inputs = 0v test inputs = 5v 7.5 11.0 12.0 18.5 ma il +vl (+5v) supply current supply = +/- 16.5v, vl = 5.0v, test inputs = 0v test inputs = 5v 4.5 10.8 9.0 17.6 ma a429 inputs vhh null to 1 transition, v(ina) ? v(inb) supply = +/-15.0v, vl = 5.00v test inputs = 0v vinb = -2.50v 5.70 6.30 v vhl 1 to null transition, v(ina) ? v(inb) supply = +/-15.0v, vl = 5.00v test inputs = 0v vinb = -2.50v 4.50 5.50 v vhhys 1 to null transition hysteresis vhh-vhl 0.8 1.2 v vll null to 0 transition, v(ina) ? v(inb) supply = +/-15.0v, vl = 5.00v test inputs = 0v vinb = +2.50v -6.30 -5.70 v vhl 0 to null transition, v(ina) ? v(inb) supply = +/-15.0v, vl = 5.00v test inputs = 0v vinb = +2.50v -5.50 -4.50 v vlhys 0 to null transition hysteresis vll-vlh -1.2 -0.8 v vcm input common mode voltage range -13 +13 v ringnd input resistance, input to gnd unpowered, ina to gnd, inb to gnd 20 30 k ? rin input resistor, ina to capa, inb to capb unpowered ina to capa, inb to capb 8.5 11.5 k ? cin input capacitance, ina to gnd, inb to gnd (3) 10 pf test logic inputs vih logic 1 input voltage functional test 2.0 v vil logic 0 input voltage functional test 0.9 v iih logic 1 input current vih = 5v supply = +/-15.0v, vl = 5.00v 0 300 a iil logic 0 input current vil = 0.8v supply = +/-15.0v, vl = 5.00v 0 40 a logic outputs voh logic 1 output voltage vsupply = +/-15.0v, vl = 5.0v ioh = -100ua (room temp) ioh = -2.8ma 4.0 3.5 v v vol logic 0 output voltage vsupply = +/-15.0v, vl = 5.0v iol = 100ua (room temp) iol = 2.0ma 0.1 0.8 v v
?2010 device engineering inc page 5 of 11 ds-mw-03283-01 rev k 08/10/10 symbol parameter conditions (1,2) min. max. units tr output rise time cl = 60 pf (4) 10 70 ns tf output fall time cl = 60 pf (4) 10 70 ns tplh prop delay, a429 to lh output a429 in = 0 to 10v (4) capa, capb, out cl = 60 pf 1500 ns tphl prop delay, a429 to hl output a429 in = 0 to 10v (4) capa, capb, out cl = 60 pf 1500 ns dtp matching of tplh and tphl |tplh-tphl| (4) 500 ns tptlh prop delay, testa/b to lh output cl = 60 pf, vin = 0.8v/2.0v (4) 400 600 ns tpthl prop delay, testa/b to hl output cl = 60 pf, vin = 0.8v/2.0v (4) 800 1300 ns notes: 1. unless otherwise noted, currents flowi ng in to dut are positive, currents flow ing out of dut are negative, voltages are referenced to ground. 2. unless otherwise noted, tcase = -55c to +125c for -xmx, - 40c to +125c for -xax, and -55c to +85c for ?xex versions; +vs = +13.5 to 16.5v, -vs = -13.5 to ?16.5v, +vl = 4.5 to 5.5v. 3. guaranteed by design. not production tested. 4. sample tested. ac test waveforms
?2010 device engineering inc page 6 of 11 ds-mw-03283-01 rev k 08/10/10 functional characteristics test inputs outputs arinc inputs v(a) ? v(b) test a test b out_a out_b output state null 0 0 0 0 null low 0 0 0 1 low high 0 0 1 0 high x 0 1 0 1 low x 1 0 1 0 high x 1 1 0 0 null v[ina ? inb] v[out_a] v[out_b] parameter characteristics (100kbs) min max units time y 9.75 10.25 us time x 4.87 5.13 us pulse rise time 0.5 2 us pulse fall time 0.5 2 us vhigh +7.25 11 v diff vhh +6.5 v diff vhl +2.5 v diff vnull -0.5 +0.5 v diff vll -2.5 v diff vlh -6.5 v diff vlow -11 -7.25 v diff
?2010 device engineering inc page 7 of 11 ds-mw-03283-01 rev k 08/10/10 applications discussion the standard connections for the dei3283 are shown in the figure below. dual 15vdc supplies are recommended for the +vs/-vs supplies. decoupling of all supplies should be done near the ic to avoid propagation of noise spikes due to switching transient s. the ground connection should be sturdy and isolated from large switching currents to provide as quiet a ground reference as possibl e. the noise filter capacitors are optional and are added to provide extr a noise immunity by limiting bandwidth of the input signal be fore it reaches the window comparator stage. two capacitors are used for each channel and they must be the same value. the suggested capacitor value for a 100 khz operation is 39 pf. for lower data rates, larger values of capacitance may be used to yield bette r noise performance. to get optimum performance, the following equation can be used to calculate capacitor value for a specific data ra te: where c filter is the capacitor value in pf, and f o is the input frequency (10 khz f o 150 khz). applications arinc receiver standard connections
?2010 device engineering inc page 8 of 11 ds-mw-03283-01 rev k 08/10/10 process flow process step plastic standard ceramic standard plastic burn-in ceramic burn-in thermal cycle mil-std-883b m1010.4 condition b no 10 cycles no 10 cycles constant acceleration mil-std-883b m2001, method d. n/a yes n/a yes gross & fine leak mil-std-883b m1014.10 n/a yes n/a yes pre-burn-in electrical test n/a n/a yes yes burn in mil-std-883b m1015 condition a n/a n/a 160hrs @ +125 c 160hrs @ +125 c final electrical test, room temperature 100% 100% 100% 100% final electrical test, high temperature 100% @ +85 or +125c 100% @ +125c 100% @ +85 or +125c 100% @ +125c final electrical test, low temperature 0.65% aql @ -55 or -40c 0.65% aql @ -55c 0.65% aql @ -55 or -40c 0.65% aql @ -55c burn-in circuit
?2010 device engineering inc page 9 of 11 ds-mw-03283-01 rev k 08/10/10 package characteristics package characteristics package type 20l ceramic lcc 20l cerdip 20l cerdip green 20l soic 20l soic green reference (see ordering info) 20 clcc 20 cerdip 20 cerdip g 20 soic 20 soic g jedec mo reference mo-047 ms-030-a- ae ms-030-a- ae ms-013-ae ms-013-ae thermal resistance: ja (4 layer pcb) jc 85 c/w 30 c/w 70 c/w 28 c/w 70 c/w 28 c/w 85 c/w 30 c/w 85 c/w 30 c/w jedec moisture sensitivity level (msl) hermetic hermetic hermetic msl 1 / 250 c msl 1 / 250 c lead finish material / jedec pb-free code snpb solder dip na snpb solder dip na snagcu solder dip e1 snpb plate na matte sn e3 pb-free designation not pb-free not pb-free pb free not pb-free rohs compliant 20l soic ( ? g and non - g ) package
?2010 device engineering inc page 10 of 11 ds-mw-03283-01 rev k 08/10/10 20l cerdip (-g and non-g) package 20l ceramic lcc package
?2010 device engineering inc page 11 of 11 ds-mw-03283-01 rev k 08/10/10 ordering information part number marking package operating temperature range burn in dei3283-cmb dei3283-cmb 20 cerdip -55 c to +125 c y dei3283-cmb-g dei3283-cmb e1 20 cerdip g -55 c to +125 c y dei3283-cms dei3283-cms 20 cerdip -55 c to +125 c n dei3283-cms-g dei3283-cms e1 20 cerdip g -55 c to +125 c n dei3283-emb dei3283-emb 20 clcc -55 c to +125 c y dei3283-ems dei3283-ems 20 clcc -55 c to +125 c n dei3283-sab dei3283-sab 20 soic -40 c to +125 c y DEI3283-SAB-G dei3283-sab e3 20 soic g -40 c to +125 c y dei3283-sas dei3283-sas 20 soic -40 c to +125 c n dei3283-sas-g dei3283-sas e3 20 soic g -40 c to +125 c n dei3283-seb dei3283-seb 20 soic -55 c to +85 c y dei3283-seb-g dei3283-seb e3 20 soic g -55 c to +85 c y dei3283-ses dei3283-ses 20 soic -55 c to +85 c n dei3283-ses-g dei3283-ses e3 20 soic g -55 c to +85 c n dei3283-smb dei3283-smb 20 soic -55 c to +125 c y dei3283-smb-g dei3283-smb e3 20 soic g -55 c to +125 c y dei3283-sms dei3283-sms 20 soic -55 c to +125 c n dei3283-sms-g dei3283-sms e3 20 soic g -55 c to +125 c n notes: 1. all packages marked with lot code and date code. ?e1? or ?e3? after date code denotes pb free category. 2. the ?cmb/-emb/-sab/-seb/-smb parts may be marked as ? cms/-ems/-sas/-ses/-sms with a ?b? stamp to denote burn-in. dei reserves the right to make changes to any products or sp ecifications herein. dei makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose.

▲Up To Search▲

Price & Availability of DEI3283-SAB-G

	To Download DEI3283-SAB-G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .